Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.36 97.48 92.33 97.44 68.75 95.77 98.17 96.58


Total test records in report: 2215
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T2073 /workspace/coverage/default/29.usbdev_streaming_out.4048755854 Jun 10 05:27:17 PM PDT 24 Jun 10 05:29:20 PM PDT 24 4761252977 ps
T2074 /workspace/coverage/default/44.usbdev_rx_crc_err.2872637589 Jun 10 05:28:24 PM PDT 24 Jun 10 05:28:25 PM PDT 24 148689321 ps
T2075 /workspace/coverage/default/29.usbdev_min_length_out_transaction.2402019090 Jun 10 05:27:16 PM PDT 24 Jun 10 05:27:17 PM PDT 24 154358656 ps
T2076 /workspace/coverage/default/10.min_length_in_transaction.2260155459 Jun 10 05:25:16 PM PDT 24 Jun 10 05:25:17 PM PDT 24 155517721 ps
T2077 /workspace/coverage/default/1.usbdev_rx_crc_err.3733475406 Jun 10 05:24:26 PM PDT 24 Jun 10 05:24:28 PM PDT 24 138074443 ps
T2078 /workspace/coverage/default/37.usbdev_rx_crc_err.2272379806 Jun 10 05:27:53 PM PDT 24 Jun 10 05:27:55 PM PDT 24 149778213 ps
T2079 /workspace/coverage/default/1.usbdev_bitstuff_err.1076125370 Jun 10 05:24:15 PM PDT 24 Jun 10 05:24:17 PM PDT 24 150015644 ps
T2080 /workspace/coverage/default/22.usbdev_link_in_err.3467200420 Jun 10 05:26:26 PM PDT 24 Jun 10 05:26:28 PM PDT 24 180671058 ps
T2081 /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1891102371 Jun 10 05:27:23 PM PDT 24 Jun 10 05:27:25 PM PDT 24 169410736 ps
T2082 /workspace/coverage/default/39.usbdev_max_usb_traffic.748113029 Jun 10 05:27:54 PM PDT 24 Jun 10 05:29:23 PM PDT 24 11579060382 ps
T2083 /workspace/coverage/default/25.usbdev_av_buffer.3035015426 Jun 10 05:26:42 PM PDT 24 Jun 10 05:26:43 PM PDT 24 212498371 ps
T2084 /workspace/coverage/default/20.min_length_in_transaction.3054903767 Jun 10 05:26:25 PM PDT 24 Jun 10 05:26:26 PM PDT 24 167200170 ps
T2085 /workspace/coverage/default/2.usbdev_data_toggle_restore.344713591 Jun 10 05:24:20 PM PDT 24 Jun 10 05:24:22 PM PDT 24 885362464 ps
T2086 /workspace/coverage/default/46.usbdev_min_length_out_transaction.2801805034 Jun 10 05:28:36 PM PDT 24 Jun 10 05:28:37 PM PDT 24 153632387 ps
T2087 /workspace/coverage/default/0.usbdev_setup_trans_ignored.2032019936 Jun 10 05:24:11 PM PDT 24 Jun 10 05:24:13 PM PDT 24 153346184 ps
T2088 /workspace/coverage/default/35.usbdev_link_in_err.2592108379 Jun 10 05:27:24 PM PDT 24 Jun 10 05:27:25 PM PDT 24 225733055 ps
T2089 /workspace/coverage/default/48.usbdev_pending_in_trans.1911466058 Jun 10 05:28:48 PM PDT 24 Jun 10 05:28:49 PM PDT 24 159440927 ps
T2090 /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1650942608 Jun 10 05:26:41 PM PDT 24 Jun 10 05:26:42 PM PDT 24 207481542 ps
T2091 /workspace/coverage/default/28.usbdev_disconnected.2829531207 Jun 10 05:27:18 PM PDT 24 Jun 10 05:27:20 PM PDT 24 165170967 ps
T2092 /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1123768938 Jun 10 05:25:18 PM PDT 24 Jun 10 05:25:20 PM PDT 24 224546772 ps
T2093 /workspace/coverage/default/33.usbdev_link_suspend.3174578199 Jun 10 05:27:15 PM PDT 24 Jun 10 05:27:20 PM PDT 24 3339272820 ps
T2094 /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2111258754 Jun 10 05:28:51 PM PDT 24 Jun 10 05:28:52 PM PDT 24 167989240 ps
T2095 /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2662173026 Jun 10 05:26:32 PM PDT 24 Jun 10 05:26:34 PM PDT 24 146492994 ps
T2096 /workspace/coverage/default/43.usbdev_pkt_buffer.680506685 Jun 10 05:28:48 PM PDT 24 Jun 10 05:29:22 PM PDT 24 12545543397 ps
T2097 /workspace/coverage/default/39.usbdev_stall_trans.1376220236 Jun 10 05:27:54 PM PDT 24 Jun 10 05:27:55 PM PDT 24 161649442 ps
T2098 /workspace/coverage/default/28.usbdev_pkt_buffer.2439381419 Jun 10 05:26:52 PM PDT 24 Jun 10 05:27:17 PM PDT 24 10923619833 ps
T2099 /workspace/coverage/default/34.usbdev_max_length_out_transaction.4191112767 Jun 10 05:27:36 PM PDT 24 Jun 10 05:27:37 PM PDT 24 194375544 ps
T2100 /workspace/coverage/default/9.usbdev_phy_pins_sense.381955736 Jun 10 05:25:15 PM PDT 24 Jun 10 05:25:16 PM PDT 24 86417557 ps
T2101 /workspace/coverage/default/32.usbdev_out_stall.3797446526 Jun 10 05:27:29 PM PDT 24 Jun 10 05:27:30 PM PDT 24 228349645 ps
T2102 /workspace/coverage/default/41.usbdev_rx_crc_err.1608360811 Jun 10 05:28:07 PM PDT 24 Jun 10 05:28:09 PM PDT 24 184018617 ps
T2103 /workspace/coverage/default/13.usbdev_stall_trans.1645139309 Jun 10 05:25:30 PM PDT 24 Jun 10 05:25:31 PM PDT 24 163487670 ps
T2104 /workspace/coverage/default/15.usbdev_min_length_out_transaction.326512466 Jun 10 05:25:45 PM PDT 24 Jun 10 05:25:46 PM PDT 24 149149871 ps
T2105 /workspace/coverage/default/24.usbdev_link_suspend.2103952094 Jun 10 05:26:39 PM PDT 24 Jun 10 05:26:43 PM PDT 24 3288731879 ps
T2106 /workspace/coverage/default/19.usbdev_smoke.2204022259 Jun 10 05:25:57 PM PDT 24 Jun 10 05:25:59 PM PDT 24 218450789 ps
T2107 /workspace/coverage/default/25.max_length_in_transaction.449379077 Jun 10 05:26:38 PM PDT 24 Jun 10 05:26:39 PM PDT 24 253641282 ps
T2108 /workspace/coverage/default/47.usbdev_aon_wake_disconnect.804055635 Jun 10 05:29:05 PM PDT 24 Jun 10 05:29:10 PM PDT 24 4083885453 ps
T2109 /workspace/coverage/default/36.usbdev_setup_stage.4093319221 Jun 10 05:27:42 PM PDT 24 Jun 10 05:27:43 PM PDT 24 174342970 ps
T2110 /workspace/coverage/default/38.usbdev_smoke.1214221211 Jun 10 05:27:53 PM PDT 24 Jun 10 05:27:54 PM PDT 24 222959333 ps
T2111 /workspace/coverage/default/43.random_length_in_trans.3535658684 Jun 10 05:28:18 PM PDT 24 Jun 10 05:28:19 PM PDT 24 194688879 ps
T2112 /workspace/coverage/default/22.max_length_in_transaction.3869637522 Jun 10 05:26:19 PM PDT 24 Jun 10 05:26:21 PM PDT 24 243043946 ps
T111 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.693330960 Jun 10 05:08:58 PM PDT 24 Jun 10 05:09:00 PM PDT 24 85008848 ps
T116 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1037259093 Jun 10 05:09:00 PM PDT 24 Jun 10 05:09:01 PM PDT 24 53507081 ps
T105 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4245760237 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:50 PM PDT 24 92439101 ps
T106 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1296347409 Jun 10 05:08:51 PM PDT 24 Jun 10 05:08:54 PM PDT 24 62218391 ps
T107 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1814055546 Jun 10 05:08:59 PM PDT 24 Jun 10 05:09:01 PM PDT 24 103615050 ps
T224 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3441149584 Jun 10 05:08:48 PM PDT 24 Jun 10 05:08:50 PM PDT 24 102300586 ps
T2113 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1106303103 Jun 10 05:08:39 PM PDT 24 Jun 10 05:08:45 PM PDT 24 708309509 ps
T112 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.322595843 Jun 10 05:08:51 PM PDT 24 Jun 10 05:08:53 PM PDT 24 178351657 ps
T113 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.632425808 Jun 10 05:09:03 PM PDT 24 Jun 10 05:09:05 PM PDT 24 105676744 ps
T117 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2735397817 Jun 10 05:09:10 PM PDT 24 Jun 10 05:09:12 PM PDT 24 40490491 ps
T108 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1420850420 Jun 10 05:08:46 PM PDT 24 Jun 10 05:08:49 PM PDT 24 213158920 ps
T109 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2922716154 Jun 10 05:09:00 PM PDT 24 Jun 10 05:09:03 PM PDT 24 440031607 ps
T228 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.480003334 Jun 10 05:08:53 PM PDT 24 Jun 10 05:08:56 PM PDT 24 178725865 ps
T223 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3176636617 Jun 10 05:08:48 PM PDT 24 Jun 10 05:08:51 PM PDT 24 91109853 ps
T118 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2481878813 Jun 10 05:08:49 PM PDT 24 Jun 10 05:08:51 PM PDT 24 112780517 ps
T110 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3275775547 Jun 10 05:08:49 PM PDT 24 Jun 10 05:08:51 PM PDT 24 47263166 ps
T2114 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3232878620 Jun 10 05:08:46 PM PDT 24 Jun 10 05:08:49 PM PDT 24 378360471 ps
T227 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.693066952 Jun 10 05:08:54 PM PDT 24 Jun 10 05:08:55 PM PDT 24 66069684 ps
T266 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.532874668 Jun 10 05:08:54 PM PDT 24 Jun 10 05:08:56 PM PDT 24 161050585 ps
T119 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3070023945 Jun 10 05:08:55 PM PDT 24 Jun 10 05:08:56 PM PDT 24 94263472 ps
T251 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.4152598652 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:49 PM PDT 24 57932518 ps
T120 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3367389582 Jun 10 05:09:03 PM PDT 24 Jun 10 05:09:04 PM PDT 24 103240974 ps
T230 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.70721036 Jun 10 05:08:56 PM PDT 24 Jun 10 05:09:02 PM PDT 24 1022530086 ps
T267 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.672083368 Jun 10 05:08:51 PM PDT 24 Jun 10 05:08:52 PM PDT 24 132072383 ps
T274 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2841707545 Jun 10 05:08:46 PM PDT 24 Jun 10 05:08:47 PM PDT 24 82199598 ps
T243 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.564015076 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:49 PM PDT 24 96916767 ps
T231 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3339841586 Jun 10 05:09:00 PM PDT 24 Jun 10 05:09:02 PM PDT 24 328711329 ps
T2115 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3506708649 Jun 10 05:08:44 PM PDT 24 Jun 10 05:08:45 PM PDT 24 164579614 ps
T244 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1007150493 Jun 10 05:09:00 PM PDT 24 Jun 10 05:09:06 PM PDT 24 869917194 ps
T247 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2199300156 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:51 PM PDT 24 738807863 ps
T237 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1935789103 Jun 10 05:08:55 PM PDT 24 Jun 10 05:08:58 PM PDT 24 93686157 ps
T121 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3287313246 Jun 10 05:09:00 PM PDT 24 Jun 10 05:09:01 PM PDT 24 67751797 ps
T252 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1558598875 Jun 10 05:08:45 PM PDT 24 Jun 10 05:08:54 PM PDT 24 1730632609 ps
T253 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3449453528 Jun 10 05:08:42 PM PDT 24 Jun 10 05:08:44 PM PDT 24 109398345 ps
T273 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2530610594 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:48 PM PDT 24 48933085 ps
T246 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1309844474 Jun 10 05:09:02 PM PDT 24 Jun 10 05:09:06 PM PDT 24 1067995600 ps
T254 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3780765447 Jun 10 05:08:56 PM PDT 24 Jun 10 05:08:57 PM PDT 24 96307277 ps
T255 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1429831747 Jun 10 05:08:48 PM PDT 24 Jun 10 05:08:49 PM PDT 24 55289101 ps
T275 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.748251880 Jun 10 05:08:58 PM PDT 24 Jun 10 05:08:59 PM PDT 24 74488810 ps
T256 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3108760832 Jun 10 05:09:11 PM PDT 24 Jun 10 05:09:13 PM PDT 24 65449339 ps
T257 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2858893549 Jun 10 05:08:45 PM PDT 24 Jun 10 05:08:47 PM PDT 24 176464109 ps
T258 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2612945614 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:49 PM PDT 24 69255146 ps
T245 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1448084619 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:50 PM PDT 24 106790894 ps
T284 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2875665499 Jun 10 05:09:00 PM PDT 24 Jun 10 05:09:01 PM PDT 24 34209170 ps
T234 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.355738277 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:50 PM PDT 24 85900734 ps
T271 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2138971356 Jun 10 05:08:53 PM PDT 24 Jun 10 05:08:55 PM PDT 24 124205515 ps
T241 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2897133825 Jun 10 05:08:54 PM PDT 24 Jun 10 05:08:56 PM PDT 24 228907362 ps
T276 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2284490776 Jun 10 05:09:09 PM PDT 24 Jun 10 05:09:10 PM PDT 24 64314867 ps
T277 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1629576723 Jun 10 05:09:02 PM PDT 24 Jun 10 05:09:03 PM PDT 24 46050569 ps
T235 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1654888936 Jun 10 05:08:50 PM PDT 24 Jun 10 05:08:54 PM PDT 24 324416849 ps
T2116 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1423829481 Jun 10 05:08:46 PM PDT 24 Jun 10 05:08:48 PM PDT 24 45429727 ps
T272 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3587794803 Jun 10 05:08:58 PM PDT 24 Jun 10 05:09:01 PM PDT 24 295501061 ps
T2117 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1639005494 Jun 10 05:08:45 PM PDT 24 Jun 10 05:08:47 PM PDT 24 67004166 ps
T283 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2823795961 Jun 10 05:09:04 PM PDT 24 Jun 10 05:09:06 PM PDT 24 35940945 ps
T278 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3955082020 Jun 10 05:08:45 PM PDT 24 Jun 10 05:08:46 PM PDT 24 46589390 ps
T259 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1352975810 Jun 10 05:08:45 PM PDT 24 Jun 10 05:08:46 PM PDT 24 63501089 ps
T260 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2602000424 Jun 10 05:08:42 PM PDT 24 Jun 10 05:08:50 PM PDT 24 1653224110 ps
T279 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1413702042 Jun 10 05:08:53 PM PDT 24 Jun 10 05:08:55 PM PDT 24 91365384 ps
T2118 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2839770044 Jun 10 05:08:46 PM PDT 24 Jun 10 05:08:47 PM PDT 24 66974821 ps
T2119 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2345879709 Jun 10 05:08:52 PM PDT 24 Jun 10 05:08:55 PM PDT 24 444710740 ps
T2120 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3109013983 Jun 10 05:08:56 PM PDT 24 Jun 10 05:08:58 PM PDT 24 87552810 ps
T280 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1303982248 Jun 10 05:09:09 PM PDT 24 Jun 10 05:09:10 PM PDT 24 71930262 ps
T236 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2752309167 Jun 10 05:08:46 PM PDT 24 Jun 10 05:08:49 PM PDT 24 109470146 ps
T285 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.847603864 Jun 10 05:08:46 PM PDT 24 Jun 10 05:08:47 PM PDT 24 51309910 ps
T2121 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1720388537 Jun 10 05:08:51 PM PDT 24 Jun 10 05:08:52 PM PDT 24 73291716 ps
T2122 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.535251753 Jun 10 05:09:04 PM PDT 24 Jun 10 05:09:06 PM PDT 24 79494449 ps
T288 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4077399518 Jun 10 05:08:44 PM PDT 24 Jun 10 05:08:47 PM PDT 24 314079356 ps
T286 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2849053950 Jun 10 05:08:57 PM PDT 24 Jun 10 05:08:58 PM PDT 24 46318391 ps
T2123 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3190508357 Jun 10 05:08:55 PM PDT 24 Jun 10 05:08:57 PM PDT 24 121231687 ps
T287 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3398384489 Jun 10 05:09:24 PM PDT 24 Jun 10 05:09:26 PM PDT 24 36818226 ps
T239 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3149415915 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:50 PM PDT 24 215745643 ps
T2124 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.321436981 Jun 10 05:09:10 PM PDT 24 Jun 10 05:09:11 PM PDT 24 102122370 ps
T2125 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1563367584 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:49 PM PDT 24 172251512 ps
T2126 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2278979200 Jun 10 05:08:50 PM PDT 24 Jun 10 05:08:52 PM PDT 24 67335195 ps
T2127 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1913624950 Jun 10 05:08:58 PM PDT 24 Jun 10 05:08:59 PM PDT 24 32816341 ps
T289 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2972949903 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:53 PM PDT 24 2169291161 ps
T261 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1643320270 Jun 10 05:08:45 PM PDT 24 Jun 10 05:08:47 PM PDT 24 131618107 ps
T2128 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2005148218 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:51 PM PDT 24 391980758 ps
T2129 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3447889565 Jun 10 05:08:57 PM PDT 24 Jun 10 05:09:00 PM PDT 24 205085607 ps
T2130 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4069572443 Jun 10 05:09:02 PM PDT 24 Jun 10 05:09:03 PM PDT 24 42579687 ps
T262 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3378299666 Jun 10 05:08:46 PM PDT 24 Jun 10 05:08:55 PM PDT 24 1675667376 ps
T2131 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4042392273 Jun 10 05:08:49 PM PDT 24 Jun 10 05:08:51 PM PDT 24 61582183 ps
T2132 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3972864793 Jun 10 05:08:57 PM PDT 24 Jun 10 05:08:58 PM PDT 24 103747374 ps
T2133 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.4073324628 Jun 10 05:08:58 PM PDT 24 Jun 10 05:08:59 PM PDT 24 45240467 ps
T2134 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1816022336 Jun 10 05:08:57 PM PDT 24 Jun 10 05:08:58 PM PDT 24 74172301 ps
T2135 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.955624584 Jun 10 05:08:59 PM PDT 24 Jun 10 05:09:01 PM PDT 24 152694683 ps
T2136 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2364743904 Jun 10 05:09:02 PM PDT 24 Jun 10 05:09:03 PM PDT 24 44204234 ps
T264 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2938396119 Jun 10 05:08:49 PM PDT 24 Jun 10 05:08:51 PM PDT 24 85426552 ps
T2137 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1709829205 Jun 10 05:08:56 PM PDT 24 Jun 10 05:08:59 PM PDT 24 107358036 ps
T240 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1611458585 Jun 10 05:08:56 PM PDT 24 Jun 10 05:08:59 PM PDT 24 116938141 ps
T2138 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3082057925 Jun 10 05:08:58 PM PDT 24 Jun 10 05:08:59 PM PDT 24 83364617 ps
T2139 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.19028549 Jun 10 05:08:50 PM PDT 24 Jun 10 05:08:52 PM PDT 24 199429031 ps
T2140 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3165396164 Jun 10 05:08:44 PM PDT 24 Jun 10 05:08:45 PM PDT 24 65182906 ps
T2141 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.345737387 Jun 10 05:08:54 PM PDT 24 Jun 10 05:08:56 PM PDT 24 94001120 ps
T2142 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.910703194 Jun 10 05:08:51 PM PDT 24 Jun 10 05:08:53 PM PDT 24 134659096 ps
T2143 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2188355155 Jun 10 05:08:56 PM PDT 24 Jun 10 05:08:57 PM PDT 24 37363161 ps
T2144 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.472169366 Jun 10 05:08:49 PM PDT 24 Jun 10 05:08:51 PM PDT 24 75383221 ps
T291 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2016271470 Jun 10 05:08:56 PM PDT 24 Jun 10 05:09:01 PM PDT 24 922263862 ps
T2145 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3588184231 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:51 PM PDT 24 375064967 ps
T2146 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.918195522 Jun 10 05:09:00 PM PDT 24 Jun 10 05:09:01 PM PDT 24 123671147 ps
T2147 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.465349354 Jun 10 05:08:49 PM PDT 24 Jun 10 05:08:52 PM PDT 24 106357102 ps
T2148 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.835652971 Jun 10 05:09:05 PM PDT 24 Jun 10 05:09:06 PM PDT 24 55426822 ps
T2149 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.913985394 Jun 10 05:08:48 PM PDT 24 Jun 10 05:08:49 PM PDT 24 112579182 ps
T2150 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.406206812 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:49 PM PDT 24 154728833 ps
T2151 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.4015753716 Jun 10 05:08:53 PM PDT 24 Jun 10 05:08:56 PM PDT 24 326428801 ps
T2152 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.75434772 Jun 10 05:08:54 PM PDT 24 Jun 10 05:08:56 PM PDT 24 173593836 ps
T2153 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2824790970 Jun 10 05:09:01 PM PDT 24 Jun 10 05:09:02 PM PDT 24 46070034 ps
T2154 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3082225577 Jun 10 05:08:48 PM PDT 24 Jun 10 05:08:50 PM PDT 24 238557291 ps
T2155 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2848260982 Jun 10 05:08:50 PM PDT 24 Jun 10 05:08:55 PM PDT 24 308198521 ps
T2156 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3768115675 Jun 10 05:08:44 PM PDT 24 Jun 10 05:08:45 PM PDT 24 63667866 ps
T263 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4067927878 Jun 10 05:08:49 PM PDT 24 Jun 10 05:08:54 PM PDT 24 677464673 ps
T292 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1948215673 Jun 10 05:08:46 PM PDT 24 Jun 10 05:08:50 PM PDT 24 1007959355 ps
T2157 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2229985404 Jun 10 05:09:03 PM PDT 24 Jun 10 05:09:04 PM PDT 24 49168296 ps
T2158 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1315461281 Jun 10 05:08:59 PM PDT 24 Jun 10 05:09:00 PM PDT 24 56595314 ps
T265 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2709574063 Jun 10 05:08:55 PM PDT 24 Jun 10 05:08:56 PM PDT 24 52486187 ps
T2159 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1068876727 Jun 10 05:09:05 PM PDT 24 Jun 10 05:09:06 PM PDT 24 43681191 ps
T290 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3901609603 Jun 10 05:09:01 PM PDT 24 Jun 10 05:09:05 PM PDT 24 558943734 ps
T2160 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.980903990 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:50 PM PDT 24 178297240 ps
T2161 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3006224891 Jun 10 05:08:58 PM PDT 24 Jun 10 05:08:59 PM PDT 24 28814832 ps
T2162 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.571798308 Jun 10 05:08:52 PM PDT 24 Jun 10 05:08:54 PM PDT 24 175808983 ps
T2163 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1032334977 Jun 10 05:08:44 PM PDT 24 Jun 10 05:08:45 PM PDT 24 39378562 ps
T2164 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3166861313 Jun 10 05:08:56 PM PDT 24 Jun 10 05:08:58 PM PDT 24 167751483 ps
T2165 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1446571311 Jun 10 05:08:46 PM PDT 24 Jun 10 05:08:49 PM PDT 24 118326787 ps
T2166 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.4037213116 Jun 10 05:08:54 PM PDT 24 Jun 10 05:08:56 PM PDT 24 71436987 ps
T2167 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1417484664 Jun 10 05:08:44 PM PDT 24 Jun 10 05:08:46 PM PDT 24 165375248 ps
T2168 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.251226247 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:48 PM PDT 24 65806705 ps
T2169 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1212935487 Jun 10 05:08:55 PM PDT 24 Jun 10 05:08:56 PM PDT 24 113405335 ps
T2170 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3909708800 Jun 10 05:08:49 PM PDT 24 Jun 10 05:08:51 PM PDT 24 91833639 ps
T238 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.276588320 Jun 10 05:08:41 PM PDT 24 Jun 10 05:08:46 PM PDT 24 1091616722 ps
T2171 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.570727504 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:49 PM PDT 24 182498068 ps
T2172 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1235626142 Jun 10 05:09:09 PM PDT 24 Jun 10 05:09:10 PM PDT 24 67875720 ps
T2173 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1735900804 Jun 10 05:08:50 PM PDT 24 Jun 10 05:08:51 PM PDT 24 116107611 ps
T2174 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1869313104 Jun 10 05:09:12 PM PDT 24 Jun 10 05:09:14 PM PDT 24 85240515 ps
T2175 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3581105516 Jun 10 05:09:02 PM PDT 24 Jun 10 05:09:03 PM PDT 24 46863365 ps
T2176 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2519588571 Jun 10 05:08:48 PM PDT 24 Jun 10 05:08:51 PM PDT 24 192785492 ps
T2177 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.19530963 Jun 10 05:08:57 PM PDT 24 Jun 10 05:09:01 PM PDT 24 158384276 ps
T2178 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4138363231 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:51 PM PDT 24 256634297 ps
T2179 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2323644675 Jun 10 05:08:53 PM PDT 24 Jun 10 05:08:55 PM PDT 24 71126554 ps
T2180 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1215191044 Jun 10 05:08:48 PM PDT 24 Jun 10 05:08:53 PM PDT 24 221801986 ps
T2181 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.628226488 Jun 10 05:09:02 PM PDT 24 Jun 10 05:09:04 PM PDT 24 51691584 ps
T2182 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2823892984 Jun 10 05:08:54 PM PDT 24 Jun 10 05:08:55 PM PDT 24 37902415 ps
T2183 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1820448171 Jun 10 05:08:53 PM PDT 24 Jun 10 05:08:56 PM PDT 24 418720092 ps
T2184 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.293115561 Jun 10 05:08:44 PM PDT 24 Jun 10 05:08:46 PM PDT 24 97758922 ps
T2185 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1282287941 Jun 10 05:08:59 PM PDT 24 Jun 10 05:09:02 PM PDT 24 158908236 ps
T2186 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2245030600 Jun 10 05:08:52 PM PDT 24 Jun 10 05:08:54 PM PDT 24 109939949 ps
T2187 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.763544379 Jun 10 05:08:49 PM PDT 24 Jun 10 05:08:50 PM PDT 24 39963946 ps
T2188 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2095635286 Jun 10 05:08:42 PM PDT 24 Jun 10 05:08:44 PM PDT 24 57752011 ps
T2189 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2006102790 Jun 10 05:09:00 PM PDT 24 Jun 10 05:09:03 PM PDT 24 157762394 ps
T2190 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.4247015550 Jun 10 05:08:41 PM PDT 24 Jun 10 05:08:42 PM PDT 24 57680823 ps
T2191 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1374943349 Jun 10 05:09:01 PM PDT 24 Jun 10 05:09:03 PM PDT 24 75485081 ps
T2192 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3433918786 Jun 10 05:09:11 PM PDT 24 Jun 10 05:09:13 PM PDT 24 48003812 ps
T2193 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3086281819 Jun 10 05:08:49 PM PDT 24 Jun 10 05:08:52 PM PDT 24 831069410 ps
T2194 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2875279951 Jun 10 05:08:48 PM PDT 24 Jun 10 05:08:49 PM PDT 24 66302439 ps
T2195 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2352074094 Jun 10 05:08:45 PM PDT 24 Jun 10 05:08:46 PM PDT 24 138466956 ps
T2196 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3150440396 Jun 10 05:09:03 PM PDT 24 Jun 10 05:09:05 PM PDT 24 436591606 ps
T2197 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3433866956 Jun 10 05:08:51 PM PDT 24 Jun 10 05:08:53 PM PDT 24 64386969 ps
T2198 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.901738459 Jun 10 05:08:45 PM PDT 24 Jun 10 05:08:49 PM PDT 24 127832399 ps
T2199 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3804932324 Jun 10 05:09:03 PM PDT 24 Jun 10 05:09:05 PM PDT 24 128255294 ps
T2200 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3483852330 Jun 10 05:08:52 PM PDT 24 Jun 10 05:08:56 PM PDT 24 464705381 ps
T2201 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.762528500 Jun 10 05:08:58 PM PDT 24 Jun 10 05:09:01 PM PDT 24 225679403 ps
T2202 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.558004316 Jun 10 05:08:55 PM PDT 24 Jun 10 05:08:56 PM PDT 24 37580090 ps
T2203 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.4206201301 Jun 10 05:09:01 PM PDT 24 Jun 10 05:09:02 PM PDT 24 53216290 ps
T2204 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1299281990 Jun 10 05:08:46 PM PDT 24 Jun 10 05:08:49 PM PDT 24 358798086 ps
T2205 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1451605436 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:51 PM PDT 24 102040187 ps
T2206 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3038029645 Jun 10 05:09:02 PM PDT 24 Jun 10 05:09:03 PM PDT 24 50269434 ps
T2207 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.778328576 Jun 10 05:08:57 PM PDT 24 Jun 10 05:08:59 PM PDT 24 142094493 ps
T2208 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2395265843 Jun 10 05:08:45 PM PDT 24 Jun 10 05:08:54 PM PDT 24 2256531473 ps
T2209 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2496043135 Jun 10 05:08:48 PM PDT 24 Jun 10 05:08:51 PM PDT 24 181014281 ps
T2210 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3215605891 Jun 10 05:08:54 PM PDT 24 Jun 10 05:08:56 PM PDT 24 44115721 ps
T2211 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3468555824 Jun 10 05:08:51 PM PDT 24 Jun 10 05:08:53 PM PDT 24 83998449 ps
T2212 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3969819433 Jun 10 05:09:08 PM PDT 24 Jun 10 05:09:09 PM PDT 24 39111882 ps
T2213 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3791453688 Jun 10 05:08:47 PM PDT 24 Jun 10 05:08:49 PM PDT 24 214367707 ps
T2214 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1418745898 Jun 10 05:08:42 PM PDT 24 Jun 10 05:08:43 PM PDT 24 95152095 ps
T2215 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1447288254 Jun 10 05:09:07 PM PDT 24 Jun 10 05:09:09 PM PDT 24 118259015 ps
T293 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3206767238 Jun 10 05:08:56 PM PDT 24 Jun 10 05:09:00 PM PDT 24 579347189 ps

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3588415230
Short name T29
Test name
Test status
Simulation time 15790361018 ps
CPU time 32.95 seconds
Started Jun 10 05:28:39 PM PDT 24
Finished Jun 10 05:29:13 PM PDT 24
Peak memory 205176 kb
Host smart-903d41e8-472e-4329-8e21-7991a46a1c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35884
15230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3588415230
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3070023945
Short name T119
Test name
Test status
Simulation time 94263472 ps
CPU time 0.79 seconds
Started Jun 10 05:08:55 PM PDT 24
Finished Jun 10 05:08:56 PM PDT 24
Peak memory 204916 kb
Host smart-5257bc72-b9e2-4866-8d51-5c4228600fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3070023945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3070023945
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3870263403
Short name T8
Test name
Test status
Simulation time 23394394664 ps
CPU time 26.18 seconds
Started Jun 10 05:24:01 PM PDT 24
Finished Jun 10 05:24:28 PM PDT 24
Peak memory 205148 kb
Host smart-d62260c7-4872-40bd-b940-f8ddd13a73cc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3870263403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3870263403
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1814055546
Short name T107
Test name
Test status
Simulation time 103615050 ps
CPU time 1.32 seconds
Started Jun 10 05:08:59 PM PDT 24
Finished Jun 10 05:09:01 PM PDT 24
Peak memory 213480 kb
Host smart-27c17d28-f37f-4b94-b53a-267975a97d53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814055546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1814055546
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1906278990
Short name T5
Test name
Test status
Simulation time 22759866522 ps
CPU time 517.76 seconds
Started Jun 10 05:24:05 PM PDT 24
Finished Jun 10 05:32:43 PM PDT 24
Peak memory 205276 kb
Host smart-bb5468f1-b886-40c9-a405-f50767f52747
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1906278990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1906278990
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.2635183622
Short name T300
Test name
Test status
Simulation time 223953176 ps
CPU time 0.92 seconds
Started Jun 10 05:27:12 PM PDT 24
Finished Jun 10 05:27:13 PM PDT 24
Peak memory 205024 kb
Host smart-44df9f61-2a4b-438a-a74e-4a965fdcc430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26351
83622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.2635183622
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.748251880
Short name T275
Test name
Test status
Simulation time 74488810 ps
CPU time 0.75 seconds
Started Jun 10 05:08:58 PM PDT 24
Finished Jun 10 05:08:59 PM PDT 24
Peak memory 205148 kb
Host smart-81036afa-c374-48da-86a8-2ebab6c03cfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=748251880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.748251880
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.2595355042
Short name T21
Test name
Test status
Simulation time 166697296 ps
CPU time 0.84 seconds
Started Jun 10 05:24:31 PM PDT 24
Finished Jun 10 05:24:32 PM PDT 24
Peak memory 205012 kb
Host smart-995134a5-b631-49e8-9f71-e863629d5d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25953
55042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.2595355042
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.478676956
Short name T42
Test name
Test status
Simulation time 134577591 ps
CPU time 0.77 seconds
Started Jun 10 05:25:01 PM PDT 24
Finished Jun 10 05:25:03 PM PDT 24
Peak memory 205040 kb
Host smart-0e941497-aa93-4669-b76a-a57aee4e9e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47867
6956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.478676956
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3515585561
Short name T72
Test name
Test status
Simulation time 215999586 ps
CPU time 0.91 seconds
Started Jun 10 05:28:50 PM PDT 24
Finished Jun 10 05:28:51 PM PDT 24
Peak memory 205024 kb
Host smart-dd6f9134-bd24-4b7e-a73e-5850ab612f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35155
85561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3515585561
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1007150493
Short name T244
Test name
Test status
Simulation time 869917194 ps
CPU time 5.38 seconds
Started Jun 10 05:09:00 PM PDT 24
Finished Jun 10 05:09:06 PM PDT 24
Peak memory 205136 kb
Host smart-d059cdfc-530d-478a-a367-9c4a8cad2ef3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1007150493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1007150493
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2114596884
Short name T102
Test name
Test status
Simulation time 1064495416 ps
CPU time 2.02 seconds
Started Jun 10 05:24:19 PM PDT 24
Finished Jun 10 05:24:22 PM PDT 24
Peak memory 222232 kb
Host smart-5d826398-36fe-498d-b3eb-b3d2c14d252a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2114596884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2114596884
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1965354702
Short name T26
Test name
Test status
Simulation time 71817471 ps
CPU time 0.68 seconds
Started Jun 10 05:25:25 PM PDT 24
Finished Jun 10 05:25:26 PM PDT 24
Peak memory 205020 kb
Host smart-de8b1754-4f49-4bd0-8116-fa013839fc05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19653
54702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1965354702
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.955630461
Short name T3
Test name
Test status
Simulation time 137515454 ps
CPU time 0.77 seconds
Started Jun 10 05:27:04 PM PDT 24
Finished Jun 10 05:27:05 PM PDT 24
Peak memory 205132 kb
Host smart-c1fc5c54-caf1-4cd3-ab25-1aa655be62f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95563
0461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.955630461
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2800516609
Short name T53
Test name
Test status
Simulation time 199663590 ps
CPU time 0.9 seconds
Started Jun 10 05:29:08 PM PDT 24
Finished Jun 10 05:29:10 PM PDT 24
Peak memory 204888 kb
Host smart-905be5c5-f2d7-4a52-b887-9fffbfb6f696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28005
16609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2800516609
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3287313246
Short name T121
Test name
Test status
Simulation time 67751797 ps
CPU time 0.72 seconds
Started Jun 10 05:09:00 PM PDT 24
Finished Jun 10 05:09:01 PM PDT 24
Peak memory 204888 kb
Host smart-e95accfd-c169-464f-ba2a-f8b3692fd2b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3287313246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.3287313246
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3673422839
Short name T64
Test name
Test status
Simulation time 1048685865 ps
CPU time 2.25 seconds
Started Jun 10 05:29:04 PM PDT 24
Finished Jun 10 05:29:07 PM PDT 24
Peak memory 205148 kb
Host smart-7a84957f-e4a7-47c6-b212-0659b1e8971a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36734
22839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3673422839
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.53387814
Short name T14
Test name
Test status
Simulation time 23331310455 ps
CPU time 27.89 seconds
Started Jun 10 05:24:46 PM PDT 24
Finished Jun 10 05:25:15 PM PDT 24
Peak memory 205260 kb
Host smart-1a054241-57c4-4a7f-822a-cfb5596988f4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=53387814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.53387814
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1442556249
Short name T47
Test name
Test status
Simulation time 214279825 ps
CPU time 0.88 seconds
Started Jun 10 05:28:34 PM PDT 24
Finished Jun 10 05:28:35 PM PDT 24
Peak memory 204988 kb
Host smart-391d80b6-0727-4674-897a-5d74a46b1dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14425
56249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1442556249
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.355738277
Short name T234
Test name
Test status
Simulation time 85900734 ps
CPU time 2.15 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:50 PM PDT 24
Peak memory 205308 kb
Host smart-4a4e3b18-99af-4ad3-935f-c000e3872dbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=355738277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.355738277
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.4152598652
Short name T251
Test name
Test status
Simulation time 57932518 ps
CPU time 1.45 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 213384 kb
Host smart-35141b73-db4d-4f85-8ad8-fe9b2323563f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4152598652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.4152598652
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1499273285
Short name T486
Test name
Test status
Simulation time 340682425 ps
CPU time 2.06 seconds
Started Jun 10 05:24:12 PM PDT 24
Finished Jun 10 05:24:15 PM PDT 24
Peak memory 205136 kb
Host smart-48406d9e-f2a3-423e-80bd-8dcf26bca31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14992
73285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1499273285
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.2204711524
Short name T408
Test name
Test status
Simulation time 144757085 ps
CPU time 0.75 seconds
Started Jun 10 05:24:06 PM PDT 24
Finished Jun 10 05:24:07 PM PDT 24
Peak memory 204996 kb
Host smart-c3fe232a-ca7b-4f92-97a3-f0674b022d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22047
11524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.2204711524
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1413702042
Short name T279
Test name
Test status
Simulation time 91365384 ps
CPU time 0.72 seconds
Started Jun 10 05:08:53 PM PDT 24
Finished Jun 10 05:08:55 PM PDT 24
Peak memory 204892 kb
Host smart-2a1c2d2b-ef11-458a-ab4f-ac0f7cbd76d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1413702042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1413702042
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1309844474
Short name T246
Test name
Test status
Simulation time 1067995600 ps
CPU time 4.3 seconds
Started Jun 10 05:09:02 PM PDT 24
Finished Jun 10 05:09:06 PM PDT 24
Peak memory 205196 kb
Host smart-140c1bee-9bdc-4761-a821-1db83655cc87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1309844474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1309844474
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.685272897
Short name T470
Test name
Test status
Simulation time 167643420 ps
CPU time 0.85 seconds
Started Jun 10 05:24:05 PM PDT 24
Finished Jun 10 05:24:06 PM PDT 24
Peak memory 205012 kb
Host smart-12e19019-7406-433a-8823-bb2759702f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68527
2897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.685272897
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2725648483
Short name T97
Test name
Test status
Simulation time 20943785057 ps
CPU time 158.91 seconds
Started Jun 10 05:24:16 PM PDT 24
Finished Jun 10 05:26:56 PM PDT 24
Peak memory 205216 kb
Host smart-34bc44a1-76a8-46b4-a655-57816e072a80
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2725648483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2725648483
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2530610594
Short name T273
Test name
Test status
Simulation time 48933085 ps
CPU time 0.79 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:48 PM PDT 24
Peak memory 204944 kb
Host smart-e8c569f9-1b8f-48f6-9d16-0ee276bfe467
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2530610594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2530610594
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.1818537934
Short name T44
Test name
Test status
Simulation time 13328671969 ps
CPU time 16.31 seconds
Started Jun 10 05:26:57 PM PDT 24
Finished Jun 10 05:27:14 PM PDT 24
Peak memory 205092 kb
Host smart-ef941e4c-fde7-4189-8536-c31134ab4cfa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1818537934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.1818537934
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.4241508062
Short name T350
Test name
Test status
Simulation time 3639323153 ps
CPU time 4.29 seconds
Started Jun 10 05:28:18 PM PDT 24
Finished Jun 10 05:28:23 PM PDT 24
Peak memory 205188 kb
Host smart-d354079a-f695-440c-89f9-e5b97cdce387
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4241508062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.4241508062
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.70721036
Short name T230
Test name
Test status
Simulation time 1022530086 ps
CPU time 5.21 seconds
Started Jun 10 05:08:56 PM PDT 24
Finished Jun 10 05:09:02 PM PDT 24
Peak memory 205244 kb
Host smart-de68da8f-4557-4ce2-a6d1-3ec537ef2f91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=70721036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.70721036
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1810705665
Short name T54
Test name
Test status
Simulation time 209587226 ps
CPU time 0.88 seconds
Started Jun 10 05:25:18 PM PDT 24
Finished Jun 10 05:25:19 PM PDT 24
Peak memory 205016 kb
Host smart-212e56bf-cfd4-4495-9386-1591e455cb9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18107
05665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1810705665
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3553391543
Short name T222
Test name
Test status
Simulation time 5134046699 ps
CPU time 44.29 seconds
Started Jun 10 05:24:02 PM PDT 24
Finished Jun 10 05:24:46 PM PDT 24
Peak memory 205136 kb
Host smart-d16954d2-b420-4721-a2ea-db507f2df94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35533
91543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3553391543
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1948215673
Short name T292
Test name
Test status
Simulation time 1007959355 ps
CPU time 3.43 seconds
Started Jun 10 05:08:46 PM PDT 24
Finished Jun 10 05:08:50 PM PDT 24
Peak memory 205236 kb
Host smart-a9c4a880-6afc-4040-acb6-e54cead1dedd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1948215673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1948215673
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.2796500504
Short name T208
Test name
Test status
Simulation time 8243815621 ps
CPU time 136.67 seconds
Started Jun 10 05:24:06 PM PDT 24
Finished Jun 10 05:26:23 PM PDT 24
Peak memory 205288 kb
Host smart-5fa109a5-b27c-48b4-a8dc-4bc7159b3911
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2796500504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2796500504
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1913624950
Short name T2127
Test name
Test status
Simulation time 32816341 ps
CPU time 0.67 seconds
Started Jun 10 05:08:58 PM PDT 24
Finished Jun 10 05:08:59 PM PDT 24
Peak memory 204924 kb
Host smart-5ab41cfb-43fd-4bcb-801f-47d9934b2501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1913624950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1913624950
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3339841586
Short name T231
Test name
Test status
Simulation time 328711329 ps
CPU time 2.57 seconds
Started Jun 10 05:09:00 PM PDT 24
Finished Jun 10 05:09:02 PM PDT 24
Peak memory 205148 kb
Host smart-5d4cffc2-bcda-41d1-beda-8fec0a38347f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3339841586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3339841586
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3176636617
Short name T223
Test name
Test status
Simulation time 91109853 ps
CPU time 2.39 seconds
Started Jun 10 05:08:48 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 205332 kb
Host smart-db589204-28a0-4516-85ff-2b0d278940d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3176636617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3176636617
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3545374644
Short name T212
Test name
Test status
Simulation time 18104727572 ps
CPU time 40.49 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:26:26 PM PDT 24
Peak memory 205400 kb
Host smart-e5695cdf-2784-430b-9243-9da2330734f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35453
74644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3545374644
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.2627382209
Short name T77
Test name
Test status
Simulation time 141948039 ps
CPU time 0.75 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:54 PM PDT 24
Peak memory 205004 kb
Host smart-8382a2af-ef35-4d81-9d1f-f48852627c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26273
82209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.2627382209
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.963810236
Short name T62
Test name
Test status
Simulation time 179409508 ps
CPU time 0.84 seconds
Started Jun 10 05:25:39 PM PDT 24
Finished Jun 10 05:25:40 PM PDT 24
Peak memory 205024 kb
Host smart-61e83ef4-a18f-47b8-8777-fec5561b2293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96381
0236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.963810236
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2542101402
Short name T99
Test name
Test status
Simulation time 18701050394 ps
CPU time 438.55 seconds
Started Jun 10 05:24:13 PM PDT 24
Finished Jun 10 05:31:33 PM PDT 24
Peak memory 205292 kb
Host smart-f5d26892-6528-4ae8-bc41-b9abffac9bc3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2542101402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2542101402
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.1654541041
Short name T1047
Test name
Test status
Simulation time 173578547 ps
CPU time 0.78 seconds
Started Jun 10 05:24:08 PM PDT 24
Finished Jun 10 05:24:09 PM PDT 24
Peak memory 205052 kb
Host smart-dcbcebcb-8bd7-46dd-9775-3cae3b1725b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16545
41041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.1654541041
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.741394421
Short name T31
Test name
Test status
Simulation time 150775191 ps
CPU time 0.79 seconds
Started Jun 10 05:25:23 PM PDT 24
Finished Jun 10 05:25:24 PM PDT 24
Peak memory 205008 kb
Host smart-5f30e724-1cf0-4b0d-9598-b35792b8303c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74139
4421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.741394421
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.186934229
Short name T4
Test name
Test status
Simulation time 5165128186 ps
CPU time 140.18 seconds
Started Jun 10 05:25:51 PM PDT 24
Finished Jun 10 05:28:11 PM PDT 24
Peak memory 205232 kb
Host smart-099f8376-031f-469d-ac8e-20a96be3e183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18693
4229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.186934229
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.643105153
Short name T1113
Test name
Test status
Simulation time 1423865255 ps
CPU time 2.82 seconds
Started Jun 10 05:28:58 PM PDT 24
Finished Jun 10 05:29:01 PM PDT 24
Peak memory 205156 kb
Host smart-066a6c90-60dd-458e-9488-dfa34d08f734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64310
5153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.643105153
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3142661041
Short name T1843
Test name
Test status
Simulation time 185909046 ps
CPU time 0.83 seconds
Started Jun 10 05:24:12 PM PDT 24
Finished Jun 10 05:24:13 PM PDT 24
Peak memory 205004 kb
Host smart-6a6e2d89-acb9-4085-ad4e-42cf64e04cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31426
61041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3142661041
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_smoke.2411341478
Short name T1745
Test name
Test status
Simulation time 241006982 ps
CPU time 0.91 seconds
Started Jun 10 05:24:02 PM PDT 24
Finished Jun 10 05:24:03 PM PDT 24
Peak memory 204968 kb
Host smart-cdb43010-c570-4272-9cd1-c32f38d2c315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24113
41478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2411341478
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1902865110
Short name T494
Test name
Test status
Simulation time 41256147 ps
CPU time 0.66 seconds
Started Jun 10 05:24:17 PM PDT 24
Finished Jun 10 05:24:19 PM PDT 24
Peak memory 204996 kb
Host smart-5aa18b96-8bb8-4506-95a8-9d0d68b0a6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19028
65110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1902865110
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2204014144
Short name T1737
Test name
Test status
Simulation time 238043117 ps
CPU time 0.94 seconds
Started Jun 10 05:24:08 PM PDT 24
Finished Jun 10 05:24:10 PM PDT 24
Peak memory 205024 kb
Host smart-f85eb266-332a-492e-a3da-2361ce856d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22040
14144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2204014144
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.209437265
Short name T795
Test name
Test status
Simulation time 145723140 ps
CPU time 0.8 seconds
Started Jun 10 05:25:27 PM PDT 24
Finished Jun 10 05:25:28 PM PDT 24
Peak memory 204884 kb
Host smart-8cb33ce2-53f8-449e-96db-cbfbb654bb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20943
7265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.209437265
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1237369962
Short name T1211
Test name
Test status
Simulation time 194749227 ps
CPU time 0.94 seconds
Started Jun 10 05:25:29 PM PDT 24
Finished Jun 10 05:25:30 PM PDT 24
Peak memory 205012 kb
Host smart-a71de645-9e94-49bd-8ed6-5e7d7ec27f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12373
69962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1237369962
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3517631945
Short name T1331
Test name
Test status
Simulation time 228735786 ps
CPU time 1.01 seconds
Started Jun 10 05:25:43 PM PDT 24
Finished Jun 10 05:25:44 PM PDT 24
Peak memory 205024 kb
Host smart-4508401f-b5a9-402b-9787-6059e0e4e0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35176
31945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3517631945
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1466576598
Short name T175
Test name
Test status
Simulation time 159880864 ps
CPU time 0.78 seconds
Started Jun 10 05:26:05 PM PDT 24
Finished Jun 10 05:26:06 PM PDT 24
Peak memory 204956 kb
Host smart-a4cef0e4-bb99-4ab1-991c-44a896c150ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14665
76598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1466576598
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.851200913
Short name T296
Test name
Test status
Simulation time 167330496 ps
CPU time 0.77 seconds
Started Jun 10 05:26:05 PM PDT 24
Finished Jun 10 05:26:07 PM PDT 24
Peak memory 205088 kb
Host smart-eb031dcc-62c0-4787-9574-4c6ae35c8d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85120
0913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.851200913
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2204022259
Short name T2106
Test name
Test status
Simulation time 218450789 ps
CPU time 0.94 seconds
Started Jun 10 05:25:57 PM PDT 24
Finished Jun 10 05:25:59 PM PDT 24
Peak memory 205028 kb
Host smart-8acbde4d-43ab-4c62-8507-b08d09b57d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22040
22259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2204022259
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.228139415
Short name T1033
Test name
Test status
Simulation time 148905723 ps
CPU time 0.77 seconds
Started Jun 10 05:26:30 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205020 kb
Host smart-3bc61071-e090-437f-87a1-010f14f36a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22813
9415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.228139415
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.276588320
Short name T238
Test name
Test status
Simulation time 1091616722 ps
CPU time 4.68 seconds
Started Jun 10 05:08:41 PM PDT 24
Finished Jun 10 05:08:46 PM PDT 24
Peak memory 205172 kb
Host smart-3ca4fbac-0d52-41bb-b9a9-7aa3ebb6a15f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=276588320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.276588320
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.3601412165
Short name T1904
Test name
Test status
Simulation time 11882293820 ps
CPU time 232.12 seconds
Started Jun 10 05:24:05 PM PDT 24
Finished Jun 10 05:27:57 PM PDT 24
Peak memory 205256 kb
Host smart-1de3f4d7-f282-4304-82dc-cd593ef93c41
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3601412165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.3601412165
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3280783807
Short name T146
Test name
Test status
Simulation time 202007887 ps
CPU time 0.86 seconds
Started Jun 10 05:24:12 PM PDT 24
Finished Jun 10 05:24:13 PM PDT 24
Peak memory 205004 kb
Host smart-e114061e-a440-4e39-a47a-96719d8ee489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32807
83807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3280783807
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.976923809
Short name T136
Test name
Test status
Simulation time 168847284 ps
CPU time 0.85 seconds
Started Jun 10 05:25:17 PM PDT 24
Finished Jun 10 05:25:18 PM PDT 24
Peak memory 204984 kb
Host smart-310f4dc4-1643-4996-8f3b-875a454ed810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97692
3809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.976923809
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2430362179
Short name T1338
Test name
Test status
Simulation time 20141918701 ps
CPU time 46.38 seconds
Started Jun 10 05:25:19 PM PDT 24
Finished Jun 10 05:26:06 PM PDT 24
Peak memory 205172 kb
Host smart-83c70530-fa84-47ad-b093-ce6e57cda099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24303
62179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2430362179
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.254625651
Short name T149
Test name
Test status
Simulation time 194777251 ps
CPU time 0.84 seconds
Started Jun 10 05:25:25 PM PDT 24
Finished Jun 10 05:25:26 PM PDT 24
Peak memory 204984 kb
Host smart-6d0209f8-ac3b-4883-89e2-56aad9816c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25462
5651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.254625651
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3247445950
Short name T1041
Test name
Test status
Simulation time 983722263 ps
CPU time 2.33 seconds
Started Jun 10 05:25:31 PM PDT 24
Finished Jun 10 05:25:33 PM PDT 24
Peak memory 205176 kb
Host smart-4828b047-a031-4752-861f-d9e1ad616b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32474
45950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3247445950
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.580689103
Short name T140
Test name
Test status
Simulation time 193635435 ps
CPU time 0.89 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:31 PM PDT 24
Peak memory 205000 kb
Host smart-a0bf88fd-ad96-4028-ab6e-89f7be174402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58068
9103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.580689103
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1439560194
Short name T1803
Test name
Test status
Simulation time 201541909 ps
CPU time 0.86 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:39 PM PDT 24
Peak memory 205044 kb
Host smart-28d90078-2e96-48b6-b51d-d1c66d8609b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14395
60194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1439560194
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3470710213
Short name T1626
Test name
Test status
Simulation time 202707707 ps
CPU time 0.91 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:38 PM PDT 24
Peak memory 205004 kb
Host smart-73d05fad-70d7-4a45-bb89-e4fb42956987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34707
10213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3470710213
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.4270275386
Short name T150
Test name
Test status
Simulation time 210578117 ps
CPU time 0.88 seconds
Started Jun 10 05:25:51 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 205120 kb
Host smart-987ae4d0-a712-4a9e-be0b-dd8b07c40f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42702
75386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.4270275386
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2729693067
Short name T153
Test name
Test status
Simulation time 200942947 ps
CPU time 0.89 seconds
Started Jun 10 05:26:02 PM PDT 24
Finished Jun 10 05:26:03 PM PDT 24
Peak memory 205036 kb
Host smart-955e91b3-f87a-4978-91e3-571a64412ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27296
93067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2729693067
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.754830044
Short name T83
Test name
Test status
Simulation time 228536189 ps
CPU time 0.9 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:29 PM PDT 24
Peak memory 204996 kb
Host smart-45e20e74-2cf1-433b-8c28-20c65779883a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75483
0044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.754830044
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1508476068
Short name T132
Test name
Test status
Simulation time 236667161 ps
CPU time 0.93 seconds
Started Jun 10 05:26:38 PM PDT 24
Finished Jun 10 05:26:39 PM PDT 24
Peak memory 205004 kb
Host smart-3bb52f95-09f7-4016-98b1-d98d3e217ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15084
76068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1508476068
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.598149947
Short name T134
Test name
Test status
Simulation time 235299820 ps
CPU time 0.88 seconds
Started Jun 10 05:27:41 PM PDT 24
Finished Jun 10 05:27:42 PM PDT 24
Peak memory 205028 kb
Host smart-f1b051f0-54fb-4749-af53-87756da5ee1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59814
9947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.598149947
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.472169366
Short name T2144
Test name
Test status
Simulation time 75383221 ps
CPU time 1.94 seconds
Started Jun 10 05:08:49 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 205136 kb
Host smart-9a066aa4-8708-47b7-847d-36447a863bab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=472169366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.472169366
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2602000424
Short name T260
Test name
Test status
Simulation time 1653224110 ps
CPU time 7.17 seconds
Started Jun 10 05:08:42 PM PDT 24
Finished Jun 10 05:08:50 PM PDT 24
Peak memory 205144 kb
Host smart-8ffe0085-a161-47eb-baca-31432ba88340
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2602000424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2602000424
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1639005494
Short name T2117
Test name
Test status
Simulation time 67004166 ps
CPU time 0.88 seconds
Started Jun 10 05:08:45 PM PDT 24
Finished Jun 10 05:08:47 PM PDT 24
Peak memory 204648 kb
Host smart-fa7858df-0a32-418e-8032-b9830490ce93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1639005494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1639005494
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4245760237
Short name T105
Test name
Test status
Simulation time 92439101 ps
CPU time 2.05 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:50 PM PDT 24
Peak memory 217060 kb
Host smart-056113e4-5474-4094-9e0c-4dca9eaed07e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245760237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.4245760237
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2352074094
Short name T2195
Test name
Test status
Simulation time 138466956 ps
CPU time 1.08 seconds
Started Jun 10 05:08:45 PM PDT 24
Finished Jun 10 05:08:46 PM PDT 24
Peak memory 205068 kb
Host smart-40c559d7-0683-44c9-9ad2-3c05752065a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2352074094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2352074094
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3449453528
Short name T253
Test name
Test status
Simulation time 109398345 ps
CPU time 1.47 seconds
Started Jun 10 05:08:42 PM PDT 24
Finished Jun 10 05:08:44 PM PDT 24
Peak memory 213420 kb
Host smart-3474952f-bb7c-4a20-b439-6b7bbbc800ca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3449453528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3449453528
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1106303103
Short name T2113
Test name
Test status
Simulation time 708309509 ps
CPU time 4.91 seconds
Started Jun 10 05:08:39 PM PDT 24
Finished Jun 10 05:08:45 PM PDT 24
Peak memory 205040 kb
Host smart-ee01d571-c067-47b7-9771-265aff609e08
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1106303103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1106303103
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3791453688
Short name T2213
Test name
Test status
Simulation time 214367707 ps
CPU time 1.27 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 205252 kb
Host smart-9f24ee3d-10b1-4fed-b923-aff965449456
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3791453688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3791453688
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1820448171
Short name T2183
Test name
Test status
Simulation time 418720092 ps
CPU time 2.91 seconds
Started Jun 10 05:08:53 PM PDT 24
Finished Jun 10 05:08:56 PM PDT 24
Peak memory 205188 kb
Host smart-7e7e45ef-141f-49cc-b950-24b5da0b5406
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1820448171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1820448171
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.901738459
Short name T2198
Test name
Test status
Simulation time 127832399 ps
CPU time 3.4 seconds
Started Jun 10 05:08:45 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 205060 kb
Host smart-f2e29055-ee58-4042-809e-673f270a575d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=901738459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.901738459
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2395265843
Short name T2208
Test name
Test status
Simulation time 2256531473 ps
CPU time 8.69 seconds
Started Jun 10 05:08:45 PM PDT 24
Finished Jun 10 05:08:54 PM PDT 24
Peak memory 205128 kb
Host smart-752650a4-3a99-461a-b2fc-f404f6a5b70d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2395265843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2395265843
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3768115675
Short name T2156
Test name
Test status
Simulation time 63667866 ps
CPU time 0.86 seconds
Started Jun 10 05:08:44 PM PDT 24
Finished Jun 10 05:08:45 PM PDT 24
Peak memory 204916 kb
Host smart-a023cd69-ce49-438f-ae9c-f50f8d6f7c53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3768115675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3768115675
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1417484664
Short name T2167
Test name
Test status
Simulation time 165375248 ps
CPU time 1.89 seconds
Started Jun 10 05:08:44 PM PDT 24
Finished Jun 10 05:08:46 PM PDT 24
Peak memory 216928 kb
Host smart-635e0a8a-25c2-47c8-bdcf-4e64fe43889f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417484664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.1417484664
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2875279951
Short name T2194
Test name
Test status
Simulation time 66302439 ps
CPU time 0.96 seconds
Started Jun 10 05:08:48 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 205116 kb
Host smart-dc89cd10-7bef-4d8c-91d6-5ee28e604b34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2875279951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2875279951
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.4247015550
Short name T2190
Test name
Test status
Simulation time 57680823 ps
CPU time 0.71 seconds
Started Jun 10 05:08:41 PM PDT 24
Finished Jun 10 05:08:42 PM PDT 24
Peak memory 204920 kb
Host smart-8050d57b-cef4-4b0e-8a06-80c38b0759b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4247015550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.4247015550
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4138363231
Short name T2178
Test name
Test status
Simulation time 256634297 ps
CPU time 2.61 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 205064 kb
Host smart-b48eadae-10b3-4945-a4f5-d4271029f849
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4138363231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.4138363231
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.913985394
Short name T2149
Test name
Test status
Simulation time 112579182 ps
CPU time 1.13 seconds
Started Jun 10 05:08:48 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 205176 kb
Host smart-4a6d32fd-1586-4ce6-b89a-30dcb0fcdde0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=913985394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.913985394
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3149415915
Short name T239
Test name
Test status
Simulation time 215745643 ps
CPU time 2.77 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:50 PM PDT 24
Peak memory 205240 kb
Host smart-3e1943e8-c027-48ca-9175-998f1ac1f861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3149415915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3149415915
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3587794803
Short name T272
Test name
Test status
Simulation time 295501061 ps
CPU time 2.03 seconds
Started Jun 10 05:08:58 PM PDT 24
Finished Jun 10 05:09:01 PM PDT 24
Peak memory 213480 kb
Host smart-2a8db934-42d8-4d97-b568-ac9909df558c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587794803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3587794803
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.4037213116
Short name T2166
Test name
Test status
Simulation time 71436987 ps
CPU time 0.85 seconds
Started Jun 10 05:08:54 PM PDT 24
Finished Jun 10 05:08:56 PM PDT 24
Peak memory 204956 kb
Host smart-da0227e7-7aa2-49be-94c1-c93d5ba62aa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4037213116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.4037213116
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2188355155
Short name T2143
Test name
Test status
Simulation time 37363161 ps
CPU time 0.67 seconds
Started Jun 10 05:08:56 PM PDT 24
Finished Jun 10 05:08:57 PM PDT 24
Peak memory 204956 kb
Host smart-b5ab80d8-4c4c-419d-bcd4-3fa9124c0321
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2188355155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2188355155
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.955624584
Short name T2135
Test name
Test status
Simulation time 152694683 ps
CPU time 1.6 seconds
Started Jun 10 05:08:59 PM PDT 24
Finished Jun 10 05:09:01 PM PDT 24
Peak memory 205272 kb
Host smart-f63770d5-3788-4537-a688-dac20dbdee9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=955624584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.955624584
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3468555824
Short name T2211
Test name
Test status
Simulation time 83998449 ps
CPU time 2.12 seconds
Started Jun 10 05:08:51 PM PDT 24
Finished Jun 10 05:08:53 PM PDT 24
Peak memory 205208 kb
Host smart-5d53ea60-3045-4a25-a29e-cb7a9f5de3aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3468555824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3468555824
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3483852330
Short name T2200
Test name
Test status
Simulation time 464705381 ps
CPU time 4.08 seconds
Started Jun 10 05:08:52 PM PDT 24
Finished Jun 10 05:08:56 PM PDT 24
Peak memory 205228 kb
Host smart-383cffa8-ccf0-4a1c-8f7e-127df32b5859
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3483852330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3483852330
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2138971356
Short name T271
Test name
Test status
Simulation time 124205515 ps
CPU time 1.38 seconds
Started Jun 10 05:08:53 PM PDT 24
Finished Jun 10 05:08:55 PM PDT 24
Peak memory 215116 kb
Host smart-5a514ae9-3a14-49bc-b8a2-f5967d95491d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138971356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2138971356
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3275775547
Short name T110
Test name
Test status
Simulation time 47263166 ps
CPU time 1 seconds
Started Jun 10 05:08:49 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 205068 kb
Host smart-acc19151-d335-486c-a78c-a9cb87739f48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3275775547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3275775547
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.558004316
Short name T2202
Test name
Test status
Simulation time 37580090 ps
CPU time 0.63 seconds
Started Jun 10 05:08:55 PM PDT 24
Finished Jun 10 05:08:56 PM PDT 24
Peak memory 204968 kb
Host smart-483845d4-9a21-4bbc-911c-1bd939684ef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=558004316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.558004316
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2323644675
Short name T2179
Test name
Test status
Simulation time 71126554 ps
CPU time 1.1 seconds
Started Jun 10 05:08:53 PM PDT 24
Finished Jun 10 05:08:55 PM PDT 24
Peak memory 205256 kb
Host smart-246b01ab-3dbe-451b-9bc9-3949cac7ead5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2323644675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.2323644675
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.910703194
Short name T2142
Test name
Test status
Simulation time 134659096 ps
CPU time 1.89 seconds
Started Jun 10 05:08:51 PM PDT 24
Finished Jun 10 05:08:53 PM PDT 24
Peak memory 205244 kb
Host smart-eed32be6-acea-403e-9efc-993c4613e6f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=910703194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.910703194
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.75434772
Short name T2152
Test name
Test status
Simulation time 173593836 ps
CPU time 1.92 seconds
Started Jun 10 05:08:54 PM PDT 24
Finished Jun 10 05:08:56 PM PDT 24
Peak memory 213512 kb
Host smart-1ac35932-a914-42bc-b9a1-5a4d801ff0a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75434772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev
_csr_mem_rw_with_rand_reset.75434772
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.693066952
Short name T227
Test name
Test status
Simulation time 66069684 ps
CPU time 0.99 seconds
Started Jun 10 05:08:54 PM PDT 24
Finished Jun 10 05:08:55 PM PDT 24
Peak memory 205132 kb
Host smart-e0548738-51a0-4301-a373-358404aaada7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=693066952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.693066952
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.532874668
Short name T266
Test name
Test status
Simulation time 161050585 ps
CPU time 1.5 seconds
Started Jun 10 05:08:54 PM PDT 24
Finished Jun 10 05:08:56 PM PDT 24
Peak memory 205256 kb
Host smart-2f175530-694d-43be-bb3c-df9dfc370b2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=532874668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.532874668
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.762528500
Short name T2201
Test name
Test status
Simulation time 225679403 ps
CPU time 2.61 seconds
Started Jun 10 05:08:58 PM PDT 24
Finished Jun 10 05:09:01 PM PDT 24
Peak memory 205284 kb
Host smart-851f9a5d-0397-4ba0-b576-6bcec3946467
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=762528500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.762528500
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4042392273
Short name T2131
Test name
Test status
Simulation time 61582183 ps
CPU time 1.39 seconds
Started Jun 10 05:08:49 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 213492 kb
Host smart-f167963a-6f15-4a09-82df-f9bf85dd3896
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042392273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.4042392273
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.4073324628
Short name T2133
Test name
Test status
Simulation time 45240467 ps
CPU time 0.98 seconds
Started Jun 10 05:08:58 PM PDT 24
Finished Jun 10 05:08:59 PM PDT 24
Peak memory 205100 kb
Host smart-df5628b1-b1f7-4392-a93a-3a7809450541
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4073324628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.4073324628
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.763544379
Short name T2187
Test name
Test status
Simulation time 39963946 ps
CPU time 0.67 seconds
Started Jun 10 05:08:49 PM PDT 24
Finished Jun 10 05:08:50 PM PDT 24
Peak memory 204940 kb
Host smart-be0a8847-e0be-4506-8bfa-4a211f795c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=763544379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.763544379
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3909708800
Short name T2170
Test name
Test status
Simulation time 91833639 ps
CPU time 1.24 seconds
Started Jun 10 05:08:49 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 205188 kb
Host smart-f885dcf5-649b-4146-bed2-5e136cca4103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3909708800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3909708800
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3447889565
Short name T2129
Test name
Test status
Simulation time 205085607 ps
CPU time 2.47 seconds
Started Jun 10 05:08:57 PM PDT 24
Finished Jun 10 05:09:00 PM PDT 24
Peak memory 220980 kb
Host smart-86b72e87-6dec-4108-8184-025eafe1b7fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3447889565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3447889565
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3901609603
Short name T290
Test name
Test status
Simulation time 558943734 ps
CPU time 2.96 seconds
Started Jun 10 05:09:01 PM PDT 24
Finished Jun 10 05:09:05 PM PDT 24
Peak memory 205176 kb
Host smart-5d67f576-3764-434c-8f5c-e7cb0591b9ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3901609603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3901609603
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3190508357
Short name T2123
Test name
Test status
Simulation time 121231687 ps
CPU time 1.47 seconds
Started Jun 10 05:08:55 PM PDT 24
Finished Jun 10 05:08:57 PM PDT 24
Peak memory 213484 kb
Host smart-f894539f-3901-4fde-966b-17e9fc5855c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190508357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3190508357
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3108760832
Short name T256
Test name
Test status
Simulation time 65449339 ps
CPU time 0.96 seconds
Started Jun 10 05:09:11 PM PDT 24
Finished Jun 10 05:09:13 PM PDT 24
Peak memory 205160 kb
Host smart-dd32c6fc-9293-4be5-a2a8-e1f0aebd3db1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3108760832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3108760832
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3082225577
Short name T2154
Test name
Test status
Simulation time 238557291 ps
CPU time 1.8 seconds
Started Jun 10 05:08:48 PM PDT 24
Finished Jun 10 05:08:50 PM PDT 24
Peak memory 205164 kb
Host smart-797406f9-a73f-4bac-9d90-4d62548054b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3082225577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3082225577
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.480003334
Short name T228
Test name
Test status
Simulation time 178725865 ps
CPU time 1.84 seconds
Started Jun 10 05:08:53 PM PDT 24
Finished Jun 10 05:08:56 PM PDT 24
Peak memory 213468 kb
Host smart-727bd99d-726c-48d3-89bf-2ba27ff97a66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=480003334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.480003334
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2922716154
Short name T109
Test name
Test status
Simulation time 440031607 ps
CPU time 2.92 seconds
Started Jun 10 05:09:00 PM PDT 24
Finished Jun 10 05:09:03 PM PDT 24
Peak memory 205532 kb
Host smart-f27bef12-4fde-4e82-9b02-d327257d2da8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2922716154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2922716154
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2897133825
Short name T241
Test name
Test status
Simulation time 228907362 ps
CPU time 1.84 seconds
Started Jun 10 05:08:54 PM PDT 24
Finished Jun 10 05:08:56 PM PDT 24
Peak memory 213356 kb
Host smart-a0ce46ac-5340-4114-82d7-b5cb098dce87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897133825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2897133825
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.693330960
Short name T111
Test name
Test status
Simulation time 85008848 ps
CPU time 1.11 seconds
Started Jun 10 05:08:58 PM PDT 24
Finished Jun 10 05:09:00 PM PDT 24
Peak memory 205344 kb
Host smart-ca67340a-58f6-416b-95e0-30a3301d5293
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=693330960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.693330960
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.778328576
Short name T2207
Test name
Test status
Simulation time 142094493 ps
CPU time 1.73 seconds
Started Jun 10 05:08:57 PM PDT 24
Finished Jun 10 05:08:59 PM PDT 24
Peak memory 205220 kb
Host smart-96132a2a-4a06-4b83-ab4e-eac1d5b6b96d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=778328576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.778328576
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1296347409
Short name T106
Test name
Test status
Simulation time 62218391 ps
CPU time 1.72 seconds
Started Jun 10 05:08:51 PM PDT 24
Finished Jun 10 05:08:54 PM PDT 24
Peak memory 205484 kb
Host smart-e8488d76-0254-41e6-a9a5-1d5aff4f0716
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1296347409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1296347409
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.4015753716
Short name T2151
Test name
Test status
Simulation time 326428801 ps
CPU time 2.38 seconds
Started Jun 10 05:08:53 PM PDT 24
Finished Jun 10 05:08:56 PM PDT 24
Peak memory 205176 kb
Host smart-4590435f-778a-41e6-b3b7-aa831ec1142b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4015753716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.4015753716
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3972864793
Short name T2132
Test name
Test status
Simulation time 103747374 ps
CPU time 0.91 seconds
Started Jun 10 05:08:57 PM PDT 24
Finished Jun 10 05:08:58 PM PDT 24
Peak memory 205000 kb
Host smart-26eee1c3-1efc-41b5-8868-235514c4ef65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3972864793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3972864793
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2823892984
Short name T2182
Test name
Test status
Simulation time 37902415 ps
CPU time 0.69 seconds
Started Jun 10 05:08:54 PM PDT 24
Finished Jun 10 05:08:55 PM PDT 24
Peak memory 204876 kb
Host smart-707fc23d-810a-45ab-a1cd-3058302484d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2823892984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2823892984
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3150440396
Short name T2196
Test name
Test status
Simulation time 436591606 ps
CPU time 1.84 seconds
Started Jun 10 05:09:03 PM PDT 24
Finished Jun 10 05:09:05 PM PDT 24
Peak memory 205144 kb
Host smart-e1ce393a-2458-4737-9fb2-c224f7d4545b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3150440396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3150440396
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1935789103
Short name T237
Test name
Test status
Simulation time 93686157 ps
CPU time 2.24 seconds
Started Jun 10 05:08:55 PM PDT 24
Finished Jun 10 05:08:58 PM PDT 24
Peak memory 220788 kb
Host smart-010532db-d8af-42c7-bd78-b18850f87778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1935789103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1935789103
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3804932324
Short name T2199
Test name
Test status
Simulation time 128255294 ps
CPU time 1.23 seconds
Started Jun 10 05:09:03 PM PDT 24
Finished Jun 10 05:09:05 PM PDT 24
Peak memory 221596 kb
Host smart-0784fa0e-c7eb-4e74-a528-86006319e178
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804932324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3804932324
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1816022336
Short name T2134
Test name
Test status
Simulation time 74172301 ps
CPU time 1 seconds
Started Jun 10 05:08:57 PM PDT 24
Finished Jun 10 05:08:58 PM PDT 24
Peak memory 205148 kb
Host smart-ee74d741-ed22-43fb-acc6-ecbd7226df91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1816022336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1816022336
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3082057925
Short name T2138
Test name
Test status
Simulation time 83364617 ps
CPU time 0.74 seconds
Started Jun 10 05:08:58 PM PDT 24
Finished Jun 10 05:08:59 PM PDT 24
Peak memory 204924 kb
Host smart-f8adafeb-cc59-4910-8f0b-fe986c110824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3082057925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3082057925
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.632425808
Short name T113
Test name
Test status
Simulation time 105676744 ps
CPU time 1.21 seconds
Started Jun 10 05:09:03 PM PDT 24
Finished Jun 10 05:09:05 PM PDT 24
Peak memory 205040 kb
Host smart-03e3e922-4915-463e-87c5-a5e5447dd294
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=632425808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.632425808
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3166861313
Short name T2164
Test name
Test status
Simulation time 167751483 ps
CPU time 1.76 seconds
Started Jun 10 05:08:56 PM PDT 24
Finished Jun 10 05:08:58 PM PDT 24
Peak memory 205240 kb
Host smart-085ad1c8-6041-4c2f-aa6e-d5d75e77bc18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3166861313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3166861313
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2016271470
Short name T291
Test name
Test status
Simulation time 922263862 ps
CPU time 4.8 seconds
Started Jun 10 05:08:56 PM PDT 24
Finished Jun 10 05:09:01 PM PDT 24
Peak memory 205164 kb
Host smart-edbd1309-3c82-48c6-a64d-15c8f3ad41f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2016271470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2016271470
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2006102790
Short name T2189
Test name
Test status
Simulation time 157762394 ps
CPU time 1.81 seconds
Started Jun 10 05:09:00 PM PDT 24
Finished Jun 10 05:09:03 PM PDT 24
Peak memory 213432 kb
Host smart-d02f883f-94a3-48ad-aba0-d987a593af50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006102790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2006102790
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2709574063
Short name T265
Test name
Test status
Simulation time 52486187 ps
CPU time 0.86 seconds
Started Jun 10 05:08:55 PM PDT 24
Finished Jun 10 05:08:56 PM PDT 24
Peak memory 204948 kb
Host smart-ecb99589-43c0-4b0b-aca4-d2207bc2c64e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2709574063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2709574063
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1447288254
Short name T2215
Test name
Test status
Simulation time 118259015 ps
CPU time 1.54 seconds
Started Jun 10 05:09:07 PM PDT 24
Finished Jun 10 05:09:09 PM PDT 24
Peak memory 205240 kb
Host smart-ab5f0320-9d5e-44b7-a580-a0e17d973f86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1447288254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1447288254
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1611458585
Short name T240
Test name
Test status
Simulation time 116938141 ps
CPU time 2.49 seconds
Started Jun 10 05:08:56 PM PDT 24
Finished Jun 10 05:08:59 PM PDT 24
Peak memory 213428 kb
Host smart-af093d59-0730-48f7-bd48-203712326160
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1611458585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1611458585
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3206767238
Short name T293
Test name
Test status
Simulation time 579347189 ps
CPU time 4.17 seconds
Started Jun 10 05:08:56 PM PDT 24
Finished Jun 10 05:09:00 PM PDT 24
Peak memory 205084 kb
Host smart-fd3a40de-25fd-423a-aedb-f4cbdf47f90b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3206767238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3206767238
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1709829205
Short name T2137
Test name
Test status
Simulation time 107358036 ps
CPU time 2.73 seconds
Started Jun 10 05:08:56 PM PDT 24
Finished Jun 10 05:08:59 PM PDT 24
Peak memory 213388 kb
Host smart-8656794b-466c-4ea4-ac72-692ee267345d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709829205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1709829205
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3780765447
Short name T254
Test name
Test status
Simulation time 96307277 ps
CPU time 1.15 seconds
Started Jun 10 05:08:56 PM PDT 24
Finished Jun 10 05:08:57 PM PDT 24
Peak memory 205132 kb
Host smart-8a302e9e-26b1-4533-bc09-294027b4191a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3780765447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3780765447
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3006224891
Short name T2161
Test name
Test status
Simulation time 28814832 ps
CPU time 0.65 seconds
Started Jun 10 05:08:58 PM PDT 24
Finished Jun 10 05:08:59 PM PDT 24
Peak memory 205148 kb
Host smart-7dd7b9f4-6daf-4f64-bf73-338e429ffc55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3006224891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3006224891
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3109013983
Short name T2120
Test name
Test status
Simulation time 87552810 ps
CPU time 1.09 seconds
Started Jun 10 05:08:56 PM PDT 24
Finished Jun 10 05:08:58 PM PDT 24
Peak memory 205224 kb
Host smart-b4d8a53d-96d6-477a-87d7-db8a8e4ca671
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3109013983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3109013983
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1282287941
Short name T2185
Test name
Test status
Simulation time 158908236 ps
CPU time 1.95 seconds
Started Jun 10 05:08:59 PM PDT 24
Finished Jun 10 05:09:02 PM PDT 24
Peak memory 205256 kb
Host smart-eea23edd-5d8b-4d61-905f-a2c98d626cd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1282287941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1282287941
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1446571311
Short name T2165
Test name
Test status
Simulation time 118326787 ps
CPU time 3.19 seconds
Started Jun 10 05:08:46 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 205048 kb
Host smart-04bf7938-85f1-495e-bc2f-c225c48f264c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1446571311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1446571311
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1558598875
Short name T252
Test name
Test status
Simulation time 1730632609 ps
CPU time 8.67 seconds
Started Jun 10 05:08:45 PM PDT 24
Finished Jun 10 05:08:54 PM PDT 24
Peak memory 204748 kb
Host smart-f29af032-e14f-49fd-8cf6-bf243bd3b6fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1558598875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1558598875
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3506708649
Short name T2115
Test name
Test status
Simulation time 164579614 ps
CPU time 1.06 seconds
Started Jun 10 05:08:44 PM PDT 24
Finished Jun 10 05:08:45 PM PDT 24
Peak memory 204832 kb
Host smart-e0002f28-44cf-495c-9d4d-90722d75489b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3506708649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3506708649
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1563367584
Short name T2125
Test name
Test status
Simulation time 172251512 ps
CPU time 1.41 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 213432 kb
Host smart-966bcec0-6d9b-472d-8fe3-72587084bb7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563367584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1563367584
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1418745898
Short name T2214
Test name
Test status
Simulation time 95152095 ps
CPU time 1.05 seconds
Started Jun 10 05:08:42 PM PDT 24
Finished Jun 10 05:08:43 PM PDT 24
Peak memory 205444 kb
Host smart-4d40aa12-a639-44c7-910f-e122d99e9a97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1418745898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1418745898
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.847603864
Short name T285
Test name
Test status
Simulation time 51309910 ps
CPU time 0.7 seconds
Started Jun 10 05:08:46 PM PDT 24
Finished Jun 10 05:08:47 PM PDT 24
Peak memory 204944 kb
Host smart-f83894a4-b3f2-42c4-8c48-3b0de519f296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=847603864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.847603864
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2095635286
Short name T2188
Test name
Test status
Simulation time 57752011 ps
CPU time 1.34 seconds
Started Jun 10 05:08:42 PM PDT 24
Finished Jun 10 05:08:44 PM PDT 24
Peak memory 213384 kb
Host smart-dc6ff823-ab00-457d-a19c-1f16e66f00f8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2095635286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2095635286
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3232878620
Short name T2114
Test name
Test status
Simulation time 378360471 ps
CPU time 2.79 seconds
Started Jun 10 05:08:46 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 205048 kb
Host smart-2d499fcc-e6d2-46f3-a591-fac8b3bdc791
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3232878620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3232878620
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3165396164
Short name T2140
Test name
Test status
Simulation time 65182906 ps
CPU time 1.11 seconds
Started Jun 10 05:08:44 PM PDT 24
Finished Jun 10 05:08:45 PM PDT 24
Peak memory 205184 kb
Host smart-b837af3d-a0ee-4779-b655-277909fe9c87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3165396164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3165396164
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.293115561
Short name T2184
Test name
Test status
Simulation time 97758922 ps
CPU time 2.1 seconds
Started Jun 10 05:08:44 PM PDT 24
Finished Jun 10 05:08:46 PM PDT 24
Peak memory 213296 kb
Host smart-b702285c-069d-44c6-ae70-e2ee0ef2b69a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=293115561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.293115561
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2005148218
Short name T2128
Test name
Test status
Simulation time 391980758 ps
CPU time 2.9 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 205176 kb
Host smart-812955d0-0bc3-4bfd-8e6a-83d6f4ac6c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2005148218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2005148218
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2823795961
Short name T283
Test name
Test status
Simulation time 35940945 ps
CPU time 0.68 seconds
Started Jun 10 05:09:04 PM PDT 24
Finished Jun 10 05:09:06 PM PDT 24
Peak memory 204944 kb
Host smart-40171420-27ec-4c19-bd28-2d6aba1522f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2823795961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2823795961
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2849053950
Short name T286
Test name
Test status
Simulation time 46318391 ps
CPU time 0.68 seconds
Started Jun 10 05:08:57 PM PDT 24
Finished Jun 10 05:08:58 PM PDT 24
Peak memory 204920 kb
Host smart-d6a74bf1-3256-4034-a7de-7513feb467ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2849053950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2849053950
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1869313104
Short name T2174
Test name
Test status
Simulation time 85240515 ps
CPU time 0.75 seconds
Started Jun 10 05:09:12 PM PDT 24
Finished Jun 10 05:09:14 PM PDT 24
Peak memory 204948 kb
Host smart-d3336ea1-68a2-4f5d-a25d-dbf5bfb3d713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1869313104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1869313104
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.835652971
Short name T2148
Test name
Test status
Simulation time 55426822 ps
CPU time 0.73 seconds
Started Jun 10 05:09:05 PM PDT 24
Finished Jun 10 05:09:06 PM PDT 24
Peak memory 204916 kb
Host smart-928c7ee9-dd76-4370-aa97-6090b1522955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=835652971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.835652971
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.535251753
Short name T2122
Test name
Test status
Simulation time 79494449 ps
CPU time 0.72 seconds
Started Jun 10 05:09:04 PM PDT 24
Finished Jun 10 05:09:06 PM PDT 24
Peak memory 204948 kb
Host smart-2304958d-fbab-4376-91e2-f126ca04756e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=535251753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.535251753
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2229985404
Short name T2157
Test name
Test status
Simulation time 49168296 ps
CPU time 0.66 seconds
Started Jun 10 05:09:03 PM PDT 24
Finished Jun 10 05:09:04 PM PDT 24
Peak memory 204944 kb
Host smart-e2dbedb0-788c-4419-bd1d-6cb31842c4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2229985404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2229985404
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3969819433
Short name T2212
Test name
Test status
Simulation time 39111882 ps
CPU time 0.68 seconds
Started Jun 10 05:09:08 PM PDT 24
Finished Jun 10 05:09:09 PM PDT 24
Peak memory 204896 kb
Host smart-4bb5b418-b309-4e7e-b243-cad81b8b6261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3969819433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3969819433
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2824790970
Short name T2153
Test name
Test status
Simulation time 46070034 ps
CPU time 0.71 seconds
Started Jun 10 05:09:01 PM PDT 24
Finished Jun 10 05:09:02 PM PDT 24
Peak memory 204876 kb
Host smart-1a12d820-9aef-4a6a-99d0-21496df07c42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2824790970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2824790970
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3398384489
Short name T287
Test name
Test status
Simulation time 36818226 ps
CPU time 0.69 seconds
Started Jun 10 05:09:24 PM PDT 24
Finished Jun 10 05:09:26 PM PDT 24
Peak memory 204924 kb
Host smart-cf025e06-bb9c-49f5-b7ec-3cf0a463bcac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3398384489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3398384489
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.19028549
Short name T2139
Test name
Test status
Simulation time 199429031 ps
CPU time 2.31 seconds
Started Jun 10 05:08:50 PM PDT 24
Finished Jun 10 05:08:52 PM PDT 24
Peak memory 205144 kb
Host smart-be0228b5-057a-49f0-bdc4-9c1c1372abfc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=19028549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.19028549
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4067927878
Short name T263
Test name
Test status
Simulation time 677464673 ps
CPU time 4.64 seconds
Started Jun 10 05:08:49 PM PDT 24
Finished Jun 10 05:08:54 PM PDT 24
Peak memory 205108 kb
Host smart-e2abbc47-54a3-45ce-a254-3feb57821c2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4067927878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.4067927878
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2612945614
Short name T258
Test name
Test status
Simulation time 69255146 ps
CPU time 0.82 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 204956 kb
Host smart-cdbed32d-6243-4e11-9296-f3f2b4f9b08b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2612945614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2612945614
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.406206812
Short name T2150
Test name
Test status
Simulation time 154728833 ps
CPU time 1.64 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 213384 kb
Host smart-8efc8303-318f-4c53-a187-e4520ab9dc97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406206812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.406206812
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.672083368
Short name T267
Test name
Test status
Simulation time 132072383 ps
CPU time 0.98 seconds
Started Jun 10 05:08:51 PM PDT 24
Finished Jun 10 05:08:52 PM PDT 24
Peak memory 204992 kb
Host smart-299703c8-6ac0-4198-8a93-e1b0fc9d82f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=672083368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.672083368
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2839770044
Short name T2118
Test name
Test status
Simulation time 66974821 ps
CPU time 0.69 seconds
Started Jun 10 05:08:46 PM PDT 24
Finished Jun 10 05:08:47 PM PDT 24
Peak memory 204924 kb
Host smart-209c1623-41e2-4dd2-9041-4c3dea39252f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2839770044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2839770044
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1643320270
Short name T261
Test name
Test status
Simulation time 131618107 ps
CPU time 1.51 seconds
Started Jun 10 05:08:45 PM PDT 24
Finished Jun 10 05:08:47 PM PDT 24
Peak memory 213416 kb
Host smart-f3af6b4e-497b-41aa-ac6d-4148a174cc64
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1643320270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1643320270
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3588184231
Short name T2145
Test name
Test status
Simulation time 375064967 ps
CPU time 2.82 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 205064 kb
Host smart-0d3c4d65-2f36-426e-bb0d-77e7ce324a49
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3588184231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3588184231
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1420850420
Short name T108
Test name
Test status
Simulation time 213158920 ps
CPU time 2.07 seconds
Started Jun 10 05:08:46 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 205152 kb
Host smart-deaf722d-c743-40a9-81a4-b7972742030f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1420850420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1420850420
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4077399518
Short name T288
Test name
Test status
Simulation time 314079356 ps
CPU time 2.57 seconds
Started Jun 10 05:08:44 PM PDT 24
Finished Jun 10 05:08:47 PM PDT 24
Peak memory 205096 kb
Host smart-7a12a290-ac0c-4a88-98e4-099e04377d51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4077399518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.4077399518
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.628226488
Short name T2181
Test name
Test status
Simulation time 51691584 ps
CPU time 0.74 seconds
Started Jun 10 05:09:02 PM PDT 24
Finished Jun 10 05:09:04 PM PDT 24
Peak memory 204948 kb
Host smart-fb6ad837-c4ee-4a3a-8f37-c50466cbe3c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=628226488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.628226488
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1303982248
Short name T280
Test name
Test status
Simulation time 71930262 ps
CPU time 0.7 seconds
Started Jun 10 05:09:09 PM PDT 24
Finished Jun 10 05:09:10 PM PDT 24
Peak memory 204956 kb
Host smart-ab679eb8-3a17-47ea-89a4-d3fae6b0313b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1303982248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1303982248
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.321436981
Short name T2124
Test name
Test status
Simulation time 102122370 ps
CPU time 0.76 seconds
Started Jun 10 05:09:10 PM PDT 24
Finished Jun 10 05:09:11 PM PDT 24
Peak memory 204912 kb
Host smart-1a5ed64c-a7ec-456a-b7af-bbb8fa83bb07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=321436981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.321436981
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1629576723
Short name T277
Test name
Test status
Simulation time 46050569 ps
CPU time 0.71 seconds
Started Jun 10 05:09:02 PM PDT 24
Finished Jun 10 05:09:03 PM PDT 24
Peak memory 204884 kb
Host smart-b626f2ee-483c-4ecb-ad18-cb4bcb765203
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1629576723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1629576723
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1037259093
Short name T116
Test name
Test status
Simulation time 53507081 ps
CPU time 0.69 seconds
Started Jun 10 05:09:00 PM PDT 24
Finished Jun 10 05:09:01 PM PDT 24
Peak memory 204920 kb
Host smart-fdaa75e8-a94d-4bcd-ad5f-95537438ba09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1037259093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1037259093
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2735397817
Short name T117
Test name
Test status
Simulation time 40490491 ps
CPU time 0.73 seconds
Started Jun 10 05:09:10 PM PDT 24
Finished Jun 10 05:09:12 PM PDT 24
Peak memory 204856 kb
Host smart-2a06a305-1f7c-4476-bb96-51a9d4aa8d02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2735397817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2735397817
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1235626142
Short name T2172
Test name
Test status
Simulation time 67875720 ps
CPU time 0.77 seconds
Started Jun 10 05:09:09 PM PDT 24
Finished Jun 10 05:09:10 PM PDT 24
Peak memory 204936 kb
Host smart-f4f2e5ef-e99f-4e73-a6c7-9c46962a85b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1235626142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1235626142
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2875665499
Short name T284
Test name
Test status
Simulation time 34209170 ps
CPU time 0.69 seconds
Started Jun 10 05:09:00 PM PDT 24
Finished Jun 10 05:09:01 PM PDT 24
Peak memory 204892 kb
Host smart-32b120c1-4c58-4723-aa70-9dfcf9f0d8e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2875665499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2875665499
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2364743904
Short name T2136
Test name
Test status
Simulation time 44204234 ps
CPU time 0.73 seconds
Started Jun 10 05:09:02 PM PDT 24
Finished Jun 10 05:09:03 PM PDT 24
Peak memory 205192 kb
Host smart-784b320e-5657-4033-b945-29b9507d6030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2364743904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2364743904
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3367389582
Short name T120
Test name
Test status
Simulation time 103240974 ps
CPU time 0.75 seconds
Started Jun 10 05:09:03 PM PDT 24
Finished Jun 10 05:09:04 PM PDT 24
Peak memory 204920 kb
Host smart-b0df2d10-2870-43f2-9a5d-9827e93c1c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3367389582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3367389582
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.19530963
Short name T2177
Test name
Test status
Simulation time 158384276 ps
CPU time 3.39 seconds
Started Jun 10 05:08:57 PM PDT 24
Finished Jun 10 05:09:01 PM PDT 24
Peak memory 205384 kb
Host smart-1316cc52-913c-4936-928b-58072c212e82
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=19530963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.19530963
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3378299666
Short name T262
Test name
Test status
Simulation time 1675667376 ps
CPU time 8.31 seconds
Started Jun 10 05:08:46 PM PDT 24
Finished Jun 10 05:08:55 PM PDT 24
Peak memory 205104 kb
Host smart-9862998c-9e53-4799-8004-09f72d777393
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3378299666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3378299666
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1720388537
Short name T2121
Test name
Test status
Simulation time 73291716 ps
CPU time 0.78 seconds
Started Jun 10 05:08:51 PM PDT 24
Finished Jun 10 05:08:52 PM PDT 24
Peak memory 204928 kb
Host smart-2f3d3272-eed2-4a2b-8ddc-cb3260747ef4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1720388537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1720388537
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2496043135
Short name T2209
Test name
Test status
Simulation time 181014281 ps
CPU time 2.48 seconds
Started Jun 10 05:08:48 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 213464 kb
Host smart-9b056b10-c9e7-4cdd-b33f-e710f0d2687f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496043135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2496043135
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1352975810
Short name T259
Test name
Test status
Simulation time 63501089 ps
CPU time 1 seconds
Started Jun 10 05:08:45 PM PDT 24
Finished Jun 10 05:08:46 PM PDT 24
Peak memory 205052 kb
Host smart-6351bb2f-5e66-4c5c-b94e-66e931ce2ad4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1352975810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1352975810
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2481878813
Short name T118
Test name
Test status
Simulation time 112780517 ps
CPU time 0.76 seconds
Started Jun 10 05:08:49 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 205156 kb
Host smart-254f9ad1-5769-4332-9e2a-b4913d96453d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2481878813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2481878813
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2858893549
Short name T257
Test name
Test status
Simulation time 176464109 ps
CPU time 2.27 seconds
Started Jun 10 05:08:45 PM PDT 24
Finished Jun 10 05:08:47 PM PDT 24
Peak memory 213352 kb
Host smart-84becbb8-86a0-449b-a872-b9bceb395658
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2858893549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2858893549
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1215191044
Short name T2180
Test name
Test status
Simulation time 221801986 ps
CPU time 4.24 seconds
Started Jun 10 05:08:48 PM PDT 24
Finished Jun 10 05:08:53 PM PDT 24
Peak memory 204992 kb
Host smart-9af4174d-535f-4907-bb14-127186a56c15
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1215191044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1215191044
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.322595843
Short name T112
Test name
Test status
Simulation time 178351657 ps
CPU time 1.38 seconds
Started Jun 10 05:08:51 PM PDT 24
Finished Jun 10 05:08:53 PM PDT 24
Peak memory 205208 kb
Host smart-cc5bcc81-64d8-48e0-bdc3-0a9bf65883ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=322595843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.322595843
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2752309167
Short name T236
Test name
Test status
Simulation time 109470146 ps
CPU time 2.1 seconds
Started Jun 10 05:08:46 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 205252 kb
Host smart-79bb60dc-0e97-4c81-8c95-c9daf78cd4c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2752309167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2752309167
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2345879709
Short name T2119
Test name
Test status
Simulation time 444710740 ps
CPU time 2.91 seconds
Started Jun 10 05:08:52 PM PDT 24
Finished Jun 10 05:08:55 PM PDT 24
Peak memory 205260 kb
Host smart-5796b0e8-68e2-4602-aa73-2d482b52ecfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2345879709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2345879709
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.4206201301
Short name T2203
Test name
Test status
Simulation time 53216290 ps
CPU time 0.73 seconds
Started Jun 10 05:09:01 PM PDT 24
Finished Jun 10 05:09:02 PM PDT 24
Peak memory 204916 kb
Host smart-53be440b-0dd0-4c17-b240-eec4b633cd17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4206201301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.4206201301
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1315461281
Short name T2158
Test name
Test status
Simulation time 56595314 ps
CPU time 0.68 seconds
Started Jun 10 05:08:59 PM PDT 24
Finished Jun 10 05:09:00 PM PDT 24
Peak memory 204940 kb
Host smart-be7dd12f-cd0b-40ba-9ced-e225dd011a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1315461281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1315461281
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2284490776
Short name T276
Test name
Test status
Simulation time 64314867 ps
CPU time 0.71 seconds
Started Jun 10 05:09:09 PM PDT 24
Finished Jun 10 05:09:10 PM PDT 24
Peak memory 204912 kb
Host smart-14d2d1f1-3918-43c9-a3c3-5f78a526f356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2284490776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2284490776
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.918195522
Short name T2146
Test name
Test status
Simulation time 123671147 ps
CPU time 0.74 seconds
Started Jun 10 05:09:00 PM PDT 24
Finished Jun 10 05:09:01 PM PDT 24
Peak memory 204932 kb
Host smart-9c922d03-24bf-4fe6-bd6b-d335fc4a47d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=918195522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.918195522
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3581105516
Short name T2175
Test name
Test status
Simulation time 46863365 ps
CPU time 0.69 seconds
Started Jun 10 05:09:02 PM PDT 24
Finished Jun 10 05:09:03 PM PDT 24
Peak memory 204900 kb
Host smart-e8dab5ee-f93c-4628-a93f-fc071703a78b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3581105516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3581105516
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1068876727
Short name T2159
Test name
Test status
Simulation time 43681191 ps
CPU time 0.69 seconds
Started Jun 10 05:09:05 PM PDT 24
Finished Jun 10 05:09:06 PM PDT 24
Peak memory 204900 kb
Host smart-421a2e9c-c4ee-4e66-9565-efe0507946fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1068876727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1068876727
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3433918786
Short name T2192
Test name
Test status
Simulation time 48003812 ps
CPU time 0.73 seconds
Started Jun 10 05:09:11 PM PDT 24
Finished Jun 10 05:09:13 PM PDT 24
Peak memory 204856 kb
Host smart-35bd7f3a-1460-44d8-9b07-52e68180516b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3433918786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3433918786
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1374943349
Short name T2191
Test name
Test status
Simulation time 75485081 ps
CPU time 0.71 seconds
Started Jun 10 05:09:01 PM PDT 24
Finished Jun 10 05:09:03 PM PDT 24
Peak memory 204888 kb
Host smart-5305aeb6-9bc9-4512-9f0c-0af7cf545361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1374943349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1374943349
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3038029645
Short name T2206
Test name
Test status
Simulation time 50269434 ps
CPU time 0.68 seconds
Started Jun 10 05:09:02 PM PDT 24
Finished Jun 10 05:09:03 PM PDT 24
Peak memory 204908 kb
Host smart-dba91fc1-008e-4649-be71-f925f88aa30f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3038029645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3038029645
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4069572443
Short name T2130
Test name
Test status
Simulation time 42579687 ps
CPU time 0.67 seconds
Started Jun 10 05:09:02 PM PDT 24
Finished Jun 10 05:09:03 PM PDT 24
Peak memory 204908 kb
Host smart-28397d94-7b06-4e1b-b51c-4bc09d06d0c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4069572443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.4069572443
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1448084619
Short name T245
Test name
Test status
Simulation time 106790894 ps
CPU time 1.78 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:50 PM PDT 24
Peak memory 213448 kb
Host smart-0cb5ee1c-a81f-46f3-bce8-4f87a39752cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448084619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1448084619
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.345737387
Short name T2141
Test name
Test status
Simulation time 94001120 ps
CPU time 1.1 seconds
Started Jun 10 05:08:54 PM PDT 24
Finished Jun 10 05:08:56 PM PDT 24
Peak memory 205420 kb
Host smart-cec4d081-4ba8-4a2a-92b6-db6d09e4c050
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=345737387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.345737387
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1032334977
Short name T2163
Test name
Test status
Simulation time 39378562 ps
CPU time 0.68 seconds
Started Jun 10 05:08:44 PM PDT 24
Finished Jun 10 05:08:45 PM PDT 24
Peak memory 204876 kb
Host smart-2f540a7a-e6f2-4626-8377-3577a8a83cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1032334977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1032334977
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1423829481
Short name T2116
Test name
Test status
Simulation time 45429727 ps
CPU time 1.08 seconds
Started Jun 10 05:08:46 PM PDT 24
Finished Jun 10 05:08:48 PM PDT 24
Peak memory 205276 kb
Host smart-26bdab00-f2ae-4d16-84b0-a794dbe383f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1423829481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1423829481
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2848260982
Short name T2155
Test name
Test status
Simulation time 308198521 ps
CPU time 3.79 seconds
Started Jun 10 05:08:50 PM PDT 24
Finished Jun 10 05:08:55 PM PDT 24
Peak memory 221036 kb
Host smart-2175b556-a2c4-4384-9071-d98997f6d43b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2848260982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2848260982
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2199300156
Short name T247
Test name
Test status
Simulation time 738807863 ps
CPU time 3.29 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 205228 kb
Host smart-261a8718-04d9-4d73-8e40-3949873fbbb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2199300156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2199300156
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2245030600
Short name T2186
Test name
Test status
Simulation time 109939949 ps
CPU time 1.69 seconds
Started Jun 10 05:08:52 PM PDT 24
Finished Jun 10 05:08:54 PM PDT 24
Peak memory 213444 kb
Host smart-1a403d21-ec1e-43c2-8209-77922768cfd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245030600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2245030600
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1429831747
Short name T255
Test name
Test status
Simulation time 55289101 ps
CPU time 0.79 seconds
Started Jun 10 05:08:48 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 204980 kb
Host smart-4da21d20-29fa-4f8e-97c1-8a2908f98250
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1429831747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1429831747
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3955082020
Short name T278
Test name
Test status
Simulation time 46589390 ps
CPU time 0.76 seconds
Started Jun 10 05:08:45 PM PDT 24
Finished Jun 10 05:08:46 PM PDT 24
Peak memory 204924 kb
Host smart-ed8c452f-a5c8-488d-af6b-6e5aefae9e9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3955082020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3955082020
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3433866956
Short name T2197
Test name
Test status
Simulation time 64386969 ps
CPU time 1.11 seconds
Started Jun 10 05:08:51 PM PDT 24
Finished Jun 10 05:08:53 PM PDT 24
Peak memory 205200 kb
Host smart-05424ca9-0d26-445f-8538-7f47ba92ffe5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3433866956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3433866956
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1654888936
Short name T235
Test name
Test status
Simulation time 324416849 ps
CPU time 3.81 seconds
Started Jun 10 05:08:50 PM PDT 24
Finished Jun 10 05:08:54 PM PDT 24
Peak memory 213456 kb
Host smart-65afaf95-71a3-4cc4-94e3-936482d10732
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1654888936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1654888936
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2972949903
Short name T289
Test name
Test status
Simulation time 2169291161 ps
CPU time 6.05 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:53 PM PDT 24
Peak memory 205320 kb
Host smart-c28462e9-d887-437d-bbc0-49a21638e0b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2972949903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2972949903
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.564015076
Short name T243
Test name
Test status
Simulation time 96916767 ps
CPU time 1.45 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 213468 kb
Host smart-e85cb3e5-d957-46da-bee6-4a5992ea7835
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564015076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.564015076
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2278979200
Short name T2126
Test name
Test status
Simulation time 67335195 ps
CPU time 0.98 seconds
Started Jun 10 05:08:50 PM PDT 24
Finished Jun 10 05:08:52 PM PDT 24
Peak memory 205220 kb
Host smart-0e3db19a-60a1-41fc-aa24-15f80f5bf358
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2278979200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2278979200
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2841707545
Short name T274
Test name
Test status
Simulation time 82199598 ps
CPU time 0.72 seconds
Started Jun 10 05:08:46 PM PDT 24
Finished Jun 10 05:08:47 PM PDT 24
Peak memory 204944 kb
Host smart-39b3ef5b-9fbd-49ad-ab2d-093dc37d466f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2841707545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2841707545
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3441149584
Short name T224
Test name
Test status
Simulation time 102300586 ps
CPU time 1.08 seconds
Started Jun 10 05:08:48 PM PDT 24
Finished Jun 10 05:08:50 PM PDT 24
Peak memory 205236 kb
Host smart-5bfd1928-29b4-48d0-b872-cf1c4aa8b7f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3441149584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3441149584
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1451605436
Short name T2205
Test name
Test status
Simulation time 102040187 ps
CPU time 2.8 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 220908 kb
Host smart-1257d6a5-4b05-4fe3-9a31-d96420f23a08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1451605436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1451605436
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3086281819
Short name T2193
Test name
Test status
Simulation time 831069410 ps
CPU time 3.02 seconds
Started Jun 10 05:08:49 PM PDT 24
Finished Jun 10 05:08:52 PM PDT 24
Peak memory 205248 kb
Host smart-1e9d6d0d-ae99-4d5f-b644-811a2101d540
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3086281819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3086281819
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.251226247
Short name T2168
Test name
Test status
Simulation time 65806705 ps
CPU time 1.21 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:48 PM PDT 24
Peak memory 215036 kb
Host smart-9208936d-9ec0-4bb5-a279-5a9951771930
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251226247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev
_csr_mem_rw_with_rand_reset.251226247
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1735900804
Short name T2173
Test name
Test status
Simulation time 116107611 ps
CPU time 1.1 seconds
Started Jun 10 05:08:50 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 205116 kb
Host smart-689ccf24-43e2-4ae6-9f7b-6f6294923303
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1735900804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1735900804
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1212935487
Short name T2169
Test name
Test status
Simulation time 113405335 ps
CPU time 0.74 seconds
Started Jun 10 05:08:55 PM PDT 24
Finished Jun 10 05:08:56 PM PDT 24
Peak memory 204960 kb
Host smart-0dfeff43-eb6a-4918-a106-3c178d4362a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1212935487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1212935487
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.570727504
Short name T2171
Test name
Test status
Simulation time 182498068 ps
CPU time 1.63 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 205180 kb
Host smart-1cb028d2-63be-4533-9a91-b6d9714108b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=570727504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.570727504
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.465349354
Short name T2147
Test name
Test status
Simulation time 106357102 ps
CPU time 2.09 seconds
Started Jun 10 05:08:49 PM PDT 24
Finished Jun 10 05:08:52 PM PDT 24
Peak memory 205284 kb
Host smart-c126ac0a-268f-4640-a7aa-3dbd6f4ea593
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=465349354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.465349354
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2519588571
Short name T2176
Test name
Test status
Simulation time 192785492 ps
CPU time 1.82 seconds
Started Jun 10 05:08:48 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 221604 kb
Host smart-3e6dff97-b3b3-4b25-9a81-426fe83c32fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519588571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2519588571
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2938396119
Short name T264
Test name
Test status
Simulation time 85426552 ps
CPU time 0.98 seconds
Started Jun 10 05:08:49 PM PDT 24
Finished Jun 10 05:08:51 PM PDT 24
Peak memory 205064 kb
Host smart-5e85e778-c82b-4ae6-bd2e-09244be4c40b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2938396119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2938396119
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3215605891
Short name T2210
Test name
Test status
Simulation time 44115721 ps
CPU time 0.66 seconds
Started Jun 10 05:08:54 PM PDT 24
Finished Jun 10 05:08:56 PM PDT 24
Peak memory 204908 kb
Host smart-a5a719f0-d78c-4a62-8068-49654d29b18d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3215605891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3215605891
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.571798308
Short name T2162
Test name
Test status
Simulation time 175808983 ps
CPU time 1.5 seconds
Started Jun 10 05:08:52 PM PDT 24
Finished Jun 10 05:08:54 PM PDT 24
Peak memory 205256 kb
Host smart-12116870-7fba-4eee-97b7-a046b1ec9deb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=571798308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.571798308
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.980903990
Short name T2160
Test name
Test status
Simulation time 178297240 ps
CPU time 2.31 seconds
Started Jun 10 05:08:47 PM PDT 24
Finished Jun 10 05:08:50 PM PDT 24
Peak memory 220844 kb
Host smart-dbd91292-18a0-402e-910e-bf1a0728a9d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=980903990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.980903990
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1299281990
Short name T2204
Test name
Test status
Simulation time 358798086 ps
CPU time 2.67 seconds
Started Jun 10 05:08:46 PM PDT 24
Finished Jun 10 05:08:49 PM PDT 24
Peak memory 205264 kb
Host smart-bf267b34-818f-4eb6-a47f-67ca7c97719d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1299281990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1299281990
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.3997644944
Short name T701
Test name
Test status
Simulation time 263208487 ps
CPU time 0.96 seconds
Started Jun 10 05:24:09 PM PDT 24
Finished Jun 10 05:24:11 PM PDT 24
Peak memory 205020 kb
Host smart-52cc96eb-38fe-4969-8692-ba3b12037236
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3997644944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.3997644944
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.2708107102
Short name T351
Test name
Test status
Simulation time 210308477 ps
CPU time 0.82 seconds
Started Jun 10 05:24:13 PM PDT 24
Finished Jun 10 05:24:14 PM PDT 24
Peak memory 205056 kb
Host smart-49cad595-ffd6-4812-a96a-4676f79532c5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2708107102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.2708107102
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.3927957925
Short name T1690
Test name
Test status
Simulation time 183254172 ps
CPU time 0.87 seconds
Started Jun 10 05:24:06 PM PDT 24
Finished Jun 10 05:24:08 PM PDT 24
Peak memory 204984 kb
Host smart-82f05527-0143-4df8-8ea8-a22cc52a63d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39279
57925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.3927957925
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.3829565673
Short name T570
Test name
Test status
Simulation time 3446944462 ps
CPU time 4.33 seconds
Started Jun 10 05:24:03 PM PDT 24
Finished Jun 10 05:24:08 PM PDT 24
Peak memory 204948 kb
Host smart-4e88ac80-8856-460f-9540-94e8c558f058
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3829565673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.3829565673
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.3035063478
Short name T225
Test name
Test status
Simulation time 13321824150 ps
CPU time 15.04 seconds
Started Jun 10 05:24:07 PM PDT 24
Finished Jun 10 05:24:22 PM PDT 24
Peak memory 205272 kb
Host smart-a505eee0-0757-4aed-9de4-1a2562895595
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3035063478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.3035063478
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3877032965
Short name T542
Test name
Test status
Simulation time 174425370 ps
CPU time 0.82 seconds
Started Jun 10 05:24:07 PM PDT 24
Finished Jun 10 05:24:08 PM PDT 24
Peak memory 205012 kb
Host smart-8b7233f8-2259-4abb-a95c-401557e91da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38770
32965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3877032965
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.3713049469
Short name T57
Test name
Test status
Simulation time 166813287 ps
CPU time 0.82 seconds
Started Jun 10 05:24:07 PM PDT 24
Finished Jun 10 05:24:08 PM PDT 24
Peak memory 205064 kb
Host smart-5c31b295-65ad-4d8f-a296-db627a52e827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37130
49469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.3713049469
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2175279288
Short name T2065
Test name
Test status
Simulation time 797987978 ps
CPU time 1.98 seconds
Started Jun 10 05:24:06 PM PDT 24
Finished Jun 10 05:24:08 PM PDT 24
Peak memory 205100 kb
Host smart-26549d3f-6db4-46aa-90e8-82e0f9c02e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21752
79288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2175279288
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.1953372810
Short name T557
Test name
Test status
Simulation time 141333620 ps
CPU time 0.8 seconds
Started Jun 10 05:24:10 PM PDT 24
Finished Jun 10 05:24:11 PM PDT 24
Peak memory 204972 kb
Host smart-806c4297-36d9-4e75-a4fa-00a41da2583d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19533
72810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.1953372810
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.611160323
Short name T889
Test name
Test status
Simulation time 31034212 ps
CPU time 0.67 seconds
Started Jun 10 05:24:06 PM PDT 24
Finished Jun 10 05:24:07 PM PDT 24
Peak memory 205016 kb
Host smart-e5992f3d-d004-4c1f-a9c7-3289597ffb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61116
0323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.611160323
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.1085425467
Short name T1251
Test name
Test status
Simulation time 725126930 ps
CPU time 1.86 seconds
Started Jun 10 05:24:04 PM PDT 24
Finished Jun 10 05:24:07 PM PDT 24
Peak memory 205096 kb
Host smart-8cd57554-c0bd-40b5-9fdf-5f27a2cdf79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10854
25467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.1085425467
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2341266043
Short name T1988
Test name
Test status
Simulation time 171194420 ps
CPU time 1.39 seconds
Started Jun 10 05:24:03 PM PDT 24
Finished Jun 10 05:24:05 PM PDT 24
Peak memory 205120 kb
Host smart-37c0c884-f245-4b24-bb68-c98d3311f597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23412
66043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2341266043
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1412183940
Short name T1717
Test name
Test status
Simulation time 223890012 ps
CPU time 0.94 seconds
Started Jun 10 05:24:11 PM PDT 24
Finished Jun 10 05:24:12 PM PDT 24
Peak memory 205036 kb
Host smart-96d5ba18-ff73-41ec-bc2a-8d3265525909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14121
83940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1412183940
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.1726035473
Short name T1448
Test name
Test status
Simulation time 145191120 ps
CPU time 0.79 seconds
Started Jun 10 05:24:13 PM PDT 24
Finished Jun 10 05:24:15 PM PDT 24
Peak memory 205088 kb
Host smart-3fd1c9b9-5ab2-439b-967a-180e0f2635cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17260
35473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.1726035473
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.3735468123
Short name T2055
Test name
Test status
Simulation time 178452363 ps
CPU time 0.86 seconds
Started Jun 10 05:24:06 PM PDT 24
Finished Jun 10 05:24:07 PM PDT 24
Peak memory 205012 kb
Host smart-2d33c5f9-596b-493f-889c-08ae85d5c182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37354
68123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3735468123
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3708233097
Short name T2014
Test name
Test status
Simulation time 229727415 ps
CPU time 0.91 seconds
Started Jun 10 05:24:03 PM PDT 24
Finished Jun 10 05:24:05 PM PDT 24
Peak memory 204848 kb
Host smart-185ad5d5-7b05-4010-be17-c7c3dc258dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37082
33097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3708233097
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.483829676
Short name T1472
Test name
Test status
Simulation time 3334136929 ps
CPU time 3.93 seconds
Started Jun 10 05:24:07 PM PDT 24
Finished Jun 10 05:24:12 PM PDT 24
Peak memory 205124 kb
Host smart-d6bc6954-3c14-49b5-9611-73dd83c47f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48382
9676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.483829676
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3725720249
Short name T808
Test name
Test status
Simulation time 234902209 ps
CPU time 0.91 seconds
Started Jun 10 05:24:02 PM PDT 24
Finished Jun 10 05:24:04 PM PDT 24
Peak memory 205048 kb
Host smart-e20153c0-10b8-4f2c-8ba7-773e620b419c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37257
20249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3725720249
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.999179038
Short name T1290
Test name
Test status
Simulation time 13608265918 ps
CPU time 389.14 seconds
Started Jun 10 05:24:09 PM PDT 24
Finished Jun 10 05:30:38 PM PDT 24
Peak memory 205188 kb
Host smart-d7a962cb-6ef6-4eb2-a4e7-40aac82b91c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99917
9038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.999179038
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.272203574
Short name T1805
Test name
Test status
Simulation time 159152750 ps
CPU time 0.81 seconds
Started Jun 10 05:24:08 PM PDT 24
Finished Jun 10 05:24:09 PM PDT 24
Peak memory 205004 kb
Host smart-c4aae861-eefa-443f-9d8e-cf1c20760ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27220
3574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.272203574
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2978786319
Short name T1354
Test name
Test status
Simulation time 247339125 ps
CPU time 0.95 seconds
Started Jun 10 05:24:06 PM PDT 24
Finished Jun 10 05:24:08 PM PDT 24
Peak memory 205028 kb
Host smart-a86a7246-75c5-4e0a-bf4e-c2c69291a381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29787
86319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2978786319
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.2845880129
Short name T1592
Test name
Test status
Simulation time 267772278 ps
CPU time 0.95 seconds
Started Jun 10 05:24:03 PM PDT 24
Finished Jun 10 05:24:04 PM PDT 24
Peak memory 205016 kb
Host smart-08a2b34e-1e24-4f19-9213-f10698ea7568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28458
80129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2845880129
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.1681139703
Short name T1128
Test name
Test status
Simulation time 148585694 ps
CPU time 0.81 seconds
Started Jun 10 05:24:06 PM PDT 24
Finished Jun 10 05:24:07 PM PDT 24
Peak memory 205092 kb
Host smart-b6153a91-4f37-4757-ac33-e79c259b3add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16811
39703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.1681139703
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2620804945
Short name T676
Test name
Test status
Simulation time 244105151 ps
CPU time 0.9 seconds
Started Jun 10 05:24:09 PM PDT 24
Finished Jun 10 05:24:11 PM PDT 24
Peak memory 205008 kb
Host smart-149ad699-8350-4a77-8f22-f278ed5b1873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26208
04945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2620804945
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1364192609
Short name T1247
Test name
Test status
Simulation time 263050622 ps
CPU time 0.91 seconds
Started Jun 10 05:24:07 PM PDT 24
Finished Jun 10 05:24:08 PM PDT 24
Peak memory 204976 kb
Host smart-b2f6a851-408f-4403-8c97-998072ea2f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13641
92609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1364192609
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3203878280
Short name T903
Test name
Test status
Simulation time 145861089 ps
CPU time 0.79 seconds
Started Jun 10 05:24:11 PM PDT 24
Finished Jun 10 05:24:12 PM PDT 24
Peak memory 204992 kb
Host smart-310ebd54-dd77-4120-b129-6276cd655278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32038
78280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3203878280
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1704522456
Short name T1199
Test name
Test status
Simulation time 56193817 ps
CPU time 0.68 seconds
Started Jun 10 05:24:07 PM PDT 24
Finished Jun 10 05:24:08 PM PDT 24
Peak memory 204972 kb
Host smart-535efc7e-5125-416c-b556-fb1b0e70e6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17045
22456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1704522456
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.352795803
Short name T588
Test name
Test status
Simulation time 15609559202 ps
CPU time 35.3 seconds
Started Jun 10 05:24:09 PM PDT 24
Finished Jun 10 05:24:44 PM PDT 24
Peak memory 205164 kb
Host smart-5161849c-d755-4232-bb9e-c7824b36c130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35279
5803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.352795803
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3160653031
Short name T1706
Test name
Test status
Simulation time 213819692 ps
CPU time 0.86 seconds
Started Jun 10 05:24:05 PM PDT 24
Finished Jun 10 05:24:06 PM PDT 24
Peak memory 205000 kb
Host smart-20806712-ace8-414d-8b79-2e9c9f32fe7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31606
53031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3160653031
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.2193918361
Short name T698
Test name
Test status
Simulation time 147006090 ps
CPU time 0.79 seconds
Started Jun 10 05:24:12 PM PDT 24
Finished Jun 10 05:24:14 PM PDT 24
Peak memory 205024 kb
Host smart-f5a9149d-0fcd-4c98-b507-bb08db6e546a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21939
18361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.2193918361
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2227884847
Short name T103
Test name
Test status
Simulation time 647444491 ps
CPU time 1.59 seconds
Started Jun 10 05:24:09 PM PDT 24
Finished Jun 10 05:24:11 PM PDT 24
Peak memory 222464 kb
Host smart-196f560b-3279-4158-9155-a35c1f4f8fb9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2227884847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2227884847
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.2032019936
Short name T2087
Test name
Test status
Simulation time 153346184 ps
CPU time 0.81 seconds
Started Jun 10 05:24:11 PM PDT 24
Finished Jun 10 05:24:13 PM PDT 24
Peak memory 205032 kb
Host smart-1a30edd7-b67c-42b8-9f9e-29f8c155b737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20320
19936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.2032019936
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.4027505616
Short name T369
Test name
Test status
Simulation time 196570507 ps
CPU time 0.85 seconds
Started Jun 10 05:24:08 PM PDT 24
Finished Jun 10 05:24:09 PM PDT 24
Peak memory 204992 kb
Host smart-0fc5e82f-47a2-4e85-83f5-4e4511442374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40275
05616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.4027505616
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3729100606
Short name T730
Test name
Test status
Simulation time 183491955 ps
CPU time 0.81 seconds
Started Jun 10 05:24:10 PM PDT 24
Finished Jun 10 05:24:11 PM PDT 24
Peak memory 204988 kb
Host smart-753fa5ec-2d84-4cf6-823a-31d105630ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37291
00606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3729100606
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.4243456818
Short name T1942
Test name
Test status
Simulation time 7702296050 ps
CPU time 55.24 seconds
Started Jun 10 05:24:09 PM PDT 24
Finished Jun 10 05:25:05 PM PDT 24
Peak memory 205132 kb
Host smart-cd403364-f6ac-4a73-927e-0deec946332e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42434
56818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.4243456818
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.72049338
Short name T1719
Test name
Test status
Simulation time 30983544965 ps
CPU time 192.89 seconds
Started Jun 10 05:24:09 PM PDT 24
Finished Jun 10 05:27:22 PM PDT 24
Peak memory 205204 kb
Host smart-e5e57702-f51f-4e34-b35f-b80858e4f933
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72049338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus
_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_tr
affic.72049338
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.3994838933
Short name T847
Test name
Test status
Simulation time 286091661 ps
CPU time 1.06 seconds
Started Jun 10 05:24:23 PM PDT 24
Finished Jun 10 05:24:25 PM PDT 24
Peak memory 205008 kb
Host smart-5ab6c824-44d9-4069-973e-bcd547d418c1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3994838933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.3994838933
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.3578342164
Short name T689
Test name
Test status
Simulation time 156045676 ps
CPU time 0.84 seconds
Started Jun 10 05:24:15 PM PDT 24
Finished Jun 10 05:24:16 PM PDT 24
Peak memory 204856 kb
Host smart-79cd70f3-5941-41d8-a91b-9eb96ce16f3d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3578342164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.3578342164
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.1043005047
Short name T164
Test name
Test status
Simulation time 249615639 ps
CPU time 0.93 seconds
Started Jun 10 05:24:18 PM PDT 24
Finished Jun 10 05:24:19 PM PDT 24
Peak memory 205008 kb
Host smart-e0664bd5-538c-42bf-a97d-857784e82596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10430
05047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.1043005047
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1328078900
Short name T1759
Test name
Test status
Simulation time 3539359747 ps
CPU time 5.42 seconds
Started Jun 10 05:24:16 PM PDT 24
Finished Jun 10 05:24:22 PM PDT 24
Peak memory 205056 kb
Host smart-676f681a-984d-436e-b166-6c184119a6f5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1328078900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.1328078900
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.906395247
Short name T1255
Test name
Test status
Simulation time 13397259510 ps
CPU time 13.65 seconds
Started Jun 10 05:24:16 PM PDT 24
Finished Jun 10 05:24:30 PM PDT 24
Peak memory 205104 kb
Host smart-4827df12-0769-4cfc-8c18-f0557f3549f4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=906395247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.906395247
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.3832022087
Short name T601
Test name
Test status
Simulation time 23391894022 ps
CPU time 27.48 seconds
Started Jun 10 05:24:13 PM PDT 24
Finished Jun 10 05:24:41 PM PDT 24
Peak memory 205184 kb
Host smart-f62911c6-b99f-47a6-b1e4-faeaa2d7d7a5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3832022087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.3832022087
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.909209090
Short name T380
Test name
Test status
Simulation time 154157064 ps
CPU time 0.85 seconds
Started Jun 10 05:24:14 PM PDT 24
Finished Jun 10 05:24:16 PM PDT 24
Peak memory 205044 kb
Host smart-c357315c-ac2b-46a6-b1d5-4e2e0efcbac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90920
9090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.909209090
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1076125370
Short name T2079
Test name
Test status
Simulation time 150015644 ps
CPU time 0.77 seconds
Started Jun 10 05:24:15 PM PDT 24
Finished Jun 10 05:24:17 PM PDT 24
Peak memory 205016 kb
Host smart-9c13c1af-b37a-44d3-ab6b-fa51499df8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10761
25370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1076125370
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1076273615
Short name T564
Test name
Test status
Simulation time 493128137 ps
CPU time 1.4 seconds
Started Jun 10 05:24:18 PM PDT 24
Finished Jun 10 05:24:20 PM PDT 24
Peak memory 205016 kb
Host smart-d904a187-67c7-4c79-aa49-a6c8c7673693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10762
73615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1076273615
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.4148698804
Short name T1670
Test name
Test status
Simulation time 179482509 ps
CPU time 0.78 seconds
Started Jun 10 05:24:14 PM PDT 24
Finished Jun 10 05:24:15 PM PDT 24
Peak memory 205004 kb
Host smart-760e6625-b9dd-470b-89e5-f879b3e38cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41486
98804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.4148698804
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.4233677566
Short name T1593
Test name
Test status
Simulation time 32753862 ps
CPU time 0.64 seconds
Started Jun 10 05:24:16 PM PDT 24
Finished Jun 10 05:24:17 PM PDT 24
Peak memory 205000 kb
Host smart-caeba6b9-ec8c-4f6e-89e2-ac96ffde5226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42336
77566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.4233677566
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.3535803596
Short name T1582
Test name
Test status
Simulation time 763954633 ps
CPU time 2.02 seconds
Started Jun 10 05:24:17 PM PDT 24
Finished Jun 10 05:24:19 PM PDT 24
Peak memory 204988 kb
Host smart-c6239270-a7a6-47f7-aa03-b2b930256e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35358
03596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.3535803596
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.3166135219
Short name T495
Test name
Test status
Simulation time 310598922 ps
CPU time 1.01 seconds
Started Jun 10 05:24:24 PM PDT 24
Finished Jun 10 05:24:25 PM PDT 24
Peak memory 205000 kb
Host smart-63c3a135-5aca-47e9-b92d-05789781929c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31661
35219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3166135219
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1030296566
Short name T969
Test name
Test status
Simulation time 160676526 ps
CPU time 0.77 seconds
Started Jun 10 05:24:21 PM PDT 24
Finished Jun 10 05:24:22 PM PDT 24
Peak memory 205008 kb
Host smart-8fa6257f-a1e2-46f3-9380-3d30e1956352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10302
96566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1030296566
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.676453660
Short name T1768
Test name
Test status
Simulation time 174670575 ps
CPU time 0.83 seconds
Started Jun 10 05:24:15 PM PDT 24
Finished Jun 10 05:24:17 PM PDT 24
Peak memory 205004 kb
Host smart-6fd45355-e28f-410c-afa2-f6a82884576f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67645
3660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.676453660
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.2730570975
Short name T1262
Test name
Test status
Simulation time 184059728 ps
CPU time 0.85 seconds
Started Jun 10 05:24:12 PM PDT 24
Finished Jun 10 05:24:14 PM PDT 24
Peak memory 205040 kb
Host smart-ccfdc67d-b17c-4a20-b4d9-b95212a7e794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27305
70975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.2730570975
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.3098410978
Short name T527
Test name
Test status
Simulation time 3282779371 ps
CPU time 4.47 seconds
Started Jun 10 05:24:11 PM PDT 24
Finished Jun 10 05:24:17 PM PDT 24
Peak memory 205072 kb
Host smart-48ad028b-d896-4a5d-8777-7d48fce39880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30984
10978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.3098410978
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.4259472021
Short name T2035
Test name
Test status
Simulation time 229685357 ps
CPU time 0.91 seconds
Started Jun 10 05:24:12 PM PDT 24
Finished Jun 10 05:24:13 PM PDT 24
Peak memory 205176 kb
Host smart-bc0b7975-5434-4e7e-b646-0aba880d8300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42594
72021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.4259472021
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.159245442
Short name T1484
Test name
Test status
Simulation time 12235510319 ps
CPU time 340.67 seconds
Started Jun 10 05:24:15 PM PDT 24
Finished Jun 10 05:29:57 PM PDT 24
Peak memory 205208 kb
Host smart-33d0693e-4339-4a0b-b562-3c14355fdc5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15924
5442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.159245442
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2013558456
Short name T1314
Test name
Test status
Simulation time 147636859 ps
CPU time 0.76 seconds
Started Jun 10 05:24:15 PM PDT 24
Finished Jun 10 05:24:16 PM PDT 24
Peak memory 205028 kb
Host smart-659a361c-389c-4fb9-a4d0-797a9d8656d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20135
58456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2013558456
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.2857108695
Short name T80
Test name
Test status
Simulation time 199720153 ps
CPU time 0.91 seconds
Started Jun 10 05:24:13 PM PDT 24
Finished Jun 10 05:24:14 PM PDT 24
Peak memory 204900 kb
Host smart-eb407721-befc-4d6b-be11-ea2947eed27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28571
08695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.2857108695
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3372845882
Short name T911
Test name
Test status
Simulation time 237871224 ps
CPU time 0.92 seconds
Started Jun 10 05:24:15 PM PDT 24
Finished Jun 10 05:24:16 PM PDT 24
Peak memory 205024 kb
Host smart-456b990a-9d49-4d12-8e88-efa9851d357c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33728
45882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3372845882
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1731147858
Short name T1978
Test name
Test status
Simulation time 149233072 ps
CPU time 0.79 seconds
Started Jun 10 05:24:14 PM PDT 24
Finished Jun 10 05:24:15 PM PDT 24
Peak memory 205024 kb
Host smart-a9c6838f-6355-4af4-9ef9-bc7f7f3759ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17311
47858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1731147858
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1086118139
Short name T1209
Test name
Test status
Simulation time 167429260 ps
CPU time 0.8 seconds
Started Jun 10 05:24:19 PM PDT 24
Finished Jun 10 05:24:21 PM PDT 24
Peak memory 204996 kb
Host smart-ddc06c4d-dd2d-4621-aef6-0cf8f1c33ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10861
18139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1086118139
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_eop_single_bit_handling.3752707956
Short name T424
Test name
Test status
Simulation time 168545633 ps
CPU time 0.8 seconds
Started Jun 10 05:24:17 PM PDT 24
Finished Jun 10 05:24:18 PM PDT 24
Peak memory 205064 kb
Host smart-82a49a55-cfc4-4005-9305-09803a13ddfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37527
07956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_eop_single_bit_handling.3752707956
Directory /workspace/1.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.229054119
Short name T1077
Test name
Test status
Simulation time 150238482 ps
CPU time 0.81 seconds
Started Jun 10 05:24:17 PM PDT 24
Finished Jun 10 05:24:18 PM PDT 24
Peak memory 204996 kb
Host smart-f76bc7a4-372b-4edc-8427-776bb498b5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22905
4119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.229054119
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3626961281
Short name T670
Test name
Test status
Simulation time 14885680928 ps
CPU time 33.35 seconds
Started Jun 10 05:24:12 PM PDT 24
Finished Jun 10 05:24:46 PM PDT 24
Peak memory 205256 kb
Host smart-ba4f6fe3-28d0-48c4-bab9-a3e06b9c3904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36269
61281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3626961281
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3119833865
Short name T682
Test name
Test status
Simulation time 182163615 ps
CPU time 0.85 seconds
Started Jun 10 05:24:14 PM PDT 24
Finished Jun 10 05:24:15 PM PDT 24
Peak memory 204996 kb
Host smart-45201a4a-a934-4296-9cee-b0279cc31649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31198
33865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3119833865
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1759547086
Short name T1475
Test name
Test status
Simulation time 217150414 ps
CPU time 0.85 seconds
Started Jun 10 05:24:16 PM PDT 24
Finished Jun 10 05:24:17 PM PDT 24
Peak memory 205004 kb
Host smart-cda27ed6-c033-45d5-bf9b-1b2847355568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17595
47086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1759547086
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.1349722539
Short name T98
Test name
Test status
Simulation time 22795657298 ps
CPU time 185.97 seconds
Started Jun 10 05:24:13 PM PDT 24
Finished Jun 10 05:27:20 PM PDT 24
Peak memory 205164 kb
Host smart-ebff023d-1348-4891-8a1b-abc159b192f5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1349722539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.1349722539
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.3176872055
Short name T602
Test name
Test status
Simulation time 168730080 ps
CPU time 0.88 seconds
Started Jun 10 05:24:19 PM PDT 24
Finished Jun 10 05:24:21 PM PDT 24
Peak memory 205008 kb
Host smart-8b7a7ac2-0450-4486-aaf8-4042ca64f1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31768
72055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.3176872055
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3733475406
Short name T2077
Test name
Test status
Simulation time 138074443 ps
CPU time 0.82 seconds
Started Jun 10 05:24:26 PM PDT 24
Finished Jun 10 05:24:28 PM PDT 24
Peak memory 205004 kb
Host smart-b1c74d59-a445-409c-acf9-db3f9da2e6f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37334
75406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3733475406
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.294115907
Short name T1713
Test name
Test status
Simulation time 144508149 ps
CPU time 0.79 seconds
Started Jun 10 05:24:19 PM PDT 24
Finished Jun 10 05:24:21 PM PDT 24
Peak memory 205008 kb
Host smart-3d0bad9f-aab6-4661-b62f-416da3d7958e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29411
5907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.294115907
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3991324424
Short name T1465
Test name
Test status
Simulation time 158526833 ps
CPU time 0.79 seconds
Started Jun 10 05:24:18 PM PDT 24
Finished Jun 10 05:24:20 PM PDT 24
Peak memory 204916 kb
Host smart-6c4bc3f3-d153-414f-9bee-18dd207d4bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39913
24424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3991324424
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1728789670
Short name T1533
Test name
Test status
Simulation time 166427448 ps
CPU time 0.82 seconds
Started Jun 10 05:24:16 PM PDT 24
Finished Jun 10 05:24:17 PM PDT 24
Peak memory 204992 kb
Host smart-44d626d1-6e0e-4f8c-9323-2864b107262f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17287
89670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1728789670
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.2298719211
Short name T895
Test name
Test status
Simulation time 172380088 ps
CPU time 0.8 seconds
Started Jun 10 05:24:14 PM PDT 24
Finished Jun 10 05:24:15 PM PDT 24
Peak memory 205076 kb
Host smart-e5b75db4-54e2-4c98-8b02-6083253414b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22987
19211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.2298719211
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.3090817646
Short name T662
Test name
Test status
Simulation time 8073521076 ps
CPU time 215.63 seconds
Started Jun 10 05:24:14 PM PDT 24
Finished Jun 10 05:27:50 PM PDT 24
Peak memory 205232 kb
Host smart-b8043b38-f173-43fb-9f43-ce3f01139d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30908
17646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.3090817646
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.3158638963
Short name T777
Test name
Test status
Simulation time 22311217256 ps
CPU time 609.55 seconds
Started Jun 10 05:24:16 PM PDT 24
Finished Jun 10 05:34:26 PM PDT 24
Peak memory 205192 kb
Host smart-9ab49934-8e9e-4fc6-b817-91b780313eec
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158638963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_
traffic.3158638963
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.1852045251
Short name T30
Test name
Test status
Simulation time 237441321 ps
CPU time 0.94 seconds
Started Jun 10 05:25:11 PM PDT 24
Finished Jun 10 05:25:13 PM PDT 24
Peak memory 205048 kb
Host smart-bb2f88a4-6394-4c20-b29c-0d2b82741d76
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1852045251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.1852045251
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.2260155459
Short name T2076
Test name
Test status
Simulation time 155517721 ps
CPU time 0.8 seconds
Started Jun 10 05:25:16 PM PDT 24
Finished Jun 10 05:25:17 PM PDT 24
Peak memory 205020 kb
Host smart-d230e0cc-07af-42ee-832a-61603eb778a0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2260155459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.2260155459
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.10672916
Short name T1351
Test name
Test status
Simulation time 212216785 ps
CPU time 1.07 seconds
Started Jun 10 05:25:13 PM PDT 24
Finished Jun 10 05:25:15 PM PDT 24
Peak memory 205000 kb
Host smart-8515839e-91a7-4c4c-8098-7958c69e81c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10672
916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.10672916
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.3184424740
Short name T729
Test name
Test status
Simulation time 3962169694 ps
CPU time 4.81 seconds
Started Jun 10 05:25:14 PM PDT 24
Finished Jun 10 05:25:20 PM PDT 24
Peak memory 205092 kb
Host smart-30b27155-5487-46e5-bb1b-2c7352686ab4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3184424740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.3184424740
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1268583436
Short name T1194
Test name
Test status
Simulation time 13426427271 ps
CPU time 13.14 seconds
Started Jun 10 05:25:14 PM PDT 24
Finished Jun 10 05:25:28 PM PDT 24
Peak memory 205236 kb
Host smart-62e03d17-5a6c-4391-bfa0-544f279c6f16
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1268583436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1268583436
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.1666310369
Short name T1437
Test name
Test status
Simulation time 23338108502 ps
CPU time 31.37 seconds
Started Jun 10 05:25:10 PM PDT 24
Finished Jun 10 05:25:42 PM PDT 24
Peak memory 205044 kb
Host smart-11637e01-2711-42f5-92b5-2b771a547473
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1666310369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.1666310369
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.341557059
Short name T995
Test name
Test status
Simulation time 156592273 ps
CPU time 0.82 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:25:10 PM PDT 24
Peak memory 204980 kb
Host smart-52314f50-6419-486f-9f1e-ac1089ba499b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34155
7059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.341557059
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.570296161
Short name T575
Test name
Test status
Simulation time 154193850 ps
CPU time 0.8 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:25:10 PM PDT 24
Peak memory 204992 kb
Host smart-f8ae73d7-808d-4357-a687-bb32a7a0cc24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57029
6161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.570296161
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2672649475
Short name T717
Test name
Test status
Simulation time 660071795 ps
CPU time 1.76 seconds
Started Jun 10 05:25:12 PM PDT 24
Finished Jun 10 05:25:14 PM PDT 24
Peak memory 205156 kb
Host smart-c294730c-6052-4ac5-bdec-6734f391d81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26726
49475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2672649475
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.888081755
Short name T343
Test name
Test status
Simulation time 140130865 ps
CPU time 0.77 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:25:10 PM PDT 24
Peak memory 205040 kb
Host smart-2a8c9594-a7af-4aa0-921d-06c1a6a0d225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88808
1755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.888081755
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1764065971
Short name T1420
Test name
Test status
Simulation time 56811446 ps
CPU time 0.67 seconds
Started Jun 10 05:25:10 PM PDT 24
Finished Jun 10 05:25:11 PM PDT 24
Peak memory 205012 kb
Host smart-f8520663-cc5c-49ca-bf02-60574dee5282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17640
65971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1764065971
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2152627885
Short name T1309
Test name
Test status
Simulation time 930300439 ps
CPU time 2.23 seconds
Started Jun 10 05:25:11 PM PDT 24
Finished Jun 10 05:25:14 PM PDT 24
Peak memory 205056 kb
Host smart-2796d6f9-f2be-4b7f-830c-b745576dbe10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21526
27885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2152627885
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.168261456
Short name T694
Test name
Test status
Simulation time 188479762 ps
CPU time 2.39 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:25:12 PM PDT 24
Peak memory 205088 kb
Host smart-399644fd-eeb3-4c96-be5c-e0dd26dfa09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16826
1456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.168261456
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.2227988408
Short name T739
Test name
Test status
Simulation time 220360999 ps
CPU time 0.89 seconds
Started Jun 10 05:25:12 PM PDT 24
Finished Jun 10 05:25:13 PM PDT 24
Peak memory 205000 kb
Host smart-d1d616fb-eca4-4c21-8091-0d7d7414463f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22279
88408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.2227988408
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.538561434
Short name T1345
Test name
Test status
Simulation time 161779775 ps
CPU time 0.78 seconds
Started Jun 10 05:25:12 PM PDT 24
Finished Jun 10 05:25:14 PM PDT 24
Peak memory 205024 kb
Host smart-64a36903-14e1-40d3-a209-a17c80b07ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53856
1434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.538561434
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.984106187
Short name T980
Test name
Test status
Simulation time 221720770 ps
CPU time 0.99 seconds
Started Jun 10 05:25:12 PM PDT 24
Finished Jun 10 05:25:13 PM PDT 24
Peak memory 205072 kb
Host smart-7e0fb6ea-fd48-40cd-834f-3518bdfb21ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98410
6187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.984106187
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.220170188
Short name T2026
Test name
Test status
Simulation time 218410554 ps
CPU time 0.9 seconds
Started Jun 10 05:25:08 PM PDT 24
Finished Jun 10 05:25:09 PM PDT 24
Peak memory 205040 kb
Host smart-f11413ff-a464-48f4-8746-5a6f03a9c88e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22017
0188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.220170188
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.625539757
Short name T360
Test name
Test status
Simulation time 3278071762 ps
CPU time 3.82 seconds
Started Jun 10 05:25:08 PM PDT 24
Finished Jun 10 05:25:12 PM PDT 24
Peak memory 205088 kb
Host smart-a462f3a1-df4c-4b04-a26a-79d4cb6560b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62553
9757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.625539757
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1176472096
Short name T803
Test name
Test status
Simulation time 193436952 ps
CPU time 0.85 seconds
Started Jun 10 05:25:13 PM PDT 24
Finished Jun 10 05:25:14 PM PDT 24
Peak memory 205020 kb
Host smart-dbbf4c8f-0a38-4473-8e3b-8842372438eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11764
72096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1176472096
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.125908970
Short name T1005
Test name
Test status
Simulation time 8502144585 ps
CPU time 237.33 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:29:07 PM PDT 24
Peak memory 205200 kb
Host smart-bc09bdcf-a7f4-475b-9bd6-f2550b6d5b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12590
8970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.125908970
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2359516632
Short name T496
Test name
Test status
Simulation time 156239885 ps
CPU time 0.83 seconds
Started Jun 10 05:25:08 PM PDT 24
Finished Jun 10 05:25:09 PM PDT 24
Peak memory 204996 kb
Host smart-e0a1d2a6-ea1f-4e25-83cb-30990ce3a775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23595
16632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2359516632
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.252428504
Short name T1042
Test name
Test status
Simulation time 161975647 ps
CPU time 0.85 seconds
Started Jun 10 05:25:14 PM PDT 24
Finished Jun 10 05:25:16 PM PDT 24
Peak memory 204936 kb
Host smart-5a0830b8-753f-4bc1-a513-f3e7f20fd331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25242
8504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.252428504
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.4235227136
Short name T1237
Test name
Test status
Simulation time 189986224 ps
CPU time 0.86 seconds
Started Jun 10 05:25:07 PM PDT 24
Finished Jun 10 05:25:08 PM PDT 24
Peak memory 205028 kb
Host smart-da42a547-cdc5-4b96-aa53-6e5b4722cf6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42352
27136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.4235227136
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2470770898
Short name T706
Test name
Test status
Simulation time 187399561 ps
CPU time 0.83 seconds
Started Jun 10 05:25:14 PM PDT 24
Finished Jun 10 05:25:16 PM PDT 24
Peak memory 204940 kb
Host smart-de98e7c8-6272-4f0f-8fb7-16161fd5f448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24707
70898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2470770898
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.3138038421
Short name T1138
Test name
Test status
Simulation time 147513865 ps
CPU time 0.8 seconds
Started Jun 10 05:25:15 PM PDT 24
Finished Jun 10 05:25:16 PM PDT 24
Peak memory 204992 kb
Host smart-c41b9293-79ab-434d-ac21-6e55317a6671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31380
38421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.3138038421
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_eop_single_bit_handling.2256924622
Short name T1489
Test name
Test status
Simulation time 152707896 ps
CPU time 0.79 seconds
Started Jun 10 05:25:11 PM PDT 24
Finished Jun 10 05:25:12 PM PDT 24
Peak memory 205028 kb
Host smart-81d0e175-8688-4fe9-b338-2cbc6125047d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22569
24622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_eop_single_bit_handling.2256924622
Directory /workspace/10.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1036668940
Short name T2043
Test name
Test status
Simulation time 144235285 ps
CPU time 0.81 seconds
Started Jun 10 05:25:11 PM PDT 24
Finished Jun 10 05:25:12 PM PDT 24
Peak memory 204960 kb
Host smart-24c54f27-9558-4359-9f88-b72d52c331e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10366
68940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1036668940
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2266742389
Short name T1004
Test name
Test status
Simulation time 55889351 ps
CPU time 0.66 seconds
Started Jun 10 05:25:15 PM PDT 24
Finished Jun 10 05:25:17 PM PDT 24
Peak memory 205024 kb
Host smart-511eefc7-1ade-4571-8146-7faca7173d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22667
42389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2266742389
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3919572770
Short name T1980
Test name
Test status
Simulation time 10155531920 ps
CPU time 21.89 seconds
Started Jun 10 05:25:06 PM PDT 24
Finished Jun 10 05:25:28 PM PDT 24
Peak memory 205200 kb
Host smart-fb7c7c13-0e5f-49bd-83ad-57a44ef82109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39195
72770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3919572770
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3637340069
Short name T1746
Test name
Test status
Simulation time 222474377 ps
CPU time 0.86 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:25:10 PM PDT 24
Peak memory 205008 kb
Host smart-d307fd66-6725-4734-a806-bbdf0a06cd65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36373
40069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3637340069
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.254385233
Short name T43
Test name
Test status
Simulation time 176890360 ps
CPU time 0.92 seconds
Started Jun 10 05:25:14 PM PDT 24
Finished Jun 10 05:25:16 PM PDT 24
Peak memory 205020 kb
Host smart-1b12ac43-04e2-4a26-82f3-245aa52af0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25438
5233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.254385233
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.2767641919
Short name T383
Test name
Test status
Simulation time 199510797 ps
CPU time 0.83 seconds
Started Jun 10 05:25:10 PM PDT 24
Finished Jun 10 05:25:11 PM PDT 24
Peak memory 205016 kb
Host smart-05cd1b33-7c89-4d4a-adcc-cdf41c61f2b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27676
41919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.2767641919
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3030031618
Short name T60
Test name
Test status
Simulation time 187791399 ps
CPU time 0.84 seconds
Started Jun 10 05:25:10 PM PDT 24
Finished Jun 10 05:25:12 PM PDT 24
Peak memory 205040 kb
Host smart-3792fa63-b21e-46f9-8388-c19bde09af74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30300
31618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3030031618
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3291835744
Short name T1909
Test name
Test status
Simulation time 153263052 ps
CPU time 0.84 seconds
Started Jun 10 05:25:13 PM PDT 24
Finished Jun 10 05:25:14 PM PDT 24
Peak memory 205020 kb
Host smart-849b97ff-c6c6-44f7-a88d-d2c1d9b72c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32918
35744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3291835744
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2829770365
Short name T1154
Test name
Test status
Simulation time 299695994 ps
CPU time 1.05 seconds
Started Jun 10 05:25:11 PM PDT 24
Finished Jun 10 05:25:13 PM PDT 24
Peak memory 205008 kb
Host smart-36a6f72c-5c60-44d8-8f2f-0c3b9bf29aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28297
70365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2829770365
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1537039562
Short name T1189
Test name
Test status
Simulation time 181678514 ps
CPU time 0.89 seconds
Started Jun 10 05:25:14 PM PDT 24
Finished Jun 10 05:25:15 PM PDT 24
Peak memory 204908 kb
Host smart-e7ae53e7-6deb-4197-ac18-3025882b2bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15370
39562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1537039562
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.168605706
Short name T33
Test name
Test status
Simulation time 178235352 ps
CPU time 0.86 seconds
Started Jun 10 05:25:10 PM PDT 24
Finished Jun 10 05:25:11 PM PDT 24
Peak memory 204992 kb
Host smart-0f6a3411-c572-43d0-94e2-282783ad0221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16860
5706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.168605706
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.1531417806
Short name T437
Test name
Test status
Simulation time 8627042109 ps
CPU time 81.37 seconds
Started Jun 10 05:25:14 PM PDT 24
Finished Jun 10 05:26:36 PM PDT 24
Peak memory 205168 kb
Host smart-dbcc2b83-fd57-49f4-a539-5fe85bc38635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15314
17806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.1531417806
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.3962245847
Short name T590
Test name
Test status
Simulation time 245768591 ps
CPU time 0.97 seconds
Started Jun 10 05:25:26 PM PDT 24
Finished Jun 10 05:25:28 PM PDT 24
Peak memory 205072 kb
Host smart-9502e417-6bae-467e-a94d-32eaba31d50e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3962245847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.3962245847
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.3227088566
Short name T396
Test name
Test status
Simulation time 168323602 ps
CPU time 0.81 seconds
Started Jun 10 05:25:27 PM PDT 24
Finished Jun 10 05:25:28 PM PDT 24
Peak memory 205068 kb
Host smart-0f70bdd2-0f4f-4089-9a4c-d0f229cfba36
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3227088566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.3227088566
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.3847332252
Short name T1776
Test name
Test status
Simulation time 174630836 ps
CPU time 0.82 seconds
Started Jun 10 05:25:27 PM PDT 24
Finished Jun 10 05:25:28 PM PDT 24
Peak memory 204992 kb
Host smart-b3a11418-66fd-4cd1-8cfb-30e34ef8ba90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38473
32252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.3847332252
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1684275315
Short name T959
Test name
Test status
Simulation time 4103930711 ps
CPU time 5.5 seconds
Started Jun 10 05:25:17 PM PDT 24
Finished Jun 10 05:25:22 PM PDT 24
Peak memory 205100 kb
Host smart-38edcdbf-eb35-468f-a282-d03ff5f223df
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1684275315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.1684275315
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.3660597965
Short name T418
Test name
Test status
Simulation time 13349828893 ps
CPU time 13.71 seconds
Started Jun 10 05:25:13 PM PDT 24
Finished Jun 10 05:25:27 PM PDT 24
Peak memory 205304 kb
Host smart-807d6bed-fc68-4dcb-93fa-cf05f8590e3b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3660597965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.3660597965
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.2808121297
Short name T1414
Test name
Test status
Simulation time 23482007971 ps
CPU time 28.79 seconds
Started Jun 10 05:25:24 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 205120 kb
Host smart-f3868cf2-8770-4b3c-97e0-c89814b2e983
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2808121297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.2808121297
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3140089291
Short name T1110
Test name
Test status
Simulation time 146676324 ps
CPU time 0.79 seconds
Started Jun 10 05:25:15 PM PDT 24
Finished Jun 10 05:25:16 PM PDT 24
Peak memory 205024 kb
Host smart-0ccc51af-692e-456e-ba53-f910e707ade8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31400
89291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3140089291
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.450523757
Short name T1299
Test name
Test status
Simulation time 153165687 ps
CPU time 0.78 seconds
Started Jun 10 05:25:21 PM PDT 24
Finished Jun 10 05:25:22 PM PDT 24
Peak memory 205040 kb
Host smart-f9727d34-3214-49c8-aa60-8e8bb3219ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45052
3757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.450523757
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2247077851
Short name T1538
Test name
Test status
Simulation time 569810663 ps
CPU time 1.54 seconds
Started Jun 10 05:25:11 PM PDT 24
Finished Jun 10 05:25:13 PM PDT 24
Peak memory 205024 kb
Host smart-87de6b4e-f14e-4464-816a-b669ecf7b8bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22470
77851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2247077851
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.325930711
Short name T1971
Test name
Test status
Simulation time 146040157 ps
CPU time 0.81 seconds
Started Jun 10 05:25:24 PM PDT 24
Finished Jun 10 05:25:25 PM PDT 24
Peak memory 205008 kb
Host smart-e6b8fc77-8aa2-4629-a686-a261b8fd9c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32593
0711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.325930711
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2187603366
Short name T347
Test name
Test status
Simulation time 53509211 ps
CPU time 0.66 seconds
Started Jun 10 05:25:15 PM PDT 24
Finished Jun 10 05:25:16 PM PDT 24
Peak memory 204988 kb
Host smart-f3bb594a-8f5c-4635-b677-3d8967dfe38b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21876
03366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2187603366
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2056805877
Short name T992
Test name
Test status
Simulation time 1015009297 ps
CPU time 2.32 seconds
Started Jun 10 05:25:10 PM PDT 24
Finished Jun 10 05:25:13 PM PDT 24
Peak memory 205072 kb
Host smart-718c04bf-9657-4acd-8df4-a676b987e188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20568
05877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2056805877
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.902689094
Short name T95
Test name
Test status
Simulation time 312030062 ps
CPU time 2.49 seconds
Started Jun 10 05:25:26 PM PDT 24
Finished Jun 10 05:25:29 PM PDT 24
Peak memory 205156 kb
Host smart-26424f94-86fb-406d-a3f1-c6f299a43dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90268
9094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.902689094
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.3849441339
Short name T1322
Test name
Test status
Simulation time 254434996 ps
CPU time 0.92 seconds
Started Jun 10 05:25:28 PM PDT 24
Finished Jun 10 05:25:30 PM PDT 24
Peak memory 205020 kb
Host smart-7280aeca-fb92-4ae3-9ceb-28cffddcbed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38494
41339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.3849441339
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1919820354
Short name T636
Test name
Test status
Simulation time 144081812 ps
CPU time 0.79 seconds
Started Jun 10 05:25:24 PM PDT 24
Finished Jun 10 05:25:25 PM PDT 24
Peak memory 205000 kb
Host smart-c74a7c51-105d-4ed2-baa2-cc8dc0437389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19198
20354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1919820354
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1590159430
Short name T1444
Test name
Test status
Simulation time 202863320 ps
CPU time 0.93 seconds
Started Jun 10 05:25:29 PM PDT 24
Finished Jun 10 05:25:31 PM PDT 24
Peak memory 204996 kb
Host smart-bef05b0c-7b61-4fdf-ac45-ca3ab1af379e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15901
59430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1590159430
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.3110937361
Short name T1454
Test name
Test status
Simulation time 154619852 ps
CPU time 0.83 seconds
Started Jun 10 05:25:23 PM PDT 24
Finished Jun 10 05:25:25 PM PDT 24
Peak memory 204848 kb
Host smart-4ec5d7d5-7d6a-4a6f-abb8-0da5ec819797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31109
37361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.3110937361
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.3827043407
Short name T967
Test name
Test status
Simulation time 3336514791 ps
CPU time 4.17 seconds
Started Jun 10 05:25:24 PM PDT 24
Finished Jun 10 05:25:28 PM PDT 24
Peak memory 205072 kb
Host smart-cd3c7ac2-5402-4a81-a38b-38bfe47919c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38270
43407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.3827043407
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.4002953524
Short name T672
Test name
Test status
Simulation time 189667665 ps
CPU time 0.94 seconds
Started Jun 10 05:25:26 PM PDT 24
Finished Jun 10 05:25:27 PM PDT 24
Peak memory 205004 kb
Host smart-c8e94cee-5aec-457a-945b-2923ef9541c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40029
53524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.4002953524
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.280967546
Short name T1897
Test name
Test status
Simulation time 5256603534 ps
CPU time 36.59 seconds
Started Jun 10 05:25:17 PM PDT 24
Finished Jun 10 05:25:54 PM PDT 24
Peak memory 205068 kb
Host smart-ff4d3f15-1968-45de-8a2b-c90a82e47aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28096
7546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.280967546
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1561479161
Short name T2003
Test name
Test status
Simulation time 145338922 ps
CPU time 0.76 seconds
Started Jun 10 05:25:19 PM PDT 24
Finished Jun 10 05:25:20 PM PDT 24
Peak memory 205036 kb
Host smart-346643ca-c6b7-43a4-872d-54f8968580be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15614
79161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1561479161
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.4017831082
Short name T81
Test name
Test status
Simulation time 173601789 ps
CPU time 0.89 seconds
Started Jun 10 05:25:18 PM PDT 24
Finished Jun 10 05:25:19 PM PDT 24
Peak memory 205088 kb
Host smart-d504119b-00f3-4c50-b45e-648656f4c18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40178
31082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.4017831082
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2492585717
Short name T643
Test name
Test status
Simulation time 216289971 ps
CPU time 0.89 seconds
Started Jun 10 05:25:29 PM PDT 24
Finished Jun 10 05:25:30 PM PDT 24
Peak memory 205004 kb
Host smart-92dbdb16-6804-4b7a-9d21-fc2587afe066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24925
85717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2492585717
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.326000311
Short name T55
Test name
Test status
Simulation time 154772564 ps
CPU time 0.8 seconds
Started Jun 10 05:25:17 PM PDT 24
Finished Jun 10 05:25:18 PM PDT 24
Peak memory 205016 kb
Host smart-4f835897-a45d-48aa-824d-1f9dc75524da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32600
0311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.326000311
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2860140845
Short name T1673
Test name
Test status
Simulation time 162283128 ps
CPU time 0.87 seconds
Started Jun 10 05:25:22 PM PDT 24
Finished Jun 10 05:25:24 PM PDT 24
Peak memory 204992 kb
Host smart-66f9c73f-4563-4909-b882-75d35c891bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28601
40845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2860140845
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_eop_single_bit_handling.3273173
Short name T1936
Test name
Test status
Simulation time 237482516 ps
CPU time 1 seconds
Started Jun 10 05:25:29 PM PDT 24
Finished Jun 10 05:25:31 PM PDT 24
Peak memory 204996 kb
Host smart-a6004519-c78e-4277-99d3-68a62149459c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32731
73 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_eop_single_bit_handling.3273173
Directory /workspace/11.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2833948069
Short name T1016
Test name
Test status
Simulation time 151201457 ps
CPU time 0.76 seconds
Started Jun 10 05:25:17 PM PDT 24
Finished Jun 10 05:25:18 PM PDT 24
Peak memory 204984 kb
Host smart-8862e749-e1d7-4c9b-a696-67fb15f30dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28339
48069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2833948069
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.5536779
Short name T1215
Test name
Test status
Simulation time 168122559 ps
CPU time 0.9 seconds
Started Jun 10 05:25:26 PM PDT 24
Finished Jun 10 05:25:27 PM PDT 24
Peak memory 205044 kb
Host smart-82462cf3-2ba8-4cce-96c2-0e2844da1a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55367
79 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.5536779
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.980280186
Short name T1859
Test name
Test status
Simulation time 239364154 ps
CPU time 0.97 seconds
Started Jun 10 05:25:28 PM PDT 24
Finished Jun 10 05:25:29 PM PDT 24
Peak memory 204996 kb
Host smart-f79a24e9-ccaa-446b-bac1-6de8fb788ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98028
0186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.980280186
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.2499913649
Short name T1115
Test name
Test status
Simulation time 169278497 ps
CPU time 0.83 seconds
Started Jun 10 05:25:21 PM PDT 24
Finished Jun 10 05:25:22 PM PDT 24
Peak memory 205080 kb
Host smart-aed48f45-d20a-4c5d-9f8d-1fed6ee84ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24999
13649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.2499913649
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.129949272
Short name T732
Test name
Test status
Simulation time 143360829 ps
CPU time 0.75 seconds
Started Jun 10 05:25:15 PM PDT 24
Finished Jun 10 05:25:17 PM PDT 24
Peak memory 204992 kb
Host smart-f6ebf6a5-00ee-4f6e-bc66-3489cff175c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12994
9272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.129949272
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1999919827
Short name T170
Test name
Test status
Simulation time 150871335 ps
CPU time 0.85 seconds
Started Jun 10 05:25:22 PM PDT 24
Finished Jun 10 05:25:23 PM PDT 24
Peak memory 204956 kb
Host smart-8c33922a-9974-41c2-928d-c2e85d436519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19999
19827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1999919827
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1962310017
Short name T1417
Test name
Test status
Simulation time 142474154 ps
CPU time 0.79 seconds
Started Jun 10 05:25:26 PM PDT 24
Finished Jun 10 05:25:27 PM PDT 24
Peak memory 205008 kb
Host smart-6415ce1a-4a1e-4f33-9be7-f9b38b4bde5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19623
10017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1962310017
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.211121884
Short name T988
Test name
Test status
Simulation time 190463890 ps
CPU time 0.87 seconds
Started Jun 10 05:25:11 PM PDT 24
Finished Jun 10 05:25:12 PM PDT 24
Peak memory 204992 kb
Host smart-9dae9820-e048-49a6-bf93-95af505de06e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21112
1884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.211121884
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1123768938
Short name T2092
Test name
Test status
Simulation time 224546772 ps
CPU time 0.9 seconds
Started Jun 10 05:25:18 PM PDT 24
Finished Jun 10 05:25:20 PM PDT 24
Peak memory 205020 kb
Host smart-b852e8d8-47f6-4567-9ce0-3db98afe6c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11237
68938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1123768938
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3062403764
Short name T1602
Test name
Test status
Simulation time 217479116 ps
CPU time 0.83 seconds
Started Jun 10 05:25:24 PM PDT 24
Finished Jun 10 05:25:25 PM PDT 24
Peak memory 205004 kb
Host smart-a3eeb2f7-c87d-459b-81c6-7bc794f5f34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30624
03764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3062403764
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1702770639
Short name T1515
Test name
Test status
Simulation time 12428748267 ps
CPU time 97.03 seconds
Started Jun 10 05:25:29 PM PDT 24
Finished Jun 10 05:27:06 PM PDT 24
Peak memory 205160 kb
Host smart-e23fdffc-c571-4daa-ade4-500a8a635506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17027
70639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1702770639
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.1377624060
Short name T1563
Test name
Test status
Simulation time 246798946 ps
CPU time 0.89 seconds
Started Jun 10 05:25:27 PM PDT 24
Finished Jun 10 05:25:28 PM PDT 24
Peak memory 204996 kb
Host smart-ce84702d-4ec8-481a-92bb-86a1477afc1a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1377624060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.1377624060
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.2738874638
Short name T1227
Test name
Test status
Simulation time 215829813 ps
CPU time 0.87 seconds
Started Jun 10 05:25:34 PM PDT 24
Finished Jun 10 05:25:35 PM PDT 24
Peak memory 205020 kb
Host smart-80d7b73f-c6b7-4d4a-bd1f-39279365d05b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2738874638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.2738874638
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.2644515108
Short name T358
Test name
Test status
Simulation time 249303195 ps
CPU time 1.08 seconds
Started Jun 10 05:25:27 PM PDT 24
Finished Jun 10 05:25:28 PM PDT 24
Peak memory 205056 kb
Host smart-071bb2ce-c7b7-486c-b90b-12be40a69917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26445
15108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.2644515108
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.3680471893
Short name T1225
Test name
Test status
Simulation time 3452657737 ps
CPU time 4.1 seconds
Started Jun 10 05:25:28 PM PDT 24
Finished Jun 10 05:25:32 PM PDT 24
Peak memory 205124 kb
Host smart-ff032d7d-652f-4984-be3e-795899ae3fdc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3680471893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.3680471893
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.3276608484
Short name T10
Test name
Test status
Simulation time 13323090620 ps
CPU time 13.11 seconds
Started Jun 10 05:25:29 PM PDT 24
Finished Jun 10 05:25:42 PM PDT 24
Peak memory 205160 kb
Host smart-7c379245-2da5-48de-880f-8c7cf3bf15b9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3276608484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.3276608484
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2983922924
Short name T2016
Test name
Test status
Simulation time 23364887599 ps
CPU time 24.64 seconds
Started Jun 10 05:25:26 PM PDT 24
Finished Jun 10 05:25:51 PM PDT 24
Peak memory 205188 kb
Host smart-f3cb0485-529c-4df1-a9da-0cc630d78dd6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2983922924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.2983922924
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.32801246
Short name T1603
Test name
Test status
Simulation time 153766964 ps
CPU time 0.83 seconds
Started Jun 10 05:25:27 PM PDT 24
Finished Jun 10 05:25:28 PM PDT 24
Peak memory 204992 kb
Host smart-8ab91132-397f-412a-8c56-f6fe9c39446f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32801
246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.32801246
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1198627075
Short name T310
Test name
Test status
Simulation time 149169208 ps
CPU time 0.83 seconds
Started Jun 10 05:25:31 PM PDT 24
Finished Jun 10 05:25:32 PM PDT 24
Peak memory 204992 kb
Host smart-afe7e083-fd0b-442e-9e40-a757245321b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11986
27075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1198627075
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3563459602
Short name T1590
Test name
Test status
Simulation time 1612903902 ps
CPU time 3.67 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:34 PM PDT 24
Peak memory 205080 kb
Host smart-46a0db23-e243-453b-ba41-f8af94f7914c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35634
59602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3563459602
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.1482061428
Short name T1913
Test name
Test status
Simulation time 142382222 ps
CPU time 0.79 seconds
Started Jun 10 05:25:22 PM PDT 24
Finished Jun 10 05:25:23 PM PDT 24
Peak memory 204980 kb
Host smart-c06ce067-8b81-4565-97d6-409085e3a0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14820
61428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.1482061428
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.2611374411
Short name T1865
Test name
Test status
Simulation time 35012512 ps
CPU time 0.7 seconds
Started Jun 10 05:25:27 PM PDT 24
Finished Jun 10 05:25:28 PM PDT 24
Peak memory 204876 kb
Host smart-c5c64625-9dea-4aba-a7df-67663aa0cbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26113
74411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2611374411
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1034704831
Short name T1282
Test name
Test status
Simulation time 1052084291 ps
CPU time 2.51 seconds
Started Jun 10 05:25:28 PM PDT 24
Finished Jun 10 05:25:31 PM PDT 24
Peak memory 205108 kb
Host smart-fc716b74-da5a-4ed4-a49e-bd98baa73045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10347
04831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1034704831
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3288698361
Short name T850
Test name
Test status
Simulation time 330527576 ps
CPU time 1.99 seconds
Started Jun 10 05:25:27 PM PDT 24
Finished Jun 10 05:25:30 PM PDT 24
Peak memory 205076 kb
Host smart-6e32831b-e330-4316-b67f-396d5376e0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32886
98361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3288698361
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.844850082
Short name T1866
Test name
Test status
Simulation time 204774449 ps
CPU time 0.82 seconds
Started Jun 10 05:25:27 PM PDT 24
Finished Jun 10 05:25:28 PM PDT 24
Peak memory 205008 kb
Host smart-dd1d871f-1e99-4897-9c37-556200d5055c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84485
0082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.844850082
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.1800262479
Short name T747
Test name
Test status
Simulation time 161074010 ps
CPU time 0.78 seconds
Started Jun 10 05:25:31 PM PDT 24
Finished Jun 10 05:25:32 PM PDT 24
Peak memory 205028 kb
Host smart-725d8606-5a25-4524-bac4-0d99dce9db02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18002
62479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.1800262479
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.502558059
Short name T1274
Test name
Test status
Simulation time 248481012 ps
CPU time 0.97 seconds
Started Jun 10 05:25:26 PM PDT 24
Finished Jun 10 05:25:27 PM PDT 24
Peak memory 204964 kb
Host smart-1a3bafc5-fce7-4ace-962a-21e85f4ed149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50255
8059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.502558059
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.2311127496
Short name T1029
Test name
Test status
Simulation time 203510000 ps
CPU time 0.87 seconds
Started Jun 10 05:25:27 PM PDT 24
Finished Jun 10 05:25:28 PM PDT 24
Peak memory 205016 kb
Host smart-21d1d3a0-9f00-4562-aba8-ecbeaff890dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23111
27496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.2311127496
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.963362194
Short name T750
Test name
Test status
Simulation time 3363616721 ps
CPU time 4.06 seconds
Started Jun 10 05:25:25 PM PDT 24
Finished Jun 10 05:25:29 PM PDT 24
Peak memory 205080 kb
Host smart-d299aecd-0c1f-4a07-a634-e1eb683ba6fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96336
2194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.963362194
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.4094711715
Short name T1558
Test name
Test status
Simulation time 212305861 ps
CPU time 0.9 seconds
Started Jun 10 05:25:28 PM PDT 24
Finished Jun 10 05:25:29 PM PDT 24
Peak memory 205004 kb
Host smart-028acaca-e627-406e-8623-29f63747bacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40947
11715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.4094711715
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.3029419572
Short name T546
Test name
Test status
Simulation time 3928791296 ps
CPU time 38.86 seconds
Started Jun 10 05:25:21 PM PDT 24
Finished Jun 10 05:26:01 PM PDT 24
Peak memory 205148 kb
Host smart-f4260b65-964a-4146-b237-81a63ec6c876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30294
19572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.3029419572
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.3255618756
Short name T1714
Test name
Test status
Simulation time 142936958 ps
CPU time 0.79 seconds
Started Jun 10 05:25:23 PM PDT 24
Finished Jun 10 05:25:25 PM PDT 24
Peak memory 205008 kb
Host smart-721d8aaf-7b76-4976-80cf-b3423068aa1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32556
18756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.3255618756
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.2802229542
Short name T414
Test name
Test status
Simulation time 188455295 ps
CPU time 0.95 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:31 PM PDT 24
Peak memory 204988 kb
Host smart-fc7718f0-cd37-4ae8-a55e-f28d2bb78b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28022
29542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.2802229542
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2573414706
Short name T1511
Test name
Test status
Simulation time 159761963 ps
CPU time 0.83 seconds
Started Jun 10 05:25:25 PM PDT 24
Finished Jun 10 05:25:26 PM PDT 24
Peak memory 205012 kb
Host smart-5e5fb4e7-0d4e-4c2a-b66f-e57a31189b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25734
14706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2573414706
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.558860265
Short name T1679
Test name
Test status
Simulation time 250015846 ps
CPU time 0.93 seconds
Started Jun 10 05:25:28 PM PDT 24
Finished Jun 10 05:25:29 PM PDT 24
Peak memory 204992 kb
Host smart-f407ac7f-f686-485c-8415-8e49a4a7daba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55886
0265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.558860265
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1360516073
Short name T1992
Test name
Test status
Simulation time 165036507 ps
CPU time 0.77 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:32 PM PDT 24
Peak memory 205024 kb
Host smart-0dc73502-a96f-4be0-8839-5e1a894e5064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13605
16073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1360516073
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_eop_single_bit_handling.2085222464
Short name T1796
Test name
Test status
Simulation time 194564691 ps
CPU time 0.87 seconds
Started Jun 10 05:25:35 PM PDT 24
Finished Jun 10 05:25:36 PM PDT 24
Peak memory 205036 kb
Host smart-33cca3e0-c7ca-4640-ab23-c4d0428dfcfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20852
22464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_eop_single_bit_handling.2085222464
Directory /workspace/12.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3949669504
Short name T1438
Test name
Test status
Simulation time 167079734 ps
CPU time 0.77 seconds
Started Jun 10 05:25:25 PM PDT 24
Finished Jun 10 05:25:26 PM PDT 24
Peak memory 204988 kb
Host smart-36310e3f-7be1-4575-a37d-52b1cdab1cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39496
69504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3949669504
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.4250675112
Short name T1248
Test name
Test status
Simulation time 38053805 ps
CPU time 0.68 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:39 PM PDT 24
Peak memory 205016 kb
Host smart-46f05af2-80cb-4573-9a23-7a75ad39f715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42506
75112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.4250675112
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.628237974
Short name T1616
Test name
Test status
Simulation time 21306072163 ps
CPU time 50.81 seconds
Started Jun 10 05:25:21 PM PDT 24
Finished Jun 10 05:26:12 PM PDT 24
Peak memory 205248 kb
Host smart-34658f84-c3eb-4fb1-9e37-01594db93c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62823
7974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.628237974
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.93375729
Short name T677
Test name
Test status
Simulation time 151028584 ps
CPU time 0.77 seconds
Started Jun 10 05:25:25 PM PDT 24
Finished Jun 10 05:25:26 PM PDT 24
Peak memory 204912 kb
Host smart-09d2030c-54f9-41f3-b574-c2bbaf1eb636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93375
729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.93375729
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.238334137
Short name T961
Test name
Test status
Simulation time 161533204 ps
CPU time 0.78 seconds
Started Jun 10 05:25:36 PM PDT 24
Finished Jun 10 05:25:37 PM PDT 24
Peak memory 204980 kb
Host smart-df3f740f-65ea-4a47-98ad-894cb18dbfc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23833
4137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.238334137
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.3167839695
Short name T1002
Test name
Test status
Simulation time 176216363 ps
CPU time 0.85 seconds
Started Jun 10 05:25:24 PM PDT 24
Finished Jun 10 05:25:25 PM PDT 24
Peak memory 205004 kb
Host smart-4205e248-9e0a-4eb4-82d6-c7139bf61066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31678
39695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.3167839695
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.3138265489
Short name T1080
Test name
Test status
Simulation time 136340256 ps
CPU time 0.78 seconds
Started Jun 10 05:25:23 PM PDT 24
Finished Jun 10 05:25:24 PM PDT 24
Peak memory 205088 kb
Host smart-86b2226d-f09c-4d9a-8367-9b7c4c35d172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31382
65489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.3138265489
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.734495532
Short name T1501
Test name
Test status
Simulation time 157192050 ps
CPU time 0.8 seconds
Started Jun 10 05:25:23 PM PDT 24
Finished Jun 10 05:25:24 PM PDT 24
Peak memory 204896 kb
Host smart-bdf24fd6-b45b-44f4-89cc-bc8e292691f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73449
5532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.734495532
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.179835819
Short name T191
Test name
Test status
Simulation time 235762278 ps
CPU time 0.95 seconds
Started Jun 10 05:25:25 PM PDT 24
Finished Jun 10 05:25:26 PM PDT 24
Peak memory 205000 kb
Host smart-4f1e6a94-39c2-4ebe-87c4-369fd48d669b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17983
5819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.179835819
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2295129079
Short name T1175
Test name
Test status
Simulation time 144168881 ps
CPU time 0.77 seconds
Started Jun 10 05:25:24 PM PDT 24
Finished Jun 10 05:25:25 PM PDT 24
Peak memory 204988 kb
Host smart-a7222dfa-0dbd-46b3-8bf0-3a2d68cc8694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22951
29079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2295129079
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2792058034
Short name T402
Test name
Test status
Simulation time 164961703 ps
CPU time 0.88 seconds
Started Jun 10 05:25:27 PM PDT 24
Finished Jun 10 05:25:29 PM PDT 24
Peak memory 205004 kb
Host smart-09a88375-f450-46cc-ae58-75013157ef4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27920
58034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2792058034
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.1192370362
Short name T367
Test name
Test status
Simulation time 12685585974 ps
CPU time 354.73 seconds
Started Jun 10 05:25:26 PM PDT 24
Finished Jun 10 05:31:21 PM PDT 24
Peak memory 205148 kb
Host smart-6e41b15a-32d0-4d57-814d-068cd7b43e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11923
70362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.1192370362
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.337819515
Short name T1230
Test name
Test status
Simulation time 245686131 ps
CPU time 0.89 seconds
Started Jun 10 05:25:34 PM PDT 24
Finished Jun 10 05:25:35 PM PDT 24
Peak memory 204996 kb
Host smart-13c6febe-7e2b-4057-ae6f-1ec02f8abda5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=337819515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.337819515
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.909232787
Short name T1234
Test name
Test status
Simulation time 144000739 ps
CPU time 0.79 seconds
Started Jun 10 05:25:36 PM PDT 24
Finished Jun 10 05:25:37 PM PDT 24
Peak memory 205060 kb
Host smart-c91bbbe9-9bf8-48bf-b1b1-148876bedca3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=909232787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.909232787
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.1064554825
Short name T1165
Test name
Test status
Simulation time 189076282 ps
CPU time 0.86 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:32 PM PDT 24
Peak memory 205016 kb
Host smart-72a95095-fdda-4710-8f1d-64b877a80ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10645
54825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.1064554825
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.890432897
Short name T482
Test name
Test status
Simulation time 3375769078 ps
CPU time 4.11 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:34 PM PDT 24
Peak memory 205176 kb
Host smart-72babcef-8903-4322-8cf9-f6e559a8bb02
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=890432897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.890432897
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.2917111309
Short name T1615
Test name
Test status
Simulation time 13334863823 ps
CPU time 16.47 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:47 PM PDT 24
Peak memory 205120 kb
Host smart-f4e71015-58db-42ac-9c37-2c16d38794a3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2917111309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.2917111309
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.4179370447
Short name T508
Test name
Test status
Simulation time 23342297857 ps
CPU time 22.47 seconds
Started Jun 10 05:25:34 PM PDT 24
Finished Jun 10 05:25:57 PM PDT 24
Peak memory 205068 kb
Host smart-3e347ec1-1fd3-4dbf-b14c-1268ff508823
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4179370447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.4179370447
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.364982118
Short name T1421
Test name
Test status
Simulation time 149621672 ps
CPU time 0.76 seconds
Started Jun 10 05:25:26 PM PDT 24
Finished Jun 10 05:25:27 PM PDT 24
Peak memory 204972 kb
Host smart-29c58692-76e2-4f5e-be0f-449604dbc26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36498
2118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.364982118
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3406775936
Short name T891
Test name
Test status
Simulation time 146542467 ps
CPU time 0.79 seconds
Started Jun 10 05:25:27 PM PDT 24
Finished Jun 10 05:25:28 PM PDT 24
Peak memory 204992 kb
Host smart-91a1bbb4-34a3-46d1-bdd2-f2f36c82ef09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34067
75936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3406775936
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.2163074670
Short name T970
Test name
Test status
Simulation time 142722184 ps
CPU time 0.86 seconds
Started Jun 10 05:25:29 PM PDT 24
Finished Jun 10 05:25:30 PM PDT 24
Peak memory 205028 kb
Host smart-42fd5222-61c5-45b5-9d13-b396c916f4d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21630
74670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.2163074670
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.15809845
Short name T2052
Test name
Test status
Simulation time 89596932 ps
CPU time 0.72 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:31 PM PDT 24
Peak memory 205000 kb
Host smart-28397768-9fa7-40bc-8691-6ca154b3a793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15809
845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.15809845
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.235451119
Short name T566
Test name
Test status
Simulation time 801879599 ps
CPU time 2.14 seconds
Started Jun 10 05:25:36 PM PDT 24
Finished Jun 10 05:25:39 PM PDT 24
Peak memory 205124 kb
Host smart-ef10fa3f-e124-4215-a244-a99e014f23cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23545
1119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.235451119
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2316498808
Short name T538
Test name
Test status
Simulation time 266450356 ps
CPU time 1.42 seconds
Started Jun 10 05:25:33 PM PDT 24
Finished Jun 10 05:25:35 PM PDT 24
Peak memory 205092 kb
Host smart-8c7ce9bb-9f0c-446c-a9a7-21ecc5fb9917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23164
98808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2316498808
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2690006591
Short name T71
Test name
Test status
Simulation time 239863694 ps
CPU time 0.88 seconds
Started Jun 10 05:25:29 PM PDT 24
Finished Jun 10 05:25:31 PM PDT 24
Peak memory 205036 kb
Host smart-6739e050-2939-498e-a2ed-182f2f07b635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26900
06591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2690006591
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1025532668
Short name T673
Test name
Test status
Simulation time 141152940 ps
CPU time 0.79 seconds
Started Jun 10 05:25:32 PM PDT 24
Finished Jun 10 05:25:33 PM PDT 24
Peak memory 205012 kb
Host smart-383c65e0-66a3-4ad2-92f5-3adb90f1d9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10255
32668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1025532668
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.3046244564
Short name T856
Test name
Test status
Simulation time 196645436 ps
CPU time 0.95 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:38 PM PDT 24
Peak memory 205032 kb
Host smart-6109bbf1-b813-418a-82f9-911b8a56ffe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30462
44564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.3046244564
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1345857350
Short name T1302
Test name
Test status
Simulation time 287992577 ps
CPU time 1 seconds
Started Jun 10 05:25:27 PM PDT 24
Finished Jun 10 05:25:29 PM PDT 24
Peak memory 205008 kb
Host smart-67df04ca-9bab-473b-9a64-8b03bde84c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13458
57350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1345857350
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3944579589
Short name T403
Test name
Test status
Simulation time 3334543473 ps
CPU time 3.96 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:35 PM PDT 24
Peak memory 204972 kb
Host smart-dc9e3d9a-26f4-4749-8044-7ef406148c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39445
79589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3944579589
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2093332751
Short name T1383
Test name
Test status
Simulation time 187313138 ps
CPU time 0.87 seconds
Started Jun 10 05:25:29 PM PDT 24
Finished Jun 10 05:25:30 PM PDT 24
Peak memory 205040 kb
Host smart-b76cbd0e-7b4e-4526-84e9-8bbd248ba863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20933
32751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2093332751
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.2383564396
Short name T1003
Test name
Test status
Simulation time 6281456360 ps
CPU time 175.07 seconds
Started Jun 10 05:25:33 PM PDT 24
Finished Jun 10 05:28:29 PM PDT 24
Peak memory 205204 kb
Host smart-6678543a-297d-497f-9144-57a3aacdeadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23835
64396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.2383564396
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.4186986879
Short name T294
Test name
Test status
Simulation time 160678973 ps
CPU time 0.77 seconds
Started Jun 10 05:25:31 PM PDT 24
Finished Jun 10 05:25:32 PM PDT 24
Peak memory 205048 kb
Host smart-2599576b-6de1-440d-9c13-3fb6665c49e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41869
86879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.4186986879
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.292866034
Short name T409
Test name
Test status
Simulation time 146041184 ps
CPU time 0.85 seconds
Started Jun 10 05:25:29 PM PDT 24
Finished Jun 10 05:25:30 PM PDT 24
Peak memory 204992 kb
Host smart-cf1bc495-9861-456f-b427-6adb274d88e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29286
6034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.292866034
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.575566894
Short name T887
Test name
Test status
Simulation time 243393073 ps
CPU time 0.95 seconds
Started Jun 10 05:25:29 PM PDT 24
Finished Jun 10 05:25:31 PM PDT 24
Peak memory 204996 kb
Host smart-d3dd5710-08bf-4b11-b8d9-aca6b23aafc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57556
6894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.575566894
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1650854535
Short name T1289
Test name
Test status
Simulation time 168205322 ps
CPU time 0.8 seconds
Started Jun 10 05:25:28 PM PDT 24
Finished Jun 10 05:25:29 PM PDT 24
Peak memory 204896 kb
Host smart-7bf2c890-9ac4-4e0e-9251-d057c75d0918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16508
54535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1650854535
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1487898106
Short name T218
Test name
Test status
Simulation time 208810401 ps
CPU time 0.86 seconds
Started Jun 10 05:25:32 PM PDT 24
Finished Jun 10 05:25:33 PM PDT 24
Peak memory 205016 kb
Host smart-725ec2c4-a55e-43e1-b59c-8174c7c430ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14878
98106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1487898106
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_eop_single_bit_handling.3523354112
Short name T1939
Test name
Test status
Simulation time 201352211 ps
CPU time 0.88 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:39 PM PDT 24
Peak memory 205064 kb
Host smart-e4f47062-242a-462f-9cbe-eb1ea175f0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35233
54112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_eop_single_bit_handling.3523354112
Directory /workspace/13.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1261590814
Short name T382
Test name
Test status
Simulation time 142454916 ps
CPU time 0.76 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:32 PM PDT 24
Peak memory 204976 kb
Host smart-406ceb34-8d35-43e4-9239-4f0cab2e9cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12615
90814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1261590814
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2269033300
Short name T488
Test name
Test status
Simulation time 40078738 ps
CPU time 0.66 seconds
Started Jun 10 05:25:33 PM PDT 24
Finished Jun 10 05:25:34 PM PDT 24
Peak memory 204992 kb
Host smart-11021b0d-a10d-49c0-8e38-ad8d1cc480f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22690
33300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2269033300
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1614997942
Short name T1727
Test name
Test status
Simulation time 18453098052 ps
CPU time 44.08 seconds
Started Jun 10 05:25:35 PM PDT 24
Finished Jun 10 05:26:20 PM PDT 24
Peak memory 205184 kb
Host smart-5156d8ec-1e70-4e65-9382-8ab533ecefb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16149
97942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1614997942
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3913866417
Short name T49
Test name
Test status
Simulation time 190712843 ps
CPU time 0.91 seconds
Started Jun 10 05:25:40 PM PDT 24
Finished Jun 10 05:25:42 PM PDT 24
Peak memory 205040 kb
Host smart-4e16824b-07ed-4623-a2ae-2b77048c4fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39138
66417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3913866417
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2377825127
Short name T846
Test name
Test status
Simulation time 219613888 ps
CPU time 0.87 seconds
Started Jun 10 05:25:29 PM PDT 24
Finished Jun 10 05:25:30 PM PDT 24
Peak memory 204920 kb
Host smart-d606db7b-4ca1-4d0b-bbbb-d0058a23f37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23778
25127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2377825127
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.4019390333
Short name T1223
Test name
Test status
Simulation time 167131537 ps
CPU time 0.83 seconds
Started Jun 10 05:25:31 PM PDT 24
Finished Jun 10 05:25:32 PM PDT 24
Peak memory 205004 kb
Host smart-0658937c-ceac-425f-a1ce-d00f28243632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40193
90333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.4019390333
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.991973782
Short name T1773
Test name
Test status
Simulation time 140370874 ps
CPU time 0.74 seconds
Started Jun 10 05:25:34 PM PDT 24
Finished Jun 10 05:25:35 PM PDT 24
Peak memory 204908 kb
Host smart-7712fd6d-8b3a-4315-8ce8-1cc55a4ad264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99197
3782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.991973782
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.4109890586
Short name T1039
Test name
Test status
Simulation time 149353008 ps
CPU time 0.74 seconds
Started Jun 10 05:25:34 PM PDT 24
Finished Jun 10 05:25:35 PM PDT 24
Peak memory 204904 kb
Host smart-2abc426a-331e-4ebe-9cb3-1611bb45d5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41098
90586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.4109890586
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.2791286224
Short name T719
Test name
Test status
Simulation time 145820239 ps
CPU time 0.81 seconds
Started Jun 10 05:25:36 PM PDT 24
Finished Jun 10 05:25:38 PM PDT 24
Peak memory 204912 kb
Host smart-245179ab-b61b-4914-a63b-99722bc91eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27912
86224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2791286224
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1862081407
Short name T1149
Test name
Test status
Simulation time 180128169 ps
CPU time 0.85 seconds
Started Jun 10 05:25:29 PM PDT 24
Finished Jun 10 05:25:31 PM PDT 24
Peak memory 205008 kb
Host smart-6bf4c8e2-7bcd-4e03-8892-305499ce6ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18620
81407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1862081407
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.1645139309
Short name T2103
Test name
Test status
Simulation time 163487670 ps
CPU time 0.82 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:31 PM PDT 24
Peak memory 204916 kb
Host smart-d756d3dd-7576-4af3-a77e-2b825ea11054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16451
39309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.1645139309
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.2699132555
Short name T1324
Test name
Test status
Simulation time 4486731513 ps
CPU time 127.11 seconds
Started Jun 10 05:25:36 PM PDT 24
Finished Jun 10 05:27:43 PM PDT 24
Peak memory 205192 kb
Host smart-f7980695-cb8e-432d-bb88-70d97fdfbab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26991
32555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.2699132555
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.4256420381
Short name T1294
Test name
Test status
Simulation time 254846176 ps
CPU time 0.93 seconds
Started Jun 10 05:25:35 PM PDT 24
Finished Jun 10 05:25:36 PM PDT 24
Peak memory 205036 kb
Host smart-cfba7f4f-47e4-43fb-adbc-c80b8924f2c5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4256420381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.4256420381
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.1674668255
Short name T1182
Test name
Test status
Simulation time 223354323 ps
CPU time 0.89 seconds
Started Jun 10 05:25:33 PM PDT 24
Finished Jun 10 05:25:34 PM PDT 24
Peak memory 205008 kb
Host smart-0ed37fbd-d1db-4553-bcb1-efbe1b35a3cb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1674668255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.1674668255
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.3423404045
Short name T638
Test name
Test status
Simulation time 214257179 ps
CPU time 0.99 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:38 PM PDT 24
Peak memory 204968 kb
Host smart-24fef067-a4b9-44fd-8526-3dae5c843ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34234
04045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.3423404045
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.93857348
Short name T841
Test name
Test status
Simulation time 4198665806 ps
CPU time 5.79 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:37 PM PDT 24
Peak memory 205076 kb
Host smart-a0e6cd62-0303-4936-b2e6-fbb7ff65b441
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=93857348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.93857348
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2323061181
Short name T685
Test name
Test status
Simulation time 13383337113 ps
CPU time 14.58 seconds
Started Jun 10 05:25:32 PM PDT 24
Finished Jun 10 05:25:47 PM PDT 24
Peak memory 205088 kb
Host smart-cbfa13f9-5625-4550-803b-e6698bf7819f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2323061181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2323061181
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1431263752
Short name T16
Test name
Test status
Simulation time 23337858042 ps
CPU time 23.97 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:54 PM PDT 24
Peak memory 205096 kb
Host smart-8ceba8af-da87-4c7c-b733-1f4e20532d1c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1431263752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.1431263752
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3489751291
Short name T491
Test name
Test status
Simulation time 156421574 ps
CPU time 0.78 seconds
Started Jun 10 05:25:36 PM PDT 24
Finished Jun 10 05:25:37 PM PDT 24
Peak memory 205028 kb
Host smart-7f31bc2c-99c2-4fda-a47d-91d3a41ece97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34897
51291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3489751291
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3019898926
Short name T56
Test name
Test status
Simulation time 175619315 ps
CPU time 0.79 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:31 PM PDT 24
Peak memory 204888 kb
Host smart-e2e99071-2ac9-42a6-9a7d-4c26b7ce5fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30198
98926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3019898926
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.650369490
Short name T217
Test name
Test status
Simulation time 963134819 ps
CPU time 2.47 seconds
Started Jun 10 05:25:34 PM PDT 24
Finished Jun 10 05:25:37 PM PDT 24
Peak memory 205088 kb
Host smart-914a1bda-5c89-40b5-9a87-9c18ec6b4bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65036
9490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.650369490
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2041493013
Short name T1846
Test name
Test status
Simulation time 139348732 ps
CPU time 0.78 seconds
Started Jun 10 05:25:32 PM PDT 24
Finished Jun 10 05:25:33 PM PDT 24
Peak memory 205024 kb
Host smart-2c5f9ce4-7b7a-4106-b16a-f22f2631313f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20414
93013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2041493013
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.3777140921
Short name T299
Test name
Test status
Simulation time 41925755 ps
CPU time 0.67 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:39 PM PDT 24
Peak memory 205020 kb
Host smart-8cc9e4fe-7eda-4f8f-aed6-401de38aabd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37771
40921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3777140921
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.3822958206
Short name T752
Test name
Test status
Simulation time 782403185 ps
CPU time 2 seconds
Started Jun 10 05:25:33 PM PDT 24
Finished Jun 10 05:25:35 PM PDT 24
Peak memory 205132 kb
Host smart-732b8122-2b8c-4db7-850f-9a0090bd5dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38229
58206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.3822958206
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.4239287703
Short name T1896
Test name
Test status
Simulation time 185427114 ps
CPU time 1.8 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:40 PM PDT 24
Peak memory 205116 kb
Host smart-a628094a-a728-424f-9d02-0fd9acdb999c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42392
87703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.4239287703
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3654692556
Short name T2051
Test name
Test status
Simulation time 246080928 ps
CPU time 0.92 seconds
Started Jun 10 05:25:35 PM PDT 24
Finished Jun 10 05:25:36 PM PDT 24
Peak memory 205032 kb
Host smart-e15cdd04-85dd-448d-8ca6-2fd6212c5a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36546
92556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3654692556
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.2195669947
Short name T1006
Test name
Test status
Simulation time 142175998 ps
CPU time 0.81 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:39 PM PDT 24
Peak memory 205032 kb
Host smart-5c3560c9-7c14-4bea-b407-86f40b4a952d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21956
69947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.2195669947
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2249688400
Short name T1232
Test name
Test status
Simulation time 169966740 ps
CPU time 0.81 seconds
Started Jun 10 05:25:38 PM PDT 24
Finished Jun 10 05:25:40 PM PDT 24
Peak memory 205000 kb
Host smart-7bcb3480-6af9-4d54-971b-e55f1083a987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22496
88400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2249688400
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.696126815
Short name T50
Test name
Test status
Simulation time 233741260 ps
CPU time 0.92 seconds
Started Jun 10 05:25:40 PM PDT 24
Finished Jun 10 05:25:41 PM PDT 24
Peak memory 204988 kb
Host smart-7274cef5-fbd0-4963-8602-2db4befb83e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69612
6815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.696126815
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.2187502909
Short name T743
Test name
Test status
Simulation time 3374543760 ps
CPU time 3.88 seconds
Started Jun 10 05:25:31 PM PDT 24
Finished Jun 10 05:25:35 PM PDT 24
Peak memory 205072 kb
Host smart-711e4ad7-0b29-434e-b93d-c94e2083b011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21875
02909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.2187502909
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1914502680
Short name T755
Test name
Test status
Simulation time 190330951 ps
CPU time 0.87 seconds
Started Jun 10 05:25:33 PM PDT 24
Finished Jun 10 05:25:34 PM PDT 24
Peak memory 204932 kb
Host smart-502dcfaa-2e4d-454d-a6fd-5c29a95cf75d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19145
02680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1914502680
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.2161475662
Short name T1316
Test name
Test status
Simulation time 7816110864 ps
CPU time 212.89 seconds
Started Jun 10 05:25:32 PM PDT 24
Finished Jun 10 05:29:05 PM PDT 24
Peak memory 205212 kb
Host smart-55d24e36-1710-46e2-8719-449a9ee52afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21614
75662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.2161475662
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3074684816
Short name T1712
Test name
Test status
Simulation time 150920823 ps
CPU time 0.81 seconds
Started Jun 10 05:25:34 PM PDT 24
Finished Jun 10 05:25:35 PM PDT 24
Peak memory 204988 kb
Host smart-c7951ff0-0921-4462-bb44-adddfd25558c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30746
84816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3074684816
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.1807836153
Short name T1594
Test name
Test status
Simulation time 183168815 ps
CPU time 0.85 seconds
Started Jun 10 05:25:36 PM PDT 24
Finished Jun 10 05:25:37 PM PDT 24
Peak memory 204988 kb
Host smart-aeba1387-df71-4f36-b6a6-791bb85e1375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18078
36153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1807836153
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1392779486
Short name T1387
Test name
Test status
Simulation time 163092844 ps
CPU time 0.87 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:38 PM PDT 24
Peak memory 205000 kb
Host smart-815f2c15-fca4-488e-9408-4388c6926493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13927
79486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1392779486
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2301560847
Short name T1141
Test name
Test status
Simulation time 162973684 ps
CPU time 0.83 seconds
Started Jun 10 05:25:36 PM PDT 24
Finished Jun 10 05:25:37 PM PDT 24
Peak memory 205020 kb
Host smart-4234570d-4211-4fc4-9003-b83336e17543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23015
60847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2301560847
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2003103471
Short name T168
Test name
Test status
Simulation time 171628439 ps
CPU time 0.86 seconds
Started Jun 10 05:25:32 PM PDT 24
Finished Jun 10 05:25:33 PM PDT 24
Peak memory 205088 kb
Host smart-1b4af3ac-de96-4b53-92dd-c7691a2e1635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20031
03471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2003103471
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_eop_single_bit_handling.2916294842
Short name T923
Test name
Test status
Simulation time 155133131 ps
CPU time 0.8 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:39 PM PDT 24
Peak memory 204988 kb
Host smart-33ad32b0-e9b6-464d-9869-ef06231e5e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29162
94842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_eop_single_bit_handling.2916294842
Directory /workspace/14.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1449641625
Short name T1845
Test name
Test status
Simulation time 159296186 ps
CPU time 0.79 seconds
Started Jun 10 05:25:36 PM PDT 24
Finished Jun 10 05:25:37 PM PDT 24
Peak memory 205048 kb
Host smart-c5c02db6-ecd6-4bf4-9bf6-d4ba0fed053a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14496
41625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1449641625
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3481999212
Short name T877
Test name
Test status
Simulation time 42855818 ps
CPU time 0.66 seconds
Started Jun 10 05:25:33 PM PDT 24
Finished Jun 10 05:25:34 PM PDT 24
Peak memory 204992 kb
Host smart-4cd52ca2-8781-4c62-a3d7-8419e7607010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34819
99212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3481999212
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.1799583202
Short name T1809
Test name
Test status
Simulation time 8727363432 ps
CPU time 21.28 seconds
Started Jun 10 05:25:38 PM PDT 24
Finished Jun 10 05:26:00 PM PDT 24
Peak memory 205180 kb
Host smart-6be8bc49-0e9e-4222-8019-bf94bf1f193d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17995
83202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.1799583202
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.1219361186
Short name T1379
Test name
Test status
Simulation time 169019521 ps
CPU time 0.79 seconds
Started Jun 10 05:25:36 PM PDT 24
Finished Jun 10 05:25:38 PM PDT 24
Peak memory 205020 kb
Host smart-26249389-1c4e-4c20-a407-92173a45b574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12193
61186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1219361186
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.123674905
Short name T2068
Test name
Test status
Simulation time 265138678 ps
CPU time 0.9 seconds
Started Jun 10 05:25:32 PM PDT 24
Finished Jun 10 05:25:33 PM PDT 24
Peak memory 205024 kb
Host smart-f6a67166-32c8-4f26-bc98-bc7fac2491a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12367
4905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.123674905
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.3507717879
Short name T762
Test name
Test status
Simulation time 164971556 ps
CPU time 0.81 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:39 PM PDT 24
Peak memory 205052 kb
Host smart-5e43e762-833d-409c-82b7-d004027571e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35077
17879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.3507717879
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.3259056408
Short name T1235
Test name
Test status
Simulation time 135784587 ps
CPU time 0.75 seconds
Started Jun 10 05:25:34 PM PDT 24
Finished Jun 10 05:25:35 PM PDT 24
Peak memory 205052 kb
Host smart-deb0e864-e207-4cf0-86d5-e40f788c1d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32590
56408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.3259056408
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2709064381
Short name T1440
Test name
Test status
Simulation time 149773083 ps
CPU time 0.77 seconds
Started Jun 10 05:25:35 PM PDT 24
Finished Jun 10 05:25:36 PM PDT 24
Peak memory 205044 kb
Host smart-91abb8a0-623a-4912-9bb0-f15b60ff376b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27090
64381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2709064381
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.120950036
Short name T1725
Test name
Test status
Simulation time 228980987 ps
CPU time 0.87 seconds
Started Jun 10 05:25:39 PM PDT 24
Finished Jun 10 05:25:41 PM PDT 24
Peak memory 205052 kb
Host smart-2215a286-cb92-4159-8bc2-7f6958a97793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12095
0036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.120950036
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2049683577
Short name T180
Test name
Test status
Simulation time 195503252 ps
CPU time 0.87 seconds
Started Jun 10 05:25:30 PM PDT 24
Finished Jun 10 05:25:32 PM PDT 24
Peak memory 204968 kb
Host smart-cea37cf7-358d-4044-8ee4-5ef44d3f122e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20496
83577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2049683577
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.309573122
Short name T819
Test name
Test status
Simulation time 172359004 ps
CPU time 0.81 seconds
Started Jun 10 05:25:38 PM PDT 24
Finished Jun 10 05:25:40 PM PDT 24
Peak memory 205028 kb
Host smart-d0b90624-f2e5-458d-a1b3-8a223ad15f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30957
3122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.309573122
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.79941918
Short name T562
Test name
Test status
Simulation time 184559064 ps
CPU time 0.83 seconds
Started Jun 10 05:25:33 PM PDT 24
Finished Jun 10 05:25:34 PM PDT 24
Peak memory 205008 kb
Host smart-b643ce25-e479-4170-9764-5a36b0ad9e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79941
918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.79941918
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.1296791490
Short name T1395
Test name
Test status
Simulation time 14756571860 ps
CPU time 390.98 seconds
Started Jun 10 05:25:35 PM PDT 24
Finished Jun 10 05:32:06 PM PDT 24
Peak memory 205180 kb
Host smart-23288569-56ab-4f93-9013-5382520b8790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12967
91490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.1296791490
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.1506611427
Short name T1658
Test name
Test status
Simulation time 274664833 ps
CPU time 0.98 seconds
Started Jun 10 05:25:39 PM PDT 24
Finished Jun 10 05:25:41 PM PDT 24
Peak memory 205012 kb
Host smart-0698f41b-3ed3-4271-8125-b62e8ab1f4da
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1506611427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.1506611427
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.2246098097
Short name T1315
Test name
Test status
Simulation time 163039055 ps
CPU time 0.79 seconds
Started Jun 10 05:25:40 PM PDT 24
Finished Jun 10 05:25:42 PM PDT 24
Peak memory 204980 kb
Host smart-4a0fe65a-b77c-43ee-ba7f-257d2434653d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2246098097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.2246098097
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.2679048055
Short name T710
Test name
Test status
Simulation time 186282541 ps
CPU time 0.86 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:25:47 PM PDT 24
Peak memory 204948 kb
Host smart-9f3d7093-3748-43e0-9cc9-04f6d4f63dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26790
48055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.2679048055
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.1268201756
Short name T782
Test name
Test status
Simulation time 4158948001 ps
CPU time 4.84 seconds
Started Jun 10 05:25:39 PM PDT 24
Finished Jun 10 05:25:45 PM PDT 24
Peak memory 205100 kb
Host smart-7d7ee5da-1df5-4b14-97dd-cd51a2923891
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1268201756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.1268201756
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.2348232795
Short name T45
Test name
Test status
Simulation time 13349401721 ps
CPU time 14.21 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:52 PM PDT 24
Peak memory 205044 kb
Host smart-8f612b44-949e-44dc-9694-d36fea3c298d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2348232795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.2348232795
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.1208500686
Short name T1702
Test name
Test status
Simulation time 23400375425 ps
CPU time 24.04 seconds
Started Jun 10 05:25:45 PM PDT 24
Finished Jun 10 05:26:10 PM PDT 24
Peak memory 205076 kb
Host smart-b1f6ad1d-aeb1-4694-a476-7c1e38dec211
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1208500686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.1208500686
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.4277278733
Short name T354
Test name
Test status
Simulation time 216156031 ps
CPU time 0.88 seconds
Started Jun 10 05:25:39 PM PDT 24
Finished Jun 10 05:25:40 PM PDT 24
Peak memory 205008 kb
Host smart-19ad2e20-a754-4b00-bb6b-b34ef95432e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42772
78733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.4277278733
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2010132657
Short name T1830
Test name
Test status
Simulation time 808510930 ps
CPU time 1.97 seconds
Started Jun 10 05:25:35 PM PDT 24
Finished Jun 10 05:25:37 PM PDT 24
Peak memory 205144 kb
Host smart-6c7b2833-67e0-4e19-84a1-c985ee368fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20101
32657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2010132657
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.1748964735
Short name T1973
Test name
Test status
Simulation time 142047132 ps
CPU time 0.78 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:39 PM PDT 24
Peak memory 205076 kb
Host smart-c861e24c-1697-493f-bb0c-d61245a0cebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17489
64735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1748964735
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.619147333
Short name T397
Test name
Test status
Simulation time 61923387 ps
CPU time 0.68 seconds
Started Jun 10 05:25:40 PM PDT 24
Finished Jun 10 05:25:42 PM PDT 24
Peak memory 205024 kb
Host smart-1869f004-3e46-4d20-b72a-17a59ed4e78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61914
7333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.619147333
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.2024670502
Short name T1764
Test name
Test status
Simulation time 910832253 ps
CPU time 2.34 seconds
Started Jun 10 05:25:39 PM PDT 24
Finished Jun 10 05:25:42 PM PDT 24
Peak memory 205088 kb
Host smart-bfbb0e49-7fc5-4a96-b341-4648c3237417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20246
70502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.2024670502
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3772877607
Short name T1600
Test name
Test status
Simulation time 213365138 ps
CPU time 1.9 seconds
Started Jun 10 05:25:38 PM PDT 24
Finished Jun 10 05:25:41 PM PDT 24
Peak memory 205036 kb
Host smart-657d3fad-6d19-4f36-9f5d-ae59d0e82c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37728
77607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3772877607
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.94667044
Short name T788
Test name
Test status
Simulation time 221492187 ps
CPU time 1.01 seconds
Started Jun 10 05:25:40 PM PDT 24
Finished Jun 10 05:25:42 PM PDT 24
Peak memory 204880 kb
Host smart-5dc4cfd0-3a40-4d76-91c5-ae134801ad84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94667
044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.94667044
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2997902069
Short name T455
Test name
Test status
Simulation time 151488764 ps
CPU time 0.76 seconds
Started Jun 10 05:25:39 PM PDT 24
Finished Jun 10 05:25:41 PM PDT 24
Peak memory 205056 kb
Host smart-ba6c3a25-0eeb-4493-a9d1-584a1c5057d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29979
02069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2997902069
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.914655865
Short name T1743
Test name
Test status
Simulation time 221701084 ps
CPU time 1.03 seconds
Started Jun 10 05:25:38 PM PDT 24
Finished Jun 10 05:25:40 PM PDT 24
Peak memory 205008 kb
Host smart-43372a47-085e-4ccc-9823-d79015120014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91465
5865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.914655865
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3926485294
Short name T1333
Test name
Test status
Simulation time 268426435 ps
CPU time 0.97 seconds
Started Jun 10 05:25:39 PM PDT 24
Finished Jun 10 05:25:41 PM PDT 24
Peak memory 205004 kb
Host smart-f9bb2802-f194-4a34-b447-8f9395c4fcca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39264
85294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3926485294
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.3190367649
Short name T1771
Test name
Test status
Simulation time 3330012043 ps
CPU time 4.61 seconds
Started Jun 10 05:25:35 PM PDT 24
Finished Jun 10 05:25:40 PM PDT 24
Peak memory 205112 kb
Host smart-9e0f1e57-0b38-4e19-b8a6-63b6392a6e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31903
67649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.3190367649
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3989318320
Short name T616
Test name
Test status
Simulation time 188360857 ps
CPU time 0.88 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:38 PM PDT 24
Peak memory 205176 kb
Host smart-abc7baeb-ec77-409b-91bb-15643b9eeeec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39893
18320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3989318320
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.3887404213
Short name T1982
Test name
Test status
Simulation time 11632717468 ps
CPU time 353.08 seconds
Started Jun 10 05:25:42 PM PDT 24
Finished Jun 10 05:31:36 PM PDT 24
Peak memory 205224 kb
Host smart-54e0a13d-6828-4340-b1b4-dc71c2d0bfef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38874
04213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.3887404213
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.326512466
Short name T2104
Test name
Test status
Simulation time 149149871 ps
CPU time 0.78 seconds
Started Jun 10 05:25:45 PM PDT 24
Finished Jun 10 05:25:46 PM PDT 24
Peak memory 204992 kb
Host smart-696c5734-c275-41be-b905-c3a0ec837425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32651
2466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.326512466
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.3841913546
Short name T1291
Test name
Test status
Simulation time 156370779 ps
CPU time 0.8 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:38 PM PDT 24
Peak memory 205076 kb
Host smart-7632b80c-a394-4143-a947-2fe276bf74f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38419
13546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.3841913546
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.622271717
Short name T799
Test name
Test status
Simulation time 166900279 ps
CPU time 0.78 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:39 PM PDT 24
Peak memory 205108 kb
Host smart-82708847-b46f-47ef-8596-7e805ab963e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62227
1717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.622271717
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2394827194
Short name T1464
Test name
Test status
Simulation time 167921168 ps
CPU time 0.81 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:25:52 PM PDT 24
Peak memory 204984 kb
Host smart-b8c1414c-7f0b-462d-bff8-1de221549865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23948
27194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2394827194
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1665550288
Short name T946
Test name
Test status
Simulation time 221304234 ps
CPU time 0.83 seconds
Started Jun 10 05:25:39 PM PDT 24
Finished Jun 10 05:25:41 PM PDT 24
Peak memory 205080 kb
Host smart-9dbfe90a-a4b6-4479-98bf-e3e3900eb341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16655
50288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1665550288
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_eop_single_bit_handling.394961347
Short name T1575
Test name
Test status
Simulation time 191737153 ps
CPU time 0.84 seconds
Started Jun 10 05:25:40 PM PDT 24
Finished Jun 10 05:25:42 PM PDT 24
Peak memory 204816 kb
Host smart-38f3ada1-4853-4393-bd4e-19cd553192dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39496
1347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_eop_single_bit_handling.394961347
Directory /workspace/15.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3261065827
Short name T1549
Test name
Test status
Simulation time 180230982 ps
CPU time 0.8 seconds
Started Jun 10 05:25:39 PM PDT 24
Finished Jun 10 05:25:41 PM PDT 24
Peak memory 205052 kb
Host smart-792eb1f6-47da-4dd9-93c6-a8e2d62ca124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32610
65827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3261065827
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.2892703569
Short name T1208
Test name
Test status
Simulation time 45585888 ps
CPU time 0.75 seconds
Started Jun 10 05:25:41 PM PDT 24
Finished Jun 10 05:25:42 PM PDT 24
Peak memory 205004 kb
Host smart-c458014b-6d9f-46bf-9eff-6e466664e7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28927
03569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.2892703569
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1149417
Short name T1912
Test name
Test status
Simulation time 7374023390 ps
CPU time 17.8 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:26:04 PM PDT 24
Peak memory 205228 kb
Host smart-0ddaf264-d0c4-4261-9662-047adc15ae56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11494
17 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1149417
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.3218642400
Short name T621
Test name
Test status
Simulation time 191740167 ps
CPU time 0.87 seconds
Started Jun 10 05:25:36 PM PDT 24
Finished Jun 10 05:25:37 PM PDT 24
Peak memory 205144 kb
Host smart-f8fe726d-1c73-4652-aaa5-27c18807ec9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32186
42400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.3218642400
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2247777890
Short name T605
Test name
Test status
Simulation time 215768087 ps
CPU time 0.86 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:25:47 PM PDT 24
Peak memory 204984 kb
Host smart-9796982c-786f-48ed-a546-159f32ef021a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22477
77890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2247777890
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.581797304
Short name T1956
Test name
Test status
Simulation time 168082651 ps
CPU time 0.88 seconds
Started Jun 10 05:25:37 PM PDT 24
Finished Jun 10 05:25:39 PM PDT 24
Peak memory 205032 kb
Host smart-539ca742-2a78-41f2-a317-fdc7c1c430af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58179
7304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.581797304
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.2399571367
Short name T1537
Test name
Test status
Simulation time 142434548 ps
CPU time 0.75 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:25:48 PM PDT 24
Peak memory 204988 kb
Host smart-30f21661-c803-4295-bee3-43ec74a493f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23995
71367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2399571367
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3210955331
Short name T2025
Test name
Test status
Simulation time 164156286 ps
CPU time 0.81 seconds
Started Jun 10 05:25:41 PM PDT 24
Finished Jun 10 05:25:42 PM PDT 24
Peak memory 205012 kb
Host smart-f6003309-19eb-4d57-84c4-4d3421c03ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32109
55331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3210955331
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.38651496
Short name T1557
Test name
Test status
Simulation time 143900576 ps
CPU time 0.72 seconds
Started Jun 10 05:25:39 PM PDT 24
Finished Jun 10 05:25:41 PM PDT 24
Peak memory 204764 kb
Host smart-2ef09771-f379-408c-a1ef-c4a1a0eca622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38651
496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.38651496
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.809585516
Short name T1807
Test name
Test status
Simulation time 204471270 ps
CPU time 0.99 seconds
Started Jun 10 05:25:38 PM PDT 24
Finished Jun 10 05:25:40 PM PDT 24
Peak memory 205008 kb
Host smart-35479adf-1263-4dff-a8d8-4f74863ec55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80958
5516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.809585516
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.2806802535
Short name T1933
Test name
Test status
Simulation time 190993209 ps
CPU time 0.87 seconds
Started Jun 10 05:25:43 PM PDT 24
Finished Jun 10 05:25:45 PM PDT 24
Peak memory 205008 kb
Host smart-9456f8a2-11e9-4742-b545-6b44017c7370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28068
02535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2806802535
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.4001533716
Short name T1758
Test name
Test status
Simulation time 151345371 ps
CPU time 0.85 seconds
Started Jun 10 05:25:42 PM PDT 24
Finished Jun 10 05:25:43 PM PDT 24
Peak memory 205032 kb
Host smart-1125c463-dbec-4424-a9ae-1d57c3dedeb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40015
33716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.4001533716
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.1339484418
Short name T1125
Test name
Test status
Simulation time 8605677827 ps
CPU time 63.46 seconds
Started Jun 10 05:25:44 PM PDT 24
Finished Jun 10 05:26:47 PM PDT 24
Peak memory 205144 kb
Host smart-b45793d5-329d-412e-a1ef-0ccbc4501e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13394
84418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.1339484418
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.3238922042
Short name T1880
Test name
Test status
Simulation time 245676089 ps
CPU time 0.96 seconds
Started Jun 10 05:25:49 PM PDT 24
Finished Jun 10 05:25:50 PM PDT 24
Peak memory 205040 kb
Host smart-69ab4056-958b-4599-89f4-7c8c33ce469e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3238922042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.3238922042
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.142514191
Short name T481
Test name
Test status
Simulation time 205584663 ps
CPU time 0.85 seconds
Started Jun 10 05:25:47 PM PDT 24
Finished Jun 10 05:25:48 PM PDT 24
Peak memory 204988 kb
Host smart-b26ef19f-05f2-4cee-8eb9-97cd1dadaa74
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=142514191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.142514191
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.2588082024
Short name T1423
Test name
Test status
Simulation time 163419498 ps
CPU time 0.84 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 204984 kb
Host smart-2c1ae899-684c-4ff8-88fa-a594deb2f671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25880
82024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.2588082024
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.863673432
Short name T902
Test name
Test status
Simulation time 3986980080 ps
CPU time 4.9 seconds
Started Jun 10 05:25:40 PM PDT 24
Finished Jun 10 05:25:46 PM PDT 24
Peak memory 205068 kb
Host smart-544f3e1d-33a5-4009-8c30-49586efc8403
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=863673432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.863673432
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.4037909912
Short name T1571
Test name
Test status
Simulation time 13319593899 ps
CPU time 13.36 seconds
Started Jun 10 05:25:44 PM PDT 24
Finished Jun 10 05:25:58 PM PDT 24
Peak memory 205120 kb
Host smart-126ab7a5-3fcb-409a-9ab6-08fb06e13e2a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4037909912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.4037909912
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.3700089709
Short name T610
Test name
Test status
Simulation time 23318742940 ps
CPU time 24.27 seconds
Started Jun 10 05:25:41 PM PDT 24
Finished Jun 10 05:26:06 PM PDT 24
Peak memory 205344 kb
Host smart-4c1663dc-a039-46e7-96a4-9cdc1241d5bc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3700089709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.3700089709
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2024661091
Short name T1955
Test name
Test status
Simulation time 206879700 ps
CPU time 0.84 seconds
Started Jun 10 05:25:43 PM PDT 24
Finished Jun 10 05:25:44 PM PDT 24
Peak memory 205004 kb
Host smart-c9e68913-8956-4447-9c70-b01e7bf03908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20246
61091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2024661091
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.236353876
Short name T1709
Test name
Test status
Simulation time 171041957 ps
CPU time 0.76 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:25:47 PM PDT 24
Peak memory 204964 kb
Host smart-d84ca216-85fc-4abe-b6dd-e9acd6b64628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23635
3876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.236353876
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3138919152
Short name T207
Test name
Test status
Simulation time 1273371185 ps
CPU time 2.97 seconds
Started Jun 10 05:25:42 PM PDT 24
Finished Jun 10 05:25:45 PM PDT 24
Peak memory 205080 kb
Host smart-00f80e14-22d7-4fc3-b757-7a330ae80a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31389
19152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3138919152
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.1778182020
Short name T976
Test name
Test status
Simulation time 132622850 ps
CPU time 0.86 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:25:48 PM PDT 24
Peak memory 204980 kb
Host smart-dbda9c98-7522-451c-a839-1005be4899cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17781
82020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.1778182020
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.320650411
Short name T767
Test name
Test status
Simulation time 39985996 ps
CPU time 0.66 seconds
Started Jun 10 05:25:44 PM PDT 24
Finished Jun 10 05:25:45 PM PDT 24
Peak memory 205000 kb
Host smart-6c479bf4-abf6-4a44-a04c-f94c96f44229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32065
0411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.320650411
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1722763444
Short name T1055
Test name
Test status
Simulation time 1003963067 ps
CPU time 2.57 seconds
Started Jun 10 05:25:41 PM PDT 24
Finished Jun 10 05:25:44 PM PDT 24
Peak memory 205108 kb
Host smart-389b9864-5224-4e7b-8512-5baec0e7e3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17227
63444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1722763444
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.184658552
Short name T85
Test name
Test status
Simulation time 243163871 ps
CPU time 1.66 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:25:48 PM PDT 24
Peak memory 205128 kb
Host smart-36d8b501-31a5-4bb4-9d8b-7bd4ffbc9abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18465
8552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.184658552
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.952334995
Short name T559
Test name
Test status
Simulation time 158540188 ps
CPU time 0.75 seconds
Started Jun 10 05:25:47 PM PDT 24
Finished Jun 10 05:25:48 PM PDT 24
Peak memory 204988 kb
Host smart-e113b65b-0014-44e3-91b0-74bc527aa0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95233
4995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.952334995
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.20407222
Short name T1402
Test name
Test status
Simulation time 138221576 ps
CPU time 0.73 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:25:47 PM PDT 24
Peak memory 204996 kb
Host smart-57e24101-8e4c-4ac7-b3a1-96e06f6537d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20407
222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.20407222
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.3782644755
Short name T1238
Test name
Test status
Simulation time 150994714 ps
CPU time 0.9 seconds
Started Jun 10 05:25:43 PM PDT 24
Finished Jun 10 05:25:44 PM PDT 24
Peak memory 205048 kb
Host smart-d7aafbd8-cde0-42bb-9b22-2c6d1112301c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37826
44755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.3782644755
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.4234461403
Short name T861
Test name
Test status
Simulation time 230910627 ps
CPU time 0.9 seconds
Started Jun 10 05:25:40 PM PDT 24
Finished Jun 10 05:25:42 PM PDT 24
Peak memory 205008 kb
Host smart-a9c769d8-e347-43da-b2c9-e68487f44727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42344
61403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.4234461403
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2140353459
Short name T1014
Test name
Test status
Simulation time 3302383905 ps
CPU time 4.94 seconds
Started Jun 10 05:25:44 PM PDT 24
Finished Jun 10 05:25:49 PM PDT 24
Peak memory 205096 kb
Host smart-86330a5b-4b3e-47be-84b6-598ad83b0386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21403
53459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2140353459
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3868216249
Short name T1305
Test name
Test status
Simulation time 191800956 ps
CPU time 0.87 seconds
Started Jun 10 05:25:41 PM PDT 24
Finished Jun 10 05:25:42 PM PDT 24
Peak memory 204988 kb
Host smart-0b37bdfe-25b4-4160-a735-020a05210ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38682
16249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3868216249
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.1255679379
Short name T547
Test name
Test status
Simulation time 6341446897 ps
CPU time 61.29 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:26:48 PM PDT 24
Peak memory 205188 kb
Host smart-3d308374-a372-462e-be87-ee69c38ffd0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12556
79379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.1255679379
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3994243520
Short name T1453
Test name
Test status
Simulation time 149466533 ps
CPU time 0.79 seconds
Started Jun 10 05:25:40 PM PDT 24
Finished Jun 10 05:25:41 PM PDT 24
Peak memory 205024 kb
Host smart-6a48a374-e68e-4f89-90c0-b2bdfc69baf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39942
43520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3994243520
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3218634221
Short name T964
Test name
Test status
Simulation time 223365687 ps
CPU time 0.93 seconds
Started Jun 10 05:25:47 PM PDT 24
Finished Jun 10 05:25:49 PM PDT 24
Peak memory 204928 kb
Host smart-acfc2431-cfc8-4301-bc83-b365217bc79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32186
34221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3218634221
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.3282177652
Short name T709
Test name
Test status
Simulation time 198407915 ps
CPU time 0.86 seconds
Started Jun 10 05:25:48 PM PDT 24
Finished Jun 10 05:25:49 PM PDT 24
Peak memory 205044 kb
Host smart-182dc058-d4da-41e1-a5cd-c176168d7271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32821
77652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.3282177652
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2332005330
Short name T1858
Test name
Test status
Simulation time 165086509 ps
CPU time 0.78 seconds
Started Jun 10 05:25:51 PM PDT 24
Finished Jun 10 05:25:52 PM PDT 24
Peak memory 205056 kb
Host smart-949c6d5c-6616-439b-9a33-5d88181d834a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23320
05330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2332005330
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2970556287
Short name T432
Test name
Test status
Simulation time 177847694 ps
CPU time 0.82 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:54 PM PDT 24
Peak memory 204988 kb
Host smart-4382349b-6d04-4132-a438-a7d00c0d7a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29705
56287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2970556287
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.1771909087
Short name T1278
Test name
Test status
Simulation time 176310241 ps
CPU time 0.78 seconds
Started Jun 10 05:25:49 PM PDT 24
Finished Jun 10 05:25:50 PM PDT 24
Peak memory 205020 kb
Host smart-5b10cdf7-a27e-4108-9ee2-34f8d8b1fee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17719
09087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.1771909087
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_eop_single_bit_handling.4018642014
Short name T1392
Test name
Test status
Simulation time 185109210 ps
CPU time 0.82 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 204988 kb
Host smart-c409ad32-a3f5-4cbe-b2e5-f7337367d726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40186
42014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_eop_single_bit_handling.4018642014
Directory /workspace/16.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1695060354
Short name T849
Test name
Test status
Simulation time 167684875 ps
CPU time 0.95 seconds
Started Jun 10 05:25:48 PM PDT 24
Finished Jun 10 05:25:49 PM PDT 24
Peak memory 205008 kb
Host smart-46eae09b-8554-463d-aae1-4827be8fffbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16950
60354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1695060354
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.3690460791
Short name T1447
Test name
Test status
Simulation time 59300623 ps
CPU time 0.67 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:54 PM PDT 24
Peak memory 204976 kb
Host smart-779e0a50-d1b5-4e47-96d2-468fdc914150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36904
60791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3690460791
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2844529938
Short name T592
Test name
Test status
Simulation time 178604876 ps
CPU time 0.82 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:25:47 PM PDT 24
Peak memory 205004 kb
Host smart-021a9cb3-17f8-4747-82b9-31a75757efeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28445
29938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2844529938
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2979263800
Short name T829
Test name
Test status
Simulation time 230193529 ps
CPU time 0.88 seconds
Started Jun 10 05:25:50 PM PDT 24
Finished Jun 10 05:25:51 PM PDT 24
Peak memory 205000 kb
Host smart-0bab8c31-0bd9-4854-9a29-effc5d3ea276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29792
63800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2979263800
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.1830826241
Short name T1632
Test name
Test status
Simulation time 175768383 ps
CPU time 0.86 seconds
Started Jun 10 05:25:51 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 205016 kb
Host smart-5754b43e-baab-45c0-801f-cbd6b979bf82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18308
26241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.1830826241
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.765601847
Short name T553
Test name
Test status
Simulation time 189780503 ps
CPU time 0.8 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:25:48 PM PDT 24
Peak memory 205012 kb
Host smart-6330591b-7a81-42e9-af71-9ba218f63acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76560
1847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.765601847
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3634175910
Short name T1137
Test name
Test status
Simulation time 151179549 ps
CPU time 0.77 seconds
Started Jun 10 05:25:47 PM PDT 24
Finished Jun 10 05:25:49 PM PDT 24
Peak memory 205004 kb
Host smart-fb8b182d-180b-4f43-983c-ec1ec60f0f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36341
75910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3634175910
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1572704499
Short name T1671
Test name
Test status
Simulation time 161869996 ps
CPU time 0.81 seconds
Started Jun 10 05:25:44 PM PDT 24
Finished Jun 10 05:25:46 PM PDT 24
Peak memory 205064 kb
Host smart-239db665-d6d6-449b-8e33-1039bb144e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15727
04499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1572704499
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2701389017
Short name T537
Test name
Test status
Simulation time 151404035 ps
CPU time 0.78 seconds
Started Jun 10 05:25:50 PM PDT 24
Finished Jun 10 05:25:51 PM PDT 24
Peak memory 205040 kb
Host smart-f32e10c2-22af-4a71-a1b4-aacce0c2551a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27013
89017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2701389017
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.885090686
Short name T1135
Test name
Test status
Simulation time 226691868 ps
CPU time 0.94 seconds
Started Jun 10 05:25:53 PM PDT 24
Finished Jun 10 05:25:55 PM PDT 24
Peak memory 205008 kb
Host smart-94f23852-9980-4efd-92ac-5eb84cf574cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88509
0686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.885090686
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.738715670
Short name T1092
Test name
Test status
Simulation time 6029010124 ps
CPU time 57.24 seconds
Started Jun 10 05:25:45 PM PDT 24
Finished Jun 10 05:26:42 PM PDT 24
Peak memory 205144 kb
Host smart-64658d5b-6a41-41bd-a77e-a08f82438279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73871
5670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.738715670
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.1502736040
Short name T1123
Test name
Test status
Simulation time 236023122 ps
CPU time 0.89 seconds
Started Jun 10 05:25:56 PM PDT 24
Finished Jun 10 05:25:57 PM PDT 24
Peak memory 205028 kb
Host smart-ee62c940-b0b9-4685-b8fa-c34a3096c72c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1502736040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.1502736040
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.851699456
Short name T815
Test name
Test status
Simulation time 162664118 ps
CPU time 0.82 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 204984 kb
Host smart-17ab9e67-6b01-4878-ad8d-4555b140c30a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=851699456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.851699456
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.481597308
Short name T1490
Test name
Test status
Simulation time 211289939 ps
CPU time 0.86 seconds
Started Jun 10 05:25:51 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 204992 kb
Host smart-6adac656-e885-457c-b3f2-79ebaf2af829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48159
7308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.481597308
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.2977236304
Short name T865
Test name
Test status
Simulation time 3702926423 ps
CPU time 5.17 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:57 PM PDT 24
Peak memory 205172 kb
Host smart-aa95a073-1b7b-43d5-9fc8-1928fc6307aa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2977236304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.2977236304
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3554328145
Short name T1628
Test name
Test status
Simulation time 13385550490 ps
CPU time 14.1 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:26:01 PM PDT 24
Peak memory 205184 kb
Host smart-c985f3a8-adaa-43e3-bc4c-b029410c03e5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3554328145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3554328145
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.528661785
Short name T1910
Test name
Test status
Simulation time 23496112150 ps
CPU time 25.39 seconds
Started Jun 10 05:25:46 PM PDT 24
Finished Jun 10 05:26:12 PM PDT 24
Peak memory 205180 kb
Host smart-2dbbe326-6f40-43d5-9745-f487dbdda6d8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=528661785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.528661785
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2396622429
Short name T129
Test name
Test status
Simulation time 154845841 ps
CPU time 0.81 seconds
Started Jun 10 05:25:47 PM PDT 24
Finished Jun 10 05:25:48 PM PDT 24
Peak memory 204956 kb
Host smart-3c0d5a6c-4eb4-4d39-818d-2e47ca0ed3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23966
22429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2396622429
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.3340744046
Short name T715
Test name
Test status
Simulation time 145380355 ps
CPU time 0.78 seconds
Started Jun 10 05:25:51 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 204984 kb
Host smart-af9b3a38-e019-4207-9a52-5a49e60f0cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33407
44046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.3340744046
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1286704201
Short name T1224
Test name
Test status
Simulation time 710138069 ps
CPU time 1.77 seconds
Started Jun 10 05:25:50 PM PDT 24
Finished Jun 10 05:25:52 PM PDT 24
Peak memory 205096 kb
Host smart-279437fc-b3ec-4473-a54e-b4ff701fde49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12867
04201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1286704201
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.1925803690
Short name T1892
Test name
Test status
Simulation time 202900968 ps
CPU time 0.81 seconds
Started Jun 10 05:25:48 PM PDT 24
Finished Jun 10 05:25:49 PM PDT 24
Peak memory 204920 kb
Host smart-481db6e6-e13e-4cd9-a254-7ba7ee1c2cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19258
03690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.1925803690
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.1514392014
Short name T1226
Test name
Test status
Simulation time 64153693 ps
CPU time 0.7 seconds
Started Jun 10 05:25:56 PM PDT 24
Finished Jun 10 05:25:57 PM PDT 24
Peak memory 205004 kb
Host smart-bbb3979a-baa6-4c62-a702-3e6c3e37e7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15143
92014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1514392014
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.1430391062
Short name T595
Test name
Test status
Simulation time 923992592 ps
CPU time 2.65 seconds
Started Jun 10 05:25:56 PM PDT 24
Finished Jun 10 05:25:59 PM PDT 24
Peak memory 205096 kb
Host smart-0b6a407d-6129-4bdd-b8b3-c9931f0af89a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14303
91062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.1430391062
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.304076480
Short name T622
Test name
Test status
Simulation time 157949333 ps
CPU time 1.4 seconds
Started Jun 10 05:25:44 PM PDT 24
Finished Jun 10 05:25:46 PM PDT 24
Peak memory 205164 kb
Host smart-74dc8f49-c9b3-4506-9eea-c62786f803bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30407
6480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.304076480
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.3885250742
Short name T897
Test name
Test status
Simulation time 174451326 ps
CPU time 0.85 seconds
Started Jun 10 05:25:56 PM PDT 24
Finished Jun 10 05:25:57 PM PDT 24
Peak memory 204932 kb
Host smart-73ec38ea-6dc1-4f8e-91ae-625fe753bb9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38852
50742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.3885250742
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3709667724
Short name T483
Test name
Test status
Simulation time 147405703 ps
CPU time 0.74 seconds
Started Jun 10 05:25:51 PM PDT 24
Finished Jun 10 05:25:52 PM PDT 24
Peak memory 205000 kb
Host smart-9ddaba00-8626-4fbe-ae22-4f496bd5447b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37096
67724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3709667724
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.628724315
Short name T1806
Test name
Test status
Simulation time 202072393 ps
CPU time 0.87 seconds
Started Jun 10 05:25:51 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 205004 kb
Host smart-5cd51b9b-33e2-4380-8882-d90f5b0ad00a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62872
4315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.628724315
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2255160849
Short name T740
Test name
Test status
Simulation time 205696093 ps
CPU time 0.85 seconds
Started Jun 10 05:25:48 PM PDT 24
Finished Jun 10 05:25:49 PM PDT 24
Peak memory 204984 kb
Host smart-197788f7-861a-40b8-b67f-7d668ecb4c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22551
60849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2255160849
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.46497579
Short name T1170
Test name
Test status
Simulation time 3339142511 ps
CPU time 4.01 seconds
Started Jun 10 05:25:56 PM PDT 24
Finished Jun 10 05:26:00 PM PDT 24
Peak memory 205028 kb
Host smart-89d3f929-8dd5-4ea7-acf2-1c5d2c79a104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46497
579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.46497579
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.602584905
Short name T1202
Test name
Test status
Simulation time 226792948 ps
CPU time 0.91 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 205020 kb
Host smart-a9dfce30-562b-4f54-853c-d9a6f05474ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60258
4905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.602584905
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.3777757327
Short name T1048
Test name
Test status
Simulation time 15012051506 ps
CPU time 112.9 seconds
Started Jun 10 05:25:51 PM PDT 24
Finished Jun 10 05:27:44 PM PDT 24
Peak memory 205304 kb
Host smart-cb499673-a0cd-4af1-9bf8-e5d131d4df5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37777
57327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.3777757327
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1556605079
Short name T742
Test name
Test status
Simulation time 168205397 ps
CPU time 0.78 seconds
Started Jun 10 05:25:47 PM PDT 24
Finished Jun 10 05:25:48 PM PDT 24
Peak memory 204996 kb
Host smart-c698f759-d2a2-4fa2-8254-83a1e4ba19bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15566
05079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1556605079
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1565095791
Short name T525
Test name
Test status
Simulation time 165534435 ps
CPU time 0.78 seconds
Started Jun 10 05:25:53 PM PDT 24
Finished Jun 10 05:25:55 PM PDT 24
Peak memory 204996 kb
Host smart-4e34b6fd-a420-4bcc-a28e-c549c7432db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15650
95791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1565095791
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1593607684
Short name T1300
Test name
Test status
Simulation time 151867622 ps
CPU time 0.83 seconds
Started Jun 10 05:25:51 PM PDT 24
Finished Jun 10 05:25:52 PM PDT 24
Peak memory 205016 kb
Host smart-3184f4ff-5ef9-45f3-9dc3-3e075308dc3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15936
07684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1593607684
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3780233793
Short name T1169
Test name
Test status
Simulation time 160842134 ps
CPU time 0.77 seconds
Started Jun 10 05:25:54 PM PDT 24
Finished Jun 10 05:26:00 PM PDT 24
Peak memory 205004 kb
Host smart-fbbc105f-3538-4e62-bc2f-817f917de78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37802
33793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3780233793
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.4069854082
Short name T167
Test name
Test status
Simulation time 165726080 ps
CPU time 0.79 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:54 PM PDT 24
Peak memory 204980 kb
Host smart-9b1b67c9-5569-46f4-ae76-36849cd55964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40698
54082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.4069854082
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_eop_single_bit_handling.2927491138
Short name T1358
Test name
Test status
Simulation time 223478513 ps
CPU time 0.94 seconds
Started Jun 10 05:25:51 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 205008 kb
Host smart-21621382-8df4-41ee-bf43-04a34ac7bea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29274
91138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_eop_single_bit_handling.2927491138
Directory /workspace/17.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2313797341
Short name T892
Test name
Test status
Simulation time 74032372 ps
CPU time 0.7 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:54 PM PDT 24
Peak memory 204984 kb
Host smart-9dd83449-3481-4326-ae44-5102c69a1225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23137
97341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2313797341
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1396469133
Short name T1088
Test name
Test status
Simulation time 16714097053 ps
CPU time 40.8 seconds
Started Jun 10 05:25:58 PM PDT 24
Finished Jun 10 05:26:39 PM PDT 24
Peak memory 205200 kb
Host smart-45bcee49-b22d-49c0-97e9-adda8777e0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13964
69133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1396469133
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2664115521
Short name T1720
Test name
Test status
Simulation time 161532673 ps
CPU time 0.82 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:54 PM PDT 24
Peak memory 204984 kb
Host smart-6329fdae-0826-41f2-b7df-5193522081bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26641
15521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2664115521
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3675582342
Short name T1552
Test name
Test status
Simulation time 204524800 ps
CPU time 0.87 seconds
Started Jun 10 05:25:50 PM PDT 24
Finished Jun 10 05:25:51 PM PDT 24
Peak memory 204988 kb
Host smart-ab8fd744-5cc3-499f-a7b3-06e2579714a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36755
82342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3675582342
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.2315322574
Short name T449
Test name
Test status
Simulation time 180138527 ps
CPU time 0.82 seconds
Started Jun 10 05:25:53 PM PDT 24
Finished Jun 10 05:25:55 PM PDT 24
Peak memory 205020 kb
Host smart-7ea436ed-4e04-4421-bc3a-2d532ee2e140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23153
22574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.2315322574
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.4135278911
Short name T1380
Test name
Test status
Simulation time 143157675 ps
CPU time 0.79 seconds
Started Jun 10 05:25:50 PM PDT 24
Finished Jun 10 05:25:52 PM PDT 24
Peak memory 204932 kb
Host smart-2df9d9f6-9ef2-4a00-96d6-4a8a5518f2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41352
78911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.4135278911
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2066393136
Short name T2042
Test name
Test status
Simulation time 158759845 ps
CPU time 0.85 seconds
Started Jun 10 05:25:51 PM PDT 24
Finished Jun 10 05:25:52 PM PDT 24
Peak memory 204944 kb
Host smart-c3fafd44-8345-4b24-a4a2-b43db346c3f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20663
93136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2066393136
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3643642426
Short name T1833
Test name
Test status
Simulation time 155660237 ps
CPU time 0.78 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:54 PM PDT 24
Peak memory 205032 kb
Host smart-8b51b01a-78ec-40de-9768-815743214ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36436
42426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3643642426
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2804653041
Short name T864
Test name
Test status
Simulation time 243085023 ps
CPU time 0.97 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:54 PM PDT 24
Peak memory 205008 kb
Host smart-c7c0310f-abb2-429b-8097-1004ed4e6f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28046
53041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2804653041
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2496114761
Short name T1340
Test name
Test status
Simulation time 185543447 ps
CPU time 0.84 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:54 PM PDT 24
Peak memory 205008 kb
Host smart-b9ca31b1-0f4e-4f26-992a-5fd2da0c8188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24961
14761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2496114761
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.1086591342
Short name T1394
Test name
Test status
Simulation time 144558954 ps
CPU time 0.78 seconds
Started Jun 10 05:25:58 PM PDT 24
Finished Jun 10 05:25:59 PM PDT 24
Peak memory 205044 kb
Host smart-82db515b-f198-4e54-b8fd-085f1142fd80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10865
91342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1086591342
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.2066163693
Short name T551
Test name
Test status
Simulation time 244931543 ps
CPU time 0.94 seconds
Started Jun 10 05:25:57 PM PDT 24
Finished Jun 10 05:25:59 PM PDT 24
Peak memory 205020 kb
Host smart-7c37ad67-2e56-46b9-9fbe-f1a6c67803ad
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2066163693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.2066163693
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.3777425603
Short name T436
Test name
Test status
Simulation time 188982401 ps
CPU time 0.82 seconds
Started Jun 10 05:25:56 PM PDT 24
Finished Jun 10 05:25:57 PM PDT 24
Peak memory 205020 kb
Host smart-0ae01287-2b82-489b-aef9-622ef4645465
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3777425603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.3777425603
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.612732763
Short name T23
Test name
Test status
Simulation time 232327649 ps
CPU time 0.89 seconds
Started Jun 10 05:26:04 PM PDT 24
Finished Jun 10 05:26:06 PM PDT 24
Peak memory 205016 kb
Host smart-6aba126e-af82-4b13-9344-f953b170a130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61273
2763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.612732763
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.2121570284
Short name T918
Test name
Test status
Simulation time 4098517743 ps
CPU time 5.2 seconds
Started Jun 10 05:25:53 PM PDT 24
Finished Jun 10 05:25:59 PM PDT 24
Peak memory 205096 kb
Host smart-6956f401-9da3-45f2-8e51-dbc22a045132
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2121570284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.2121570284
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.2953443074
Short name T921
Test name
Test status
Simulation time 13368088159 ps
CPU time 12.89 seconds
Started Jun 10 05:25:53 PM PDT 24
Finished Jun 10 05:26:06 PM PDT 24
Peak memory 205240 kb
Host smart-ec4cf7ae-632e-4426-aa8a-8e2ca710c52f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2953443074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.2953443074
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.351706409
Short name T1070
Test name
Test status
Simulation time 23359243580 ps
CPU time 25.97 seconds
Started Jun 10 05:26:03 PM PDT 24
Finished Jun 10 05:26:30 PM PDT 24
Peak memory 205108 kb
Host smart-8f22d328-3759-416e-a60c-8a9559cdc75a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=351706409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.351706409
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.4156910671
Short name T1381
Test name
Test status
Simulation time 198278298 ps
CPU time 0.92 seconds
Started Jun 10 05:25:50 PM PDT 24
Finished Jun 10 05:25:51 PM PDT 24
Peak memory 204976 kb
Host smart-37302176-68a9-4a0e-803a-1b8b09bb2cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41569
10671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.4156910671
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.2853302659
Short name T1560
Test name
Test status
Simulation time 156135483 ps
CPU time 0.78 seconds
Started Jun 10 05:26:00 PM PDT 24
Finished Jun 10 05:26:02 PM PDT 24
Peak memory 205016 kb
Host smart-8b17d0ab-2de6-40fe-a47d-5570ec22c467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28533
02659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.2853302659
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1568235042
Short name T1786
Test name
Test status
Simulation time 873722137 ps
CPU time 2.11 seconds
Started Jun 10 05:25:50 PM PDT 24
Finished Jun 10 05:25:52 PM PDT 24
Peak memory 205064 kb
Host smart-ead425d8-d25d-49a5-b962-46b3c74b7161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15682
35042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1568235042
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.674497192
Short name T606
Test name
Test status
Simulation time 159957960 ps
CPU time 0.8 seconds
Started Jun 10 05:25:53 PM PDT 24
Finished Jun 10 05:25:54 PM PDT 24
Peak memory 205040 kb
Host smart-6fdbac9a-c6a4-4df7-b061-0c20936d5d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67449
7192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.674497192
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.534163339
Short name T1449
Test name
Test status
Simulation time 37535218 ps
CPU time 0.66 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 205020 kb
Host smart-6a16c576-941d-431b-9fa5-ccf529621289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53416
3339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.534163339
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.1178744090
Short name T591
Test name
Test status
Simulation time 1031450089 ps
CPU time 2.35 seconds
Started Jun 10 05:25:53 PM PDT 24
Finished Jun 10 05:25:56 PM PDT 24
Peak memory 205148 kb
Host smart-655b0cf7-16fe-4b63-b766-72e6772aecc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11787
44090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.1178744090
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1276086110
Short name T760
Test name
Test status
Simulation time 255702959 ps
CPU time 1.57 seconds
Started Jun 10 05:25:55 PM PDT 24
Finished Jun 10 05:25:57 PM PDT 24
Peak memory 205088 kb
Host smart-103af9c5-921b-4bf0-8942-1d677e093b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12760
86110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1276086110
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2369886644
Short name T468
Test name
Test status
Simulation time 244121602 ps
CPU time 0.94 seconds
Started Jun 10 05:25:56 PM PDT 24
Finished Jun 10 05:25:57 PM PDT 24
Peak memory 205016 kb
Host smart-faf839f5-dfe9-4a75-8979-a66035d85b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23698
86644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2369886644
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2389835666
Short name T1969
Test name
Test status
Simulation time 143220332 ps
CPU time 0.77 seconds
Started Jun 10 05:26:04 PM PDT 24
Finished Jun 10 05:26:05 PM PDT 24
Peak memory 205012 kb
Host smart-e273722b-8049-4c9a-84ce-9b8c67ea952a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23898
35666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2389835666
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1494470909
Short name T1469
Test name
Test status
Simulation time 164726833 ps
CPU time 0.86 seconds
Started Jun 10 05:25:53 PM PDT 24
Finished Jun 10 05:25:55 PM PDT 24
Peak memory 205052 kb
Host smart-7ea59034-6035-49c3-8fb9-34eddc4450b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14944
70909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1494470909
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2240664621
Short name T1735
Test name
Test status
Simulation time 221031800 ps
CPU time 0.89 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 205008 kb
Host smart-4c4fc339-8767-415d-9a7f-16ed114872a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22406
64621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2240664621
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.3178186628
Short name T960
Test name
Test status
Simulation time 3381417973 ps
CPU time 4.81 seconds
Started Jun 10 05:25:50 PM PDT 24
Finished Jun 10 05:25:56 PM PDT 24
Peak memory 205072 kb
Host smart-271836fc-8833-44eb-af4f-4ec026750553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31781
86628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.3178186628
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3743476332
Short name T1504
Test name
Test status
Simulation time 215964182 ps
CPU time 0.96 seconds
Started Jun 10 05:25:53 PM PDT 24
Finished Jun 10 05:25:55 PM PDT 24
Peak memory 205008 kb
Host smart-9bdbdb91-03db-44ad-ae49-8e929928d6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37434
76332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3743476332
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.4264411337
Short name T529
Test name
Test status
Simulation time 11517974163 ps
CPU time 304.96 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:30:58 PM PDT 24
Peak memory 205232 kb
Host smart-8660bbf2-9867-44ef-8202-5cf629fc2588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42644
11337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.4264411337
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3813271137
Short name T929
Test name
Test status
Simulation time 156672161 ps
CPU time 0.79 seconds
Started Jun 10 05:25:54 PM PDT 24
Finished Jun 10 05:25:55 PM PDT 24
Peak memory 204908 kb
Host smart-bd35dc0f-7d72-4d79-bf90-38367ac8dbb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38132
71137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3813271137
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2590186886
Short name T152
Test name
Test status
Simulation time 243444056 ps
CPU time 0.89 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:54 PM PDT 24
Peak memory 205024 kb
Host smart-6c5100d0-5078-4bbc-8890-2c8f1602bda7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25901
86886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2590186886
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.713144668
Short name T308
Test name
Test status
Simulation time 151886366 ps
CPU time 0.76 seconds
Started Jun 10 05:25:51 PM PDT 24
Finished Jun 10 05:25:52 PM PDT 24
Peak memory 204988 kb
Host smart-dda1425e-f811-4aae-ab4d-7d632390664d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71314
4668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.713144668
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.658867946
Short name T1854
Test name
Test status
Simulation time 162833473 ps
CPU time 0.81 seconds
Started Jun 10 05:25:58 PM PDT 24
Finished Jun 10 05:25:59 PM PDT 24
Peak memory 205032 kb
Host smart-89750db6-280b-493a-bec7-e90cab0d8d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65886
7946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.658867946
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.354219620
Short name T1071
Test name
Test status
Simulation time 189191114 ps
CPU time 0.88 seconds
Started Jun 10 05:25:53 PM PDT 24
Finished Jun 10 05:25:55 PM PDT 24
Peak memory 205008 kb
Host smart-6339b0ba-6531-4916-80fe-6574fd4f09f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35421
9620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.354219620
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3215489300
Short name T1903
Test name
Test status
Simulation time 180589317 ps
CPU time 0.87 seconds
Started Jun 10 05:25:55 PM PDT 24
Finished Jun 10 05:25:56 PM PDT 24
Peak memory 205044 kb
Host smart-b17af43c-065a-4636-aa91-45eb97a00c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32154
89300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3215489300
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_eop_single_bit_handling.3336035219
Short name T586
Test name
Test status
Simulation time 185072799 ps
CPU time 0.84 seconds
Started Jun 10 05:25:54 PM PDT 24
Finished Jun 10 05:25:55 PM PDT 24
Peak memory 205044 kb
Host smart-ca76d433-b1a4-4807-aff7-210c5d5b3131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33360
35219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_eop_single_bit_handling.3336035219
Directory /workspace/18.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.905208448
Short name T1064
Test name
Test status
Simulation time 153011391 ps
CPU time 0.78 seconds
Started Jun 10 05:26:08 PM PDT 24
Finished Jun 10 05:26:09 PM PDT 24
Peak memory 204996 kb
Host smart-1ee326e3-cb99-4e78-abc7-9c04a9e42469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90520
8448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.905208448
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2021103615
Short name T753
Test name
Test status
Simulation time 33968755 ps
CPU time 0.65 seconds
Started Jun 10 05:25:54 PM PDT 24
Finished Jun 10 05:25:55 PM PDT 24
Peak memory 204896 kb
Host smart-93d04b07-231d-472c-85a3-8a9320ad1875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20211
03615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2021103615
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2793129670
Short name T1000
Test name
Test status
Simulation time 21967054263 ps
CPU time 48.28 seconds
Started Jun 10 05:25:54 PM PDT 24
Finished Jun 10 05:26:43 PM PDT 24
Peak memory 205276 kb
Host smart-70490f1d-b5b9-47ad-a4b6-ccf6d67484db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27931
29670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2793129670
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.506021795
Short name T1044
Test name
Test status
Simulation time 178315472 ps
CPU time 0.87 seconds
Started Jun 10 05:25:52 PM PDT 24
Finished Jun 10 05:25:54 PM PDT 24
Peak memory 205020 kb
Host smart-c12637d1-0047-4bd5-adf0-604737d9871f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50602
1795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.506021795
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.3504096685
Short name T579
Test name
Test status
Simulation time 199525952 ps
CPU time 0.89 seconds
Started Jun 10 05:25:51 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 204996 kb
Host smart-7e81eaf7-57bb-45c3-9e5a-18836862d98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35040
96685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3504096685
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.4214967214
Short name T956
Test name
Test status
Simulation time 164119182 ps
CPU time 0.8 seconds
Started Jun 10 05:25:55 PM PDT 24
Finished Jun 10 05:25:56 PM PDT 24
Peak memory 205004 kb
Host smart-de6196e9-34ba-4c29-b59d-fed25130191a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42149
67214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.4214967214
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.1939829331
Short name T127
Test name
Test status
Simulation time 141101309 ps
CPU time 0.81 seconds
Started Jun 10 05:26:04 PM PDT 24
Finished Jun 10 05:26:06 PM PDT 24
Peak memory 205000 kb
Host smart-54738c80-4362-4291-bdd0-3d41f82ce448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19398
29331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.1939829331
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.2964067347
Short name T1695
Test name
Test status
Simulation time 148405996 ps
CPU time 0.86 seconds
Started Jun 10 05:25:56 PM PDT 24
Finished Jun 10 05:25:57 PM PDT 24
Peak memory 205024 kb
Host smart-83cb46a5-498c-4888-b0cc-161128144e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29640
67347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2964067347
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3020577993
Short name T1509
Test name
Test status
Simulation time 153993841 ps
CPU time 0.81 seconds
Started Jun 10 05:25:56 PM PDT 24
Finished Jun 10 05:25:57 PM PDT 24
Peak memory 205008 kb
Host smart-6cb87c74-0a2d-41f2-bd59-151e97205e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30205
77993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3020577993
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.4020873722
Short name T1081
Test name
Test status
Simulation time 248456925 ps
CPU time 1.04 seconds
Started Jun 10 05:25:54 PM PDT 24
Finished Jun 10 05:25:56 PM PDT 24
Peak memory 205108 kb
Host smart-c08c97c6-1a2d-46c2-8b02-33291828de9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40208
73722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.4020873722
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3507214020
Short name T1819
Test name
Test status
Simulation time 166824963 ps
CPU time 0.82 seconds
Started Jun 10 05:26:01 PM PDT 24
Finished Jun 10 05:26:02 PM PDT 24
Peak memory 204988 kb
Host smart-49400d07-9dc4-4921-b158-57c3773f5ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35072
14020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3507214020
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.3925033565
Short name T927
Test name
Test status
Simulation time 175553990 ps
CPU time 0.87 seconds
Started Jun 10 05:25:56 PM PDT 24
Finished Jun 10 05:25:58 PM PDT 24
Peak memory 205000 kb
Host smart-53dfa2d4-496d-40f5-b490-29f06bb0b79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39250
33565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.3925033565
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.1169849934
Short name T989
Test name
Test status
Simulation time 12647422539 ps
CPU time 331.54 seconds
Started Jun 10 05:25:57 PM PDT 24
Finished Jun 10 05:31:30 PM PDT 24
Peak memory 205228 kb
Host smart-69072f82-a842-4d4c-adf3-7666e110573e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11698
49934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.1169849934
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.4025979118
Short name T1399
Test name
Test status
Simulation time 251785223 ps
CPU time 0.98 seconds
Started Jun 10 05:26:05 PM PDT 24
Finished Jun 10 05:26:06 PM PDT 24
Peak memory 205044 kb
Host smart-9a791f43-0ccb-4b7f-83e4-aac481fd7714
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4025979118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.4025979118
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.2896794784
Short name T388
Test name
Test status
Simulation time 167993796 ps
CPU time 0.82 seconds
Started Jun 10 05:26:22 PM PDT 24
Finished Jun 10 05:26:23 PM PDT 24
Peak memory 205048 kb
Host smart-56831ff8-f86b-465b-ab91-e09d5aeda678
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2896794784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.2896794784
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.2542344757
Short name T632
Test name
Test status
Simulation time 201357156 ps
CPU time 0.91 seconds
Started Jun 10 05:26:09 PM PDT 24
Finished Jun 10 05:26:11 PM PDT 24
Peak memory 205016 kb
Host smart-03db6e61-9a03-4b52-a2f1-200cd1607565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25423
44757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.2542344757
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.625846878
Short name T413
Test name
Test status
Simulation time 3892852813 ps
CPU time 4.91 seconds
Started Jun 10 05:25:55 PM PDT 24
Finished Jun 10 05:26:00 PM PDT 24
Peak memory 205204 kb
Host smart-0c435412-b39f-47a5-92f0-7b53fc6c069f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=625846878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.625846878
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.1568188716
Short name T2056
Test name
Test status
Simulation time 13348016265 ps
CPU time 13.4 seconds
Started Jun 10 05:25:59 PM PDT 24
Finished Jun 10 05:26:12 PM PDT 24
Peak memory 205240 kb
Host smart-b343223e-a446-469d-9b2f-34ce9a0edda0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1568188716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.1568188716
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.2305094238
Short name T1087
Test name
Test status
Simulation time 23373288133 ps
CPU time 24.76 seconds
Started Jun 10 05:26:01 PM PDT 24
Finished Jun 10 05:26:26 PM PDT 24
Peak memory 205104 kb
Host smart-872d7681-1fa8-4af3-9856-58290b31a59b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2305094238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.2305094238
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1290397953
Short name T2029
Test name
Test status
Simulation time 157457882 ps
CPU time 0.8 seconds
Started Jun 10 05:26:06 PM PDT 24
Finished Jun 10 05:26:08 PM PDT 24
Peak memory 205060 kb
Host smart-a30a3c38-81ef-4579-8ee6-a3cbdc0a5528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12903
97953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1290397953
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.3971474742
Short name T780
Test name
Test status
Simulation time 152038950 ps
CPU time 0.77 seconds
Started Jun 10 05:26:13 PM PDT 24
Finished Jun 10 05:26:14 PM PDT 24
Peak memory 205020 kb
Host smart-842b2401-fb90-445e-8a1f-126815f0ef4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39714
74742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.3971474742
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3434921365
Short name T1578
Test name
Test status
Simulation time 1069026784 ps
CPU time 2.43 seconds
Started Jun 10 05:26:10 PM PDT 24
Finished Jun 10 05:26:13 PM PDT 24
Peak memory 205132 kb
Host smart-65c9989a-32df-4a6a-8da1-80ce716b8755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34349
21365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3434921365
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.2650390949
Short name T1057
Test name
Test status
Simulation time 186517677 ps
CPU time 0.82 seconds
Started Jun 10 05:26:03 PM PDT 24
Finished Jun 10 05:26:04 PM PDT 24
Peak memory 205020 kb
Host smart-fcefb345-fc48-44fc-961d-eb4a73b1db00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26503
90949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.2650390949
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.562732008
Short name T1995
Test name
Test status
Simulation time 34622476 ps
CPU time 0.67 seconds
Started Jun 10 05:26:03 PM PDT 24
Finished Jun 10 05:26:04 PM PDT 24
Peak memory 205088 kb
Host smart-736bd249-6b23-41b2-bf40-b29c137a6f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56273
2008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.562732008
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.752123001
Short name T1660
Test name
Test status
Simulation time 839285182 ps
CPU time 1.99 seconds
Started Jun 10 05:26:05 PM PDT 24
Finished Jun 10 05:26:07 PM PDT 24
Peak memory 205104 kb
Host smart-bf42b7a1-8e5c-4ee2-9968-2ed53f05d469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75212
3001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.752123001
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2454454383
Short name T1357
Test name
Test status
Simulation time 197769451 ps
CPU time 1.28 seconds
Started Jun 10 05:26:11 PM PDT 24
Finished Jun 10 05:26:13 PM PDT 24
Peak memory 205136 kb
Host smart-eb6ee1c7-8b87-4c1c-9a56-ac75db81c36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24544
54383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2454454383
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2297197733
Short name T1640
Test name
Test status
Simulation time 198890903 ps
CPU time 0.87 seconds
Started Jun 10 05:26:07 PM PDT 24
Finished Jun 10 05:26:08 PM PDT 24
Peak memory 204980 kb
Host smart-7570018a-43dd-4968-95a7-77123fa2cd1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22971
97733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2297197733
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.617505280
Short name T1365
Test name
Test status
Simulation time 166222053 ps
CPU time 0.78 seconds
Started Jun 10 05:26:22 PM PDT 24
Finished Jun 10 05:26:23 PM PDT 24
Peak memory 204992 kb
Host smart-749b4b80-4b9a-4cb4-8297-4894bd7c94bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61750
5280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.617505280
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2238029645
Short name T1564
Test name
Test status
Simulation time 236374071 ps
CPU time 0.96 seconds
Started Jun 10 05:26:26 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 205004 kb
Host smart-bcfe2e8d-12eb-4e9d-a03d-ebf60cb3bb29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22380
29645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2238029645
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1325524078
Short name T851
Test name
Test status
Simulation time 264801912 ps
CPU time 0.9 seconds
Started Jun 10 05:25:59 PM PDT 24
Finished Jun 10 05:26:00 PM PDT 24
Peak memory 205000 kb
Host smart-16e146b6-9105-46fc-bc88-5fc4b0e64a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13255
24078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1325524078
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2455712505
Short name T1043
Test name
Test status
Simulation time 3344978490 ps
CPU time 3.9 seconds
Started Jun 10 05:26:01 PM PDT 24
Finished Jun 10 05:26:05 PM PDT 24
Peak memory 205100 kb
Host smart-89a971d1-6181-4a22-8ea4-8df0b469c18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24557
12505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2455712505
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1778276053
Short name T765
Test name
Test status
Simulation time 187012745 ps
CPU time 0.89 seconds
Started Jun 10 05:26:10 PM PDT 24
Finished Jun 10 05:26:11 PM PDT 24
Peak memory 205032 kb
Host smart-a19f4857-86cb-4577-a770-472224013a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17782
76053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1778276053
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.2594649322
Short name T471
Test name
Test status
Simulation time 6718238114 ps
CPU time 47.78 seconds
Started Jun 10 05:26:19 PM PDT 24
Finished Jun 10 05:27:07 PM PDT 24
Peak memory 205200 kb
Host smart-70f60335-218b-471e-9a35-080e1454cc78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25946
49322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.2594649322
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.371991
Short name T879
Test name
Test status
Simulation time 158625976 ps
CPU time 0.79 seconds
Started Jun 10 05:26:03 PM PDT 24
Finished Jun 10 05:26:04 PM PDT 24
Peak memory 205092 kb
Host smart-71e8f346-af8b-44f9-8351-cda87000db4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37199
1 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.371991
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.3741120501
Short name T82
Test name
Test status
Simulation time 170717757 ps
CPU time 0.89 seconds
Started Jun 10 05:26:12 PM PDT 24
Finished Jun 10 05:26:13 PM PDT 24
Peak memory 205008 kb
Host smart-697a5278-cc16-44e9-94dd-a66ae8895354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37411
20501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.3741120501
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.552376134
Short name T625
Test name
Test status
Simulation time 155151477 ps
CPU time 0.77 seconds
Started Jun 10 05:26:16 PM PDT 24
Finished Jun 10 05:26:17 PM PDT 24
Peak memory 204988 kb
Host smart-3214ac04-c1c8-423e-87fe-0d13ca3b65cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55237
6134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.552376134
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1633013157
Short name T987
Test name
Test status
Simulation time 219524285 ps
CPU time 0.94 seconds
Started Jun 10 05:26:01 PM PDT 24
Finished Jun 10 05:26:02 PM PDT 24
Peak memory 205000 kb
Host smart-08676701-178b-4caf-9d9c-7b81cb0a9a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16330
13157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1633013157
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1039054498
Short name T1664
Test name
Test status
Simulation time 212602496 ps
CPU time 0.9 seconds
Started Jun 10 05:26:12 PM PDT 24
Finished Jun 10 05:26:14 PM PDT 24
Peak memory 205004 kb
Host smart-c0822ba4-a9f3-4601-8c40-322f7439e921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10390
54498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1039054498
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_eop_single_bit_handling.2074157171
Short name T1506
Test name
Test status
Simulation time 172163322 ps
CPU time 0.83 seconds
Started Jun 10 05:26:23 PM PDT 24
Finished Jun 10 05:26:24 PM PDT 24
Peak memory 205008 kb
Host smart-17123b2d-8619-4d24-99a1-23704cefafd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20741
57171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_eop_single_bit_handling.2074157171
Directory /workspace/19.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2032903178
Short name T1864
Test name
Test status
Simulation time 169026623 ps
CPU time 0.77 seconds
Started Jun 10 05:26:05 PM PDT 24
Finished Jun 10 05:26:06 PM PDT 24
Peak memory 204984 kb
Host smart-1f1dafca-74fd-4ce3-815d-c2362226f862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20329
03178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2032903178
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.4077444397
Short name T1621
Test name
Test status
Simulation time 48566739 ps
CPU time 0.64 seconds
Started Jun 10 05:26:09 PM PDT 24
Finished Jun 10 05:26:10 PM PDT 24
Peak memory 204996 kb
Host smart-6bb5e667-a5db-4346-8c92-c6e8612d7920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40774
44397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.4077444397
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3866934442
Short name T1173
Test name
Test status
Simulation time 13242039465 ps
CPU time 32.38 seconds
Started Jun 10 05:26:08 PM PDT 24
Finished Jun 10 05:26:41 PM PDT 24
Peak memory 205196 kb
Host smart-77c1bdd8-fe1f-4e3e-b2cf-dd3f375f1147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38669
34442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3866934442
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.877241445
Short name T1001
Test name
Test status
Simulation time 187770714 ps
CPU time 0.84 seconds
Started Jun 10 05:26:16 PM PDT 24
Finished Jun 10 05:26:17 PM PDT 24
Peak memory 204944 kb
Host smart-44814226-51ba-426e-a6aa-f1a9247fd447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87724
1445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.877241445
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1807276560
Short name T1711
Test name
Test status
Simulation time 205192901 ps
CPU time 0.89 seconds
Started Jun 10 05:26:06 PM PDT 24
Finished Jun 10 05:26:07 PM PDT 24
Peak memory 204896 kb
Host smart-5c95aaa0-3d32-400a-8d1c-8c530f1cc1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18072
76560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1807276560
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.1644117781
Short name T917
Test name
Test status
Simulation time 237852262 ps
CPU time 0.96 seconds
Started Jun 10 05:26:23 PM PDT 24
Finished Jun 10 05:26:24 PM PDT 24
Peak memory 205008 kb
Host smart-0db366de-a2b7-4e12-b633-d56e3163c5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16441
17781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.1644117781
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1002756527
Short name T721
Test name
Test status
Simulation time 166303681 ps
CPU time 0.85 seconds
Started Jun 10 05:26:17 PM PDT 24
Finished Jun 10 05:26:18 PM PDT 24
Peak memory 205004 kb
Host smart-7d3d15c8-c6fd-486b-a0f5-80d264207fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10027
56527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1002756527
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1134761538
Short name T1700
Test name
Test status
Simulation time 190827741 ps
CPU time 0.83 seconds
Started Jun 10 05:26:09 PM PDT 24
Finished Jun 10 05:26:10 PM PDT 24
Peak memory 204852 kb
Host smart-61437834-a595-4407-85ef-2eb1c079898a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11347
61538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1134761538
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1093035246
Short name T983
Test name
Test status
Simulation time 178737708 ps
CPU time 0.84 seconds
Started Jun 10 05:26:17 PM PDT 24
Finished Jun 10 05:26:18 PM PDT 24
Peak memory 204956 kb
Host smart-51f1e50c-6f26-49a6-a535-78d06498cf8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10930
35246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1093035246
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1747576529
Short name T973
Test name
Test status
Simulation time 14095744449 ps
CPU time 395.29 seconds
Started Jun 10 05:26:04 PM PDT 24
Finished Jun 10 05:32:40 PM PDT 24
Peak memory 205232 kb
Host smart-4349afc3-3bf7-444a-b21e-ad4b1fe1b89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17475
76529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1747576529
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.3099513357
Short name T1641
Test name
Test status
Simulation time 292913030 ps
CPU time 0.93 seconds
Started Jun 10 05:24:21 PM PDT 24
Finished Jun 10 05:24:23 PM PDT 24
Peak memory 204996 kb
Host smart-8069cd8b-1167-41b4-8cbb-da305eca950c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3099513357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.3099513357
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.3202506851
Short name T1068
Test name
Test status
Simulation time 181312463 ps
CPU time 0.85 seconds
Started Jun 10 05:24:25 PM PDT 24
Finished Jun 10 05:24:26 PM PDT 24
Peak memory 205032 kb
Host smart-870a090e-b8e8-463f-a2ae-de7e91cf12ef
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3202506851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.3202506851
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.215790746
Short name T1204
Test name
Test status
Simulation time 271561666 ps
CPU time 0.94 seconds
Started Jun 10 05:24:22 PM PDT 24
Finished Jun 10 05:24:24 PM PDT 24
Peak memory 204980 kb
Host smart-a723567c-bd42-4567-92f3-2a65f8a29c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21579
0746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.215790746
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.2819595747
Short name T1163
Test name
Test status
Simulation time 3491346908 ps
CPU time 4.59 seconds
Started Jun 10 05:24:19 PM PDT 24
Finished Jun 10 05:24:25 PM PDT 24
Peak memory 205024 kb
Host smart-0913c4e2-d8ab-4512-a0f0-7cf0ca34f4b0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2819595747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.2819595747
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.4126293491
Short name T968
Test name
Test status
Simulation time 13313069605 ps
CPU time 13.68 seconds
Started Jun 10 05:24:19 PM PDT 24
Finished Jun 10 05:24:37 PM PDT 24
Peak memory 205212 kb
Host smart-4b0a8ee6-23cf-471b-977d-1d54d4e6c36a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4126293491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.4126293491
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1287504262
Short name T1032
Test name
Test status
Simulation time 23397198840 ps
CPU time 23.8 seconds
Started Jun 10 05:24:17 PM PDT 24
Finished Jun 10 05:24:42 PM PDT 24
Peak memory 205120 kb
Host smart-a862f6a5-5cfa-476a-b8a9-48f952d74ad0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1287504262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.1287504262
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1261416553
Short name T1589
Test name
Test status
Simulation time 164533169 ps
CPU time 0.78 seconds
Started Jun 10 05:24:28 PM PDT 24
Finished Jun 10 05:24:29 PM PDT 24
Peak memory 205040 kb
Host smart-c50e76af-2c28-406a-b613-3b86df1af201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12614
16553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1261416553
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.4210873458
Short name T1862
Test name
Test status
Simulation time 199937367 ps
CPU time 0.82 seconds
Started Jun 10 05:24:21 PM PDT 24
Finished Jun 10 05:24:22 PM PDT 24
Peak memory 205016 kb
Host smart-a2241527-d74f-41ff-9a8f-c13d365ff82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42108
73458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.4210873458
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.344713591
Short name T2085
Test name
Test status
Simulation time 885362464 ps
CPU time 2.04 seconds
Started Jun 10 05:24:20 PM PDT 24
Finished Jun 10 05:24:22 PM PDT 24
Peak memory 205084 kb
Host smart-bcc1456c-fb0f-462f-bed2-756f90e21821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34471
3591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.344713591
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.168492160
Short name T1171
Test name
Test status
Simulation time 154095329 ps
CPU time 0.77 seconds
Started Jun 10 05:24:26 PM PDT 24
Finished Jun 10 05:24:28 PM PDT 24
Peak memory 205028 kb
Host smart-dff8d454-79bb-45d4-be05-e7566190525f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16849
2160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.168492160
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.252897877
Short name T1359
Test name
Test status
Simulation time 108395618 ps
CPU time 0.73 seconds
Started Jun 10 05:24:23 PM PDT 24
Finished Jun 10 05:24:24 PM PDT 24
Peak memory 205048 kb
Host smart-ec83ef47-ffe2-4e00-b1d7-d778390095f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25289
7877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.252897877
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.582805582
Short name T531
Test name
Test status
Simulation time 804715490 ps
CPU time 1.94 seconds
Started Jun 10 05:24:22 PM PDT 24
Finished Jun 10 05:24:25 PM PDT 24
Peak memory 205140 kb
Host smart-0219b50a-eb1d-41c6-afda-0784a61f02b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58280
5582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.582805582
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.66540361
Short name T1306
Test name
Test status
Simulation time 208392567 ps
CPU time 1.5 seconds
Started Jun 10 05:24:25 PM PDT 24
Finished Jun 10 05:24:27 PM PDT 24
Peak memory 205112 kb
Host smart-2c45f88f-7f93-417e-a2ed-1f2cd05f85fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66540
361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.66540361
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.51311907
Short name T812
Test name
Test status
Simulation time 225818426 ps
CPU time 0.87 seconds
Started Jun 10 05:24:20 PM PDT 24
Finished Jun 10 05:24:22 PM PDT 24
Peak memory 205032 kb
Host smart-a432e0d6-f4ca-4696-8217-e51bb2fe0813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51311
907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.51311907
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1142957441
Short name T1408
Test name
Test status
Simulation time 188220321 ps
CPU time 0.86 seconds
Started Jun 10 05:24:25 PM PDT 24
Finished Jun 10 05:24:26 PM PDT 24
Peak memory 205004 kb
Host smart-19e30b39-e3a5-492e-8337-e7a048424e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11429
57441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1142957441
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.107942550
Short name T1724
Test name
Test status
Simulation time 252433401 ps
CPU time 0.93 seconds
Started Jun 10 05:24:32 PM PDT 24
Finished Jun 10 05:24:33 PM PDT 24
Peak memory 205036 kb
Host smart-ea68f42e-bf23-4da8-b424-3d073223a1dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10794
2550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.107942550
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1361765654
Short name T1200
Test name
Test status
Simulation time 256078309 ps
CPU time 0.93 seconds
Started Jun 10 05:24:24 PM PDT 24
Finished Jun 10 05:24:25 PM PDT 24
Peak memory 205004 kb
Host smart-5ee1ce11-0439-48b8-b6df-03e3185e9264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13617
65654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1361765654
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.2482007783
Short name T2001
Test name
Test status
Simulation time 3371247723 ps
CPU time 4.06 seconds
Started Jun 10 05:24:22 PM PDT 24
Finished Jun 10 05:24:27 PM PDT 24
Peak memory 205072 kb
Host smart-3beb4eec-3cf0-4141-907a-c467a51f773d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24820
07783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.2482007783
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3214378719
Short name T365
Test name
Test status
Simulation time 244210950 ps
CPU time 1 seconds
Started Jun 10 05:24:26 PM PDT 24
Finished Jun 10 05:24:28 PM PDT 24
Peak memory 205064 kb
Host smart-cc1a36d6-a9c8-4330-8849-44ed53ab08c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32143
78719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3214378719
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.3828236350
Short name T441
Test name
Test status
Simulation time 6673024791 ps
CPU time 46.79 seconds
Started Jun 10 05:24:20 PM PDT 24
Finished Jun 10 05:25:07 PM PDT 24
Peak memory 205052 kb
Host smart-a56a86a7-aa18-45fd-9326-822cbef9c49c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38282
36350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.3828236350
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2047533570
Short name T453
Test name
Test status
Simulation time 140640051 ps
CPU time 0.77 seconds
Started Jun 10 05:24:22 PM PDT 24
Finished Jun 10 05:24:24 PM PDT 24
Peak memory 205028 kb
Host smart-11675be8-ad02-4681-b4d2-b4a78bae6286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20475
33570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2047533570
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3614444336
Short name T154
Test name
Test status
Simulation time 201079568 ps
CPU time 0.82 seconds
Started Jun 10 05:24:28 PM PDT 24
Finished Jun 10 05:24:29 PM PDT 24
Peak memory 205004 kb
Host smart-bb87fcdf-d74b-423e-a2ea-53d0c5fb3ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36144
44336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3614444336
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2141996463
Short name T1555
Test name
Test status
Simulation time 165865893 ps
CPU time 0.84 seconds
Started Jun 10 05:24:22 PM PDT 24
Finished Jun 10 05:24:24 PM PDT 24
Peak memory 205000 kb
Host smart-888c5516-e39c-46b3-a0c8-cef014a725b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21419
96463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2141996463
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3109766663
Short name T744
Test name
Test status
Simulation time 139878585 ps
CPU time 0.74 seconds
Started Jun 10 05:24:27 PM PDT 24
Finished Jun 10 05:24:29 PM PDT 24
Peak memory 205004 kb
Host smart-b68fb238-eb57-41b5-a4c3-d7eeb6685e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31097
66663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3109766663
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3216751562
Short name T445
Test name
Test status
Simulation time 180777022 ps
CPU time 0.82 seconds
Started Jun 10 05:24:24 PM PDT 24
Finished Jun 10 05:24:25 PM PDT 24
Peak memory 205012 kb
Host smart-002bee55-097e-4185-a96c-9b1db8928a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32167
51562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3216751562
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1011791426
Short name T1162
Test name
Test status
Simulation time 166030587 ps
CPU time 0.79 seconds
Started Jun 10 05:24:25 PM PDT 24
Finished Jun 10 05:24:26 PM PDT 24
Peak memory 204944 kb
Host smart-2db036b7-f4bd-4446-b937-3a3dd38f037c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10117
91426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1011791426
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_eop_single_bit_handling.1488104284
Short name T1058
Test name
Test status
Simulation time 171140028 ps
CPU time 0.81 seconds
Started Jun 10 05:24:23 PM PDT 24
Finished Jun 10 05:24:25 PM PDT 24
Peak memory 205036 kb
Host smart-b17d295a-845e-4bd9-98f5-d7686ca651fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14881
04284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_eop_single_bit_handling.1488104284
Directory /workspace/2.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1370872622
Short name T1618
Test name
Test status
Simulation time 144645050 ps
CPU time 0.82 seconds
Started Jun 10 05:24:22 PM PDT 24
Finished Jun 10 05:24:24 PM PDT 24
Peak memory 205092 kb
Host smart-3ee8214e-415b-47e6-8e6b-f0fc62241ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13708
72622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1370872622
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3380993386
Short name T38
Test name
Test status
Simulation time 44112650 ps
CPU time 0.68 seconds
Started Jun 10 05:24:25 PM PDT 24
Finished Jun 10 05:24:26 PM PDT 24
Peak memory 204992 kb
Host smart-4d2af6f7-aa61-4a48-a707-09ad6646e615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33809
93386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3380993386
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1821594661
Short name T1090
Test name
Test status
Simulation time 9555933696 ps
CPU time 21.76 seconds
Started Jun 10 05:24:26 PM PDT 24
Finished Jun 10 05:24:48 PM PDT 24
Peak memory 205268 kb
Host smart-3b929ca9-1d3d-4881-9ace-9f9f2fe71b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18215
94661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1821594661
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1586141695
Short name T776
Test name
Test status
Simulation time 149536948 ps
CPU time 0.78 seconds
Started Jun 10 05:24:25 PM PDT 24
Finished Jun 10 05:24:26 PM PDT 24
Peak memory 204944 kb
Host smart-6fe7a9e7-2739-4497-ba5c-ec360086059c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15861
41695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1586141695
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3217764004
Short name T1694
Test name
Test status
Simulation time 165057025 ps
CPU time 0.79 seconds
Started Jun 10 05:24:19 PM PDT 24
Finished Jun 10 05:24:21 PM PDT 24
Peak memory 205028 kb
Host smart-5048c1b2-9606-4db2-aa50-7316516338de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32177
64004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3217764004
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.540914240
Short name T802
Test name
Test status
Simulation time 16798806031 ps
CPU time 130.03 seconds
Started Jun 10 05:24:22 PM PDT 24
Finished Jun 10 05:26:33 PM PDT 24
Peak memory 205284 kb
Host smart-9640f303-2783-4062-a964-e7cfb29ee0b4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=540914240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.540914240
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.1167502453
Short name T206
Test name
Test status
Simulation time 15406629799 ps
CPU time 326.79 seconds
Started Jun 10 05:24:21 PM PDT 24
Finished Jun 10 05:29:49 PM PDT 24
Peak memory 205284 kb
Host smart-d358f904-aa58-4768-9439-e929936f3c57
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1167502453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.1167502453
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.3800798272
Short name T439
Test name
Test status
Simulation time 35838459605 ps
CPU time 925.3 seconds
Started Jun 10 05:24:23 PM PDT 24
Finished Jun 10 05:39:49 PM PDT 24
Peak memory 205268 kb
Host smart-6381d1db-2de5-4c97-889f-2accfdd86671
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3800798272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3800798272
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.3004858342
Short name T86
Test name
Test status
Simulation time 154559526 ps
CPU time 0.79 seconds
Started Jun 10 05:24:21 PM PDT 24
Finished Jun 10 05:24:23 PM PDT 24
Peak memory 204992 kb
Host smart-0c40e365-f044-4c46-87af-c6a777cac2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30048
58342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.3004858342
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.4093235722
Short name T963
Test name
Test status
Simulation time 161469858 ps
CPU time 0.79 seconds
Started Jun 10 05:24:24 PM PDT 24
Finished Jun 10 05:24:26 PM PDT 24
Peak memory 204948 kb
Host smart-8cd9948a-4630-4177-9770-f363f0c23d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40932
35722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.4093235722
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3721935985
Short name T122
Test name
Test status
Simulation time 756690224 ps
CPU time 1.69 seconds
Started Jun 10 05:24:28 PM PDT 24
Finished Jun 10 05:24:30 PM PDT 24
Peak memory 222480 kb
Host smart-b537ac98-15ca-4a46-9c39-0e9f6284df98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3721935985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3721935985
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1795694014
Short name T1018
Test name
Test status
Simulation time 169583153 ps
CPU time 0.78 seconds
Started Jun 10 05:24:24 PM PDT 24
Finished Jun 10 05:24:25 PM PDT 24
Peak memory 205032 kb
Host smart-0f450266-fd28-49a6-8dd9-8bdc843350bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17956
94014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1795694014
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.1191442945
Short name T618
Test name
Test status
Simulation time 156080655 ps
CPU time 0.77 seconds
Started Jun 10 05:24:28 PM PDT 24
Finished Jun 10 05:24:29 PM PDT 24
Peak memory 205000 kb
Host smart-b62afe97-4992-483f-b879-0d39e850eb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11914
42945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.1191442945
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.4092653905
Short name T797
Test name
Test status
Simulation time 245384189 ps
CPU time 0.94 seconds
Started Jun 10 05:24:18 PM PDT 24
Finished Jun 10 05:24:20 PM PDT 24
Peak memory 205020 kb
Host smart-3ce5d14f-753c-4307-b218-90bfd1c0b60c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40926
53905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.4092653905
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.3758635443
Short name T975
Test name
Test status
Simulation time 169760884 ps
CPU time 0.82 seconds
Started Jun 10 05:24:22 PM PDT 24
Finished Jun 10 05:24:23 PM PDT 24
Peak memory 204996 kb
Host smart-fb1f03d3-7bd3-40bc-b032-8db14c8a8442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37586
35443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.3758635443
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2994254064
Short name T536
Test name
Test status
Simulation time 228585138 ps
CPU time 0.82 seconds
Started Jun 10 05:24:23 PM PDT 24
Finished Jun 10 05:24:24 PM PDT 24
Peak memory 204988 kb
Host smart-cadb8fa3-fa7a-4ffa-aa03-74d89ae1b666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29942
54064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2994254064
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.705782147
Short name T1488
Test name
Test status
Simulation time 12666543008 ps
CPU time 356.83 seconds
Started Jun 10 05:24:28 PM PDT 24
Finished Jun 10 05:30:25 PM PDT 24
Peak memory 205192 kb
Host smart-61f52352-e29d-4a39-9b51-44d03584941b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70578
2147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.705782147
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.68213338
Short name T1370
Test name
Test status
Simulation time 25849325553 ps
CPU time 205.48 seconds
Started Jun 10 05:24:24 PM PDT 24
Finished Jun 10 05:27:50 PM PDT 24
Peak memory 205208 kb
Host smart-0169d15e-ae51-4e65-a9a4-e87df9b3d058
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68213338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus
_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_tr
affic.68213338
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.4254993369
Short name T1349
Test name
Test status
Simulation time 237040879 ps
CPU time 0.9 seconds
Started Jun 10 05:26:07 PM PDT 24
Finished Jun 10 05:26:09 PM PDT 24
Peak memory 205020 kb
Host smart-12898e13-91a7-4dd0-be4c-82babf632dc3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4254993369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.4254993369
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.3054903767
Short name T2084
Test name
Test status
Simulation time 167200170 ps
CPU time 0.82 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:26:26 PM PDT 24
Peak memory 205032 kb
Host smart-d8166ecd-92ce-4484-ae85-04230d6e3540
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3054903767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.3054903767
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.3643109234
Short name T583
Test name
Test status
Simulation time 225633677 ps
CPU time 0.91 seconds
Started Jun 10 05:26:21 PM PDT 24
Finished Jun 10 05:26:22 PM PDT 24
Peak memory 205012 kb
Host smart-0ab68963-c5b7-40c2-a395-56006493a3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36431
09234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.3643109234
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.3611979374
Short name T1627
Test name
Test status
Simulation time 3891922816 ps
CPU time 5.87 seconds
Started Jun 10 05:26:14 PM PDT 24
Finished Jun 10 05:26:20 PM PDT 24
Peak memory 205208 kb
Host smart-6008bbd5-5368-4d1f-bb80-f6614812bbe6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3611979374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.3611979374
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.1661115801
Short name T1685
Test name
Test status
Simulation time 13369756851 ps
CPU time 16.27 seconds
Started Jun 10 05:26:05 PM PDT 24
Finished Jun 10 05:26:22 PM PDT 24
Peak memory 205048 kb
Host smart-3fe7b086-3ea2-441b-a0b4-544f75713051
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1661115801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.1661115801
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.3296238423
Short name T1669
Test name
Test status
Simulation time 23310300833 ps
CPU time 24.18 seconds
Started Jun 10 05:26:14 PM PDT 24
Finished Jun 10 05:26:39 PM PDT 24
Peak memory 205124 kb
Host smart-8e0bd315-a902-48f0-b50b-912108e6eba8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3296238423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.3296238423
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1971495971
Short name T301
Test name
Test status
Simulation time 187274033 ps
CPU time 0.88 seconds
Started Jun 10 05:26:13 PM PDT 24
Finished Jun 10 05:26:14 PM PDT 24
Peak memory 205008 kb
Host smart-6448afbc-6bd7-4441-9313-25c748dd3fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19714
95971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1971495971
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.722042341
Short name T58
Test name
Test status
Simulation time 151796153 ps
CPU time 0.79 seconds
Started Jun 10 05:26:06 PM PDT 24
Finished Jun 10 05:26:07 PM PDT 24
Peak memory 204984 kb
Host smart-33624abd-b447-4643-86f1-d076c3accbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72204
2341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.722042341
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1658174313
Short name T1794
Test name
Test status
Simulation time 1511497500 ps
CPU time 3.37 seconds
Started Jun 10 05:26:08 PM PDT 24
Finished Jun 10 05:26:11 PM PDT 24
Peak memory 205068 kb
Host smart-273f4748-7d66-4b73-943c-f5c3641d4522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16581
74313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1658174313
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2088603009
Short name T36
Test name
Test status
Simulation time 142175656 ps
CPU time 0.79 seconds
Started Jun 10 05:26:06 PM PDT 24
Finished Jun 10 05:26:07 PM PDT 24
Peak memory 205040 kb
Host smart-12a4728f-abc3-47b7-8023-856698af5d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20886
03009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2088603009
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.4039796276
Short name T504
Test name
Test status
Simulation time 32641317 ps
CPU time 0.65 seconds
Started Jun 10 05:26:05 PM PDT 24
Finished Jun 10 05:26:07 PM PDT 24
Peak memory 204964 kb
Host smart-d8872ad7-cb39-4b4b-a272-49c27b922d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40397
96276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.4039796276
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3783362201
Short name T1158
Test name
Test status
Simulation time 794928878 ps
CPU time 1.97 seconds
Started Jun 10 05:26:05 PM PDT 24
Finished Jun 10 05:26:08 PM PDT 24
Peak memory 205056 kb
Host smart-8fbe8b36-1418-4d72-a54a-abfd3cbdaf11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37833
62201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3783362201
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3698021037
Short name T766
Test name
Test status
Simulation time 270870105 ps
CPU time 1.85 seconds
Started Jun 10 05:26:12 PM PDT 24
Finished Jun 10 05:26:14 PM PDT 24
Peak memory 205188 kb
Host smart-4e4700db-9300-4a18-8155-93c6bafe3e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36980
21037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3698021037
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.900126140
Short name T1834
Test name
Test status
Simulation time 172386953 ps
CPU time 0.83 seconds
Started Jun 10 05:26:09 PM PDT 24
Finished Jun 10 05:26:11 PM PDT 24
Peak memory 205036 kb
Host smart-d76e72bd-68ba-414c-9b60-ec90ea888aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90012
6140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.900126140
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1309683547
Short name T589
Test name
Test status
Simulation time 143934623 ps
CPU time 0.75 seconds
Started Jun 10 05:26:21 PM PDT 24
Finished Jun 10 05:26:22 PM PDT 24
Peak memory 205028 kb
Host smart-3e5eaf6f-c802-4eb6-bfa4-cff3e5f61e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13096
83547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1309683547
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1831123235
Short name T671
Test name
Test status
Simulation time 203344539 ps
CPU time 0.87 seconds
Started Jun 10 05:26:03 PM PDT 24
Finished Jun 10 05:26:05 PM PDT 24
Peak memory 205020 kb
Host smart-0c3256e7-350c-4da7-b7cb-4fc427cc2457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18311
23235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1831123235
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.898697305
Short name T613
Test name
Test status
Simulation time 202255045 ps
CPU time 0.87 seconds
Started Jun 10 05:26:12 PM PDT 24
Finished Jun 10 05:26:13 PM PDT 24
Peak memory 205008 kb
Host smart-ea1db421-cbaa-4953-94a0-2bc68915aa20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89869
7305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.898697305
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2440283710
Short name T166
Test name
Test status
Simulation time 3266720438 ps
CPU time 4.86 seconds
Started Jun 10 05:26:07 PM PDT 24
Finished Jun 10 05:26:13 PM PDT 24
Peak memory 205072 kb
Host smart-a757b499-77ac-46b2-b13a-67fdeb5f925d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24402
83710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2440283710
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2818890432
Short name T1824
Test name
Test status
Simulation time 253463844 ps
CPU time 0.98 seconds
Started Jun 10 05:26:06 PM PDT 24
Finished Jun 10 05:26:08 PM PDT 24
Peak memory 205060 kb
Host smart-0129a85b-109f-4d9d-9fba-7c67d49fdc32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28188
90432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2818890432
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.1395386785
Short name T728
Test name
Test status
Simulation time 6987143013 ps
CPU time 186.97 seconds
Started Jun 10 05:26:08 PM PDT 24
Finished Jun 10 05:29:15 PM PDT 24
Peak memory 205216 kb
Host smart-8415c778-51c7-4df6-841c-b17ec4dd17d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13953
86785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.1395386785
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1565870861
Short name T569
Test name
Test status
Simulation time 159004766 ps
CPU time 0.81 seconds
Started Jun 10 05:26:06 PM PDT 24
Finished Jun 10 05:26:08 PM PDT 24
Peak memory 204976 kb
Host smart-fb269adf-0fa1-421b-b6a0-45c5adf4e7a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15658
70861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1565870861
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3436711189
Short name T144
Test name
Test status
Simulation time 219403113 ps
CPU time 0.9 seconds
Started Jun 10 05:26:19 PM PDT 24
Finished Jun 10 05:26:20 PM PDT 24
Peak memory 205036 kb
Host smart-5508e3e6-4a80-4fb4-93c3-5a8adad47e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34367
11189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3436711189
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.397184838
Short name T1401
Test name
Test status
Simulation time 187568366 ps
CPU time 0.9 seconds
Started Jun 10 05:26:14 PM PDT 24
Finished Jun 10 05:26:16 PM PDT 24
Peak memory 205008 kb
Host smart-588d09d5-f783-4659-971a-4e7c8350b90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39718
4838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.397184838
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.484569469
Short name T999
Test name
Test status
Simulation time 191676472 ps
CPU time 0.84 seconds
Started Jun 10 05:26:21 PM PDT 24
Finished Jun 10 05:26:22 PM PDT 24
Peak memory 205032 kb
Host smart-c4cf15c9-065c-42a4-9487-db72b2e992f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48456
9469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.484569469
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.125610741
Short name T1222
Test name
Test status
Simulation time 183938209 ps
CPU time 0.84 seconds
Started Jun 10 05:26:14 PM PDT 24
Finished Jun 10 05:26:15 PM PDT 24
Peak memory 205012 kb
Host smart-afa53088-3be8-4b24-aec3-f461a17efd9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12561
0741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.125610741
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.1831253451
Short name T1076
Test name
Test status
Simulation time 162295072 ps
CPU time 0.8 seconds
Started Jun 10 05:26:21 PM PDT 24
Finished Jun 10 05:26:22 PM PDT 24
Peak memory 205036 kb
Host smart-da4ba1a1-7e42-46cf-91a9-bc4186ad20af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18312
53451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1831253451
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_eop_single_bit_handling.3381988144
Short name T898
Test name
Test status
Simulation time 201942761 ps
CPU time 0.85 seconds
Started Jun 10 05:26:22 PM PDT 24
Finished Jun 10 05:26:24 PM PDT 24
Peak memory 204856 kb
Host smart-f194cd89-53f8-4f95-94f8-c3e11ef4cbe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33819
88144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_eop_single_bit_handling.3381988144
Directory /workspace/20.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.269206476
Short name T2064
Test name
Test status
Simulation time 172420260 ps
CPU time 0.8 seconds
Started Jun 10 05:26:09 PM PDT 24
Finished Jun 10 05:26:11 PM PDT 24
Peak memory 204932 kb
Host smart-4e2d136d-05f2-4ebc-8dd2-5b36cb40d540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26920
6476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.269206476
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2303991212
Short name T40
Test name
Test status
Simulation time 122117065 ps
CPU time 0.72 seconds
Started Jun 10 05:26:09 PM PDT 24
Finished Jun 10 05:26:10 PM PDT 24
Peak memory 205028 kb
Host smart-34024cf6-b257-4af8-9dd2-6dff5e9740eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23039
91212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2303991212
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.2189060187
Short name T201
Test name
Test status
Simulation time 13375718445 ps
CPU time 29.7 seconds
Started Jun 10 05:26:12 PM PDT 24
Finished Jun 10 05:26:42 PM PDT 24
Peak memory 205180 kb
Host smart-85f9166f-2e12-4f81-ab7e-06cba9afa79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21890
60187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.2189060187
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2957767595
Short name T888
Test name
Test status
Simulation time 148911721 ps
CPU time 0.79 seconds
Started Jun 10 05:26:17 PM PDT 24
Finished Jun 10 05:26:18 PM PDT 24
Peak memory 205004 kb
Host smart-9d2f7247-624e-4703-902b-1fb00eb9727e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29577
67595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2957767595
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2208538769
Short name T1999
Test name
Test status
Simulation time 166399586 ps
CPU time 0.82 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:26:26 PM PDT 24
Peak memory 205020 kb
Host smart-1fbf041f-4843-4049-b971-9bac76695ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22085
38769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2208538769
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.4148824645
Short name T1293
Test name
Test status
Simulation time 177351057 ps
CPU time 0.94 seconds
Started Jun 10 05:26:09 PM PDT 24
Finished Jun 10 05:26:11 PM PDT 24
Peak memory 205000 kb
Host smart-70892579-283d-4967-aac4-4b0184943362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41488
24645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.4148824645
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.511919006
Short name T1147
Test name
Test status
Simulation time 169904249 ps
CPU time 0.8 seconds
Started Jun 10 05:26:10 PM PDT 24
Finished Jun 10 05:26:11 PM PDT 24
Peak memory 204904 kb
Host smart-06aaf8b8-0aed-42cb-8192-b2596370a684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51191
9006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.511919006
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3388920992
Short name T805
Test name
Test status
Simulation time 175985470 ps
CPU time 0.8 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 204868 kb
Host smart-9e9d7618-3e55-41a6-bfcb-688d0c07f4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33889
20992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3388920992
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1424286823
Short name T936
Test name
Test status
Simulation time 150980954 ps
CPU time 0.85 seconds
Started Jun 10 05:26:10 PM PDT 24
Finished Jun 10 05:26:11 PM PDT 24
Peak memory 204924 kb
Host smart-49348943-a14c-4124-a48e-41a665786c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14242
86823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1424286823
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3633650089
Short name T1463
Test name
Test status
Simulation time 225645762 ps
CPU time 0.95 seconds
Started Jun 10 05:26:10 PM PDT 24
Finished Jun 10 05:26:11 PM PDT 24
Peak memory 205072 kb
Host smart-38c9fd58-1840-4163-898c-30c85d0408f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36336
50089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3633650089
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.928687415
Short name T813
Test name
Test status
Simulation time 190842215 ps
CPU time 0.85 seconds
Started Jun 10 05:26:13 PM PDT 24
Finished Jun 10 05:26:15 PM PDT 24
Peak memory 205004 kb
Host smart-4cc97b69-6b67-43af-94db-ed862af4fc3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92868
7415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.928687415
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.366177653
Short name T302
Test name
Test status
Simulation time 176071121 ps
CPU time 0.83 seconds
Started Jun 10 05:26:12 PM PDT 24
Finished Jun 10 05:26:13 PM PDT 24
Peak memory 205028 kb
Host smart-035c4823-9998-4be0-8925-6ddecbe69d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36617
7653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.366177653
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.866212923
Short name T1250
Test name
Test status
Simulation time 5098491883 ps
CPU time 135.38 seconds
Started Jun 10 05:26:08 PM PDT 24
Finished Jun 10 05:28:24 PM PDT 24
Peak memory 205216 kb
Host smart-3a2b75a0-21cf-4219-8f6a-f6b77a78303b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86621
2923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.866212923
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.3213512246
Short name T1310
Test name
Test status
Simulation time 243752350 ps
CPU time 0.91 seconds
Started Jun 10 05:26:28 PM PDT 24
Finished Jun 10 05:26:30 PM PDT 24
Peak memory 205020 kb
Host smart-68d3c40c-81fe-4b3d-a1b4-e3c0e610e89a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3213512246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.3213512246
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.569293256
Short name T779
Test name
Test status
Simulation time 228735845 ps
CPU time 0.95 seconds
Started Jun 10 05:26:29 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205012 kb
Host smart-e4395893-4d8d-4168-b352-21fd030ea19a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=569293256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.569293256
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.3329752981
Short name T1831
Test name
Test status
Simulation time 238688176 ps
CPU time 0.93 seconds
Started Jun 10 05:26:15 PM PDT 24
Finished Jun 10 05:26:16 PM PDT 24
Peak memory 205028 kb
Host smart-3097fb91-24c4-460e-8897-46e478ca66d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33297
52981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.3329752981
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3927371559
Short name T1131
Test name
Test status
Simulation time 3743298030 ps
CPU time 5.07 seconds
Started Jun 10 05:26:10 PM PDT 24
Finished Jun 10 05:26:16 PM PDT 24
Peak memory 205240 kb
Host smart-538b143f-78f5-40c5-8ee2-9ea02ecb2747
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3927371559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.3927371559
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3987647004
Short name T1774
Test name
Test status
Simulation time 13405497360 ps
CPU time 12.97 seconds
Started Jun 10 05:26:28 PM PDT 24
Finished Jun 10 05:26:42 PM PDT 24
Peak memory 204992 kb
Host smart-f0601a2a-3547-46e1-9ad0-71b899ceee64
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3987647004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3987647004
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.669432121
Short name T2008
Test name
Test status
Simulation time 23365838908 ps
CPU time 22.58 seconds
Started Jun 10 05:26:08 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205112 kb
Host smart-760943d9-4cf5-424c-bb1b-06d20af3ee0c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=669432121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.669432121
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1525944280
Short name T1040
Test name
Test status
Simulation time 152826671 ps
CPU time 0.82 seconds
Started Jun 10 05:26:23 PM PDT 24
Finished Jun 10 05:26:25 PM PDT 24
Peak memory 205008 kb
Host smart-fdf97712-3a09-4eb4-8853-ad7fe46f1e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15259
44280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1525944280
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.3880957052
Short name T229
Test name
Test status
Simulation time 219386301 ps
CPU time 0.93 seconds
Started Jun 10 05:26:13 PM PDT 24
Finished Jun 10 05:26:15 PM PDT 24
Peak memory 205044 kb
Host smart-e4624842-c5ef-4e1b-bc67-123faffd0cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38809
57052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.3880957052
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2311377449
Short name T935
Test name
Test status
Simulation time 909057423 ps
CPU time 2.11 seconds
Started Jun 10 05:26:28 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205112 kb
Host smart-47c95fe2-88a1-4a31-af92-d1ebd6ac5663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23113
77449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2311377449
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.2526030000
Short name T68
Test name
Test status
Simulation time 150816026 ps
CPU time 0.74 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:26:26 PM PDT 24
Peak memory 205004 kb
Host smart-e5d179d4-32cf-4f1e-a1d0-2de62ee20590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25260
30000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.2526030000
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.254248191
Short name T1023
Test name
Test status
Simulation time 48511035 ps
CPU time 0.71 seconds
Started Jun 10 05:26:23 PM PDT 24
Finished Jun 10 05:26:24 PM PDT 24
Peak memory 205004 kb
Host smart-4d41ab5d-de21-478f-8ce6-e7de8623dd4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25424
8191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.254248191
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.243487233
Short name T2009
Test name
Test status
Simulation time 701480818 ps
CPU time 1.86 seconds
Started Jun 10 05:26:26 PM PDT 24
Finished Jun 10 05:26:29 PM PDT 24
Peak memory 205072 kb
Host smart-f1adb3ab-bfac-42ba-bda9-c8e2a0a99a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24348
7233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.243487233
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.4191860916
Short name T1054
Test name
Test status
Simulation time 337579835 ps
CPU time 2.08 seconds
Started Jun 10 05:26:10 PM PDT 24
Finished Jun 10 05:26:13 PM PDT 24
Peak memory 205056 kb
Host smart-74eef73c-cddb-4bbb-a11c-7ee1ee3ac224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41918
60916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.4191860916
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.821520274
Short name T1907
Test name
Test status
Simulation time 206408030 ps
CPU time 0.85 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:29 PM PDT 24
Peak memory 205004 kb
Host smart-6f5ce93b-02e8-4da3-a6d2-be99c0c792de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82152
0274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.821520274
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.4260219077
Short name T603
Test name
Test status
Simulation time 147742602 ps
CPU time 0.78 seconds
Started Jun 10 05:26:28 PM PDT 24
Finished Jun 10 05:26:30 PM PDT 24
Peak memory 205028 kb
Host smart-c5091747-600d-47a4-823f-7f8e41650dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42602
19077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.4260219077
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1878965589
Short name T22
Test name
Test status
Simulation time 257377612 ps
CPU time 0.98 seconds
Started Jun 10 05:26:11 PM PDT 24
Finished Jun 10 05:26:12 PM PDT 24
Peak memory 205076 kb
Host smart-66027b66-c498-4793-b5ae-7e2f5a5db51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18789
65589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1878965589
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.2481938260
Short name T464
Test name
Test status
Simulation time 169338159 ps
CPU time 0.84 seconds
Started Jun 10 05:26:10 PM PDT 24
Finished Jun 10 05:26:12 PM PDT 24
Peak memory 205076 kb
Host smart-fc1a7d63-6159-444c-a69d-4fec2214f603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24819
38260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.2481938260
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3224080906
Short name T1130
Test name
Test status
Simulation time 3306432585 ps
CPU time 4.02 seconds
Started Jun 10 05:26:13 PM PDT 24
Finished Jun 10 05:26:18 PM PDT 24
Peak memory 205100 kb
Host smart-9caa3380-a917-4a8e-86dd-c4c141eab240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32240
80906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3224080906
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.651694042
Short name T1840
Test name
Test status
Simulation time 187972842 ps
CPU time 0.87 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:29 PM PDT 24
Peak memory 205012 kb
Host smart-703128f8-d603-41bf-a647-cea035838fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65169
4042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.651694042
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.2241152671
Short name T1312
Test name
Test status
Simulation time 10538158860 ps
CPU time 76.13 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:27:42 PM PDT 24
Peak memory 205160 kb
Host smart-9453a380-89b0-4695-b022-c28cc4073b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22411
52671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.2241152671
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3016440695
Short name T1804
Test name
Test status
Simulation time 158361580 ps
CPU time 0.77 seconds
Started Jun 10 05:26:19 PM PDT 24
Finished Jun 10 05:26:20 PM PDT 24
Peak memory 205020 kb
Host smart-8d308dc2-aa79-48a5-9212-bebfc001ac4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30164
40695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3016440695
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.179160509
Short name T1297
Test name
Test status
Simulation time 199437417 ps
CPU time 0.85 seconds
Started Jun 10 05:26:26 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 205044 kb
Host smart-e663f63d-ea65-418a-8409-04fff3fc10ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17916
0509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.179160509
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.391616376
Short name T1317
Test name
Test status
Simulation time 194726550 ps
CPU time 0.88 seconds
Started Jun 10 05:26:10 PM PDT 24
Finished Jun 10 05:26:12 PM PDT 24
Peak memory 205076 kb
Host smart-acf39ed4-8c96-4298-84a7-618855487764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39161
6376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.391616376
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.133281863
Short name T843
Test name
Test status
Simulation time 153204679 ps
CPU time 0.85 seconds
Started Jun 10 05:26:11 PM PDT 24
Finished Jun 10 05:26:12 PM PDT 24
Peak memory 204880 kb
Host smart-bfd21f69-05fa-4efd-a340-49df5ad799b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13328
1863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.133281863
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1215732413
Short name T385
Test name
Test status
Simulation time 164810646 ps
CPU time 0.93 seconds
Started Jun 10 05:26:13 PM PDT 24
Finished Jun 10 05:26:14 PM PDT 24
Peak memory 205012 kb
Host smart-2dc2490f-0aa2-4954-973c-0b7bad2f1730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12157
32413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1215732413
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.442134720
Short name T1817
Test name
Test status
Simulation time 165167621 ps
CPU time 0.79 seconds
Started Jun 10 05:26:17 PM PDT 24
Finished Jun 10 05:26:19 PM PDT 24
Peak memory 205008 kb
Host smart-a7a4066a-9515-497c-b69a-884eac1f5741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44213
4720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.442134720
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_eop_single_bit_handling.3222004366
Short name T381
Test name
Test status
Simulation time 189309296 ps
CPU time 0.89 seconds
Started Jun 10 05:26:29 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205040 kb
Host smart-27968344-e52e-49ea-ab56-e8385df152d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32220
04366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_eop_single_bit_handling.3222004366
Directory /workspace/21.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2941841559
Short name T1747
Test name
Test status
Simulation time 160885368 ps
CPU time 0.75 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:26:27 PM PDT 24
Peak memory 205076 kb
Host smart-71b9543e-6450-4825-b8c3-04215ea277ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29418
41559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2941841559
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1761253458
Short name T1242
Test name
Test status
Simulation time 41098669 ps
CPU time 0.65 seconds
Started Jun 10 05:26:14 PM PDT 24
Finished Jun 10 05:26:15 PM PDT 24
Peak memory 205080 kb
Host smart-0e87b494-fdd1-468f-9ff4-df8ec2108362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17612
53458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1761253458
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3027521191
Short name T1486
Test name
Test status
Simulation time 15074842865 ps
CPU time 33.1 seconds
Started Jun 10 05:26:19 PM PDT 24
Finished Jun 10 05:26:53 PM PDT 24
Peak memory 205276 kb
Host smart-fb03bb4f-e8f6-43a1-8aea-1a7e21d7f59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30275
21191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3027521191
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1190604031
Short name T1967
Test name
Test status
Simulation time 150810514 ps
CPU time 0.79 seconds
Started Jun 10 05:26:10 PM PDT 24
Finished Jun 10 05:26:11 PM PDT 24
Peak memory 205020 kb
Host smart-0cc7b916-d9c5-43c9-87d2-f3f07f865f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11906
04031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1190604031
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1237596743
Short name T1279
Test name
Test status
Simulation time 203724755 ps
CPU time 0.89 seconds
Started Jun 10 05:26:09 PM PDT 24
Finished Jun 10 05:26:11 PM PDT 24
Peak memory 205136 kb
Host smart-b256ac14-b4f5-4984-a12e-e507f22b0411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12375
96743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1237596743
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.4253467687
Short name T1718
Test name
Test status
Simulation time 179153576 ps
CPU time 0.84 seconds
Started Jun 10 05:26:16 PM PDT 24
Finished Jun 10 05:26:18 PM PDT 24
Peak memory 205004 kb
Host smart-13080a0f-9288-4985-a4fe-031fb20dcd0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42534
67687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.4253467687
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3098007350
Short name T576
Test name
Test status
Simulation time 147438123 ps
CPU time 0.76 seconds
Started Jun 10 05:26:29 PM PDT 24
Finished Jun 10 05:26:33 PM PDT 24
Peak memory 205004 kb
Host smart-2fe70ab8-3c55-4667-9cd7-4db9d7068bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30980
07350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3098007350
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.349172702
Short name T642
Test name
Test status
Simulation time 172163244 ps
CPU time 0.83 seconds
Started Jun 10 05:26:24 PM PDT 24
Finished Jun 10 05:26:26 PM PDT 24
Peak memory 204952 kb
Host smart-3ba82de4-6f1f-4163-b35d-53c45d216772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34917
2702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.349172702
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3485406969
Short name T24
Test name
Test status
Simulation time 151918026 ps
CPU time 0.8 seconds
Started Jun 10 05:26:26 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 204996 kb
Host smart-869d922d-799e-4558-b4b9-4997c2a01921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34854
06969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3485406969
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.647158398
Short name T1435
Test name
Test status
Simulation time 232292960 ps
CPU time 1.02 seconds
Started Jun 10 05:26:24 PM PDT 24
Finished Jun 10 05:26:26 PM PDT 24
Peak memory 205056 kb
Host smart-972ce6d8-f3b6-49ba-8a50-40ddab07170c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64715
8398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.647158398
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.703008975
Short name T1970
Test name
Test status
Simulation time 221745201 ps
CPU time 0.86 seconds
Started Jun 10 05:26:28 PM PDT 24
Finished Jun 10 05:26:30 PM PDT 24
Peak memory 205004 kb
Host smart-9e67a823-d5c3-49a7-bad9-fe631501ec80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70300
8975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.703008975
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.341534438
Short name T1426
Test name
Test status
Simulation time 174365787 ps
CPU time 0.88 seconds
Started Jun 10 05:26:26 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 204996 kb
Host smart-84448062-0929-47e1-88e7-4ef079a57f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34153
4438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.341534438
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.1718470343
Short name T2024
Test name
Test status
Simulation time 14721966432 ps
CPU time 414.51 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:33:20 PM PDT 24
Peak memory 204984 kb
Host smart-a1b18a6d-3b14-40c5-9c97-7b467db3bea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17184
70343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.1718470343
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.3869637522
Short name T2112
Test name
Test status
Simulation time 243043946 ps
CPU time 1.01 seconds
Started Jun 10 05:26:19 PM PDT 24
Finished Jun 10 05:26:21 PM PDT 24
Peak memory 204980 kb
Host smart-8e6498ac-5775-40f7-bdaa-871d40cc6860
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3869637522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.3869637522
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.2794126647
Short name T2038
Test name
Test status
Simulation time 183203310 ps
CPU time 0.84 seconds
Started Jun 10 05:26:20 PM PDT 24
Finished Jun 10 05:26:21 PM PDT 24
Peak memory 205064 kb
Host smart-feec7990-e527-4d50-bc7a-4022f26c05d2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2794126647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.2794126647
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.2035041179
Short name T893
Test name
Test status
Simulation time 252300016 ps
CPU time 0.97 seconds
Started Jun 10 05:26:26 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 205016 kb
Host smart-cf6706d5-5575-46d0-ab7e-aa9cc32fd02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20350
41179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.2035041179
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.533878910
Short name T754
Test name
Test status
Simulation time 4164229944 ps
CPU time 5.01 seconds
Started Jun 10 05:26:12 PM PDT 24
Finished Jun 10 05:26:18 PM PDT 24
Peak memory 205172 kb
Host smart-e0317466-63c4-44fb-bb58-ccb3469849cf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=533878910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.533878910
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3795623302
Short name T836
Test name
Test status
Simulation time 13383719043 ps
CPU time 15.28 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:43 PM PDT 24
Peak memory 205092 kb
Host smart-1c898674-5e23-4fbb-9807-e79a1f7351cd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3795623302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3795623302
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.3152136065
Short name T318
Test name
Test status
Simulation time 23331789710 ps
CPU time 30.12 seconds
Started Jun 10 05:26:14 PM PDT 24
Finished Jun 10 05:26:45 PM PDT 24
Peak memory 205208 kb
Host smart-0403e2d8-9501-4a12-8ece-264f2bcc9682
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3152136065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.3152136065
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.59553193
Short name T1295
Test name
Test status
Simulation time 191025593 ps
CPU time 0.85 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:26:26 PM PDT 24
Peak memory 205092 kb
Host smart-a68a4514-05d6-4ca2-b6bc-5852930653b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59553
193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.59553193
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.563949187
Short name T339
Test name
Test status
Simulation time 149149333 ps
CPU time 0.76 seconds
Started Jun 10 05:26:13 PM PDT 24
Finished Jun 10 05:26:14 PM PDT 24
Peak memory 205144 kb
Host smart-53597cdd-18c3-488d-b3e4-3a541f401386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56394
9187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.563949187
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.3846146967
Short name T205
Test name
Test status
Simulation time 1123690759 ps
CPU time 2.35 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 205160 kb
Host smart-f9c268a3-2678-494f-9984-9c4264647063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38461
46967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.3846146967
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.3456891543
Short name T1105
Test name
Test status
Simulation time 146403423 ps
CPU time 0.8 seconds
Started Jun 10 05:26:18 PM PDT 24
Finished Jun 10 05:26:19 PM PDT 24
Peak memory 205008 kb
Host smart-d38003ad-7e8e-4858-a27b-7b729e9d8239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34568
91543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.3456891543
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.2556432738
Short name T789
Test name
Test status
Simulation time 41877141 ps
CPU time 0.67 seconds
Started Jun 10 05:26:29 PM PDT 24
Finished Jun 10 05:26:33 PM PDT 24
Peak memory 204984 kb
Host smart-d9e5b989-dcf5-4a44-9610-404b45912685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25564
32738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2556432738
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3095433069
Short name T794
Test name
Test status
Simulation time 827571701 ps
CPU time 2 seconds
Started Jun 10 05:26:26 PM PDT 24
Finished Jun 10 05:26:29 PM PDT 24
Peak memory 205104 kb
Host smart-fb854bfb-20b9-41a4-b23c-4192343e273b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30954
33069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3095433069
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.301450282
Short name T653
Test name
Test status
Simulation time 204482956 ps
CPU time 2.37 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 205052 kb
Host smart-6a1a3636-1c32-4abf-a0dc-9db6722fcaa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30145
0282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.301450282
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.326325104
Short name T73
Test name
Test status
Simulation time 182291391 ps
CPU time 0.86 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:30 PM PDT 24
Peak memory 205004 kb
Host smart-55341561-b707-4426-9dca-f3223ca0c76f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32632
5104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.326325104
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3678243857
Short name T801
Test name
Test status
Simulation time 136506325 ps
CPU time 0.75 seconds
Started Jun 10 05:26:20 PM PDT 24
Finished Jun 10 05:26:21 PM PDT 24
Peak memory 204980 kb
Host smart-52feeb4d-cf66-4a50-be90-8a5326725b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36782
43857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3678243857
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3717542486
Short name T1116
Test name
Test status
Simulation time 245974992 ps
CPU time 0.98 seconds
Started Jun 10 05:26:12 PM PDT 24
Finished Jun 10 05:26:13 PM PDT 24
Peak memory 205020 kb
Host smart-b9f6c088-785e-4b2d-8611-4387a23bcf05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37175
42486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3717542486
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3467200420
Short name T2080
Test name
Test status
Simulation time 180671058 ps
CPU time 0.81 seconds
Started Jun 10 05:26:26 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 205008 kb
Host smart-e4fd21a0-af42-4e33-98d6-206c1f5a3336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34672
00420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3467200420
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2765616190
Short name T124
Test name
Test status
Simulation time 3306526554 ps
CPU time 4.42 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:26:29 PM PDT 24
Peak memory 204936 kb
Host smart-3b32b008-f6dc-4416-b34c-a5c5d39af323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27656
16190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2765616190
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3609815226
Short name T1879
Test name
Test status
Simulation time 224553124 ps
CPU time 0.86 seconds
Started Jun 10 05:26:13 PM PDT 24
Finished Jun 10 05:26:14 PM PDT 24
Peak memory 205004 kb
Host smart-ef0a5db8-7a33-4bdb-b3ae-f9241a51d891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36098
15226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3609815226
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.831888720
Short name T1106
Test name
Test status
Simulation time 11477241044 ps
CPU time 316.55 seconds
Started Jun 10 05:26:15 PM PDT 24
Finished Jun 10 05:31:32 PM PDT 24
Peak memory 205236 kb
Host smart-a0f31ebf-a271-439f-aba5-9eabbdc85d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83188
8720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.831888720
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3433402944
Short name T1325
Test name
Test status
Simulation time 143066200 ps
CPU time 0.75 seconds
Started Jun 10 05:26:14 PM PDT 24
Finished Jun 10 05:26:15 PM PDT 24
Peak memory 204932 kb
Host smart-c5d44fb0-28bf-4aa8-bed5-24c87db1cb46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34334
02944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3433402944
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.2019417958
Short name T650
Test name
Test status
Simulation time 171861614 ps
CPU time 0.83 seconds
Started Jun 10 05:26:26 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 204988 kb
Host smart-dbf4f05c-e796-4b97-bc3c-6e38c4657c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20194
17958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.2019417958
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2619200384
Short name T84
Test name
Test status
Simulation time 150305807 ps
CPU time 0.77 seconds
Started Jun 10 05:26:37 PM PDT 24
Finished Jun 10 05:26:38 PM PDT 24
Peak memory 205000 kb
Host smart-5a5b157d-a199-47d6-aa97-0860f045c47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26192
00384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2619200384
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.995010839
Short name T1220
Test name
Test status
Simulation time 154764121 ps
CPU time 0.8 seconds
Started Jun 10 05:26:18 PM PDT 24
Finished Jun 10 05:26:19 PM PDT 24
Peak memory 205008 kb
Host smart-800a24a1-e571-4f5b-a016-3a638f4ee7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99501
0839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.995010839
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3174390613
Short name T1637
Test name
Test status
Simulation time 184365129 ps
CPU time 0.84 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:30 PM PDT 24
Peak memory 205044 kb
Host smart-5918d1ee-a8e0-41ee-80ee-01f840fe7ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31743
90613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3174390613
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_eop_single_bit_handling.2941127423
Short name T330
Test name
Test status
Simulation time 183788756 ps
CPU time 0.88 seconds
Started Jun 10 05:26:16 PM PDT 24
Finished Jun 10 05:26:17 PM PDT 24
Peak memory 205148 kb
Host smart-504698a5-cab4-473e-8832-778886f71d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29411
27423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_eop_single_bit_handling.2941127423
Directory /workspace/22.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.1419748061
Short name T1945
Test name
Test status
Simulation time 141514475 ps
CPU time 0.81 seconds
Started Jun 10 05:26:29 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205036 kb
Host smart-b7578be9-bc27-457e-a29d-0d9506841a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14197
48061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.1419748061
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1673358017
Short name T634
Test name
Test status
Simulation time 36177720 ps
CPU time 0.65 seconds
Started Jun 10 05:26:20 PM PDT 24
Finished Jun 10 05:26:21 PM PDT 24
Peak memory 204960 kb
Host smart-abc915d1-7594-4fc6-b003-f9e7030b6777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16733
58017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1673358017
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.125977476
Short name T447
Test name
Test status
Simulation time 19004082780 ps
CPU time 45.68 seconds
Started Jun 10 05:26:16 PM PDT 24
Finished Jun 10 05:27:02 PM PDT 24
Peak memory 205164 kb
Host smart-e6f13059-698b-4320-ac27-0f0ac418246b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12597
7476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.125977476
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2041356203
Short name T545
Test name
Test status
Simulation time 149244361 ps
CPU time 0.85 seconds
Started Jun 10 05:26:17 PM PDT 24
Finished Jun 10 05:26:18 PM PDT 24
Peak memory 205032 kb
Host smart-fa45f2c6-96ff-4637-9e8e-37acb252623c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20413
56203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2041356203
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2282603258
Short name T809
Test name
Test status
Simulation time 241327055 ps
CPU time 0.93 seconds
Started Jun 10 05:26:32 PM PDT 24
Finished Jun 10 05:26:34 PM PDT 24
Peak memory 204984 kb
Host smart-b8109041-53ec-4e5e-9ec9-415c9d20a677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22826
03258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2282603258
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.3428078829
Short name T871
Test name
Test status
Simulation time 162727861 ps
CPU time 0.85 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:29 PM PDT 24
Peak memory 205008 kb
Host smart-0cd5a8e1-359c-4bcc-b05d-a5540ddbf0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34280
78829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.3428078829
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.758253518
Short name T2047
Test name
Test status
Simulation time 135466075 ps
CPU time 0.75 seconds
Started Jun 10 05:26:29 PM PDT 24
Finished Jun 10 05:26:30 PM PDT 24
Peak memory 205040 kb
Host smart-5a0d5d66-167a-4db4-9b37-06d1af3fca8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75825
3518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.758253518
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.585635391
Short name T612
Test name
Test status
Simulation time 141839327 ps
CPU time 0.76 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:30 PM PDT 24
Peak memory 205008 kb
Host smart-3f067154-9e08-4701-a281-33b0615eed13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58563
5391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.585635391
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1164051643
Short name T1185
Test name
Test status
Simulation time 179849342 ps
CPU time 0.79 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:26:27 PM PDT 24
Peak memory 205012 kb
Host smart-5ded471d-ef14-4ea7-be89-6099d97560ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11640
51643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1164051643
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1564713659
Short name T1550
Test name
Test status
Simulation time 228234557 ps
CPU time 0.97 seconds
Started Jun 10 05:26:29 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205028 kb
Host smart-7130ec41-e061-4872-89a6-495fe2189b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15647
13659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1564713659
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.950345539
Short name T1072
Test name
Test status
Simulation time 180440030 ps
CPU time 0.84 seconds
Started Jun 10 05:26:16 PM PDT 24
Finished Jun 10 05:26:17 PM PDT 24
Peak memory 205000 kb
Host smart-679b9d40-f01f-463b-a7a0-1b09c81cbb59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95034
5539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.950345539
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.4272312213
Short name T1672
Test name
Test status
Simulation time 172656813 ps
CPU time 0.82 seconds
Started Jun 10 05:26:18 PM PDT 24
Finished Jun 10 05:26:19 PM PDT 24
Peak memory 204972 kb
Host smart-aaec92d5-13cd-4888-b679-f8043e79305d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42723
12213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.4272312213
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.1673333834
Short name T578
Test name
Test status
Simulation time 14772723789 ps
CPU time 106.29 seconds
Started Jun 10 05:26:14 PM PDT 24
Finished Jun 10 05:28:01 PM PDT 24
Peak memory 205216 kb
Host smart-fd02bfdc-6e30-473c-a781-ae25cee1fdfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16733
33834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.1673333834
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.961514626
Short name T1269
Test name
Test status
Simulation time 261382120 ps
CPU time 1.02 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:29 PM PDT 24
Peak memory 204996 kb
Host smart-c54aa0de-6171-485e-b4d8-eee6fe0f9eb3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=961514626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.961514626
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.3097244693
Short name T910
Test name
Test status
Simulation time 152953704 ps
CPU time 0.81 seconds
Started Jun 10 05:26:32 PM PDT 24
Finished Jun 10 05:26:34 PM PDT 24
Peak memory 205040 kb
Host smart-d82d6cab-21db-4473-9123-6b14f0f97087
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3097244693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.3097244693
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.3586024551
Short name T1425
Test name
Test status
Simulation time 184490123 ps
CPU time 0.85 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 204996 kb
Host smart-f1c7b2be-3447-43ff-aba0-759f1d2847fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35860
24551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.3586024551
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3416500124
Short name T1943
Test name
Test status
Simulation time 3827292816 ps
CPU time 4.62 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:33 PM PDT 24
Peak memory 205248 kb
Host smart-fb3a4b3c-87eb-4a3e-8ec2-0d18851f9000
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3416500124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.3416500124
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.3763682937
Short name T115
Test name
Test status
Simulation time 13387347837 ps
CPU time 12.75 seconds
Started Jun 10 05:26:18 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205132 kb
Host smart-fada876b-909e-42f9-8a74-68f2fe8720d9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3763682937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3763682937
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.3699032937
Short name T1330
Test name
Test status
Simulation time 23324370206 ps
CPU time 26.96 seconds
Started Jun 10 05:26:19 PM PDT 24
Finished Jun 10 05:26:47 PM PDT 24
Peak memory 205124 kb
Host smart-71f13ba7-530e-47bc-883e-fb8b26088ca4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3699032937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.3699032937
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3348519999
Short name T462
Test name
Test status
Simulation time 179972970 ps
CPU time 0.8 seconds
Started Jun 10 05:26:28 PM PDT 24
Finished Jun 10 05:26:30 PM PDT 24
Peak memory 204988 kb
Host smart-19b65c9e-c844-4a5b-b77b-f3b9d70f90fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33485
19999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3348519999
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.424352015
Short name T1607
Test name
Test status
Simulation time 212828781 ps
CPU time 0.84 seconds
Started Jun 10 05:26:23 PM PDT 24
Finished Jun 10 05:26:25 PM PDT 24
Peak memory 205052 kb
Host smart-77012bc7-a4a0-436e-ab18-354bd1e5b5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42435
2015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.424352015
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.4175136357
Short name T69
Test name
Test status
Simulation time 1232069194 ps
CPU time 2.71 seconds
Started Jun 10 05:26:19 PM PDT 24
Finished Jun 10 05:26:22 PM PDT 24
Peak memory 205088 kb
Host smart-22797d99-e58b-4687-8c29-45ebcf6e7a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41751
36357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.4175136357
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.2096168359
Short name T371
Test name
Test status
Simulation time 143229747 ps
CPU time 0.79 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:26:27 PM PDT 24
Peak memory 205024 kb
Host smart-07285c61-cf2c-45d1-bd7d-6105e88a3670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20961
68359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2096168359
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3903403066
Short name T1051
Test name
Test status
Simulation time 51357717 ps
CPU time 0.68 seconds
Started Jun 10 05:26:20 PM PDT 24
Finished Jun 10 05:26:21 PM PDT 24
Peak memory 204996 kb
Host smart-19e62dec-b8dc-4bca-b41b-6ada82e9fb1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39034
03066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3903403066
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.1129135890
Short name T901
Test name
Test status
Simulation time 988226388 ps
CPU time 2.3 seconds
Started Jun 10 05:26:28 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205196 kb
Host smart-02a0b57a-e0dc-4b04-932b-3ea0daea9954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11291
35890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.1129135890
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3526731938
Short name T922
Test name
Test status
Simulation time 167520564 ps
CPU time 1.53 seconds
Started Jun 10 05:26:24 PM PDT 24
Finished Jun 10 05:26:26 PM PDT 24
Peak memory 205124 kb
Host smart-e98e4c8a-cbd0-4bf0-9af4-3efdf5212961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35267
31938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3526731938
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.2294959441
Short name T1801
Test name
Test status
Simulation time 215344166 ps
CPU time 0.85 seconds
Started Jun 10 05:26:22 PM PDT 24
Finished Jun 10 05:26:23 PM PDT 24
Peak memory 204980 kb
Host smart-061a6b6e-6587-4dd8-a9fc-b896933d24b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22949
59441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2294959441
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2182752767
Short name T1273
Test name
Test status
Simulation time 142124111 ps
CPU time 0.83 seconds
Started Jun 10 05:26:34 PM PDT 24
Finished Jun 10 05:26:36 PM PDT 24
Peak memory 205000 kb
Host smart-0c0bd9c1-d8f2-4f1a-8b62-5a75c92e4c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21827
52767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2182752767
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3515477009
Short name T1530
Test name
Test status
Simulation time 266278898 ps
CPU time 0.9 seconds
Started Jun 10 05:26:16 PM PDT 24
Finished Jun 10 05:26:17 PM PDT 24
Peak memory 205048 kb
Host smart-cf931418-6dc3-473d-96ef-e2e23e2297cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35154
77009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3515477009
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.3118438032
Short name T615
Test name
Test status
Simulation time 174249170 ps
CPU time 0.8 seconds
Started Jun 10 05:26:29 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205024 kb
Host smart-106ed6fa-7f0a-4bb3-af32-c1e5b89a25b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31184
38032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.3118438032
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3113855215
Short name T342
Test name
Test status
Simulation time 3300896745 ps
CPU time 4.04 seconds
Started Jun 10 05:26:21 PM PDT 24
Finished Jun 10 05:26:26 PM PDT 24
Peak memory 205148 kb
Host smart-12d5b1d6-cbad-420d-9263-fec620bfa021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31138
55215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3113855215
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.582185677
Short name T1241
Test name
Test status
Simulation time 198351056 ps
CPU time 0.88 seconds
Started Jun 10 05:26:17 PM PDT 24
Finished Jun 10 05:26:18 PM PDT 24
Peak memory 204996 kb
Host smart-9703b179-6bbb-4797-993a-2f814e16aab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58218
5677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.582185677
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.1516309171
Short name T344
Test name
Test status
Simulation time 9026673684 ps
CPU time 83.88 seconds
Started Jun 10 05:26:23 PM PDT 24
Finished Jun 10 05:27:48 PM PDT 24
Peak memory 205192 kb
Host smart-518e12c4-32f4-4489-b0c3-01d3401e68fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15163
09171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.1516309171
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3961653730
Short name T955
Test name
Test status
Simulation time 146197955 ps
CPU time 0.77 seconds
Started Jun 10 05:26:24 PM PDT 24
Finished Jun 10 05:26:25 PM PDT 24
Peak memory 204984 kb
Host smart-85ec2bc0-bada-41d6-8868-72629d6f7575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39616
53730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3961653730
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.4133942561
Short name T1696
Test name
Test status
Simulation time 228496109 ps
CPU time 0.89 seconds
Started Jun 10 05:26:28 PM PDT 24
Finished Jun 10 05:26:30 PM PDT 24
Peak memory 205032 kb
Host smart-696f485f-e7a8-422a-97d3-e674907144c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41339
42561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.4133942561
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.1169410025
Short name T604
Test name
Test status
Simulation time 210895218 ps
CPU time 0.88 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:26:26 PM PDT 24
Peak memory 204988 kb
Host smart-cb32b7f6-b2f2-499e-9fdd-6d97caa2ab87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11694
10025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.1169410025
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1059163647
Short name T758
Test name
Test status
Simulation time 164884484 ps
CPU time 0.9 seconds
Started Jun 10 05:26:20 PM PDT 24
Finished Jun 10 05:26:21 PM PDT 24
Peak memory 205036 kb
Host smart-9b7b0ec9-8aec-478a-97bb-cbe9236fde0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10591
63647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1059163647
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1436242260
Short name T768
Test name
Test status
Simulation time 171307300 ps
CPU time 0.81 seconds
Started Jun 10 05:26:26 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 205040 kb
Host smart-851b81e6-af10-4725-bc67-03ca56050b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14362
42260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1436242260
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.3002360436
Short name T1391
Test name
Test status
Simulation time 154192316 ps
CPU time 0.79 seconds
Started Jun 10 05:26:22 PM PDT 24
Finished Jun 10 05:26:23 PM PDT 24
Peak memory 205004 kb
Host smart-35f5b7fa-19d5-4e0a-a2e0-f167d1d04c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30023
60436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.3002360436
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_eop_single_bit_handling.4046926126
Short name T572
Test name
Test status
Simulation time 180174297 ps
CPU time 0.82 seconds
Started Jun 10 05:26:23 PM PDT 24
Finished Jun 10 05:26:24 PM PDT 24
Peak memory 204948 kb
Host smart-2ef6c065-261e-445c-8e4a-bbcfb52b72ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40469
26126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_eop_single_bit_handling.4046926126
Directory /workspace/23.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3905175198
Short name T522
Test name
Test status
Simulation time 192335464 ps
CPU time 0.86 seconds
Started Jun 10 05:26:26 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 205012 kb
Host smart-925d2f7e-602e-42b9-a623-eee9bda334dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39051
75198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3905175198
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1024928395
Short name T1271
Test name
Test status
Simulation time 39562335 ps
CPU time 0.66 seconds
Started Jun 10 05:26:24 PM PDT 24
Finished Jun 10 05:26:25 PM PDT 24
Peak memory 205084 kb
Host smart-c148b2b2-9a4a-43be-ae93-fba7e6fa4ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10249
28395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1024928395
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.1502582487
Short name T1521
Test name
Test status
Simulation time 14154407261 ps
CPU time 34.26 seconds
Started Jun 10 05:26:20 PM PDT 24
Finished Jun 10 05:26:54 PM PDT 24
Peak memory 205284 kb
Host smart-ea4e6f7f-6669-4349-bdf6-338eeb84f11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15025
82487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.1502582487
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1904422101
Short name T580
Test name
Test status
Simulation time 159391772 ps
CPU time 0.8 seconds
Started Jun 10 05:26:31 PM PDT 24
Finished Jun 10 05:26:33 PM PDT 24
Peak memory 205004 kb
Host smart-4a38100e-e6ff-4375-b1e2-152e8691a678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19044
22101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1904422101
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.945998282
Short name T1503
Test name
Test status
Simulation time 231103887 ps
CPU time 0.91 seconds
Started Jun 10 05:26:21 PM PDT 24
Finished Jun 10 05:26:23 PM PDT 24
Peak memory 205080 kb
Host smart-0110cb52-6160-470f-b471-54c28d153a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94599
8282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.945998282
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.518950015
Short name T1133
Test name
Test status
Simulation time 151029392 ps
CPU time 0.82 seconds
Started Jun 10 05:26:30 PM PDT 24
Finished Jun 10 05:26:32 PM PDT 24
Peak memory 205016 kb
Host smart-9985337c-54de-4d92-addf-c18f70bdb064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51895
0015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.518950015
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2287412510
Short name T990
Test name
Test status
Simulation time 143483085 ps
CPU time 0.75 seconds
Started Jun 10 05:26:30 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205048 kb
Host smart-321dc1fa-7448-447d-bf6e-3119ac9d7f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22874
12510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2287412510
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.406193155
Short name T323
Test name
Test status
Simulation time 224214436 ps
CPU time 0.84 seconds
Started Jun 10 05:26:24 PM PDT 24
Finished Jun 10 05:26:25 PM PDT 24
Peak memory 204960 kb
Host smart-1b088007-1cdc-40ec-aa28-f9faa9c19a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40619
3155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.406193155
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3475638008
Short name T857
Test name
Test status
Simulation time 235729471 ps
CPU time 1.02 seconds
Started Jun 10 05:26:20 PM PDT 24
Finished Jun 10 05:26:22 PM PDT 24
Peak memory 205012 kb
Host smart-04a03b6a-a484-43aa-85ba-6eb8ee182f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34756
38008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3475638008
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.820997454
Short name T535
Test name
Test status
Simulation time 189797018 ps
CPU time 0.85 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 204988 kb
Host smart-412500d1-5142-420b-b788-e123b6b5239d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82099
7454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.820997454
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.28207518
Short name T1091
Test name
Test status
Simulation time 219260714 ps
CPU time 0.82 seconds
Started Jun 10 05:26:24 PM PDT 24
Finished Jun 10 05:26:25 PM PDT 24
Peak memory 204988 kb
Host smart-97a30436-5adb-4bef-9890-c440ee83cc2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28207
518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.28207518
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.1893159888
Short name T733
Test name
Test status
Simulation time 13169910238 ps
CPU time 363.07 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:32:32 PM PDT 24
Peak memory 205204 kb
Host smart-58d764db-c4ed-40f0-b16b-35f1d6989cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18931
59888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.1893159888
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.1598015486
Short name T1697
Test name
Test status
Simulation time 243294072 ps
CPU time 0.9 seconds
Started Jun 10 05:26:28 PM PDT 24
Finished Jun 10 05:26:30 PM PDT 24
Peak memory 205064 kb
Host smart-a660a26b-6d0d-4b4a-983e-b43e82b2de31
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1598015486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.1598015486
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.264077348
Short name T1989
Test name
Test status
Simulation time 171506153 ps
CPU time 0.81 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:29 PM PDT 24
Peak memory 204892 kb
Host smart-5602b302-f348-4655-acd1-2f63f3d5b662
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=264077348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.264077348
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.3116907152
Short name T349
Test name
Test status
Simulation time 209186103 ps
CPU time 0.84 seconds
Started Jun 10 05:26:34 PM PDT 24
Finished Jun 10 05:26:40 PM PDT 24
Peak memory 205032 kb
Host smart-19bc9535-b016-4488-b69b-b2c5afe1baf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31169
07152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.3116907152
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.2753014732
Short name T492
Test name
Test status
Simulation time 3721255199 ps
CPU time 4.61 seconds
Started Jun 10 05:26:28 PM PDT 24
Finished Jun 10 05:26:34 PM PDT 24
Peak memory 205084 kb
Host smart-c65812c3-34b2-48bb-801c-047a0009bc36
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2753014732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.2753014732
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.3873475943
Short name T2072
Test name
Test status
Simulation time 13299107740 ps
CPU time 14.37 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:42 PM PDT 24
Peak memory 205064 kb
Host smart-1f8d3514-4c48-412f-b1d0-297a1d0305f6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3873475943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.3873475943
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1485603217
Short name T431
Test name
Test status
Simulation time 23349894607 ps
CPU time 24.83 seconds
Started Jun 10 05:26:23 PM PDT 24
Finished Jun 10 05:26:48 PM PDT 24
Peak memory 205172 kb
Host smart-019b50a2-025c-4366-8404-e98bc45df0d0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1485603217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.1485603217
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2882896398
Short name T1733
Test name
Test status
Simulation time 159871703 ps
CPU time 0.79 seconds
Started Jun 10 05:26:31 PM PDT 24
Finished Jun 10 05:26:32 PM PDT 24
Peak memory 205000 kb
Host smart-dac2d046-c472-4e29-ab93-0241f3ce1fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28828
96398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2882896398
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.1154601254
Short name T1655
Test name
Test status
Simulation time 158061231 ps
CPU time 0.8 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 205060 kb
Host smart-f5c4f934-8a4c-46b2-a399-eb5932380d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11546
01254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.1154601254
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.2895071734
Short name T1813
Test name
Test status
Simulation time 612741731 ps
CPU time 1.51 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:26:27 PM PDT 24
Peak memory 204996 kb
Host smart-8d67d430-f79c-441f-bca4-85914658bb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28950
71734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.2895071734
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.159670440
Short name T1152
Test name
Test status
Simulation time 142607907 ps
CPU time 0.75 seconds
Started Jun 10 05:26:28 PM PDT 24
Finished Jun 10 05:26:30 PM PDT 24
Peak memory 204932 kb
Host smart-192671d0-9a54-430f-94c4-fe42cac262e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15967
0440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.159670440
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.2061526111
Short name T1707
Test name
Test status
Simulation time 52139593 ps
CPU time 0.69 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:29 PM PDT 24
Peak memory 205036 kb
Host smart-7254ee28-3820-49d9-b090-b449ba844114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20615
26111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2061526111
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.593103682
Short name T1153
Test name
Test status
Simulation time 795587139 ps
CPU time 2.1 seconds
Started Jun 10 05:26:30 PM PDT 24
Finished Jun 10 05:26:33 PM PDT 24
Peak memory 205148 kb
Host smart-24e29792-fd62-40f1-9870-ac3c67d6bc47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59310
3682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.593103682
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3019493535
Short name T1097
Test name
Test status
Simulation time 273448609 ps
CPU time 1.76 seconds
Started Jun 10 05:26:39 PM PDT 24
Finished Jun 10 05:26:41 PM PDT 24
Peak memory 205120 kb
Host smart-57922a98-bc0c-4a35-85de-33cea7efcf4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30194
93535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3019493535
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1119964950
Short name T938
Test name
Test status
Simulation time 224079629 ps
CPU time 0.87 seconds
Started Jun 10 05:26:34 PM PDT 24
Finished Jun 10 05:26:35 PM PDT 24
Peak memory 205056 kb
Host smart-d3234aaa-dd81-4326-961f-13d00274d6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11199
64950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1119964950
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2528447654
Short name T1887
Test name
Test status
Simulation time 142308841 ps
CPU time 0.75 seconds
Started Jun 10 05:26:33 PM PDT 24
Finished Jun 10 05:26:35 PM PDT 24
Peak memory 205020 kb
Host smart-cd24e596-dd0b-4279-9074-7dae8e15c78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25284
47654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2528447654
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3442585222
Short name T1382
Test name
Test status
Simulation time 190096860 ps
CPU time 0.84 seconds
Started Jun 10 05:26:27 PM PDT 24
Finished Jun 10 05:26:30 PM PDT 24
Peak memory 204996 kb
Host smart-1298246f-a91b-4109-97a8-94b25fd99760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34425
85222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3442585222
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.1907804736
Short name T2011
Test name
Test status
Simulation time 194632760 ps
CPU time 0.81 seconds
Started Jun 10 05:26:34 PM PDT 24
Finished Jun 10 05:26:35 PM PDT 24
Peak memory 205020 kb
Host smart-6f5ac45f-9b8c-48fc-8167-0f71855c4f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19078
04736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.1907804736
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2103952094
Short name T2105
Test name
Test status
Simulation time 3288731879 ps
CPU time 3.62 seconds
Started Jun 10 05:26:39 PM PDT 24
Finished Jun 10 05:26:43 PM PDT 24
Peak memory 205080 kb
Host smart-02e36aa5-7615-4894-8b34-a399b8017993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21039
52094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2103952094
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.344315273
Short name T1424
Test name
Test status
Simulation time 209377346 ps
CPU time 0.84 seconds
Started Jun 10 05:26:28 PM PDT 24
Finished Jun 10 05:26:30 PM PDT 24
Peak memory 205016 kb
Host smart-4515d945-6b65-4815-950d-a8157586fc80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34431
5273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.344315273
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.3520611583
Short name T971
Test name
Test status
Simulation time 9332981956 ps
CPU time 264.7 seconds
Started Jun 10 05:26:35 PM PDT 24
Finished Jun 10 05:31:00 PM PDT 24
Peak memory 205212 kb
Host smart-91951d41-0442-4ade-bdc0-1f717796790c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35206
11583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.3520611583
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3902818844
Short name T1287
Test name
Test status
Simulation time 146487539 ps
CPU time 0.78 seconds
Started Jun 10 05:26:37 PM PDT 24
Finished Jun 10 05:26:38 PM PDT 24
Peak memory 205012 kb
Host smart-c47de340-69f5-4776-9eb3-e334cb48ac7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39028
18844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3902818844
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2523307207
Short name T141
Test name
Test status
Simulation time 227315267 ps
CPU time 0.92 seconds
Started Jun 10 05:26:34 PM PDT 24
Finished Jun 10 05:26:36 PM PDT 24
Peak memory 205060 kb
Host smart-165b8001-8cd6-4d7d-afe0-2ece351d088f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25233
07207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2523307207
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.1883540976
Short name T1998
Test name
Test status
Simulation time 172809483 ps
CPU time 0.81 seconds
Started Jun 10 05:26:33 PM PDT 24
Finished Jun 10 05:26:34 PM PDT 24
Peak memory 205076 kb
Host smart-ad7daf6d-a0f6-45f3-9c73-c205fa0259a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18835
40976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.1883540976
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2335501367
Short name T723
Test name
Test status
Simulation time 145056547 ps
CPU time 0.79 seconds
Started Jun 10 05:26:26 PM PDT 24
Finished Jun 10 05:26:28 PM PDT 24
Peak memory 204976 kb
Host smart-b7630d17-edee-49b8-ab5b-9b2b3b7e288f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23355
01367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2335501367
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2367277719
Short name T574
Test name
Test status
Simulation time 184470726 ps
CPU time 0.81 seconds
Started Jun 10 05:26:33 PM PDT 24
Finished Jun 10 05:26:35 PM PDT 24
Peak memory 205060 kb
Host smart-7f6e03cc-d42e-4664-8b89-24b76f6a7267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23672
77719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2367277719
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3879272742
Short name T1406
Test name
Test status
Simulation time 162836625 ps
CPU time 0.82 seconds
Started Jun 10 05:26:29 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205000 kb
Host smart-839c3461-6d71-4e7e-aae0-1badc4bef431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38792
72742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3879272742
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_eop_single_bit_handling.3220721158
Short name T834
Test name
Test status
Simulation time 159659579 ps
CPU time 0.83 seconds
Started Jun 10 05:26:33 PM PDT 24
Finished Jun 10 05:26:34 PM PDT 24
Peak memory 205052 kb
Host smart-e1045dd3-9ee7-4faa-91c0-a499972e01c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32207
21158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_eop_single_bit_handling.3220721158
Directory /workspace/24.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2662173026
Short name T2095
Test name
Test status
Simulation time 146492994 ps
CPU time 0.77 seconds
Started Jun 10 05:26:32 PM PDT 24
Finished Jun 10 05:26:34 PM PDT 24
Peak memory 205040 kb
Host smart-c24684e0-e290-4ef6-a89b-acb7d7a3a466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26621
73026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2662173026
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.153597240
Short name T1378
Test name
Test status
Simulation time 53633061 ps
CPU time 0.71 seconds
Started Jun 10 05:26:30 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205008 kb
Host smart-3ff48be7-0290-4e46-abae-5c36f2e6408d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15359
7240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.153597240
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3100901757
Short name T268
Test name
Test status
Simulation time 19075436887 ps
CPU time 44.59 seconds
Started Jun 10 05:26:33 PM PDT 24
Finished Jun 10 05:27:18 PM PDT 24
Peak memory 205256 kb
Host smart-535e4851-b8c4-49fa-afe9-dcf9de1a3d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31009
01757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3100901757
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1660440991
Short name T282
Test name
Test status
Simulation time 206584768 ps
CPU time 0.86 seconds
Started Jun 10 05:26:30 PM PDT 24
Finished Jun 10 05:26:32 PM PDT 24
Peak memory 204960 kb
Host smart-ed7771e9-8c59-408c-be24-7a96ccffc49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16604
40991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1660440991
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3697097632
Short name T1512
Test name
Test status
Simulation time 257143391 ps
CPU time 0.94 seconds
Started Jun 10 05:26:30 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205040 kb
Host smart-88b95c1c-deb0-4d50-bf46-55e2045e7348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36970
97632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3697097632
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.2770300114
Short name T1260
Test name
Test status
Simulation time 211995528 ps
CPU time 0.91 seconds
Started Jun 10 05:26:33 PM PDT 24
Finished Jun 10 05:26:35 PM PDT 24
Peak memory 205024 kb
Host smart-13c3fdfc-9ede-4e30-85ba-cbbe3d3757df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27703
00114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.2770300114
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.464029486
Short name T1112
Test name
Test status
Simulation time 130894537 ps
CPU time 0.78 seconds
Started Jun 10 05:26:34 PM PDT 24
Finished Jun 10 05:26:35 PM PDT 24
Peak memory 205024 kb
Host smart-78ef6d0f-1feb-4bf6-92fb-9f6a9b90fc98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46402
9486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.464029486
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.691773950
Short name T173
Test name
Test status
Simulation time 167361135 ps
CPU time 0.84 seconds
Started Jun 10 05:26:29 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 205060 kb
Host smart-0941744c-b274-4e6b-9bca-c56eb66bd8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69177
3950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.691773950
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3397770708
Short name T759
Test name
Test status
Simulation time 159677093 ps
CPU time 0.81 seconds
Started Jun 10 05:26:31 PM PDT 24
Finished Jun 10 05:26:33 PM PDT 24
Peak memory 205008 kb
Host smart-a1ac68b6-ffb4-4003-b041-48ffdb6b79cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33977
70708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3397770708
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3715840401
Short name T171
Test name
Test status
Simulation time 290324744 ps
CPU time 1 seconds
Started Jun 10 05:26:25 PM PDT 24
Finished Jun 10 05:26:27 PM PDT 24
Peak memory 205020 kb
Host smart-05425031-64bd-4872-8d08-495554238cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37158
40401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3715840401
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.580098567
Short name T707
Test name
Test status
Simulation time 184705832 ps
CPU time 0.86 seconds
Started Jun 10 05:26:34 PM PDT 24
Finished Jun 10 05:26:35 PM PDT 24
Peak memory 205036 kb
Host smart-b93b9c2f-0eca-4aae-a7c5-833bb12f480d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58009
8567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.580098567
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1705636229
Short name T1914
Test name
Test status
Simulation time 214573101 ps
CPU time 0.83 seconds
Started Jun 10 05:26:38 PM PDT 24
Finished Jun 10 05:26:39 PM PDT 24
Peak memory 205012 kb
Host smart-b93abe5c-77d8-4a91-aedc-d486c0e16d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17056
36229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1705636229
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.3076526794
Short name T1812
Test name
Test status
Simulation time 7659915673 ps
CPU time 71.51 seconds
Started Jun 10 05:26:33 PM PDT 24
Finished Jun 10 05:27:45 PM PDT 24
Peak memory 205240 kb
Host smart-91c4cbdd-9206-4849-abc6-f69cb429bbd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30765
26794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.3076526794
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.449379077
Short name T2107
Test name
Test status
Simulation time 253641282 ps
CPU time 0.99 seconds
Started Jun 10 05:26:38 PM PDT 24
Finished Jun 10 05:26:39 PM PDT 24
Peak memory 205012 kb
Host smart-fbf7fc04-b6fa-4c17-bba7-29beeda70423
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=449379077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.449379077
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.868908224
Short name T2044
Test name
Test status
Simulation time 152101758 ps
CPU time 0.83 seconds
Started Jun 10 05:26:32 PM PDT 24
Finished Jun 10 05:26:34 PM PDT 24
Peak memory 204992 kb
Host smart-3616634c-fce7-4ca1-94fa-5914f887faec
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=868908224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.868908224
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.1220397555
Short name T1894
Test name
Test status
Simulation time 304812459 ps
CPU time 0.95 seconds
Started Jun 10 05:26:34 PM PDT 24
Finished Jun 10 05:26:36 PM PDT 24
Peak memory 205024 kb
Host smart-3d73ee1b-a7e9-4205-95d5-ddbf690500e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12203
97555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.1220397555
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.836646577
Short name T1207
Test name
Test status
Simulation time 3890572941 ps
CPU time 4.62 seconds
Started Jun 10 05:26:31 PM PDT 24
Finished Jun 10 05:26:36 PM PDT 24
Peak memory 205044 kb
Host smart-53b53c20-80c8-481f-badd-74d5a1be5b96
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=836646577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.836646577
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3618264852
Short name T1415
Test name
Test status
Simulation time 13351018906 ps
CPU time 12.92 seconds
Started Jun 10 05:26:43 PM PDT 24
Finished Jun 10 05:27:02 PM PDT 24
Peak memory 205204 kb
Host smart-8c79203e-7bd3-4a14-937a-d503fe087c0b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3618264852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3618264852
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.3512023298
Short name T2002
Test name
Test status
Simulation time 23464643976 ps
CPU time 23.98 seconds
Started Jun 10 05:26:41 PM PDT 24
Finished Jun 10 05:27:06 PM PDT 24
Peak memory 205152 kb
Host smart-aba5933e-70a5-4a0e-b6d3-4b2e007f5f2b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3512023298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.3512023298
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3035015426
Short name T2083
Test name
Test status
Simulation time 212498371 ps
CPU time 0.84 seconds
Started Jun 10 05:26:42 PM PDT 24
Finished Jun 10 05:26:43 PM PDT 24
Peak memory 205032 kb
Host smart-5d62287c-b043-4a3a-a2c4-dc75a3e2828d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30350
15426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3035015426
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2768486138
Short name T668
Test name
Test status
Simulation time 205049994 ps
CPU time 0.84 seconds
Started Jun 10 05:26:32 PM PDT 24
Finished Jun 10 05:26:34 PM PDT 24
Peak memory 204976 kb
Host smart-6a85d822-6f66-4b9e-9ab9-ddd918251553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27684
86138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2768486138
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2264628685
Short name T1678
Test name
Test status
Simulation time 730630535 ps
CPU time 1.83 seconds
Started Jun 10 05:26:41 PM PDT 24
Finished Jun 10 05:26:43 PM PDT 24
Peak memory 205164 kb
Host smart-ab696101-88de-4617-84bc-3a63d2fb44b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22646
28685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2264628685
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.757789346
Short name T1069
Test name
Test status
Simulation time 144189089 ps
CPU time 0.76 seconds
Started Jun 10 05:26:40 PM PDT 24
Finished Jun 10 05:26:41 PM PDT 24
Peak memory 205056 kb
Host smart-455ddd18-fd77-46ef-a711-4a257ad61be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75778
9346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.757789346
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.31349611
Short name T1508
Test name
Test status
Simulation time 46073942 ps
CPU time 0.67 seconds
Started Jun 10 05:26:41 PM PDT 24
Finished Jun 10 05:26:42 PM PDT 24
Peak memory 204988 kb
Host smart-a6db6ded-01d6-4703-a697-2bc9ac963113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31349
611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.31349611
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.283340812
Short name T785
Test name
Test status
Simulation time 906343886 ps
CPU time 2.37 seconds
Started Jun 10 05:26:43 PM PDT 24
Finished Jun 10 05:26:46 PM PDT 24
Peak memory 205104 kb
Host smart-11bd3e70-ca1c-48db-86f8-f25ee1c5e2bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28334
0812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.283340812
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1394352085
Short name T480
Test name
Test status
Simulation time 248858977 ps
CPU time 1.49 seconds
Started Jun 10 05:26:30 PM PDT 24
Finished Jun 10 05:26:32 PM PDT 24
Peak memory 205188 kb
Host smart-7e62defd-ec2c-4e88-b2f5-d632e39d7147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13943
52085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1394352085
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3722050168
Short name T1535
Test name
Test status
Simulation time 253981146 ps
CPU time 0.92 seconds
Started Jun 10 05:26:31 PM PDT 24
Finished Jun 10 05:26:33 PM PDT 24
Peak memory 205012 kb
Host smart-d55b7a62-fd42-4822-8cf0-936adde79b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37220
50168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3722050168
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.3301846893
Short name T1362
Test name
Test status
Simulation time 152067340 ps
CPU time 0.75 seconds
Started Jun 10 05:26:33 PM PDT 24
Finished Jun 10 05:26:35 PM PDT 24
Peak memory 204968 kb
Host smart-736124ce-c782-410b-9823-899d81a79c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33018
46893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.3301846893
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2403573712
Short name T644
Test name
Test status
Simulation time 217852147 ps
CPU time 0.98 seconds
Started Jun 10 05:26:32 PM PDT 24
Finished Jun 10 05:26:34 PM PDT 24
Peak memory 204972 kb
Host smart-46e5fb6f-2e04-4780-9534-3e2021873d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24035
73712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2403573712
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.665848988
Short name T51
Test name
Test status
Simulation time 168932736 ps
CPU time 0.84 seconds
Started Jun 10 05:26:44 PM PDT 24
Finished Jun 10 05:26:45 PM PDT 24
Peak memory 204992 kb
Host smart-24f4de61-6376-4b05-b92f-8131d0b0b739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66584
8988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.665848988
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1256400652
Short name T1192
Test name
Test status
Simulation time 3315883898 ps
CPU time 3.87 seconds
Started Jun 10 05:26:32 PM PDT 24
Finished Jun 10 05:26:37 PM PDT 24
Peak memory 205056 kb
Host smart-a9d68690-6ec1-4516-a107-d0873d5280fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12564
00652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1256400652
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3340710613
Short name T1186
Test name
Test status
Simulation time 212019464 ps
CPU time 0.93 seconds
Started Jun 10 05:26:37 PM PDT 24
Finished Jun 10 05:26:38 PM PDT 24
Peak memory 205060 kb
Host smart-446ea6e8-419d-48a1-9fdc-2474be735d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33407
10613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3340710613
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2650590507
Short name T1492
Test name
Test status
Simulation time 5710506900 ps
CPU time 55.58 seconds
Started Jun 10 05:26:34 PM PDT 24
Finished Jun 10 05:27:30 PM PDT 24
Peak memory 205188 kb
Host smart-ef173df0-8ca2-4965-8134-dc43efe0e310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26505
90507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2650590507
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3509058347
Short name T1400
Test name
Test status
Simulation time 148287088 ps
CPU time 0.77 seconds
Started Jun 10 05:26:31 PM PDT 24
Finished Jun 10 05:26:33 PM PDT 24
Peak memory 204996 kb
Host smart-6d51668c-62f3-4237-89a3-07b079bd5f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35090
58347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3509058347
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.4140940554
Short name T1184
Test name
Test status
Simulation time 175768318 ps
CPU time 0.85 seconds
Started Jun 10 05:26:42 PM PDT 24
Finished Jun 10 05:26:44 PM PDT 24
Peak memory 204984 kb
Host smart-84ba925a-72d4-4449-9cca-b1c950c6fa29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41409
40554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.4140940554
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.73881099
Short name T1468
Test name
Test status
Simulation time 154580912 ps
CPU time 0.78 seconds
Started Jun 10 05:26:41 PM PDT 24
Finished Jun 10 05:26:42 PM PDT 24
Peak memory 205016 kb
Host smart-950d6f71-2bd8-4a67-ac4b-96a66f0c2e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73881
099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.73881099
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.4243871847
Short name T1570
Test name
Test status
Simulation time 162759964 ps
CPU time 0.8 seconds
Started Jun 10 05:26:38 PM PDT 24
Finished Jun 10 05:26:40 PM PDT 24
Peak memory 205004 kb
Host smart-947c66e3-a5f0-4f75-9990-a3b862e0254e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42438
71847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.4243871847
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2446269891
Short name T1038
Test name
Test status
Simulation time 155884836 ps
CPU time 0.83 seconds
Started Jun 10 05:26:32 PM PDT 24
Finished Jun 10 05:26:33 PM PDT 24
Peak memory 204916 kb
Host smart-a12fbef6-1654-4240-a33b-bfb9333646c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24462
69891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2446269891
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_eop_single_bit_handling.579270738
Short name T1477
Test name
Test status
Simulation time 225673655 ps
CPU time 0.93 seconds
Started Jun 10 05:26:32 PM PDT 24
Finished Jun 10 05:26:34 PM PDT 24
Peak memory 204904 kb
Host smart-0b0bd539-025e-45e5-8f00-7d1effba93c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57927
0738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_eop_single_bit_handling.579270738
Directory /workspace/25.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.485503661
Short name T952
Test name
Test status
Simulation time 144337711 ps
CPU time 0.74 seconds
Started Jun 10 05:26:39 PM PDT 24
Finished Jun 10 05:26:40 PM PDT 24
Peak memory 205028 kb
Host smart-9b8bc678-6d14-4908-9006-c4970f3635a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48550
3661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.485503661
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.112624459
Short name T997
Test name
Test status
Simulation time 69607022 ps
CPU time 0.68 seconds
Started Jun 10 05:26:47 PM PDT 24
Finished Jun 10 05:26:48 PM PDT 24
Peak memory 204996 kb
Host smart-95831daa-1299-42b0-bbcc-4c821068f13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11262
4459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.112624459
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3916107943
Short name T1974
Test name
Test status
Simulation time 10287808472 ps
CPU time 22.8 seconds
Started Jun 10 05:26:38 PM PDT 24
Finished Jun 10 05:27:01 PM PDT 24
Peak memory 205172 kb
Host smart-dfc7bef3-b364-41d6-aefb-10f7c27c847e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39161
07943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3916107943
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.3707776676
Short name T1148
Test name
Test status
Simulation time 190864393 ps
CPU time 0.87 seconds
Started Jun 10 05:27:07 PM PDT 24
Finished Jun 10 05:27:09 PM PDT 24
Peak memory 205008 kb
Host smart-070b2b31-2874-43a9-9fa9-9d0c92381d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37077
76676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.3707776676
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.866058731
Short name T428
Test name
Test status
Simulation time 169360582 ps
CPU time 0.87 seconds
Started Jun 10 05:26:33 PM PDT 24
Finished Jun 10 05:26:35 PM PDT 24
Peak memory 204992 kb
Host smart-581a1d9c-7532-43ce-9ef2-ef4c9655f46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86605
8731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.866058731
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.1516371994
Short name T517
Test name
Test status
Simulation time 191379150 ps
CPU time 0.94 seconds
Started Jun 10 05:27:06 PM PDT 24
Finished Jun 10 05:27:07 PM PDT 24
Peak memory 204904 kb
Host smart-7f834830-6d2d-411a-95a0-b9ac39a72909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15163
71994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.1516371994
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.2667707412
Short name T533
Test name
Test status
Simulation time 138435025 ps
CPU time 0.75 seconds
Started Jun 10 05:26:37 PM PDT 24
Finished Jun 10 05:26:38 PM PDT 24
Peak memory 204848 kb
Host smart-9875b8f3-2c88-4692-a34a-ab2ea261fa9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26677
07412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.2667707412
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.609607806
Short name T190
Test name
Test status
Simulation time 157052550 ps
CPU time 0.76 seconds
Started Jun 10 05:26:42 PM PDT 24
Finished Jun 10 05:26:44 PM PDT 24
Peak memory 205000 kb
Host smart-d8c6c37f-5e74-479d-8f43-44082de995ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60960
7806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.609607806
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1001364980
Short name T1783
Test name
Test status
Simulation time 150633600 ps
CPU time 0.83 seconds
Started Jun 10 05:26:31 PM PDT 24
Finished Jun 10 05:26:32 PM PDT 24
Peak memory 205024 kb
Host smart-23fcc2a1-b217-4317-8e3e-5f7c90f9b921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10013
64980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1001364980
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2136721027
Short name T178
Test name
Test status
Simulation time 257913289 ps
CPU time 1 seconds
Started Jun 10 05:26:33 PM PDT 24
Finished Jun 10 05:26:34 PM PDT 24
Peak memory 205040 kb
Host smart-21bf6d4f-ae47-415d-9b75-0d73f06361e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21367
21027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2136721027
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.228254793
Short name T599
Test name
Test status
Simulation time 203129607 ps
CPU time 0.83 seconds
Started Jun 10 05:26:40 PM PDT 24
Finished Jun 10 05:26:41 PM PDT 24
Peak memory 205008 kb
Host smart-dd8b8310-df1e-4452-acc6-3b5be96dd5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22825
4793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.228254793
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1321436562
Short name T684
Test name
Test status
Simulation time 202682452 ps
CPU time 0.82 seconds
Started Jun 10 05:26:30 PM PDT 24
Finished Jun 10 05:26:31 PM PDT 24
Peak memory 204928 kb
Host smart-a5466a8a-7571-4897-9473-84008d501853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13214
36562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1321436562
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.4042499045
Short name T366
Test name
Test status
Simulation time 4995883614 ps
CPU time 45.69 seconds
Started Jun 10 05:26:45 PM PDT 24
Finished Jun 10 05:27:31 PM PDT 24
Peak memory 205180 kb
Host smart-75685c44-1086-47c6-a762-d131d0b7ca13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40424
99045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.4042499045
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.1000702693
Short name T34
Test name
Test status
Simulation time 240254295 ps
CPU time 1.04 seconds
Started Jun 10 05:26:44 PM PDT 24
Finished Jun 10 05:26:46 PM PDT 24
Peak memory 205020 kb
Host smart-25eaa73c-9c2b-4e1a-9dbf-8b94db034dfa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1000702693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.1000702693
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.3643473145
Short name T1377
Test name
Test status
Simulation time 154711400 ps
CPU time 0.77 seconds
Started Jun 10 05:26:56 PM PDT 24
Finished Jun 10 05:26:57 PM PDT 24
Peak memory 204956 kb
Host smart-102d797d-e63f-427d-a34a-50228dfdd5de
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3643473145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.3643473145
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.504382112
Short name T1389
Test name
Test status
Simulation time 201746485 ps
CPU time 0.84 seconds
Started Jun 10 05:26:46 PM PDT 24
Finished Jun 10 05:26:47 PM PDT 24
Peak memory 204992 kb
Host smart-eba66ddb-6539-4911-89c0-6a69908de4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50438
2112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.504382112
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2024440767
Short name T1569
Test name
Test status
Simulation time 3471000735 ps
CPU time 4.26 seconds
Started Jun 10 05:26:43 PM PDT 24
Finished Jun 10 05:26:48 PM PDT 24
Peak memory 205092 kb
Host smart-27915f37-14cd-42a9-b4ec-7ec68d1fe9ad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2024440767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.2024440767
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.3471011328
Short name T391
Test name
Test status
Simulation time 13385552220 ps
CPU time 12.65 seconds
Started Jun 10 05:26:34 PM PDT 24
Finished Jun 10 05:26:47 PM PDT 24
Peak memory 205160 kb
Host smart-c81569dd-4c71-4844-bb73-ef9a7c7b3009
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3471011328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.3471011328
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.1219711491
Short name T596
Test name
Test status
Simulation time 23354304477 ps
CPU time 24.18 seconds
Started Jun 10 05:26:32 PM PDT 24
Finished Jun 10 05:26:57 PM PDT 24
Peak memory 205088 kb
Host smart-ee1fe4d3-8b58-40a2-83a1-7ec39e18c036
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1219711491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.1219711491
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.592824271
Short name T473
Test name
Test status
Simulation time 163468385 ps
CPU time 0.79 seconds
Started Jun 10 05:26:41 PM PDT 24
Finished Jun 10 05:26:42 PM PDT 24
Peak memory 205004 kb
Host smart-cc6081ca-f87d-49d8-a8a8-69aa821ec4a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59282
4271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.592824271
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.3801746647
Short name T270
Test name
Test status
Simulation time 186581660 ps
CPU time 0.82 seconds
Started Jun 10 05:26:41 PM PDT 24
Finished Jun 10 05:26:42 PM PDT 24
Peak memory 205004 kb
Host smart-72ff4c11-0076-4531-bb7b-aea80eb0af6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38017
46647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3801746647
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.848197076
Short name T1949
Test name
Test status
Simulation time 1307305016 ps
CPU time 3.11 seconds
Started Jun 10 05:26:34 PM PDT 24
Finished Jun 10 05:26:38 PM PDT 24
Peak memory 205200 kb
Host smart-b60e44fd-c1ce-4544-ab39-542d87e15436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84819
7076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.848197076
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.4288037751
Short name T786
Test name
Test status
Simulation time 139418624 ps
CPU time 0.78 seconds
Started Jun 10 05:26:37 PM PDT 24
Finished Jun 10 05:26:38 PM PDT 24
Peak memory 205008 kb
Host smart-c63fd43b-8425-4112-9349-0a106978499e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42880
37751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.4288037751
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.882417831
Short name T1585
Test name
Test status
Simulation time 43372537 ps
CPU time 0.63 seconds
Started Jun 10 05:26:31 PM PDT 24
Finished Jun 10 05:26:33 PM PDT 24
Peak memory 205000 kb
Host smart-7596bff9-8be8-4a91-ba8f-50c55a31beed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88241
7831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.882417831
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2420891279
Short name T640
Test name
Test status
Simulation time 697990023 ps
CPU time 1.9 seconds
Started Jun 10 05:26:46 PM PDT 24
Finished Jun 10 05:26:48 PM PDT 24
Peak memory 205104 kb
Host smart-fd21ad86-cdd0-4c16-afdb-43566640c893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24208
91279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2420891279
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.688775286
Short name T1457
Test name
Test status
Simulation time 163064837 ps
CPU time 1.52 seconds
Started Jun 10 05:26:34 PM PDT 24
Finished Jun 10 05:26:36 PM PDT 24
Peak memory 205176 kb
Host smart-ba0b42fe-7a39-48b8-87be-c7a4d759c477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68877
5286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.688775286
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3293635044
Short name T906
Test name
Test status
Simulation time 240664026 ps
CPU time 0.9 seconds
Started Jun 10 05:27:00 PM PDT 24
Finished Jun 10 05:27:01 PM PDT 24
Peak memory 205032 kb
Host smart-c2534d2d-7103-4be0-af43-980afa8c0624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32936
35044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3293635044
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2580975140
Short name T1661
Test name
Test status
Simulation time 155037568 ps
CPU time 0.76 seconds
Started Jun 10 05:26:44 PM PDT 24
Finished Jun 10 05:26:45 PM PDT 24
Peak memory 205020 kb
Host smart-de3feb9c-7df6-4647-a607-f6fa923c9759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25809
75140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2580975140
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.371415455
Short name T1981
Test name
Test status
Simulation time 221904539 ps
CPU time 0.9 seconds
Started Jun 10 05:26:32 PM PDT 24
Finished Jun 10 05:26:34 PM PDT 24
Peak memory 204976 kb
Host smart-0d838bef-adde-483a-bf09-8a1482536403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37141
5455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.371415455
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3537707137
Short name T1684
Test name
Test status
Simulation time 216397690 ps
CPU time 0.82 seconds
Started Jun 10 05:26:35 PM PDT 24
Finished Jun 10 05:26:36 PM PDT 24
Peak memory 205000 kb
Host smart-e0c9e8ef-8b9e-4258-8d11-ec805ec06731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35377
07137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3537707137
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.3415266180
Short name T1884
Test name
Test status
Simulation time 3307834314 ps
CPU time 3.72 seconds
Started Jun 10 05:26:34 PM PDT 24
Finished Jun 10 05:26:38 PM PDT 24
Peak memory 205024 kb
Host smart-856cb9bb-5e18-4784-b525-44262f3efeb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34152
66180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.3415266180
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3067590446
Short name T582
Test name
Test status
Simulation time 200439280 ps
CPU time 0.9 seconds
Started Jun 10 05:26:36 PM PDT 24
Finished Jun 10 05:26:37 PM PDT 24
Peak memory 205020 kb
Host smart-25eb7e2c-96f4-4cd1-934f-68cdc12de27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30675
90446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3067590446
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.3229369184
Short name T631
Test name
Test status
Simulation time 7664060345 ps
CPU time 75.41 seconds
Started Jun 10 05:26:53 PM PDT 24
Finished Jun 10 05:28:09 PM PDT 24
Peak memory 205104 kb
Host smart-42c9118d-5a71-428e-8831-ca8990993509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32293
69184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.3229369184
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.4288211548
Short name T125
Test name
Test status
Simulation time 201887089 ps
CPU time 0.82 seconds
Started Jun 10 05:26:38 PM PDT 24
Finished Jun 10 05:26:39 PM PDT 24
Peak memory 205028 kb
Host smart-00d39e4a-8a3b-4066-af6f-ccba585afcd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42882
11548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.4288211548
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3251784576
Short name T137
Test name
Test status
Simulation time 271022029 ps
CPU time 0.98 seconds
Started Jun 10 05:26:37 PM PDT 24
Finished Jun 10 05:26:38 PM PDT 24
Peak memory 204976 kb
Host smart-2651a115-5914-493e-8e0f-4335665821d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32517
84576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3251784576
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.3075015008
Short name T1164
Test name
Test status
Simulation time 210819963 ps
CPU time 0.87 seconds
Started Jun 10 05:26:46 PM PDT 24
Finished Jun 10 05:26:48 PM PDT 24
Peak memory 204984 kb
Host smart-51cfb656-e498-4650-af21-353a581c0949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30750
15008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3075015008
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2181033239
Short name T878
Test name
Test status
Simulation time 155296223 ps
CPU time 0.77 seconds
Started Jun 10 05:26:54 PM PDT 24
Finished Jun 10 05:26:55 PM PDT 24
Peak memory 204904 kb
Host smart-6133765e-04e0-4984-8c52-4ef2e56999c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21810
33239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2181033239
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3725410255
Short name T1675
Test name
Test status
Simulation time 175160227 ps
CPU time 0.8 seconds
Started Jun 10 05:27:05 PM PDT 24
Finished Jun 10 05:27:06 PM PDT 24
Peak memory 204932 kb
Host smart-a70dd9ee-f90f-4e27-bf61-c3d16bf3dad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37254
10255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3725410255
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2346772290
Short name T200
Test name
Test status
Simulation time 154117788 ps
CPU time 0.82 seconds
Started Jun 10 05:26:40 PM PDT 24
Finished Jun 10 05:26:41 PM PDT 24
Peak memory 205004 kb
Host smart-fde86c3a-26d0-40a8-a394-51ce76a11046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23467
72290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2346772290
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_eop_single_bit_handling.3305900526
Short name T1633
Test name
Test status
Simulation time 181823950 ps
CPU time 0.86 seconds
Started Jun 10 05:26:40 PM PDT 24
Finished Jun 10 05:26:41 PM PDT 24
Peak memory 205096 kb
Host smart-dc8dad5f-a7c3-42f4-bd40-bc000545804f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33059
00526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_eop_single_bit_handling.3305900526
Directory /workspace/26.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2452643949
Short name T966
Test name
Test status
Simulation time 195069218 ps
CPU time 0.79 seconds
Started Jun 10 05:26:36 PM PDT 24
Finished Jun 10 05:26:37 PM PDT 24
Peak memory 204992 kb
Host smart-801699b2-09d1-4c02-931a-24fcc2618607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24526
43949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2452643949
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1210737046
Short name T444
Test name
Test status
Simulation time 41928473 ps
CPU time 0.66 seconds
Started Jun 10 05:26:54 PM PDT 24
Finished Jun 10 05:26:55 PM PDT 24
Peak memory 205024 kb
Host smart-839f2123-ab2a-4056-aad8-df90bb93cf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12107
37046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1210737046
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3275531895
Short name T854
Test name
Test status
Simulation time 12458763759 ps
CPU time 29.53 seconds
Started Jun 10 05:26:42 PM PDT 24
Finished Jun 10 05:27:12 PM PDT 24
Peak memory 205240 kb
Host smart-e6eeb353-d27e-4acd-a607-95b316560191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32755
31895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3275531895
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1510390336
Short name T1479
Test name
Test status
Simulation time 144700655 ps
CPU time 0.8 seconds
Started Jun 10 05:26:38 PM PDT 24
Finished Jun 10 05:26:39 PM PDT 24
Peak memory 205012 kb
Host smart-812ff4c2-9c11-464c-a3a6-2ca3398f3b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15103
90336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1510390336
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.3477015994
Short name T1344
Test name
Test status
Simulation time 191476385 ps
CPU time 0.87 seconds
Started Jun 10 05:26:38 PM PDT 24
Finished Jun 10 05:26:39 PM PDT 24
Peak memory 205004 kb
Host smart-234b9783-8546-4b14-a427-66d5e3fc5c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34770
15994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.3477015994
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.1851823161
Short name T1849
Test name
Test status
Simulation time 179107389 ps
CPU time 0.83 seconds
Started Jun 10 05:26:35 PM PDT 24
Finished Jun 10 05:26:37 PM PDT 24
Peak memory 204988 kb
Host smart-e1c21a2d-a294-4020-9da5-de74389d4d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18518
23161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.1851823161
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1986961629
Short name T1622
Test name
Test status
Simulation time 139803680 ps
CPU time 0.77 seconds
Started Jun 10 05:26:41 PM PDT 24
Finished Jun 10 05:26:42 PM PDT 24
Peak memory 205016 kb
Host smart-23ae689f-fdba-43ae-879d-b717b0c81ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19869
61629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1986961629
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.84262960
Short name T1376
Test name
Test status
Simulation time 170567942 ps
CPU time 0.77 seconds
Started Jun 10 05:26:35 PM PDT 24
Finished Jun 10 05:26:37 PM PDT 24
Peak memory 205076 kb
Host smart-bf837a81-819a-4b18-bf8f-7a4274fe2766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84262
960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.84262960
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.4132332339
Short name T1035
Test name
Test status
Simulation time 145529842 ps
CPU time 0.8 seconds
Started Jun 10 05:26:38 PM PDT 24
Finished Jun 10 05:26:39 PM PDT 24
Peak memory 205000 kb
Host smart-fb643873-3e09-4f3a-89da-7cc662a2bf41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41323
32339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.4132332339
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.423898105
Short name T905
Test name
Test status
Simulation time 234022740 ps
CPU time 0.95 seconds
Started Jun 10 05:26:42 PM PDT 24
Finished Jun 10 05:26:44 PM PDT 24
Peak memory 204996 kb
Host smart-5fc8304e-b38b-4618-ac7d-0b408a46e0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42389
8105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.423898105
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1650942608
Short name T2090
Test name
Test status
Simulation time 207481542 ps
CPU time 0.88 seconds
Started Jun 10 05:26:41 PM PDT 24
Finished Jun 10 05:26:42 PM PDT 24
Peak memory 204988 kb
Host smart-314b8f28-8e82-4f9c-bdd0-46c433ab0a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16509
42608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1650942608
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.926037981
Short name T568
Test name
Test status
Simulation time 177326202 ps
CPU time 0.81 seconds
Started Jun 10 05:26:36 PM PDT 24
Finished Jun 10 05:26:37 PM PDT 24
Peak memory 204992 kb
Host smart-68f2c15b-cc11-4e12-85a6-9fcfeca1c393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92603
7981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.926037981
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.492884974
Short name T951
Test name
Test status
Simulation time 13145220971 ps
CPU time 386.89 seconds
Started Jun 10 05:26:41 PM PDT 24
Finished Jun 10 05:33:08 PM PDT 24
Peak memory 205184 kb
Host smart-be7369a5-b1f3-47ee-b3df-7bbd1f895b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49288
4974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.492884974
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.3810182267
Short name T560
Test name
Test status
Simulation time 237726337 ps
CPU time 0.9 seconds
Started Jun 10 05:26:50 PM PDT 24
Finished Jun 10 05:26:51 PM PDT 24
Peak memory 205020 kb
Host smart-0142f54d-9e6c-4210-aff5-d1ca96632b61
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3810182267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.3810182267
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.3595792510
Short name T1031
Test name
Test status
Simulation time 169832958 ps
CPU time 0.82 seconds
Started Jun 10 05:26:48 PM PDT 24
Finished Jun 10 05:26:49 PM PDT 24
Peak memory 204984 kb
Host smart-02257d93-6970-4096-8061-a0ac117c2b5b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3595792510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.3595792510
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.660345238
Short name T1871
Test name
Test status
Simulation time 238079641 ps
CPU time 0.94 seconds
Started Jun 10 05:26:47 PM PDT 24
Finished Jun 10 05:26:48 PM PDT 24
Peak memory 205168 kb
Host smart-6b827602-09e4-485b-9e25-e8f91b5bcc45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66034
5238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.660345238
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.2435689586
Short name T505
Test name
Test status
Simulation time 4340829640 ps
CPU time 4.75 seconds
Started Jun 10 05:26:40 PM PDT 24
Finished Jun 10 05:26:45 PM PDT 24
Peak memory 205132 kb
Host smart-68cdf030-b9d5-4176-bb04-f4fc46d09ade
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2435689586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.2435689586
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2758740752
Short name T1266
Test name
Test status
Simulation time 13345216691 ps
CPU time 15.43 seconds
Started Jun 10 05:26:57 PM PDT 24
Finished Jun 10 05:27:13 PM PDT 24
Peak memory 205092 kb
Host smart-a35eaf70-b2b5-49c3-abae-281a8e2bdf35
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2758740752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2758740752
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.977268902
Short name T996
Test name
Test status
Simulation time 23437453685 ps
CPU time 31.36 seconds
Started Jun 10 05:26:51 PM PDT 24
Finished Jun 10 05:27:23 PM PDT 24
Peak memory 205096 kb
Host smart-82e8b2dc-e165-4e9d-bec0-c2ff4ad82500
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=977268902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.977268902
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2353910824
Short name T416
Test name
Test status
Simulation time 190645428 ps
CPU time 0.81 seconds
Started Jun 10 05:26:42 PM PDT 24
Finished Jun 10 05:26:43 PM PDT 24
Peak memory 205004 kb
Host smart-57533548-f3f8-45f6-929e-217e98051b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23539
10824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2353910824
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.4236490793
Short name T1432
Test name
Test status
Simulation time 141339417 ps
CPU time 0.79 seconds
Started Jun 10 05:26:44 PM PDT 24
Finished Jun 10 05:26:45 PM PDT 24
Peak memory 204904 kb
Host smart-b63e824d-913d-469b-8bb6-2aaa3ec1650f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42364
90793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.4236490793
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.2967117229
Short name T2027
Test name
Test status
Simulation time 897523754 ps
CPU time 2.11 seconds
Started Jun 10 05:26:43 PM PDT 24
Finished Jun 10 05:26:45 PM PDT 24
Peak memory 205084 kb
Host smart-40afcc8a-3583-4a52-83f7-7446e0140f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29671
17229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.2967117229
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1940383388
Short name T1505
Test name
Test status
Simulation time 143580668 ps
CPU time 0.77 seconds
Started Jun 10 05:26:50 PM PDT 24
Finished Jun 10 05:26:51 PM PDT 24
Peak memory 204904 kb
Host smart-81c8fd91-c71d-4066-923f-abea6e0e9ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19403
83388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1940383388
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.2570372534
Short name T697
Test name
Test status
Simulation time 35666747 ps
CPU time 0.65 seconds
Started Jun 10 05:26:41 PM PDT 24
Finished Jun 10 05:26:42 PM PDT 24
Peak memory 204996 kb
Host smart-27b7757e-86f0-41f4-81fd-714a968e3313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25703
72534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2570372534
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.1690836405
Short name T1318
Test name
Test status
Simulation time 766854760 ps
CPU time 1.99 seconds
Started Jun 10 05:26:39 PM PDT 24
Finished Jun 10 05:26:41 PM PDT 24
Peak memory 205184 kb
Host smart-998fc129-c7eb-4d43-b8d8-77fbe2f51716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16908
36405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.1690836405
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1745200188
Short name T1938
Test name
Test status
Simulation time 203914497 ps
CPU time 2.09 seconds
Started Jun 10 05:26:42 PM PDT 24
Finished Jun 10 05:26:44 PM PDT 24
Peak memory 205116 kb
Host smart-dbf5ffdf-f2f6-4d23-a22e-d7b05fcc5278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17452
00188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1745200188
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.3920707462
Short name T2007
Test name
Test status
Simulation time 216125971 ps
CPU time 0.87 seconds
Started Jun 10 05:26:47 PM PDT 24
Finished Jun 10 05:26:48 PM PDT 24
Peak memory 204956 kb
Host smart-87ed89ed-8a86-4914-8829-8118ceb8dcc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39207
07462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3920707462
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3863488600
Short name T75
Test name
Test status
Simulation time 142152479 ps
CPU time 0.82 seconds
Started Jun 10 05:26:45 PM PDT 24
Finished Jun 10 05:26:46 PM PDT 24
Peak memory 205000 kb
Host smart-f9f9f9f1-3ee2-4b45-a51d-c470f9f9e721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38634
88600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3863488600
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2124073533
Short name T1428
Test name
Test status
Simulation time 241422822 ps
CPU time 0.89 seconds
Started Jun 10 05:26:43 PM PDT 24
Finished Jun 10 05:26:44 PM PDT 24
Peak memory 205000 kb
Host smart-1589fdd9-a1b1-4629-ae54-ac00d1255ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21240
73533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2124073533
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.376335874
Short name T737
Test name
Test status
Simulation time 162032275 ps
CPU time 0.82 seconds
Started Jun 10 05:26:57 PM PDT 24
Finished Jun 10 05:26:58 PM PDT 24
Peak memory 205008 kb
Host smart-d8fa9044-79e1-4398-b894-4ed5ff58cf56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37633
5874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.376335874
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.1906409890
Short name T1350
Test name
Test status
Simulation time 3273238302 ps
CPU time 3.9 seconds
Started Jun 10 05:26:47 PM PDT 24
Finished Jun 10 05:26:51 PM PDT 24
Peak memory 205044 kb
Host smart-0483b760-f60f-4ea5-9aa0-b70c38cd7d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19064
09890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1906409890
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2350320235
Short name T665
Test name
Test status
Simulation time 198859804 ps
CPU time 0.85 seconds
Started Jun 10 05:26:47 PM PDT 24
Finished Jun 10 05:26:48 PM PDT 24
Peak memory 205004 kb
Host smart-08596c25-adf7-42e3-a9c4-25a644c2ca61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23503
20235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2350320235
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.791147862
Short name T1787
Test name
Test status
Simulation time 5634382219 ps
CPU time 39.27 seconds
Started Jun 10 05:26:45 PM PDT 24
Finished Jun 10 05:27:25 PM PDT 24
Peak memory 205148 kb
Host smart-5b77834b-5387-438a-920b-10b8276f4995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79114
7862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.791147862
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1538323206
Short name T2060
Test name
Test status
Simulation time 147612660 ps
CPU time 0.78 seconds
Started Jun 10 05:26:45 PM PDT 24
Finished Jun 10 05:26:46 PM PDT 24
Peak memory 205012 kb
Host smart-90bfcf08-d7ad-4b14-8f48-31ac4057ec76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15383
23206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1538323206
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2371116351
Short name T1828
Test name
Test status
Simulation time 190897695 ps
CPU time 0.83 seconds
Started Jun 10 05:26:47 PM PDT 24
Finished Jun 10 05:26:48 PM PDT 24
Peak memory 204984 kb
Host smart-a552e7e1-1e96-46e6-8150-34a48bb030c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23711
16351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2371116351
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.1525299722
Short name T519
Test name
Test status
Simulation time 192026880 ps
CPU time 0.84 seconds
Started Jun 10 05:26:48 PM PDT 24
Finished Jun 10 05:26:49 PM PDT 24
Peak memory 204992 kb
Host smart-d7661ecd-986e-451c-98c5-a54d7376bf01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15252
99722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.1525299722
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1398314118
Short name T1946
Test name
Test status
Simulation time 217489426 ps
CPU time 0.84 seconds
Started Jun 10 05:26:59 PM PDT 24
Finished Jun 10 05:27:00 PM PDT 24
Peak memory 205020 kb
Host smart-e848cd75-b883-47d5-9927-cdc4cbfd320e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13983
14118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1398314118
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3620909477
Short name T1918
Test name
Test status
Simulation time 196276984 ps
CPU time 0.82 seconds
Started Jun 10 05:27:10 PM PDT 24
Finished Jun 10 05:27:11 PM PDT 24
Peak memory 205012 kb
Host smart-1cbe0a5d-d694-417c-afe9-495f4ab3d2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36209
09477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3620909477
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3461016539
Short name T648
Test name
Test status
Simulation time 205069993 ps
CPU time 0.94 seconds
Started Jun 10 05:27:06 PM PDT 24
Finished Jun 10 05:27:07 PM PDT 24
Peak memory 205016 kb
Host smart-748a6984-67ca-4ffa-b26d-64215b783455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34610
16539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3461016539
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_eop_single_bit_handling.1577749156
Short name T1111
Test name
Test status
Simulation time 213862197 ps
CPU time 0.91 seconds
Started Jun 10 05:26:50 PM PDT 24
Finished Jun 10 05:26:51 PM PDT 24
Peak memory 205024 kb
Host smart-713cdc31-bd1a-4077-b707-76391ff13c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15777
49156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_eop_single_bit_handling.1577749156
Directory /workspace/27.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2733075160
Short name T1446
Test name
Test status
Simulation time 153125139 ps
CPU time 0.81 seconds
Started Jun 10 05:26:51 PM PDT 24
Finished Jun 10 05:26:52 PM PDT 24
Peak memory 205008 kb
Host smart-c5f69ca7-a30f-4310-8134-6f7ced7e7ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27330
75160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2733075160
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3945405227
Short name T2066
Test name
Test status
Simulation time 88226215 ps
CPU time 0.71 seconds
Started Jun 10 05:27:08 PM PDT 24
Finished Jun 10 05:27:09 PM PDT 24
Peak memory 204928 kb
Host smart-ae3788f0-8bc7-48a2-a6de-6555ecd1482f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39454
05227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3945405227
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2643326524
Short name T790
Test name
Test status
Simulation time 24040478164 ps
CPU time 54.37 seconds
Started Jun 10 05:26:49 PM PDT 24
Finished Jun 10 05:27:43 PM PDT 24
Peak memory 205216 kb
Host smart-bb3fff99-50a2-40b1-bb16-6a3d1c24a0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26433
26524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2643326524
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2841286793
Short name T1548
Test name
Test status
Simulation time 184109533 ps
CPU time 0.82 seconds
Started Jun 10 05:26:47 PM PDT 24
Finished Jun 10 05:26:48 PM PDT 24
Peak memory 204984 kb
Host smart-d1644977-45ad-4eed-8b38-e672b904dc49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28412
86793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2841286793
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3203204754
Short name T1620
Test name
Test status
Simulation time 230233513 ps
CPU time 0.94 seconds
Started Jun 10 05:27:14 PM PDT 24
Finished Jun 10 05:27:16 PM PDT 24
Peak memory 204992 kb
Host smart-65dca32e-2c6d-4910-9d56-e6849b5c8535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32032
04754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3203204754
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.3735876106
Short name T1253
Test name
Test status
Simulation time 154614437 ps
CPU time 0.76 seconds
Started Jun 10 05:26:46 PM PDT 24
Finished Jun 10 05:26:47 PM PDT 24
Peak memory 205008 kb
Host smart-690e4821-ddee-4c1b-8df5-1bfd8149599c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37358
76106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.3735876106
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.265517101
Short name T61
Test name
Test status
Simulation time 163270112 ps
CPU time 0.8 seconds
Started Jun 10 05:26:46 PM PDT 24
Finished Jun 10 05:26:47 PM PDT 24
Peak memory 205024 kb
Host smart-b72bf6fb-88d7-417d-9481-01b6d8ce2ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26551
7101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.265517101
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.883764325
Short name T192
Test name
Test status
Simulation time 143236806 ps
CPU time 0.75 seconds
Started Jun 10 05:26:47 PM PDT 24
Finished Jun 10 05:26:49 PM PDT 24
Peak memory 204972 kb
Host smart-534fc418-826b-4129-b1dc-66062c23c08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88376
4325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.883764325
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.4189767516
Short name T724
Test name
Test status
Simulation time 163733162 ps
CPU time 0.82 seconds
Started Jun 10 05:26:55 PM PDT 24
Finished Jun 10 05:26:56 PM PDT 24
Peak memory 205008 kb
Host smart-10dfa531-ca16-4e96-8eec-8a9ca4081281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41897
67516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.4189767516
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.188825368
Short name T195
Test name
Test status
Simulation time 204024443 ps
CPU time 0.93 seconds
Started Jun 10 05:26:43 PM PDT 24
Finished Jun 10 05:26:44 PM PDT 24
Peak memory 205004 kb
Host smart-4d3cbff6-4c7b-409f-b109-845f688e77b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18882
5368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.188825368
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.112187064
Short name T395
Test name
Test status
Simulation time 154147713 ps
CPU time 0.77 seconds
Started Jun 10 05:26:46 PM PDT 24
Finished Jun 10 05:26:48 PM PDT 24
Peak memory 205032 kb
Host smart-905b9051-e75a-4045-86a4-aa4d6a72127a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11218
7064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.112187064
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1249563631
Short name T718
Test name
Test status
Simulation time 196201287 ps
CPU time 0.91 seconds
Started Jun 10 05:27:03 PM PDT 24
Finished Jun 10 05:27:04 PM PDT 24
Peak memory 205008 kb
Host smart-785a5ce8-297b-4259-afa8-1997672f0657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12495
63631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1249563631
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.817005199
Short name T1757
Test name
Test status
Simulation time 13666009070 ps
CPU time 107.65 seconds
Started Jun 10 05:26:47 PM PDT 24
Finished Jun 10 05:28:35 PM PDT 24
Peak memory 205204 kb
Host smart-8d06fa9d-51c3-43ba-9af3-0c85b40adf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81700
5199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.817005199
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.1393026070
Short name T1473
Test name
Test status
Simulation time 261128592 ps
CPU time 0.93 seconds
Started Jun 10 05:27:20 PM PDT 24
Finished Jun 10 05:27:21 PM PDT 24
Peak memory 205032 kb
Host smart-9b27a782-9692-40c2-a9ef-daab8279710b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1393026070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.1393026070
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.3359894822
Short name T1283
Test name
Test status
Simulation time 178849520 ps
CPU time 0.83 seconds
Started Jun 10 05:26:57 PM PDT 24
Finished Jun 10 05:26:58 PM PDT 24
Peak memory 205044 kb
Host smart-e3be6d87-bc8a-491b-a694-f29519ace1d5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3359894822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.3359894822
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.4146221163
Short name T984
Test name
Test status
Simulation time 204909197 ps
CPU time 0.8 seconds
Started Jun 10 05:27:18 PM PDT 24
Finished Jun 10 05:27:19 PM PDT 24
Peak memory 205008 kb
Host smart-8fdd8bc0-c870-479a-95a6-ed212a7c271f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41462
21163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.4146221163
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1538873827
Short name T1756
Test name
Test status
Simulation time 4411452661 ps
CPU time 5.36 seconds
Started Jun 10 05:26:49 PM PDT 24
Finished Jun 10 05:26:55 PM PDT 24
Peak memory 205124 kb
Host smart-9263f455-5f08-45b6-aa2b-bda2dcf1d9e6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1538873827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.1538873827
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.2753268772
Short name T1212
Test name
Test status
Simulation time 13494650391 ps
CPU time 13.3 seconds
Started Jun 10 05:26:48 PM PDT 24
Finished Jun 10 05:27:02 PM PDT 24
Peak memory 205264 kb
Host smart-1e8cc6ab-d61d-4e25-b3b8-0f25920a3b02
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2753268772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.2753268772
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.725699526
Short name T328
Test name
Test status
Simulation time 23373528550 ps
CPU time 27.52 seconds
Started Jun 10 05:26:46 PM PDT 24
Finished Jun 10 05:27:14 PM PDT 24
Peak memory 205192 kb
Host smart-b17b378c-ac63-4177-8b77-7d41bc37abdf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=725699526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.725699526
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3741956376
Short name T757
Test name
Test status
Simulation time 158537772 ps
CPU time 0.79 seconds
Started Jun 10 05:26:51 PM PDT 24
Finished Jun 10 05:26:52 PM PDT 24
Peak memory 205008 kb
Host smart-3f34797c-cf9b-4ef6-bb48-ec9058f49493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37419
56376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3741956376
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.1954743370
Short name T1761
Test name
Test status
Simulation time 149491688 ps
CPU time 0.77 seconds
Started Jun 10 05:26:51 PM PDT 24
Finished Jun 10 05:26:53 PM PDT 24
Peak memory 204888 kb
Host smart-8bc1f59f-1efd-4204-9a49-0653bd7c8eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19547
43370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.1954743370
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2459526396
Short name T1644
Test name
Test status
Simulation time 1069810374 ps
CPU time 2.4 seconds
Started Jun 10 05:27:04 PM PDT 24
Finished Jun 10 05:27:06 PM PDT 24
Peak memory 205112 kb
Host smart-14cad0d4-b7ea-450e-aad4-4603e996fca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24595
26396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2459526396
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.2829531207
Short name T2091
Test name
Test status
Simulation time 165170967 ps
CPU time 0.8 seconds
Started Jun 10 05:27:18 PM PDT 24
Finished Jun 10 05:27:20 PM PDT 24
Peak memory 205020 kb
Host smart-a2d3ed6e-cc10-4e9a-a42c-ebf23d5b45ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28295
31207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.2829531207
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.2560095151
Short name T1751
Test name
Test status
Simulation time 50211223 ps
CPU time 0.69 seconds
Started Jun 10 05:26:53 PM PDT 24
Finished Jun 10 05:26:54 PM PDT 24
Peak memory 204924 kb
Host smart-6a84e179-8776-4af7-8277-cf0d09815105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25600
95151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2560095151
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.2086415119
Short name T2019
Test name
Test status
Simulation time 969435339 ps
CPU time 2.32 seconds
Started Jun 10 05:27:04 PM PDT 24
Finished Jun 10 05:27:07 PM PDT 24
Peak memory 205100 kb
Host smart-165e46e1-481c-4b74-a89d-dc243a22efe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20864
15119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.2086415119
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1946653044
Short name T2005
Test name
Test status
Simulation time 220354918 ps
CPU time 1.5 seconds
Started Jun 10 05:26:50 PM PDT 24
Finished Jun 10 05:26:51 PM PDT 24
Peak memory 205052 kb
Host smart-c4b36ddf-f7fb-4a35-ad76-13ef8cd14b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19466
53044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1946653044
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.3110430240
Short name T1144
Test name
Test status
Simulation time 191052538 ps
CPU time 0.99 seconds
Started Jun 10 05:26:51 PM PDT 24
Finished Jun 10 05:26:53 PM PDT 24
Peak memory 205140 kb
Host smart-95521cdc-3494-46e0-bf5e-4829da85a230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31104
30240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3110430240
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3850280346
Short name T1957
Test name
Test status
Simulation time 153067182 ps
CPU time 0.81 seconds
Started Jun 10 05:26:52 PM PDT 24
Finished Jun 10 05:26:53 PM PDT 24
Peak memory 205020 kb
Host smart-68579f0e-8844-4462-bb18-3bf4b1b4e261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38502
80346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3850280346
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.134776542
Short name T1104
Test name
Test status
Simulation time 188024153 ps
CPU time 0.88 seconds
Started Jun 10 05:27:00 PM PDT 24
Finished Jun 10 05:27:01 PM PDT 24
Peak memory 205036 kb
Host smart-243aa4a7-8f3b-41fa-a222-0bb8da62629c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13477
6542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.134776542
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.1788720853
Short name T1666
Test name
Test status
Simulation time 194778573 ps
CPU time 0.87 seconds
Started Jun 10 05:27:11 PM PDT 24
Finished Jun 10 05:27:13 PM PDT 24
Peak memory 204992 kb
Host smart-bc98432d-5941-4223-9d0b-3d969910880a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17887
20853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.1788720853
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.2612428015
Short name T484
Test name
Test status
Simulation time 3279491258 ps
CPU time 4.15 seconds
Started Jun 10 05:26:53 PM PDT 24
Finished Jun 10 05:26:58 PM PDT 24
Peak memory 204980 kb
Host smart-489d0b18-c926-4d9f-af3b-a558770f07aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26124
28015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.2612428015
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2493526769
Short name T885
Test name
Test status
Simulation time 209298701 ps
CPU time 0.87 seconds
Started Jun 10 05:26:54 PM PDT 24
Finished Jun 10 05:26:55 PM PDT 24
Peak memory 205028 kb
Host smart-3b8650f5-a8a3-46bd-8645-1235aba1ade8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24935
26769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2493526769
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2907515057
Short name T359
Test name
Test status
Simulation time 14698057124 ps
CPU time 100.37 seconds
Started Jun 10 05:27:11 PM PDT 24
Finished Jun 10 05:28:52 PM PDT 24
Peak memory 205124 kb
Host smart-3d716327-8446-4a9f-9268-faf3223c69b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29075
15057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2907515057
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.184771277
Short name T1523
Test name
Test status
Simulation time 210536711 ps
CPU time 0.81 seconds
Started Jun 10 05:26:48 PM PDT 24
Finished Jun 10 05:26:49 PM PDT 24
Peak memory 204992 kb
Host smart-20816a0a-d23b-4b72-ab53-bbfda2a881d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18477
1277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.184771277
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.993064977
Short name T1371
Test name
Test status
Simulation time 196933265 ps
CPU time 0.95 seconds
Started Jun 10 05:26:55 PM PDT 24
Finished Jun 10 05:26:57 PM PDT 24
Peak memory 205012 kb
Host smart-e90f91b6-9b4f-48c9-8a37-79e0670d7d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99306
4977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.993064977
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.1828660299
Short name T1343
Test name
Test status
Simulation time 189997856 ps
CPU time 0.88 seconds
Started Jun 10 05:26:59 PM PDT 24
Finished Jun 10 05:27:01 PM PDT 24
Peak memory 205004 kb
Host smart-e3c9803c-a886-49f9-86ca-7d4747da5637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18286
60299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.1828660299
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1731225136
Short name T1920
Test name
Test status
Simulation time 174468994 ps
CPU time 0.83 seconds
Started Jun 10 05:26:53 PM PDT 24
Finished Jun 10 05:26:54 PM PDT 24
Peak memory 204936 kb
Host smart-dc6487fe-a5d0-49a3-b680-4fe505f3dc0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17312
25136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1731225136
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.396857033
Short name T1870
Test name
Test status
Simulation time 213907152 ps
CPU time 0.89 seconds
Started Jun 10 05:26:52 PM PDT 24
Finished Jun 10 05:26:53 PM PDT 24
Peak memory 205144 kb
Host smart-729d95ea-94f3-4388-a879-7559bfd84478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39685
7033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.396857033
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3585672048
Short name T1659
Test name
Test status
Simulation time 156568422 ps
CPU time 0.81 seconds
Started Jun 10 05:27:08 PM PDT 24
Finished Jun 10 05:27:09 PM PDT 24
Peak memory 205004 kb
Host smart-7f0d026e-64a5-40cf-a481-9fd3dcb696e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35856
72048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3585672048
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_eop_single_bit_handling.118986807
Short name T930
Test name
Test status
Simulation time 143859515 ps
CPU time 0.82 seconds
Started Jun 10 05:27:04 PM PDT 24
Finished Jun 10 05:27:10 PM PDT 24
Peak memory 204852 kb
Host smart-2ae804a2-2bcf-429f-a40f-706cd31beb1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11898
6807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_eop_single_bit_handling.118986807
Directory /workspace/28.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3887493706
Short name T1643
Test name
Test status
Simulation time 148747352 ps
CPU time 0.77 seconds
Started Jun 10 05:27:04 PM PDT 24
Finished Jun 10 05:27:05 PM PDT 24
Peak memory 205044 kb
Host smart-f3edf3f1-af85-4bcb-be92-c4bb34137847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38874
93706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3887493706
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3047331875
Short name T2000
Test name
Test status
Simulation time 40917464 ps
CPU time 0.69 seconds
Started Jun 10 05:27:17 PM PDT 24
Finished Jun 10 05:27:19 PM PDT 24
Peak memory 204984 kb
Host smart-0d52b2f5-060a-4b76-bb52-2af59b57a67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30473
31875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3047331875
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2439381419
Short name T2098
Test name
Test status
Simulation time 10923619833 ps
CPU time 24.86 seconds
Started Jun 10 05:26:52 PM PDT 24
Finished Jun 10 05:27:17 PM PDT 24
Peak memory 205128 kb
Host smart-f2a8a5e5-4dae-4466-92a2-8181c8d96f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24393
81419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2439381419
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.642798122
Short name T1872
Test name
Test status
Simulation time 199419028 ps
CPU time 0.95 seconds
Started Jun 10 05:26:55 PM PDT 24
Finished Jun 10 05:26:56 PM PDT 24
Peak memory 204992 kb
Host smart-a28a91c0-7be6-40c0-9f37-37ebd83c4893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64279
8122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.642798122
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.610976590
Short name T1676
Test name
Test status
Simulation time 236083923 ps
CPU time 0.97 seconds
Started Jun 10 05:26:58 PM PDT 24
Finished Jun 10 05:27:00 PM PDT 24
Peak memory 205108 kb
Host smart-b982de0c-8acf-4861-8205-7d261b7cc234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61097
6590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.610976590
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.648020199
Short name T1245
Test name
Test status
Simulation time 174952319 ps
CPU time 0.81 seconds
Started Jun 10 05:27:04 PM PDT 24
Finished Jun 10 05:27:06 PM PDT 24
Peak memory 205004 kb
Host smart-6d11488e-6d9d-4e61-823f-926fa14024ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64802
0199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.648020199
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.263721264
Short name T1329
Test name
Test status
Simulation time 167821667 ps
CPU time 0.81 seconds
Started Jun 10 05:26:58 PM PDT 24
Finished Jun 10 05:26:59 PM PDT 24
Peak memory 205068 kb
Host smart-687c8f79-5054-4dfe-b378-101748b1f3e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26372
1264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.263721264
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2909656669
Short name T28
Test name
Test status
Simulation time 164543452 ps
CPU time 0.79 seconds
Started Jun 10 05:26:51 PM PDT 24
Finished Jun 10 05:26:52 PM PDT 24
Peak memory 204992 kb
Host smart-1d2a4d21-cb16-4418-8ca5-9283de0fbd11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29096
56669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2909656669
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3974034386
Short name T20
Test name
Test status
Simulation time 173329796 ps
CPU time 0.9 seconds
Started Jun 10 05:27:15 PM PDT 24
Finished Jun 10 05:27:17 PM PDT 24
Peak memory 204996 kb
Host smart-a291e692-81bc-4731-8e3e-1cd6cfe9ec37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39740
34386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3974034386
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2909822905
Short name T691
Test name
Test status
Simulation time 291410688 ps
CPU time 0.97 seconds
Started Jun 10 05:27:12 PM PDT 24
Finished Jun 10 05:27:13 PM PDT 24
Peak memory 204996 kb
Host smart-c2c93beb-6b35-4d53-b632-364db8cef009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29098
22905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2909822905
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.266351193
Short name T379
Test name
Test status
Simulation time 203014890 ps
CPU time 0.82 seconds
Started Jun 10 05:27:07 PM PDT 24
Finished Jun 10 05:27:08 PM PDT 24
Peak memory 205060 kb
Host smart-61c0ef50-ad1c-496b-84cb-ade29ed6785c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26635
1193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.266351193
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.3101310158
Short name T800
Test name
Test status
Simulation time 164012594 ps
CPU time 0.8 seconds
Started Jun 10 05:27:15 PM PDT 24
Finished Jun 10 05:27:16 PM PDT 24
Peak memory 204988 kb
Host smart-56ec1089-3e2f-40fc-873c-26a848b466f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31013
10158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.3101310158
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.2081554670
Short name T912
Test name
Test status
Simulation time 13157026084 ps
CPU time 126.36 seconds
Started Jun 10 05:26:56 PM PDT 24
Finished Jun 10 05:29:03 PM PDT 24
Peak memory 205224 kb
Host smart-2695a3ef-6fc0-44c1-b1c4-6cf8eb746300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20815
54670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.2081554670
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.1176166002
Short name T1891
Test name
Test status
Simulation time 268165198 ps
CPU time 0.96 seconds
Started Jun 10 05:27:16 PM PDT 24
Finished Jun 10 05:27:17 PM PDT 24
Peak memory 205012 kb
Host smart-169510fb-bf49-4f39-8e8a-387eccc8a1ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1176166002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.1176166002
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.1526773022
Short name T1950
Test name
Test status
Simulation time 161320777 ps
CPU time 0.87 seconds
Started Jun 10 05:27:02 PM PDT 24
Finished Jun 10 05:27:03 PM PDT 24
Peak memory 205036 kb
Host smart-216cc792-22cd-44ce-b332-0560c52e71c0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1526773022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.1526773022
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.4027124344
Short name T18
Test name
Test status
Simulation time 185650047 ps
CPU time 0.84 seconds
Started Jun 10 05:27:21 PM PDT 24
Finished Jun 10 05:27:22 PM PDT 24
Peak memory 205048 kb
Host smart-320db4cf-8973-4730-b78c-a1081e49935c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40271
24344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.4027124344
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.327322620
Short name T13
Test name
Test status
Simulation time 3493085037 ps
CPU time 4.76 seconds
Started Jun 10 05:26:57 PM PDT 24
Finished Jun 10 05:27:02 PM PDT 24
Peak memory 205072 kb
Host smart-cbdfc4b0-5cc8-4735-b56c-cd5d90eea530
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=327322620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.327322620
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.3891825151
Short name T1654
Test name
Test status
Simulation time 23335565203 ps
CPU time 22.82 seconds
Started Jun 10 05:27:17 PM PDT 24
Finished Jun 10 05:27:40 PM PDT 24
Peak memory 205120 kb
Host smart-4d0c8a84-13da-4471-91d2-c463c42057cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3891825151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.3891825151
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2326833643
Short name T982
Test name
Test status
Simulation time 150572496 ps
CPU time 0.76 seconds
Started Jun 10 05:26:58 PM PDT 24
Finished Jun 10 05:26:59 PM PDT 24
Peak memory 205032 kb
Host smart-17ab5be8-1020-464a-9c77-b2733f809d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23268
33643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2326833643
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.145166564
Short name T940
Test name
Test status
Simulation time 154513608 ps
CPU time 0.83 seconds
Started Jun 10 05:26:58 PM PDT 24
Finished Jun 10 05:27:00 PM PDT 24
Peak memory 205028 kb
Host smart-96bba629-a409-49c1-ab17-0c003ca9ba95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14516
6564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.145166564
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.3006297809
Short name T1528
Test name
Test status
Simulation time 433272473 ps
CPU time 1.3 seconds
Started Jun 10 05:26:58 PM PDT 24
Finished Jun 10 05:27:00 PM PDT 24
Peak memory 205000 kb
Host smart-b885c347-5024-4527-bcdf-b96712ef3164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30062
97809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3006297809
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.485194422
Short name T423
Test name
Test status
Simulation time 145224507 ps
CPU time 0.76 seconds
Started Jun 10 05:27:12 PM PDT 24
Finished Jun 10 05:27:13 PM PDT 24
Peak memory 205012 kb
Host smart-2a8bfb51-5b78-442e-9113-5dee7f67e095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48519
4422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.485194422
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.618267312
Short name T466
Test name
Test status
Simulation time 50998863 ps
CPU time 0.67 seconds
Started Jun 10 05:27:03 PM PDT 24
Finished Jun 10 05:27:04 PM PDT 24
Peak memory 205048 kb
Host smart-e667ac30-7d7e-425a-9c69-bd69be655ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61826
7312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.618267312
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3888155090
Short name T1168
Test name
Test status
Simulation time 836827472 ps
CPU time 2.01 seconds
Started Jun 10 05:27:20 PM PDT 24
Finished Jun 10 05:27:22 PM PDT 24
Peak memory 205100 kb
Host smart-b1b617ca-d457-4c5c-b5d6-eaa397eff3eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38881
55090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3888155090
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3223461344
Short name T609
Test name
Test status
Simulation time 423513871 ps
CPU time 2.35 seconds
Started Jun 10 05:27:32 PM PDT 24
Finished Jun 10 05:27:35 PM PDT 24
Peak memory 205072 kb
Host smart-180a13f7-42c5-4c0b-9d84-75df5d165751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32234
61344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3223461344
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1789327175
Short name T1483
Test name
Test status
Simulation time 268923217 ps
CPU time 0.96 seconds
Started Jun 10 05:27:01 PM PDT 24
Finished Jun 10 05:27:02 PM PDT 24
Peak memory 204884 kb
Host smart-69426b57-0007-4982-9378-13da220aca6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17893
27175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1789327175
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2367010399
Short name T1900
Test name
Test status
Simulation time 146698983 ps
CPU time 0.81 seconds
Started Jun 10 05:27:01 PM PDT 24
Finished Jun 10 05:27:03 PM PDT 24
Peak memory 204988 kb
Host smart-9d452347-59a1-4d20-865b-57730fa65ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23670
10399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2367010399
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1216067926
Short name T555
Test name
Test status
Simulation time 268370871 ps
CPU time 0.97 seconds
Started Jun 10 05:27:18 PM PDT 24
Finished Jun 10 05:27:19 PM PDT 24
Peak memory 204992 kb
Host smart-6db7cc1a-af0e-4400-a148-414b4901249e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12160
67926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1216067926
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.3811270643
Short name T1820
Test name
Test status
Simulation time 199424357 ps
CPU time 0.83 seconds
Started Jun 10 05:27:17 PM PDT 24
Finished Jun 10 05:27:19 PM PDT 24
Peak memory 204980 kb
Host smart-f2ae5afa-d971-486e-80f3-6d1f3a684029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38112
70643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.3811270643
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.878867926
Short name T633
Test name
Test status
Simulation time 3303981878 ps
CPU time 4.04 seconds
Started Jun 10 05:26:57 PM PDT 24
Finished Jun 10 05:27:01 PM PDT 24
Peak memory 205024 kb
Host smart-afeb7960-3eb7-4a35-a50c-7f4da268ae33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87886
7926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.878867926
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.86508272
Short name T608
Test name
Test status
Simulation time 198078850 ps
CPU time 0.84 seconds
Started Jun 10 05:27:24 PM PDT 24
Finished Jun 10 05:27:25 PM PDT 24
Peak memory 204984 kb
Host smart-6182d024-22a8-4ed7-8b04-4ed7f1e0308e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86508
272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.86508272
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.2056588741
Short name T2059
Test name
Test status
Simulation time 10010020399 ps
CPU time 76.4 seconds
Started Jun 10 05:27:24 PM PDT 24
Finished Jun 10 05:28:51 PM PDT 24
Peak memory 205088 kb
Host smart-ff7f60c5-8933-451b-a459-6ca5fcc69cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20565
88741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.2056588741
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2402019090
Short name T2075
Test name
Test status
Simulation time 154358656 ps
CPU time 0.78 seconds
Started Jun 10 05:27:16 PM PDT 24
Finished Jun 10 05:27:17 PM PDT 24
Peak memory 205004 kb
Host smart-060d906b-c517-403a-b738-677b017661c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24020
19090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2402019090
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3547144523
Short name T597
Test name
Test status
Simulation time 184964050 ps
CPU time 0.82 seconds
Started Jun 10 05:27:24 PM PDT 24
Finished Jun 10 05:27:25 PM PDT 24
Peak memory 205032 kb
Host smart-9db55226-b256-45e7-8930-68f16fd9040e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35471
44523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3547144523
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.4050325394
Short name T1544
Test name
Test status
Simulation time 155409765 ps
CPU time 0.88 seconds
Started Jun 10 05:27:15 PM PDT 24
Finished Jun 10 05:27:16 PM PDT 24
Peak memory 205008 kb
Host smart-05338dcf-041a-4408-8c87-010837eaae9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40503
25394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.4050325394
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3730391740
Short name T1361
Test name
Test status
Simulation time 169292689 ps
CPU time 0.78 seconds
Started Jun 10 05:26:58 PM PDT 24
Finished Jun 10 05:27:00 PM PDT 24
Peak memory 205004 kb
Host smart-6355dfae-1e50-4428-9d38-81c681203374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37303
91740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3730391740
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.753623986
Short name T506
Test name
Test status
Simulation time 172351505 ps
CPU time 0.88 seconds
Started Jun 10 05:26:58 PM PDT 24
Finished Jun 10 05:27:00 PM PDT 24
Peak memory 205020 kb
Host smart-1b3d7d7a-4d6f-47ff-bfee-dc0dc5e09396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75362
3986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.753623986
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.539033391
Short name T2040
Test name
Test status
Simulation time 158847969 ps
CPU time 0.79 seconds
Started Jun 10 05:27:23 PM PDT 24
Finished Jun 10 05:27:24 PM PDT 24
Peak memory 204992 kb
Host smart-8dcc6e7b-d35b-4fd3-a2b2-19d26b6749ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53903
3391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.539033391
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_eop_single_bit_handling.1766101385
Short name T457
Test name
Test status
Simulation time 163781882 ps
CPU time 0.84 seconds
Started Jun 10 05:26:59 PM PDT 24
Finished Jun 10 05:27:00 PM PDT 24
Peak memory 205012 kb
Host smart-222ae480-1e42-4d92-a8db-56b4ce679d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17661
01385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_eop_single_bit_handling.1766101385
Directory /workspace/29.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.3550229063
Short name T100
Test name
Test status
Simulation time 154702595 ps
CPU time 0.77 seconds
Started Jun 10 05:27:13 PM PDT 24
Finished Jun 10 05:27:15 PM PDT 24
Peak memory 205008 kb
Host smart-69e47928-bcf6-40d3-afa5-f6f8453bd0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35502
29063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.3550229063
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.827960119
Short name T928
Test name
Test status
Simulation time 77236990 ps
CPU time 0.69 seconds
Started Jun 10 05:26:56 PM PDT 24
Finished Jun 10 05:26:57 PM PDT 24
Peak memory 204980 kb
Host smart-6c61d097-616f-4292-8c8c-68484ed646db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82796
0119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.827960119
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.3997451243
Short name T94
Test name
Test status
Simulation time 20789962178 ps
CPU time 48.92 seconds
Started Jun 10 05:26:58 PM PDT 24
Finished Jun 10 05:27:48 PM PDT 24
Peak memory 205292 kb
Host smart-18e07991-df81-455e-9d9d-7e69b824d424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39974
51243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.3997451243
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1025444367
Short name T1584
Test name
Test status
Simulation time 161715816 ps
CPU time 0.8 seconds
Started Jun 10 05:27:21 PM PDT 24
Finished Jun 10 05:27:22 PM PDT 24
Peak memory 205000 kb
Host smart-be315453-8334-4a38-9d20-103a18d14883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10254
44367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1025444367
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3123681261
Short name T540
Test name
Test status
Simulation time 183800736 ps
CPU time 0.83 seconds
Started Jun 10 05:27:28 PM PDT 24
Finished Jun 10 05:27:29 PM PDT 24
Peak memory 204880 kb
Host smart-4a32bfba-741b-4e86-83d6-f570ea75d21b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31236
81261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3123681261
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.361104978
Short name T933
Test name
Test status
Simulation time 172666195 ps
CPU time 0.86 seconds
Started Jun 10 05:27:00 PM PDT 24
Finished Jun 10 05:27:01 PM PDT 24
Peak memory 205024 kb
Host smart-68bfa02c-8518-476e-8296-353aeb32fb89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36110
4978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.361104978
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.4177752510
Short name T1954
Test name
Test status
Simulation time 163169099 ps
CPU time 0.82 seconds
Started Jun 10 05:26:58 PM PDT 24
Finished Jun 10 05:26:59 PM PDT 24
Peak memory 205088 kb
Host smart-f6af2cd9-a738-4f75-ae20-abbd94fd8dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41777
52510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.4177752510
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.3099930893
Short name T169
Test name
Test status
Simulation time 167004043 ps
CPU time 0.77 seconds
Started Jun 10 05:26:59 PM PDT 24
Finished Jun 10 05:27:01 PM PDT 24
Peak memory 205004 kb
Host smart-3f358b63-ee81-42e4-914b-63051c08843c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30999
30893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.3099930893
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2546667433
Short name T1461
Test name
Test status
Simulation time 170855379 ps
CPU time 0.78 seconds
Started Jun 10 05:27:15 PM PDT 24
Finished Jun 10 05:27:17 PM PDT 24
Peak memory 204892 kb
Host smart-3524a13a-318f-4e12-8c50-3cd9e4562ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25466
67433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2546667433
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1618024870
Short name T1134
Test name
Test status
Simulation time 211422094 ps
CPU time 0.93 seconds
Started Jun 10 05:27:16 PM PDT 24
Finished Jun 10 05:27:18 PM PDT 24
Peak memory 205004 kb
Host smart-ddf0e155-9341-42c2-ba11-0c12c069af4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16180
24870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1618024870
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.1118268922
Short name T814
Test name
Test status
Simulation time 158516068 ps
CPU time 0.76 seconds
Started Jun 10 05:26:58 PM PDT 24
Finished Jun 10 05:26:59 PM PDT 24
Peak memory 205004 kb
Host smart-6ae28264-3a83-45b7-9d65-1960b3536569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11182
68922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.1118268922
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.3068454891
Short name T1662
Test name
Test status
Simulation time 152825453 ps
CPU time 0.81 seconds
Started Jun 10 05:26:55 PM PDT 24
Finished Jun 10 05:26:56 PM PDT 24
Peak memory 205140 kb
Host smart-62b7a23d-6907-45a1-9af4-618a758e9630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30684
54891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.3068454891
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.4048755854
Short name T2073
Test name
Test status
Simulation time 4761252977 ps
CPU time 122.29 seconds
Started Jun 10 05:27:17 PM PDT 24
Finished Jun 10 05:29:20 PM PDT 24
Peak memory 205228 kb
Host smart-52f90a4c-9cbd-46a1-b9eb-648c795b19be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40487
55854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.4048755854
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.636834120
Short name T378
Test name
Test status
Simulation time 235400573 ps
CPU time 1.04 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:24:45 PM PDT 24
Peak memory 205012 kb
Host smart-d208f214-d26d-4220-ad61-f1d36764dfc0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=636834120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.636834120
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.38790015
Short name T1485
Test name
Test status
Simulation time 194253030 ps
CPU time 0.83 seconds
Started Jun 10 05:24:40 PM PDT 24
Finished Jun 10 05:24:41 PM PDT 24
Peak memory 205036 kb
Host smart-f87c3539-f9c7-43c1-9ffd-7fafebc0d2f6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=38790015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.38790015
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.201944141
Short name T1929
Test name
Test status
Simulation time 206102552 ps
CPU time 0.89 seconds
Started Jun 10 05:24:35 PM PDT 24
Finished Jun 10 05:24:36 PM PDT 24
Peak memory 205004 kb
Host smart-81fdcd1b-7448-40d4-93e5-a70174fba872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20194
4141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.201944141
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.2881876463
Short name T942
Test name
Test status
Simulation time 3553214689 ps
CPU time 4.06 seconds
Started Jun 10 05:24:26 PM PDT 24
Finished Jun 10 05:24:31 PM PDT 24
Peak memory 205096 kb
Host smart-e0c1d764-ee93-4fae-8dfe-9fd1d7e06f16
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2881876463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.2881876463
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.3001354124
Short name T1687
Test name
Test status
Simulation time 13328081799 ps
CPU time 13.37 seconds
Started Jun 10 05:24:25 PM PDT 24
Finished Jun 10 05:24:39 PM PDT 24
Peak memory 205052 kb
Host smart-c849d35b-405e-4624-855f-d31ec61a7f7d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3001354124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.3001354124
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.619725715
Short name T1478
Test name
Test status
Simulation time 23386404310 ps
CPU time 24.6 seconds
Started Jun 10 05:24:26 PM PDT 24
Finished Jun 10 05:24:51 PM PDT 24
Peak memory 205228 kb
Host smart-3e256859-ad73-429a-8c3d-3d5a420c1399
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=619725715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.619725715
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2899501078
Short name T1911
Test name
Test status
Simulation time 180924404 ps
CPU time 0.83 seconds
Started Jun 10 05:24:26 PM PDT 24
Finished Jun 10 05:24:28 PM PDT 24
Peak memory 205044 kb
Host smart-9da45d82-fc49-4db4-aa4a-e9de5f400ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28995
01078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2899501078
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.2881764600
Short name T1739
Test name
Test status
Simulation time 197690159 ps
CPU time 0.87 seconds
Started Jun 10 05:24:31 PM PDT 24
Finished Jun 10 05:24:32 PM PDT 24
Peak memory 205016 kb
Host smart-43110535-ccf8-46c4-b1f5-12073d6337aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28817
64600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.2881764600
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.599387378
Short name T1968
Test name
Test status
Simulation time 648220682 ps
CPU time 1.72 seconds
Started Jun 10 05:24:26 PM PDT 24
Finished Jun 10 05:24:28 PM PDT 24
Peak memory 205008 kb
Host smart-5d6c65dd-df86-470c-b52e-b224c9b99333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59938
7378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.599387378
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.3832168938
Short name T666
Test name
Test status
Simulation time 169641544 ps
CPU time 0.79 seconds
Started Jun 10 05:24:29 PM PDT 24
Finished Jun 10 05:24:30 PM PDT 24
Peak memory 205008 kb
Host smart-f4082b09-e61a-4e25-bc4b-ea93e6c3eef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38321
68938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.3832168938
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1004379981
Short name T307
Test name
Test status
Simulation time 42590141 ps
CPU time 0.65 seconds
Started Jun 10 05:24:26 PM PDT 24
Finished Jun 10 05:24:32 PM PDT 24
Peak memory 205020 kb
Host smart-ce287349-3a50-4ad5-9ea8-4d6300d441c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10043
79981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1004379981
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3974215898
Short name T1513
Test name
Test status
Simulation time 792342202 ps
CPU time 1.98 seconds
Started Jun 10 05:24:25 PM PDT 24
Finished Jun 10 05:24:28 PM PDT 24
Peak memory 205080 kb
Host smart-c4d054e6-eff5-423c-a694-c621e78760b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39742
15898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3974215898
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.456315924
Short name T518
Test name
Test status
Simulation time 282961693 ps
CPU time 1.48 seconds
Started Jun 10 05:24:30 PM PDT 24
Finished Jun 10 05:24:31 PM PDT 24
Peak memory 204996 kb
Host smart-7479da20-f273-45f9-88a0-6c5df253d49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45631
5924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.456315924
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1382952984
Short name T1129
Test name
Test status
Simulation time 145310767 ps
CPU time 0.88 seconds
Started Jun 10 05:24:31 PM PDT 24
Finished Jun 10 05:24:32 PM PDT 24
Peak memory 205004 kb
Host smart-97695944-9e12-4a24-aa99-e7a780b5ecc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13829
52984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1382952984
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.629261407
Short name T74
Test name
Test status
Simulation time 148148089 ps
CPU time 0.8 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:24:44 PM PDT 24
Peak memory 205016 kb
Host smart-30c141e8-57e6-4b5f-a406-a6a1dff84106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62926
1407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.629261407
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2664318776
Short name T305
Test name
Test status
Simulation time 200489200 ps
CPU time 0.83 seconds
Started Jun 10 05:24:27 PM PDT 24
Finished Jun 10 05:24:28 PM PDT 24
Peak memory 204984 kb
Host smart-1b3eb7b5-3f76-4ba4-9099-1b1561a89910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26643
18776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2664318776
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.3929142079
Short name T1353
Test name
Test status
Simulation time 202731625 ps
CPU time 0.86 seconds
Started Jun 10 05:24:29 PM PDT 24
Finished Jun 10 05:24:30 PM PDT 24
Peak memory 205032 kb
Host smart-73d22ee7-bd89-4426-b63c-070bf95ef8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39291
42079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.3929142079
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.3316600305
Short name T1916
Test name
Test status
Simulation time 3332547028 ps
CPU time 4.08 seconds
Started Jun 10 05:24:27 PM PDT 24
Finished Jun 10 05:24:31 PM PDT 24
Peak memory 205084 kb
Host smart-b1eec0ed-5407-49d2-abed-0a77f89796d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33166
00305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.3316600305
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1473074108
Short name T1451
Test name
Test status
Simulation time 198969645 ps
CPU time 0.81 seconds
Started Jun 10 05:24:24 PM PDT 24
Finished Jun 10 05:24:25 PM PDT 24
Peak memory 205032 kb
Host smart-26165170-f119-455c-adb2-2a08da6b64fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14730
74108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1473074108
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.3792889799
Short name T1651
Test name
Test status
Simulation time 15321841357 ps
CPU time 435.8 seconds
Started Jun 10 05:24:25 PM PDT 24
Finished Jun 10 05:31:42 PM PDT 24
Peak memory 205220 kb
Host smart-07b5b8c4-d7db-4f5c-98a3-ee847f002b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37928
89799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.3792889799
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1368590060
Short name T1139
Test name
Test status
Simulation time 151286617 ps
CPU time 0.79 seconds
Started Jun 10 05:24:26 PM PDT 24
Finished Jun 10 05:24:28 PM PDT 24
Peak memory 205024 kb
Host smart-482486dc-b476-4fbc-b1ba-10fd650eece4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13685
90060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1368590060
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2405144707
Short name T138
Test name
Test status
Simulation time 161236562 ps
CPU time 0.78 seconds
Started Jun 10 05:24:30 PM PDT 24
Finished Jun 10 05:24:31 PM PDT 24
Peak memory 205008 kb
Host smart-3491dae7-1af9-4775-8745-a7d64e1c402c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24051
44707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2405144707
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.1737861756
Short name T1629
Test name
Test status
Simulation time 157961526 ps
CPU time 0.81 seconds
Started Jun 10 05:24:28 PM PDT 24
Finished Jun 10 05:24:29 PM PDT 24
Peak memory 205056 kb
Host smart-de7d232b-2e4c-4cac-926d-ed75212e380a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17378
61756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.1737861756
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3154434952
Short name T986
Test name
Test status
Simulation time 146552555 ps
CPU time 0.87 seconds
Started Jun 10 05:24:27 PM PDT 24
Finished Jun 10 05:24:28 PM PDT 24
Peak memory 205032 kb
Host smart-85a362e9-45e8-4368-be21-af3ab622e8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31544
34952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3154434952
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1632077038
Short name T370
Test name
Test status
Simulation time 157780073 ps
CPU time 0.77 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:24:44 PM PDT 24
Peak memory 205008 kb
Host smart-c249a846-dbe4-4fee-9d9c-aeabbd4efb16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16320
77038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1632077038
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2322126173
Short name T1150
Test name
Test status
Simulation time 169825202 ps
CPU time 0.81 seconds
Started Jun 10 05:24:42 PM PDT 24
Finished Jun 10 05:24:43 PM PDT 24
Peak memory 205012 kb
Host smart-cfd57a14-f1b0-402a-b747-b2f31428e2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23221
26173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2322126173
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_eop_single_bit_handling.315371552
Short name T874
Test name
Test status
Simulation time 186375828 ps
CPU time 0.84 seconds
Started Jun 10 05:24:35 PM PDT 24
Finished Jun 10 05:24:37 PM PDT 24
Peak memory 205008 kb
Host smart-2f749719-819b-4341-b48c-727ebb068a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31537
1552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_eop_single_bit_handling.315371552
Directory /workspace/3.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.134617044
Short name T1927
Test name
Test status
Simulation time 138770276 ps
CPU time 0.77 seconds
Started Jun 10 05:24:38 PM PDT 24
Finished Jun 10 05:24:39 PM PDT 24
Peak memory 205004 kb
Host smart-7d9d434a-2ab0-4ab8-8427-b2e41f2bf9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13461
7044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.134617044
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1034081912
Short name T1924
Test name
Test status
Simulation time 72895462 ps
CPU time 0.71 seconds
Started Jun 10 05:24:42 PM PDT 24
Finished Jun 10 05:24:43 PM PDT 24
Peak memory 205004 kb
Host smart-25842eca-1250-4279-b485-76a520615650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10340
81912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1034081912
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2150956533
Short name T248
Test name
Test status
Simulation time 18966479113 ps
CPU time 41.88 seconds
Started Jun 10 05:24:34 PM PDT 24
Finished Jun 10 05:25:16 PM PDT 24
Peak memory 205176 kb
Host smart-26230670-a787-4c71-9179-1982e446bacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21509
56533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2150956533
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1781490658
Short name T1418
Test name
Test status
Simulation time 151739605 ps
CPU time 0.83 seconds
Started Jun 10 05:24:27 PM PDT 24
Finished Jun 10 05:24:29 PM PDT 24
Peak memory 205012 kb
Host smart-244df2de-f6a1-40bb-9243-aec0e293194e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17814
90658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1781490658
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.545306498
Short name T866
Test name
Test status
Simulation time 191555738 ps
CPU time 0.87 seconds
Started Jun 10 05:24:27 PM PDT 24
Finished Jun 10 05:24:28 PM PDT 24
Peak memory 205024 kb
Host smart-918bc248-3c42-4080-825a-bb112cdf4e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54530
6498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.545306498
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.1320484830
Short name T202
Test name
Test status
Simulation time 20947324995 ps
CPU time 127.56 seconds
Started Jun 10 05:24:38 PM PDT 24
Finished Jun 10 05:26:46 PM PDT 24
Peak memory 205220 kb
Host smart-4b4a098a-b5d0-41db-aa69-a1fa521f01ec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1320484830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.1320484830
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.603235223
Short name T1601
Test name
Test status
Simulation time 17585636411 ps
CPU time 137.84 seconds
Started Jun 10 05:24:27 PM PDT 24
Finished Jun 10 05:26:46 PM PDT 24
Peak memory 205244 kb
Host smart-bd21d8e5-a65d-425f-af90-7a4d14f5312c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=603235223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.603235223
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.3966237838
Short name T2057
Test name
Test status
Simulation time 12150982810 ps
CPU time 61.67 seconds
Started Jun 10 05:24:30 PM PDT 24
Finished Jun 10 05:25:32 PM PDT 24
Peak memory 205200 kb
Host smart-5bf060ae-53f3-4d9d-874e-6a5828365d1f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3966237838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.3966237838
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.1489272889
Short name T1056
Test name
Test status
Simulation time 145803213 ps
CPU time 0.8 seconds
Started Jun 10 05:24:42 PM PDT 24
Finished Jun 10 05:24:43 PM PDT 24
Peak memory 205008 kb
Host smart-bcedc3aa-eea7-4e98-8364-a85405bf5b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14892
72889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.1489272889
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1299466722
Short name T1579
Test name
Test status
Simulation time 156250308 ps
CPU time 0.8 seconds
Started Jun 10 05:24:30 PM PDT 24
Finished Jun 10 05:24:31 PM PDT 24
Peak memory 205008 kb
Host smart-aa306199-1c42-4f42-9ba7-90ab571566a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12994
66722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1299466722
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1015818206
Short name T123
Test name
Test status
Simulation time 482422230 ps
CPU time 1.35 seconds
Started Jun 10 05:24:33 PM PDT 24
Finished Jun 10 05:24:34 PM PDT 24
Peak memory 222440 kb
Host smart-752bbf50-50b0-4929-9c77-34adb8d1d357
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1015818206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1015818206
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2389026014
Short name T1798
Test name
Test status
Simulation time 152300798 ps
CPU time 0.79 seconds
Started Jun 10 05:24:30 PM PDT 24
Finished Jun 10 05:24:31 PM PDT 24
Peak memory 205020 kb
Host smart-b0ad3db4-d9f6-446a-8963-47a69877646e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23890
26014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2389026014
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.604455608
Short name T498
Test name
Test status
Simulation time 166327378 ps
CPU time 0.81 seconds
Started Jun 10 05:24:46 PM PDT 24
Finished Jun 10 05:24:48 PM PDT 24
Peak memory 205036 kb
Host smart-a3c26410-b2e6-488b-ad7d-472eba3c4093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60445
5608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.604455608
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.914760895
Short name T778
Test name
Test status
Simulation time 198283740 ps
CPU time 0.96 seconds
Started Jun 10 05:24:30 PM PDT 24
Finished Jun 10 05:24:31 PM PDT 24
Peak memory 205000 kb
Host smart-653173a7-6b75-4e20-8312-bcac772ce7f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91476
0895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.914760895
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2085773103
Short name T1120
Test name
Test status
Simulation time 159179063 ps
CPU time 0.82 seconds
Started Jun 10 05:24:25 PM PDT 24
Finished Jun 10 05:24:26 PM PDT 24
Peak memory 205044 kb
Host smart-55e645a3-a5eb-4e3c-8ad0-8ba025142109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20857
73103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2085773103
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.1817603394
Short name T407
Test name
Test status
Simulation time 12433850339 ps
CPU time 93.74 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:26:17 PM PDT 24
Peak memory 205228 kb
Host smart-9aca2b4b-7fc5-46db-9200-a43afbf1d839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18176
03394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.1817603394
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.1867105715
Short name T196
Test name
Test status
Simulation time 14832589524 ps
CPU time 308.18 seconds
Started Jun 10 05:24:47 PM PDT 24
Finished Jun 10 05:29:56 PM PDT 24
Peak memory 205216 kb
Host smart-adf521f2-7439-4754-9359-0ea0e350e615
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867105715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_
traffic.1867105715
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.1563048132
Short name T2031
Test name
Test status
Simulation time 245823293 ps
CPU time 0.95 seconds
Started Jun 10 05:27:07 PM PDT 24
Finished Jun 10 05:27:08 PM PDT 24
Peak memory 204952 kb
Host smart-21e2f2e4-d9f6-4735-88d3-f0edcdd4be85
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1563048132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.1563048132
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.3462032833
Short name T1649
Test name
Test status
Simulation time 165059502 ps
CPU time 0.86 seconds
Started Jun 10 05:27:28 PM PDT 24
Finished Jun 10 05:27:29 PM PDT 24
Peak memory 205028 kb
Host smart-2d312d37-603b-41ca-84f4-69164b9ea6d1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3462032833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.3462032833
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.2747348187
Short name T1802
Test name
Test status
Simulation time 194127643 ps
CPU time 0.87 seconds
Started Jun 10 05:27:04 PM PDT 24
Finished Jun 10 05:27:05 PM PDT 24
Peak memory 204984 kb
Host smart-87d81b92-29ab-4329-9aa0-d6cba0d3ef55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27473
48187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.2747348187
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.221325977
Short name T1145
Test name
Test status
Simulation time 3511917842 ps
CPU time 4.09 seconds
Started Jun 10 05:27:28 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 205056 kb
Host smart-4cf9dc62-4eea-4680-b54a-60ec96de951a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=221325977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.221325977
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.4060947038
Short name T511
Test name
Test status
Simulation time 13352868018 ps
CPU time 12.8 seconds
Started Jun 10 05:27:06 PM PDT 24
Finished Jun 10 05:27:19 PM PDT 24
Peak memory 204936 kb
Host smart-efe9157a-9b4f-4e02-be93-3542edb29ed3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4060947038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.4060947038
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.3112577222
Short name T629
Test name
Test status
Simulation time 23403909200 ps
CPU time 24.9 seconds
Started Jun 10 05:27:00 PM PDT 24
Finished Jun 10 05:27:26 PM PDT 24
Peak memory 205252 kb
Host smart-ae9a1ec7-41d3-490c-a4e8-1ebad69c3eac
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3112577222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.3112577222
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.3560752918
Short name T1181
Test name
Test status
Simulation time 148402834 ps
CPU time 0.8 seconds
Started Jun 10 05:27:01 PM PDT 24
Finished Jun 10 05:27:02 PM PDT 24
Peak memory 204788 kb
Host smart-ff82289f-d061-46e2-9be9-7ad822af4e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35607
52918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.3560752918
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.4292563421
Short name T1407
Test name
Test status
Simulation time 178844160 ps
CPU time 0.77 seconds
Started Jun 10 05:27:23 PM PDT 24
Finished Jun 10 05:27:24 PM PDT 24
Peak memory 205040 kb
Host smart-09bc6f21-ebf9-4e50-85bd-4b74445ed94b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42925
63421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.4292563421
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.4192884192
Short name T1736
Test name
Test status
Simulation time 1009698487 ps
CPU time 2.18 seconds
Started Jun 10 05:27:16 PM PDT 24
Finished Jun 10 05:27:19 PM PDT 24
Peak memory 205104 kb
Host smart-934bb577-cef0-49d2-946c-199e4504ccfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41928
84192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.4192884192
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.2714170444
Short name T1553
Test name
Test status
Simulation time 165937359 ps
CPU time 0.78 seconds
Started Jun 10 05:26:58 PM PDT 24
Finished Jun 10 05:26:59 PM PDT 24
Peak memory 205080 kb
Host smart-ca257029-8fdc-49e2-b853-baf938c86e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27141
70444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2714170444
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.446690468
Short name T994
Test name
Test status
Simulation time 88344476 ps
CPU time 0.74 seconds
Started Jun 10 05:27:01 PM PDT 24
Finished Jun 10 05:27:02 PM PDT 24
Peak memory 205016 kb
Host smart-c8e370de-16f8-42da-b7c1-a77b87c4dece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44669
0468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.446690468
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.4137011097
Short name T1416
Test name
Test status
Simulation time 950527869 ps
CPU time 2.13 seconds
Started Jun 10 05:27:01 PM PDT 24
Finished Jun 10 05:27:04 PM PDT 24
Peak memory 205132 kb
Host smart-155c5607-a81b-4160-af95-8008a3397361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41370
11097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.4137011097
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1655932986
Short name T410
Test name
Test status
Simulation time 199970410 ps
CPU time 1.73 seconds
Started Jun 10 05:27:01 PM PDT 24
Finished Jun 10 05:27:03 PM PDT 24
Peak memory 204808 kb
Host smart-369a07d1-74ac-4adb-bcf7-61e2870c1b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16559
32986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1655932986
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.4055739721
Short name T1648
Test name
Test status
Simulation time 193850462 ps
CPU time 0.82 seconds
Started Jun 10 05:27:31 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 205004 kb
Host smart-226f5bb2-3659-4175-bac0-151040cd07e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40557
39721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.4055739721
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1148716306
Short name T332
Test name
Test status
Simulation time 215386277 ps
CPU time 0.93 seconds
Started Jun 10 05:27:27 PM PDT 24
Finished Jun 10 05:27:29 PM PDT 24
Peak memory 205016 kb
Host smart-0b48d43b-0723-47a9-92f9-2f457349be04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11487
16306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1148716306
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1272767750
Short name T1926
Test name
Test status
Simulation time 212997178 ps
CPU time 0.86 seconds
Started Jun 10 05:26:59 PM PDT 24
Finished Jun 10 05:27:00 PM PDT 24
Peak memory 205004 kb
Host smart-8cd9d6e0-1da3-4d14-afc4-35cacd24ec1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12727
67750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1272767750
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.2610988116
Short name T163
Test name
Test status
Simulation time 3321554286 ps
CPU time 3.63 seconds
Started Jun 10 05:27:10 PM PDT 24
Finished Jun 10 05:27:14 PM PDT 24
Peak memory 205072 kb
Host smart-51328882-163f-4f01-bc36-9dbff5ce490c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26109
88116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.2610988116
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3151976392
Short name T394
Test name
Test status
Simulation time 197657116 ps
CPU time 0.88 seconds
Started Jun 10 05:27:20 PM PDT 24
Finished Jun 10 05:27:21 PM PDT 24
Peak memory 204960 kb
Host smart-f78cb7e0-a794-49cf-a8cc-d3ddf4893481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31519
76392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3151976392
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.681915091
Short name T426
Test name
Test status
Simulation time 10349654966 ps
CPU time 95.71 seconds
Started Jun 10 05:27:06 PM PDT 24
Finished Jun 10 05:28:42 PM PDT 24
Peak memory 205268 kb
Host smart-e4c30a4d-21a5-4575-86d5-2d1f732cc69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68191
5091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.681915091
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3052506334
Short name T855
Test name
Test status
Simulation time 154477616 ps
CPU time 0.8 seconds
Started Jun 10 05:27:00 PM PDT 24
Finished Jun 10 05:27:01 PM PDT 24
Peak memory 205056 kb
Host smart-efe9076b-b678-4ad1-a52f-349666ccf490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30525
06334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3052506334
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.743520838
Short name T135
Test name
Test status
Simulation time 215385610 ps
CPU time 0.85 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:30 PM PDT 24
Peak memory 204996 kb
Host smart-5b3a0091-1eca-423f-81ae-3dcef3b89fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74352
0838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.743520838
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3035396978
Short name T908
Test name
Test status
Simulation time 200768968 ps
CPU time 0.83 seconds
Started Jun 10 05:27:26 PM PDT 24
Finished Jun 10 05:27:27 PM PDT 24
Peak memory 205040 kb
Host smart-23b05769-d10a-4570-ae36-119a98892628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30353
96978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3035396978
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2838060509
Short name T1520
Test name
Test status
Simulation time 152536050 ps
CPU time 0.82 seconds
Started Jun 10 05:27:07 PM PDT 24
Finished Jun 10 05:27:08 PM PDT 24
Peak memory 204968 kb
Host smart-29fab4f1-51b7-4736-af86-8d0abdeae8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28380
60509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2838060509
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1165273859
Short name T838
Test name
Test status
Simulation time 191552976 ps
CPU time 0.84 seconds
Started Jun 10 05:27:05 PM PDT 24
Finished Jun 10 05:27:07 PM PDT 24
Peak memory 205012 kb
Host smart-169e12a1-3b59-4a82-ba13-78d292835456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11652
73859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1165273859
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.4196848812
Short name T681
Test name
Test status
Simulation time 166025583 ps
CPU time 0.79 seconds
Started Jun 10 05:27:05 PM PDT 24
Finished Jun 10 05:27:06 PM PDT 24
Peak memory 204984 kb
Host smart-9afce3e1-3bee-46cb-8f18-9e9f7e29fe41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41968
48812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.4196848812
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_eop_single_bit_handling.2855821321
Short name T1609
Test name
Test status
Simulation time 173043110 ps
CPU time 0.79 seconds
Started Jun 10 05:27:18 PM PDT 24
Finished Jun 10 05:27:20 PM PDT 24
Peak memory 205032 kb
Host smart-542cb831-9584-48ac-af41-5f255724deb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28558
21321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_eop_single_bit_handling.2855821321
Directory /workspace/30.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1020990531
Short name T523
Test name
Test status
Simulation time 159950603 ps
CPU time 0.81 seconds
Started Jun 10 05:27:23 PM PDT 24
Finished Jun 10 05:27:24 PM PDT 24
Peak memory 205020 kb
Host smart-709357c0-4c95-460c-a3ab-b5d2489b9408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10209
90531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1020990531
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.732814362
Short name T1107
Test name
Test status
Simulation time 62228937 ps
CPU time 0.66 seconds
Started Jun 10 05:27:28 PM PDT 24
Finished Jun 10 05:27:29 PM PDT 24
Peak memory 204972 kb
Host smart-6d94582a-311b-4841-bc86-2b525f8fa144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73281
4362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.732814362
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.199857620
Short name T204
Test name
Test status
Simulation time 10006604100 ps
CPU time 24.73 seconds
Started Jun 10 05:27:04 PM PDT 24
Finished Jun 10 05:27:29 PM PDT 24
Peak memory 205184 kb
Host smart-dc8d0b9b-ec0c-4435-ad10-e9ddc76fa4a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19985
7620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.199857620
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2912131198
Short name T1766
Test name
Test status
Simulation time 184313098 ps
CPU time 0.83 seconds
Started Jun 10 05:27:05 PM PDT 24
Finished Jun 10 05:27:06 PM PDT 24
Peak memory 204944 kb
Host smart-4c37323d-06cf-47b4-8ec6-3beee012f267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29121
31198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2912131198
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.361120685
Short name T1568
Test name
Test status
Simulation time 227594232 ps
CPU time 0.94 seconds
Started Jun 10 05:27:06 PM PDT 24
Finished Jun 10 05:27:07 PM PDT 24
Peak memory 204996 kb
Host smart-750c558f-c55d-4d07-bc4f-ff935d84209c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36112
0685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.361120685
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.49331855
Short name T1393
Test name
Test status
Simulation time 158059086 ps
CPU time 0.78 seconds
Started Jun 10 05:27:31 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 205040 kb
Host smart-533e14c1-76d1-4f39-abad-9bb8afcebae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49331
855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.49331855
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2741617381
Short name T1701
Test name
Test status
Simulation time 225476037 ps
CPU time 0.81 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:30 PM PDT 24
Peak memory 204884 kb
Host smart-0912979c-6a49-44b3-bb61-d55f77816576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27416
17381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2741617381
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.999431850
Short name T1689
Test name
Test status
Simulation time 169542280 ps
CPU time 0.86 seconds
Started Jun 10 05:27:08 PM PDT 24
Finished Jun 10 05:27:09 PM PDT 24
Peak memory 204932 kb
Host smart-b55f4f0d-28e6-4fb1-88b1-ce46c67a8a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99943
1850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.999431850
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2206616505
Short name T1108
Test name
Test status
Simulation time 154678175 ps
CPU time 0.83 seconds
Started Jun 10 05:27:08 PM PDT 24
Finished Jun 10 05:27:09 PM PDT 24
Peak memory 205012 kb
Host smart-e5c22a91-91b1-4d31-8472-304ad5fccb8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22066
16505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2206616505
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.515067872
Short name T1482
Test name
Test status
Simulation time 211886412 ps
CPU time 0.92 seconds
Started Jun 10 05:27:16 PM PDT 24
Finished Jun 10 05:27:18 PM PDT 24
Peak memory 205036 kb
Host smart-6923850b-37a6-4bc7-8fc5-cf7adf55e755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51506
7872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.515067872
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2145516815
Short name T1652
Test name
Test status
Simulation time 175303155 ps
CPU time 0.81 seconds
Started Jun 10 05:27:30 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 205040 kb
Host smart-79c236bf-4283-434b-a384-e96ba792bd97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21455
16815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2145516815
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.571347234
Short name T2037
Test name
Test status
Simulation time 185830095 ps
CPU time 0.89 seconds
Started Jun 10 05:27:32 PM PDT 24
Finished Jun 10 05:27:33 PM PDT 24
Peak memory 204920 kb
Host smart-ee733474-8ff3-4276-a4d9-804b52210a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57134
7234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.571347234
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.1504105625
Short name T1363
Test name
Test status
Simulation time 6887123068 ps
CPU time 197.18 seconds
Started Jun 10 05:27:18 PM PDT 24
Finished Jun 10 05:30:35 PM PDT 24
Peak memory 205212 kb
Host smart-691d0cf8-f81c-4413-9935-8e5417624564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15041
05625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.1504105625
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.3727800596
Short name T1683
Test name
Test status
Simulation time 307676690 ps
CPU time 0.96 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:30 PM PDT 24
Peak memory 205020 kb
Host smart-c664450f-3521-4764-922e-bea91b01f736
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3727800596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.3727800596
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.3320830529
Short name T1630
Test name
Test status
Simulation time 164578080 ps
CPU time 0.78 seconds
Started Jun 10 05:27:15 PM PDT 24
Finished Jun 10 05:27:17 PM PDT 24
Peak memory 205036 kb
Host smart-231c9cb3-f3e1-4a12-b724-c562629a82cd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3320830529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.3320830529
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.1253682289
Short name T549
Test name
Test status
Simulation time 220152913 ps
CPU time 0.91 seconds
Started Jun 10 05:27:37 PM PDT 24
Finished Jun 10 05:27:44 PM PDT 24
Peak memory 205004 kb
Host smart-827b0221-5883-419b-84ab-6398f8b39d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12536
82289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.1253682289
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3289494342
Short name T916
Test name
Test status
Simulation time 3756884509 ps
CPU time 4.83 seconds
Started Jun 10 05:27:12 PM PDT 24
Finished Jun 10 05:27:17 PM PDT 24
Peak memory 205100 kb
Host smart-8f8e1c41-fea0-4dec-8ac6-e2fc7fdfb7de
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3289494342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3289494342
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.553565091
Short name T1855
Test name
Test status
Simulation time 13553408464 ps
CPU time 12.64 seconds
Started Jun 10 05:27:34 PM PDT 24
Finished Jun 10 05:27:47 PM PDT 24
Peak memory 204976 kb
Host smart-df50f66a-9cd6-485d-bef7-c6baa7314c69
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=553565091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.553565091
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.2054804276
Short name T775
Test name
Test status
Simulation time 23356262028 ps
CPU time 24.36 seconds
Started Jun 10 05:27:21 PM PDT 24
Finished Jun 10 05:27:46 PM PDT 24
Peak memory 205176 kb
Host smart-f22c4d9c-3b67-4a08-9556-b0b1ad8707c5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2054804276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.2054804276
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.4208757265
Short name T1574
Test name
Test status
Simulation time 148395715 ps
CPU time 0.82 seconds
Started Jun 10 05:27:12 PM PDT 24
Finished Jun 10 05:27:13 PM PDT 24
Peak memory 205008 kb
Host smart-876a8fac-9f9e-4436-811f-b35819a1d9a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42087
57265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.4208757265
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1202767305
Short name T1539
Test name
Test status
Simulation time 146295642 ps
CPU time 0.78 seconds
Started Jun 10 05:27:09 PM PDT 24
Finished Jun 10 05:27:10 PM PDT 24
Peak memory 205008 kb
Host smart-66821f35-7e28-4ecf-990a-ec5fa004034a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12027
67305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1202767305
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3228578639
Short name T1948
Test name
Test status
Simulation time 682443758 ps
CPU time 1.74 seconds
Started Jun 10 05:27:23 PM PDT 24
Finished Jun 10 05:27:26 PM PDT 24
Peak memory 204972 kb
Host smart-796576c7-f198-4f23-8ad3-4db5f6624d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32285
78639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3228578639
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.3883293343
Short name T635
Test name
Test status
Simulation time 148375298 ps
CPU time 0.75 seconds
Started Jun 10 05:27:42 PM PDT 24
Finished Jun 10 05:27:43 PM PDT 24
Peak memory 204888 kb
Host smart-50a0e5cd-f233-40ff-8ce4-09f58c6f36be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38832
93343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3883293343
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.4011838256
Short name T232
Test name
Test status
Simulation time 50512542 ps
CPU time 0.68 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:31 PM PDT 24
Peak memory 204880 kb
Host smart-264471df-7ba1-4c68-8528-584c0945a44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40118
38256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.4011838256
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3169028265
Short name T1442
Test name
Test status
Simulation time 1009368124 ps
CPU time 2.37 seconds
Started Jun 10 05:27:10 PM PDT 24
Finished Jun 10 05:27:13 PM PDT 24
Peak memory 205080 kb
Host smart-3019606e-89e9-44fd-bdc8-e733c069d6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31690
28265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3169028265
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.480964071
Short name T1060
Test name
Test status
Simulation time 297834100 ps
CPU time 2.2 seconds
Started Jun 10 05:27:35 PM PDT 24
Finished Jun 10 05:27:38 PM PDT 24
Peak memory 204964 kb
Host smart-5006f000-bb6b-42f4-8c9f-d6a5ae01fc43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48096
4071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.480964071
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.1121910909
Short name T1049
Test name
Test status
Simulation time 289986334 ps
CPU time 1 seconds
Started Jun 10 05:27:27 PM PDT 24
Finished Jun 10 05:27:29 PM PDT 24
Peak memory 205020 kb
Host smart-c2c7b61d-488b-4382-bda9-38205b647c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11219
10909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.1121910909
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1748015798
Short name T1541
Test name
Test status
Simulation time 147416122 ps
CPU time 0.78 seconds
Started Jun 10 05:27:17 PM PDT 24
Finished Jun 10 05:27:18 PM PDT 24
Peak memory 204968 kb
Host smart-494b82b5-9a55-40f2-9c84-d1d4bde277d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17480
15798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1748015798
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.4044774425
Short name T688
Test name
Test status
Simulation time 162205417 ps
CPU time 0.81 seconds
Started Jun 10 05:27:10 PM PDT 24
Finished Jun 10 05:27:11 PM PDT 24
Peak memory 204996 kb
Host smart-5077497b-d9da-4a80-a45a-e3d937d03b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40447
74425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.4044774425
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.2134934124
Short name T656
Test name
Test status
Simulation time 226762990 ps
CPU time 0.92 seconds
Started Jun 10 05:27:09 PM PDT 24
Finished Jun 10 05:27:11 PM PDT 24
Peak memory 205000 kb
Host smart-b59f341e-77d5-4234-b05b-25c68e87274f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21349
34124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.2134934124
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2685347101
Short name T304
Test name
Test status
Simulation time 3304139715 ps
CPU time 4.06 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:34 PM PDT 24
Peak memory 205072 kb
Host smart-45e1f595-5ce4-4400-8449-4320171c82c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26853
47101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2685347101
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2827090203
Short name T607
Test name
Test status
Simulation time 211676039 ps
CPU time 0.96 seconds
Started Jun 10 05:27:30 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 204852 kb
Host smart-31b28f8c-6ff8-4765-9b81-73a44ad3f6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28270
90203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2827090203
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.1832473036
Short name T1527
Test name
Test status
Simulation time 4277162744 ps
CPU time 120.32 seconds
Started Jun 10 05:27:11 PM PDT 24
Finished Jun 10 05:29:11 PM PDT 24
Peak memory 205172 kb
Host smart-51f91aab-bd48-4596-a94d-cb829a7ffa06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18324
73036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.1832473036
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.4107019485
Short name T932
Test name
Test status
Simulation time 184877121 ps
CPU time 0.86 seconds
Started Jun 10 05:27:12 PM PDT 24
Finished Jun 10 05:27:13 PM PDT 24
Peak memory 205044 kb
Host smart-c3f987ea-cabb-4498-a7fb-835826311f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41070
19485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.4107019485
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.3333893006
Short name T2023
Test name
Test status
Simulation time 212310448 ps
CPU time 0.89 seconds
Started Jun 10 05:27:31 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 205000 kb
Host smart-949f1bc0-9c0f-4a00-a7b7-3db548f15a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33338
93006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.3333893006
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3600828722
Short name T1281
Test name
Test status
Simulation time 171588176 ps
CPU time 0.85 seconds
Started Jun 10 05:27:07 PM PDT 24
Finished Jun 10 05:27:08 PM PDT 24
Peak memory 204968 kb
Host smart-c27b89b7-454a-4c79-b596-e1cf8c74ddd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36008
28722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3600828722
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.4050533223
Short name T128
Test name
Test status
Simulation time 146488281 ps
CPU time 0.77 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:30 PM PDT 24
Peak memory 204884 kb
Host smart-20286a19-85ff-4261-a3c8-7611851959f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40505
33223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.4050533223
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1528307392
Short name T816
Test name
Test status
Simulation time 236840159 ps
CPU time 0.92 seconds
Started Jun 10 05:27:09 PM PDT 24
Finished Jun 10 05:27:10 PM PDT 24
Peak memory 205004 kb
Host smart-2394b7b8-22d1-40d1-80b0-74cdb7b50689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15283
07392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1528307392
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.789690272
Short name T835
Test name
Test status
Simulation time 192424024 ps
CPU time 0.81 seconds
Started Jun 10 05:27:27 PM PDT 24
Finished Jun 10 05:27:28 PM PDT 24
Peak memory 205080 kb
Host smart-41212201-e4c9-4351-8bc8-dc081250cbd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78969
0272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.789690272
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_eop_single_bit_handling.2381436282
Short name T811
Test name
Test status
Simulation time 179629807 ps
CPU time 0.85 seconds
Started Jun 10 05:27:13 PM PDT 24
Finished Jun 10 05:27:14 PM PDT 24
Peak memory 205032 kb
Host smart-95ebb427-72a2-4c1c-afe4-14f5456bbddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23814
36282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_eop_single_bit_handling.2381436282
Directory /workspace/31.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3989979170
Short name T619
Test name
Test status
Simulation time 141323807 ps
CPU time 0.79 seconds
Started Jun 10 05:27:33 PM PDT 24
Finished Jun 10 05:27:34 PM PDT 24
Peak memory 205036 kb
Host smart-61354784-513d-4ec5-a2fc-fb1eebc59cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39899
79170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3989979170
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2426991242
Short name T1867
Test name
Test status
Simulation time 48775428 ps
CPU time 0.69 seconds
Started Jun 10 05:27:13 PM PDT 24
Finished Jun 10 05:27:14 PM PDT 24
Peak memory 204908 kb
Host smart-f218b33b-9d9f-4018-98d8-0181e39c955b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24269
91242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2426991242
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.3147052972
Short name T242
Test name
Test status
Simulation time 11951892436 ps
CPU time 27.69 seconds
Started Jun 10 05:27:27 PM PDT 24
Finished Jun 10 05:27:55 PM PDT 24
Peak memory 205240 kb
Host smart-d7f6004e-b906-4531-ae76-a7fb336bd05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31470
52972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.3147052972
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.826445906
Short name T1975
Test name
Test status
Simulation time 166356108 ps
CPU time 0.81 seconds
Started Jun 10 05:27:28 PM PDT 24
Finished Jun 10 05:27:30 PM PDT 24
Peak memory 205004 kb
Host smart-d0dd7609-1b3b-4319-9803-4f25cacc3ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82644
5906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.826445906
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2060059443
Short name T1791
Test name
Test status
Simulation time 166105216 ps
CPU time 0.78 seconds
Started Jun 10 05:27:32 PM PDT 24
Finished Jun 10 05:27:33 PM PDT 24
Peak memory 204880 kb
Host smart-45ceb94c-9546-46d6-b66d-10eb9585b7b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20600
59443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2060059443
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.3831340968
Short name T1634
Test name
Test status
Simulation time 183877221 ps
CPU time 0.82 seconds
Started Jun 10 05:27:35 PM PDT 24
Finished Jun 10 05:27:37 PM PDT 24
Peak memory 204812 kb
Host smart-3afa0e8d-de0e-478c-be22-15932aa77c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38313
40968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.3831340968
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.636624271
Short name T1647
Test name
Test status
Simulation time 139691246 ps
CPU time 0.76 seconds
Started Jun 10 05:27:27 PM PDT 24
Finished Jun 10 05:27:28 PM PDT 24
Peak memory 204888 kb
Host smart-7441594d-41d3-40fb-a919-ca27f3fdbc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63662
4271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.636624271
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.793072786
Short name T1336
Test name
Test status
Simulation time 145507829 ps
CPU time 0.76 seconds
Started Jun 10 05:27:28 PM PDT 24
Finished Jun 10 05:27:29 PM PDT 24
Peak memory 205020 kb
Host smart-694a8cf5-3e82-4e98-b8eb-1f3ea45ff05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79307
2786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.793072786
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3407672529
Short name T1932
Test name
Test status
Simulation time 161610612 ps
CPU time 0.79 seconds
Started Jun 10 05:27:28 PM PDT 24
Finished Jun 10 05:27:29 PM PDT 24
Peak memory 205096 kb
Host smart-6915d8a3-c768-41eb-bd81-62ab59c47d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34076
72529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3407672529
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3494816308
Short name T1868
Test name
Test status
Simulation time 231889459 ps
CPU time 0.99 seconds
Started Jun 10 05:27:38 PM PDT 24
Finished Jun 10 05:27:39 PM PDT 24
Peak memory 204984 kb
Host smart-ba0afcb2-3c00-4f18-98c6-4d40f9dd9e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34948
16308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3494816308
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.2361437368
Short name T563
Test name
Test status
Simulation time 188447920 ps
CPU time 0.84 seconds
Started Jun 10 05:27:12 PM PDT 24
Finished Jun 10 05:27:13 PM PDT 24
Peak memory 205044 kb
Host smart-523212bf-dbac-417b-92d8-e566cea66f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23614
37368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.2361437368
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.3669242409
Short name T1229
Test name
Test status
Simulation time 167900266 ps
CPU time 0.82 seconds
Started Jun 10 05:27:12 PM PDT 24
Finished Jun 10 05:27:13 PM PDT 24
Peak memory 205008 kb
Host smart-98a687fa-765f-43f9-905a-cc39eaa31d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36692
42409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3669242409
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1546527583
Short name T1883
Test name
Test status
Simulation time 14410948232 ps
CPU time 415.75 seconds
Started Jun 10 05:27:40 PM PDT 24
Finished Jun 10 05:34:36 PM PDT 24
Peak memory 205080 kb
Host smart-367a89c8-da3d-4c0d-b135-2064ec4cd0ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15465
27583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1546527583
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.1985440726
Short name T1984
Test name
Test status
Simulation time 250746184 ps
CPU time 0.94 seconds
Started Jun 10 05:27:16 PM PDT 24
Finished Jun 10 05:27:17 PM PDT 24
Peak memory 205008 kb
Host smart-377927c3-eff3-4c79-b343-b58d13f1da9d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1985440726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.1985440726
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.897948595
Short name T1037
Test name
Test status
Simulation time 219140525 ps
CPU time 0.84 seconds
Started Jun 10 05:27:27 PM PDT 24
Finished Jun 10 05:27:28 PM PDT 24
Peak memory 204820 kb
Host smart-1ea6d53d-d252-4355-b9a7-2b7e47a21795
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=897948595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.897948595
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.1295714495
Short name T443
Test name
Test status
Simulation time 219393224 ps
CPU time 0.9 seconds
Started Jun 10 05:27:47 PM PDT 24
Finished Jun 10 05:27:48 PM PDT 24
Peak memory 204812 kb
Host smart-d9461ca2-d812-4700-9584-b85bee7714aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12957
14495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.1295714495
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3872720816
Short name T1008
Test name
Test status
Simulation time 4140491828 ps
CPU time 5.51 seconds
Started Jun 10 05:27:35 PM PDT 24
Finished Jun 10 05:27:41 PM PDT 24
Peak memory 205152 kb
Host smart-e54fce76-08f0-4354-a4cd-2a4692c6f4f6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3872720816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.3872720816
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3860310830
Short name T479
Test name
Test status
Simulation time 13317051306 ps
CPU time 12.7 seconds
Started Jun 10 05:27:10 PM PDT 24
Finished Jun 10 05:27:23 PM PDT 24
Peak memory 205044 kb
Host smart-b9f54d26-a18b-43bc-ac4f-a8b3e041ad0f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3860310830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3860310830
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.4080361940
Short name T862
Test name
Test status
Simulation time 23370741922 ps
CPU time 31.25 seconds
Started Jun 10 05:27:21 PM PDT 24
Finished Jun 10 05:27:53 PM PDT 24
Peak memory 205104 kb
Host smart-deb11fe4-634c-4f65-9182-1acf11fd0c15
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4080361940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.4080361940
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3085287794
Short name T357
Test name
Test status
Simulation time 210541797 ps
CPU time 0.84 seconds
Started Jun 10 05:27:16 PM PDT 24
Finished Jun 10 05:27:18 PM PDT 24
Peak memory 204988 kb
Host smart-d19be0f4-5e2a-4c0c-8285-153289821835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30852
87794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3085287794
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.1204540750
Short name T1793
Test name
Test status
Simulation time 161762409 ps
CPU time 0.82 seconds
Started Jun 10 05:27:06 PM PDT 24
Finished Jun 10 05:27:07 PM PDT 24
Peak memory 204980 kb
Host smart-58641276-9f75-44ba-9496-380559546e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12045
40750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.1204540750
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3385137390
Short name T1267
Test name
Test status
Simulation time 1020428287 ps
CPU time 2.58 seconds
Started Jun 10 05:27:17 PM PDT 24
Finished Jun 10 05:27:20 PM PDT 24
Peak memory 205120 kb
Host smart-983efad5-d580-448f-85b9-8e8eea90358e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33851
37390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3385137390
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.111759311
Short name T317
Test name
Test status
Simulation time 144719791 ps
CPU time 0.79 seconds
Started Jun 10 05:27:16 PM PDT 24
Finished Jun 10 05:27:17 PM PDT 24
Peak memory 205028 kb
Host smart-16e608da-677b-456f-8a4b-63194b030774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11175
9311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.111759311
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2018317464
Short name T1265
Test name
Test status
Simulation time 97166161 ps
CPU time 0.7 seconds
Started Jun 10 05:27:17 PM PDT 24
Finished Jun 10 05:27:19 PM PDT 24
Peak memory 204984 kb
Host smart-180f2a93-65a5-4dc1-ac4b-ab95feb5993a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20183
17464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2018317464
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3430526563
Short name T325
Test name
Test status
Simulation time 916679354 ps
CPU time 2.35 seconds
Started Jun 10 05:27:11 PM PDT 24
Finished Jun 10 05:27:14 PM PDT 24
Peak memory 205212 kb
Host smart-4a940c89-7782-4b6d-a87d-e0c36ddee170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34305
26563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3430526563
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1990718068
Short name T96
Test name
Test status
Simulation time 200791712 ps
CPU time 1.89 seconds
Started Jun 10 05:27:28 PM PDT 24
Finished Jun 10 05:27:30 PM PDT 24
Peak memory 205080 kb
Host smart-03386792-3eb5-444d-a9f3-6cfd7d2d70b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19907
18068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1990718068
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.2331380570
Short name T962
Test name
Test status
Simulation time 221812300 ps
CPU time 0.88 seconds
Started Jun 10 05:27:16 PM PDT 24
Finished Jun 10 05:27:17 PM PDT 24
Peak memory 205016 kb
Host smart-d907aa19-2b1b-4582-ab0b-d14ccd079234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23313
80570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2331380570
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1500847937
Short name T919
Test name
Test status
Simulation time 137093434 ps
CPU time 0.76 seconds
Started Jun 10 05:27:25 PM PDT 24
Finished Jun 10 05:27:26 PM PDT 24
Peak memory 205016 kb
Host smart-0ff68fe0-4307-4384-8acd-711d14058bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15008
47937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1500847937
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.4288350036
Short name T1986
Test name
Test status
Simulation time 205753977 ps
CPU time 0.88 seconds
Started Jun 10 05:27:31 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 205000 kb
Host smart-082da3d8-469c-42f9-a65d-517a1e53a255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42883
50036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.4288350036
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2206129443
Short name T1086
Test name
Test status
Simulation time 249821954 ps
CPU time 0.89 seconds
Started Jun 10 05:27:30 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 205016 kb
Host smart-4ff0aa7d-ec38-41bc-94aa-a7f2a59e66e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22061
29443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2206129443
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.913836951
Short name T1177
Test name
Test status
Simulation time 3276788438 ps
CPU time 4.59 seconds
Started Jun 10 05:27:27 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 205088 kb
Host smart-49186ca0-e8c1-42b1-8c63-e78fac855e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91383
6951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.913836951
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.983255133
Short name T1522
Test name
Test status
Simulation time 195985602 ps
CPU time 0.86 seconds
Started Jun 10 05:27:11 PM PDT 24
Finished Jun 10 05:27:12 PM PDT 24
Peak memory 204932 kb
Host smart-9dc70696-b3b3-4b07-964e-faaa739f8711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98325
5133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.983255133
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.1164825612
Short name T1740
Test name
Test status
Simulation time 12360412940 ps
CPU time 351.61 seconds
Started Jun 10 05:27:27 PM PDT 24
Finished Jun 10 05:33:20 PM PDT 24
Peak memory 205236 kb
Host smart-8fb91202-d98e-442c-ab39-4b6f562bf53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11648
25612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.1164825612
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.127325892
Short name T587
Test name
Test status
Simulation time 161427653 ps
CPU time 0.78 seconds
Started Jun 10 05:27:16 PM PDT 24
Finished Jun 10 05:27:18 PM PDT 24
Peak memory 205052 kb
Host smart-006d70a1-cb79-46d0-a149-768bc7dd5ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12732
5892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.127325892
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3049745305
Short name T142
Test name
Test status
Simulation time 191963899 ps
CPU time 0.83 seconds
Started Jun 10 05:27:07 PM PDT 24
Finished Jun 10 05:27:08 PM PDT 24
Peak memory 205076 kb
Host smart-1f0aecfe-9cc0-4c77-b3e9-940482b242b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30497
45305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3049745305
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3797446526
Short name T2101
Test name
Test status
Simulation time 228349645 ps
CPU time 0.86 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:30 PM PDT 24
Peak memory 205004 kb
Host smart-3d9119cc-3fe3-40f4-9385-b258cc3decc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37974
46526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3797446526
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3351973468
Short name T1467
Test name
Test status
Simulation time 195041971 ps
CPU time 0.82 seconds
Started Jun 10 05:27:31 PM PDT 24
Finished Jun 10 05:27:40 PM PDT 24
Peak memory 204964 kb
Host smart-80b00289-3d34-4931-bd19-6fb5f181dcf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33519
73468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3351973468
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2915435936
Short name T1741
Test name
Test status
Simulation time 163875643 ps
CPU time 0.8 seconds
Started Jun 10 05:27:11 PM PDT 24
Finished Jun 10 05:27:12 PM PDT 24
Peak memory 204960 kb
Host smart-4f7fcfa2-7a27-4659-8dd3-d0662cc1fb34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29154
35936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2915435936
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_eop_single_bit_handling.2023898317
Short name T658
Test name
Test status
Simulation time 174703269 ps
CPU time 0.82 seconds
Started Jun 10 05:27:26 PM PDT 24
Finished Jun 10 05:27:27 PM PDT 24
Peak memory 205040 kb
Host smart-2c6d008a-6e5b-4171-9006-b1c514142a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20238
98317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_eop_single_bit_handling.2023898317
Directory /workspace/32.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.4114768767
Short name T1857
Test name
Test status
Simulation time 228769477 ps
CPU time 0.83 seconds
Started Jun 10 05:27:11 PM PDT 24
Finished Jun 10 05:27:13 PM PDT 24
Peak memory 204932 kb
Host smart-c91a5ff0-80ae-4611-957e-0b348e33c7a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41147
68767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.4114768767
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.769591896
Short name T1547
Test name
Test status
Simulation time 47535968 ps
CPU time 0.66 seconds
Started Jun 10 05:27:12 PM PDT 24
Finished Jun 10 05:27:13 PM PDT 24
Peak memory 205016 kb
Host smart-0b947518-089f-484f-b4ed-e98bd790a21d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76959
1896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.769591896
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.4207267356
Short name T91
Test name
Test status
Simulation time 10094603457 ps
CPU time 25.61 seconds
Started Jun 10 05:27:12 PM PDT 24
Finished Jun 10 05:27:38 PM PDT 24
Peak memory 205284 kb
Host smart-51ac6bb0-9f6c-4be0-865c-f11b876787bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42072
67356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.4207267356
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1777011641
Short name T1800
Test name
Test status
Simulation time 199891955 ps
CPU time 0.87 seconds
Started Jun 10 05:27:10 PM PDT 24
Finished Jun 10 05:27:11 PM PDT 24
Peak memory 205004 kb
Host smart-e223079e-3c4f-40ba-bf5c-c355a01af17d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17770
11641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1777011641
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.486740276
Short name T1124
Test name
Test status
Simulation time 201473129 ps
CPU time 0.86 seconds
Started Jun 10 05:27:10 PM PDT 24
Finished Jun 10 05:27:11 PM PDT 24
Peak memory 204972 kb
Host smart-e7889925-0a22-4328-8aba-74997f79f632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48674
0276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.486740276
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.2785922742
Short name T329
Test name
Test status
Simulation time 184613809 ps
CPU time 0.81 seconds
Started Jun 10 05:27:12 PM PDT 24
Finished Jun 10 05:27:13 PM PDT 24
Peak memory 205020 kb
Host smart-a44c38f6-6565-48c2-bbda-f10af163754e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27859
22742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.2785922742
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.2585602097
Short name T1919
Test name
Test status
Simulation time 134669167 ps
CPU time 0.74 seconds
Started Jun 10 05:27:17 PM PDT 24
Finished Jun 10 05:27:18 PM PDT 24
Peak memory 205016 kb
Host smart-db876186-a651-4274-806e-77c6fb32db90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25856
02097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.2585602097
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.3746202442
Short name T182
Test name
Test status
Simulation time 156842527 ps
CPU time 0.77 seconds
Started Jun 10 05:27:38 PM PDT 24
Finished Jun 10 05:27:39 PM PDT 24
Peak memory 204992 kb
Host smart-4aa51d27-e14d-4cf9-b705-000184cccdd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37462
02442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.3746202442
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3550592819
Short name T333
Test name
Test status
Simulation time 147840800 ps
CPU time 0.76 seconds
Started Jun 10 05:27:26 PM PDT 24
Finished Jun 10 05:27:27 PM PDT 24
Peak memory 205012 kb
Host smart-88f915a6-d7a5-4d54-a372-ac26073d0719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35505
92819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3550592819
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.952274204
Short name T1296
Test name
Test status
Simulation time 229553109 ps
CPU time 0.95 seconds
Started Jun 10 05:27:45 PM PDT 24
Finished Jun 10 05:27:46 PM PDT 24
Peak memory 204988 kb
Host smart-0f3d4af4-3c3a-4d1c-a3c6-4a4494cf8054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95227
4204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.952274204
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3332891853
Short name T1983
Test name
Test status
Simulation time 169531058 ps
CPU time 0.78 seconds
Started Jun 10 05:27:31 PM PDT 24
Finished Jun 10 05:27:33 PM PDT 24
Peak memory 205048 kb
Host smart-e9626a20-25d4-4b6b-a8c2-bff6f14e3ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33328
91853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3332891853
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.3188417003
Short name T649
Test name
Test status
Simulation time 171481154 ps
CPU time 0.84 seconds
Started Jun 10 05:27:27 PM PDT 24
Finished Jun 10 05:27:28 PM PDT 24
Peak memory 204812 kb
Host smart-07a88865-e3d7-4689-a484-52421f0d4682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31884
17003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3188417003
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.641281939
Short name T512
Test name
Test status
Simulation time 15105761317 ps
CPU time 141.97 seconds
Started Jun 10 05:27:50 PM PDT 24
Finished Jun 10 05:30:12 PM PDT 24
Peak memory 204980 kb
Host smart-d9532024-ce6b-4f7c-9dd4-fbd2fd196eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64128
1939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.641281939
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.1106929697
Short name T1390
Test name
Test status
Simulation time 252923525 ps
CPU time 0.91 seconds
Started Jun 10 05:27:37 PM PDT 24
Finished Jun 10 05:27:41 PM PDT 24
Peak memory 205020 kb
Host smart-b694b194-05eb-4998-b145-da7c2567f9fd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1106929697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.1106929697
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.4124204294
Short name T1284
Test name
Test status
Simulation time 158340131 ps
CPU time 0.84 seconds
Started Jun 10 05:27:19 PM PDT 24
Finished Jun 10 05:27:20 PM PDT 24
Peak memory 205064 kb
Host smart-6febf0b9-e854-493f-b4ab-77da184d2bd7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4124204294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.4124204294
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.2046240039
Short name T503
Test name
Test status
Simulation time 262420058 ps
CPU time 0.89 seconds
Started Jun 10 05:27:31 PM PDT 24
Finished Jun 10 05:27:33 PM PDT 24
Peak memory 205012 kb
Host smart-b6170903-fd5d-40de-871a-b9affb72c42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20462
40039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.2046240039
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.2690236529
Short name T1730
Test name
Test status
Simulation time 3863989387 ps
CPU time 4.62 seconds
Started Jun 10 05:27:26 PM PDT 24
Finished Jun 10 05:27:31 PM PDT 24
Peak memory 205228 kb
Host smart-ef6b9f38-09f1-40a9-af56-723412fa6a44
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2690236529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.2690236529
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.750769871
Short name T1844
Test name
Test status
Simulation time 13302227646 ps
CPU time 12.14 seconds
Started Jun 10 05:27:34 PM PDT 24
Finished Jun 10 05:27:47 PM PDT 24
Peak memory 204964 kb
Host smart-a54e9fc5-8912-4a0c-a90a-c2c16cdfa812
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=750769871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.750769871
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1104704574
Short name T390
Test name
Test status
Simulation time 23421090381 ps
CPU time 23.45 seconds
Started Jun 10 05:27:37 PM PDT 24
Finished Jun 10 05:28:01 PM PDT 24
Peak memory 205080 kb
Host smart-6c2ddcfb-c9b9-4984-b98d-17d2f059dd12
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1104704574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.1104704574
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.2729964851
Short name T1715
Test name
Test status
Simulation time 151285474 ps
CPU time 0.79 seconds
Started Jun 10 05:27:46 PM PDT 24
Finished Jun 10 05:27:47 PM PDT 24
Peak memory 205052 kb
Host smart-c057fae0-f543-4e61-b434-56ca24723367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27299
64851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.2729964851
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2156182133
Short name T1339
Test name
Test status
Simulation time 174963424 ps
CPU time 0.78 seconds
Started Jun 10 05:27:39 PM PDT 24
Finished Jun 10 05:27:40 PM PDT 24
Peak memory 204816 kb
Host smart-02860d99-f6af-48ff-943a-ac29a3223293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21561
82133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2156182133
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.902978402
Short name T198
Test name
Test status
Simulation time 1091199873 ps
CPU time 2.45 seconds
Started Jun 10 05:27:13 PM PDT 24
Finished Jun 10 05:27:16 PM PDT 24
Peak memory 205172 kb
Host smart-5dfb146a-66b0-4b62-afb7-3c1d2c1b7a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90297
8402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.902978402
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2344042489
Short name T1136
Test name
Test status
Simulation time 158007199 ps
CPU time 0.82 seconds
Started Jun 10 05:27:15 PM PDT 24
Finished Jun 10 05:27:17 PM PDT 24
Peak memory 205028 kb
Host smart-29133154-a1e3-4650-bff1-f7b0a060cfd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23440
42489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2344042489
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.1274028475
Short name T2022
Test name
Test status
Simulation time 35219607 ps
CPU time 0.66 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:30 PM PDT 24
Peak memory 204840 kb
Host smart-53bf2771-a197-4db7-9cbb-89f175751ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12740
28475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1274028475
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.4102773111
Short name T1093
Test name
Test status
Simulation time 973066250 ps
CPU time 2.31 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 205124 kb
Host smart-bd17186d-2b4b-480d-90f9-977eaa258999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41027
73111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.4102773111
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2378993610
Short name T1770
Test name
Test status
Simulation time 186137224 ps
CPU time 2.07 seconds
Started Jun 10 05:27:30 PM PDT 24
Finished Jun 10 05:27:38 PM PDT 24
Peak memory 205092 kb
Host smart-661e11a9-9283-4f7c-9018-21775635086f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23789
93610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2378993610
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2148911629
Short name T552
Test name
Test status
Simulation time 221148966 ps
CPU time 0.86 seconds
Started Jun 10 05:27:35 PM PDT 24
Finished Jun 10 05:27:36 PM PDT 24
Peak memory 205008 kb
Host smart-32406012-c657-4cd9-a2e2-43e1a03763a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21489
11629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2148911629
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.3536285435
Short name T1778
Test name
Test status
Simulation time 165100745 ps
CPU time 0.78 seconds
Started Jun 10 05:27:27 PM PDT 24
Finished Jun 10 05:27:29 PM PDT 24
Peak memory 205004 kb
Host smart-bbefb5b6-c14e-4372-a3e9-fdb0028f201c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35362
85435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.3536285435
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1099459871
Short name T2004
Test name
Test status
Simulation time 275618811 ps
CPU time 0.93 seconds
Started Jun 10 05:27:38 PM PDT 24
Finished Jun 10 05:27:40 PM PDT 24
Peak memory 205016 kb
Host smart-5fef6d68-7b3e-48f9-8d84-9531f88fb8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10994
59871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1099459871
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.115722789
Short name T465
Test name
Test status
Simulation time 261610616 ps
CPU time 0.92 seconds
Started Jun 10 05:27:14 PM PDT 24
Finished Jun 10 05:27:15 PM PDT 24
Peak memory 205048 kb
Host smart-9ec1fd39-0279-46d5-b112-6895bf9ff7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11572
2789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.115722789
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3174578199
Short name T2093
Test name
Test status
Simulation time 3339272820 ps
CPU time 4.3 seconds
Started Jun 10 05:27:15 PM PDT 24
Finished Jun 10 05:27:20 PM PDT 24
Peak memory 204884 kb
Host smart-c424bcba-438f-4156-8ef3-69dcf514e239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31745
78199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3174578199
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1614309582
Short name T411
Test name
Test status
Simulation time 188156697 ps
CPU time 0.84 seconds
Started Jun 10 05:27:15 PM PDT 24
Finished Jun 10 05:27:16 PM PDT 24
Peak memory 204888 kb
Host smart-13369dae-8163-4570-ace6-7b2a80cacf26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16143
09582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1614309582
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.3784519898
Short name T515
Test name
Test status
Simulation time 5722557575 ps
CPU time 157.1 seconds
Started Jun 10 05:27:16 PM PDT 24
Finished Jun 10 05:29:54 PM PDT 24
Peak memory 205232 kb
Host smart-3ba2acf8-1973-4b34-9f47-5c257397db00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37845
19898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.3784519898
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2928414869
Short name T412
Test name
Test status
Simulation time 141852124 ps
CPU time 0.77 seconds
Started Jun 10 05:27:26 PM PDT 24
Finished Jun 10 05:27:27 PM PDT 24
Peak memory 205044 kb
Host smart-d9e19dc4-24f1-4b3c-8fe9-90e469330b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29284
14869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2928414869
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.776805855
Short name T139
Test name
Test status
Simulation time 224345826 ps
CPU time 0.87 seconds
Started Jun 10 05:27:34 PM PDT 24
Finished Jun 10 05:27:35 PM PDT 24
Peak memory 204840 kb
Host smart-e1e4d443-cce5-4a40-bd5e-f2acead63d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77680
5855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.776805855
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.3982691766
Short name T341
Test name
Test status
Simulation time 180651300 ps
CPU time 0.83 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:30 PM PDT 24
Peak memory 205008 kb
Host smart-740e86ed-f356-40c5-b569-cf1c0c37fcd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39826
91766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.3982691766
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3099298373
Short name T1908
Test name
Test status
Simulation time 217272279 ps
CPU time 0.97 seconds
Started Jun 10 05:27:30 PM PDT 24
Finished Jun 10 05:27:31 PM PDT 24
Peak memory 204844 kb
Host smart-8548beb5-e2d6-4d91-a6c9-3fe115894f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30992
98373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3099298373
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3763443879
Short name T1847
Test name
Test status
Simulation time 162604839 ps
CPU time 0.75 seconds
Started Jun 10 05:27:15 PM PDT 24
Finished Jun 10 05:27:17 PM PDT 24
Peak memory 204848 kb
Host smart-5fb787bf-4c60-4096-982f-ae2c654920a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37634
43879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3763443879
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3424985367
Short name T221
Test name
Test status
Simulation time 160712598 ps
CPU time 0.85 seconds
Started Jun 10 05:27:14 PM PDT 24
Finished Jun 10 05:27:15 PM PDT 24
Peak memory 204916 kb
Host smart-49e81901-3064-46fd-9e69-2bcb936eb8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34249
85367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3424985367
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_eop_single_bit_handling.1562083440
Short name T741
Test name
Test status
Simulation time 151817882 ps
CPU time 0.77 seconds
Started Jun 10 05:27:35 PM PDT 24
Finished Jun 10 05:27:36 PM PDT 24
Peak memory 205008 kb
Host smart-b9a1c398-9560-4daf-bb9a-4453e1db5e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15620
83440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_eop_single_bit_handling.1562083440
Directory /workspace/33.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.2409594562
Short name T78
Test name
Test status
Simulation time 175275357 ps
CPU time 0.78 seconds
Started Jun 10 05:27:14 PM PDT 24
Finished Jun 10 05:27:15 PM PDT 24
Peak memory 204996 kb
Host smart-d3c12cf0-b89e-4277-ae91-d0644807c2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24095
94562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.2409594562
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2274496883
Short name T493
Test name
Test status
Simulation time 45959423 ps
CPU time 0.67 seconds
Started Jun 10 05:27:17 PM PDT 24
Finished Jun 10 05:27:18 PM PDT 24
Peak memory 204960 kb
Host smart-3cd38960-474e-48f7-97a9-81e0bfd4ae61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22744
96883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2274496883
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3082877401
Short name T1405
Test name
Test status
Simulation time 16825620344 ps
CPU time 37.96 seconds
Started Jun 10 05:27:15 PM PDT 24
Finished Jun 10 05:27:54 PM PDT 24
Peak memory 205180 kb
Host smart-4e418306-040f-4b01-ae6a-3336fb9dbb64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30828
77401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3082877401
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.131492134
Short name T1681
Test name
Test status
Simulation time 166289270 ps
CPU time 0.8 seconds
Started Jun 10 05:27:13 PM PDT 24
Finished Jun 10 05:27:15 PM PDT 24
Peak memory 205044 kb
Host smart-e2283e2c-9662-466d-86e4-c377e335a94f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13149
2134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.131492134
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.442209971
Short name T1878
Test name
Test status
Simulation time 158829702 ps
CPU time 0.84 seconds
Started Jun 10 05:27:12 PM PDT 24
Finished Jun 10 05:27:13 PM PDT 24
Peak memory 205036 kb
Host smart-5614e8eb-7891-4724-9ebf-857caceba93e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44220
9971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.442209971
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.2464541366
Short name T1346
Test name
Test status
Simulation time 175518621 ps
CPU time 0.86 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:31 PM PDT 24
Peak memory 204980 kb
Host smart-4f032c72-b0e8-4519-8c0a-592de8b9bafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24645
41366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.2464541366
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.4217250460
Short name T1214
Test name
Test status
Simulation time 139039560 ps
CPU time 0.73 seconds
Started Jun 10 05:27:15 PM PDT 24
Finished Jun 10 05:27:16 PM PDT 24
Peak memory 205056 kb
Host smart-85896a4d-f01f-4240-978a-c6d137ab7947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42172
50460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.4217250460
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2064263706
Short name T2041
Test name
Test status
Simulation time 154018267 ps
CPU time 0.78 seconds
Started Jun 10 05:27:31 PM PDT 24
Finished Jun 10 05:27:33 PM PDT 24
Peak memory 204992 kb
Host smart-845d30e7-ab02-44c5-b989-ccfe7fdbb27e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20642
63706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2064263706
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.387327887
Short name T1581
Test name
Test status
Simulation time 170411426 ps
CPU time 0.84 seconds
Started Jun 10 05:27:28 PM PDT 24
Finished Jun 10 05:27:29 PM PDT 24
Peak memory 204812 kb
Host smart-303adc0d-5c2e-4307-8810-aaa411966d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38732
7887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.387327887
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1910364868
Short name T1196
Test name
Test status
Simulation time 190604287 ps
CPU time 0.86 seconds
Started Jun 10 05:27:30 PM PDT 24
Finished Jun 10 05:27:31 PM PDT 24
Peak memory 205000 kb
Host smart-1efec3a9-07ec-4bc4-9a52-85587056de6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19103
64868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1910364868
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1432432834
Short name T1161
Test name
Test status
Simulation time 150331789 ps
CPU time 0.79 seconds
Started Jun 10 05:27:17 PM PDT 24
Finished Jun 10 05:27:18 PM PDT 24
Peak memory 205020 kb
Host smart-52aff946-7113-4e94-97ab-b5d1f6842587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14324
32834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1432432834
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.549467126
Short name T298
Test name
Test status
Simulation time 173335524 ps
CPU time 0.86 seconds
Started Jun 10 05:27:13 PM PDT 24
Finished Jun 10 05:27:14 PM PDT 24
Peak memory 204996 kb
Host smart-b4e3486c-4555-4787-a4d0-8a417f6b3e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54946
7126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.549467126
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.1399043372
Short name T1101
Test name
Test status
Simulation time 6679265940 ps
CPU time 63.3 seconds
Started Jun 10 05:27:14 PM PDT 24
Finished Jun 10 05:28:18 PM PDT 24
Peak memory 205192 kb
Host smart-3e8a66ad-bf08-43cb-a886-a3ffade3bf13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13990
43372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1399043372
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.3436380944
Short name T1815
Test name
Test status
Simulation time 246058121 ps
CPU time 1.05 seconds
Started Jun 10 05:27:24 PM PDT 24
Finished Jun 10 05:27:25 PM PDT 24
Peak memory 205024 kb
Host smart-2e98b4e6-2a5b-44e2-b2da-096967cc9006
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3436380944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.3436380944
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.4013883973
Short name T614
Test name
Test status
Simulation time 199584036 ps
CPU time 0.85 seconds
Started Jun 10 05:27:26 PM PDT 24
Finished Jun 10 05:27:27 PM PDT 24
Peak memory 205028 kb
Host smart-c0e38934-4886-4b2b-a652-0acb2f09ca8a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4013883973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.4013883973
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.217607802
Short name T1596
Test name
Test status
Simulation time 158268131 ps
CPU time 0.83 seconds
Started Jun 10 05:27:25 PM PDT 24
Finished Jun 10 05:27:26 PM PDT 24
Peak memory 205120 kb
Host smart-939bd530-2625-4b68-9194-a1369c4bd3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21760
7802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.217607802
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.3915402694
Short name T1559
Test name
Test status
Simulation time 3390826898 ps
CPU time 4.05 seconds
Started Jun 10 05:27:18 PM PDT 24
Finished Jun 10 05:27:22 PM PDT 24
Peak memory 205068 kb
Host smart-4de9e24d-b3a7-43d0-abae-b072c9e5f990
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3915402694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.3915402694
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3185819826
Short name T1510
Test name
Test status
Simulation time 13406845870 ps
CPU time 12.72 seconds
Started Jun 10 05:27:31 PM PDT 24
Finished Jun 10 05:27:44 PM PDT 24
Peak memory 205092 kb
Host smart-c91b051c-c54b-467a-ae89-f11864fa3db6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3185819826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3185819826
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.475248149
Short name T1726
Test name
Test status
Simulation time 23304214957 ps
CPU time 22.98 seconds
Started Jun 10 05:27:38 PM PDT 24
Finished Jun 10 05:28:02 PM PDT 24
Peak memory 204932 kb
Host smart-eb9576ac-2fab-4294-a077-ac85e1744f46
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=475248149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.475248149
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2516286508
Short name T1347
Test name
Test status
Simulation time 155006062 ps
CPU time 0.78 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:31 PM PDT 24
Peak memory 205040 kb
Host smart-ec3fb137-a15b-4414-8881-d75466917145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25162
86508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2516286508
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.116421643
Short name T1499
Test name
Test status
Simulation time 176365424 ps
CPU time 0.78 seconds
Started Jun 10 05:27:17 PM PDT 24
Finished Jun 10 05:27:18 PM PDT 24
Peak memory 204976 kb
Host smart-eb8cd6da-0061-46f3-848f-e916f0be2c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11642
1643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.116421643
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1723104270
Short name T1723
Test name
Test status
Simulation time 1437213388 ps
CPU time 3.18 seconds
Started Jun 10 05:27:18 PM PDT 24
Finished Jun 10 05:27:22 PM PDT 24
Peak memory 205136 kb
Host smart-71cac37e-213d-4458-93e2-fdd917ac6aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17231
04270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1723104270
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.2971114324
Short name T1586
Test name
Test status
Simulation time 145389373 ps
CPU time 0.78 seconds
Started Jun 10 05:27:32 PM PDT 24
Finished Jun 10 05:27:33 PM PDT 24
Peak memory 205080 kb
Host smart-c91b4d43-5a6e-483c-a804-07d876f415ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29711
14324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2971114324
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.1688716063
Short name T554
Test name
Test status
Simulation time 32137791 ps
CPU time 0.65 seconds
Started Jun 10 05:27:21 PM PDT 24
Finished Jun 10 05:27:22 PM PDT 24
Peak memory 205000 kb
Host smart-705b9653-4d99-4624-a291-de346a4fdad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16887
16063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1688716063
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.3148504960
Short name T160
Test name
Test status
Simulation time 954115716 ps
CPU time 2.16 seconds
Started Jun 10 05:27:44 PM PDT 24
Finished Jun 10 05:27:47 PM PDT 24
Peak memory 205012 kb
Host smart-9f0562be-cd35-4da4-b212-38b551caaed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31485
04960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.3148504960
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3511505201
Short name T1063
Test name
Test status
Simulation time 320951505 ps
CPU time 1.84 seconds
Started Jun 10 05:27:22 PM PDT 24
Finished Jun 10 05:27:24 PM PDT 24
Peak memory 205040 kb
Host smart-64f8752f-c635-4838-b701-e1fcc8120d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35115
05201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3511505201
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.1976422932
Short name T1822
Test name
Test status
Simulation time 288800021 ps
CPU time 1.05 seconds
Started Jun 10 05:27:25 PM PDT 24
Finished Jun 10 05:27:26 PM PDT 24
Peak memory 205024 kb
Host smart-ab5a65a4-78cb-4a5f-886c-26a87d75249c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19764
22932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.1976422932
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2123152040
Short name T459
Test name
Test status
Simulation time 176732275 ps
CPU time 0.79 seconds
Started Jun 10 05:27:22 PM PDT 24
Finished Jun 10 05:27:24 PM PDT 24
Peak memory 205012 kb
Host smart-165c82fd-70a6-4f12-bf7f-fd3b737d1dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21231
52040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2123152040
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2735018846
Short name T419
Test name
Test status
Simulation time 218844349 ps
CPU time 0.92 seconds
Started Jun 10 05:27:17 PM PDT 24
Finished Jun 10 05:27:19 PM PDT 24
Peak memory 204996 kb
Host smart-8f8f06bf-a4f9-4ab4-ac35-4705dcd853fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27350
18846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2735018846
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.2771294641
Short name T1767
Test name
Test status
Simulation time 266951385 ps
CPU time 0.9 seconds
Started Jun 10 05:27:39 PM PDT 24
Finished Jun 10 05:27:41 PM PDT 24
Peak memory 205000 kb
Host smart-d9c4cc09-cbb8-48e6-a763-0fb03a4455f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27712
94641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2771294641
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.3075770421
Short name T1782
Test name
Test status
Simulation time 3296807388 ps
CPU time 4.87 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:34 PM PDT 24
Peak memory 205096 kb
Host smart-80423e40-c7e2-4f1f-86aa-d9737f1b0465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30757
70421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3075770421
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.4191112767
Short name T2099
Test name
Test status
Simulation time 194375544 ps
CPU time 0.84 seconds
Started Jun 10 05:27:36 PM PDT 24
Finished Jun 10 05:27:37 PM PDT 24
Peak memory 204848 kb
Host smart-97d3f7a6-2624-4289-bfd8-f4720e3e32e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41911
12767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.4191112767
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.3875891262
Short name T1074
Test name
Test status
Simulation time 13668114883 ps
CPU time 98.36 seconds
Started Jun 10 05:27:19 PM PDT 24
Finished Jun 10 05:28:58 PM PDT 24
Peak memory 205120 kb
Host smart-8fc087fc-7001-49f7-852b-6b5399e582cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38758
91262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.3875891262
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2221236178
Short name T1157
Test name
Test status
Simulation time 160651837 ps
CPU time 0.78 seconds
Started Jun 10 05:27:19 PM PDT 24
Finished Jun 10 05:27:20 PM PDT 24
Peak memory 204904 kb
Host smart-b5c10c25-a00e-419d-a9a1-c88a2d7207db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22212
36178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2221236178
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3707390295
Short name T1977
Test name
Test status
Simulation time 164486144 ps
CPU time 0.84 seconds
Started Jun 10 05:27:18 PM PDT 24
Finished Jun 10 05:27:19 PM PDT 24
Peak memory 204980 kb
Host smart-ef4fe0ed-792e-42ac-98ee-7571eecbdd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37073
90295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3707390295
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.249907134
Short name T646
Test name
Test status
Simulation time 208115547 ps
CPU time 0.83 seconds
Started Jun 10 05:27:18 PM PDT 24
Finished Jun 10 05:27:20 PM PDT 24
Peak memory 204952 kb
Host smart-6e2eefcb-bda7-42b7-b989-cabb96d6fe9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24990
7134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.249907134
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.529591542
Short name T567
Test name
Test status
Simulation time 168881247 ps
CPU time 0.85 seconds
Started Jun 10 05:27:39 PM PDT 24
Finished Jun 10 05:27:40 PM PDT 24
Peak memory 204972 kb
Host smart-ce599c47-7af1-450f-9848-021593f354be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52959
1542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.529591542
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.1826692893
Short name T189
Test name
Test status
Simulation time 149339792 ps
CPU time 0.77 seconds
Started Jun 10 05:27:55 PM PDT 24
Finished Jun 10 05:27:56 PM PDT 24
Peak memory 204992 kb
Host smart-ab5b90e4-93f2-4584-8f34-89f002778738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18266
92893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.1826692893
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_eop_single_bit_handling.427355774
Short name T1606
Test name
Test status
Simulation time 216747543 ps
CPU time 0.89 seconds
Started Jun 10 05:27:32 PM PDT 24
Finished Jun 10 05:27:33 PM PDT 24
Peak memory 204996 kb
Host smart-33a1ab54-c1f6-476d-8f50-b689108812a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42735
5774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_eop_single_bit_handling.427355774
Directory /workspace/34.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3578218997
Short name T1566
Test name
Test status
Simulation time 167527496 ps
CPU time 0.76 seconds
Started Jun 10 05:27:39 PM PDT 24
Finished Jun 10 05:27:40 PM PDT 24
Peak memory 205020 kb
Host smart-696f6cb6-6207-4fae-a1d1-b7482c88552c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35782
18997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3578218997
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2447948433
Short name T1619
Test name
Test status
Simulation time 34251542 ps
CPU time 0.7 seconds
Started Jun 10 05:27:56 PM PDT 24
Finished Jun 10 05:27:57 PM PDT 24
Peak memory 205028 kb
Host smart-c0e8cc2d-62dd-4653-b6c0-2b0f39d7b543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24479
48433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2447948433
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1812201045
Short name T220
Test name
Test status
Simulation time 7347908994 ps
CPU time 17.72 seconds
Started Jun 10 05:27:38 PM PDT 24
Finished Jun 10 05:28:01 PM PDT 24
Peak memory 205188 kb
Host smart-b8ff5906-b9e9-47f5-b7b1-bc4eaaffc594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18122
01045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1812201045
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1175163863
Short name T1360
Test name
Test status
Simulation time 196152040 ps
CPU time 0.87 seconds
Started Jun 10 05:27:49 PM PDT 24
Finished Jun 10 05:27:50 PM PDT 24
Peak memory 205004 kb
Host smart-6291c067-f5c2-46ab-8c03-ab9e0db16cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11751
63863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1175163863
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1235372023
Short name T886
Test name
Test status
Simulation time 195414882 ps
CPU time 0.87 seconds
Started Jun 10 05:27:31 PM PDT 24
Finished Jun 10 05:27:33 PM PDT 24
Peak memory 205004 kb
Host smart-72316442-38e7-4487-9192-aa911a21fde7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12353
72023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1235372023
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.3191586994
Short name T659
Test name
Test status
Simulation time 167015946 ps
CPU time 0.87 seconds
Started Jun 10 05:27:39 PM PDT 24
Finished Jun 10 05:27:45 PM PDT 24
Peak memory 204876 kb
Host smart-29b28552-fb1d-42c8-b0e8-70f330308f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31915
86994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.3191586994
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.397079762
Short name T807
Test name
Test status
Simulation time 173908919 ps
CPU time 0.8 seconds
Started Jun 10 05:27:44 PM PDT 24
Finished Jun 10 05:27:45 PM PDT 24
Peak memory 205056 kb
Host smart-a404010c-0853-4105-9933-c2c8e2a377af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39707
9762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.397079762
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.3185204590
Short name T179
Test name
Test status
Simulation time 152002048 ps
CPU time 0.79 seconds
Started Jun 10 05:27:51 PM PDT 24
Finished Jun 10 05:27:52 PM PDT 24
Peak memory 205004 kb
Host smart-0322facf-b6b2-492e-9a29-61423424b9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31852
04590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.3185204590
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1766865542
Short name T647
Test name
Test status
Simulation time 149096308 ps
CPU time 0.83 seconds
Started Jun 10 05:27:26 PM PDT 24
Finished Jun 10 05:27:27 PM PDT 24
Peak memory 204940 kb
Host smart-4e0cb925-81be-4ac7-834e-c1a0fac765d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17668
65542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1766865542
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3052981081
Short name T174
Test name
Test status
Simulation time 276948455 ps
CPU time 0.99 seconds
Started Jun 10 05:27:59 PM PDT 24
Finished Jun 10 05:28:01 PM PDT 24
Peak memory 205004 kb
Host smart-80867205-1960-41fe-a001-eac36011d62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30529
81081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3052981081
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1891102371
Short name T2081
Test name
Test status
Simulation time 169410736 ps
CPU time 0.8 seconds
Started Jun 10 05:27:23 PM PDT 24
Finished Jun 10 05:27:25 PM PDT 24
Peak memory 205024 kb
Host smart-7c4bb175-f758-450f-b15d-71e81202d483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18911
02371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1891102371
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.24377879
Short name T384
Test name
Test status
Simulation time 258317982 ps
CPU time 0.88 seconds
Started Jun 10 05:27:22 PM PDT 24
Finished Jun 10 05:27:23 PM PDT 24
Peak memory 205008 kb
Host smart-ce508684-bc26-4de4-808c-00c3971c1cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24377
879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.24377879
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1114896541
Short name T1450
Test name
Test status
Simulation time 12817245493 ps
CPU time 123.6 seconds
Started Jun 10 05:27:19 PM PDT 24
Finished Jun 10 05:29:23 PM PDT 24
Peak memory 205168 kb
Host smart-8b6f68a3-ae62-4e0f-b9da-3a8885835b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11148
96541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1114896541
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.797301161
Short name T1191
Test name
Test status
Simulation time 237883884 ps
CPU time 0.9 seconds
Started Jun 10 05:27:43 PM PDT 24
Finished Jun 10 05:27:45 PM PDT 24
Peak memory 205028 kb
Host smart-17a3ab16-16e2-4909-b90a-bc8b8d5fc101
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=797301161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.797301161
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.290685938
Short name T364
Test name
Test status
Simulation time 215625100 ps
CPU time 0.83 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:31 PM PDT 24
Peak memory 205020 kb
Host smart-27cc55d0-8457-44c9-bdf5-c4c3b1dffcd7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=290685938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.290685938
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.1010478611
Short name T1368
Test name
Test status
Simulation time 214255384 ps
CPU time 0.87 seconds
Started Jun 10 05:27:33 PM PDT 24
Finished Jun 10 05:27:34 PM PDT 24
Peak memory 204984 kb
Host smart-0fc25b67-a4e8-4064-b422-1b87939a98a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10104
78611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.1010478611
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2398934760
Short name T1614
Test name
Test status
Simulation time 3706667986 ps
CPU time 5.24 seconds
Started Jun 10 05:27:52 PM PDT 24
Finished Jun 10 05:27:58 PM PDT 24
Peak memory 205260 kb
Host smart-dd7f81e6-2286-412e-9711-027bebb4a0ec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2398934760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.2398934760
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2422044256
Short name T1836
Test name
Test status
Simulation time 13390792471 ps
CPU time 13.47 seconds
Started Jun 10 05:27:27 PM PDT 24
Finished Jun 10 05:27:41 PM PDT 24
Peak memory 205096 kb
Host smart-42f13780-01e3-42a9-8902-83f6fbe46e27
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2422044256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2422044256
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.777033454
Short name T1653
Test name
Test status
Simulation time 23373119555 ps
CPU time 26.32 seconds
Started Jun 10 05:27:59 PM PDT 24
Finished Jun 10 05:28:26 PM PDT 24
Peak memory 205172 kb
Host smart-4c0e1a20-f0a2-4dc0-8bc8-6c176be9c6e1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=777033454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.777033454
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2172303408
Short name T2067
Test name
Test status
Simulation time 211587897 ps
CPU time 0.88 seconds
Started Jun 10 05:27:23 PM PDT 24
Finished Jun 10 05:27:24 PM PDT 24
Peak memory 205016 kb
Host smart-bdaff88a-3764-4d1e-a24d-e1cb8837dc29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21723
03408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2172303408
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.1557372324
Short name T2069
Test name
Test status
Simulation time 172122499 ps
CPU time 0.82 seconds
Started Jun 10 05:27:38 PM PDT 24
Finished Jun 10 05:27:39 PM PDT 24
Peak memory 205032 kb
Host smart-4b427dbe-9a3c-4bfb-acf5-da208533bdb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15573
72324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.1557372324
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.2163130737
Short name T548
Test name
Test status
Simulation time 302359380 ps
CPU time 1.01 seconds
Started Jun 10 05:27:30 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 204992 kb
Host smart-88aa72b2-5c88-47a8-bfbb-783e112e5c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21631
30737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.2163130737
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.3146145958
Short name T577
Test name
Test status
Simulation time 158949448 ps
CPU time 0.76 seconds
Started Jun 10 05:27:37 PM PDT 24
Finished Jun 10 05:27:38 PM PDT 24
Peak memory 205056 kb
Host smart-a19b9c4a-30ed-4147-88a2-0db0f4eed134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31461
45958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.3146145958
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.1574446243
Short name T377
Test name
Test status
Simulation time 35572682 ps
CPU time 0.65 seconds
Started Jun 10 05:27:23 PM PDT 24
Finished Jun 10 05:27:24 PM PDT 24
Peak memory 205000 kb
Host smart-d093da66-e251-4c2b-bca5-eac40109aca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15744
46243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1574446243
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.2412777278
Short name T840
Test name
Test status
Simulation time 859339364 ps
CPU time 2.05 seconds
Started Jun 10 05:27:29 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 205148 kb
Host smart-e51af9ae-2311-4a3e-9234-613db1af17f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24127
77278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.2412777278
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.97437219
Short name T1045
Test name
Test status
Simulation time 342306250 ps
CPU time 2.37 seconds
Started Jun 10 05:27:40 PM PDT 24
Finished Jun 10 05:27:42 PM PDT 24
Peak memory 205200 kb
Host smart-e6196dbd-1d9b-4c60-a8af-e0271390acd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97437
219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.97437219
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.1639004369
Short name T826
Test name
Test status
Simulation time 218775773 ps
CPU time 0.91 seconds
Started Jun 10 05:27:30 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 204956 kb
Host smart-43efe7fc-8856-4885-9cad-65fb0fad3046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16390
04369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.1639004369
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1583281074
Short name T1554
Test name
Test status
Simulation time 152634730 ps
CPU time 0.77 seconds
Started Jun 10 05:27:41 PM PDT 24
Finished Jun 10 05:27:42 PM PDT 24
Peak memory 205012 kb
Host smart-528a6247-500f-48e9-bc4f-490b838824ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15832
81074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1583281074
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3405779012
Short name T810
Test name
Test status
Simulation time 245734486 ps
CPU time 0.94 seconds
Started Jun 10 05:27:58 PM PDT 24
Finished Jun 10 05:27:59 PM PDT 24
Peak memory 205004 kb
Host smart-4bf49b3f-240f-4a69-b255-f7de529d9322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34057
79012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3405779012
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.2592108379
Short name T2088
Test name
Test status
Simulation time 225733055 ps
CPU time 0.92 seconds
Started Jun 10 05:27:24 PM PDT 24
Finished Jun 10 05:27:25 PM PDT 24
Peak memory 205032 kb
Host smart-a50862e7-e067-4960-ae5c-b12750005826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25921
08379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.2592108379
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.1399439663
Short name T1966
Test name
Test status
Simulation time 3402913325 ps
CPU time 4.33 seconds
Started Jun 10 05:27:44 PM PDT 24
Finished Jun 10 05:27:48 PM PDT 24
Peak memory 205068 kb
Host smart-38c575ce-d642-49bf-b41d-5c22eb6a22ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13994
39663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.1399439663
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.625853252
Short name T475
Test name
Test status
Simulation time 200034126 ps
CPU time 0.86 seconds
Started Jun 10 05:27:31 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 205048 kb
Host smart-0d8b4762-e261-4ee8-91bc-d2534cdebec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62585
3252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.625853252
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.3269571444
Short name T863
Test name
Test status
Simulation time 14859634069 ps
CPU time 420.21 seconds
Started Jun 10 05:27:24 PM PDT 24
Finished Jun 10 05:34:25 PM PDT 24
Peak memory 205200 kb
Host smart-99d06d43-4bf3-4d70-bc4b-7f75d599cc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32695
71444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.3269571444
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2419097145
Short name T1750
Test name
Test status
Simulation time 145571946 ps
CPU time 0.79 seconds
Started Jun 10 05:27:25 PM PDT 24
Finished Jun 10 05:27:26 PM PDT 24
Peak memory 205028 kb
Host smart-eed0a5e8-0320-4fd7-b4fc-c66babfb13f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24190
97145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2419097145
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2000637923
Short name T155
Test name
Test status
Simulation time 223594357 ps
CPU time 0.89 seconds
Started Jun 10 05:27:45 PM PDT 24
Finished Jun 10 05:27:46 PM PDT 24
Peak memory 205028 kb
Host smart-59d802cf-0cfb-47c0-9485-0a89528bab7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20006
37923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2000637923
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.2157446181
Short name T1705
Test name
Test status
Simulation time 154436575 ps
CPU time 0.83 seconds
Started Jun 10 05:27:36 PM PDT 24
Finished Jun 10 05:27:37 PM PDT 24
Peak memory 205004 kb
Host smart-589db91b-1946-43d5-8112-a8de3e5e2a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21574
46181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.2157446181
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3610059071
Short name T1355
Test name
Test status
Simulation time 168543528 ps
CPU time 0.8 seconds
Started Jun 10 05:27:23 PM PDT 24
Finished Jun 10 05:27:25 PM PDT 24
Peak memory 205024 kb
Host smart-3308807e-5e83-4141-a8c4-c8a9e6e94106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36100
59071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3610059071
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1213252778
Short name T474
Test name
Test status
Simulation time 156035020 ps
CPU time 0.76 seconds
Started Jun 10 05:27:41 PM PDT 24
Finished Jun 10 05:27:42 PM PDT 24
Peak memory 205028 kb
Host smart-f63f7137-7022-4013-9f4c-958b34830180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12132
52778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1213252778
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1292098823
Short name T184
Test name
Test status
Simulation time 182334135 ps
CPU time 0.8 seconds
Started Jun 10 05:27:48 PM PDT 24
Finished Jun 10 05:27:49 PM PDT 24
Peak memory 205040 kb
Host smart-9f1b12eb-eeb3-4299-961c-ac76147deeac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12920
98823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1292098823
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_eop_single_bit_handling.324283550
Short name T1386
Test name
Test status
Simulation time 171242585 ps
CPU time 0.8 seconds
Started Jun 10 05:27:37 PM PDT 24
Finished Jun 10 05:27:39 PM PDT 24
Peak memory 205012 kb
Host smart-a1ce2309-cef7-4496-a0a3-4071a4961bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32428
3550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_eop_single_bit_handling.324283550
Directory /workspace/35.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3076954677
Short name T1100
Test name
Test status
Simulation time 140639504 ps
CPU time 0.75 seconds
Started Jun 10 05:27:27 PM PDT 24
Finished Jun 10 05:27:28 PM PDT 24
Peak memory 205032 kb
Host smart-4abdce60-5a7c-41b9-aefe-32ef11c385cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30769
54677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3076954677
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2117282644
Short name T1298
Test name
Test status
Simulation time 36415145 ps
CPU time 0.63 seconds
Started Jun 10 05:27:30 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 204948 kb
Host smart-3cb343ff-63b3-4fe9-9cc7-1dee7e322815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21172
82644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2117282644
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1908044282
Short name T250
Test name
Test status
Simulation time 9104063039 ps
CPU time 23.89 seconds
Started Jun 10 05:27:26 PM PDT 24
Finished Jun 10 05:27:50 PM PDT 24
Peak memory 205172 kb
Host smart-84196398-eecb-4d74-b7a2-04f3610b1691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19080
44282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1908044282
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2638634678
Short name T1572
Test name
Test status
Simulation time 160883105 ps
CPU time 0.82 seconds
Started Jun 10 05:28:00 PM PDT 24
Finished Jun 10 05:28:01 PM PDT 24
Peak memory 205032 kb
Host smart-850fbd42-5dfa-4c98-901b-8f70228ac453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26386
34678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2638634678
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1908064882
Short name T1818
Test name
Test status
Simulation time 160671113 ps
CPU time 0.81 seconds
Started Jun 10 05:28:04 PM PDT 24
Finished Jun 10 05:28:05 PM PDT 24
Peak memory 205000 kb
Host smart-0b5d2207-7f31-4759-b123-77e4b84a503e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19080
64882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1908064882
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.3876305242
Short name T1151
Test name
Test status
Simulation time 177161850 ps
CPU time 0.82 seconds
Started Jun 10 05:27:30 PM PDT 24
Finished Jun 10 05:27:32 PM PDT 24
Peak memory 204992 kb
Host smart-63f65a4b-75e5-49a8-9663-0586d3b35a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38763
05242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.3876305242
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.1123848161
Short name T1979
Test name
Test status
Simulation time 145348330 ps
CPU time 0.75 seconds
Started Jun 10 05:27:35 PM PDT 24
Finished Jun 10 05:27:40 PM PDT 24
Peak memory 205004 kb
Host smart-ccf1fce8-f662-4740-bbb9-1417f125a5f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11238
48161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.1123848161
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.4217235037
Short name T1691
Test name
Test status
Simulation time 155413104 ps
CPU time 0.81 seconds
Started Jun 10 05:27:43 PM PDT 24
Finished Jun 10 05:27:44 PM PDT 24
Peak memory 205008 kb
Host smart-919fe207-80ab-4fee-97b6-c7d65c6c4394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42172
35037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.4217235037
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3789561268
Short name T1337
Test name
Test status
Simulation time 147888175 ps
CPU time 0.77 seconds
Started Jun 10 05:27:43 PM PDT 24
Finished Jun 10 05:27:44 PM PDT 24
Peak memory 205012 kb
Host smart-ab5af158-bb06-497b-91ca-1b1cdc17bf34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37895
61268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3789561268
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.334056954
Short name T187
Test name
Test status
Simulation time 217713949 ps
CPU time 0.93 seconds
Started Jun 10 05:27:49 PM PDT 24
Finished Jun 10 05:27:51 PM PDT 24
Peak memory 205020 kb
Host smart-86b17f72-06d7-415c-84b9-340c0971f140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33405
6954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.334056954
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.214084885
Short name T433
Test name
Test status
Simulation time 157200634 ps
CPU time 0.78 seconds
Started Jun 10 05:27:31 PM PDT 24
Finished Jun 10 05:27:37 PM PDT 24
Peak memory 205008 kb
Host smart-84764444-c9c6-4b46-b304-aedb32ec9977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21408
4885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.214084885
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.323244249
Short name T731
Test name
Test status
Simulation time 171253692 ps
CPU time 0.78 seconds
Started Jun 10 05:27:44 PM PDT 24
Finished Jun 10 05:27:45 PM PDT 24
Peak memory 205020 kb
Host smart-f556fe08-312d-4743-9279-cd195cb82b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32324
4249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.323244249
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.3907164197
Short name T1411
Test name
Test status
Simulation time 13439619844 ps
CPU time 118.67 seconds
Started Jun 10 05:27:28 PM PDT 24
Finished Jun 10 05:29:27 PM PDT 24
Peak memory 205184 kb
Host smart-8c959dd0-3ec1-4cb6-8c35-6ea9a6de0c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39071
64197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.3907164197
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.474032220
Short name T899
Test name
Test status
Simulation time 268390621 ps
CPU time 1 seconds
Started Jun 10 05:28:04 PM PDT 24
Finished Jun 10 05:28:05 PM PDT 24
Peak memory 205000 kb
Host smart-d87a17e8-8bfa-42dd-9a86-a60ed2e8457d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=474032220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.474032220
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.2199377470
Short name T749
Test name
Test status
Simulation time 175615686 ps
CPU time 0.85 seconds
Started Jun 10 05:27:40 PM PDT 24
Finished Jun 10 05:27:41 PM PDT 24
Peak memory 205024 kb
Host smart-f74b7893-96e0-4ab5-9cbe-b575fd6a0b09
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2199377470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.2199377470
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.1372954713
Short name T825
Test name
Test status
Simulation time 184575378 ps
CPU time 0.88 seconds
Started Jun 10 05:27:40 PM PDT 24
Finished Jun 10 05:27:42 PM PDT 24
Peak memory 204992 kb
Host smart-812fc76b-8404-4ccf-a449-52537c959168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13729
54713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.1372954713
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.3483164306
Short name T456
Test name
Test status
Simulation time 3899367919 ps
CPU time 5.29 seconds
Started Jun 10 05:27:28 PM PDT 24
Finished Jun 10 05:27:34 PM PDT 24
Peak memory 205164 kb
Host smart-bdf52289-7da0-4e30-a832-bcf183de0b88
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3483164306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.3483164306
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.910151209
Short name T46
Test name
Test status
Simulation time 13375817923 ps
CPU time 14.27 seconds
Started Jun 10 05:27:26 PM PDT 24
Finished Jun 10 05:27:40 PM PDT 24
Peak memory 205228 kb
Host smart-77ab9229-9d19-4c94-b64a-eff59a4a3ca5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=910151209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.910151209
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.3099687745
Short name T872
Test name
Test status
Simulation time 23327091126 ps
CPU time 23 seconds
Started Jun 10 05:27:28 PM PDT 24
Finished Jun 10 05:27:51 PM PDT 24
Peak memory 205200 kb
Host smart-25e48782-01a3-4982-8325-0c9cccd5a048
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3099687745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.3099687745
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2094602420
Short name T88
Test name
Test status
Simulation time 148898348 ps
CPU time 0.81 seconds
Started Jun 10 05:27:30 PM PDT 24
Finished Jun 10 05:27:31 PM PDT 24
Peak memory 204980 kb
Host smart-e74b0af1-d4a0-4ad4-8610-9cec4341fa19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20946
02420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2094602420
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.1923702775
Short name T1772
Test name
Test status
Simulation time 162354872 ps
CPU time 0.8 seconds
Started Jun 10 05:27:30 PM PDT 24
Finished Jun 10 05:27:31 PM PDT 24
Peak memory 204980 kb
Host smart-0228a504-d59d-49ae-b039-4e5ca0cc8263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19237
02775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.1923702775
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1735200756
Short name T1639
Test name
Test status
Simulation time 827905651 ps
CPU time 2.17 seconds
Started Jun 10 05:28:05 PM PDT 24
Finished Jun 10 05:28:07 PM PDT 24
Peak memory 205096 kb
Host smart-cc749e1a-21f3-4e44-b257-02132f4d36c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17352
00756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1735200756
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.3068854724
Short name T467
Test name
Test status
Simulation time 138755080 ps
CPU time 0.82 seconds
Started Jun 10 05:28:04 PM PDT 24
Finished Jun 10 05:28:05 PM PDT 24
Peak memory 205040 kb
Host smart-66cd13e9-d877-4083-833f-7a26d9533c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30688
54724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.3068854724
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.2079164564
Short name T1264
Test name
Test status
Simulation time 44760591 ps
CPU time 0.71 seconds
Started Jun 10 05:28:09 PM PDT 24
Finished Jun 10 05:28:10 PM PDT 24
Peak memory 205020 kb
Host smart-abcc676b-3bd1-45f0-bb8e-6379d2578b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20791
64564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2079164564
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2878994264
Short name T714
Test name
Test status
Simulation time 785128634 ps
CPU time 1.87 seconds
Started Jun 10 05:27:45 PM PDT 24
Finished Jun 10 05:27:47 PM PDT 24
Peak memory 205192 kb
Host smart-30397da4-0c17-4324-8662-85359e473714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28789
94264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2878994264
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3009194747
Short name T1268
Test name
Test status
Simulation time 215435091 ps
CPU time 2.25 seconds
Started Jun 10 05:27:34 PM PDT 24
Finished Jun 10 05:27:37 PM PDT 24
Peak memory 205120 kb
Host smart-f956f0e7-8493-45ec-ad1d-c9aba899b22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30091
94747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3009194747
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3964360272
Short name T845
Test name
Test status
Simulation time 182006783 ps
CPU time 0.9 seconds
Started Jun 10 05:28:07 PM PDT 24
Finished Jun 10 05:28:08 PM PDT 24
Peak memory 205028 kb
Host smart-4269c6df-e258-4cad-80e4-a2d3be25d2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39643
60272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3964360272
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3688674902
Short name T1597
Test name
Test status
Simulation time 147659856 ps
CPU time 0.81 seconds
Started Jun 10 05:27:42 PM PDT 24
Finished Jun 10 05:27:43 PM PDT 24
Peak memory 204928 kb
Host smart-f4dfada6-50f9-415f-bb7a-b04aa1b2b3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36886
74902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3688674902
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2527942919
Short name T1905
Test name
Test status
Simulation time 199900675 ps
CPU time 0.84 seconds
Started Jun 10 05:27:57 PM PDT 24
Finished Jun 10 05:27:58 PM PDT 24
Peak memory 204980 kb
Host smart-4dba3f52-c990-4a8c-a25c-b754aa716ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25279
42919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2527942919
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.3354764334
Short name T655
Test name
Test status
Simulation time 195738949 ps
CPU time 0.93 seconds
Started Jun 10 05:27:35 PM PDT 24
Finished Jun 10 05:27:37 PM PDT 24
Peak memory 204972 kb
Host smart-c08ee96a-a913-41ea-9a8f-214574844923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33547
64334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.3354764334
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.2147622611
Short name T939
Test name
Test status
Simulation time 3304011360 ps
CPU time 4.16 seconds
Started Jun 10 05:27:36 PM PDT 24
Finished Jun 10 05:27:40 PM PDT 24
Peak memory 205068 kb
Host smart-177a597a-3f0c-4d81-b4fe-5a86b555b3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21476
22611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.2147622611
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2639384558
Short name T2010
Test name
Test status
Simulation time 203039390 ps
CPU time 0.93 seconds
Started Jun 10 05:27:37 PM PDT 24
Finished Jun 10 05:27:38 PM PDT 24
Peak memory 205080 kb
Host smart-6820dc97-9881-4fa0-9020-b5234104e0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26393
84558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2639384558
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.959175733
Short name T526
Test name
Test status
Simulation time 13361768007 ps
CPU time 129.79 seconds
Started Jun 10 05:27:35 PM PDT 24
Finished Jun 10 05:29:45 PM PDT 24
Peak memory 205144 kb
Host smart-684c9696-9628-4d70-9fce-a67bd0180b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95917
5733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.959175733
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3021082774
Short name T1098
Test name
Test status
Simulation time 182952817 ps
CPU time 0.8 seconds
Started Jun 10 05:28:14 PM PDT 24
Finished Jun 10 05:28:15 PM PDT 24
Peak memory 204988 kb
Host smart-cb7006d1-9236-4b4b-b7f8-b6159a7850c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30210
82774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3021082774
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.414127464
Short name T130
Test name
Test status
Simulation time 250182901 ps
CPU time 0.91 seconds
Started Jun 10 05:27:55 PM PDT 24
Finished Jun 10 05:27:56 PM PDT 24
Peak memory 204932 kb
Host smart-9e03a19e-855f-4662-868b-3807edf0dfa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41412
7464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.414127464
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.1802354389
Short name T1388
Test name
Test status
Simulation time 175899856 ps
CPU time 0.81 seconds
Started Jun 10 05:28:11 PM PDT 24
Finished Jun 10 05:28:12 PM PDT 24
Peak memory 205040 kb
Host smart-5e120e35-83b6-4700-a19a-e4563be209a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18023
54389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.1802354389
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.839012869
Short name T769
Test name
Test status
Simulation time 198457643 ps
CPU time 0.83 seconds
Started Jun 10 05:27:35 PM PDT 24
Finished Jun 10 05:27:37 PM PDT 24
Peak memory 205032 kb
Host smart-fcfff80d-1152-4dc9-b27f-35d7e3b69b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83901
2869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.839012869
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3394261978
Short name T1228
Test name
Test status
Simulation time 191550702 ps
CPU time 0.79 seconds
Started Jun 10 05:27:34 PM PDT 24
Finished Jun 10 05:27:35 PM PDT 24
Peak memory 204980 kb
Host smart-00fd5929-d3cb-4339-bfd7-29d1a934ccb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33942
61978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3394261978
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1973318329
Short name T1364
Test name
Test status
Simulation time 151346999 ps
CPU time 0.8 seconds
Started Jun 10 05:27:37 PM PDT 24
Finished Jun 10 05:27:38 PM PDT 24
Peak memory 204884 kb
Host smart-46da0bc7-0c17-410f-8f3f-ea3eecadaefb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19733
18329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1973318329
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_eop_single_bit_handling.2307334435
Short name T322
Test name
Test status
Simulation time 188495029 ps
CPU time 0.79 seconds
Started Jun 10 05:27:59 PM PDT 24
Finished Jun 10 05:28:01 PM PDT 24
Peak memory 205008 kb
Host smart-6b637327-3ecd-41cc-b405-d2336717c487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23073
34435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_eop_single_bit_handling.2307334435
Directory /workspace/36.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.4241222789
Short name T398
Test name
Test status
Simulation time 152874507 ps
CPU time 0.76 seconds
Started Jun 10 05:27:59 PM PDT 24
Finished Jun 10 05:28:00 PM PDT 24
Peak memory 205036 kb
Host smart-912c31c1-3929-4791-babe-3be429f3d8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42412
22789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.4241222789
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3957538444
Short name T687
Test name
Test status
Simulation time 34145198 ps
CPU time 0.72 seconds
Started Jun 10 05:27:39 PM PDT 24
Finished Jun 10 05:27:40 PM PDT 24
Peak memory 205132 kb
Host smart-cd349b7d-775d-426e-9d39-d69f7d54f371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39575
38444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3957538444
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1089859942
Short name T92
Test name
Test status
Simulation time 21033326649 ps
CPU time 50.36 seconds
Started Jun 10 05:27:58 PM PDT 24
Finished Jun 10 05:28:49 PM PDT 24
Peak memory 205152 kb
Host smart-eff28e9d-1957-4c58-9c20-b14199006203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10898
59942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1089859942
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3736072957
Short name T1257
Test name
Test status
Simulation time 155361874 ps
CPU time 0.81 seconds
Started Jun 10 05:27:58 PM PDT 24
Finished Jun 10 05:27:59 PM PDT 24
Peak memory 205028 kb
Host smart-371af734-43f9-48f8-b4b4-28bb7d6f2af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37360
72957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3736072957
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.814135181
Short name T165
Test name
Test status
Simulation time 190216038 ps
CPU time 0.98 seconds
Started Jun 10 05:28:13 PM PDT 24
Finished Jun 10 05:28:15 PM PDT 24
Peak memory 204996 kb
Host smart-6b3604ea-003e-4138-89b8-d7ed5c46499a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81413
5181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.814135181
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.810252758
Short name T1901
Test name
Test status
Simulation time 148573660 ps
CPU time 0.78 seconds
Started Jun 10 05:27:35 PM PDT 24
Finished Jun 10 05:27:36 PM PDT 24
Peak memory 204916 kb
Host smart-41550c36-ab7f-4e8f-8598-8778524becca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81025
2758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.810252758
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3650901126
Short name T320
Test name
Test status
Simulation time 138653869 ps
CPU time 0.81 seconds
Started Jun 10 05:28:03 PM PDT 24
Finished Jun 10 05:28:04 PM PDT 24
Peak memory 205040 kb
Host smart-736ae9f3-b75e-4510-ae97-b7a17e429523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36509
01126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3650901126
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.4093319221
Short name T2109
Test name
Test status
Simulation time 174342970 ps
CPU time 0.82 seconds
Started Jun 10 05:27:42 PM PDT 24
Finished Jun 10 05:27:43 PM PDT 24
Peak memory 205120 kb
Host smart-acd0e83a-344e-4e19-bcd6-f2e826e67225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40933
19221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.4093319221
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3827981469
Short name T37
Test name
Test status
Simulation time 152932021 ps
CPU time 0.76 seconds
Started Jun 10 05:27:42 PM PDT 24
Finished Jun 10 05:27:43 PM PDT 24
Peak memory 205032 kb
Host smart-d043410b-3c28-4b9f-86b4-fa83a2d37f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38279
81469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3827981469
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1386344572
Short name T186
Test name
Test status
Simulation time 174815996 ps
CPU time 0.89 seconds
Started Jun 10 05:27:27 PM PDT 24
Finished Jun 10 05:27:29 PM PDT 24
Peak memory 205016 kb
Host smart-f5b43afa-bdf0-4855-b021-c090663a5031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13863
44572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1386344572
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.174699371
Short name T530
Test name
Test status
Simulation time 155462138 ps
CPU time 0.88 seconds
Started Jun 10 05:27:43 PM PDT 24
Finished Jun 10 05:27:44 PM PDT 24
Peak memory 204932 kb
Host smart-bfd60e92-7a38-4139-9ec5-b243740598b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17469
9371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.174699371
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.4242297307
Short name T1876
Test name
Test status
Simulation time 155626488 ps
CPU time 0.78 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:28:20 PM PDT 24
Peak memory 205016 kb
Host smart-61525bfa-c13f-406c-831b-67e9f2b0658c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42422
97307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.4242297307
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.702216896
Short name T2053
Test name
Test status
Simulation time 6045761681 ps
CPU time 169.45 seconds
Started Jun 10 05:27:42 PM PDT 24
Finished Jun 10 05:30:32 PM PDT 24
Peak memory 205204 kb
Host smart-c9d17e05-82ec-4ec3-ace7-4e8a553fc8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70221
6896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.702216896
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.93847388
Short name T2045
Test name
Test status
Simulation time 251466659 ps
CPU time 0.92 seconds
Started Jun 10 05:27:56 PM PDT 24
Finished Jun 10 05:27:57 PM PDT 24
Peak memory 205036 kb
Host smart-71b1e0b4-e649-4e0b-aac5-0d133ecadc76
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=93847388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.93847388
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.3176807258
Short name T1218
Test name
Test status
Simulation time 154992623 ps
CPU time 0.84 seconds
Started Jun 10 05:28:15 PM PDT 24
Finished Jun 10 05:28:16 PM PDT 24
Peak memory 205080 kb
Host smart-898bac85-6a01-47c2-9233-052ad44532f1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3176807258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.3176807258
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.19167212
Short name T1456
Test name
Test status
Simulation time 4368134841 ps
CPU time 5.24 seconds
Started Jun 10 05:27:37 PM PDT 24
Finished Jun 10 05:27:43 PM PDT 24
Peak memory 205096 kb
Host smart-e2a2739c-1c5e-4898-aa6d-0d985569507b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=19167212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.19167212
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.2263595720
Short name T1117
Test name
Test status
Simulation time 13314662560 ps
CPU time 13.26 seconds
Started Jun 10 05:28:05 PM PDT 24
Finished Jun 10 05:28:19 PM PDT 24
Peak memory 205088 kb
Host smart-a57910cc-58f4-4586-a676-4da6d07e51cf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2263595720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.2263595720
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.3339057535
Short name T828
Test name
Test status
Simulation time 23431511091 ps
CPU time 27.76 seconds
Started Jun 10 05:27:37 PM PDT 24
Finished Jun 10 05:28:06 PM PDT 24
Peak memory 205228 kb
Host smart-695dd933-cfde-4895-bbcb-979df95dcf14
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3339057535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.3339057535
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.372041657
Short name T1972
Test name
Test status
Simulation time 174087938 ps
CPU time 0.83 seconds
Started Jun 10 05:27:41 PM PDT 24
Finished Jun 10 05:27:42 PM PDT 24
Peak memory 204988 kb
Host smart-c62338cd-7cda-4c8c-b65b-79d260a524bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37204
1657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.372041657
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.2206056345
Short name T763
Test name
Test status
Simulation time 154158646 ps
CPU time 0.78 seconds
Started Jun 10 05:27:38 PM PDT 24
Finished Jun 10 05:27:39 PM PDT 24
Peak memory 205036 kb
Host smart-0b6f9844-b67c-4fa4-ad5c-635488d51a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22060
56345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.2206056345
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.961761298
Short name T203
Test name
Test status
Simulation time 1098268448 ps
CPU time 2.55 seconds
Started Jun 10 05:28:13 PM PDT 24
Finished Jun 10 05:28:16 PM PDT 24
Peak memory 205036 kb
Host smart-77d89707-7708-4f75-b67e-3200fac183b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96176
1298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.961761298
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.41719935
Short name T1308
Test name
Test status
Simulation time 139238582 ps
CPU time 0.78 seconds
Started Jun 10 05:27:41 PM PDT 24
Finished Jun 10 05:27:42 PM PDT 24
Peak memory 205000 kb
Host smart-c1e64481-2397-49b0-9dd9-1551ef5b2088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41719
935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.41719935
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.3112193623
Short name T126
Test name
Test status
Simulation time 36324857 ps
CPU time 0.67 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:28:21 PM PDT 24
Peak memory 204996 kb
Host smart-44106273-16e0-4a5d-8196-399ed973ecd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31121
93623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.3112193623
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3859885051
Short name T497
Test name
Test status
Simulation time 799922430 ps
CPU time 1.89 seconds
Started Jun 10 05:28:05 PM PDT 24
Finished Jun 10 05:28:08 PM PDT 24
Peak memory 205140 kb
Host smart-14fe3a0c-3b82-4f9a-879b-c158fd298e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38598
85051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3859885051
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3083690893
Short name T858
Test name
Test status
Simulation time 198668622 ps
CPU time 2.13 seconds
Started Jun 10 05:28:02 PM PDT 24
Finished Jun 10 05:28:04 PM PDT 24
Peak memory 205096 kb
Host smart-9aa14057-f84f-4052-a5ed-b5b15df59510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30836
90893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3083690893
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2574712037
Short name T594
Test name
Test status
Simulation time 272039182 ps
CPU time 0.92 seconds
Started Jun 10 05:27:53 PM PDT 24
Finished Jun 10 05:27:54 PM PDT 24
Peak memory 205032 kb
Host smart-247ebe89-ca26-4bd7-bbe0-e1e682bb4f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25747
12037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2574712037
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2319400430
Short name T1143
Test name
Test status
Simulation time 172530602 ps
CPU time 0.79 seconds
Started Jun 10 05:28:14 PM PDT 24
Finished Jun 10 05:28:16 PM PDT 24
Peak memory 204984 kb
Host smart-47e340a2-1c83-4d59-af99-40950e87ab25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23194
00430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2319400430
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3819367269
Short name T311
Test name
Test status
Simulation time 165437524 ps
CPU time 0.87 seconds
Started Jun 10 05:28:07 PM PDT 24
Finished Jun 10 05:28:09 PM PDT 24
Peak memory 205040 kb
Host smart-7d984a77-31ac-401a-821e-dc561068e93e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38193
67269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3819367269
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.4010159777
Short name T1556
Test name
Test status
Simulation time 255143906 ps
CPU time 0.95 seconds
Started Jun 10 05:28:09 PM PDT 24
Finished Jun 10 05:28:10 PM PDT 24
Peak memory 204992 kb
Host smart-19c545d5-da37-4960-9142-39e827a9c9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40101
59777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.4010159777
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.2276007487
Short name T1311
Test name
Test status
Simulation time 3274896094 ps
CPU time 4.04 seconds
Started Jun 10 05:28:04 PM PDT 24
Finished Jun 10 05:28:08 PM PDT 24
Peak memory 204972 kb
Host smart-40d73e36-b01e-43ff-a67c-a51ce8c58df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22760
07487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.2276007487
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1287039553
Short name T1699
Test name
Test status
Simulation time 214969740 ps
CPU time 0.93 seconds
Started Jun 10 05:27:40 PM PDT 24
Finished Jun 10 05:27:42 PM PDT 24
Peak memory 205092 kb
Host smart-9af1d779-7841-4eb0-8bf9-b2331e30b645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12870
39553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1287039553
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.1404620301
Short name T1624
Test name
Test status
Simulation time 6345433065 ps
CPU time 190.14 seconds
Started Jun 10 05:27:40 PM PDT 24
Finished Jun 10 05:30:51 PM PDT 24
Peak memory 205156 kb
Host smart-3ba5520e-66a3-433b-bf35-3944409c5d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14046
20301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.1404620301
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2780327243
Short name T1962
Test name
Test status
Simulation time 197721467 ps
CPU time 0.9 seconds
Started Jun 10 05:27:44 PM PDT 24
Finished Jun 10 05:27:45 PM PDT 24
Peak memory 204904 kb
Host smart-06adacaa-c1ce-489f-8fe2-02255d0bd44f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27803
27243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2780327243
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3960195212
Short name T147
Test name
Test status
Simulation time 226688643 ps
CPU time 0.9 seconds
Started Jun 10 05:27:59 PM PDT 24
Finished Jun 10 05:28:01 PM PDT 24
Peak memory 205032 kb
Host smart-897f9b0c-4496-400d-9b0a-5bf4d7bfd455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39601
95212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3960195212
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.2530196906
Short name T734
Test name
Test status
Simulation time 207738243 ps
CPU time 0.85 seconds
Started Jun 10 05:28:14 PM PDT 24
Finished Jun 10 05:28:15 PM PDT 24
Peak memory 205048 kb
Host smart-61479ff5-3989-4e4c-bbc2-c7011debb62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25301
96906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.2530196906
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1936125277
Short name T1495
Test name
Test status
Simulation time 238659372 ps
CPU time 0.93 seconds
Started Jun 10 05:28:11 PM PDT 24
Finished Jun 10 05:28:12 PM PDT 24
Peak memory 205012 kb
Host smart-1b28eb9e-8d48-4f29-999f-d58bf07c1bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19361
25277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1936125277
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1394468950
Short name T934
Test name
Test status
Simulation time 192915845 ps
CPU time 0.89 seconds
Started Jun 10 05:27:52 PM PDT 24
Finished Jun 10 05:27:53 PM PDT 24
Peak memory 205004 kb
Host smart-b7423328-5cb5-40f0-a95d-98ae9cc42f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13944
68950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1394468950
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.3201373285
Short name T1065
Test name
Test status
Simulation time 152032773 ps
CPU time 0.84 seconds
Started Jun 10 05:27:56 PM PDT 24
Finished Jun 10 05:27:57 PM PDT 24
Peak memory 205008 kb
Host smart-58572827-1288-41c6-a65b-863411575e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32013
73285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.3201373285
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_eop_single_bit_handling.1488958996
Short name T524
Test name
Test status
Simulation time 183155837 ps
CPU time 0.81 seconds
Started Jun 10 05:27:54 PM PDT 24
Finished Jun 10 05:27:56 PM PDT 24
Peak memory 204992 kb
Host smart-b91641e6-15d9-462d-ac0d-002d7fcc1567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14889
58996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_eop_single_bit_handling.1488958996
Directory /workspace/37.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1678751924
Short name T818
Test name
Test status
Simulation time 171293223 ps
CPU time 0.84 seconds
Started Jun 10 05:28:00 PM PDT 24
Finished Jun 10 05:28:01 PM PDT 24
Peak memory 204992 kb
Host smart-1a08c90c-7f5a-4931-b9b2-ac7c07dc8b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16787
51924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1678751924
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1327800252
Short name T41
Test name
Test status
Simulation time 47344567 ps
CPU time 0.65 seconds
Started Jun 10 05:28:21 PM PDT 24
Finished Jun 10 05:28:23 PM PDT 24
Peak memory 205000 kb
Host smart-b1d7778e-d9e6-4c2f-9ed7-a0e26a5ac727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13278
00252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1327800252
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1597397981
Short name T93
Test name
Test status
Simulation time 9709829534 ps
CPU time 22.83 seconds
Started Jun 10 05:28:17 PM PDT 24
Finished Jun 10 05:28:43 PM PDT 24
Peak memory 205076 kb
Host smart-097a9851-e9a1-4fd6-8aef-56ed8e92e38f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15973
97981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1597397981
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2076287587
Short name T870
Test name
Test status
Simulation time 228737897 ps
CPU time 0.91 seconds
Started Jun 10 05:27:54 PM PDT 24
Finished Jun 10 05:27:56 PM PDT 24
Peak memory 204888 kb
Host smart-06cbb1d2-3da6-4964-a480-bc0124b5c8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20762
87587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2076287587
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.2624219389
Short name T837
Test name
Test status
Simulation time 185685492 ps
CPU time 0.85 seconds
Started Jun 10 05:28:22 PM PDT 24
Finished Jun 10 05:28:23 PM PDT 24
Peak memory 205024 kb
Host smart-933c08ec-4055-40cc-9bd1-698d2fbe165d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26242
19389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.2624219389
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.4009062205
Short name T1436
Test name
Test status
Simulation time 183112380 ps
CPU time 0.83 seconds
Started Jun 10 05:27:54 PM PDT 24
Finished Jun 10 05:27:56 PM PDT 24
Peak memory 205044 kb
Host smart-d8715c08-97c2-4fb8-a77b-2c92f65ba1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40090
62205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.4009062205
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2272379806
Short name T2078
Test name
Test status
Simulation time 149778213 ps
CPU time 0.79 seconds
Started Jun 10 05:27:53 PM PDT 24
Finished Jun 10 05:27:55 PM PDT 24
Peak memory 205004 kb
Host smart-1b58820c-0b49-4a79-a930-1f00dcb3fc6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22723
79806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2272379806
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2122460579
Short name T1529
Test name
Test status
Simulation time 152027128 ps
CPU time 0.8 seconds
Started Jun 10 05:27:54 PM PDT 24
Finished Jun 10 05:27:56 PM PDT 24
Peak memory 204884 kb
Host smart-8e6a916c-ebfb-4314-b92c-1d2c1d6c04e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21224
60579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2122460579
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2433402658
Short name T972
Test name
Test status
Simulation time 202314656 ps
CPU time 0.83 seconds
Started Jun 10 05:27:59 PM PDT 24
Finished Jun 10 05:28:00 PM PDT 24
Peak memory 205016 kb
Host smart-d534a290-1cae-4678-b5c7-1edfea574906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24334
02658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2433402658
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1356618809
Short name T2032
Test name
Test status
Simulation time 252674914 ps
CPU time 0.96 seconds
Started Jun 10 05:28:17 PM PDT 24
Finished Jun 10 05:28:18 PM PDT 24
Peak memory 205028 kb
Host smart-d19860f8-163e-4042-9031-343e6b768ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13566
18809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1356618809
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.3508258015
Short name T1573
Test name
Test status
Simulation time 147854367 ps
CPU time 0.77 seconds
Started Jun 10 05:27:54 PM PDT 24
Finished Jun 10 05:27:56 PM PDT 24
Peak memory 205036 kb
Host smart-fe911d5b-36cc-4e4c-b87b-5e067eadc25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35082
58015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.3508258015
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1456480646
Short name T645
Test name
Test status
Simulation time 168715142 ps
CPU time 0.79 seconds
Started Jun 10 05:28:12 PM PDT 24
Finished Jun 10 05:28:13 PM PDT 24
Peak memory 205000 kb
Host smart-a1310d00-cce0-437b-bc61-7c97a9cd529d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14564
80646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1456480646
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.224473663
Short name T458
Test name
Test status
Simulation time 15211384715 ps
CPU time 409.72 seconds
Started Jun 10 05:27:53 PM PDT 24
Finished Jun 10 05:34:43 PM PDT 24
Peak memory 205272 kb
Host smart-932df7e2-33d6-4b2d-b709-cec9cde57f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22447
3663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.224473663
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.25583145
Short name T726
Test name
Test status
Simulation time 234493145 ps
CPU time 0.94 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:22 PM PDT 24
Peak memory 205020 kb
Host smart-c9300747-3baf-4fe0-9ca1-95a2cfb6073c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=25583145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.25583145
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.574280907
Short name T1028
Test name
Test status
Simulation time 164693077 ps
CPU time 0.83 seconds
Started Jun 10 05:28:18 PM PDT 24
Finished Jun 10 05:28:20 PM PDT 24
Peak memory 205012 kb
Host smart-975cb6d6-e2e1-48f2-9cb6-bba3944910d0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=574280907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.574280907
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.1892151025
Short name T852
Test name
Test status
Simulation time 156934619 ps
CPU time 0.8 seconds
Started Jun 10 05:28:07 PM PDT 24
Finished Jun 10 05:28:09 PM PDT 24
Peak memory 205044 kb
Host smart-9aa84560-e980-44b2-b6e1-fa18d89ad5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18921
51025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.1892151025
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1556833817
Short name T1645
Test name
Test status
Simulation time 4245142999 ps
CPU time 5.8 seconds
Started Jun 10 05:27:54 PM PDT 24
Finished Jun 10 05:28:00 PM PDT 24
Peak memory 205096 kb
Host smart-38c745a8-1870-4187-8a9a-408eb6d1ca15
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1556833817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1556833817
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.755105194
Short name T1121
Test name
Test status
Simulation time 13318964056 ps
CPU time 13.21 seconds
Started Jun 10 05:27:57 PM PDT 24
Finished Jun 10 05:28:11 PM PDT 24
Peak memory 205104 kb
Host smart-a166d3e8-4a2a-4f53-ab51-ab98d2907f93
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=755105194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.755105194
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.1700134500
Short name T2062
Test name
Test status
Simulation time 23319445744 ps
CPU time 22.78 seconds
Started Jun 10 05:28:16 PM PDT 24
Finished Jun 10 05:28:43 PM PDT 24
Peak memory 205172 kb
Host smart-4e88c637-07e4-432e-b836-0e1d248db5b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1700134500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.1700134500
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3308005703
Short name T1960
Test name
Test status
Simulation time 187849854 ps
CPU time 0.87 seconds
Started Jun 10 05:28:16 PM PDT 24
Finished Jun 10 05:28:17 PM PDT 24
Peak memory 205008 kb
Host smart-8c900944-ed61-44cf-8761-521bd93fd528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33080
05703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3308005703
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.266763517
Short name T76
Test name
Test status
Simulation time 153966803 ps
CPU time 0.79 seconds
Started Jun 10 05:28:21 PM PDT 24
Finished Jun 10 05:28:22 PM PDT 24
Peak memory 205008 kb
Host smart-67c653d9-155a-4120-8d6d-8c3a845f19ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26676
3517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.266763517
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.2619823582
Short name T830
Test name
Test status
Simulation time 1054655399 ps
CPU time 2.4 seconds
Started Jun 10 05:28:16 PM PDT 24
Finished Jun 10 05:28:19 PM PDT 24
Peak memory 205220 kb
Host smart-1883fda4-18a0-43c6-a4e7-d9a5feb9620c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26198
23582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.2619823582
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.2745131876
Short name T1009
Test name
Test status
Simulation time 157746717 ps
CPU time 0.79 seconds
Started Jun 10 05:27:56 PM PDT 24
Finished Jun 10 05:27:57 PM PDT 24
Peak memory 205008 kb
Host smart-21f85940-a7e7-490f-ba8b-a0fab5a9a955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27451
31876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.2745131876
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.2400511118
Short name T335
Test name
Test status
Simulation time 34349306 ps
CPU time 0.62 seconds
Started Jun 10 05:27:54 PM PDT 24
Finished Jun 10 05:27:56 PM PDT 24
Peak memory 204988 kb
Host smart-301d0ca3-515d-4d6d-93d7-655ed0a2704e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24005
11118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2400511118
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.1885878503
Short name T2063
Test name
Test status
Simulation time 973851527 ps
CPU time 2.16 seconds
Started Jun 10 05:27:53 PM PDT 24
Finished Jun 10 05:27:55 PM PDT 24
Peak memory 205104 kb
Host smart-b7cf1c5c-1144-4db3-8292-8f915536def6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18858
78503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.1885878503
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.976545873
Short name T2006
Test name
Test status
Simulation time 390102039 ps
CPU time 2.37 seconds
Started Jun 10 05:27:52 PM PDT 24
Finished Jun 10 05:27:54 PM PDT 24
Peak memory 205128 kb
Host smart-c51704a1-2d2c-4fdb-85d5-687fd9bb7109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97654
5873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.976545873
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3553290155
Short name T1623
Test name
Test status
Simulation time 167843700 ps
CPU time 0.82 seconds
Started Jun 10 05:28:15 PM PDT 24
Finished Jun 10 05:28:17 PM PDT 24
Peak memory 205024 kb
Host smart-9728f94c-0f50-4b04-924b-611799eccc1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35532
90155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3553290155
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.997439153
Short name T1543
Test name
Test status
Simulation time 158171003 ps
CPU time 0.77 seconds
Started Jun 10 05:27:56 PM PDT 24
Finished Jun 10 05:27:57 PM PDT 24
Peak memory 205008 kb
Host smart-b1f075ba-7d24-4ebd-aab8-22209f8a0d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99743
9153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.997439153
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2121737710
Short name T389
Test name
Test status
Simulation time 180061340 ps
CPU time 0.85 seconds
Started Jun 10 05:27:52 PM PDT 24
Finished Jun 10 05:27:53 PM PDT 24
Peak memory 205000 kb
Host smart-511c1b15-1af9-4de7-a99b-235e0326286b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21217
37710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2121737710
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3200226275
Short name T1166
Test name
Test status
Simulation time 184563057 ps
CPU time 0.84 seconds
Started Jun 10 05:27:54 PM PDT 24
Finished Jun 10 05:27:55 PM PDT 24
Peak memory 205004 kb
Host smart-1bc55b70-7094-4ddd-aaa8-9e3704283fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32002
26275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3200226275
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3384797509
Short name T1176
Test name
Test status
Simulation time 3257386469 ps
CPU time 3.78 seconds
Started Jun 10 05:27:55 PM PDT 24
Finished Jun 10 05:27:59 PM PDT 24
Peak memory 205028 kb
Host smart-7524631a-7587-48b6-9bc0-724b627b5b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33847
97509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3384797509
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1587762729
Short name T1142
Test name
Test status
Simulation time 191968461 ps
CPU time 0.87 seconds
Started Jun 10 05:27:51 PM PDT 24
Finished Jun 10 05:27:53 PM PDT 24
Peak memory 205092 kb
Host smart-89d431c7-a48c-4d1e-b24b-a607a9764fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15877
62729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1587762729
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.3299870308
Short name T565
Test name
Test status
Simulation time 13563762438 ps
CPU time 106.86 seconds
Started Jun 10 05:28:14 PM PDT 24
Finished Jun 10 05:30:02 PM PDT 24
Peak memory 205252 kb
Host smart-b23f13c3-b4c2-4c3f-804d-4c878a099a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32998
70308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.3299870308
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1431407104
Short name T1738
Test name
Test status
Simulation time 197400785 ps
CPU time 0.83 seconds
Started Jun 10 05:27:52 PM PDT 24
Finished Jun 10 05:27:53 PM PDT 24
Peak memory 205056 kb
Host smart-e372dab3-136a-4621-aec3-d7cee2b34b90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14314
07104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1431407104
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1794590005
Short name T1256
Test name
Test status
Simulation time 172178744 ps
CPU time 0.79 seconds
Started Jun 10 05:27:55 PM PDT 24
Finished Jun 10 05:27:56 PM PDT 24
Peak memory 204976 kb
Host smart-1dfca046-5798-4520-9cab-a169234cbbd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17945
90005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1794590005
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1741654619
Short name T1625
Test name
Test status
Simulation time 157902838 ps
CPU time 0.91 seconds
Started Jun 10 05:27:56 PM PDT 24
Finished Jun 10 05:27:57 PM PDT 24
Peak memory 205016 kb
Host smart-cf8a935a-c652-49ab-9e60-ecef0583a42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17416
54619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1741654619
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2609452316
Short name T1944
Test name
Test status
Simulation time 194803561 ps
CPU time 0.8 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:28:20 PM PDT 24
Peak memory 205024 kb
Host smart-0e197209-5fba-4add-bece-80decfebaddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26094
52316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2609452316
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3685900015
Short name T1940
Test name
Test status
Simulation time 166625543 ps
CPU time 0.79 seconds
Started Jun 10 05:27:55 PM PDT 24
Finished Jun 10 05:27:56 PM PDT 24
Peak memory 205012 kb
Host smart-c34cd216-0f36-4077-a4fe-b80e18cf3e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36859
00015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3685900015
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.4158923449
Short name T70
Test name
Test status
Simulation time 156449573 ps
CPU time 0.84 seconds
Started Jun 10 05:27:59 PM PDT 24
Finished Jun 10 05:28:00 PM PDT 24
Peak memory 204984 kb
Host smart-e8fd6cc5-4834-46d9-abdd-60f3c6bf9abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41589
23449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.4158923449
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_eop_single_bit_handling.3049161725
Short name T87
Test name
Test status
Simulation time 191404231 ps
CPU time 0.92 seconds
Started Jun 10 05:28:15 PM PDT 24
Finished Jun 10 05:28:17 PM PDT 24
Peak memory 204992 kb
Host smart-1889c9fe-0dc8-4d27-84ae-a22748e525c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30491
61725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_eop_single_bit_handling.3049161725
Directory /workspace/38.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.63602579
Short name T1053
Test name
Test status
Simulation time 133821022 ps
CPU time 0.78 seconds
Started Jun 10 05:27:54 PM PDT 24
Finished Jun 10 05:27:55 PM PDT 24
Peak memory 205068 kb
Host smart-4ae4bf87-cb41-4e39-9a66-87a4c588e8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63602
579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.63602579
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.45802871
Short name T1895
Test name
Test status
Simulation time 48879943 ps
CPU time 0.65 seconds
Started Jun 10 05:27:57 PM PDT 24
Finished Jun 10 05:27:58 PM PDT 24
Peak memory 204988 kb
Host smart-988d7bd3-f47c-433b-ac96-9c2deee22b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45802
871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.45802871
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.176373760
Short name T478
Test name
Test status
Simulation time 10991110350 ps
CPU time 25.69 seconds
Started Jun 10 05:27:54 PM PDT 24
Finished Jun 10 05:28:21 PM PDT 24
Peak memory 205120 kb
Host smart-f8de481f-2135-4e99-a6fe-4ee8db8351cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17637
3760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.176373760
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1623500402
Short name T693
Test name
Test status
Simulation time 233327878 ps
CPU time 0.9 seconds
Started Jun 10 05:27:52 PM PDT 24
Finished Jun 10 05:27:53 PM PDT 24
Peak memory 205008 kb
Host smart-8da46f7f-442e-4df9-8cfc-b493b2104c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16235
00402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1623500402
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1937750271
Short name T860
Test name
Test status
Simulation time 228927190 ps
CPU time 0.86 seconds
Started Jun 10 05:28:16 PM PDT 24
Finished Jun 10 05:28:17 PM PDT 24
Peak memory 205000 kb
Host smart-3899bb6a-99ea-4bdd-8d7d-72923d8a1d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19377
50271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1937750271
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.2582756289
Short name T1010
Test name
Test status
Simulation time 159953412 ps
CPU time 0.83 seconds
Started Jun 10 05:28:22 PM PDT 24
Finished Jun 10 05:28:23 PM PDT 24
Peak memory 204904 kb
Host smart-61a81776-c759-46ef-a442-16d61cc0a725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25827
56289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.2582756289
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3681796146
Short name T556
Test name
Test status
Simulation time 134843005 ps
CPU time 0.74 seconds
Started Jun 10 05:28:18 PM PDT 24
Finished Jun 10 05:28:19 PM PDT 24
Peak memory 205028 kb
Host smart-f2530508-e632-40bc-b2ac-a329fedd6fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36817
96146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3681796146
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3977257111
Short name T1213
Test name
Test status
Simulation time 185840264 ps
CPU time 0.77 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:28:20 PM PDT 24
Peak memory 205016 kb
Host smart-b276215c-2096-4936-aa37-0bae6bd4faa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39772
57111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3977257111
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2511922495
Short name T1015
Test name
Test status
Simulation time 184224564 ps
CPU time 0.8 seconds
Started Jun 10 05:27:55 PM PDT 24
Finished Jun 10 05:27:56 PM PDT 24
Peak memory 205008 kb
Host smart-68dffb0e-1d05-4709-be1a-b0faaf9b7bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25119
22495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2511922495
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1214221211
Short name T2110
Test name
Test status
Simulation time 222959333 ps
CPU time 0.94 seconds
Started Jun 10 05:27:53 PM PDT 24
Finished Jun 10 05:27:54 PM PDT 24
Peak memory 204996 kb
Host smart-221ec718-fde7-44c3-8af2-cdd47c016f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12142
21211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1214221211
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1741892117
Short name T611
Test name
Test status
Simulation time 203379786 ps
CPU time 0.82 seconds
Started Jun 10 05:28:14 PM PDT 24
Finished Jun 10 05:28:15 PM PDT 24
Peak memory 204992 kb
Host smart-3ac885b1-bbc1-4e8b-ba5a-9f847b7db776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17418
92117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1741892117
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.3101590616
Short name T690
Test name
Test status
Simulation time 191299590 ps
CPU time 0.82 seconds
Started Jun 10 05:28:17 PM PDT 24
Finished Jun 10 05:28:18 PM PDT 24
Peak memory 205000 kb
Host smart-796c3fd5-04ea-4267-ad68-ae36c04664fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31015
90616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3101590616
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.4218118012
Short name T1431
Test name
Test status
Simulation time 8795570610 ps
CPU time 83.91 seconds
Started Jun 10 05:28:13 PM PDT 24
Finished Jun 10 05:29:37 PM PDT 24
Peak memory 205232 kb
Host smart-0794b940-2eff-4732-9d6d-e91c5df38043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42181
18012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.4218118012
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.3955962745
Short name T2
Test name
Test status
Simulation time 247382759 ps
CPU time 0.96 seconds
Started Jun 10 05:28:04 PM PDT 24
Finished Jun 10 05:28:05 PM PDT 24
Peak memory 205020 kb
Host smart-4ab9ae9f-1894-4104-abb4-824266834b30
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3955962745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.3955962745
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.3153376640
Short name T1698
Test name
Test status
Simulation time 158920906 ps
CPU time 0.8 seconds
Started Jun 10 05:28:23 PM PDT 24
Finished Jun 10 05:28:25 PM PDT 24
Peak memory 204988 kb
Host smart-1cd06b1d-e72a-47ce-b637-192455204a48
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3153376640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.3153376640
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.2928450325
Short name T1500
Test name
Test status
Simulation time 241147423 ps
CPU time 0.92 seconds
Started Jun 10 05:27:59 PM PDT 24
Finished Jun 10 05:28:00 PM PDT 24
Peak memory 204976 kb
Host smart-ba0fed99-030c-48ef-bf2c-13919487d01f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29284
50325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.2928450325
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.3092946136
Short name T926
Test name
Test status
Simulation time 4117070914 ps
CPU time 4.68 seconds
Started Jun 10 05:28:16 PM PDT 24
Finished Jun 10 05:28:21 PM PDT 24
Peak memory 205260 kb
Host smart-62c63b8e-2c15-46a0-84c3-0cf9c1a26387
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3092946136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.3092946136
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.180474351
Short name T550
Test name
Test status
Simulation time 13324529318 ps
CPU time 13.27 seconds
Started Jun 10 05:28:06 PM PDT 24
Finished Jun 10 05:28:20 PM PDT 24
Peak memory 205140 kb
Host smart-b77a0e41-b0fb-4b2b-8b32-8da42c68a8da
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=180474351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.180474351
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.2194133590
Short name T958
Test name
Test status
Simulation time 23320822606 ps
CPU time 29.82 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:51 PM PDT 24
Peak memory 205016 kb
Host smart-30b3be23-bda4-48ec-86e6-1c2993ddd149
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2194133590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.2194133590
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2347770622
Short name T1027
Test name
Test status
Simulation time 162338661 ps
CPU time 0.76 seconds
Started Jun 10 05:28:05 PM PDT 24
Finished Jun 10 05:28:06 PM PDT 24
Peak memory 204936 kb
Host smart-78976cda-95bf-4ab8-b5e4-a8008e6936f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23477
70622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2347770622
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.708167425
Short name T1459
Test name
Test status
Simulation time 177599139 ps
CPU time 0.8 seconds
Started Jun 10 05:27:57 PM PDT 24
Finished Jun 10 05:27:58 PM PDT 24
Peak memory 205008 kb
Host smart-793df302-ddb0-4205-9410-ebdcefbb06f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70816
7425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.708167425
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.58620530
Short name T1419
Test name
Test status
Simulation time 645216503 ps
CPU time 1.74 seconds
Started Jun 10 05:27:56 PM PDT 24
Finished Jun 10 05:27:58 PM PDT 24
Peak memory 204984 kb
Host smart-b5cc036c-88fb-439e-8c92-6e3af9766552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58620
530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.58620530
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.564653252
Short name T839
Test name
Test status
Simulation time 142710776 ps
CPU time 0.8 seconds
Started Jun 10 05:28:35 PM PDT 24
Finished Jun 10 05:28:36 PM PDT 24
Peak memory 205004 kb
Host smart-3301d5be-858c-43a0-9d33-1adeb9f922de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56465
3252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.564653252
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3924263117
Short name T1994
Test name
Test status
Simulation time 33512366 ps
CPU time 0.64 seconds
Started Jun 10 05:27:57 PM PDT 24
Finished Jun 10 05:27:58 PM PDT 24
Peak memory 204996 kb
Host smart-e8ce3fb5-5e16-4fe1-a85d-f513dc296426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39242
63117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3924263117
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.1089772932
Short name T513
Test name
Test status
Simulation time 906779356 ps
CPU time 2.03 seconds
Started Jun 10 05:27:52 PM PDT 24
Finished Jun 10 05:27:54 PM PDT 24
Peak memory 205100 kb
Host smart-07d457cd-10e2-4b15-8090-afde04839069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10897
72932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.1089772932
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3819979012
Short name T904
Test name
Test status
Simulation time 288364636 ps
CPU time 1.91 seconds
Started Jun 10 05:27:54 PM PDT 24
Finished Jun 10 05:27:57 PM PDT 24
Peak memory 204984 kb
Host smart-a4801160-487f-434c-b1ea-0ee7f5e0c9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38199
79012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3819979012
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.4165555372
Short name T528
Test name
Test status
Simulation time 164359423 ps
CPU time 0.81 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:28:21 PM PDT 24
Peak memory 205008 kb
Host smart-7106284d-568c-485c-9f61-d7591f766c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41655
55372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.4165555372
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2903346413
Short name T806
Test name
Test status
Simulation time 146234220 ps
CPU time 0.81 seconds
Started Jun 10 05:28:10 PM PDT 24
Finished Jun 10 05:28:11 PM PDT 24
Peak memory 204980 kb
Host smart-ef690f11-6a57-489e-8764-f208548af644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29033
46413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2903346413
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.1817433576
Short name T1928
Test name
Test status
Simulation time 246384689 ps
CPU time 1 seconds
Started Jun 10 05:27:59 PM PDT 24
Finished Jun 10 05:28:00 PM PDT 24
Peak memory 205004 kb
Host smart-52fb81be-7ddb-4183-a5c4-0dace259d1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18174
33576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.1817433576
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.1171056881
Short name T882
Test name
Test status
Simulation time 184358125 ps
CPU time 0.84 seconds
Started Jun 10 05:27:54 PM PDT 24
Finished Jun 10 05:27:56 PM PDT 24
Peak memory 205140 kb
Host smart-5a7085ff-b48b-4838-9ede-31970708b40c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11710
56881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.1171056881
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.664585460
Short name T541
Test name
Test status
Simulation time 3293582366 ps
CPU time 4.26 seconds
Started Jun 10 05:28:00 PM PDT 24
Finished Jun 10 05:28:05 PM PDT 24
Peak memory 205056 kb
Host smart-8bafa90b-d280-46ef-bfae-ce27d25fac13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66458
5460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.664585460
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.533200868
Short name T953
Test name
Test status
Simulation time 195795451 ps
CPU time 0.95 seconds
Started Jun 10 05:28:00 PM PDT 24
Finished Jun 10 05:28:01 PM PDT 24
Peak memory 204892 kb
Host smart-7c63b147-23f4-4132-81bd-cfc3111cadfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53320
0868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.533200868
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.748113029
Short name T2082
Test name
Test status
Simulation time 11579060382 ps
CPU time 88.66 seconds
Started Jun 10 05:27:54 PM PDT 24
Finished Jun 10 05:29:23 PM PDT 24
Peak memory 205372 kb
Host smart-a0b54397-06d6-4e1a-914f-4839db69f8d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74811
3029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.748113029
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1748239696
Short name T1367
Test name
Test status
Simulation time 153088190 ps
CPU time 0.81 seconds
Started Jun 10 05:28:09 PM PDT 24
Finished Jun 10 05:28:10 PM PDT 24
Peak memory 205024 kb
Host smart-2f3f6c1a-7d87-4a0e-afbe-02607d6d614a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17482
39696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1748239696
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.459383921
Short name T156
Test name
Test status
Simulation time 222053711 ps
CPU time 0.95 seconds
Started Jun 10 05:27:56 PM PDT 24
Finished Jun 10 05:27:57 PM PDT 24
Peak memory 205000 kb
Host smart-203c7266-d933-4b6b-85ac-2a65779be3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45938
3921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.459383921
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1681029924
Short name T502
Test name
Test status
Simulation time 176719887 ps
CPU time 0.88 seconds
Started Jun 10 05:28:03 PM PDT 24
Finished Jun 10 05:28:04 PM PDT 24
Peak memory 204972 kb
Host smart-37c72361-41e8-4955-9883-dd93eb2ef3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16810
29924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1681029924
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1485187873
Short name T1099
Test name
Test status
Simulation time 176463701 ps
CPU time 0.81 seconds
Started Jun 10 05:27:51 PM PDT 24
Finished Jun 10 05:27:52 PM PDT 24
Peak memory 205024 kb
Host smart-e448e2c2-a734-4a04-a894-559062161d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14851
87873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1485187873
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.47690802
Short name T1734
Test name
Test status
Simulation time 203391527 ps
CPU time 0.8 seconds
Started Jun 10 05:28:13 PM PDT 24
Finished Jun 10 05:28:14 PM PDT 24
Peak memory 205008 kb
Host smart-93e52427-1ae5-44ad-b51a-d457c57e8163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47690
802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.47690802
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.3152946377
Short name T172
Test name
Test status
Simulation time 144697946 ps
CPU time 0.79 seconds
Started Jun 10 05:28:01 PM PDT 24
Finished Jun 10 05:28:02 PM PDT 24
Peak memory 205024 kb
Host smart-7a282b06-77cf-4585-a496-cb74dc6fcdb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31529
46377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.3152946377
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_eop_single_bit_handling.3701894744
Short name T19
Test name
Test status
Simulation time 180174021 ps
CPU time 0.86 seconds
Started Jun 10 05:27:59 PM PDT 24
Finished Jun 10 05:28:00 PM PDT 24
Peak memory 204992 kb
Host smart-233cf451-f5fc-4006-ab39-8da7950f5fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37018
94744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_eop_single_bit_handling.3701894744
Directory /workspace/39.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1468997466
Short name T1784
Test name
Test status
Simulation time 182849941 ps
CPU time 0.83 seconds
Started Jun 10 05:28:17 PM PDT 24
Finished Jun 10 05:28:18 PM PDT 24
Peak memory 205008 kb
Host smart-54ddad4e-8396-467b-b84b-51c0fb3b6c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14689
97466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1468997466
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3524201609
Short name T1011
Test name
Test status
Simulation time 98560072 ps
CPU time 0.73 seconds
Started Jun 10 05:28:27 PM PDT 24
Finished Jun 10 05:28:28 PM PDT 24
Peak memory 204992 kb
Host smart-564097bc-011e-4afd-931c-7bec35c758e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35242
01609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3524201609
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2000107614
Short name T216
Test name
Test status
Simulation time 24015020047 ps
CPU time 50.63 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:29:10 PM PDT 24
Peak memory 205036 kb
Host smart-c79d0990-d8a8-4b67-8e5e-25b271859325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20001
07614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2000107614
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2866567934
Short name T1083
Test name
Test status
Simulation time 145167093 ps
CPU time 0.74 seconds
Started Jun 10 05:28:26 PM PDT 24
Finished Jun 10 05:28:27 PM PDT 24
Peak memory 205024 kb
Host smart-f353f983-4511-4269-84a2-31141de60a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28665
67934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2866567934
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1837061067
Short name T796
Test name
Test status
Simulation time 254085674 ps
CPU time 0.89 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:22 PM PDT 24
Peak memory 204868 kb
Host smart-73903ea5-14a2-43db-b306-2cbee25b3aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18370
61067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1837061067
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.3042614268
Short name T1022
Test name
Test status
Simulation time 163076139 ps
CPU time 0.89 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:22 PM PDT 24
Peak memory 205032 kb
Host smart-d7069d8b-06bb-47b2-a7f2-7c21de310de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30426
14268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.3042614268
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2194401074
Short name T1799
Test name
Test status
Simulation time 175821173 ps
CPU time 0.8 seconds
Started Jun 10 05:27:59 PM PDT 24
Finished Jun 10 05:28:00 PM PDT 24
Peak memory 204992 kb
Host smart-8fc30723-04ae-4ad1-b970-3780decf0810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21944
01074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2194401074
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3810730372
Short name T1781
Test name
Test status
Simulation time 166375903 ps
CPU time 0.78 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:21 PM PDT 24
Peak memory 205028 kb
Host smart-2afcc9a4-7a6e-45fe-b03f-b72b819d269d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38107
30372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3810730372
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.3859904352
Short name T1963
Test name
Test status
Simulation time 153304950 ps
CPU time 0.79 seconds
Started Jun 10 05:28:21 PM PDT 24
Finished Jun 10 05:28:22 PM PDT 24
Peak memory 205032 kb
Host smart-561fe4e4-43bd-411d-8774-5de76cdbfe55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38599
04352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.3859904352
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1141684953
Short name T1874
Test name
Test status
Simulation time 265677970 ps
CPU time 1.06 seconds
Started Jun 10 05:28:16 PM PDT 24
Finished Jun 10 05:28:18 PM PDT 24
Peak memory 204848 kb
Host smart-0bb757c5-b99f-4da7-9ead-7abe28db5e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11416
84953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1141684953
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.4151810929
Short name T485
Test name
Test status
Simulation time 198708825 ps
CPU time 0.89 seconds
Started Jun 10 05:28:00 PM PDT 24
Finished Jun 10 05:28:01 PM PDT 24
Peak memory 204948 kb
Host smart-cf3102fe-e2fc-4bce-9f37-f519aeb571d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41518
10929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.4151810929
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1376220236
Short name T2097
Test name
Test status
Simulation time 161649442 ps
CPU time 0.82 seconds
Started Jun 10 05:27:54 PM PDT 24
Finished Jun 10 05:27:55 PM PDT 24
Peak memory 204984 kb
Host smart-d6de6e0f-43cb-4aa6-9bca-38cb2ba1d679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13762
20236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1376220236
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.2352891408
Short name T770
Test name
Test status
Simulation time 5378362806 ps
CPU time 35.91 seconds
Started Jun 10 05:27:53 PM PDT 24
Finished Jun 10 05:28:30 PM PDT 24
Peak memory 205140 kb
Host smart-4494bea8-9e7f-48e4-b10b-43a049609375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23528
91408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.2352891408
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.1864564891
Short name T954
Test name
Test status
Simulation time 276454264 ps
CPU time 0.93 seconds
Started Jun 10 05:24:42 PM PDT 24
Finished Jun 10 05:24:43 PM PDT 24
Peak memory 205016 kb
Host smart-06164bd5-de2a-4055-968c-7b3967ee5a88
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1864564891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.1864564891
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.2622680542
Short name T490
Test name
Test status
Simulation time 158329779 ps
CPU time 0.83 seconds
Started Jun 10 05:24:38 PM PDT 24
Finished Jun 10 05:24:40 PM PDT 24
Peak memory 205068 kb
Host smart-89fcf8cd-5e0a-4c47-9f0f-f532a803d3cd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2622680542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.2622680542
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.2073055473
Short name T392
Test name
Test status
Simulation time 164366939 ps
CPU time 0.86 seconds
Started Jun 10 05:24:47 PM PDT 24
Finished Jun 10 05:24:49 PM PDT 24
Peak memory 205012 kb
Host smart-667005a1-a6e5-473e-945f-fe0d70a06312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20730
55473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.2073055473
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.1647866416
Short name T998
Test name
Test status
Simulation time 3623972728 ps
CPU time 5.08 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:24:49 PM PDT 24
Peak memory 205132 kb
Host smart-99209805-3258-44fb-8308-08f39f9d7450
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1647866416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.1647866416
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.447365265
Short name T1025
Test name
Test status
Simulation time 13376448252 ps
CPU time 14.01 seconds
Started Jun 10 05:24:47 PM PDT 24
Finished Jun 10 05:25:02 PM PDT 24
Peak memory 205128 kb
Host smart-940a0966-1b13-416d-a81d-5407d5c6312d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=447365265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.447365265
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1051653325
Short name T1
Test name
Test status
Simulation time 141453268 ps
CPU time 0.78 seconds
Started Jun 10 05:24:47 PM PDT 24
Finished Jun 10 05:24:48 PM PDT 24
Peak memory 204996 kb
Host smart-31030ccc-ec3e-4f29-8c36-1099dc235890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10516
53325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1051653325
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3337407285
Short name T1254
Test name
Test status
Simulation time 158638587 ps
CPU time 0.78 seconds
Started Jun 10 05:24:31 PM PDT 24
Finished Jun 10 05:24:32 PM PDT 24
Peak memory 204964 kb
Host smart-f0568d3c-0e12-4c49-b1d3-b81dbbb2f51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33374
07285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3337407285
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.3419043966
Short name T1816
Test name
Test status
Simulation time 1275885613 ps
CPU time 3.04 seconds
Started Jun 10 05:24:31 PM PDT 24
Finished Jun 10 05:24:35 PM PDT 24
Peak memory 205100 kb
Host smart-1e615b8d-b932-42f5-946e-ca6195e77b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34190
43966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.3419043966
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.25591192
Short name T686
Test name
Test status
Simulation time 164263769 ps
CPU time 0.78 seconds
Started Jun 10 05:24:34 PM PDT 24
Finished Jun 10 05:24:35 PM PDT 24
Peak memory 205028 kb
Host smart-9d18a336-042e-4d2c-ba17-fce7b9d9cd12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25591
192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.25591192
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.4073302787
Short name T1341
Test name
Test status
Simulation time 82203485 ps
CPU time 0.75 seconds
Started Jun 10 05:24:33 PM PDT 24
Finished Jun 10 05:24:34 PM PDT 24
Peak memory 205020 kb
Host smart-731e2555-8a5e-4c3d-b9db-38808e2c7003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40733
02787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.4073302787
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2033398460
Short name T1487
Test name
Test status
Simulation time 771226154 ps
CPU time 1.91 seconds
Started Jun 10 05:24:46 PM PDT 24
Finished Jun 10 05:24:49 PM PDT 24
Peak memory 205096 kb
Host smart-847ce15c-c386-4ad5-8c69-d21977bb7b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20333
98460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2033398460
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1947620104
Short name T1856
Test name
Test status
Simulation time 192125009 ps
CPU time 1.28 seconds
Started Jun 10 05:24:33 PM PDT 24
Finished Jun 10 05:24:35 PM PDT 24
Peak memory 205076 kb
Host smart-533a7b93-6724-4228-abd3-af907ba6330d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19476
20104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1947620104
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1060133368
Short name T1348
Test name
Test status
Simulation time 233732303 ps
CPU time 0.87 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:24:45 PM PDT 24
Peak memory 205020 kb
Host smart-dbaa07e7-f093-4a97-a0c8-922750f346b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10601
33368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1060133368
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1683699603
Short name T751
Test name
Test status
Simulation time 143033363 ps
CPU time 0.72 seconds
Started Jun 10 05:24:34 PM PDT 24
Finished Jun 10 05:24:36 PM PDT 24
Peak memory 205032 kb
Host smart-26e70aba-e612-4fda-9945-2726891012c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16836
99603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1683699603
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.966792214
Short name T1502
Test name
Test status
Simulation time 221628037 ps
CPU time 0.94 seconds
Started Jun 10 05:24:32 PM PDT 24
Finished Jun 10 05:24:33 PM PDT 24
Peak memory 204884 kb
Host smart-33495c0c-e993-47d2-9e1d-a7564414d212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96679
2214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.966792214
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.2670164046
Short name T913
Test name
Test status
Simulation time 240504194 ps
CPU time 0.91 seconds
Started Jun 10 05:24:41 PM PDT 24
Finished Jun 10 05:24:43 PM PDT 24
Peak memory 205000 kb
Host smart-c3db993e-d94f-4754-b80a-cd54cf28db3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26701
64046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.2670164046
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.2821238425
Short name T1839
Test name
Test status
Simulation time 3273698278 ps
CPU time 3.98 seconds
Started Jun 10 05:24:32 PM PDT 24
Finished Jun 10 05:24:36 PM PDT 24
Peak memory 205100 kb
Host smart-dedfb0d2-f132-4b73-98e2-01f9d8847e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28212
38425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2821238425
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2137654972
Short name T440
Test name
Test status
Simulation time 194292499 ps
CPU time 0.89 seconds
Started Jun 10 05:24:46 PM PDT 24
Finished Jun 10 05:24:48 PM PDT 24
Peak memory 205012 kb
Host smart-751e8731-852e-4d2b-9350-d618405ec43a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21376
54972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2137654972
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3886119810
Short name T1179
Test name
Test status
Simulation time 11397514327 ps
CPU time 82.16 seconds
Started Jun 10 05:24:38 PM PDT 24
Finished Jun 10 05:26:01 PM PDT 24
Peak memory 205080 kb
Host smart-1045d4c1-440a-4388-b7cc-ca210ab7e686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38861
19810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3886119810
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1158829693
Short name T1193
Test name
Test status
Simulation time 183229771 ps
CPU time 0.87 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:46 PM PDT 24
Peak memory 205036 kb
Host smart-afa1181f-cc0e-432a-ad94-bd6171c42d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11588
29693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1158829693
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.1725813548
Short name T1785
Test name
Test status
Simulation time 169672806 ps
CPU time 0.8 seconds
Started Jun 10 05:24:38 PM PDT 24
Finished Jun 10 05:24:39 PM PDT 24
Peak memory 205004 kb
Host smart-2d43b379-e126-4c33-8071-12fed5516665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17258
13548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1725813548
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.3876866846
Short name T873
Test name
Test status
Simulation time 189862216 ps
CPU time 0.87 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:47 PM PDT 24
Peak memory 205008 kb
Host smart-43f61934-37f6-4004-9493-800d44c8d027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38768
66846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.3876866846
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.336751267
Short name T295
Test name
Test status
Simulation time 191270443 ps
CPU time 0.81 seconds
Started Jun 10 05:24:33 PM PDT 24
Finished Jun 10 05:24:34 PM PDT 24
Peak memory 205008 kb
Host smart-d169579b-e2c1-4431-93ad-c3f3868b3a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33675
1267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.336751267
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.888452087
Short name T1635
Test name
Test status
Simulation time 157597143 ps
CPU time 0.78 seconds
Started Jun 10 05:24:37 PM PDT 24
Finished Jun 10 05:24:38 PM PDT 24
Peak memory 205004 kb
Host smart-0caa34f2-1906-4f75-bd62-38159420cff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88845
2087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.888452087
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.4088847397
Short name T194
Test name
Test status
Simulation time 185706842 ps
CPU time 0.81 seconds
Started Jun 10 05:24:35 PM PDT 24
Finished Jun 10 05:24:36 PM PDT 24
Peak memory 205124 kb
Host smart-6e9b5958-bb7b-42ed-8470-5a4bc579ebf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40888
47397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.4088847397
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_eop_single_bit_handling.3947580031
Short name T1728
Test name
Test status
Simulation time 190501200 ps
CPU time 0.88 seconds
Started Jun 10 05:24:46 PM PDT 24
Finished Jun 10 05:24:48 PM PDT 24
Peak memory 205000 kb
Host smart-b53665fa-5a08-43bb-93d5-acc7a666e856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39475
80031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_eop_single_bit_handling.3947580031
Directory /workspace/4.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.911607440
Short name T1742
Test name
Test status
Simulation time 147584855 ps
CPU time 0.79 seconds
Started Jun 10 05:24:51 PM PDT 24
Finished Jun 10 05:24:53 PM PDT 24
Peak memory 205012 kb
Host smart-8708eeb5-d8ea-4e8f-8cb7-4b977d9e256e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91160
7440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.911607440
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3401847426
Short name T1729
Test name
Test status
Simulation time 43104552 ps
CPU time 0.65 seconds
Started Jun 10 05:24:34 PM PDT 24
Finished Jun 10 05:24:35 PM PDT 24
Peak memory 204980 kb
Host smart-02902b3a-9a9e-421c-b719-719f6afdc42b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34018
47426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3401847426
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.4058296905
Short name T249
Test name
Test status
Simulation time 9585405919 ps
CPU time 24.28 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:25:10 PM PDT 24
Peak memory 205260 kb
Host smart-b0232f91-2f37-4bc1-8c9d-84bfecf4af37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40582
96905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.4058296905
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3007979673
Short name T867
Test name
Test status
Simulation time 174362078 ps
CPU time 0.83 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:46 PM PDT 24
Peak memory 204952 kb
Host smart-15210ee3-d334-4861-8936-83bfebff189c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30079
79673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3007979673
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1464024420
Short name T355
Test name
Test status
Simulation time 278235923 ps
CPU time 0.96 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:24:45 PM PDT 24
Peak memory 204992 kb
Host smart-3d247c32-ae4e-47fc-ac22-a6dc12e6cbc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14640
24420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1464024420
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1880173622
Short name T197
Test name
Test status
Simulation time 10232735771 ps
CPU time 173.33 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:27:39 PM PDT 24
Peak memory 205296 kb
Host smart-88bb709a-7e92-4397-b869-7f5c50a27343
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1880173622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1880173622
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.4239755710
Short name T783
Test name
Test status
Simulation time 9870132039 ps
CPU time 92.41 seconds
Started Jun 10 05:24:34 PM PDT 24
Finished Jun 10 05:26:06 PM PDT 24
Peak memory 205124 kb
Host smart-402ef410-93ac-40ae-a0ac-5612dc19146b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4239755710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.4239755710
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2008824849
Short name T1180
Test name
Test status
Simulation time 16771819370 ps
CPU time 379.64 seconds
Started Jun 10 05:24:32 PM PDT 24
Finished Jun 10 05:30:52 PM PDT 24
Peak memory 205268 kb
Host smart-5137e25f-71fa-4893-ac1c-9d6ec2ab594a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2008824849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2008824849
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.3572699494
Short name T1066
Test name
Test status
Simulation time 185056816 ps
CPU time 0.85 seconds
Started Jun 10 05:24:34 PM PDT 24
Finished Jun 10 05:24:35 PM PDT 24
Peak memory 205008 kb
Host smart-bea9a6af-2b33-4876-a261-7f34e31fbbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35726
99494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.3572699494
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.4071659440
Short name T1470
Test name
Test status
Simulation time 143985250 ps
CPU time 0.73 seconds
Started Jun 10 05:24:37 PM PDT 24
Finished Jun 10 05:24:39 PM PDT 24
Peak memory 205004 kb
Host smart-3ddbaa30-77f8-45b1-bac8-b98b8b72c736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40716
59440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.4071659440
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1999674056
Short name T104
Test name
Test status
Simulation time 324791066 ps
CPU time 1.14 seconds
Started Jun 10 05:24:48 PM PDT 24
Finished Jun 10 05:24:50 PM PDT 24
Peak memory 221340 kb
Host smart-f9c20f8f-6181-45c4-ba3a-3eef61397696
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1999674056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1999674056
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.504098595
Short name T1046
Test name
Test status
Simulation time 149583402 ps
CPU time 0.84 seconds
Started Jun 10 05:24:47 PM PDT 24
Finished Jun 10 05:24:49 PM PDT 24
Peak memory 205012 kb
Host smart-0481a045-fae5-4fc9-b4be-d60b04275e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50409
8595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.504098595
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.407850433
Short name T313
Test name
Test status
Simulation time 153339149 ps
CPU time 0.79 seconds
Started Jun 10 05:24:48 PM PDT 24
Finished Jun 10 05:24:50 PM PDT 24
Peak memory 204984 kb
Host smart-e0f48ac2-8a8f-4446-b305-4298e89edc34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40785
0433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.407850433
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.703149526
Short name T1665
Test name
Test status
Simulation time 213800572 ps
CPU time 0.94 seconds
Started Jun 10 05:24:33 PM PDT 24
Finished Jun 10 05:24:35 PM PDT 24
Peak memory 205072 kb
Host smart-f8f4b173-c8b6-43c8-93eb-2d39a8383b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70314
9526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.703149526
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.729014222
Short name T1525
Test name
Test status
Simulation time 152870890 ps
CPU time 0.82 seconds
Started Jun 10 05:24:39 PM PDT 24
Finished Jun 10 05:24:40 PM PDT 24
Peak memory 204940 kb
Host smart-3ad07469-6753-46fb-9ee3-b05ae44d5300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72901
4222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.729014222
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3341261694
Short name T832
Test name
Test status
Simulation time 154297736 ps
CPU time 0.74 seconds
Started Jun 10 05:24:33 PM PDT 24
Finished Jun 10 05:24:35 PM PDT 24
Peak memory 204996 kb
Host smart-285d2fd5-feaa-4d1a-a1ce-d15b079b0edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33412
61694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3341261694
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.3379318679
Short name T2015
Test name
Test status
Simulation time 10176246601 ps
CPU time 94.63 seconds
Started Jun 10 05:24:34 PM PDT 24
Finished Jun 10 05:26:09 PM PDT 24
Peak memory 205100 kb
Host smart-70c4475a-a188-4c35-be89-75fbfbfdad88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33793
18679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.3379318679
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.715972948
Short name T1814
Test name
Test status
Simulation time 20381264263 ps
CPU time 144.22 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:27:08 PM PDT 24
Peak memory 205184 kb
Host smart-094b579d-d74c-4018-8ddc-f1950cb83148
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715972948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bu
s_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_t
raffic.715972948
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.680063386
Short name T386
Test name
Test status
Simulation time 256226058 ps
CPU time 1.02 seconds
Started Jun 10 05:28:02 PM PDT 24
Finished Jun 10 05:28:03 PM PDT 24
Peak memory 205052 kb
Host smart-03c53bf6-6c78-4530-b359-d57df0d92728
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=680063386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.680063386
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.3143763228
Short name T1258
Test name
Test status
Simulation time 154859409 ps
CPU time 0.82 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:28:21 PM PDT 24
Peak memory 205000 kb
Host smart-2e84267c-9bd3-468c-a13d-00ddb032960e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3143763228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.3143763228
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.633443161
Short name T334
Test name
Test status
Simulation time 258128168 ps
CPU time 0.88 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:22 PM PDT 24
Peak memory 205016 kb
Host smart-17eee3cb-a7cc-4746-bad7-4cac0f964a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63344
3161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.633443161
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1591891205
Short name T1906
Test name
Test status
Simulation time 4213846123 ps
CPU time 4.79 seconds
Started Jun 10 05:28:37 PM PDT 24
Finished Jun 10 05:28:42 PM PDT 24
Peak memory 205116 kb
Host smart-55ba51f9-5b6d-4b8f-9b29-d89aba4e0a7f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1591891205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.1591891205
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.336404725
Short name T1246
Test name
Test status
Simulation time 13328117103 ps
CPU time 13.66 seconds
Started Jun 10 05:28:10 PM PDT 24
Finished Jun 10 05:28:24 PM PDT 24
Peak memory 205188 kb
Host smart-7afd340d-c26a-46cf-b408-b267b3128902
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=336404725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.336404725
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.1183735654
Short name T11
Test name
Test status
Simulation time 23449802860 ps
CPU time 26.3 seconds
Started Jun 10 05:28:01 PM PDT 24
Finished Jun 10 05:28:28 PM PDT 24
Peak memory 205156 kb
Host smart-b515c54a-b1e3-4e19-820c-b8b5f611f3e8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1183735654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.1183735654
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2085023917
Short name T1598
Test name
Test status
Simulation time 158571829 ps
CPU time 0.82 seconds
Started Jun 10 05:28:00 PM PDT 24
Finished Jun 10 05:28:01 PM PDT 24
Peak memory 204884 kb
Host smart-93adcefa-b5a6-4ee7-90ff-491b67f23982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20850
23917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2085023917
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.4145200234
Short name T711
Test name
Test status
Simulation time 164437820 ps
CPU time 0.79 seconds
Started Jun 10 05:27:59 PM PDT 24
Finished Jun 10 05:28:00 PM PDT 24
Peak memory 204904 kb
Host smart-3f6872c2-2466-47ad-8672-cfd5e70f26bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41452
00234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.4145200234
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.1020498754
Short name T65
Test name
Test status
Simulation time 691319187 ps
CPU time 1.65 seconds
Started Jun 10 05:28:12 PM PDT 24
Finished Jun 10 05:28:14 PM PDT 24
Peak memory 205208 kb
Host smart-079b2c91-5e20-4761-80c7-81e689b8187c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10204
98754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.1020498754
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.2535804226
Short name T853
Test name
Test status
Simulation time 137496326 ps
CPU time 0.78 seconds
Started Jun 10 05:28:23 PM PDT 24
Finished Jun 10 05:28:24 PM PDT 24
Peak memory 205008 kb
Host smart-cb9d5949-d030-4a2e-8ff7-190aaaea8223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25358
04226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.2535804226
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.4242328277
Short name T1019
Test name
Test status
Simulation time 38843741 ps
CPU time 0.68 seconds
Started Jun 10 05:28:04 PM PDT 24
Finished Jun 10 05:28:05 PM PDT 24
Peak memory 204996 kb
Host smart-3c38eb65-c249-40ef-99cb-01b680d95030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42423
28277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.4242328277
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.4092118453
Short name T448
Test name
Test status
Simulation time 831769243 ps
CPU time 2.14 seconds
Started Jun 10 05:28:04 PM PDT 24
Finished Jun 10 05:28:07 PM PDT 24
Peak memory 205200 kb
Host smart-830a03f0-02df-4cb8-8341-23821d97d904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40921
18453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.4092118453
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1133475988
Short name T425
Test name
Test status
Simulation time 321760311 ps
CPU time 1.89 seconds
Started Jun 10 05:28:22 PM PDT 24
Finished Jun 10 05:28:24 PM PDT 24
Peak memory 204944 kb
Host smart-ce3037a1-97a9-4d13-8ecb-e3ebebd258fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11334
75988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1133475988
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.674142319
Short name T1094
Test name
Test status
Simulation time 178019453 ps
CPU time 0.79 seconds
Started Jun 10 05:28:06 PM PDT 24
Finished Jun 10 05:28:07 PM PDT 24
Peak memory 204992 kb
Host smart-e749497f-75fa-4300-bf33-1ff71244d2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67414
2319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.674142319
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1706383822
Short name T1976
Test name
Test status
Simulation time 170637915 ps
CPU time 0.78 seconds
Started Jun 10 05:28:11 PM PDT 24
Finished Jun 10 05:28:12 PM PDT 24
Peak memory 204716 kb
Host smart-e8eda33c-c2a5-4202-a4a4-4aef528ef9b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17063
83822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1706383822
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3246077090
Short name T1328
Test name
Test status
Simulation time 175379023 ps
CPU time 0.8 seconds
Started Jun 10 05:28:02 PM PDT 24
Finished Jun 10 05:28:03 PM PDT 24
Peak memory 204996 kb
Host smart-abc84e17-43fc-430a-a3fb-8a3c97023a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32460
77090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3246077090
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.142087691
Short name T661
Test name
Test status
Simulation time 207054766 ps
CPU time 0.86 seconds
Started Jun 10 05:28:24 PM PDT 24
Finished Jun 10 05:28:25 PM PDT 24
Peak memory 204992 kb
Host smart-e4c69f8e-1519-48b4-9a1c-fe955a0387f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14208
7691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.142087691
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.356263624
Short name T435
Test name
Test status
Simulation time 3291866129 ps
CPU time 3.77 seconds
Started Jun 10 05:28:03 PM PDT 24
Finished Jun 10 05:28:07 PM PDT 24
Peak memory 205068 kb
Host smart-7f742c2b-aad0-4df4-9c19-1b4711688762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35626
3624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.356263624
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3824041730
Short name T319
Test name
Test status
Simulation time 203802856 ps
CPU time 0.87 seconds
Started Jun 10 05:28:03 PM PDT 24
Finished Jun 10 05:28:05 PM PDT 24
Peak memory 205052 kb
Host smart-194a953b-863a-4f9c-af11-d935289f6c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38240
41730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3824041730
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.2746645733
Short name T158
Test name
Test status
Simulation time 9631487254 ps
CPU time 261.85 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:32:41 PM PDT 24
Peak memory 205276 kb
Host smart-931ea23e-78d6-4ff3-b524-4a21c5a577bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27466
45733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.2746645733
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3810417874
Short name T1587
Test name
Test status
Simulation time 171626907 ps
CPU time 0.81 seconds
Started Jun 10 05:28:21 PM PDT 24
Finished Jun 10 05:28:23 PM PDT 24
Peak memory 204920 kb
Host smart-2557bfe4-8865-412c-b18a-62c14e827155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38104
17874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3810417874
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1485228375
Short name T1996
Test name
Test status
Simulation time 179590339 ps
CPU time 0.84 seconds
Started Jun 10 05:28:02 PM PDT 24
Finished Jun 10 05:28:03 PM PDT 24
Peak memory 205040 kb
Host smart-d9450ce1-cfe6-4280-8379-75fdb981a0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14852
28375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1485228375
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.77835953
Short name T957
Test name
Test status
Simulation time 169402016 ps
CPU time 0.81 seconds
Started Jun 10 05:27:59 PM PDT 24
Finished Jun 10 05:28:01 PM PDT 24
Peak memory 205116 kb
Host smart-03f86fc6-0b6a-4181-9236-63b2773ee571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77835
953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.77835953
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.234639237
Short name T844
Test name
Test status
Simulation time 178587780 ps
CPU time 0.82 seconds
Started Jun 10 05:27:59 PM PDT 24
Finished Jun 10 05:28:00 PM PDT 24
Peak memory 204976 kb
Host smart-6c9afe38-a157-4ac7-8b3b-01b62eea6c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23463
9237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.234639237
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.54626067
Short name T337
Test name
Test status
Simulation time 190741610 ps
CPU time 0.83 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:28:21 PM PDT 24
Peak memory 205012 kb
Host smart-e1a17481-5098-4ff2-93d0-6f63c6941ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54626
067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.54626067
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1307167435
Short name T1869
Test name
Test status
Simulation time 176447716 ps
CPU time 0.87 seconds
Started Jun 10 05:28:02 PM PDT 24
Finished Jun 10 05:28:03 PM PDT 24
Peak memory 205008 kb
Host smart-c7e0de0f-0c18-4d81-9b0a-f4428916ae6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13071
67435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1307167435
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_eop_single_bit_handling.906396493
Short name T1823
Test name
Test status
Simulation time 149469912 ps
CPU time 0.8 seconds
Started Jun 10 05:28:08 PM PDT 24
Finished Jun 10 05:28:09 PM PDT 24
Peak memory 204928 kb
Host smart-974b69d5-895e-44e3-a93d-6e3da6fd3e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90639
6493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_eop_single_bit_handling.906396493
Directory /workspace/40.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.81171167
Short name T1270
Test name
Test status
Simulation time 144319514 ps
CPU time 0.76 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:28:21 PM PDT 24
Peak memory 205012 kb
Host smart-d92c658f-34bc-41bb-ba46-ab610bf411b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81171
167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.81171167
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3617970975
Short name T1398
Test name
Test status
Simulation time 49861001 ps
CPU time 0.69 seconds
Started Jun 10 05:28:01 PM PDT 24
Finished Jun 10 05:28:02 PM PDT 24
Peak memory 204960 kb
Host smart-7daf2a12-cbc7-4795-b6d3-32c55deb2e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36179
70975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3617970975
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.928804126
Short name T1540
Test name
Test status
Simulation time 12270915933 ps
CPU time 27.48 seconds
Started Jun 10 05:28:03 PM PDT 24
Finished Jun 10 05:28:31 PM PDT 24
Peak memory 205196 kb
Host smart-c752b977-18a6-42bd-8014-88a2eb576e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92880
4126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.928804126
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.3189170671
Short name T1519
Test name
Test status
Simulation time 175602301 ps
CPU time 0.82 seconds
Started Jun 10 05:28:22 PM PDT 24
Finished Jun 10 05:28:28 PM PDT 24
Peak memory 204984 kb
Host smart-b74ab7ab-45f4-43f7-8104-0458dd4fb72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31891
70671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3189170671
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2388211424
Short name T346
Test name
Test status
Simulation time 166369809 ps
CPU time 0.81 seconds
Started Jun 10 05:28:02 PM PDT 24
Finished Jun 10 05:28:03 PM PDT 24
Peak memory 204988 kb
Host smart-58509420-c9e8-408c-9874-10e850fd28a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23882
11424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2388211424
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.4133102548
Short name T336
Test name
Test status
Simulation time 168112089 ps
CPU time 0.79 seconds
Started Jun 10 05:28:39 PM PDT 24
Finished Jun 10 05:28:40 PM PDT 24
Peak memory 204848 kb
Host smart-777b8ba1-f50d-4faf-bfd4-6c8d22acc38f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41331
02548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.4133102548
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.1918155748
Short name T1052
Test name
Test status
Simulation time 147927910 ps
CPU time 0.73 seconds
Started Jun 10 05:28:29 PM PDT 24
Finished Jun 10 05:28:30 PM PDT 24
Peak memory 205028 kb
Host smart-924162dc-e763-43e7-b4ad-c0979e528eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19181
55748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.1918155748
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.902998050
Short name T1517
Test name
Test status
Simulation time 168242834 ps
CPU time 0.77 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:28:21 PM PDT 24
Peak memory 205004 kb
Host smart-7447100f-e00a-4bf9-bbf3-eb909cad643d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90299
8050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.902998050
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.663239306
Short name T363
Test name
Test status
Simulation time 178405092 ps
CPU time 0.8 seconds
Started Jun 10 05:28:21 PM PDT 24
Finished Jun 10 05:28:23 PM PDT 24
Peak memory 204992 kb
Host smart-a4ceb4f4-4780-42cf-9180-541db8d3f3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66323
9306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.663239306
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3296714704
Short name T1638
Test name
Test status
Simulation time 178121293 ps
CPU time 0.82 seconds
Started Jun 10 05:28:01 PM PDT 24
Finished Jun 10 05:28:02 PM PDT 24
Peak memory 205028 kb
Host smart-a289c768-cc02-452c-8d12-592eafb58a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32967
14704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3296714704
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.367170860
Short name T1286
Test name
Test status
Simulation time 159441773 ps
CPU time 0.78 seconds
Started Jun 10 05:28:21 PM PDT 24
Finished Jun 10 05:28:22 PM PDT 24
Peak memory 205012 kb
Host smart-5b6ec876-f489-4d52-876a-907db9cc6d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36717
0860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.367170860
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1341682158
Short name T309
Test name
Test status
Simulation time 146120185 ps
CPU time 0.84 seconds
Started Jun 10 05:28:07 PM PDT 24
Finished Jun 10 05:28:09 PM PDT 24
Peak memory 204988 kb
Host smart-bb32c4f2-3f10-4185-99ce-27f57cde6468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13416
82158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1341682158
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.1472161885
Short name T1095
Test name
Test status
Simulation time 8047418640 ps
CPU time 225.04 seconds
Started Jun 10 05:28:02 PM PDT 24
Finished Jun 10 05:31:48 PM PDT 24
Peak memory 205128 kb
Host smart-37d9998e-34fd-4b08-98b3-287d83f1b196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14721
61885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.1472161885
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.3999775707
Short name T1050
Test name
Test status
Simulation time 250043968 ps
CPU time 0.95 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:22 PM PDT 24
Peak memory 205020 kb
Host smart-cde5e928-4503-478e-995a-46c6a8fdcebe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3999775707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.3999775707
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.3377109818
Short name T894
Test name
Test status
Simulation time 162563041 ps
CPU time 0.81 seconds
Started Jun 10 05:28:22 PM PDT 24
Finished Jun 10 05:28:23 PM PDT 24
Peak memory 205032 kb
Host smart-ea8aeb78-4ed8-4027-9bab-53f5e1113afa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3377109818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.3377109818
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.3793913216
Short name T1762
Test name
Test status
Simulation time 235676781 ps
CPU time 0.89 seconds
Started Jun 10 05:28:21 PM PDT 24
Finished Jun 10 05:28:22 PM PDT 24
Peak memory 204988 kb
Host smart-21aa76e8-791c-402f-b087-1021b23a9d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37939
13216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.3793913216
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.1866892853
Short name T451
Test name
Test status
Simulation time 4259772325 ps
CPU time 4.8 seconds
Started Jun 10 05:28:11 PM PDT 24
Finished Jun 10 05:28:16 PM PDT 24
Peak memory 204896 kb
Host smart-e2621eee-eb63-4402-8079-35a8c4da73ab
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1866892853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.1866892853
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.3424160649
Short name T406
Test name
Test status
Simulation time 13392140031 ps
CPU time 12.81 seconds
Started Jun 10 05:28:21 PM PDT 24
Finished Jun 10 05:28:39 PM PDT 24
Peak memory 205112 kb
Host smart-c8c63180-f56e-4e79-8461-606393dc9837
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3424160649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3424160649
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.1174793000
Short name T2039
Test name
Test status
Simulation time 23351756113 ps
CPU time 24.48 seconds
Started Jun 10 05:28:10 PM PDT 24
Finished Jun 10 05:28:35 PM PDT 24
Peak memory 205048 kb
Host smart-ef82cd3e-cdea-4314-881f-bbf37b9d30b5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1174793000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.1174793000
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2862498013
Short name T1663
Test name
Test status
Simulation time 151515447 ps
CPU time 0.82 seconds
Started Jun 10 05:28:06 PM PDT 24
Finished Jun 10 05:28:07 PM PDT 24
Peak memory 205016 kb
Host smart-346ccf70-bbf0-4630-acc9-7e3b9fee8b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28624
98013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2862498013
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.311901088
Short name T1410
Test name
Test status
Simulation time 182642301 ps
CPU time 0.85 seconds
Started Jun 10 05:28:06 PM PDT 24
Finished Jun 10 05:28:07 PM PDT 24
Peak memory 204992 kb
Host smart-212e19e1-9758-42b1-9fee-296b55d2f116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31190
1088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.311901088
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.3417175743
Short name T1366
Test name
Test status
Simulation time 461029237 ps
CPU time 1.22 seconds
Started Jun 10 05:28:06 PM PDT 24
Finished Jun 10 05:28:08 PM PDT 24
Peak memory 204996 kb
Host smart-c994cd08-fb12-4676-8c36-1707a02dce01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34171
75743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.3417175743
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1080867154
Short name T1952
Test name
Test status
Simulation time 134166999 ps
CPU time 0.79 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:21 PM PDT 24
Peak memory 205048 kb
Host smart-62e437f1-d45d-49be-ae1a-fb23387a5623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10808
67154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1080867154
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.1596354605
Short name T1373
Test name
Test status
Simulation time 36600316 ps
CPU time 0.65 seconds
Started Jun 10 05:28:39 PM PDT 24
Finished Jun 10 05:28:41 PM PDT 24
Peak memory 204988 kb
Host smart-d3fd6925-e025-4b2d-b800-eb9a6e7a1eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15963
54605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.1596354605
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.594540880
Short name T663
Test name
Test status
Simulation time 783779195 ps
CPU time 1.88 seconds
Started Jun 10 05:28:45 PM PDT 24
Finished Jun 10 05:28:48 PM PDT 24
Peak memory 205124 kb
Host smart-33d58f6e-11b0-4e9e-9523-1e137e8809cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59454
0880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.594540880
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2616810902
Short name T534
Test name
Test status
Simulation time 381123472 ps
CPU time 2.14 seconds
Started Jun 10 05:28:08 PM PDT 24
Finished Jun 10 05:28:11 PM PDT 24
Peak memory 205000 kb
Host smart-edda954a-c4fd-4cb6-af50-3dde71db580e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26168
10902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2616810902
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3238061237
Short name T1987
Test name
Test status
Simulation time 222352285 ps
CPU time 0.94 seconds
Started Jun 10 05:28:51 PM PDT 24
Finished Jun 10 05:28:52 PM PDT 24
Peak memory 204904 kb
Host smart-fba11755-6118-405d-877f-227ae93e4b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32380
61237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3238061237
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1907090391
Short name T703
Test name
Test status
Simulation time 148497193 ps
CPU time 0.77 seconds
Started Jun 10 05:28:09 PM PDT 24
Finished Jun 10 05:28:10 PM PDT 24
Peak memory 205020 kb
Host smart-b9fc71db-76eb-459b-a991-90681d1ca828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19070
90391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1907090391
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.4081296652
Short name T1852
Test name
Test status
Simulation time 233388879 ps
CPU time 0.9 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:22 PM PDT 24
Peak memory 205000 kb
Host smart-ad00f49f-5f2c-4257-bec1-16e233893046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40812
96652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.4081296652
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2637975001
Short name T593
Test name
Test status
Simulation time 255257075 ps
CPU time 1 seconds
Started Jun 10 05:28:08 PM PDT 24
Finished Jun 10 05:28:09 PM PDT 24
Peak memory 204960 kb
Host smart-896e6d33-822b-430e-b3f6-0dd12f9c8869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26379
75001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2637975001
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.3162437814
Short name T883
Test name
Test status
Simulation time 3302807529 ps
CPU time 3.68 seconds
Started Jun 10 05:28:07 PM PDT 24
Finished Jun 10 05:28:12 PM PDT 24
Peak memory 205068 kb
Host smart-6be67464-8718-4df6-810f-94a962e8faf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31624
37814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.3162437814
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.334876139
Short name T1851
Test name
Test status
Simulation time 206628343 ps
CPU time 0.83 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:22 PM PDT 24
Peak memory 205024 kb
Host smart-b09510f8-7154-4882-b8fd-bb3b8ddb1d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33487
6139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.334876139
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.3490188106
Short name T1693
Test name
Test status
Simulation time 14417468204 ps
CPU time 402.19 seconds
Started Jun 10 05:28:06 PM PDT 24
Finished Jun 10 05:34:48 PM PDT 24
Peak memory 205220 kb
Host smart-4297cd92-a07c-44d0-8978-0835a251bd37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34901
88106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.3490188106
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2783887384
Short name T1062
Test name
Test status
Simulation time 194623799 ps
CPU time 0.79 seconds
Started Jun 10 05:28:11 PM PDT 24
Finished Jun 10 05:28:12 PM PDT 24
Peak memory 204932 kb
Host smart-8f98f44b-1a3b-4896-84a6-44dbd8ef7b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27838
87384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2783887384
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1373191352
Short name T1682
Test name
Test status
Simulation time 215324823 ps
CPU time 0.86 seconds
Started Jun 10 05:28:32 PM PDT 24
Finished Jun 10 05:28:33 PM PDT 24
Peak memory 205016 kb
Host smart-2130fb2b-6a44-46a9-8e61-0dc7da928d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13731
91352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1373191352
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2922293673
Short name T1249
Test name
Test status
Simulation time 188755426 ps
CPU time 0.89 seconds
Started Jun 10 05:28:09 PM PDT 24
Finished Jun 10 05:28:10 PM PDT 24
Peak memory 204992 kb
Host smart-121ed1ca-53ca-492e-958f-5196385b9e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29222
93673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2922293673
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.409209292
Short name T965
Test name
Test status
Simulation time 158156148 ps
CPU time 0.8 seconds
Started Jun 10 05:28:08 PM PDT 24
Finished Jun 10 05:28:09 PM PDT 24
Peak memory 205044 kb
Host smart-61cfaf28-b7cd-492e-8ce1-f8604e68b2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40920
9292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.409209292
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.710623189
Short name T1159
Test name
Test status
Simulation time 145896509 ps
CPU time 0.78 seconds
Started Jun 10 05:28:07 PM PDT 24
Finished Jun 10 05:28:09 PM PDT 24
Peak memory 205028 kb
Host smart-3df5412f-2258-4178-ad87-5f5430959b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71062
3189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.710623189
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2424472510
Short name T219
Test name
Test status
Simulation time 145486929 ps
CPU time 0.74 seconds
Started Jun 10 05:28:28 PM PDT 24
Finished Jun 10 05:28:29 PM PDT 24
Peak memory 205008 kb
Host smart-41925491-5962-4554-b322-1722b8b69f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24244
72510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2424472510
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_eop_single_bit_handling.3434343539
Short name T312
Test name
Test status
Simulation time 166037629 ps
CPU time 0.77 seconds
Started Jun 10 05:28:04 PM PDT 24
Finished Jun 10 05:28:05 PM PDT 24
Peak memory 204964 kb
Host smart-14328450-3cba-42ca-bb64-aaf67a7abd67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34343
43539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_eop_single_bit_handling.3434343539
Directory /workspace/41.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.341732544
Short name T67
Test name
Test status
Simulation time 175649340 ps
CPU time 0.76 seconds
Started Jun 10 05:28:23 PM PDT 24
Finished Jun 10 05:28:25 PM PDT 24
Peak memory 205012 kb
Host smart-48c86b49-3308-4022-ba53-e40732aa0d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34173
2544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.341732544
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2909754320
Short name T822
Test name
Test status
Simulation time 33724291 ps
CPU time 0.65 seconds
Started Jun 10 05:28:08 PM PDT 24
Finished Jun 10 05:28:09 PM PDT 24
Peak memory 205008 kb
Host smart-4bf54694-f106-4099-8f8b-aedcf2c6a5c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29097
54320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2909754320
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1145655314
Short name T214
Test name
Test status
Simulation time 18861277753 ps
CPU time 43.83 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:29:05 PM PDT 24
Peak memory 205204 kb
Host smart-7f1746dc-9139-4835-a392-f43aba01f88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11456
55314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1145655314
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1811967882
Short name T713
Test name
Test status
Simulation time 185502599 ps
CPU time 0.83 seconds
Started Jun 10 05:28:07 PM PDT 24
Finished Jun 10 05:28:09 PM PDT 24
Peak memory 204976 kb
Host smart-8d0c8781-d1a0-490f-a701-2fb04482818e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18119
67882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1811967882
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.1525334679
Short name T1231
Test name
Test status
Simulation time 196281626 ps
CPU time 0.88 seconds
Started Jun 10 05:28:06 PM PDT 24
Finished Jun 10 05:28:08 PM PDT 24
Peak memory 205000 kb
Host smart-d5730fc3-3c9d-4b1d-a223-1c608eab3b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15253
34679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1525334679
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.702762327
Short name T1102
Test name
Test status
Simulation time 187645837 ps
CPU time 0.86 seconds
Started Jun 10 05:28:49 PM PDT 24
Finished Jun 10 05:28:50 PM PDT 24
Peak memory 204904 kb
Host smart-10e20e0b-4677-4c89-92cb-3873a8910cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70276
2327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.702762327
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1608360811
Short name T2102
Test name
Test status
Simulation time 184018617 ps
CPU time 0.85 seconds
Started Jun 10 05:28:07 PM PDT 24
Finished Jun 10 05:28:09 PM PDT 24
Peak memory 204992 kb
Host smart-89c5161b-40e7-489c-aa33-9fcc21b7f527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16083
60811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1608360811
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3882819359
Short name T1604
Test name
Test status
Simulation time 156030912 ps
CPU time 0.79 seconds
Started Jun 10 05:28:05 PM PDT 24
Finished Jun 10 05:28:06 PM PDT 24
Peak memory 204984 kb
Host smart-12743dcd-5b0f-4c7b-a288-ac1772fe8bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38828
19359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3882819359
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.1362920412
Short name T1832
Test name
Test status
Simulation time 204768873 ps
CPU time 0.83 seconds
Started Jun 10 05:28:04 PM PDT 24
Finished Jun 10 05:28:05 PM PDT 24
Peak memory 205008 kb
Host smart-ea8e4b2a-9ad2-4639-aecd-24318f3eeacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13629
20412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.1362920412
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2962763515
Short name T1160
Test name
Test status
Simulation time 151179189 ps
CPU time 0.78 seconds
Started Jun 10 05:28:05 PM PDT 24
Finished Jun 10 05:28:06 PM PDT 24
Peak memory 204996 kb
Host smart-cbe90737-42e3-4a43-b5fd-b989c638985e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29627
63515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2962763515
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2765980132
Short name T1848
Test name
Test status
Simulation time 178459810 ps
CPU time 0.83 seconds
Started Jun 10 05:28:21 PM PDT 24
Finished Jun 10 05:28:37 PM PDT 24
Peak memory 204996 kb
Host smart-f57f4c17-104d-4875-9951-ff66c33c5d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27659
80132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2765980132
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.546672788
Short name T6
Test name
Test status
Simulation time 14806649175 ps
CPU time 109.59 seconds
Started Jun 10 05:28:05 PM PDT 24
Finished Jun 10 05:29:55 PM PDT 24
Peak memory 205168 kb
Host smart-5a9ea57a-4447-4a86-850e-3193ac4f60d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54667
2788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.546672788
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.3647383834
Short name T1677
Test name
Test status
Simulation time 315695196 ps
CPU time 0.98 seconds
Started Jun 10 05:28:12 PM PDT 24
Finished Jun 10 05:28:13 PM PDT 24
Peak memory 204920 kb
Host smart-520b1db8-c128-49f1-81f4-cfdf650caf1f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3647383834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.3647383834
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.1696643000
Short name T821
Test name
Test status
Simulation time 195341183 ps
CPU time 0.8 seconds
Started Jun 10 05:28:28 PM PDT 24
Finished Jun 10 05:28:29 PM PDT 24
Peak memory 205028 kb
Host smart-c041856a-9d40-4e8f-b2f8-abb9fe4c996a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1696643000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.1696643000
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.3383240926
Short name T362
Test name
Test status
Simulation time 280099413 ps
CPU time 0.89 seconds
Started Jun 10 05:29:00 PM PDT 24
Finished Jun 10 05:29:01 PM PDT 24
Peak memory 204836 kb
Host smart-1c224a57-58f0-48d1-8e50-da8505475efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33832
40926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.3383240926
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.211073889
Short name T7
Test name
Test status
Simulation time 3600884301 ps
CPU time 4.21 seconds
Started Jun 10 05:28:35 PM PDT 24
Finished Jun 10 05:28:40 PM PDT 24
Peak memory 205092 kb
Host smart-5970fc94-a60c-4b62-861a-3e0989819a5a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=211073889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.211073889
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.2681543491
Short name T1703
Test name
Test status
Simulation time 13477923972 ps
CPU time 12.77 seconds
Started Jun 10 05:28:12 PM PDT 24
Finished Jun 10 05:28:25 PM PDT 24
Peak memory 205280 kb
Host smart-2e839a0f-48ea-4858-b2e0-63dd41f57f67
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2681543491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.2681543491
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1311691199
Short name T326
Test name
Test status
Simulation time 23362302175 ps
CPU time 23.98 seconds
Started Jun 10 05:28:28 PM PDT 24
Finished Jun 10 05:28:52 PM PDT 24
Peak memory 205080 kb
Host smart-7fb971fe-e773-4a93-bf52-5f834d4b8abd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1311691199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.1311691199
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3938754261
Short name T1243
Test name
Test status
Simulation time 153931995 ps
CPU time 0.77 seconds
Started Jun 10 05:28:49 PM PDT 24
Finished Jun 10 05:28:50 PM PDT 24
Peak memory 204904 kb
Host smart-ea0d4a8e-6503-4c5c-bba2-3c26f88b9ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39387
54261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3938754261
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.2339321437
Short name T791
Test name
Test status
Simulation time 142381354 ps
CPU time 0.77 seconds
Started Jun 10 05:28:12 PM PDT 24
Finished Jun 10 05:28:13 PM PDT 24
Peak memory 205020 kb
Host smart-60973d88-1c96-4a37-8db0-eec51feb51bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23393
21437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.2339321437
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.216622635
Short name T1821
Test name
Test status
Simulation time 1116989104 ps
CPU time 2.54 seconds
Started Jun 10 05:28:12 PM PDT 24
Finished Jun 10 05:28:15 PM PDT 24
Peak memory 205160 kb
Host smart-ec40ba15-3f7f-4ef2-8be5-a5f601ea5aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21662
2635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.216622635
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.2905846780
Short name T1385
Test name
Test status
Simulation time 148341190 ps
CPU time 0.77 seconds
Started Jun 10 05:28:11 PM PDT 24
Finished Jun 10 05:28:12 PM PDT 24
Peak memory 204988 kb
Host smart-56468647-f085-474a-85ad-00e6e7384b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29058
46780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2905846780
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.632352610
Short name T1692
Test name
Test status
Simulation time 54925140 ps
CPU time 0.65 seconds
Started Jun 10 05:28:33 PM PDT 24
Finished Jun 10 05:28:34 PM PDT 24
Peak memory 204904 kb
Host smart-670cda18-8c42-42d4-8663-2df969c8bcf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63235
2610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.632352610
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.1356572283
Short name T345
Test name
Test status
Simulation time 825605526 ps
CPU time 1.94 seconds
Started Jun 10 05:28:39 PM PDT 24
Finished Jun 10 05:28:41 PM PDT 24
Peak memory 205088 kb
Host smart-c33e6d0c-29e4-4f38-9cbf-668b52ecd0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13565
72283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.1356572283
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2494510060
Short name T1674
Test name
Test status
Simulation time 257181571 ps
CPU time 1.54 seconds
Started Jun 10 05:28:37 PM PDT 24
Finished Jun 10 05:28:39 PM PDT 24
Peak memory 205092 kb
Host smart-06237f95-c407-4e91-884d-327268d3e0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24945
10060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2494510060
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3981277728
Short name T2071
Test name
Test status
Simulation time 202013721 ps
CPU time 0.81 seconds
Started Jun 10 05:28:47 PM PDT 24
Finished Jun 10 05:28:48 PM PDT 24
Peak memory 204808 kb
Host smart-bcaf3f70-8df1-48a6-b022-fa7493a4d8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39812
77728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3981277728
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1209461177
Short name T1686
Test name
Test status
Simulation time 144244059 ps
CPU time 0.76 seconds
Started Jun 10 05:28:10 PM PDT 24
Finished Jun 10 05:28:11 PM PDT 24
Peak memory 204976 kb
Host smart-8597e708-7920-480e-88b7-0bc7e6333ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12094
61177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1209461177
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.632615397
Short name T725
Test name
Test status
Simulation time 237406789 ps
CPU time 0.92 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:21 PM PDT 24
Peak memory 204896 kb
Host smart-7f1eba21-435a-4906-a15f-74d013835672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63261
5397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.632615397
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.512424593
Short name T1921
Test name
Test status
Simulation time 253808204 ps
CPU time 0.89 seconds
Started Jun 10 05:28:37 PM PDT 24
Finished Jun 10 05:28:38 PM PDT 24
Peak memory 204812 kb
Host smart-a3a7ddc0-19ed-4d93-bec2-e3e8da365c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51242
4593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.512424593
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.2540184858
Short name T1277
Test name
Test status
Simulation time 3333603979 ps
CPU time 3.9 seconds
Started Jun 10 05:28:31 PM PDT 24
Finished Jun 10 05:28:36 PM PDT 24
Peak memory 204876 kb
Host smart-5b42bff2-026c-4138-85ab-a066a6163004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25401
84858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2540184858
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1973147723
Short name T1795
Test name
Test status
Simulation time 182680841 ps
CPU time 0.82 seconds
Started Jun 10 05:28:13 PM PDT 24
Finished Jun 10 05:28:14 PM PDT 24
Peak memory 205044 kb
Host smart-891b6c4d-9b4a-4d2d-8bd8-b51d99f666b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19731
47723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1973147723
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.3858050759
Short name T1636
Test name
Test status
Simulation time 8405691091 ps
CPU time 73.32 seconds
Started Jun 10 05:28:33 PM PDT 24
Finished Jun 10 05:29:47 PM PDT 24
Peak memory 205040 kb
Host smart-818c04e7-2edf-46f9-8d29-49c7fe19252a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38580
50759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.3858050759
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.332954891
Short name T1413
Test name
Test status
Simulation time 152060899 ps
CPU time 0.78 seconds
Started Jun 10 05:28:30 PM PDT 24
Finished Jun 10 05:28:31 PM PDT 24
Peak memory 204908 kb
Host smart-ac789f87-3258-4870-9c71-5e69b4e02561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33295
4891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.332954891
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2356049729
Short name T2017
Test name
Test status
Simulation time 178222287 ps
CPU time 0.94 seconds
Started Jun 10 05:28:30 PM PDT 24
Finished Jun 10 05:28:32 PM PDT 24
Peak memory 204956 kb
Host smart-e045b259-9f43-42a1-8705-5b895ef9beb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23560
49729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2356049729
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2043643015
Short name T679
Test name
Test status
Simulation time 174620284 ps
CPU time 0.82 seconds
Started Jun 10 05:28:22 PM PDT 24
Finished Jun 10 05:28:23 PM PDT 24
Peak memory 204980 kb
Host smart-25f745e0-2d26-4d67-b789-214031eafc4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20436
43015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2043643015
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.298118126
Short name T1545
Test name
Test status
Simulation time 185675904 ps
CPU time 0.87 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:28:20 PM PDT 24
Peak memory 204972 kb
Host smart-a9185924-1759-422a-8945-60238bf797d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29811
8126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.298118126
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1146328349
Short name T1494
Test name
Test status
Simulation time 183567881 ps
CPU time 0.85 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:22 PM PDT 24
Peak memory 205012 kb
Host smart-63adf879-e22c-4a8a-bff1-124cb49c47f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11463
28349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1146328349
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2238106661
Short name T1873
Test name
Test status
Simulation time 151455751 ps
CPU time 0.81 seconds
Started Jun 10 05:28:18 PM PDT 24
Finished Jun 10 05:28:19 PM PDT 24
Peak memory 205020 kb
Host smart-d0987bcc-972b-468c-8557-c7f2103043f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22381
06661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2238106661
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_eop_single_bit_handling.1339538181
Short name T1861
Test name
Test status
Simulation time 169421632 ps
CPU time 0.85 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:21 PM PDT 24
Peak memory 205052 kb
Host smart-36b598f5-0a52-4db6-af49-2f7ff9457f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13395
38181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_eop_single_bit_handling.1339538181
Directory /workspace/42.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2111258754
Short name T2094
Test name
Test status
Simulation time 167989240 ps
CPU time 0.76 seconds
Started Jun 10 05:28:51 PM PDT 24
Finished Jun 10 05:28:52 PM PDT 24
Peak memory 204844 kb
Host smart-0fb24cbc-8f27-47ca-aee5-f42761ada668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21112
58754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.2111258754
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3238626526
Short name T2033
Test name
Test status
Simulation time 33230090 ps
CPU time 0.66 seconds
Started Jun 10 05:28:12 PM PDT 24
Finished Jun 10 05:28:13 PM PDT 24
Peak memory 205000 kb
Host smart-28c01ac7-9bb1-483e-acae-2a6be366b12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32386
26526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3238626526
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1939306320
Short name T1259
Test name
Test status
Simulation time 156147443 ps
CPU time 0.81 seconds
Started Jun 10 05:28:07 PM PDT 24
Finished Jun 10 05:28:09 PM PDT 24
Peak memory 204932 kb
Host smart-76bfd55c-222c-4632-8f4c-83f21d359bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19393
06320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1939306320
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1888356849
Short name T373
Test name
Test status
Simulation time 155036475 ps
CPU time 0.8 seconds
Started Jun 10 05:28:26 PM PDT 24
Finished Jun 10 05:28:27 PM PDT 24
Peak memory 205028 kb
Host smart-babf3e3f-c96d-4aad-83a7-854cb9fb8134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18883
56849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1888356849
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.185517318
Short name T1126
Test name
Test status
Simulation time 174265435 ps
CPU time 0.81 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:21 PM PDT 24
Peak memory 204980 kb
Host smart-8ba01c99-bc62-406d-8bab-8016764d650d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18551
7318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.185517318
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.3863708522
Short name T896
Test name
Test status
Simulation time 215583575 ps
CPU time 0.83 seconds
Started Jun 10 05:28:09 PM PDT 24
Finished Jun 10 05:28:10 PM PDT 24
Peak memory 205120 kb
Host smart-e540ded4-2c88-4b95-bb71-9eddef51406e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38637
08522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.3863708522
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3502292527
Short name T1842
Test name
Test status
Simulation time 195975184 ps
CPU time 0.9 seconds
Started Jun 10 05:28:10 PM PDT 24
Finished Jun 10 05:28:12 PM PDT 24
Peak memory 205032 kb
Host smart-eb20ea6b-2ab1-4046-9ff7-cdd214105144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35022
92527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3502292527
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.697528869
Short name T674
Test name
Test status
Simulation time 151602819 ps
CPU time 0.77 seconds
Started Jun 10 05:28:52 PM PDT 24
Finished Jun 10 05:28:53 PM PDT 24
Peak memory 205020 kb
Host smart-f7a5ed36-81df-4b73-b03d-5f43c30e2370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69752
8869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.697528869
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2143791242
Short name T1342
Test name
Test status
Simulation time 233091268 ps
CPU time 0.98 seconds
Started Jun 10 05:28:12 PM PDT 24
Finished Jun 10 05:28:14 PM PDT 24
Peak memory 205008 kb
Host smart-9c06199b-b8e7-43e4-b102-9d8a775256be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21437
91242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2143791242
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.435120880
Short name T1965
Test name
Test status
Simulation time 172609601 ps
CPU time 0.81 seconds
Started Jun 10 05:28:10 PM PDT 24
Finished Jun 10 05:28:11 PM PDT 24
Peak memory 205020 kb
Host smart-5d8fe399-419b-46e9-81b4-26ffe74b345d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43512
0880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.435120880
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.865649469
Short name T338
Test name
Test status
Simulation time 213451184 ps
CPU time 0.85 seconds
Started Jun 10 05:28:18 PM PDT 24
Finished Jun 10 05:28:19 PM PDT 24
Peak memory 205024 kb
Host smart-faa28e05-733f-43eb-abb8-1340ab952a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86564
9469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.865649469
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.64056400
Short name T446
Test name
Test status
Simulation time 7935196424 ps
CPU time 233.11 seconds
Started Jun 10 05:28:11 PM PDT 24
Finished Jun 10 05:32:05 PM PDT 24
Peak memory 205220 kb
Host smart-ad9684b1-1710-4baf-b659-ca5cd9f5bdfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64056
400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.64056400
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.3893775971
Short name T375
Test name
Test status
Simulation time 278269578 ps
CPU time 0.91 seconds
Started Jun 10 05:28:48 PM PDT 24
Finished Jun 10 05:28:49 PM PDT 24
Peak memory 205012 kb
Host smart-f4b7c1b8-3669-4399-a5ba-cc5d2b7ac5eb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3893775971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.3893775971
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.332747707
Short name T1790
Test name
Test status
Simulation time 196146181 ps
CPU time 0.82 seconds
Started Jun 10 05:28:46 PM PDT 24
Finished Jun 10 05:28:47 PM PDT 24
Peak memory 205016 kb
Host smart-f03d4cf8-5157-4cad-9619-bbf1a1ab98eb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=332747707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.332747707
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.3535658684
Short name T2111
Test name
Test status
Simulation time 194688879 ps
CPU time 0.86 seconds
Started Jun 10 05:28:18 PM PDT 24
Finished Jun 10 05:28:19 PM PDT 24
Peak memory 204984 kb
Host smart-ed429d22-0263-4ebf-85b4-e72787a5739c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35356
58684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.3535658684
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.4248702066
Short name T937
Test name
Test status
Simulation time 13381213522 ps
CPU time 13.54 seconds
Started Jun 10 05:28:45 PM PDT 24
Finished Jun 10 05:28:59 PM PDT 24
Peak memory 204896 kb
Host smart-a956ea64-6073-4708-8fbb-e084384697a2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4248702066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.4248702066
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.1000413787
Short name T361
Test name
Test status
Simulation time 23374705449 ps
CPU time 24.12 seconds
Started Jun 10 05:28:29 PM PDT 24
Finished Jun 10 05:28:53 PM PDT 24
Peak memory 205068 kb
Host smart-8c729577-940e-4ecb-b269-4aee4e528697
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1000413787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.1000413787
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1309587017
Short name T1777
Test name
Test status
Simulation time 166066356 ps
CPU time 0.81 seconds
Started Jun 10 05:28:10 PM PDT 24
Finished Jun 10 05:28:11 PM PDT 24
Peak memory 204976 kb
Host smart-91e6e50c-9ed1-47bb-85ec-77890821575b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13095
87017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1309587017
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.2055957543
Short name T1562
Test name
Test status
Simulation time 170837476 ps
CPU time 0.77 seconds
Started Jun 10 05:28:40 PM PDT 24
Finished Jun 10 05:28:41 PM PDT 24
Peak memory 204908 kb
Host smart-33a6a160-1535-4c9d-b0b3-0a416caf61a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20559
57543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.2055957543
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1196175230
Short name T213
Test name
Test status
Simulation time 570762969 ps
CPU time 1.46 seconds
Started Jun 10 05:28:37 PM PDT 24
Finished Jun 10 05:28:39 PM PDT 24
Peak memory 205052 kb
Host smart-63475537-c2e3-49bb-bf55-0b241c5cee7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11961
75230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1196175230
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3611822182
Short name T1263
Test name
Test status
Simulation time 148683745 ps
CPU time 0.79 seconds
Started Jun 10 05:28:14 PM PDT 24
Finished Jun 10 05:28:16 PM PDT 24
Peak memory 204996 kb
Host smart-5786122e-a922-4101-9ffd-314705f28278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36118
22182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3611822182
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1095575481
Short name T1532
Test name
Test status
Simulation time 33595909 ps
CPU time 0.67 seconds
Started Jun 10 05:28:27 PM PDT 24
Finished Jun 10 05:28:28 PM PDT 24
Peak memory 204996 kb
Host smart-9e8ec543-2ed2-477e-a236-bc7a287b92b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10955
75481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1095575481
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.3539324102
Short name T1476
Test name
Test status
Simulation time 954262854 ps
CPU time 2.14 seconds
Started Jun 10 05:28:26 PM PDT 24
Finished Jun 10 05:28:29 PM PDT 24
Peak memory 205064 kb
Host smart-c5709600-bd4a-4174-9bfe-bd09785e2b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35393
24102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.3539324102
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1273495467
Short name T817
Test name
Test status
Simulation time 268671136 ps
CPU time 1.59 seconds
Started Jun 10 05:28:21 PM PDT 24
Finished Jun 10 05:28:23 PM PDT 24
Peak memory 205068 kb
Host smart-26cc52bb-c564-4f2a-b487-4082142ae663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12734
95467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1273495467
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.3129655634
Short name T669
Test name
Test status
Simulation time 152949199 ps
CPU time 0.81 seconds
Started Jun 10 05:28:17 PM PDT 24
Finished Jun 10 05:28:18 PM PDT 24
Peak memory 204980 kb
Host smart-03dacf5a-3545-4e46-a3e8-c889a560f651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31296
55634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3129655634
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3909063541
Short name T1721
Test name
Test status
Simulation time 143050228 ps
CPU time 0.84 seconds
Started Jun 10 05:28:17 PM PDT 24
Finished Jun 10 05:28:19 PM PDT 24
Peak memory 204968 kb
Host smart-a4e34072-c1b1-490d-8ae5-c12f3982d062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39090
63541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3909063541
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.2604755864
Short name T664
Test name
Test status
Simulation time 211245830 ps
CPU time 0.86 seconds
Started Jun 10 05:28:27 PM PDT 24
Finished Jun 10 05:28:33 PM PDT 24
Peak memory 204880 kb
Host smart-3cc0e897-f0f4-473a-a3b8-9a787b235991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26047
55864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.2604755864
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.3938718716
Short name T1155
Test name
Test status
Simulation time 193383315 ps
CPU time 0.85 seconds
Started Jun 10 05:28:32 PM PDT 24
Finished Jun 10 05:28:38 PM PDT 24
Peak memory 204912 kb
Host smart-52eaeda3-8b00-4426-9613-fdf2902bdbd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39387
18716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3938718716
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.2244478089
Short name T1789
Test name
Test status
Simulation time 3298063532 ps
CPU time 3.97 seconds
Started Jun 10 05:28:18 PM PDT 24
Finished Jun 10 05:28:23 PM PDT 24
Peak memory 205052 kb
Host smart-9f04b558-380d-4cb4-b8a8-a54aebbd3795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22444
78089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.2244478089
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2069109532
Short name T1462
Test name
Test status
Simulation time 191573011 ps
CPU time 0.86 seconds
Started Jun 10 05:28:48 PM PDT 24
Finished Jun 10 05:28:49 PM PDT 24
Peak memory 205040 kb
Host smart-d7bdbdc0-fb35-41e8-9a73-cbfa6726146c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20691
09532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2069109532
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.2591593901
Short name T627
Test name
Test status
Simulation time 5164342030 ps
CPU time 148.98 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:30:49 PM PDT 24
Peak memory 205208 kb
Host smart-ebdbdfc3-0cbe-4058-8221-a3df7883f29f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25915
93901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.2591593901
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1810789793
Short name T699
Test name
Test status
Simulation time 160840459 ps
CPU time 0.78 seconds
Started Jun 10 05:28:39 PM PDT 24
Finished Jun 10 05:28:40 PM PDT 24
Peak memory 205020 kb
Host smart-c16acdb5-9638-43ea-8b27-bc6b0b4fea7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18107
89793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1810789793
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2268093448
Short name T151
Test name
Test status
Simulation time 230730403 ps
CPU time 0.86 seconds
Started Jun 10 05:28:14 PM PDT 24
Finished Jun 10 05:28:16 PM PDT 24
Peak memory 204980 kb
Host smart-3ffb5ab1-87ec-4715-aeff-1f267ba6e2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22680
93448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2268093448
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.3584841794
Short name T1667
Test name
Test status
Simulation time 181776827 ps
CPU time 0.86 seconds
Started Jun 10 05:28:14 PM PDT 24
Finished Jun 10 05:28:15 PM PDT 24
Peak memory 205024 kb
Host smart-cad3a295-261d-4bb9-b3e8-6e9e7e018bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35848
41794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.3584841794
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2186193257
Short name T340
Test name
Test status
Simulation time 170168888 ps
CPU time 0.78 seconds
Started Jun 10 05:28:14 PM PDT 24
Finished Jun 10 05:28:15 PM PDT 24
Peak memory 205036 kb
Host smart-35757205-7a7a-47b4-8846-361c9f0070cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21861
93257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2186193257
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.879565271
Short name T477
Test name
Test status
Simulation time 217595264 ps
CPU time 0.9 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:28:20 PM PDT 24
Peak memory 204944 kb
Host smart-28f22044-2b8e-49b5-bce3-08d405abbd57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87956
5271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.879565271
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.837954002
Short name T183
Test name
Test status
Simulation time 148316920 ps
CPU time 0.84 seconds
Started Jun 10 05:28:20 PM PDT 24
Finished Jun 10 05:28:21 PM PDT 24
Peak memory 205008 kb
Host smart-1c666d54-3084-464a-8bc4-9947c29e4412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83795
4002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.837954002
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_eop_single_bit_handling.1001970074
Short name T824
Test name
Test status
Simulation time 169869566 ps
CPU time 0.79 seconds
Started Jun 10 05:28:57 PM PDT 24
Finished Jun 10 05:28:58 PM PDT 24
Peak memory 205044 kb
Host smart-43738291-a091-481b-abfa-976a6b563e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10019
70074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_eop_single_bit_handling.1001970074
Directory /workspace/43.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2196005717
Short name T400
Test name
Test status
Simulation time 158735057 ps
CPU time 0.83 seconds
Started Jun 10 05:28:13 PM PDT 24
Finished Jun 10 05:28:14 PM PDT 24
Peak memory 205008 kb
Host smart-049f302d-2129-49d7-b7b5-6989ebd11f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21960
05717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2196005717
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.51635994
Short name T27
Test name
Test status
Simulation time 39883377 ps
CPU time 0.67 seconds
Started Jun 10 05:28:37 PM PDT 24
Finished Jun 10 05:28:39 PM PDT 24
Peak memory 205008 kb
Host smart-2235066e-9ef6-4ad6-87b2-d3b6d3efb228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51635
994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.51635994
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.680506685
Short name T2096
Test name
Test status
Simulation time 12545543397 ps
CPU time 28.73 seconds
Started Jun 10 05:28:48 PM PDT 24
Finished Jun 10 05:29:22 PM PDT 24
Peak memory 205184 kb
Host smart-47a4dd90-00f7-4602-b1af-d025746fccc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68050
6685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.680506685
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.640132630
Short name T1612
Test name
Test status
Simulation time 179001238 ps
CPU time 0.81 seconds
Started Jun 10 05:28:40 PM PDT 24
Finished Jun 10 05:28:42 PM PDT 24
Peak memory 204988 kb
Host smart-2b6fc2ce-c4fe-460a-976d-1ebb0479e09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64013
2630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.640132630
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2618966454
Short name T1518
Test name
Test status
Simulation time 287222922 ps
CPU time 0.93 seconds
Started Jun 10 05:28:23 PM PDT 24
Finished Jun 10 05:28:25 PM PDT 24
Peak memory 204984 kb
Host smart-c685f8b3-e88e-4610-9e4f-57b67dda655e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26189
66454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2618966454
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.2483878890
Short name T1576
Test name
Test status
Simulation time 174326345 ps
CPU time 0.81 seconds
Started Jun 10 05:28:14 PM PDT 24
Finished Jun 10 05:28:15 PM PDT 24
Peak memory 205008 kb
Host smart-c20d714d-e1df-48df-b5fd-bca9267fb9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24838
78890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.2483878890
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3089244423
Short name T1961
Test name
Test status
Simulation time 138166345 ps
CPU time 0.71 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:28:20 PM PDT 24
Peak memory 204812 kb
Host smart-814ead49-f9d3-4996-9ead-3ddca23dd9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30892
44423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3089244423
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.435716734
Short name T735
Test name
Test status
Simulation time 167497527 ps
CPU time 0.77 seconds
Started Jun 10 05:28:46 PM PDT 24
Finished Jun 10 05:28:47 PM PDT 24
Peak memory 205012 kb
Host smart-aafcfe43-8f7d-4c32-92dc-3f061b8da636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43571
6734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.435716734
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3421519433
Short name T683
Test name
Test status
Simulation time 174681378 ps
CPU time 0.81 seconds
Started Jun 10 05:28:15 PM PDT 24
Finished Jun 10 05:28:16 PM PDT 24
Peak memory 204964 kb
Host smart-bf59e524-fb01-40c4-8312-cb339c723b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34215
19433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3421519433
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2607101224
Short name T1561
Test name
Test status
Simulation time 214913882 ps
CPU time 0.9 seconds
Started Jun 10 05:28:41 PM PDT 24
Finished Jun 10 05:28:43 PM PDT 24
Peak memory 204900 kb
Host smart-29e70c4f-4877-4fcc-bcf6-2c33cb609911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26071
01224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2607101224
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1586863679
Short name T1089
Test name
Test status
Simulation time 160916853 ps
CPU time 0.8 seconds
Started Jun 10 05:28:34 PM PDT 24
Finished Jun 10 05:28:35 PM PDT 24
Peak memory 205048 kb
Host smart-e0d8b61b-a408-4382-aa6c-816f55eb24cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15868
63679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1586863679
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2949540190
Short name T1017
Test name
Test status
Simulation time 170455187 ps
CPU time 0.82 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:28:20 PM PDT 24
Peak memory 205020 kb
Host smart-050cbb7f-76ee-4da2-b2a1-fd978e928dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29495
40190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2949540190
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.2332561289
Short name T675
Test name
Test status
Simulation time 7102426079 ps
CPU time 65.77 seconds
Started Jun 10 05:28:19 PM PDT 24
Finished Jun 10 05:29:25 PM PDT 24
Peak memory 205184 kb
Host smart-deaab302-7043-489b-b518-006ccd57bb69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23325
61289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.2332561289
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.2877351975
Short name T1292
Test name
Test status
Simulation time 246483732 ps
CPU time 0.94 seconds
Started Jun 10 05:28:42 PM PDT 24
Finished Jun 10 05:28:43 PM PDT 24
Peak memory 204924 kb
Host smart-c9700bdd-8162-4b76-a115-73d8fb59f243
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2877351975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.2877351975
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.526927676
Short name T746
Test name
Test status
Simulation time 167167246 ps
CPU time 0.83 seconds
Started Jun 10 05:28:55 PM PDT 24
Finished Jun 10 05:28:56 PM PDT 24
Peak memory 205012 kb
Host smart-20d12a9c-9ee3-498e-aaeb-174beb8b80b9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=526927676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.526927676
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.1345302303
Short name T356
Test name
Test status
Simulation time 204065893 ps
CPU time 0.88 seconds
Started Jun 10 05:28:23 PM PDT 24
Finished Jun 10 05:28:24 PM PDT 24
Peak memory 205140 kb
Host smart-f6bea433-a8d5-40f9-b0ea-bbefaeb47c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13453
02303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.1345302303
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2722332133
Short name T226
Test name
Test status
Simulation time 3944895707 ps
CPU time 6.06 seconds
Started Jun 10 05:28:39 PM PDT 24
Finished Jun 10 05:28:46 PM PDT 24
Peak memory 205292 kb
Host smart-0ec69cdc-6f2d-44c3-a847-28669cbd12d6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2722332133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.2722332133
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.3707933446
Short name T1491
Test name
Test status
Simulation time 13400466467 ps
CPU time 12.77 seconds
Started Jun 10 05:28:29 PM PDT 24
Finished Jun 10 05:28:42 PM PDT 24
Peak memory 205112 kb
Host smart-cc61d1b2-4339-4044-a705-3f559dda06cf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3707933446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.3707933446
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2943681877
Short name T1439
Test name
Test status
Simulation time 23343905688 ps
CPU time 23.24 seconds
Started Jun 10 05:28:52 PM PDT 24
Finished Jun 10 05:29:21 PM PDT 24
Peak memory 204932 kb
Host smart-568222d6-c7a7-41fd-8b94-328d12fee4ac
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2943681877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.2943681877
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2717634181
Short name T1304
Test name
Test status
Simulation time 203408830 ps
CPU time 0.8 seconds
Started Jun 10 05:28:17 PM PDT 24
Finished Jun 10 05:28:19 PM PDT 24
Peak memory 204884 kb
Host smart-5021ea58-5cf8-46f2-9ec2-da92647c32b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27176
34181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2717634181
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.3753721633
Short name T712
Test name
Test status
Simulation time 248469233 ps
CPU time 0.87 seconds
Started Jun 10 05:28:21 PM PDT 24
Finished Jun 10 05:28:23 PM PDT 24
Peak memory 204988 kb
Host smart-6265aceb-22f3-4333-b5a6-5af400b811d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37537
21633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.3753721633
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2904638008
Short name T1546
Test name
Test status
Simulation time 543916894 ps
CPU time 1.63 seconds
Started Jun 10 05:28:23 PM PDT 24
Finished Jun 10 05:28:25 PM PDT 24
Peak memory 205096 kb
Host smart-baee782d-ae70-4828-9b02-9131d0d50014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29046
38008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2904638008
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.407779415
Short name T1127
Test name
Test status
Simulation time 189348499 ps
CPU time 0.82 seconds
Started Jun 10 05:28:28 PM PDT 24
Finished Jun 10 05:28:30 PM PDT 24
Peak memory 205028 kb
Host smart-853769cb-1710-4d2d-bd73-b1b8f6dec7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40777
9415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.407779415
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.3269059952
Short name T1114
Test name
Test status
Simulation time 56853556 ps
CPU time 0.69 seconds
Started Jun 10 05:28:28 PM PDT 24
Finished Jun 10 05:28:29 PM PDT 24
Peak memory 204976 kb
Host smart-1b823e7d-a1d8-4d1c-bab2-e3aa5e7f75cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32690
59952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3269059952
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1687494906
Short name T738
Test name
Test status
Simulation time 1078141196 ps
CPU time 2.58 seconds
Started Jun 10 05:28:41 PM PDT 24
Finished Jun 10 05:28:45 PM PDT 24
Peak memory 204964 kb
Host smart-0390fa77-9304-4d5c-b77f-789378affdc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16874
94906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1687494906
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3165487524
Short name T620
Test name
Test status
Simulation time 248389063 ps
CPU time 1.76 seconds
Started Jun 10 05:28:26 PM PDT 24
Finished Jun 10 05:28:28 PM PDT 24
Peak memory 205156 kb
Host smart-de81aee2-6b40-4b12-98ba-f7c2d4796afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31654
87524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3165487524
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2784939941
Short name T696
Test name
Test status
Simulation time 247328035 ps
CPU time 0.88 seconds
Started Jun 10 05:28:38 PM PDT 24
Finished Jun 10 05:28:39 PM PDT 24
Peak memory 204984 kb
Host smart-d6e171c1-e91f-4e79-9258-0f17e002261c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27849
39941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2784939941
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.1772058276
Short name T1167
Test name
Test status
Simulation time 134969599 ps
CPU time 0.73 seconds
Started Jun 10 05:28:22 PM PDT 24
Finished Jun 10 05:28:23 PM PDT 24
Peak memory 205036 kb
Host smart-45cd0ce7-9713-4050-a427-b7b94c22621e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17720
58276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1772058276
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2036536819
Short name T979
Test name
Test status
Simulation time 255105597 ps
CPU time 0.9 seconds
Started Jun 10 05:28:54 PM PDT 24
Finished Jun 10 05:28:56 PM PDT 24
Peak memory 205040 kb
Host smart-582ac2df-645b-4a9d-8863-e3e1dd16d505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20365
36819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2036536819
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.4165723808
Short name T1190
Test name
Test status
Simulation time 264296690 ps
CPU time 0.95 seconds
Started Jun 10 05:28:21 PM PDT 24
Finished Jun 10 05:28:23 PM PDT 24
Peak memory 204984 kb
Host smart-3a994d36-b32a-44f8-b0c1-a0e003fcf6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41657
23808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.4165723808
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.1100998382
Short name T376
Test name
Test status
Simulation time 3256614945 ps
CPU time 4.62 seconds
Started Jun 10 05:28:28 PM PDT 24
Finished Jun 10 05:28:33 PM PDT 24
Peak memory 205004 kb
Host smart-80040c54-40eb-4d46-8bdc-6ec0fa1f36ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11009
98382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.1100998382
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1612051763
Short name T1233
Test name
Test status
Simulation time 195573635 ps
CPU time 1.01 seconds
Started Jun 10 05:28:23 PM PDT 24
Finished Jun 10 05:28:25 PM PDT 24
Peak memory 205008 kb
Host smart-6463cdd9-d176-4cb5-b44a-2c1c9b5919df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16120
51763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1612051763
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3030460630
Short name T316
Test name
Test status
Simulation time 7510691109 ps
CPU time 70.89 seconds
Started Jun 10 05:28:29 PM PDT 24
Finished Jun 10 05:29:41 PM PDT 24
Peak memory 205256 kb
Host smart-817f4258-8561-4849-8d41-63401da8fcb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30304
60630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3030460630
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2865414226
Short name T1881
Test name
Test status
Simulation time 175076845 ps
CPU time 0.8 seconds
Started Jun 10 05:28:28 PM PDT 24
Finished Jun 10 05:28:29 PM PDT 24
Peak memory 205028 kb
Host smart-62fc9e06-653f-4e7f-90d4-8cf69a8c8873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28654
14226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2865414226
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2602437728
Short name T131
Test name
Test status
Simulation time 242576022 ps
CPU time 0.96 seconds
Started Jun 10 05:28:18 PM PDT 24
Finished Jun 10 05:28:20 PM PDT 24
Peak memory 205056 kb
Host smart-875b6436-3de6-43db-879d-6242343d7cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26024
37728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2602437728
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2195334118
Short name T654
Test name
Test status
Simulation time 167896333 ps
CPU time 0.82 seconds
Started Jun 10 05:28:51 PM PDT 24
Finished Jun 10 05:28:52 PM PDT 24
Peak memory 205044 kb
Host smart-9f76bbf0-968a-4b27-9990-b5e039a90875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21953
34118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2195334118
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.1085748196
Short name T438
Test name
Test status
Simulation time 170499633 ps
CPU time 0.8 seconds
Started Jun 10 05:28:59 PM PDT 24
Finished Jun 10 05:29:00 PM PDT 24
Peak memory 204844 kb
Host smart-f9be0c4c-acbd-478e-a586-3b575bbca957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10857
48196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1085748196
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3205806836
Short name T1752
Test name
Test status
Simulation time 155188033 ps
CPU time 0.82 seconds
Started Jun 10 05:28:17 PM PDT 24
Finished Jun 10 05:28:18 PM PDT 24
Peak memory 204888 kb
Host smart-ee9cd04f-1ae6-457c-a9bf-fa24cf177f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32058
06836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3205806836
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1586919397
Short name T1455
Test name
Test status
Simulation time 159427690 ps
CPU time 0.77 seconds
Started Jun 10 05:28:32 PM PDT 24
Finished Jun 10 05:28:33 PM PDT 24
Peak memory 205036 kb
Host smart-d5ee3b58-36dd-454a-9380-3c0cf86bcaaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15869
19397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1586919397
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_eop_single_bit_handling.3671879221
Short name T1118
Test name
Test status
Simulation time 158792401 ps
CPU time 0.81 seconds
Started Jun 10 05:28:24 PM PDT 24
Finished Jun 10 05:28:25 PM PDT 24
Peak memory 205012 kb
Host smart-f168ecb8-4a70-4359-a603-2b7674269f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36718
79221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_eop_single_bit_handling.3671879221
Directory /workspace/44.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1357337608
Short name T101
Test name
Test status
Simulation time 141664996 ps
CPU time 0.77 seconds
Started Jun 10 05:28:56 PM PDT 24
Finished Jun 10 05:28:57 PM PDT 24
Peak memory 205036 kb
Host smart-d79fec85-68e2-4031-b02f-265c11d20665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13573
37608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1357337608
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3777993788
Short name T1915
Test name
Test status
Simulation time 49044180 ps
CPU time 0.65 seconds
Started Jun 10 05:28:35 PM PDT 24
Finished Jun 10 05:28:36 PM PDT 24
Peak memory 204980 kb
Host smart-e5ef2cdb-e762-41da-a7e3-904a6e14ab5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37779
93788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3777993788
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1423244538
Short name T1452
Test name
Test status
Simulation time 10894035510 ps
CPU time 25.48 seconds
Started Jun 10 05:28:23 PM PDT 24
Finished Jun 10 05:28:49 PM PDT 24
Peak memory 205268 kb
Host smart-8cfe596e-bc89-4c80-9a13-64ef741fb148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14232
44538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1423244538
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.4005686084
Short name T420
Test name
Test status
Simulation time 182472635 ps
CPU time 0.94 seconds
Started Jun 10 05:28:23 PM PDT 24
Finished Jun 10 05:28:24 PM PDT 24
Peak memory 205144 kb
Host smart-533f6da8-5c77-4b03-9e2f-fc41c5394b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40056
86084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.4005686084
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3660715844
Short name T1531
Test name
Test status
Simulation time 199347289 ps
CPU time 0.9 seconds
Started Jun 10 05:28:26 PM PDT 24
Finished Jun 10 05:28:27 PM PDT 24
Peak memory 205000 kb
Host smart-44d54a32-79d6-4e01-abf5-54d3afc790ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36607
15844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3660715844
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.3906134134
Short name T489
Test name
Test status
Simulation time 157316306 ps
CPU time 0.83 seconds
Started Jun 10 05:28:41 PM PDT 24
Finished Jun 10 05:28:43 PM PDT 24
Peak memory 204992 kb
Host smart-4daf86d1-6953-48e1-86d0-f413f27bb431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39061
34134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.3906134134
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.2872637589
Short name T2074
Test name
Test status
Simulation time 148689321 ps
CPU time 0.78 seconds
Started Jun 10 05:28:24 PM PDT 24
Finished Jun 10 05:28:25 PM PDT 24
Peak memory 204992 kb
Host smart-ceb5719a-51bc-41c2-8b4c-3158b867e2e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28726
37589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.2872637589
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2688625254
Short name T1599
Test name
Test status
Simulation time 156350740 ps
CPU time 0.79 seconds
Started Jun 10 05:28:56 PM PDT 24
Finished Jun 10 05:28:58 PM PDT 24
Peak memory 205008 kb
Host smart-a813c16f-7e32-44f6-a6a6-feff6933b94b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26886
25254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2688625254
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2591012055
Short name T823
Test name
Test status
Simulation time 148374204 ps
CPU time 0.77 seconds
Started Jun 10 05:28:25 PM PDT 24
Finished Jun 10 05:28:26 PM PDT 24
Peak memory 205000 kb
Host smart-a62dc68f-ff73-4727-a9b2-8be6f39e3143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25910
12055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2591012055
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.51714628
Short name T48
Test name
Test status
Simulation time 182736437 ps
CPU time 0.83 seconds
Started Jun 10 05:28:17 PM PDT 24
Finished Jun 10 05:28:18 PM PDT 24
Peak memory 205040 kb
Host smart-ec25e965-2a2a-4389-a70f-a97808653451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51714
628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.51714628
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1748884768
Short name T1335
Test name
Test status
Simulation time 171478775 ps
CPU time 0.8 seconds
Started Jun 10 05:28:27 PM PDT 24
Finished Jun 10 05:28:28 PM PDT 24
Peak memory 204932 kb
Host smart-7fad621e-1aa3-4f1e-817f-f81667285dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17488
84768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1748884768
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3670853174
Short name T784
Test name
Test status
Simulation time 149213825 ps
CPU time 0.78 seconds
Started Jun 10 05:28:54 PM PDT 24
Finished Jun 10 05:28:55 PM PDT 24
Peak memory 204988 kb
Host smart-78b5048e-6686-4216-be7c-c680ed7d9f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36708
53174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3670853174
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.9058490
Short name T500
Test name
Test status
Simulation time 13188402884 ps
CPU time 95.04 seconds
Started Jun 10 05:28:40 PM PDT 24
Finished Jun 10 05:30:16 PM PDT 24
Peak memory 205244 kb
Host smart-bbefc2c0-5afa-45a8-a69a-f96a05ca262c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90584
90 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.9058490
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.2667692646
Short name T950
Test name
Test status
Simulation time 248289460 ps
CPU time 0.91 seconds
Started Jun 10 05:29:12 PM PDT 24
Finished Jun 10 05:29:13 PM PDT 24
Peak memory 205024 kb
Host smart-c676f25d-9d1a-425f-ba1e-7f1b4a39da42
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2667692646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.2667692646
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.2121767074
Short name T1073
Test name
Test status
Simulation time 150457125 ps
CPU time 0.76 seconds
Started Jun 10 05:28:40 PM PDT 24
Finished Jun 10 05:28:42 PM PDT 24
Peak memory 205008 kb
Host smart-1f785733-6100-4249-8516-714441dedf07
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2121767074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.2121767074
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.3106813864
Short name T487
Test name
Test status
Simulation time 177386606 ps
CPU time 0.83 seconds
Started Jun 10 05:28:58 PM PDT 24
Finished Jun 10 05:28:59 PM PDT 24
Peak memory 205024 kb
Host smart-a4968ad8-ce7c-47a4-a3cc-4b25bd5ea2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31068
13864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.3106813864
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1840126821
Short name T1198
Test name
Test status
Simulation time 3432973435 ps
CPU time 4.2 seconds
Started Jun 10 05:28:30 PM PDT 24
Finished Jun 10 05:28:35 PM PDT 24
Peak memory 205192 kb
Host smart-02316fbc-8562-4812-bb3c-3c3557a7e400
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1840126821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.1840126821
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.2814692815
Short name T1710
Test name
Test status
Simulation time 13374240464 ps
CPU time 14.63 seconds
Started Jun 10 05:29:06 PM PDT 24
Finished Jun 10 05:29:21 PM PDT 24
Peak memory 205112 kb
Host smart-c1d43826-b053-4395-872d-243228bd976a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2814692815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.2814692815
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1449767529
Short name T925
Test name
Test status
Simulation time 23324409072 ps
CPU time 24.88 seconds
Started Jun 10 05:28:58 PM PDT 24
Finished Jun 10 05:29:23 PM PDT 24
Peak memory 205092 kb
Host smart-955ae09d-2427-4c48-bd66-11360816aa78
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1449767529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.1449767529
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.194166786
Short name T792
Test name
Test status
Simulation time 179494853 ps
CPU time 0.81 seconds
Started Jun 10 05:28:59 PM PDT 24
Finished Jun 10 05:29:00 PM PDT 24
Peak memory 205004 kb
Host smart-273c4acd-ae65-41b7-9dcd-ef0d40010d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19416
6786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.194166786
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.4063312356
Short name T499
Test name
Test status
Simulation time 152295257 ps
CPU time 0.78 seconds
Started Jun 10 05:28:30 PM PDT 24
Finished Jun 10 05:28:31 PM PDT 24
Peak memory 205004 kb
Host smart-4d75a270-d846-4225-b30b-f05c27dca197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40633
12356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.4063312356
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.847272503
Short name T1898
Test name
Test status
Simulation time 565844891 ps
CPU time 1.48 seconds
Started Jun 10 05:28:52 PM PDT 24
Finished Jun 10 05:28:54 PM PDT 24
Peak memory 204968 kb
Host smart-3c8e62f1-f1c3-4cdc-9954-766495167191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84727
2503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.847272503
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.3529277047
Short name T626
Test name
Test status
Simulation time 164561642 ps
CPU time 0.82 seconds
Started Jun 10 05:28:29 PM PDT 24
Finished Jun 10 05:28:30 PM PDT 24
Peak memory 204904 kb
Host smart-19879992-0926-4e9d-8a47-e05e0f279adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35292
77047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.3529277047
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.1014792100
Short name T368
Test name
Test status
Simulation time 32480276 ps
CPU time 0.67 seconds
Started Jun 10 05:28:30 PM PDT 24
Finished Jun 10 05:28:31 PM PDT 24
Peak memory 205024 kb
Host smart-255a0fcd-a965-4898-b95d-c2fa309e7f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10147
92100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.1014792100
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.364316070
Short name T1595
Test name
Test status
Simulation time 787981299 ps
CPU time 2.25 seconds
Started Jun 10 05:28:29 PM PDT 24
Finished Jun 10 05:28:31 PM PDT 24
Peak memory 205208 kb
Host smart-7579652b-e219-4f6b-8ce8-423b5548dc4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36431
6070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.364316070
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2224714080
Short name T1688
Test name
Test status
Simulation time 218189019 ps
CPU time 1.3 seconds
Started Jun 10 05:28:57 PM PDT 24
Finished Jun 10 05:28:58 PM PDT 24
Peak memory 205176 kb
Host smart-07d28ca7-f479-4441-9330-b1b64d6fb68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22247
14080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2224714080
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3414583684
Short name T581
Test name
Test status
Simulation time 246138744 ps
CPU time 0.95 seconds
Started Jun 10 05:28:41 PM PDT 24
Finished Jun 10 05:28:43 PM PDT 24
Peak memory 204992 kb
Host smart-16a524c9-bc6a-4f15-b574-095e96286e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34145
83684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3414583684
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.504412101
Short name T1217
Test name
Test status
Simulation time 191172150 ps
CPU time 0.8 seconds
Started Jun 10 05:29:04 PM PDT 24
Finished Jun 10 05:29:05 PM PDT 24
Peak memory 204980 kb
Host smart-18bfc180-3d50-4b41-92ba-188fb955b9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50441
2101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.504412101
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.1285196427
Short name T89
Test name
Test status
Simulation time 204363537 ps
CPU time 0.88 seconds
Started Jun 10 05:28:54 PM PDT 24
Finished Jun 10 05:28:55 PM PDT 24
Peak memory 205000 kb
Host smart-c224617b-8a1c-418b-95e3-9aaacdd3669a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12851
96427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.1285196427
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.1678644125
Short name T1356
Test name
Test status
Simulation time 210016620 ps
CPU time 0.86 seconds
Started Jun 10 05:29:03 PM PDT 24
Finished Jun 10 05:29:05 PM PDT 24
Peak memory 204992 kb
Host smart-66472bac-de60-49af-9fe5-c017552df335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16786
44125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1678644125
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.1853043336
Short name T1441
Test name
Test status
Simulation time 3265298357 ps
CPU time 3.97 seconds
Started Jun 10 05:28:23 PM PDT 24
Finished Jun 10 05:28:28 PM PDT 24
Peak memory 205112 kb
Host smart-10c9d985-de50-4334-b900-8e7aa10a2cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18530
43336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.1853043336
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.859446164
Short name T393
Test name
Test status
Simulation time 190844268 ps
CPU time 0.88 seconds
Started Jun 10 05:28:27 PM PDT 24
Finished Jun 10 05:28:28 PM PDT 24
Peak memory 204984 kb
Host smart-87adb105-13d7-4e96-874c-052734a41e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85944
6164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.859446164
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.2097300245
Short name T1935
Test name
Test status
Simulation time 11315413906 ps
CPU time 110.65 seconds
Started Jun 10 05:28:30 PM PDT 24
Finished Jun 10 05:30:21 PM PDT 24
Peak memory 205240 kb
Host smart-487c91f7-fd9a-4815-b3d4-a330f824fa87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20973
00245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.2097300245
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1667079032
Short name T1369
Test name
Test status
Simulation time 140841130 ps
CPU time 0.75 seconds
Started Jun 10 05:28:48 PM PDT 24
Finished Jun 10 05:28:49 PM PDT 24
Peak memory 205032 kb
Host smart-22fbefcd-b504-4c40-a440-d3daab9cbd40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16670
79032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1667079032
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.99614916
Short name T859
Test name
Test status
Simulation time 178463205 ps
CPU time 0.86 seconds
Started Jun 10 05:28:33 PM PDT 24
Finished Jun 10 05:28:34 PM PDT 24
Peak memory 205112 kb
Host smart-19b6aeb8-8bb1-43c8-bb29-87c33da83d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99614
916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.99614916
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.772139545
Short name T584
Test name
Test status
Simulation time 172970317 ps
CPU time 0.81 seconds
Started Jun 10 05:28:56 PM PDT 24
Finished Jun 10 05:28:57 PM PDT 24
Peak memory 204980 kb
Host smart-40de7c1a-e23b-45ef-b4ed-cdafa5123ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77213
9545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.772139545
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.3435868918
Short name T476
Test name
Test status
Simulation time 173441867 ps
CPU time 0.77 seconds
Started Jun 10 05:28:40 PM PDT 24
Finished Jun 10 05:28:42 PM PDT 24
Peak memory 205004 kb
Host smart-9f2a6f0a-eeb6-4ef2-9fbe-e8a15405335b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34358
68918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.3435868918
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3927189085
Short name T1760
Test name
Test status
Simulation time 194416002 ps
CPU time 0.83 seconds
Started Jun 10 05:28:31 PM PDT 24
Finished Jun 10 05:28:32 PM PDT 24
Peak memory 204964 kb
Host smart-1753fde6-fce9-469d-8de7-3aa2c2bb0302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39271
89085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3927189085
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2277736049
Short name T177
Test name
Test status
Simulation time 169838831 ps
CPU time 0.81 seconds
Started Jun 10 05:28:36 PM PDT 24
Finished Jun 10 05:28:37 PM PDT 24
Peak memory 205000 kb
Host smart-8ecea7af-e44c-4e88-80f7-2196764cb718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22777
36049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2277736049
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_eop_single_bit_handling.3484501929
Short name T297
Test name
Test status
Simulation time 188493778 ps
CPU time 0.86 seconds
Started Jun 10 05:28:55 PM PDT 24
Finished Jun 10 05:28:56 PM PDT 24
Peak memory 205028 kb
Host smart-d6318874-6634-476e-af1c-ad41cdf9e326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34845
01929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_eop_single_bit_handling.3484501929
Directory /workspace/45.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2733516563
Short name T1078
Test name
Test status
Simulation time 165223837 ps
CPU time 0.75 seconds
Started Jun 10 05:28:57 PM PDT 24
Finished Jun 10 05:28:58 PM PDT 24
Peak memory 205040 kb
Host smart-5ae8b6fd-78b4-432f-bd37-78de1a9b6050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27335
16563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2733516563
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.95554701
Short name T25
Test name
Test status
Simulation time 86054203 ps
CPU time 0.69 seconds
Started Jun 10 05:28:43 PM PDT 24
Finished Jun 10 05:28:44 PM PDT 24
Peak memory 205048 kb
Host smart-72558012-6575-41ab-85a8-e4336d0bd6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95554
701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.95554701
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.746958681
Short name T1403
Test name
Test status
Simulation time 7018964673 ps
CPU time 16.37 seconds
Started Jun 10 05:28:56 PM PDT 24
Finished Jun 10 05:29:12 PM PDT 24
Peak memory 205260 kb
Host smart-92cc3f2d-e44a-4176-abde-dfe7e7dd3343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74695
8681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.746958681
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3055650680
Short name T1780
Test name
Test status
Simulation time 172398207 ps
CPU time 0.77 seconds
Started Jun 10 05:28:58 PM PDT 24
Finished Jun 10 05:28:59 PM PDT 24
Peak memory 204996 kb
Host smart-e9aa7d32-27d1-4ec3-8a26-941c59a94582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30556
50680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3055650680
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.536386261
Short name T1429
Test name
Test status
Simulation time 232162449 ps
CPU time 0.91 seconds
Started Jun 10 05:28:41 PM PDT 24
Finished Jun 10 05:28:43 PM PDT 24
Peak memory 204996 kb
Host smart-cb806243-968b-4eca-a048-bbb0792a2f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53638
6261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.536386261
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.1455904333
Short name T1749
Test name
Test status
Simulation time 200767783 ps
CPU time 0.84 seconds
Started Jun 10 05:28:33 PM PDT 24
Finished Jun 10 05:28:34 PM PDT 24
Peak memory 204900 kb
Host smart-83f1126a-e4e9-420b-8db5-ce4051e4163f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14559
04333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.1455904333
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.3954467601
Short name T1174
Test name
Test status
Simulation time 175400742 ps
CPU time 0.79 seconds
Started Jun 10 05:28:39 PM PDT 24
Finished Jun 10 05:28:41 PM PDT 24
Peak memory 204972 kb
Host smart-940b7d65-b910-40f4-81b3-743f3f6d7da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39544
67601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.3954467601
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.497431130
Short name T1951
Test name
Test status
Simulation time 192732134 ps
CPU time 0.8 seconds
Started Jun 10 05:29:02 PM PDT 24
Finished Jun 10 05:29:04 PM PDT 24
Peak memory 205032 kb
Host smart-57a88e14-cd47-4566-b9ed-8cb5a65c9692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49743
1130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.497431130
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.4211247861
Short name T720
Test name
Test status
Simulation time 149658683 ps
CPU time 0.76 seconds
Started Jun 10 05:29:01 PM PDT 24
Finished Jun 10 05:29:02 PM PDT 24
Peak memory 205032 kb
Host smart-3b5f5ef1-9c1b-4ef2-9ab4-9bd1e695929b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42112
47861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.4211247861
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.666811966
Short name T1280
Test name
Test status
Simulation time 235743912 ps
CPU time 0.94 seconds
Started Jun 10 05:28:58 PM PDT 24
Finished Jun 10 05:28:59 PM PDT 24
Peak memory 205000 kb
Host smart-f2d7ebd3-8ad1-4ffa-be05-33509734fa17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66681
1966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.666811966
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3530278187
Short name T1275
Test name
Test status
Simulation time 166143085 ps
CPU time 0.78 seconds
Started Jun 10 05:28:54 PM PDT 24
Finished Jun 10 05:28:56 PM PDT 24
Peak memory 205012 kb
Host smart-f2eea0f0-2983-49e0-bed2-50950a2de7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35302
78187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3530278187
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.3728749668
Short name T327
Test name
Test status
Simulation time 158799796 ps
CPU time 0.76 seconds
Started Jun 10 05:28:52 PM PDT 24
Finished Jun 10 05:28:53 PM PDT 24
Peak memory 205028 kb
Host smart-0628bedc-4f99-4883-8c24-3c07ee9bb042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37287
49668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.3728749668
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1767739119
Short name T974
Test name
Test status
Simulation time 6883253697 ps
CPU time 51.12 seconds
Started Jun 10 05:28:35 PM PDT 24
Finished Jun 10 05:29:26 PM PDT 24
Peak memory 205112 kb
Host smart-e5971277-c0dc-4afb-8bd2-cab88012a9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17677
39119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1767739119
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.937043836
Short name T463
Test name
Test status
Simulation time 266312851 ps
CPU time 0.99 seconds
Started Jun 10 05:29:00 PM PDT 24
Finished Jun 10 05:29:01 PM PDT 24
Peak memory 204852 kb
Host smart-0c358bc9-62e7-44a6-af2c-7ecafa6c15ba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=937043836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.937043836
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.2222600095
Short name T704
Test name
Test status
Simulation time 151811639 ps
CPU time 0.9 seconds
Started Jun 10 05:28:35 PM PDT 24
Finished Jun 10 05:28:37 PM PDT 24
Peak memory 205024 kb
Host smart-26abaa61-19d1-4889-ba16-834dc804413f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2222600095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.2222600095
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.2934077550
Short name T1030
Test name
Test status
Simulation time 173069543 ps
CPU time 0.88 seconds
Started Jun 10 05:28:38 PM PDT 24
Finished Jun 10 05:28:39 PM PDT 24
Peak memory 205004 kb
Host smart-cbd782c6-8ed1-4f53-8ef2-645767fd4246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29340
77550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.2934077550
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3919556474
Short name T1434
Test name
Test status
Simulation time 3510021166 ps
CPU time 5.1 seconds
Started Jun 10 05:28:39 PM PDT 24
Finished Jun 10 05:28:46 PM PDT 24
Peak memory 205180 kb
Host smart-5fd6ae53-cf70-4c0e-ac67-42d58da184fc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3919556474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.3919556474
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.2533660296
Short name T848
Test name
Test status
Simulation time 13399524307 ps
CPU time 15.57 seconds
Started Jun 10 05:28:56 PM PDT 24
Finished Jun 10 05:29:12 PM PDT 24
Peak memory 205104 kb
Host smart-40c23b38-d876-4cec-be01-256bdd2b4447
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2533660296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.2533660296
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3870010072
Short name T2030
Test name
Test status
Simulation time 23355436007 ps
CPU time 25.95 seconds
Started Jun 10 05:28:36 PM PDT 24
Finished Jun 10 05:29:02 PM PDT 24
Peak memory 205184 kb
Host smart-790a365f-33a4-4a93-98a3-544ed889e3e2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3870010072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.3870010072
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3377290582
Short name T1252
Test name
Test status
Simulation time 193647781 ps
CPU time 0.82 seconds
Started Jun 10 05:28:49 PM PDT 24
Finished Jun 10 05:28:50 PM PDT 24
Peak memory 205048 kb
Host smart-d2b54f7b-0ed5-45d4-9a23-0d5cd4680d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33772
90582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3377290582
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2206852271
Short name T63
Test name
Test status
Simulation time 191135550 ps
CPU time 0.84 seconds
Started Jun 10 05:28:58 PM PDT 24
Finished Jun 10 05:28:59 PM PDT 24
Peak memory 205040 kb
Host smart-dae72022-2acf-4456-a1fb-b58b42a6b5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22068
52271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2206852271
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.87860201
Short name T352
Test name
Test status
Simulation time 146192054 ps
CPU time 0.78 seconds
Started Jun 10 05:29:04 PM PDT 24
Finished Jun 10 05:29:05 PM PDT 24
Peak memory 204992 kb
Host smart-bb87f2bd-3db0-4be9-ba1d-360cc7d662e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87860
201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.87860201
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.1866477044
Short name T233
Test name
Test status
Simulation time 44489760 ps
CPU time 0.68 seconds
Started Jun 10 05:28:38 PM PDT 24
Finished Jun 10 05:28:39 PM PDT 24
Peak memory 205004 kb
Host smart-775eafaf-3e95-4429-8a68-0aa7d3ee2eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18664
77044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.1866477044
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.2879114770
Short name T1763
Test name
Test status
Simulation time 862201910 ps
CPU time 2.1 seconds
Started Jun 10 05:28:41 PM PDT 24
Finished Jun 10 05:28:44 PM PDT 24
Peak memory 205152 kb
Host smart-bef71e95-d090-450d-ab0a-dee3ba6359c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28791
14770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.2879114770
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3991144614
Short name T1084
Test name
Test status
Simulation time 298065855 ps
CPU time 2.28 seconds
Started Jun 10 05:29:03 PM PDT 24
Finished Jun 10 05:29:06 PM PDT 24
Peak memory 205060 kb
Host smart-f9fd673c-b399-4fe4-bb25-f7fe32e482b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39911
44614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3991144614
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1389310421
Short name T772
Test name
Test status
Simulation time 204904901 ps
CPU time 0.87 seconds
Started Jun 10 05:28:36 PM PDT 24
Finished Jun 10 05:28:37 PM PDT 24
Peak memory 205020 kb
Host smart-034f834a-f823-4853-98c0-d28a0c79a2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13893
10421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1389310421
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.2412099181
Short name T1959
Test name
Test status
Simulation time 155625492 ps
CPU time 0.8 seconds
Started Jun 10 05:28:36 PM PDT 24
Finished Jun 10 05:28:37 PM PDT 24
Peak memory 204940 kb
Host smart-47cac6b8-7c9b-4b72-bb4e-5d88d4de3f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24120
99181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.2412099181
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1907325409
Short name T1156
Test name
Test status
Simulation time 215702102 ps
CPU time 0.85 seconds
Started Jun 10 05:29:12 PM PDT 24
Finished Jun 10 05:29:14 PM PDT 24
Peak memory 205044 kb
Host smart-34d411bf-7156-42f6-8a67-1d176fb997cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19073
25409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1907325409
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.1994430672
Short name T532
Test name
Test status
Simulation time 252439784 ps
CPU time 0.92 seconds
Started Jun 10 05:29:03 PM PDT 24
Finished Jun 10 05:29:05 PM PDT 24
Peak memory 205008 kb
Host smart-b41232b4-650b-4436-bc33-9635e404beb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19944
30672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1994430672
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.286695333
Short name T429
Test name
Test status
Simulation time 3288453916 ps
CPU time 4.36 seconds
Started Jun 10 05:28:55 PM PDT 24
Finished Jun 10 05:29:00 PM PDT 24
Peak memory 205084 kb
Host smart-5e84ca41-79d9-4483-94ed-6c0f50ac33ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28669
5333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.286695333
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2032232414
Short name T520
Test name
Test status
Simulation time 243838519 ps
CPU time 0.91 seconds
Started Jun 10 05:28:56 PM PDT 24
Finished Jun 10 05:28:57 PM PDT 24
Peak memory 205004 kb
Host smart-989129fb-b473-4c27-96f1-c62d40f5c35b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20322
32414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2032232414
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.4229287546
Short name T434
Test name
Test status
Simulation time 7360491418 ps
CPU time 69.97 seconds
Started Jun 10 05:29:02 PM PDT 24
Finished Jun 10 05:30:12 PM PDT 24
Peak memory 205184 kb
Host smart-381fd4b1-9fc9-421d-a41a-100304d55477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42292
87546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.4229287546
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2801805034
Short name T2086
Test name
Test status
Simulation time 153632387 ps
CPU time 0.84 seconds
Started Jun 10 05:28:36 PM PDT 24
Finished Jun 10 05:28:37 PM PDT 24
Peak memory 204988 kb
Host smart-6fe3fef2-6654-4c33-8551-3b882bb8fc08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28018
05034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2801805034
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.4010059425
Short name T133
Test name
Test status
Simulation time 240216796 ps
CPU time 0.9 seconds
Started Jun 10 05:28:49 PM PDT 24
Finished Jun 10 05:28:55 PM PDT 24
Peak memory 205008 kb
Host smart-11e5b9b1-80d0-4dda-944b-d004e584f7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40100
59425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.4010059425
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.873332554
Short name T1754
Test name
Test status
Simulation time 194040825 ps
CPU time 0.91 seconds
Started Jun 10 05:28:37 PM PDT 24
Finished Jun 10 05:28:38 PM PDT 24
Peak memory 205088 kb
Host smart-ec456d80-7083-4d16-9a9c-b574b46fae31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87333
2554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.873332554
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.4146303765
Short name T869
Test name
Test status
Simulation time 150430246 ps
CPU time 0.8 seconds
Started Jun 10 05:28:36 PM PDT 24
Finished Jun 10 05:28:38 PM PDT 24
Peak memory 205036 kb
Host smart-2b158223-119c-45d8-b539-53a7352b37c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41463
03765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.4146303765
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1229551822
Short name T1811
Test name
Test status
Simulation time 204260842 ps
CPU time 0.83 seconds
Started Jun 10 05:28:36 PM PDT 24
Finished Jun 10 05:28:37 PM PDT 24
Peak memory 204980 kb
Host smart-31f71b83-af7c-4e07-acc7-54eb550b2c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12295
51822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1229551822
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1049351172
Short name T176
Test name
Test status
Simulation time 188885364 ps
CPU time 0.85 seconds
Started Jun 10 05:28:36 PM PDT 24
Finished Jun 10 05:28:37 PM PDT 24
Peak memory 205004 kb
Host smart-5bfc04a7-c0b7-492d-bef2-bb8d8c19dc16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10493
51172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1049351172
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_eop_single_bit_handling.3851111937
Short name T417
Test name
Test status
Simulation time 208629484 ps
CPU time 0.82 seconds
Started Jun 10 05:28:36 PM PDT 24
Finished Jun 10 05:28:37 PM PDT 24
Peak memory 204988 kb
Host smart-69a7c061-6dea-42dc-a536-2f4104276298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38511
11937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_eop_single_bit_handling.3851111937
Directory /workspace/46.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.2135409313
Short name T1886
Test name
Test status
Simulation time 143329752 ps
CPU time 0.75 seconds
Started Jun 10 05:29:06 PM PDT 24
Finished Jun 10 05:29:07 PM PDT 24
Peak memory 205004 kb
Host smart-d62d7d6e-0c43-461b-b8f5-b56802830210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21354
09313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.2135409313
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3791604350
Short name T1860
Test name
Test status
Simulation time 48802623 ps
CPU time 0.66 seconds
Started Jun 10 05:28:36 PM PDT 24
Finished Jun 10 05:28:37 PM PDT 24
Peak memory 205132 kb
Host smart-afbd1420-d78a-478e-b820-c161014514a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37916
04350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3791604350
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.475504888
Short name T1375
Test name
Test status
Simulation time 10622924857 ps
CPU time 22.97 seconds
Started Jun 10 05:28:36 PM PDT 24
Finished Jun 10 05:29:00 PM PDT 24
Peak memory 205188 kb
Host smart-8233ac9e-6ac3-4e53-8117-bbe6c3097c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47550
4888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.475504888
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2879950181
Short name T1498
Test name
Test status
Simulation time 168533907 ps
CPU time 0.82 seconds
Started Jun 10 05:28:36 PM PDT 24
Finished Jun 10 05:28:38 PM PDT 24
Peak memory 204988 kb
Host smart-69883198-9053-42b5-bf9c-6d427c456a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28799
50181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2879950181
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.4126970670
Short name T415
Test name
Test status
Simulation time 213232230 ps
CPU time 0.89 seconds
Started Jun 10 05:28:55 PM PDT 24
Finished Jun 10 05:28:56 PM PDT 24
Peak memory 205044 kb
Host smart-0f31f180-a1e5-4e38-8fd8-107edc1d02ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41269
70670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.4126970670
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.3291514118
Short name T1941
Test name
Test status
Simulation time 184260814 ps
CPU time 0.87 seconds
Started Jun 10 05:28:38 PM PDT 24
Finished Jun 10 05:28:39 PM PDT 24
Peak memory 204992 kb
Host smart-779b1e58-286c-48b7-9bec-803421f4791f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32915
14118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.3291514118
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3837276457
Short name T1146
Test name
Test status
Simulation time 141809985 ps
CPU time 0.8 seconds
Started Jun 10 05:28:54 PM PDT 24
Finished Jun 10 05:28:55 PM PDT 24
Peak memory 205000 kb
Host smart-26dad2be-172e-4975-a2cb-69c7010877d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38372
76457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3837276457
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2896948739
Short name T924
Test name
Test status
Simulation time 169040356 ps
CPU time 0.77 seconds
Started Jun 10 05:29:00 PM PDT 24
Finished Jun 10 05:29:01 PM PDT 24
Peak memory 205000 kb
Host smart-1edde3db-b85e-4396-8994-384c6979efd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28969
48739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2896948739
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3627569666
Short name T1755
Test name
Test status
Simulation time 150926434 ps
CPU time 0.79 seconds
Started Jun 10 05:28:59 PM PDT 24
Finished Jun 10 05:29:00 PM PDT 24
Peak memory 205040 kb
Host smart-b8518d2f-42d0-49a2-9fc9-652ba2973442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36275
69666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3627569666
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.821518701
Short name T1024
Test name
Test status
Simulation time 237298158 ps
CPU time 1.04 seconds
Started Jun 10 05:28:33 PM PDT 24
Finished Jun 10 05:28:34 PM PDT 24
Peak memory 204932 kb
Host smart-7a8cafa9-116a-412f-a8ec-f0ad68ced686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82151
8701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.821518701
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2170341687
Short name T637
Test name
Test status
Simulation time 183162066 ps
CPU time 0.91 seconds
Started Jun 10 05:28:36 PM PDT 24
Finished Jun 10 05:28:38 PM PDT 24
Peak memory 205008 kb
Host smart-baf4e123-4a7d-40d2-bf9d-a262a4762af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21703
41687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2170341687
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2885846980
Short name T944
Test name
Test status
Simulation time 160929190 ps
CPU time 0.77 seconds
Started Jun 10 05:29:01 PM PDT 24
Finished Jun 10 05:29:02 PM PDT 24
Peak memory 205016 kb
Host smart-ee9e88ad-badf-40d3-a80f-454bb88b0cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28858
46980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2885846980
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.1178824481
Short name T1288
Test name
Test status
Simulation time 8096502265 ps
CPU time 59.45 seconds
Started Jun 10 05:28:59 PM PDT 24
Finished Jun 10 05:29:59 PM PDT 24
Peak memory 205004 kb
Host smart-056a9b0b-aeb9-4d4f-8565-94c0bfc03139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11788
24481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.1178824481
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.1336608022
Short name T1239
Test name
Test status
Simulation time 232356276 ps
CPU time 0.91 seconds
Started Jun 10 05:28:47 PM PDT 24
Finished Jun 10 05:28:48 PM PDT 24
Peak memory 205076 kb
Host smart-5389d60b-5f1a-4124-a205-61553c9598af
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1336608022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.1336608022
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.3708116172
Short name T948
Test name
Test status
Simulation time 158901276 ps
CPU time 0.76 seconds
Started Jun 10 05:29:05 PM PDT 24
Finished Jun 10 05:29:06 PM PDT 24
Peak memory 205028 kb
Host smart-c524fca8-84bf-4a5d-b861-0a6889e56281
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3708116172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.3708116172
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.3062293115
Short name T159
Test name
Test status
Simulation time 204108305 ps
CPU time 0.84 seconds
Started Jun 10 05:28:44 PM PDT 24
Finished Jun 10 05:28:45 PM PDT 24
Peak memory 205112 kb
Host smart-4486ffda-d3ab-4a18-acc7-1fc8e628c414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30622
93115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.3062293115
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.804055635
Short name T2108
Test name
Test status
Simulation time 4083885453 ps
CPU time 4.72 seconds
Started Jun 10 05:29:05 PM PDT 24
Finished Jun 10 05:29:10 PM PDT 24
Peak memory 204916 kb
Host smart-7b0e8214-2a68-40c8-9b9c-2dbeb1240517
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=804055635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.804055635
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.2410033900
Short name T1765
Test name
Test status
Simulation time 13367921787 ps
CPU time 14.26 seconds
Started Jun 10 05:28:59 PM PDT 24
Finished Jun 10 05:29:19 PM PDT 24
Peak memory 205100 kb
Host smart-8dd5a56c-2ef2-44cd-adaa-e42ead7a9fa0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2410033900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.2410033900
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.813321998
Short name T9
Test name
Test status
Simulation time 23456136451 ps
CPU time 26.26 seconds
Started Jun 10 05:28:36 PM PDT 24
Finished Jun 10 05:29:03 PM PDT 24
Peak memory 205336 kb
Host smart-79113264-0a9c-4e6e-9ce7-2eb99b961ddd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=813321998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.813321998
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1608778447
Short name T561
Test name
Test status
Simulation time 170768367 ps
CPU time 0.8 seconds
Started Jun 10 05:29:03 PM PDT 24
Finished Jun 10 05:29:04 PM PDT 24
Peak memory 204852 kb
Host smart-aff91e3a-ccad-41e7-a7b3-2785dec570ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16087
78447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1608778447
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.1089394599
Short name T59
Test name
Test status
Simulation time 170922707 ps
CPU time 0.77 seconds
Started Jun 10 05:29:05 PM PDT 24
Finished Jun 10 05:29:06 PM PDT 24
Peak memory 205016 kb
Host smart-16034a7a-7ecf-41e3-8736-08422c2f5f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10893
94599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.1089394599
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3139240827
Short name T748
Test name
Test status
Simulation time 777498613 ps
CPU time 1.87 seconds
Started Jun 10 05:28:46 PM PDT 24
Finished Jun 10 05:28:48 PM PDT 24
Peak memory 205128 kb
Host smart-f8fef2de-42a6-4774-9df2-1c1bc9dfa4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31392
40827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3139240827
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.1343178154
Short name T1642
Test name
Test status
Simulation time 147503741 ps
CPU time 0.82 seconds
Started Jun 10 05:28:40 PM PDT 24
Finished Jun 10 05:28:42 PM PDT 24
Peak memory 205040 kb
Host smart-6dac7a82-e325-4e72-8773-37959266302d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13431
78154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.1343178154
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3280691419
Short name T1261
Test name
Test status
Simulation time 40127233 ps
CPU time 0.73 seconds
Started Jun 10 05:28:43 PM PDT 24
Finished Jun 10 05:28:45 PM PDT 24
Peak memory 205012 kb
Host smart-e6f99cd5-e8bc-4ebc-a6a1-704636844198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32806
91419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3280691419
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1643601912
Short name T1753
Test name
Test status
Simulation time 993033765 ps
CPU time 2.27 seconds
Started Jun 10 05:28:40 PM PDT 24
Finished Jun 10 05:28:43 PM PDT 24
Peak memory 205036 kb
Host smart-791fe0ce-ffea-4962-b590-bb86c20aad45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16436
01912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1643601912
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2978311723
Short name T667
Test name
Test status
Simulation time 398020763 ps
CPU time 2.17 seconds
Started Jun 10 05:29:04 PM PDT 24
Finished Jun 10 05:29:07 PM PDT 24
Peak memory 205092 kb
Host smart-d8d28654-04e5-47c1-870c-37aa43035d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29783
11723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2978311723
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.422580231
Short name T401
Test name
Test status
Simulation time 166084511 ps
CPU time 0.81 seconds
Started Jun 10 05:29:03 PM PDT 24
Finished Jun 10 05:29:04 PM PDT 24
Peak memory 205032 kb
Host smart-b61cc1fd-b4f7-4c70-9999-8bb6c60f41fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42258
0231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.422580231
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.284961914
Short name T1221
Test name
Test status
Simulation time 151677871 ps
CPU time 0.78 seconds
Started Jun 10 05:28:50 PM PDT 24
Finished Jun 10 05:28:51 PM PDT 24
Peak memory 204980 kb
Host smart-1171066c-9d9c-4ee9-87a5-f646f386234c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28496
1914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.284961914
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.4032600734
Short name T914
Test name
Test status
Simulation time 192643579 ps
CPU time 0.86 seconds
Started Jun 10 05:29:20 PM PDT 24
Finished Jun 10 05:29:21 PM PDT 24
Peak memory 204952 kb
Host smart-9970b05b-ba13-43e9-8440-b9f3fe0c61af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40326
00734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.4032600734
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.461345748
Short name T509
Test name
Test status
Simulation time 234538925 ps
CPU time 0.87 seconds
Started Jun 10 05:28:55 PM PDT 24
Finished Jun 10 05:28:56 PM PDT 24
Peak memory 205028 kb
Host smart-3cc20f03-d37f-4921-adf9-23923f82334c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46134
5748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.461345748
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.3787025238
Short name T949
Test name
Test status
Simulation time 3317244783 ps
CPU time 4.29 seconds
Started Jun 10 05:29:06 PM PDT 24
Finished Jun 10 05:29:10 PM PDT 24
Peak memory 205036 kb
Host smart-9e4e6aac-8dbf-4416-8f3b-5f774f89da7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37870
25238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.3787025238
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3653489148
Short name T2034
Test name
Test status
Simulation time 190508067 ps
CPU time 0.85 seconds
Started Jun 10 05:29:10 PM PDT 24
Finished Jun 10 05:29:11 PM PDT 24
Peak memory 205040 kb
Host smart-ebc75c22-84f4-4805-8143-d3f9c9d4f41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36534
89148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3653489148
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.1588887230
Short name T1172
Test name
Test status
Simulation time 6382311236 ps
CPU time 47.79 seconds
Started Jun 10 05:29:20 PM PDT 24
Finished Jun 10 05:30:08 PM PDT 24
Peak memory 205204 kb
Host smart-d838be23-02e8-427a-89cc-881c2d7f9fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15888
87230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.1588887230
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2416674478
Short name T695
Test name
Test status
Simulation time 165466308 ps
CPU time 0.77 seconds
Started Jun 10 05:28:45 PM PDT 24
Finished Jun 10 05:28:46 PM PDT 24
Peak memory 205004 kb
Host smart-9157cb5a-e95e-4f65-a35f-0f80e4212a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24166
74478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2416674478
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.498373708
Short name T1838
Test name
Test status
Simulation time 228225780 ps
CPU time 0.92 seconds
Started Jun 10 05:29:09 PM PDT 24
Finished Jun 10 05:29:11 PM PDT 24
Peak memory 205000 kb
Host smart-65acc00c-cf3d-4f33-8ef7-eccb97e0a0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49837
3708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.498373708
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.168672014
Short name T1012
Test name
Test status
Simulation time 196953930 ps
CPU time 0.82 seconds
Started Jun 10 05:28:41 PM PDT 24
Finished Jun 10 05:28:43 PM PDT 24
Peak memory 205020 kb
Host smart-4a364740-c7dc-40aa-8d22-2dce7e72e8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16867
2014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.168672014
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.4026508809
Short name T804
Test name
Test status
Simulation time 254697596 ps
CPU time 0.87 seconds
Started Jun 10 05:29:04 PM PDT 24
Finished Jun 10 05:29:06 PM PDT 24
Peak memory 204996 kb
Host smart-b8c2dbf5-b08e-40fb-a610-60a341f33b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40265
08809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.4026508809
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.2551672767
Short name T1374
Test name
Test status
Simulation time 153902816 ps
CPU time 0.79 seconds
Started Jun 10 05:29:18 PM PDT 24
Finished Jun 10 05:29:19 PM PDT 24
Peak memory 204840 kb
Host smart-c4c74f2e-c542-4ca8-aa09-a2e8d6cbe8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25516
72767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.2551672767
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2783857879
Short name T773
Test name
Test status
Simulation time 171665804 ps
CPU time 0.82 seconds
Started Jun 10 05:28:45 PM PDT 24
Finished Jun 10 05:28:46 PM PDT 24
Peak memory 204992 kb
Host smart-8119567a-7176-425a-888f-95d1d545429c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27838
57879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2783857879
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_eop_single_bit_handling.134942656
Short name T907
Test name
Test status
Simulation time 197893542 ps
CPU time 0.86 seconds
Started Jun 10 05:28:46 PM PDT 24
Finished Jun 10 05:28:47 PM PDT 24
Peak memory 205004 kb
Host smart-cb445bff-ff28-4ac3-92de-7c552b66977e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13494
2656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_eop_single_bit_handling.134942656
Directory /workspace/47.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.3998478377
Short name T2058
Test name
Test status
Simulation time 188019770 ps
CPU time 0.79 seconds
Started Jun 10 05:28:59 PM PDT 24
Finished Jun 10 05:29:00 PM PDT 24
Peak memory 205016 kb
Host smart-47c9929b-1ddf-4cdd-88ed-4d30e3b5522f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39984
78377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.3998478377
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1094055367
Short name T1471
Test name
Test status
Simulation time 30992290 ps
CPU time 0.62 seconds
Started Jun 10 05:29:08 PM PDT 24
Finished Jun 10 05:29:10 PM PDT 24
Peak memory 205024 kb
Host smart-2aad23ca-1134-4048-a272-84fa68a7d1f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10940
55367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1094055367
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.144832577
Short name T876
Test name
Test status
Simulation time 20535549659 ps
CPU time 45.56 seconds
Started Jun 10 05:28:39 PM PDT 24
Finished Jun 10 05:29:26 PM PDT 24
Peak memory 205172 kb
Host smart-aecfd22b-a8a3-4fba-84c6-b278abce7feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14483
2577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.144832577
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1472128968
Short name T281
Test name
Test status
Simulation time 186395766 ps
CPU time 0.86 seconds
Started Jun 10 05:29:26 PM PDT 24
Finished Jun 10 05:29:27 PM PDT 24
Peak memory 205056 kb
Host smart-d99b03fc-a573-4575-8d7f-583f4c649752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14721
28968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1472128968
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2416925888
Short name T678
Test name
Test status
Simulation time 200181663 ps
CPU time 0.86 seconds
Started Jun 10 05:28:40 PM PDT 24
Finished Jun 10 05:28:42 PM PDT 24
Peak memory 204976 kb
Host smart-5f2721d9-d0fb-4722-8e21-72c21850ee2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24169
25888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2416925888
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.3794723727
Short name T1323
Test name
Test status
Simulation time 188353023 ps
CPU time 0.84 seconds
Started Jun 10 05:28:40 PM PDT 24
Finished Jun 10 05:28:42 PM PDT 24
Peak memory 204984 kb
Host smart-b7ef531c-416c-450a-b31c-6120a3a24205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37947
23727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.3794723727
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.3593341126
Short name T374
Test name
Test status
Simulation time 147523827 ps
CPU time 0.79 seconds
Started Jun 10 05:29:10 PM PDT 24
Finished Jun 10 05:29:12 PM PDT 24
Peak memory 205004 kb
Host smart-76e5e2e1-ddda-43f0-8904-d85391be2fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35933
41126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.3593341126
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.367976548
Short name T1797
Test name
Test status
Simulation time 197210789 ps
CPU time 0.82 seconds
Started Jun 10 05:29:07 PM PDT 24
Finished Jun 10 05:29:09 PM PDT 24
Peak memory 205008 kb
Host smart-21a1a3c5-ee87-4d75-844d-09d4d9012a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36797
6548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.367976548
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3755782925
Short name T1542
Test name
Test status
Simulation time 150665002 ps
CPU time 0.78 seconds
Started Jun 10 05:28:43 PM PDT 24
Finished Jun 10 05:28:44 PM PDT 24
Peak memory 204992 kb
Host smart-ee939090-5df4-4254-b57b-1ff3df594689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37557
82925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3755782925
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.879079627
Short name T798
Test name
Test status
Simulation time 177234451 ps
CPU time 0.83 seconds
Started Jun 10 05:29:02 PM PDT 24
Finished Jun 10 05:29:04 PM PDT 24
Peak memory 204876 kb
Host smart-0e5606dc-6618-45b7-b6cf-5df9ed376e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87907
9627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.879079627
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.4092283899
Short name T991
Test name
Test status
Simulation time 193231333 ps
CPU time 0.9 seconds
Started Jun 10 05:28:41 PM PDT 24
Finished Jun 10 05:28:42 PM PDT 24
Peak memory 205012 kb
Host smart-84e9775f-c2b6-4d45-b185-3508ee59e1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40922
83899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.4092283899
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.4011113500
Short name T2012
Test name
Test status
Simulation time 188638174 ps
CPU time 0.88 seconds
Started Jun 10 05:29:06 PM PDT 24
Finished Jun 10 05:29:07 PM PDT 24
Peak memory 204996 kb
Host smart-579e25af-1ce8-4f0a-b1d2-f70cde95105c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40111
13500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.4011113500
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.1764829504
Short name T1178
Test name
Test status
Simulation time 6686827004 ps
CPU time 65.36 seconds
Started Jun 10 05:28:46 PM PDT 24
Finished Jun 10 05:29:52 PM PDT 24
Peak memory 205168 kb
Host smart-fe8a4ef1-468c-41c6-965b-e4c98c52e1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17648
29504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1764829504
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.2425005977
Short name T945
Test name
Test status
Simulation time 237379760 ps
CPU time 0.95 seconds
Started Jun 10 05:29:16 PM PDT 24
Finished Jun 10 05:29:18 PM PDT 24
Peak memory 204924 kb
Host smart-7547594c-1aba-4a06-9155-b05c97e4fecb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2425005977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.2425005977
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.4121440772
Short name T1458
Test name
Test status
Simulation time 151914555 ps
CPU time 0.78 seconds
Started Jun 10 05:29:24 PM PDT 24
Finished Jun 10 05:29:26 PM PDT 24
Peak memory 204904 kb
Host smart-7d6574a9-529c-45a2-9aef-08f5a3e65f5d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4121440772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.4121440772
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.489995201
Short name T915
Test name
Test status
Simulation time 172824962 ps
CPU time 0.8 seconds
Started Jun 10 05:28:54 PM PDT 24
Finished Jun 10 05:28:56 PM PDT 24
Peak memory 205028 kb
Host smart-ba5973ce-1624-4156-bb3d-54ad58624c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48999
5201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.489995201
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1236719576
Short name T1744
Test name
Test status
Simulation time 4375871928 ps
CPU time 6.06 seconds
Started Jun 10 05:28:43 PM PDT 24
Finished Jun 10 05:28:50 PM PDT 24
Peak memory 204992 kb
Host smart-2017ab93-9b8d-4427-824e-0d940cce3447
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1236719576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.1236719576
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.744322147
Short name T639
Test name
Test status
Simulation time 13369225510 ps
CPU time 15.91 seconds
Started Jun 10 05:29:07 PM PDT 24
Finished Jun 10 05:29:23 PM PDT 24
Peak memory 205156 kb
Host smart-433d1b68-1028-4c59-853c-99fdf27580f0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=744322147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.744322147
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3743012285
Short name T1303
Test name
Test status
Simulation time 23379941241 ps
CPU time 26.04 seconds
Started Jun 10 05:28:46 PM PDT 24
Finished Jun 10 05:29:12 PM PDT 24
Peak memory 205088 kb
Host smart-76e4eb78-6e9c-4027-9c96-80c6f55b404c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3743012285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.3743012285
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1506146316
Short name T1953
Test name
Test status
Simulation time 198065295 ps
CPU time 0.82 seconds
Started Jun 10 05:28:46 PM PDT 24
Finished Jun 10 05:28:48 PM PDT 24
Peak memory 204968 kb
Host smart-908b8015-1a47-4a4d-bc1d-28dea09f7697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15061
46316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1506146316
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.2242054379
Short name T1236
Test name
Test status
Simulation time 184926399 ps
CPU time 0.8 seconds
Started Jun 10 05:28:50 PM PDT 24
Finished Jun 10 05:28:51 PM PDT 24
Peak memory 205024 kb
Host smart-dd3a21eb-8f81-422b-b86f-ee7d615d2387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22420
54379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.2242054379
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.69982080
Short name T66
Test name
Test status
Simulation time 1537535407 ps
CPU time 3.36 seconds
Started Jun 10 05:29:23 PM PDT 24
Finished Jun 10 05:29:26 PM PDT 24
Peak memory 205048 kb
Host smart-5a3c8a4a-3864-4006-8f0f-2b9817ee9554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69982
080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.69982080
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.1151062791
Short name T1026
Test name
Test status
Simulation time 138071574 ps
CPU time 0.87 seconds
Started Jun 10 05:28:46 PM PDT 24
Finished Jun 10 05:28:48 PM PDT 24
Peak memory 205020 kb
Host smart-3fc7f99a-c0a2-4317-be6c-aca54ef3dc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11510
62791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1151062791
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.3582831958
Short name T880
Test name
Test status
Simulation time 58611816 ps
CPU time 0.69 seconds
Started Jun 10 05:28:46 PM PDT 24
Finished Jun 10 05:28:47 PM PDT 24
Peak memory 204940 kb
Host smart-51ab25ab-904e-4dcb-bf22-4c2ae99a2663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35828
31958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3582831958
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.3361909477
Short name T1132
Test name
Test status
Simulation time 872443664 ps
CPU time 1.93 seconds
Started Jun 10 05:29:09 PM PDT 24
Finished Jun 10 05:29:11 PM PDT 24
Peak memory 205176 kb
Host smart-9c981d8e-7aa4-4c96-b054-990fc882189e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33619
09477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.3361909477
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2782149029
Short name T920
Test name
Test status
Simulation time 335470623 ps
CPU time 2 seconds
Started Jun 10 05:29:17 PM PDT 24
Finished Jun 10 05:29:20 PM PDT 24
Peak memory 205068 kb
Host smart-42b0608d-14d7-4c23-bd92-0572969e4b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27821
49029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2782149029
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.3177277700
Short name T421
Test name
Test status
Simulation time 149195822 ps
CPU time 0.74 seconds
Started Jun 10 05:29:12 PM PDT 24
Finished Jun 10 05:29:13 PM PDT 24
Peak memory 204880 kb
Host smart-aa6f01fa-7b2b-4b48-806e-c1d0405cf49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31772
77700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.3177277700
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.4118721311
Short name T1514
Test name
Test status
Simulation time 170080113 ps
CPU time 0.85 seconds
Started Jun 10 05:29:08 PM PDT 24
Finished Jun 10 05:29:09 PM PDT 24
Peak memory 205004 kb
Host smart-eb2e91ad-9c27-47b7-9e77-025f4c99bf79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41187
21311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.4118721311
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.2800184268
Short name T1668
Test name
Test status
Simulation time 220709092 ps
CPU time 0.91 seconds
Started Jun 10 05:29:11 PM PDT 24
Finished Jun 10 05:29:12 PM PDT 24
Peak memory 205000 kb
Host smart-5cc1b51e-3715-46fc-94e9-144ba92b98a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28001
84268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2800184268
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.2611491072
Short name T353
Test name
Test status
Simulation time 3284388044 ps
CPU time 4.22 seconds
Started Jun 10 05:28:51 PM PDT 24
Finished Jun 10 05:28:55 PM PDT 24
Peak memory 205084 kb
Host smart-96713173-1dfa-4488-9c23-6d066aaf81e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26114
91072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.2611491072
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.406429359
Short name T652
Test name
Test status
Simulation time 250126080 ps
CPU time 0.89 seconds
Started Jun 10 05:29:07 PM PDT 24
Finished Jun 10 05:29:08 PM PDT 24
Peak memory 204988 kb
Host smart-0a1a08cd-186a-45bb-889b-c6552a6737c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40642
9359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.406429359
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.1311799528
Short name T324
Test name
Test status
Simulation time 6351164953 ps
CPU time 178.43 seconds
Started Jun 10 05:29:16 PM PDT 24
Finished Jun 10 05:32:15 PM PDT 24
Peak memory 205204 kb
Host smart-8c04e235-ed03-495c-ba70-52cc1f4c8cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13117
99528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.1311799528
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1278889297
Short name T1997
Test name
Test status
Simulation time 153315591 ps
CPU time 0.73 seconds
Started Jun 10 05:28:47 PM PDT 24
Finished Jun 10 05:28:49 PM PDT 24
Peak memory 205004 kb
Host smart-3bc6c4e7-c8af-46ba-a98c-0ec6cb759633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12788
89297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1278889297
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.3314435445
Short name T145
Test name
Test status
Simulation time 189643037 ps
CPU time 0.93 seconds
Started Jun 10 05:29:10 PM PDT 24
Finished Jun 10 05:29:12 PM PDT 24
Peak memory 204876 kb
Host smart-ad6c8a0c-80de-482d-91fe-4c7496f62b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33144
35445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3314435445
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2258141657
Short name T2061
Test name
Test status
Simulation time 181575724 ps
CPU time 0.83 seconds
Started Jun 10 05:29:11 PM PDT 24
Finished Jun 10 05:29:13 PM PDT 24
Peak memory 205036 kb
Host smart-e69e4d02-bb76-4d15-9952-66044f0b28f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22581
41657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2258141657
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.2705789466
Short name T868
Test name
Test status
Simulation time 180878044 ps
CPU time 0.81 seconds
Started Jun 10 05:29:13 PM PDT 24
Finished Jun 10 05:29:14 PM PDT 24
Peak memory 205004 kb
Host smart-b78857a9-c9e8-465c-8a28-77810f2201aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27057
89466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2705789466
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3803829430
Short name T1443
Test name
Test status
Simulation time 192993963 ps
CPU time 0.9 seconds
Started Jun 10 05:28:46 PM PDT 24
Finished Jun 10 05:28:48 PM PDT 24
Peak memory 204964 kb
Host smart-d6edee00-3be0-4032-a0db-5fd3199ab81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38038
29430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3803829430
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1911466058
Short name T2089
Test name
Test status
Simulation time 159440927 ps
CPU time 0.83 seconds
Started Jun 10 05:28:48 PM PDT 24
Finished Jun 10 05:28:49 PM PDT 24
Peak memory 204928 kb
Host smart-dfb131b6-5366-4bed-ab55-60a50c91e4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19114
66058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1911466058
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_eop_single_bit_handling.2705958963
Short name T651
Test name
Test status
Simulation time 214122238 ps
CPU time 0.95 seconds
Started Jun 10 05:28:53 PM PDT 24
Finished Jun 10 05:28:54 PM PDT 24
Peak memory 205040 kb
Host smart-df13c2a6-00cb-4064-bc14-029fccf35d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27059
58963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_eop_single_bit_handling.2705958963
Directory /workspace/48.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1048612899
Short name T1631
Test name
Test status
Simulation time 159868164 ps
CPU time 0.8 seconds
Started Jun 10 05:28:46 PM PDT 24
Finished Jun 10 05:28:47 PM PDT 24
Peak memory 204988 kb
Host smart-71df3fcf-c75b-4c15-919b-837aa10b3c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10486
12899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1048612899
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.3532226790
Short name T881
Test name
Test status
Simulation time 47880982 ps
CPU time 0.64 seconds
Started Jun 10 05:29:12 PM PDT 24
Finished Jun 10 05:29:13 PM PDT 24
Peak memory 204992 kb
Host smart-3f59fd7d-9123-48b7-8f8e-3aa5aefbb41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35322
26790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.3532226790
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2030648842
Short name T209
Test name
Test status
Simulation time 16634868532 ps
CPU time 37.69 seconds
Started Jun 10 05:28:47 PM PDT 24
Finished Jun 10 05:29:25 PM PDT 24
Peak memory 205232 kb
Host smart-c54bf42c-16b0-459b-9f15-f0a2a1486eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20306
48842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2030648842
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3895632893
Short name T756
Test name
Test status
Simulation time 159954367 ps
CPU time 0.82 seconds
Started Jun 10 05:28:47 PM PDT 24
Finished Jun 10 05:28:48 PM PDT 24
Peak memory 205028 kb
Host smart-58e3c7a1-0880-4c37-8617-a561fa21c367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38956
32893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3895632893
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.834264656
Short name T1197
Test name
Test status
Simulation time 178574737 ps
CPU time 0.81 seconds
Started Jun 10 05:29:07 PM PDT 24
Finished Jun 10 05:29:13 PM PDT 24
Peak memory 205000 kb
Host smart-6cac0473-718d-4a53-a94b-30a50386469e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83426
4656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.834264656
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.3692792707
Short name T1036
Test name
Test status
Simulation time 186937516 ps
CPU time 0.83 seconds
Started Jun 10 05:29:16 PM PDT 24
Finished Jun 10 05:29:18 PM PDT 24
Peak memory 205000 kb
Host smart-056c5479-beb1-46e3-86d4-33ce717a2204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36927
92707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.3692792707
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.517720848
Short name T793
Test name
Test status
Simulation time 164674221 ps
CPU time 0.82 seconds
Started Jun 10 05:28:51 PM PDT 24
Finished Jun 10 05:28:52 PM PDT 24
Peak memory 205040 kb
Host smart-4e7d5b1a-53f1-448f-9d7c-a8b3049838ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51772
0848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.517720848
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2528895468
Short name T188
Test name
Test status
Simulation time 174926636 ps
CPU time 0.8 seconds
Started Jun 10 05:29:29 PM PDT 24
Finished Jun 10 05:29:30 PM PDT 24
Peak memory 205036 kb
Host smart-9fa32e0f-5a07-4344-bcc0-a4ca54b29933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25288
95468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2528895468
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1592010210
Short name T977
Test name
Test status
Simulation time 197808829 ps
CPU time 0.81 seconds
Started Jun 10 05:28:47 PM PDT 24
Finished Jun 10 05:28:48 PM PDT 24
Peak memory 204936 kb
Host smart-bee6347c-8922-42f4-bf0b-5ceb65ad0b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15920
10210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1592010210
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.179577337
Short name T1397
Test name
Test status
Simulation time 241807903 ps
CPU time 0.96 seconds
Started Jun 10 05:29:00 PM PDT 24
Finished Jun 10 05:29:01 PM PDT 24
Peak memory 205004 kb
Host smart-eda51719-0af2-4119-b4ed-f44f555ea4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17957
7337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.179577337
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2123154626
Short name T1187
Test name
Test status
Simulation time 177040363 ps
CPU time 0.81 seconds
Started Jun 10 05:29:34 PM PDT 24
Finished Jun 10 05:29:35 PM PDT 24
Peak memory 204844 kb
Host smart-4c3ef6d1-d9b5-44b5-a5ca-6bb7b5886946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21231
54626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2123154626
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1307810298
Short name T1877
Test name
Test status
Simulation time 154699636 ps
CPU time 0.78 seconds
Started Jun 10 05:29:03 PM PDT 24
Finished Jun 10 05:29:05 PM PDT 24
Peak memory 205036 kb
Host smart-627004bb-2ba7-440b-a108-6b8c3117d74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13078
10298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1307810298
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.2862474166
Short name T2036
Test name
Test status
Simulation time 6937044082 ps
CPU time 185.76 seconds
Started Jun 10 05:28:54 PM PDT 24
Finished Jun 10 05:32:00 PM PDT 24
Peak memory 205228 kb
Host smart-693eb9b7-1dde-442b-b66e-02d11697f6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28624
74166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.2862474166
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.3872022762
Short name T1716
Test name
Test status
Simulation time 284036308 ps
CPU time 0.93 seconds
Started Jun 10 05:28:54 PM PDT 24
Finished Jun 10 05:28:56 PM PDT 24
Peak memory 205048 kb
Host smart-4aa66568-4caa-4e6a-8689-8bde502be3c2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3872022762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.3872022762
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.1895172196
Short name T585
Test name
Test status
Simulation time 157527408 ps
CPU time 0.82 seconds
Started Jun 10 05:29:11 PM PDT 24
Finished Jun 10 05:29:12 PM PDT 24
Peak memory 205028 kb
Host smart-2e7032ce-d222-4462-b9b5-2c4a15fe5382
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1895172196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.1895172196
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.127433373
Short name T387
Test name
Test status
Simulation time 239111476 ps
CPU time 0.92 seconds
Started Jun 10 05:29:10 PM PDT 24
Finished Jun 10 05:29:12 PM PDT 24
Peak memory 205008 kb
Host smart-b049f086-b998-4af9-960d-284a830e451a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12743
3373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.127433373
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.2999944823
Short name T1210
Test name
Test status
Simulation time 4167065492 ps
CPU time 5.09 seconds
Started Jun 10 05:28:54 PM PDT 24
Finished Jun 10 05:28:59 PM PDT 24
Peak memory 205092 kb
Host smart-9e00ace5-1d5f-456c-83dd-031c5559bd47
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2999944823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.2999944823
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.3070911433
Short name T1708
Test name
Test status
Simulation time 13416590758 ps
CPU time 16.57 seconds
Started Jun 10 05:29:27 PM PDT 24
Finished Jun 10 05:29:44 PM PDT 24
Peak memory 205004 kb
Host smart-a33fc6bb-d2d0-4dfd-b6df-870360c38bb7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3070911433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3070911433
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.136219052
Short name T1937
Test name
Test status
Simulation time 23463839383 ps
CPU time 26.06 seconds
Started Jun 10 05:28:48 PM PDT 24
Finished Jun 10 05:29:14 PM PDT 24
Peak memory 205160 kb
Host smart-3414317b-c7bf-4358-a51c-3bf873dd581e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=136219052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.136219052
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.375498433
Short name T1577
Test name
Test status
Simulation time 208219750 ps
CPU time 0.82 seconds
Started Jun 10 05:28:48 PM PDT 24
Finished Jun 10 05:28:49 PM PDT 24
Peak memory 205020 kb
Host smart-6b351f29-0e9b-4bfc-b032-ccc55b0749db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37549
8433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.375498433
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.547092549
Short name T303
Test name
Test status
Simulation time 149644385 ps
CPU time 0.8 seconds
Started Jun 10 05:28:52 PM PDT 24
Finished Jun 10 05:28:53 PM PDT 24
Peak memory 205008 kb
Host smart-0730b6ce-6c63-4563-b18d-e9645e32bbd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54709
2549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.547092549
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.330768131
Short name T1497
Test name
Test status
Simulation time 79260241 ps
CPU time 0.69 seconds
Started Jun 10 05:29:04 PM PDT 24
Finished Jun 10 05:29:05 PM PDT 24
Peak memory 205000 kb
Host smart-f50ab337-ca41-457c-8648-8e1eef5f02f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33076
8131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.330768131
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1014637453
Short name T331
Test name
Test status
Simulation time 882143869 ps
CPU time 2.09 seconds
Started Jun 10 05:28:51 PM PDT 24
Finished Jun 10 05:28:53 PM PDT 24
Peak memory 205112 kb
Host smart-3f2c4025-606b-410a-9424-5e6631496356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10146
37453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1014637453
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1571600329
Short name T617
Test name
Test status
Simulation time 164331001 ps
CPU time 1.45 seconds
Started Jun 10 05:28:53 PM PDT 24
Finished Jun 10 05:28:54 PM PDT 24
Peak memory 205096 kb
Host smart-2ea61d19-e452-4e14-a141-6111bfab2482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15716
00329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1571600329
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.4192158843
Short name T461
Test name
Test status
Simulation time 166911371 ps
CPU time 0.82 seconds
Started Jun 10 05:28:57 PM PDT 24
Finished Jun 10 05:28:58 PM PDT 24
Peak memory 205016 kb
Host smart-4193caa7-17ed-4e3a-9a33-de9f640c080b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41921
58843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.4192158843
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1324394915
Short name T1863
Test name
Test status
Simulation time 147145774 ps
CPU time 0.81 seconds
Started Jun 10 05:28:56 PM PDT 24
Finished Jun 10 05:28:57 PM PDT 24
Peak memory 204988 kb
Host smart-86cf3a36-a803-4f04-928b-edb52b492d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13243
94915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1324394915
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1152856150
Short name T469
Test name
Test status
Simulation time 214715375 ps
CPU time 0.92 seconds
Started Jun 10 05:28:53 PM PDT 24
Finished Jun 10 05:28:54 PM PDT 24
Peak memory 205028 kb
Host smart-ba8a300f-301d-42b0-8b0f-66342effa76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11528
56150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1152856150
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.2956733085
Short name T1841
Test name
Test status
Simulation time 172456523 ps
CPU time 0.9 seconds
Started Jun 10 05:28:54 PM PDT 24
Finished Jun 10 05:28:55 PM PDT 24
Peak memory 205116 kb
Host smart-1ba0647c-e97d-4ddc-993e-90d1cdb5b378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29567
33085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.2956733085
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.2067197457
Short name T1588
Test name
Test status
Simulation time 3325599840 ps
CPU time 3.99 seconds
Started Jun 10 05:28:57 PM PDT 24
Finished Jun 10 05:29:01 PM PDT 24
Peak memory 205040 kb
Host smart-14e30b75-ffd9-4fca-a08c-9fc3a4655898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20671
97457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.2067197457
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.966305305
Short name T600
Test name
Test status
Simulation time 276746718 ps
CPU time 0.93 seconds
Started Jun 10 05:29:07 PM PDT 24
Finished Jun 10 05:29:08 PM PDT 24
Peak memory 205032 kb
Host smart-f4f964fd-5866-4deb-bf26-9a578ee15005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96630
5305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.966305305
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.3231151117
Short name T1412
Test name
Test status
Simulation time 12081559301 ps
CPU time 123.09 seconds
Started Jun 10 05:29:07 PM PDT 24
Finished Jun 10 05:31:11 PM PDT 24
Peak memory 205164 kb
Host smart-9abe504d-4ef8-4517-8c9e-69cb1ca3d93c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32311
51117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.3231151117
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2481811207
Short name T1722
Test name
Test status
Simulation time 151028564 ps
CPU time 0.84 seconds
Started Jun 10 05:29:27 PM PDT 24
Finished Jun 10 05:29:33 PM PDT 24
Peak memory 205064 kb
Host smart-b7db58e4-ddb4-4368-9098-7e5a635066f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24818
11207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2481811207
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.3859280243
Short name T143
Test name
Test status
Simulation time 266439950 ps
CPU time 0.92 seconds
Started Jun 10 05:29:23 PM PDT 24
Finished Jun 10 05:29:25 PM PDT 24
Peak memory 204808 kb
Host smart-8c3a30bb-6bf9-47ab-8f7e-bd781c48199b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38592
80243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.3859280243
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.338044396
Short name T2018
Test name
Test status
Simulation time 166795826 ps
CPU time 0.77 seconds
Started Jun 10 05:29:21 PM PDT 24
Finished Jun 10 05:29:22 PM PDT 24
Peak memory 205016 kb
Host smart-56a0544c-ec1c-4390-b017-3d5728b82923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33804
4396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.338044396
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1689589460
Short name T1991
Test name
Test status
Simulation time 166373517 ps
CPU time 0.79 seconds
Started Jun 10 05:29:16 PM PDT 24
Finished Jun 10 05:29:17 PM PDT 24
Peak memory 205056 kb
Host smart-70388388-db3f-4dcd-9e78-9c7b3e62aa3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16895
89460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1689589460
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.4285487183
Short name T787
Test name
Test status
Simulation time 200360045 ps
CPU time 0.82 seconds
Started Jun 10 05:29:28 PM PDT 24
Finished Jun 10 05:29:29 PM PDT 24
Peak memory 205028 kb
Host smart-18f74674-1413-45c7-aebf-b3399a7cff71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42854
87183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.4285487183
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.636927121
Short name T32
Test name
Test status
Simulation time 166695136 ps
CPU time 0.83 seconds
Started Jun 10 05:28:55 PM PDT 24
Finished Jun 10 05:28:56 PM PDT 24
Peak memory 204984 kb
Host smart-605d71be-0fac-44d9-951c-5bce28bd8f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63692
7121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.636927121
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_eop_single_bit_handling.4218082339
Short name T1332
Test name
Test status
Simulation time 158555296 ps
CPU time 0.77 seconds
Started Jun 10 05:28:55 PM PDT 24
Finished Jun 10 05:28:56 PM PDT 24
Peak memory 204988 kb
Host smart-1ac6dbe2-f377-4f0b-9fa6-0d82b2f8c9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42180
82339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_eop_single_bit_handling.4218082339
Directory /workspace/49.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.1685520410
Short name T79
Test name
Test status
Simulation time 148429089 ps
CPU time 0.75 seconds
Started Jun 10 05:29:29 PM PDT 24
Finished Jun 10 05:29:33 PM PDT 24
Peak memory 205056 kb
Host smart-31db2a13-57a3-4637-a925-e9b1b7906006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16855
20410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.1685520410
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3515450948
Short name T430
Test name
Test status
Simulation time 33537607 ps
CPU time 0.64 seconds
Started Jun 10 05:28:52 PM PDT 24
Finished Jun 10 05:28:53 PM PDT 24
Peak memory 205012 kb
Host smart-7732ae5e-fc91-4b08-a4f8-8843c47383e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35154
50948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3515450948
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1245279486
Short name T900
Test name
Test status
Simulation time 18016857618 ps
CPU time 44.43 seconds
Started Jun 10 05:29:12 PM PDT 24
Finished Jun 10 05:29:57 PM PDT 24
Peak memory 205164 kb
Host smart-acc84e07-7d50-4fc5-842b-514a1fa63b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12452
79486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1245279486
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1105074883
Short name T641
Test name
Test status
Simulation time 219927819 ps
CPU time 0.85 seconds
Started Jun 10 05:28:53 PM PDT 24
Finished Jun 10 05:28:54 PM PDT 24
Peak memory 204988 kb
Host smart-c7217621-d91b-4063-a8e9-d087be76c83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11050
74883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1105074883
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1346390360
Short name T1748
Test name
Test status
Simulation time 198789499 ps
CPU time 0.88 seconds
Started Jun 10 05:29:14 PM PDT 24
Finished Jun 10 05:29:15 PM PDT 24
Peak memory 204900 kb
Host smart-dfe5be74-1b89-4d36-9c58-e81a5f273008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13463
90360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1346390360
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.2878686432
Short name T1826
Test name
Test status
Simulation time 243640110 ps
CPU time 0.92 seconds
Started Jun 10 05:29:39 PM PDT 24
Finished Jun 10 05:29:40 PM PDT 24
Peak memory 204992 kb
Host smart-d27416f1-604f-4efa-9c9a-e10b000544a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28786
86432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.2878686432
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.491266067
Short name T1608
Test name
Test status
Simulation time 141294383 ps
CPU time 0.72 seconds
Started Jun 10 05:29:08 PM PDT 24
Finished Jun 10 05:29:09 PM PDT 24
Peak memory 204812 kb
Host smart-3de2da7d-7ca7-4441-b7cc-8eb40e61a7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49126
6067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.491266067
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2974608189
Short name T90
Test name
Test status
Simulation time 163553195 ps
CPU time 0.75 seconds
Started Jun 10 05:29:19 PM PDT 24
Finished Jun 10 05:29:20 PM PDT 24
Peak memory 204992 kb
Host smart-90b6b3fb-a06f-43ba-814b-4a370362a077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29746
08189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2974608189
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3917221666
Short name T1061
Test name
Test status
Simulation time 169882125 ps
CPU time 0.82 seconds
Started Jun 10 05:28:57 PM PDT 24
Finished Jun 10 05:28:58 PM PDT 24
Peak memory 204976 kb
Host smart-9861f781-e59e-4819-bdfb-acf8d8958cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39172
21666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3917221666
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.568341651
Short name T1835
Test name
Test status
Simulation time 247098810 ps
CPU time 0.94 seconds
Started Jun 10 05:29:12 PM PDT 24
Finished Jun 10 05:29:14 PM PDT 24
Peak memory 205032 kb
Host smart-4d4e07e5-3bbc-4bb1-9d5c-ff2ea051a5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56834
1651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.568341651
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2438932456
Short name T761
Test name
Test status
Simulation time 208950295 ps
CPU time 0.88 seconds
Started Jun 10 05:28:55 PM PDT 24
Finished Jun 10 05:28:56 PM PDT 24
Peak memory 205008 kb
Host smart-0478dcf4-0dc7-4832-85a2-b516434862d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24389
32456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2438932456
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1052492549
Short name T1203
Test name
Test status
Simulation time 168775491 ps
CPU time 0.79 seconds
Started Jun 10 05:29:07 PM PDT 24
Finished Jun 10 05:29:08 PM PDT 24
Peak memory 205032 kb
Host smart-40ad6add-4264-40fe-bd85-4a7000a37a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10524
92549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1052492549
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.1193629631
Short name T1779
Test name
Test status
Simulation time 7095344246 ps
CPU time 53.07 seconds
Started Jun 10 05:29:16 PM PDT 24
Finished Jun 10 05:30:09 PM PDT 24
Peak memory 205216 kb
Host smart-7df01afd-6e00-4f4c-890e-a03b4144dabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11936
29631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1193629631
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.1302363111
Short name T157
Test name
Test status
Simulation time 227599274 ps
CPU time 0.99 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:24:45 PM PDT 24
Peak memory 204952 kb
Host smart-aa9e11df-f167-4013-8598-a712df7661f2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1302363111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.1302363111
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.110141623
Short name T1085
Test name
Test status
Simulation time 156714302 ps
CPU time 0.81 seconds
Started Jun 10 05:24:49 PM PDT 24
Finished Jun 10 05:24:51 PM PDT 24
Peak memory 204972 kb
Host smart-ab814f1b-9e2a-4cca-b75d-33a730a50bca
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=110141623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.110141623
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.3211260518
Short name T1272
Test name
Test status
Simulation time 217962453 ps
CPU time 0.86 seconds
Started Jun 10 05:24:38 PM PDT 24
Finished Jun 10 05:24:40 PM PDT 24
Peak memory 205096 kb
Host smart-604b1db8-d77f-4aa6-a278-00e93aaf05bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32112
60518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.3211260518
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.2809934365
Short name T1188
Test name
Test status
Simulation time 3526446776 ps
CPU time 4.56 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:51 PM PDT 24
Peak memory 205160 kb
Host smart-46119283-b209-4e45-bfb9-9022fc9f8929
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2809934365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.2809934365
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.4272430356
Short name T628
Test name
Test status
Simulation time 13296647735 ps
CPU time 12.56 seconds
Started Jun 10 05:24:38 PM PDT 24
Finished Jun 10 05:24:51 PM PDT 24
Peak memory 205088 kb
Host smart-3eca745f-3934-47a6-8f11-fc55b77ebe69
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4272430356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.4272430356
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.3322341685
Short name T736
Test name
Test status
Simulation time 23324907951 ps
CPU time 24.4 seconds
Started Jun 10 05:24:46 PM PDT 24
Finished Jun 10 05:25:12 PM PDT 24
Peak memory 205072 kb
Host smart-37eb4cf5-1659-4337-8bc5-38ba861863e7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3322341685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.3322341685
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.90295469
Short name T1122
Test name
Test status
Simulation time 152505314 ps
CPU time 0.83 seconds
Started Jun 10 05:24:32 PM PDT 24
Finished Jun 10 05:24:34 PM PDT 24
Peak memory 204968 kb
Host smart-70641d29-6148-42e4-b2cd-62556a9b987d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90295
469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.90295469
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3335501626
Short name T1565
Test name
Test status
Simulation time 171009067 ps
CPU time 0.83 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:24:44 PM PDT 24
Peak memory 205044 kb
Host smart-857b7a6a-69c6-41b9-82f5-e6b4cae2e789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33355
01626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3335501626
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2382255596
Short name T1183
Test name
Test status
Simulation time 407891862 ps
CPU time 1.17 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:24:45 PM PDT 24
Peak memory 205020 kb
Host smart-bc80972d-03ea-4bab-9b0e-e04690962b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23822
55596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2382255596
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.2860391179
Short name T1460
Test name
Test status
Simulation time 163788401 ps
CPU time 0.79 seconds
Started Jun 10 05:24:47 PM PDT 24
Finished Jun 10 05:24:49 PM PDT 24
Peak memory 205028 kb
Host smart-258495b8-c374-44b6-b648-243e93b073d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28603
91179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.2860391179
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.900290489
Short name T2050
Test name
Test status
Simulation time 33531987 ps
CPU time 0.65 seconds
Started Jun 10 05:24:39 PM PDT 24
Finished Jun 10 05:24:40 PM PDT 24
Peak memory 205032 kb
Host smart-f13818fd-f67e-44d3-ba86-b8d77da5abb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90029
0489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.900290489
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.268525009
Short name T941
Test name
Test status
Simulation time 925298801 ps
CPU time 2.15 seconds
Started Jun 10 05:24:46 PM PDT 24
Finished Jun 10 05:24:49 PM PDT 24
Peak memory 205160 kb
Host smart-66f77a94-9a72-41e0-9584-596545c01e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26852
5009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.268525009
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.697396615
Short name T1825
Test name
Test status
Simulation time 308285100 ps
CPU time 2.3 seconds
Started Jun 10 05:24:41 PM PDT 24
Finished Jun 10 05:24:44 PM PDT 24
Peak memory 205072 kb
Host smart-5dea5851-22cd-4761-b851-da7ebe0438e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69739
6615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.697396615
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.1415620958
Short name T774
Test name
Test status
Simulation time 217394985 ps
CPU time 0.93 seconds
Started Jun 10 05:24:39 PM PDT 24
Finished Jun 10 05:24:40 PM PDT 24
Peak memory 205004 kb
Host smart-29fc2f74-72e0-4501-985b-92a31afdf1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14156
20958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.1415620958
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1795010155
Short name T1850
Test name
Test status
Simulation time 140863146 ps
CPU time 0.79 seconds
Started Jun 10 05:24:46 PM PDT 24
Finished Jun 10 05:24:48 PM PDT 24
Peak memory 204908 kb
Host smart-34af7d40-84b4-4a51-88fa-08f543e61510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17950
10155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1795010155
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1970282272
Short name T1384
Test name
Test status
Simulation time 177089925 ps
CPU time 0.87 seconds
Started Jun 10 05:24:44 PM PDT 24
Finished Jun 10 05:24:45 PM PDT 24
Peak memory 205052 kb
Host smart-b1ecfa27-23df-4495-8a46-63e4b54c35ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19702
82272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1970282272
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.2312813306
Short name T833
Test name
Test status
Simulation time 166165067 ps
CPU time 0.8 seconds
Started Jun 10 05:24:41 PM PDT 24
Finished Jun 10 05:24:42 PM PDT 24
Peak memory 205036 kb
Host smart-fd709c15-705c-46ea-8176-4616bb27979a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23128
13306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.2312813306
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.3781133172
Short name T162
Test name
Test status
Simulation time 3284229859 ps
CPU time 3.83 seconds
Started Jun 10 05:24:41 PM PDT 24
Finished Jun 10 05:24:45 PM PDT 24
Peak memory 205080 kb
Host smart-cf0124c2-a481-40f3-8fc1-260c65161935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37811
33172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.3781133172
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.54639571
Short name T348
Test name
Test status
Simulation time 197320768 ps
CPU time 0.89 seconds
Started Jun 10 05:24:38 PM PDT 24
Finished Jun 10 05:24:40 PM PDT 24
Peak memory 204988 kb
Host smart-ae06a88d-c05d-43c8-b9d2-e215cc14d942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54639
571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.54639571
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.3877183148
Short name T2013
Test name
Test status
Simulation time 7771558575 ps
CPU time 215.12 seconds
Started Jun 10 05:24:46 PM PDT 24
Finished Jun 10 05:28:22 PM PDT 24
Peak memory 205232 kb
Host smart-f6a5fd20-65ef-4189-94e4-a05593093547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38771
83148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.3877183148
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3610067072
Short name T321
Test name
Test status
Simulation time 161188185 ps
CPU time 0.81 seconds
Started Jun 10 05:24:39 PM PDT 24
Finished Jun 10 05:24:40 PM PDT 24
Peak memory 204888 kb
Host smart-0f445752-e991-4167-b84f-8699b5f01ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36100
67072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3610067072
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.635373410
Short name T2049
Test name
Test status
Simulation time 218394266 ps
CPU time 0.91 seconds
Started Jun 10 05:24:42 PM PDT 24
Finished Jun 10 05:24:43 PM PDT 24
Peak memory 204980 kb
Host smart-b6f0f064-2a46-4ec2-8673-7cac16cc113f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63537
3410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.635373410
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.4068667237
Short name T1427
Test name
Test status
Simulation time 203636171 ps
CPU time 0.84 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:46 PM PDT 24
Peak memory 205044 kb
Host smart-f06f0c23-8978-4721-8d9a-e332335a28aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40686
67237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.4068667237
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1128507170
Short name T1327
Test name
Test status
Simulation time 208753892 ps
CPU time 0.87 seconds
Started Jun 10 05:24:41 PM PDT 24
Finished Jun 10 05:24:43 PM PDT 24
Peak memory 205036 kb
Host smart-b80f23e4-486f-4bad-b6e3-c9ffb4ea0e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11285
07170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1128507170
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2380917870
Short name T702
Test name
Test status
Simulation time 148522179 ps
CPU time 0.78 seconds
Started Jun 10 05:24:38 PM PDT 24
Finished Jun 10 05:24:40 PM PDT 24
Peak memory 205008 kb
Host smart-61fa2659-01c6-4b53-a154-f60d9bea43fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23809
17870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2380917870
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.182172584
Short name T185
Test name
Test status
Simulation time 150586517 ps
CPU time 0.8 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:47 PM PDT 24
Peak memory 204992 kb
Host smart-91a323d1-095f-40e6-84d5-1a280e0d30e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18217
2584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.182172584
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_eop_single_bit_handling.1607143043
Short name T705
Test name
Test status
Simulation time 180801327 ps
CPU time 0.86 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:47 PM PDT 24
Peak memory 205056 kb
Host smart-89bd6f56-af52-4c70-9015-95da72a8ad2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16071
43043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_eop_single_bit_handling.1607143043
Directory /workspace/5.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2529716792
Short name T1551
Test name
Test status
Simulation time 143125515 ps
CPU time 0.78 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:47 PM PDT 24
Peak memory 204992 kb
Host smart-061125f0-b766-4ed6-9381-1ec5fe1d5056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25297
16792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2529716792
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.316152337
Short name T680
Test name
Test status
Simulation time 37699820 ps
CPU time 0.66 seconds
Started Jun 10 05:24:41 PM PDT 24
Finished Jun 10 05:24:42 PM PDT 24
Peak memory 204892 kb
Host smart-b3a76ae2-865f-4f5e-beb1-862efb6594e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31615
2337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.316152337
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.1209895537
Short name T1109
Test name
Test status
Simulation time 9162290671 ps
CPU time 23.02 seconds
Started Jun 10 05:24:50 PM PDT 24
Finished Jun 10 05:25:14 PM PDT 24
Peak memory 205220 kb
Host smart-7ee4c8d0-c83c-4637-bca7-d01e3bd3049b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12098
95537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.1209895537
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.371150334
Short name T2028
Test name
Test status
Simulation time 207653053 ps
CPU time 0.85 seconds
Started Jun 10 05:24:51 PM PDT 24
Finished Jun 10 05:24:53 PM PDT 24
Peak memory 205024 kb
Host smart-d5205e24-814b-4c29-80c8-7e315eed4a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37115
0334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.371150334
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1139578119
Short name T558
Test name
Test status
Simulation time 272483877 ps
CPU time 0.98 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:47 PM PDT 24
Peak memory 204908 kb
Host smart-d7a1835e-beaa-4e18-ad4e-5a3edae89a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11395
78119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1139578119
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.62079571
Short name T1526
Test name
Test status
Simulation time 23704433298 ps
CPU time 621.9 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:35:06 PM PDT 24
Peak memory 205304 kb
Host smart-a576ac25-b3e4-4b9b-869c-8fea4dc9b12b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=62079571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.62079571
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.922451065
Short name T1888
Test name
Test status
Simulation time 17898749828 ps
CPU time 134.59 seconds
Started Jun 10 05:24:47 PM PDT 24
Finished Jun 10 05:27:03 PM PDT 24
Peak memory 205220 kb
Host smart-d244f8cf-3b5b-4426-9044-a6bd5e0c6a23
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=922451065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.922451065
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.2220773956
Short name T1201
Test name
Test status
Simulation time 39049229426 ps
CPU time 947.22 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:40:33 PM PDT 24
Peak memory 205272 kb
Host smart-094a1965-a1c9-436b-aac5-21d751aa5dee
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2220773956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.2220773956
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.1876614107
Short name T630
Test name
Test status
Simulation time 177508240 ps
CPU time 0.82 seconds
Started Jun 10 05:24:41 PM PDT 24
Finished Jun 10 05:24:43 PM PDT 24
Peak memory 205008 kb
Host smart-317dcf74-9f17-4ca0-955e-2a250d93d3a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18766
14107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.1876614107
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.740858834
Short name T1931
Test name
Test status
Simulation time 152682623 ps
CPU time 0.77 seconds
Started Jun 10 05:24:47 PM PDT 24
Finished Jun 10 05:24:49 PM PDT 24
Peak memory 204992 kb
Host smart-b24c5f6b-5e17-4e9a-b966-622af0c56d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74085
8834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.740858834
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.4181600010
Short name T1244
Test name
Test status
Simulation time 156077283 ps
CPU time 0.78 seconds
Started Jun 10 05:24:42 PM PDT 24
Finished Jun 10 05:24:44 PM PDT 24
Peak memory 205016 kb
Host smart-6af1b154-ead6-4d71-a16b-91d29a1c5ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41816
00010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.4181600010
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1800515900
Short name T1301
Test name
Test status
Simulation time 167808475 ps
CPU time 0.84 seconds
Started Jun 10 05:24:46 PM PDT 24
Finished Jun 10 05:24:48 PM PDT 24
Peak memory 205056 kb
Host smart-07ab7713-fed8-48ca-97c6-ae1c03550be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18005
15900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1800515900
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1624028450
Short name T1890
Test name
Test status
Simulation time 253713660 ps
CPU time 0.95 seconds
Started Jun 10 05:24:42 PM PDT 24
Finished Jun 10 05:24:45 PM PDT 24
Peak memory 205024 kb
Host smart-cb2f3077-81e4-44c0-aa63-d191078ce920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16240
28450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1624028450
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3328230889
Short name T708
Test name
Test status
Simulation time 182417153 ps
CPU time 0.84 seconds
Started Jun 10 05:24:39 PM PDT 24
Finished Jun 10 05:24:40 PM PDT 24
Peak memory 205024 kb
Host smart-f806b6f7-84cf-4f10-8271-29b98aafeb79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33282
30889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3328230889
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1259050666
Short name T2048
Test name
Test status
Simulation time 180455325 ps
CPU time 0.88 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:24:45 PM PDT 24
Peak memory 205008 kb
Host smart-9d174301-e53e-4832-90a3-7ca77893c0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12590
50666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1259050666
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.3613890488
Short name T623
Test name
Test status
Simulation time 10924655016 ps
CPU time 80.97 seconds
Started Jun 10 05:24:52 PM PDT 24
Finished Jun 10 05:26:13 PM PDT 24
Peak memory 205160 kb
Host smart-ca406aa4-450c-42f5-a25d-6b22ee528e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36138
90488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.3613890488
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.3835325212
Short name T314
Test name
Test status
Simulation time 284081551 ps
CPU time 0.91 seconds
Started Jun 10 05:24:59 PM PDT 24
Finished Jun 10 05:25:00 PM PDT 24
Peak memory 205016 kb
Host smart-02820fbf-a1b7-4c2d-ab15-27ce03752cde
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3835325212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.3835325212
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.3111659749
Short name T571
Test name
Test status
Simulation time 158695880 ps
CPU time 0.81 seconds
Started Jun 10 05:24:46 PM PDT 24
Finished Jun 10 05:24:48 PM PDT 24
Peak memory 204996 kb
Host smart-452b1cd2-2d06-42c0-8461-f505c0d11326
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3111659749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.3111659749
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.124772238
Short name T842
Test name
Test status
Simulation time 221115846 ps
CPU time 0.89 seconds
Started Jun 10 05:24:48 PM PDT 24
Finished Jun 10 05:24:50 PM PDT 24
Peak memory 204976 kb
Host smart-61efae20-0304-4645-bafc-5f493040fda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12477
2238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.124772238
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3546582388
Short name T460
Test name
Test status
Simulation time 3687795143 ps
CPU time 5.28 seconds
Started Jun 10 05:24:57 PM PDT 24
Finished Jun 10 05:25:03 PM PDT 24
Peak memory 205076 kb
Host smart-e0e2b37a-4224-486c-b1a1-f198df3bc42c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3546582388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.3546582388
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.1129284232
Short name T1605
Test name
Test status
Simulation time 13424822516 ps
CPU time 13.08 seconds
Started Jun 10 05:24:46 PM PDT 24
Finished Jun 10 05:25:01 PM PDT 24
Peak memory 205164 kb
Host smart-1971ffeb-5436-4fea-adf4-b754c1556cac
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1129284232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.1129284232
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.674221459
Short name T15
Test name
Test status
Simulation time 23314896549 ps
CPU time 26.74 seconds
Started Jun 10 05:24:47 PM PDT 24
Finished Jun 10 05:25:15 PM PDT 24
Peak memory 205092 kb
Host smart-c9ff534f-be3c-4e28-853f-0fd942166904
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=674221459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.674221459
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.774056523
Short name T1610
Test name
Test status
Simulation time 162790331 ps
CPU time 0.85 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:47 PM PDT 24
Peak memory 204876 kb
Host smart-f64d9cf2-bf14-4540-bc00-f61227a3378b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77405
6523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.774056523
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.2840045660
Short name T1893
Test name
Test status
Simulation time 177405317 ps
CPU time 0.85 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:24:45 PM PDT 24
Peak memory 205000 kb
Host smart-d3db9f2b-009c-4d65-b1de-c583e3787a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28400
45660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.2840045660
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1416498960
Short name T1474
Test name
Test status
Simulation time 1757099887 ps
CPU time 3.97 seconds
Started Jun 10 05:24:48 PM PDT 24
Finished Jun 10 05:24:53 PM PDT 24
Peak memory 204988 kb
Host smart-07c22173-d030-4251-9930-08986889819c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14164
98960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1416498960
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.395029635
Short name T890
Test name
Test status
Simulation time 139527773 ps
CPU time 0.79 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:47 PM PDT 24
Peak memory 204904 kb
Host smart-65544cde-55dc-492c-8968-d3453009283c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39502
9635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.395029635
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3644651295
Short name T1534
Test name
Test status
Simulation time 80195380 ps
CPU time 0.7 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:47 PM PDT 24
Peak memory 204896 kb
Host smart-e97bb6cd-c8c1-4760-8998-583b041b1f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36446
51295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3644651295
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3219225925
Short name T1352
Test name
Test status
Simulation time 837267259 ps
CPU time 2.14 seconds
Started Jun 10 05:24:43 PM PDT 24
Finished Jun 10 05:24:46 PM PDT 24
Peak memory 205180 kb
Host smart-57dcce01-b2b0-42ac-8b6c-2e7692963bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32192
25925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3219225925
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1633457087
Short name T943
Test name
Test status
Simulation time 208721905 ps
CPU time 2.23 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:49 PM PDT 24
Peak memory 205196 kb
Host smart-45b8f59c-2846-496b-a896-1f270ef9f326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16334
57087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1633457087
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2240753129
Short name T875
Test name
Test status
Simulation time 226313218 ps
CPU time 0.89 seconds
Started Jun 10 05:24:48 PM PDT 24
Finished Jun 10 05:24:50 PM PDT 24
Peak memory 205008 kb
Host smart-7f78fa94-68f4-481d-9901-8c483bdc2feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22407
53129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2240753129
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2143025834
Short name T1430
Test name
Test status
Simulation time 148058309 ps
CPU time 0.78 seconds
Started Jun 10 05:24:52 PM PDT 24
Finished Jun 10 05:24:53 PM PDT 24
Peak memory 205080 kb
Host smart-4058b44f-2ad5-4e13-953d-f922875ae06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21430
25834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2143025834
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2450216808
Short name T573
Test name
Test status
Simulation time 235786364 ps
CPU time 0.93 seconds
Started Jun 10 05:24:51 PM PDT 24
Finished Jun 10 05:24:52 PM PDT 24
Peak memory 205048 kb
Host smart-e221e54f-d873-4d65-9163-53b221a86243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24502
16808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2450216808
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.2427996937
Short name T510
Test name
Test status
Simulation time 262510445 ps
CPU time 0.91 seconds
Started Jun 10 05:24:54 PM PDT 24
Finished Jun 10 05:24:55 PM PDT 24
Peak memory 205040 kb
Host smart-82e42d9c-d606-426f-ba1a-dff73ffe8b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24279
96937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2427996937
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.4180545757
Short name T1611
Test name
Test status
Simulation time 3385499929 ps
CPU time 4 seconds
Started Jun 10 05:24:50 PM PDT 24
Finished Jun 10 05:24:55 PM PDT 24
Peak memory 205084 kb
Host smart-e2eab045-3641-48a3-bf35-860924592072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41805
45757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.4180545757
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.73572345
Short name T1650
Test name
Test status
Simulation time 192594500 ps
CPU time 0.92 seconds
Started Jun 10 05:24:57 PM PDT 24
Finished Jun 10 05:24:58 PM PDT 24
Peak memory 205000 kb
Host smart-47ca7742-567e-4b83-a91a-c30b7a49be02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73572
345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.73572345
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.1213534167
Short name T161
Test name
Test status
Simulation time 12055250371 ps
CPU time 330.35 seconds
Started Jun 10 05:24:57 PM PDT 24
Finished Jun 10 05:30:27 PM PDT 24
Peak memory 205216 kb
Host smart-5f74c8fd-af90-4e5b-a99c-7482a0099da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12135
34167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.1213534167
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1991354471
Short name T501
Test name
Test status
Simulation time 145223901 ps
CPU time 0.82 seconds
Started Jun 10 05:24:46 PM PDT 24
Finished Jun 10 05:24:48 PM PDT 24
Peak memory 205008 kb
Host smart-4f198550-b270-4248-8701-302d5e888aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19913
54471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1991354471
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3628029773
Short name T1964
Test name
Test status
Simulation time 226234708 ps
CPU time 0.93 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:46 PM PDT 24
Peak memory 205008 kb
Host smart-75c04623-3617-4613-9006-1cf1bd7314ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36280
29773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3628029773
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.2722304264
Short name T1082
Test name
Test status
Simulation time 162274479 ps
CPU time 0.81 seconds
Started Jun 10 05:24:56 PM PDT 24
Finished Jun 10 05:24:57 PM PDT 24
Peak memory 205028 kb
Host smart-aa5fc2a1-6df8-4c5f-b293-85e1a9f0efe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27223
04264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.2722304264
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2602118547
Short name T1882
Test name
Test status
Simulation time 159410474 ps
CPU time 0.79 seconds
Started Jun 10 05:24:56 PM PDT 24
Finished Jun 10 05:24:57 PM PDT 24
Peak memory 205024 kb
Host smart-1e196ddf-52aa-468f-ad04-08a823505729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26021
18547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2602118547
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.4200577548
Short name T1731
Test name
Test status
Simulation time 189698307 ps
CPU time 0.86 seconds
Started Jun 10 05:24:48 PM PDT 24
Finished Jun 10 05:24:50 PM PDT 24
Peak memory 204996 kb
Host smart-0003ea2f-3f2d-4926-98ed-b9a044a09367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42005
77548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.4200577548
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.4043849003
Short name T1875
Test name
Test status
Simulation time 160808145 ps
CPU time 0.78 seconds
Started Jun 10 05:24:48 PM PDT 24
Finished Jun 10 05:24:50 PM PDT 24
Peak memory 205004 kb
Host smart-a1f2c3c2-7b99-423d-8f76-9d5700d1f291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40438
49003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.4043849003
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_eop_single_bit_handling.2680241157
Short name T598
Test name
Test status
Simulation time 265099730 ps
CPU time 0.87 seconds
Started Jun 10 05:24:54 PM PDT 24
Finished Jun 10 05:24:55 PM PDT 24
Peak memory 204856 kb
Host smart-044e2d2a-c7c0-4438-bfd7-30d15cf06caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26802
41157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_eop_single_bit_handling.2680241157
Directory /workspace/6.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2905417380
Short name T1646
Test name
Test status
Simulation time 145624375 ps
CPU time 0.81 seconds
Started Jun 10 05:24:49 PM PDT 24
Finished Jun 10 05:24:50 PM PDT 24
Peak memory 205092 kb
Host smart-f1967f6a-299e-4102-aff5-a1b15565e30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29054
17380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2905417380
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.3577726108
Short name T1206
Test name
Test status
Simulation time 34664023 ps
CPU time 0.63 seconds
Started Jun 10 05:24:52 PM PDT 24
Finished Jun 10 05:24:53 PM PDT 24
Peak memory 205012 kb
Host smart-f5c5514a-2140-40bc-9104-e5b35839a3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35777
26108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3577726108
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.196958200
Short name T1481
Test name
Test status
Simulation time 19398599411 ps
CPU time 45.11 seconds
Started Jun 10 05:24:52 PM PDT 24
Finished Jun 10 05:25:38 PM PDT 24
Peak memory 205264 kb
Host smart-89002606-e562-418e-b41b-4def6ce86c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19695
8200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.196958200
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.3277344951
Short name T1583
Test name
Test status
Simulation time 158911757 ps
CPU time 0.78 seconds
Started Jun 10 05:24:51 PM PDT 24
Finished Jun 10 05:24:52 PM PDT 24
Peak memory 205024 kb
Host smart-64201960-790b-436a-86f6-69af58c68482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32773
44951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3277344951
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1936589683
Short name T1313
Test name
Test status
Simulation time 233142899 ps
CPU time 0.9 seconds
Started Jun 10 05:24:48 PM PDT 24
Finished Jun 10 05:24:50 PM PDT 24
Peak memory 205004 kb
Host smart-c0c8dd37-1cce-4efb-89f9-208596b4d043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19365
89683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1936589683
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3641728430
Short name T211
Test name
Test status
Simulation time 30993330137 ps
CPU time 752.47 seconds
Started Jun 10 05:24:44 PM PDT 24
Finished Jun 10 05:37:17 PM PDT 24
Peak memory 205240 kb
Host smart-48cbdce3-0dc0-4a55-9602-b0613253d329
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3641728430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3641728430
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.1544090083
Short name T1493
Test name
Test status
Simulation time 15695315880 ps
CPU time 432.68 seconds
Started Jun 10 05:24:46 PM PDT 24
Finished Jun 10 05:32:00 PM PDT 24
Peak memory 205328 kb
Host smart-32ad96c3-c168-4e48-8c0d-f22363dcfbe9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1544090083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.1544090083
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.3027890383
Short name T1067
Test name
Test status
Simulation time 30380224435 ps
CPU time 176.66 seconds
Started Jun 10 05:24:52 PM PDT 24
Finished Jun 10 05:27:49 PM PDT 24
Peak memory 205244 kb
Host smart-72889206-996b-40a2-b9ab-ffdfbf7c8f6f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3027890383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.3027890383
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.1101549497
Short name T1007
Test name
Test status
Simulation time 194910686 ps
CPU time 0.89 seconds
Started Jun 10 05:24:45 PM PDT 24
Finished Jun 10 05:24:47 PM PDT 24
Peak memory 205012 kb
Host smart-951e7138-aac3-49fd-8722-1dc1aebd6601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11015
49497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.1101549497
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.4116110046
Short name T771
Test name
Test status
Simulation time 184760059 ps
CPU time 0.84 seconds
Started Jun 10 05:24:50 PM PDT 24
Finished Jun 10 05:24:52 PM PDT 24
Peak memory 205008 kb
Host smart-c5d50c72-59df-4115-8970-bcd9c27f70f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41161
10046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.4116110046
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.3242094905
Short name T1445
Test name
Test status
Simulation time 155589367 ps
CPU time 0.82 seconds
Started Jun 10 05:24:55 PM PDT 24
Finished Jun 10 05:24:57 PM PDT 24
Peak memory 204968 kb
Host smart-2c7dd535-4b61-4164-b7c6-052a4dfc0be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32420
94905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3242094905
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1524617251
Short name T1372
Test name
Test status
Simulation time 155455058 ps
CPU time 0.78 seconds
Started Jun 10 05:24:53 PM PDT 24
Finished Jun 10 05:24:54 PM PDT 24
Peak memory 205008 kb
Host smart-8c4ebe3d-2e7b-43ca-bb81-26bcc82a565f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15246
17251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1524617251
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2172449933
Short name T1059
Test name
Test status
Simulation time 222038301 ps
CPU time 0.97 seconds
Started Jun 10 05:24:56 PM PDT 24
Finished Jun 10 05:24:57 PM PDT 24
Peak memory 205040 kb
Host smart-fd211443-c4a1-4dc3-8723-c0d3ca73293b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21724
49933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2172449933
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.1375587889
Short name T1240
Test name
Test status
Simulation time 186455866 ps
CPU time 0.83 seconds
Started Jun 10 05:24:50 PM PDT 24
Finished Jun 10 05:24:52 PM PDT 24
Peak memory 204992 kb
Host smart-4ef7a4c8-413f-4a2d-9e92-734078812dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13755
87889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.1375587889
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.856592150
Short name T993
Test name
Test status
Simulation time 197806035 ps
CPU time 0.87 seconds
Started Jun 10 05:24:57 PM PDT 24
Finished Jun 10 05:24:58 PM PDT 24
Peak memory 205012 kb
Host smart-67af2b6c-0223-4d22-bbb4-8c1af59b47a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85659
2150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.856592150
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3687354618
Short name T1409
Test name
Test status
Simulation time 6400972120 ps
CPU time 45.09 seconds
Started Jun 10 05:24:53 PM PDT 24
Finished Jun 10 05:25:38 PM PDT 24
Peak memory 205220 kb
Host smart-73a9420c-f3d0-42bb-ae23-d86493a66d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36873
54618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3687354618
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.1671002706
Short name T660
Test name
Test status
Simulation time 286947933 ps
CPU time 0.92 seconds
Started Jun 10 05:24:59 PM PDT 24
Finished Jun 10 05:25:00 PM PDT 24
Peak memory 205024 kb
Host smart-77644ad6-e835-4031-9087-e5b54a5a9569
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1671002706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.1671002706
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.1498653376
Short name T1889
Test name
Test status
Simulation time 172387842 ps
CPU time 0.86 seconds
Started Jun 10 05:24:57 PM PDT 24
Finished Jun 10 05:24:58 PM PDT 24
Peak memory 205024 kb
Host smart-a62bf9e8-4115-411d-877b-ca53a5a2800a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1498653376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.1498653376
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.3575302134
Short name T1524
Test name
Test status
Simulation time 195657351 ps
CPU time 0.83 seconds
Started Jun 10 05:25:04 PM PDT 24
Finished Jun 10 05:25:05 PM PDT 24
Peak memory 205008 kb
Host smart-60839abe-a2a8-4a22-8dcd-3550b908ba2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35753
02134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.3575302134
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1934112214
Short name T12
Test name
Test status
Simulation time 4069125177 ps
CPU time 5.15 seconds
Started Jun 10 05:24:51 PM PDT 24
Finished Jun 10 05:24:56 PM PDT 24
Peak memory 205276 kb
Host smart-6bd80895-7946-4840-b1e1-c7c0fdc377c6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1934112214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.1934112214
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.2775527599
Short name T1404
Test name
Test status
Simulation time 13307331126 ps
CPU time 12.61 seconds
Started Jun 10 05:24:55 PM PDT 24
Finished Jun 10 05:25:08 PM PDT 24
Peak memory 205120 kb
Host smart-cf62a134-9710-431c-81e9-6a1eee97b0df
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2775527599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.2775527599
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.1979053744
Short name T947
Test name
Test status
Simulation time 23359893579 ps
CPU time 22.48 seconds
Started Jun 10 05:24:49 PM PDT 24
Finished Jun 10 05:25:12 PM PDT 24
Peak memory 205180 kb
Host smart-b50f4a39-c2d1-4862-8bc6-690b3019aa35
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1979053744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.1979053744
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2717955696
Short name T543
Test name
Test status
Simulation time 173429432 ps
CPU time 0.8 seconds
Started Jun 10 05:24:52 PM PDT 24
Finished Jun 10 05:24:53 PM PDT 24
Peak memory 205044 kb
Host smart-8ee1d15e-c631-420c-96f8-42e0d89b5694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27179
55696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2717955696
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.1618761727
Short name T1837
Test name
Test status
Simulation time 141823488 ps
CPU time 0.79 seconds
Started Jun 10 05:24:55 PM PDT 24
Finished Jun 10 05:24:56 PM PDT 24
Peak memory 205036 kb
Host smart-5281afbf-8f63-4b2d-a6cf-fdce038013d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16187
61727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.1618761727
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3623813658
Short name T1020
Test name
Test status
Simulation time 836420827 ps
CPU time 2.29 seconds
Started Jun 10 05:24:57 PM PDT 24
Finished Jun 10 05:24:59 PM PDT 24
Peak memory 205152 kb
Host smart-c0800276-fbae-4451-ada1-db043e1fba4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36238
13658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3623813658
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3232696145
Short name T764
Test name
Test status
Simulation time 165093791 ps
CPU time 0.76 seconds
Started Jun 10 05:25:01 PM PDT 24
Finished Jun 10 05:25:02 PM PDT 24
Peak memory 205008 kb
Host smart-3af9f0cf-1c02-4681-bcdb-ef136f29aa6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32326
96145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3232696145
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3371418621
Short name T1195
Test name
Test status
Simulation time 46737792 ps
CPU time 0.68 seconds
Started Jun 10 05:24:52 PM PDT 24
Finished Jun 10 05:24:53 PM PDT 24
Peak memory 205064 kb
Host smart-d5a814e6-c62a-4715-9747-33f384663848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33714
18621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3371418621
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1223063805
Short name T521
Test name
Test status
Simulation time 976430223 ps
CPU time 2.22 seconds
Started Jun 10 05:24:47 PM PDT 24
Finished Jun 10 05:24:51 PM PDT 24
Peak memory 205140 kb
Host smart-38d46ce5-5f9f-4555-988c-0738b530332c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12230
63805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1223063805
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.250352345
Short name T1885
Test name
Test status
Simulation time 205263162 ps
CPU time 1.44 seconds
Started Jun 10 05:24:54 PM PDT 24
Finished Jun 10 05:24:56 PM PDT 24
Peak memory 205196 kb
Host smart-d0cb90b4-3253-45f1-8861-fcfc5eb03344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25035
2345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.250352345
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.1213221603
Short name T931
Test name
Test status
Simulation time 233522720 ps
CPU time 0.95 seconds
Started Jun 10 05:24:56 PM PDT 24
Finished Jun 10 05:24:57 PM PDT 24
Peak memory 205004 kb
Host smart-9c46f7d7-e784-4df4-9357-3871536751fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12132
21603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.1213221603
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2901062384
Short name T831
Test name
Test status
Simulation time 150248814 ps
CPU time 0.75 seconds
Started Jun 10 05:24:59 PM PDT 24
Finished Jun 10 05:25:00 PM PDT 24
Peak memory 205020 kb
Host smart-d80b2062-799c-44b2-99c4-89ddc49cc91d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29010
62384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2901062384
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.1750095735
Short name T1119
Test name
Test status
Simulation time 288834825 ps
CPU time 1.02 seconds
Started Jun 10 05:24:50 PM PDT 24
Finished Jun 10 05:24:52 PM PDT 24
Peak memory 205056 kb
Host smart-574f0edc-ab12-458a-86b6-52761bc77fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17500
95735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.1750095735
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.2881638387
Short name T516
Test name
Test status
Simulation time 208689876 ps
CPU time 0.86 seconds
Started Jun 10 05:24:51 PM PDT 24
Finished Jun 10 05:24:52 PM PDT 24
Peak memory 205048 kb
Host smart-4e8608d7-9bc8-4541-9719-f5c38a7b0d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28816
38387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2881638387
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.2224079420
Short name T981
Test name
Test status
Simulation time 3307079310 ps
CPU time 4.63 seconds
Started Jun 10 05:25:01 PM PDT 24
Finished Jun 10 05:25:06 PM PDT 24
Peak memory 205104 kb
Host smart-d958d97e-f568-490c-be28-7822db764b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22240
79420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.2224079420
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.788763811
Short name T1732
Test name
Test status
Simulation time 188483366 ps
CPU time 0.88 seconds
Started Jun 10 05:25:01 PM PDT 24
Finished Jun 10 05:25:02 PM PDT 24
Peak memory 205040 kb
Host smart-ebabdcaf-91d8-4e4a-8e78-00033c353285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78876
3811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.788763811
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.3617817937
Short name T1096
Test name
Test status
Simulation time 10182242484 ps
CPU time 280.36 seconds
Started Jun 10 05:24:52 PM PDT 24
Finished Jun 10 05:29:33 PM PDT 24
Peak memory 205272 kb
Host smart-7af1153e-bb0f-428c-9da3-23645ac68ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36178
17937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.3617817937
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1437995751
Short name T1480
Test name
Test status
Simulation time 146988685 ps
CPU time 0.8 seconds
Started Jun 10 05:24:51 PM PDT 24
Finished Jun 10 05:24:52 PM PDT 24
Peak memory 205020 kb
Host smart-61595767-d54e-4f26-9781-fca3f3c068f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14379
95751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1437995751
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.768737726
Short name T148
Test name
Test status
Simulation time 218933833 ps
CPU time 0.94 seconds
Started Jun 10 05:25:03 PM PDT 24
Finished Jun 10 05:25:05 PM PDT 24
Peak memory 205008 kb
Host smart-29c8c43d-b58d-494a-98b8-3482ef703c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76873
7726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.768737726
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.3988679556
Short name T1567
Test name
Test status
Simulation time 205747683 ps
CPU time 0.86 seconds
Started Jun 10 05:24:54 PM PDT 24
Finished Jun 10 05:24:56 PM PDT 24
Peak memory 205056 kb
Host smart-59559beb-d756-4aac-a764-84ce5e7f3b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39886
79556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.3988679556
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.4068973192
Short name T1775
Test name
Test status
Simulation time 188956618 ps
CPU time 0.79 seconds
Started Jun 10 05:24:50 PM PDT 24
Finished Jun 10 05:24:51 PM PDT 24
Peak memory 205000 kb
Host smart-d3759498-7cff-44dc-b7ab-752bbbf902c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40689
73192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.4068973192
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2200676764
Short name T1021
Test name
Test status
Simulation time 167389076 ps
CPU time 0.81 seconds
Started Jun 10 05:25:02 PM PDT 24
Finished Jun 10 05:25:03 PM PDT 24
Peak memory 205036 kb
Host smart-45b20e5c-fdd7-4091-8a9b-d6129bb849b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22006
76764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2200676764
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3023987594
Short name T657
Test name
Test status
Simulation time 154200700 ps
CPU time 0.81 seconds
Started Jun 10 05:25:02 PM PDT 24
Finished Jun 10 05:25:04 PM PDT 24
Peak memory 204984 kb
Host smart-69f1ac4a-31a4-4e71-9d92-0eac29387994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30239
87594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3023987594
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_eop_single_bit_handling.3158790075
Short name T399
Test name
Test status
Simulation time 171589650 ps
CPU time 0.85 seconds
Started Jun 10 05:24:56 PM PDT 24
Finished Jun 10 05:24:57 PM PDT 24
Peak memory 205028 kb
Host smart-4063f033-91ad-4728-b044-b309ddb9667c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31587
90075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_eop_single_bit_handling.3158790075
Directory /workspace/7.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.189187002
Short name T1827
Test name
Test status
Simulation time 159178580 ps
CPU time 0.84 seconds
Started Jun 10 05:25:02 PM PDT 24
Finished Jun 10 05:25:04 PM PDT 24
Peak memory 205016 kb
Host smart-5777baf7-69d3-44aa-8695-76d4e3616392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18918
7002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.189187002
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.600896134
Short name T39
Test name
Test status
Simulation time 40619333 ps
CPU time 0.67 seconds
Started Jun 10 05:25:02 PM PDT 24
Finished Jun 10 05:25:03 PM PDT 24
Peak memory 205016 kb
Host smart-4805b3cc-d1d7-4e19-9454-698ea33f47b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60089
6134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.600896134
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2911629539
Short name T727
Test name
Test status
Simulation time 17984432270 ps
CPU time 42.26 seconds
Started Jun 10 05:24:56 PM PDT 24
Finished Jun 10 05:25:39 PM PDT 24
Peak memory 205200 kb
Host smart-c0c6676f-5769-4953-882e-d36706297d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29116
29539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2911629539
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3458533379
Short name T1216
Test name
Test status
Simulation time 184271556 ps
CPU time 0.9 seconds
Started Jun 10 05:25:04 PM PDT 24
Finished Jun 10 05:25:05 PM PDT 24
Peak memory 205004 kb
Host smart-628d9aa4-8870-47ec-b3dd-98d471fd158a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34585
33379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3458533379
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1464168529
Short name T716
Test name
Test status
Simulation time 200946939 ps
CPU time 0.89 seconds
Started Jun 10 05:24:53 PM PDT 24
Finished Jun 10 05:24:54 PM PDT 24
Peak memory 205172 kb
Host smart-9f3ebac1-af84-406c-a659-5160970c56d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14641
68529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1464168529
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.2276993423
Short name T215
Test name
Test status
Simulation time 17826599693 ps
CPU time 107.39 seconds
Started Jun 10 05:24:52 PM PDT 24
Finished Jun 10 05:26:40 PM PDT 24
Peak memory 205200 kb
Host smart-47715582-7c3a-42b5-8ffa-e27cbcf93f4e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2276993423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.2276993423
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.3216469901
Short name T514
Test name
Test status
Simulation time 25958879675 ps
CPU time 244.16 seconds
Started Jun 10 05:24:59 PM PDT 24
Finished Jun 10 05:29:04 PM PDT 24
Peak memory 205256 kb
Host smart-9340b0fa-0c66-46dd-808d-4cce73fb7a0e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3216469901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.3216469901
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.268978886
Short name T700
Test name
Test status
Simulation time 14287032075 ps
CPU time 103.88 seconds
Started Jun 10 05:25:02 PM PDT 24
Finished Jun 10 05:26:47 PM PDT 24
Peak memory 205232 kb
Host smart-d65320e8-d35a-4a3a-bf54-7d3cb2c65430
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=268978886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.268978886
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.2137730279
Short name T909
Test name
Test status
Simulation time 170693965 ps
CPU time 0.81 seconds
Started Jun 10 05:24:57 PM PDT 24
Finished Jun 10 05:24:58 PM PDT 24
Peak memory 205004 kb
Host smart-105dd15c-2dca-4037-8656-655a8580260b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21377
30279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.2137730279
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2124136057
Short name T35
Test name
Test status
Simulation time 143984017 ps
CPU time 0.8 seconds
Started Jun 10 05:25:01 PM PDT 24
Finished Jun 10 05:25:02 PM PDT 24
Peak memory 205040 kb
Host smart-1f1ccabc-81d9-45d3-a88e-7193bc6774ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21241
36057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2124136057
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.4091953497
Short name T193
Test name
Test status
Simulation time 186539709 ps
CPU time 0.81 seconds
Started Jun 10 05:25:02 PM PDT 24
Finished Jun 10 05:25:03 PM PDT 24
Peak memory 204948 kb
Host smart-9b83c122-c7cc-45f8-85e7-17a9abb6fe01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40919
53497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.4091953497
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3617491458
Short name T1319
Test name
Test status
Simulation time 148817282 ps
CPU time 0.8 seconds
Started Jun 10 05:25:03 PM PDT 24
Finished Jun 10 05:25:04 PM PDT 24
Peak memory 204980 kb
Host smart-033e1ad5-bd58-4f03-98d9-2e6c8cbdd5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36174
91458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3617491458
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.919481342
Short name T1321
Test name
Test status
Simulation time 237688203 ps
CPU time 0.98 seconds
Started Jun 10 05:24:56 PM PDT 24
Finished Jun 10 05:24:57 PM PDT 24
Peak memory 204992 kb
Host smart-f81bc8fc-87cc-48e7-b274-f050f92b0580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91948
1342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.919481342
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.2602294539
Short name T1433
Test name
Test status
Simulation time 167386938 ps
CPU time 0.86 seconds
Started Jun 10 05:24:55 PM PDT 24
Finished Jun 10 05:24:56 PM PDT 24
Peak memory 205044 kb
Host smart-11868476-27d3-4435-ab4e-6e2aa146e007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26022
94539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.2602294539
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.3997831014
Short name T827
Test name
Test status
Simulation time 165955672 ps
CPU time 0.81 seconds
Started Jun 10 05:24:55 PM PDT 24
Finished Jun 10 05:24:56 PM PDT 24
Peak memory 205036 kb
Host smart-1fb34fee-f849-4c39-9fe5-0def584c40a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39978
31014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.3997831014
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3891507307
Short name T2070
Test name
Test status
Simulation time 9700398457 ps
CPU time 68.3 seconds
Started Jun 10 05:25:02 PM PDT 24
Finished Jun 10 05:26:11 PM PDT 24
Peak memory 205152 kb
Host smart-69bfc226-d86e-4613-809b-0404d35a36ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38915
07307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3891507307
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.3405484172
Short name T624
Test name
Test status
Simulation time 289046509 ps
CPU time 0.94 seconds
Started Jun 10 05:25:02 PM PDT 24
Finished Jun 10 05:25:03 PM PDT 24
Peak memory 205024 kb
Host smart-4dc20e1b-a883-416d-b028-f47146539d34
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3405484172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.3405484172
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.4134959371
Short name T1285
Test name
Test status
Simulation time 164972456 ps
CPU time 0.8 seconds
Started Jun 10 05:25:08 PM PDT 24
Finished Jun 10 05:25:10 PM PDT 24
Peak memory 205016 kb
Host smart-1d1193ac-fdb4-4167-b25b-3f11fe348642
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4134959371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.4134959371
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.2556516072
Short name T985
Test name
Test status
Simulation time 209121615 ps
CPU time 0.83 seconds
Started Jun 10 05:25:01 PM PDT 24
Finished Jun 10 05:25:02 PM PDT 24
Peak memory 205024 kb
Host smart-c227a808-9c8c-4606-8630-611fe2e2033a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25565
16072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.2556516072
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3601275849
Short name T1140
Test name
Test status
Simulation time 4104446630 ps
CPU time 4.77 seconds
Started Jun 10 05:24:55 PM PDT 24
Finished Jun 10 05:25:00 PM PDT 24
Peak memory 205092 kb
Host smart-62b10b9c-55ee-4eec-b3c3-cead4bb39472
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3601275849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.3601275849
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.3605043791
Short name T114
Test name
Test status
Simulation time 13380820308 ps
CPU time 12.97 seconds
Started Jun 10 05:25:03 PM PDT 24
Finished Jun 10 05:25:17 PM PDT 24
Peak memory 205144 kb
Host smart-c90efd6e-6c24-4abe-ae28-e60799c19d1e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3605043791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.3605043791
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.723097414
Short name T1079
Test name
Test status
Simulation time 23391967695 ps
CPU time 25.38 seconds
Started Jun 10 05:24:54 PM PDT 24
Finished Jun 10 05:25:19 PM PDT 24
Peak memory 205104 kb
Host smart-afe892b9-cb7c-48ef-ada1-8bbb2f22958c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=723097414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.723097414
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2970760082
Short name T539
Test name
Test status
Simulation time 173087057 ps
CPU time 0.79 seconds
Started Jun 10 05:24:52 PM PDT 24
Finished Jun 10 05:24:53 PM PDT 24
Peak memory 205008 kb
Host smart-a6528613-b118-4105-aa3e-0ae04cd60b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29707
60082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2970760082
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.2562433242
Short name T722
Test name
Test status
Simulation time 176760704 ps
CPU time 0.8 seconds
Started Jun 10 05:24:58 PM PDT 24
Finished Jun 10 05:24:59 PM PDT 24
Peak memory 205008 kb
Host smart-059a3bc7-a3a6-40bc-bf3e-173912612e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25624
33242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.2562433242
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.2300614755
Short name T199
Test name
Test status
Simulation time 845448268 ps
CPU time 2.1 seconds
Started Jun 10 05:24:53 PM PDT 24
Finished Jun 10 05:24:56 PM PDT 24
Peak memory 205120 kb
Host smart-8b6b682a-c0d3-4562-b639-cc9f459747a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23006
14755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.2300614755
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_enable.247061706
Short name T1034
Test name
Test status
Simulation time 59723625 ps
CPU time 0.7 seconds
Started Jun 10 05:25:02 PM PDT 24
Finished Jun 10 05:25:03 PM PDT 24
Peak memory 204972 kb
Host smart-3c04938b-dc75-4448-a02f-958af1d5d5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24706
1706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.247061706
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.776537686
Short name T450
Test name
Test status
Simulation time 1008132148 ps
CPU time 2.38 seconds
Started Jun 10 05:24:54 PM PDT 24
Finished Jun 10 05:24:57 PM PDT 24
Peak memory 205136 kb
Host smart-e98d0224-775d-4cca-8e27-e177e7891fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77653
7686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.776537686
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.998082854
Short name T1466
Test name
Test status
Simulation time 181224519 ps
CPU time 2.02 seconds
Started Jun 10 05:24:54 PM PDT 24
Finished Jun 10 05:24:56 PM PDT 24
Peak memory 205052 kb
Host smart-32a0953c-a3a8-4d1f-9948-f74ad9d6f042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99808
2854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.998082854
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.1669984822
Short name T1925
Test name
Test status
Simulation time 207802047 ps
CPU time 0.89 seconds
Started Jun 10 05:25:02 PM PDT 24
Finished Jun 10 05:25:03 PM PDT 24
Peak memory 204996 kb
Host smart-ab3d6424-3c46-4276-8011-d046271255d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16699
84822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.1669984822
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3342376354
Short name T1810
Test name
Test status
Simulation time 147718248 ps
CPU time 0.76 seconds
Started Jun 10 05:24:58 PM PDT 24
Finished Jun 10 05:24:59 PM PDT 24
Peak memory 204996 kb
Host smart-1e33aad1-83aa-458d-9b34-dcc3dd733ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33423
76354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3342376354
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1289304293
Short name T1917
Test name
Test status
Simulation time 222805672 ps
CPU time 0.86 seconds
Started Jun 10 05:24:58 PM PDT 24
Finished Jun 10 05:24:59 PM PDT 24
Peak memory 205004 kb
Host smart-569c8073-087c-48a7-b2b3-8ab25e151ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12893
04293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1289304293
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3041371004
Short name T745
Test name
Test status
Simulation time 219467313 ps
CPU time 0.89 seconds
Started Jun 10 05:24:53 PM PDT 24
Finished Jun 10 05:24:55 PM PDT 24
Peak memory 204988 kb
Host smart-aaeb6e5f-6735-45d2-983e-78dcadcdc22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30413
71004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3041371004
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.4200592117
Short name T692
Test name
Test status
Simulation time 3347525697 ps
CPU time 3.9 seconds
Started Jun 10 05:24:55 PM PDT 24
Finished Jun 10 05:24:59 PM PDT 24
Peak memory 205116 kb
Host smart-ff290d81-82de-4ad5-9a52-2e42323c0cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42005
92117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.4200592117
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3076850956
Short name T1656
Test name
Test status
Simulation time 192614335 ps
CPU time 0.83 seconds
Started Jun 10 05:24:57 PM PDT 24
Finished Jun 10 05:24:59 PM PDT 24
Peak memory 205048 kb
Host smart-db50532c-0fa2-4585-9a77-ef600520d772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30768
50956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3076850956
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.978873992
Short name T427
Test name
Test status
Simulation time 11066253950 ps
CPU time 82.12 seconds
Started Jun 10 05:24:59 PM PDT 24
Finished Jun 10 05:26:21 PM PDT 24
Peak memory 205084 kb
Host smart-51c9117b-1ad7-497c-8e96-995162b7f809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97887
3992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.978873992
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1041251552
Short name T1947
Test name
Test status
Simulation time 191217768 ps
CPU time 0.85 seconds
Started Jun 10 05:24:59 PM PDT 24
Finished Jun 10 05:25:00 PM PDT 24
Peak memory 205004 kb
Host smart-c7ff2ce1-d44a-4498-acb1-79d21dc927a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10412
51552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1041251552
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.220679572
Short name T1013
Test name
Test status
Simulation time 181815732 ps
CPU time 0.82 seconds
Started Jun 10 05:25:01 PM PDT 24
Finished Jun 10 05:25:02 PM PDT 24
Peak memory 205000 kb
Host smart-38937c3e-ee3c-48e2-b731-e46d0c3f992f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22067
9572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.220679572
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.537836601
Short name T454
Test name
Test status
Simulation time 184200384 ps
CPU time 0.88 seconds
Started Jun 10 05:25:07 PM PDT 24
Finished Jun 10 05:25:08 PM PDT 24
Peak memory 205032 kb
Host smart-f73d0fb2-ca03-43c5-aef8-2991de39f291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53783
6601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.537836601
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1337165230
Short name T1990
Test name
Test status
Simulation time 173885939 ps
CPU time 0.81 seconds
Started Jun 10 05:25:01 PM PDT 24
Finished Jun 10 05:25:03 PM PDT 24
Peak memory 204996 kb
Host smart-60a3ecab-f905-475f-b6d1-6810fc342fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13371
65230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1337165230
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1053011027
Short name T442
Test name
Test status
Simulation time 175748408 ps
CPU time 0.86 seconds
Started Jun 10 05:25:02 PM PDT 24
Finished Jun 10 05:25:03 PM PDT 24
Peak memory 205056 kb
Host smart-617290de-51ba-41d4-bf35-000d7821c19c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10530
11027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1053011027
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3538996809
Short name T2020
Test name
Test status
Simulation time 200409080 ps
CPU time 0.87 seconds
Started Jun 10 05:25:16 PM PDT 24
Finished Jun 10 05:25:17 PM PDT 24
Peak memory 205012 kb
Host smart-751c2b2a-ee94-4cd7-8e5a-6dd3fb36320e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35389
96809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3538996809
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_eop_single_bit_handling.4026740986
Short name T315
Test name
Test status
Simulation time 179887470 ps
CPU time 0.81 seconds
Started Jun 10 05:24:57 PM PDT 24
Finished Jun 10 05:24:58 PM PDT 24
Peak memory 204936 kb
Host smart-a2a0ef5d-c044-49cd-886d-d7603e8adfa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40267
40986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_eop_single_bit_handling.4026740986
Directory /workspace/8.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1343040842
Short name T1993
Test name
Test status
Simulation time 181508040 ps
CPU time 0.81 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:25:10 PM PDT 24
Peak memory 205008 kb
Host smart-bbe1ba43-2ce8-4a52-bd0b-bb5e972cea2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13430
40842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1343040842
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2232920600
Short name T1899
Test name
Test status
Simulation time 72597337 ps
CPU time 0.69 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:25:10 PM PDT 24
Peak memory 205024 kb
Host smart-a8bea1d7-bca7-44e4-a83c-ed310cad1ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22329
20600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2232920600
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.4115174216
Short name T1934
Test name
Test status
Simulation time 10858071433 ps
CPU time 24.62 seconds
Started Jun 10 05:25:01 PM PDT 24
Finished Jun 10 05:25:27 PM PDT 24
Peak memory 205196 kb
Host smart-7eef7c18-057d-4125-9651-54df0c0b5363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41151
74216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.4115174216
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2721617237
Short name T2021
Test name
Test status
Simulation time 168827716 ps
CPU time 0.78 seconds
Started Jun 10 05:25:07 PM PDT 24
Finished Jun 10 05:25:08 PM PDT 24
Peak memory 205000 kb
Host smart-e4933380-3919-4d49-94c0-6490a692c3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27216
17237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2721617237
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3714438766
Short name T472
Test name
Test status
Simulation time 237784166 ps
CPU time 0.92 seconds
Started Jun 10 05:25:07 PM PDT 24
Finished Jun 10 05:25:09 PM PDT 24
Peak memory 204996 kb
Host smart-be4c1f8d-281c-49c0-b701-d43e84acd591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37144
38766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3714438766
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1202677760
Short name T372
Test name
Test status
Simulation time 8515656787 ps
CPU time 56.47 seconds
Started Jun 10 05:25:00 PM PDT 24
Finished Jun 10 05:25:57 PM PDT 24
Peak memory 205256 kb
Host smart-17ba21fa-a7e7-442c-bbf2-0c7ac634ffef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1202677760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1202677760
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.929395108
Short name T210
Test name
Test status
Simulation time 23663750277 ps
CPU time 190.69 seconds
Started Jun 10 05:25:01 PM PDT 24
Finished Jun 10 05:28:13 PM PDT 24
Peak memory 205224 kb
Host smart-a2971b60-be16-4f29-a44e-b37626475f28
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=929395108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.929395108
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1727749538
Short name T1307
Test name
Test status
Simulation time 35936430226 ps
CPU time 213.17 seconds
Started Jun 10 05:24:57 PM PDT 24
Finished Jun 10 05:28:30 PM PDT 24
Peak memory 205080 kb
Host smart-44ed3bf0-7ad9-4030-8f30-09b272efd1aa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1727749538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1727749538
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.3259863213
Short name T544
Test name
Test status
Simulation time 218144083 ps
CPU time 0.87 seconds
Started Jun 10 05:25:10 PM PDT 24
Finished Jun 10 05:25:12 PM PDT 24
Peak memory 205008 kb
Host smart-bff47e0d-ee14-4641-8c28-e3a44e0e0c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32598
63213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.3259863213
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.796726286
Short name T1680
Test name
Test status
Simulation time 146932942 ps
CPU time 0.79 seconds
Started Jun 10 05:24:58 PM PDT 24
Finished Jun 10 05:24:59 PM PDT 24
Peak memory 205140 kb
Host smart-c5372628-987b-4e20-84b1-6c7bb4d7b45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79672
6286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.796726286
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.88803619
Short name T1657
Test name
Test status
Simulation time 148135947 ps
CPU time 0.77 seconds
Started Jun 10 05:25:08 PM PDT 24
Finished Jun 10 05:25:09 PM PDT 24
Peak memory 205004 kb
Host smart-f4d1a335-a682-4553-869c-11acc0f534eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88803
619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.88803619
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.675640243
Short name T1704
Test name
Test status
Simulation time 163127326 ps
CPU time 0.8 seconds
Started Jun 10 05:25:08 PM PDT 24
Finished Jun 10 05:25:09 PM PDT 24
Peak memory 205024 kb
Host smart-aab4b447-fe7e-48de-b2f3-ea4615c4e3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67564
0243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.675640243
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.985119785
Short name T1923
Test name
Test status
Simulation time 196000770 ps
CPU time 0.91 seconds
Started Jun 10 05:25:01 PM PDT 24
Finished Jun 10 05:25:02 PM PDT 24
Peak memory 205000 kb
Host smart-2ce30c34-5bad-4090-a656-2ffb77f80058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98511
9785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.985119785
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.861831067
Short name T1769
Test name
Test status
Simulation time 192778826 ps
CPU time 0.89 seconds
Started Jun 10 05:25:00 PM PDT 24
Finished Jun 10 05:25:01 PM PDT 24
Peak memory 205012 kb
Host smart-22b9533f-7fd4-4383-8fe6-7d1a85e9e066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86183
1067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.861831067
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2332641947
Short name T1396
Test name
Test status
Simulation time 172489790 ps
CPU time 0.78 seconds
Started Jun 10 05:24:57 PM PDT 24
Finished Jun 10 05:24:58 PM PDT 24
Peak memory 205024 kb
Host smart-c04de56a-e459-413d-ad92-2b5ef95965ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23326
41947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2332641947
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.103568940
Short name T1276
Test name
Test status
Simulation time 7327496331 ps
CPU time 68.59 seconds
Started Jun 10 05:25:11 PM PDT 24
Finished Jun 10 05:26:20 PM PDT 24
Peak memory 205244 kb
Host smart-4bf4818f-1da0-414e-a037-86d8b867ac9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10356
8940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.103568940
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.3949329276
Short name T1788
Test name
Test status
Simulation time 324137532 ps
CPU time 0.98 seconds
Started Jun 10 05:25:13 PM PDT 24
Finished Jun 10 05:25:14 PM PDT 24
Peak memory 205020 kb
Host smart-a2d38d61-3224-475c-a46f-4890c9b11ccb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3949329276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.3949329276
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.4028191426
Short name T1613
Test name
Test status
Simulation time 149659416 ps
CPU time 0.83 seconds
Started Jun 10 05:25:11 PM PDT 24
Finished Jun 10 05:25:12 PM PDT 24
Peak memory 205056 kb
Host smart-093dbca9-30b1-4991-ac7e-8449b921398e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4028191426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.4028191426
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.953348447
Short name T404
Test name
Test status
Simulation time 192443037 ps
CPU time 0.84 seconds
Started Jun 10 05:25:06 PM PDT 24
Finished Jun 10 05:25:07 PM PDT 24
Peak memory 205084 kb
Host smart-67daad9f-7f7c-469a-a661-88c75978676e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95334
8447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.953348447
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.826799753
Short name T507
Test name
Test status
Simulation time 3419301182 ps
CPU time 4.54 seconds
Started Jun 10 05:25:01 PM PDT 24
Finished Jun 10 05:25:06 PM PDT 24
Peak memory 205184 kb
Host smart-bda07492-839b-49fc-a033-d1324660c43d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=826799753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.826799753
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.1491196122
Short name T1902
Test name
Test status
Simulation time 13301269509 ps
CPU time 13.57 seconds
Started Jun 10 05:25:00 PM PDT 24
Finished Jun 10 05:25:14 PM PDT 24
Peak memory 205188 kb
Host smart-e7a15372-f411-4080-89d7-62682aba2fce
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1491196122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.1491196122
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.646630016
Short name T1507
Test name
Test status
Simulation time 23393050714 ps
CPU time 25.52 seconds
Started Jun 10 05:25:08 PM PDT 24
Finished Jun 10 05:25:34 PM PDT 24
Peak memory 205164 kb
Host smart-ec820818-cf5e-4fd3-81e0-0c3ac2f1d498
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=646630016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.646630016
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3458605235
Short name T1075
Test name
Test status
Simulation time 153275700 ps
CPU time 0.84 seconds
Started Jun 10 05:25:11 PM PDT 24
Finished Jun 10 05:25:12 PM PDT 24
Peak memory 204992 kb
Host smart-a8a18512-86a8-4fad-8d00-1b697cf2bae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34586
05235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3458605235
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.4109256720
Short name T269
Test name
Test status
Simulation time 182241702 ps
CPU time 0.81 seconds
Started Jun 10 05:25:07 PM PDT 24
Finished Jun 10 05:25:09 PM PDT 24
Peak memory 205008 kb
Host smart-d39bdf80-1693-4367-9fb0-ec6e0858db68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41092
56720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.4109256720
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.2271467581
Short name T1103
Test name
Test status
Simulation time 723511157 ps
CPU time 1.82 seconds
Started Jun 10 05:25:17 PM PDT 24
Finished Jun 10 05:25:19 PM PDT 24
Peak memory 205176 kb
Host smart-61bd2e9d-24f9-40fe-bf3b-b55c29706b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22714
67581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.2271467581
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.2766657180
Short name T17
Test name
Test status
Simulation time 133088489 ps
CPU time 0.75 seconds
Started Jun 10 05:25:06 PM PDT 24
Finished Jun 10 05:25:07 PM PDT 24
Peak memory 205068 kb
Host smart-644a9e53-0ed6-44d6-8155-3b08ce24940b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27666
57180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.2766657180
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1743646425
Short name T422
Test name
Test status
Simulation time 29106645 ps
CPU time 0.66 seconds
Started Jun 10 05:25:07 PM PDT 24
Finished Jun 10 05:25:08 PM PDT 24
Peak memory 204984 kb
Host smart-adb3d85f-b814-416e-b873-96c439055f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17436
46425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1743646425
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.2099249621
Short name T1516
Test name
Test status
Simulation time 918093693 ps
CPU time 2.1 seconds
Started Jun 10 05:25:27 PM PDT 24
Finished Jun 10 05:25:29 PM PDT 24
Peak memory 205076 kb
Host smart-ac855f0a-f92e-41b3-b017-d174896d5396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20992
49621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.2099249621
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3866357101
Short name T452
Test name
Test status
Simulation time 222601189 ps
CPU time 1.64 seconds
Started Jun 10 05:25:08 PM PDT 24
Finished Jun 10 05:25:10 PM PDT 24
Peak memory 204980 kb
Host smart-0b0861c1-1080-4569-b9e3-35582d9c3d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38663
57101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3866357101
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.174246196
Short name T405
Test name
Test status
Simulation time 205231099 ps
CPU time 0.94 seconds
Started Jun 10 05:25:10 PM PDT 24
Finished Jun 10 05:25:11 PM PDT 24
Peak memory 205008 kb
Host smart-2884c7c8-dbac-46f6-a991-8d3747e5ca2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17424
6196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.174246196
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3535993539
Short name T820
Test name
Test status
Simulation time 144415272 ps
CPU time 0.79 seconds
Started Jun 10 05:25:06 PM PDT 24
Finished Jun 10 05:25:07 PM PDT 24
Peak memory 205052 kb
Host smart-89868822-eb26-439f-99ce-ee4e04608be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35359
93539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3535993539
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3767583095
Short name T1930
Test name
Test status
Simulation time 226933041 ps
CPU time 0.93 seconds
Started Jun 10 05:25:11 PM PDT 24
Finished Jun 10 05:25:13 PM PDT 24
Peak memory 205024 kb
Host smart-d1e5363f-e099-4d4f-8ed0-d431d11998eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37675
83095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3767583095
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.129353336
Short name T52
Test name
Test status
Simulation time 249449277 ps
CPU time 0.97 seconds
Started Jun 10 05:25:13 PM PDT 24
Finished Jun 10 05:25:15 PM PDT 24
Peak memory 205052 kb
Host smart-2e0fd4cd-daab-4fee-bdbf-64331182221e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12935
3336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.129353336
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.2715313692
Short name T1985
Test name
Test status
Simulation time 3253053293 ps
CPU time 4.03 seconds
Started Jun 10 05:25:07 PM PDT 24
Finished Jun 10 05:25:11 PM PDT 24
Peak memory 205160 kb
Host smart-cc6ea679-1de4-4f70-b341-58cbd5fd5253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27153
13692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.2715313692
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3883747873
Short name T1853
Test name
Test status
Simulation time 210247999 ps
CPU time 0.92 seconds
Started Jun 10 05:25:15 PM PDT 24
Finished Jun 10 05:25:16 PM PDT 24
Peak memory 205044 kb
Host smart-ca26d90b-16c7-40c2-abc0-0b598fb2c4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38837
47873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3883747873
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3865514054
Short name T1808
Test name
Test status
Simulation time 11439689119 ps
CPU time 324.93 seconds
Started Jun 10 05:25:06 PM PDT 24
Finished Jun 10 05:30:32 PM PDT 24
Peak memory 205240 kb
Host smart-df3683a1-fe7f-4850-b91c-ecc65e41a497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38655
14054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3865514054
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3616597987
Short name T1205
Test name
Test status
Simulation time 152491345 ps
CPU time 0.83 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:25:10 PM PDT 24
Peak memory 205016 kb
Host smart-cb98b82a-cf6b-428b-bfb3-dea74f192951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36165
97987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3616597987
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1796832205
Short name T2046
Test name
Test status
Simulation time 269783184 ps
CPU time 0.94 seconds
Started Jun 10 05:25:10 PM PDT 24
Finished Jun 10 05:25:12 PM PDT 24
Peak memory 205004 kb
Host smart-c3f1a63d-2dc5-4639-b385-baa0401b120b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17968
32205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1796832205
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2309972918
Short name T884
Test name
Test status
Simulation time 179507349 ps
CPU time 0.83 seconds
Started Jun 10 05:25:08 PM PDT 24
Finished Jun 10 05:25:09 PM PDT 24
Peak memory 205020 kb
Host smart-2bb3a27d-4829-415d-994c-c072a40dfe03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23099
72918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2309972918
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2167950868
Short name T1922
Test name
Test status
Simulation time 226515920 ps
CPU time 0.85 seconds
Started Jun 10 05:25:03 PM PDT 24
Finished Jun 10 05:25:04 PM PDT 24
Peak memory 205056 kb
Host smart-f0f3ab9b-6ddd-47fa-a3fb-a0a663b8c57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21679
50868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2167950868
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3463477687
Short name T1958
Test name
Test status
Simulation time 178007636 ps
CPU time 0.86 seconds
Started Jun 10 05:25:02 PM PDT 24
Finished Jun 10 05:25:04 PM PDT 24
Peak memory 205036 kb
Host smart-c82a9ded-9fa2-45e2-9114-3e590202a58a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34634
77687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3463477687
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.875606343
Short name T1219
Test name
Test status
Simulation time 150262266 ps
CPU time 0.79 seconds
Started Jun 10 05:25:08 PM PDT 24
Finished Jun 10 05:25:09 PM PDT 24
Peak memory 205020 kb
Host smart-83ee0133-bc48-4ada-bb0a-6ae0cf26a8a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87560
6343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.875606343
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_eop_single_bit_handling.2019448048
Short name T306
Test name
Test status
Simulation time 184206991 ps
CPU time 0.91 seconds
Started Jun 10 05:25:15 PM PDT 24
Finished Jun 10 05:25:16 PM PDT 24
Peak memory 205008 kb
Host smart-efd183f9-bc96-496d-a99c-af69e1c91fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20194
48048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_eop_single_bit_handling.2019448048
Directory /workspace/9.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.748308271
Short name T2054
Test name
Test status
Simulation time 143212816 ps
CPU time 0.75 seconds
Started Jun 10 05:25:05 PM PDT 24
Finished Jun 10 05:25:06 PM PDT 24
Peak memory 205144 kb
Host smart-39bcb0eb-d00c-4da3-a5cc-3ae88b354959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74830
8271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.748308271
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.381955736
Short name T2100
Test name
Test status
Simulation time 86417557 ps
CPU time 0.71 seconds
Started Jun 10 05:25:15 PM PDT 24
Finished Jun 10 05:25:16 PM PDT 24
Peak memory 205044 kb
Host smart-a236d687-aace-4b8c-8daf-4dded98fbc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38195
5736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.381955736
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3379061600
Short name T1792
Test name
Test status
Simulation time 18016050614 ps
CPU time 42.16 seconds
Started Jun 10 05:25:10 PM PDT 24
Finished Jun 10 05:25:53 PM PDT 24
Peak memory 205252 kb
Host smart-ad233767-a6d4-4ba3-b051-5bcf09ba3605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33790
61600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3379061600
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.2216049114
Short name T1320
Test name
Test status
Simulation time 169698816 ps
CPU time 0.87 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:25:10 PM PDT 24
Peak memory 204936 kb
Host smart-1f17720b-353d-43c5-9c52-d904af5c3d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22160
49114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.2216049114
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.86090414
Short name T1326
Test name
Test status
Simulation time 245551147 ps
CPU time 0.98 seconds
Started Jun 10 05:25:07 PM PDT 24
Finished Jun 10 05:25:08 PM PDT 24
Peak memory 205052 kb
Host smart-efef450b-530d-4a9c-8a73-67b62e48eb62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86090
414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.86090414
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.1633496935
Short name T1580
Test name
Test status
Simulation time 5517135812 ps
CPU time 52.44 seconds
Started Jun 10 05:25:12 PM PDT 24
Finished Jun 10 05:26:05 PM PDT 24
Peak memory 205196 kb
Host smart-3c040e76-7699-4f28-9c5d-9decc95559b1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1633496935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.1633496935
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1422663272
Short name T1536
Test name
Test status
Simulation time 21007751625 ps
CPU time 172.23 seconds
Started Jun 10 05:25:12 PM PDT 24
Finished Jun 10 05:28:05 PM PDT 24
Peak memory 205224 kb
Host smart-231cdfd5-3aa1-4a9b-a100-31aeee9ce237
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1422663272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1422663272
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.320966256
Short name T1496
Test name
Test status
Simulation time 21879833343 ps
CPU time 177.67 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:28:07 PM PDT 24
Peak memory 205220 kb
Host smart-268dce42-6115-4c4b-a7a5-a1e0b1cd41d2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=320966256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.320966256
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.1032005946
Short name T781
Test name
Test status
Simulation time 205575571 ps
CPU time 0.93 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:25:10 PM PDT 24
Peak memory 204908 kb
Host smart-a2dee5dc-5886-4bc8-a2ea-cd17289ba161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10320
05946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.1032005946
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.223080970
Short name T1591
Test name
Test status
Simulation time 185641928 ps
CPU time 0.76 seconds
Started Jun 10 05:25:05 PM PDT 24
Finished Jun 10 05:25:06 PM PDT 24
Peak memory 205048 kb
Host smart-a968babc-da8e-4fb4-879d-ce49658fa060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22308
0970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.223080970
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.3480579005
Short name T1829
Test name
Test status
Simulation time 166338141 ps
CPU time 0.82 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:25:11 PM PDT 24
Peak memory 204972 kb
Host smart-5bcf2c39-bf30-4db1-a353-9bbc41dcbc89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34805
79005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.3480579005
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.4088333018
Short name T1334
Test name
Test status
Simulation time 168051684 ps
CPU time 0.82 seconds
Started Jun 10 05:25:06 PM PDT 24
Finished Jun 10 05:25:07 PM PDT 24
Peak memory 204928 kb
Host smart-50d781ed-18af-435f-ae32-59b1d8a51fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40883
33018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.4088333018
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1820792880
Short name T181
Test name
Test status
Simulation time 230463202 ps
CPU time 0.96 seconds
Started Jun 10 05:24:59 PM PDT 24
Finished Jun 10 05:25:01 PM PDT 24
Peak memory 204988 kb
Host smart-d77b7314-97cc-4df1-85f9-a1972012dff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18207
92880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1820792880
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2478043000
Short name T1617
Test name
Test status
Simulation time 179933915 ps
CPU time 0.87 seconds
Started Jun 10 05:25:11 PM PDT 24
Finished Jun 10 05:25:13 PM PDT 24
Peak memory 205012 kb
Host smart-3f89a1b3-8d64-4ecd-80c4-61d3e213ef23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24780
43000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2478043000
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2110812268
Short name T1422
Test name
Test status
Simulation time 204645341 ps
CPU time 0.86 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:25:10 PM PDT 24
Peak memory 205052 kb
Host smart-47aa885a-acb1-4fa2-9abc-adbc4869618a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21108
12268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2110812268
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.3002253196
Short name T978
Test name
Test status
Simulation time 5380013089 ps
CPU time 50.42 seconds
Started Jun 10 05:25:09 PM PDT 24
Finished Jun 10 05:26:00 PM PDT 24
Peak memory 205172 kb
Host smart-56094e2c-563e-4ca0-96ba-eb8c95d4f458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30022
53196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.3002253196
Directory /workspace/9.usbdev_streaming_out/latest
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