Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	41988	1		T1	5		T2	4		T3	3
all_values[1]	41988	1		T1	5		T2	4		T3	3
all_values[2]	41988	1		T1	5		T2	4		T3	3
all_values[3]	41988	1		T1	5		T2	4		T3	3
all_values[4]	41988	1		T1	5		T2	4		T3	3
all_values[5]	41988	1		T1	5		T2	4		T3	3
all_values[6]	41988	1		T1	5		T2	4		T3	3
all_values[7]	41988	1		T1	5		T2	4		T3	3
all_values[8]	41988	1		T1	5		T2	4		T3	3
all_values[9]	41988	1		T1	5		T2	4		T3	3
all_values[10]	41988	1		T1	5		T2	4		T3	3
all_values[11]	41988	1		T1	5		T2	4		T3	3
all_values[12]	41988	1		T1	5		T2	4		T3	3
all_values[13]	41988	1		T1	5		T2	4		T3	3
all_values[14]	41988	1		T1	5		T2	4		T3	3
all_values[15]	41988	1		T1	5		T2	4		T3	3
all_values[16]	41988	1		T1	5		T2	4		T3	3
all_values[17]	41988	1		T1	5		T2	4		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	747950	1		T1	85		T2	70		T3	54
auto[1]	7834	1		T1	5		T2	2		T19	4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	750319	1		T1	90		T2	72		T3	54
auto[1]	5465	1		T204	130		T207	130		T209	84

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	41011	1		T1	5		T2	4		T3	3
all_values[0]	auto[0]	auto[1]	156	1		T204	5		T207	4		T209	4
all_values[0]	auto[1]	auto[0]	681	1		T19	4		T43	3		T44	3
all_values[0]	auto[1]	auto[1]	140	1		T204	3		T207	4		T209	1
all_values[1]	auto[0]	auto[0]	39368	1		T2	2		T3	3		T16	4
all_values[1]	auto[0]	auto[1]	149	1		T204	3		T207	4		T209	3
all_values[1]	auto[1]	auto[0]	2314	1		T1	5		T2	2		T7	2
all_values[1]	auto[1]	auto[1]	157	1		T204	5		T207	4		T209	2
all_values[2]	auto[0]	auto[0]	41560	1		T1	5		T2	4		T3	3
all_values[2]	auto[0]	auto[1]	144	1		T207	2		T209	1		T208	3
all_values[2]	auto[1]	auto[0]	118	1		T35	2		T39	2		T40	2
all_values[2]	auto[1]	auto[1]	166	1		T204	3		T207	6		T209	3
all_values[3]	auto[0]	auto[0]	40166	1		T1	5		T2	4		T3	3
all_values[3]	auto[0]	auto[1]	158	1		T204	6		T207	3		T209	5
all_values[3]	auto[1]	auto[0]	1515	1		T63	1485		T205	2		T270	1
all_values[3]	auto[1]	auto[1]	149	1		T204	2		T207	5		T208	4
all_values[4]	auto[0]	auto[0]	41664	1		T1	5		T2	4		T3	3
all_values[4]	auto[0]	auto[1]	158	1		T204	2		T207	4		T209	5
all_values[4]	auto[1]	auto[0]	21	1		T64	2		T204	1		T271	1
all_values[4]	auto[1]	auto[1]	145	1		T204	5		T207	4		T208	3
all_values[5]	auto[0]	auto[0]	41674	1		T1	5		T2	4		T3	3
all_values[5]	auto[0]	auto[1]	149	1		T204	4		T207	2		T209	3
all_values[5]	auto[1]	auto[0]	20	1		T209	1		T208	2		T270	1
all_values[5]	auto[1]	auto[1]	145	1		T204	4		T207	5		T208	1
all_values[6]	auto[0]	auto[0]	41666	1		T1	5		T2	4		T3	3
all_values[6]	auto[0]	auto[1]	134	1		T204	1		T209	4		T208	2
all_values[6]	auto[1]	auto[0]	20	1		T204	2		T207	2		T205	1
all_values[6]	auto[1]	auto[1]	168	1		T204	5		T207	4		T209	1
all_values[7]	auto[0]	auto[0]	41658	1		T1	5		T2	4		T3	3
all_values[7]	auto[0]	auto[1]	171	1		T204	5		T207	5		T209	4
all_values[7]	auto[1]	auto[0]	29	1		T45	2		T46	2		T47	2
all_values[7]	auto[1]	auto[1]	130	1		T204	3		T207	2		T209	1
all_values[8]	auto[0]	auto[0]	41650	1		T1	5		T2	4		T3	3
all_values[8]	auto[0]	auto[1]	148	1		T204	2		T207	3		T208	5
all_values[8]	auto[1]	auto[0]	36	1		T51	11		T208	2		T270	1
all_values[8]	auto[1]	auto[1]	154	1		T204	6		T207	5		T209	5
all_values[9]	auto[0]	auto[0]	41641	1		T1	5		T2	4		T3	3
all_values[9]	auto[0]	auto[1]	159	1		T204	2		T207	3		T208	1
all_values[9]	auto[1]	auto[0]	58	1		T60	5		T61	5		T62	5
all_values[9]	auto[1]	auto[1]	130	1		T204	6		T207	4		T209	5
all_values[10]	auto[0]	auto[0]	41675	1		T1	5		T2	4		T3	3
all_values[10]	auto[0]	auto[1]	156	1		T204	5		T207	2		T209	4
all_values[10]	auto[1]	auto[0]	24	1		T207	3		T209	1		T206	1
all_values[10]	auto[1]	auto[1]	133	1		T204	3		T207	3		T208	5
all_values[11]	auto[0]	auto[0]	41557	1		T1	5		T2	4		T3	3
all_values[11]	auto[0]	auto[1]	138	1		T204	3		T207	2		T209	3
all_values[11]	auto[1]	auto[0]	124	1		T42	2		T69	2		T70	2
all_values[11]	auto[1]	auto[1]	169	1		T204	5		T207	4		T209	2
all_values[12]	auto[0]	auto[0]	41646	1		T1	5		T2	4		T3	3
all_values[12]	auto[0]	auto[1]	166	1		T204	3		T207	6		T208	5
all_values[12]	auto[1]	auto[0]	16	1		T206	2		T270	1		T271	2
all_values[12]	auto[1]	auto[1]	160	1		T204	5		T207	2		T209	4
all_values[13]	auto[0]	auto[0]	41659	1		T1	5		T2	4		T3	3
all_values[13]	auto[0]	auto[1]	157	1		T204	4		T207	2		T208	2
all_values[13]	auto[1]	auto[0]	29	1		T208	1		T205	1		T269	1
all_values[13]	auto[1]	auto[1]	143	1		T204	4		T207	6		T209	5
all_values[14]	auto[0]	auto[0]	41650	1		T1	5		T2	4		T3	3
all_values[14]	auto[0]	auto[1]	150	1		T204	3		T207	3		T209	4
all_values[14]	auto[1]	auto[0]	25	1		T204	1		T269	1		T272	2
all_values[14]	auto[1]	auto[1]	163	1		T204	4		T207	5		T209	1
all_values[15]	auto[0]	auto[0]	41654	1		T1	5		T2	4		T3	3
all_values[15]	auto[0]	auto[1]	160	1		T204	3		T207	5		T209	4
all_values[15]	auto[1]	auto[0]	17	1		T209	1		T208	2		T205	1
all_values[15]	auto[1]	auto[1]	157	1		T204	5		T207	2		T205	3
all_values[16]	auto[0]	auto[0]	41628	1		T1	5		T2	4		T3	3
all_values[16]	auto[0]	auto[1]	156	1		T204	3		T207	5		T208	5
all_values[16]	auto[1]	auto[0]	43	1		T66	8		T67	8		T68	8
all_values[16]	auto[1]	auto[1]	161	1		T204	3		T207	3		T209	5
all_values[17]	auto[0]	auto[0]	41669	1		T1	5		T2	4		T3	3
all_values[17]	auto[0]	auto[1]	145	1		T204	1		T207	2		T209	5
all_values[17]	auto[1]	auto[0]	33	1		T52	2		T53	2		T207	1
all_values[17]	auto[1]	auto[1]	141	1		T204	4		T207	5		T208	2