Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	41988	1		T1	5		T2	4		T3	3
all_pins[1]	41988	1		T1	5		T2	4		T3	3
all_pins[2]	41988	1		T1	5		T2	4		T3	3
all_pins[3]	41988	1		T1	5		T2	4		T3	3
all_pins[4]	41988	1		T1	5		T2	4		T3	3
all_pins[5]	41988	1		T1	5		T2	4		T3	3
all_pins[6]	41988	1		T1	5		T2	4		T3	3
all_pins[7]	41988	1		T1	5		T2	4		T3	3
all_pins[8]	41988	1		T1	5		T2	4		T3	3
all_pins[9]	41988	1		T1	5		T2	4		T3	3
all_pins[10]	41988	1		T1	5		T2	4		T3	3
all_pins[11]	41988	1		T1	5		T2	4		T3	3
all_pins[12]	41988	1		T1	5		T2	4		T3	3
all_pins[13]	41988	1		T1	5		T2	4		T3	3
all_pins[14]	41988	1		T1	5		T2	4		T3	3
all_pins[15]	41988	1		T1	5		T2	4		T3	3
all_pins[16]	41988	1		T1	5		T2	4		T3	3
all_pins[17]	41988	1		T1	5		T2	4		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	752977	1		T1	88		T2	71		T3	54
values[0x1]	2807	1		T1	2		T2	1		T19	1
transitions[0x0=>0x1]	2489	1		T1	2		T2	1		T19	1
transitions[0x1=>0x0]	2502	1		T1	2		T2	1		T19	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	41876	1		T1	5		T2	4		T3	3
all_pins[0]	values[0x1]	112	1		T19	1		T78	1		T273	1
all_pins[0]	transitions[0x0=>0x1]	92	1		T19	1		T78	1		T273	1
all_pins[0]	transitions[0x1=>0x0]	1408	1		T1	2		T2	1		T7	1
all_pins[1]	values[0x0]	40560	1		T1	3		T2	3		T3	3
all_pins[1]	values[0x1]	1428	1		T1	2		T2	1		T7	1
all_pins[1]	transitions[0x0=>0x1]	1409	1		T1	2		T2	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	120	1		T35	1		T39	1		T40	1
all_pins[2]	values[0x0]	41849	1		T1	5		T2	4		T3	3
all_pins[2]	values[0x1]	139	1		T35	1		T39	1		T40	1
all_pins[2]	transitions[0x0=>0x1]	117	1		T35	1		T39	1		T40	1
all_pins[2]	transitions[0x1=>0x0]	55	1		T63	1		T204	2		T207	3
all_pins[3]	values[0x0]	41911	1		T1	5		T2	4		T3	3
all_pins[3]	values[0x1]	77	1		T63	1		T204	2		T207	4
all_pins[3]	transitions[0x0=>0x1]	62	1		T63	1		T204	2		T207	4
all_pins[3]	transitions[0x1=>0x0]	54	1		T64	1		T204	3		T208	3
all_pins[4]	values[0x0]	41919	1		T1	5		T2	4		T3	3
all_pins[4]	values[0x1]	69	1		T64	1		T204	3		T208	3
all_pins[4]	transitions[0x0=>0x1]	46	1		T64	1		T208	2		T205	2
all_pins[4]	transitions[0x1=>0x0]	58	1		T207	3		T206	2		T270	2
all_pins[5]	values[0x0]	41907	1		T1	5		T2	4		T3	3
all_pins[5]	values[0x1]	81	1		T204	3		T207	3		T208	1
all_pins[5]	transitions[0x0=>0x1]	58	1		T204	3		T207	3		T205	1
all_pins[5]	transitions[0x1=>0x0]	53	1		T207	1		T209	1		T208	1
all_pins[6]	values[0x0]	41912	1		T1	5		T2	4		T3	3
all_pins[6]	values[0x1]	76	1		T207	1		T209	1		T208	2
all_pins[6]	transitions[0x0=>0x1]	60	1		T209	1		T208	2		T205	2
all_pins[6]	transitions[0x1=>0x0]	43	1		T45	1		T46	1		T47	1
all_pins[7]	values[0x0]	41929	1		T1	5		T2	4		T3	3
all_pins[7]	values[0x1]	59	1		T45	1		T46	1		T47	1
all_pins[7]	transitions[0x0=>0x1]	45	1		T45	1		T46	1		T47	1
all_pins[7]	transitions[0x1=>0x0]	53	1		T51	1		T204	1		T207	2
all_pins[8]	values[0x0]	41921	1		T1	5		T2	4		T3	3
all_pins[8]	values[0x1]	67	1		T51	1		T204	3		T207	2
all_pins[8]	transitions[0x0=>0x1]	55	1		T51	1		T204	3		T207	1
all_pins[8]	transitions[0x1=>0x0]	60	1		T60	2		T61	2		T62	2
all_pins[9]	values[0x0]	41916	1		T1	5		T2	4		T3	3
all_pins[9]	values[0x1]	72	1		T60	2		T61	2		T62	2
all_pins[9]	transitions[0x0=>0x1]	46	1		T60	2		T61	2		T62	2
all_pins[9]	transitions[0x1=>0x0]	39	1		T208	1		T206	1		T270	2
all_pins[10]	values[0x0]	41923	1		T1	5		T2	4		T3	3
all_pins[10]	values[0x1]	65	1		T208	4		T205	1		T206	1
all_pins[10]	transitions[0x0=>0x1]	52	1		T208	3		T206	1		T270	1
all_pins[10]	transitions[0x1=>0x0]	118	1		T42	1		T69	1		T70	1
all_pins[11]	values[0x0]	41857	1		T1	5		T2	4		T3	3
all_pins[11]	values[0x1]	131	1		T42	1		T69	1		T70	1
all_pins[11]	transitions[0x0=>0x1]	113	1		T42	1		T69	1		T70	1
all_pins[11]	transitions[0x1=>0x0]	66	1		T204	3		T207	1		T206	1
all_pins[12]	values[0x0]	41904	1		T1	5		T2	4		T3	3
all_pins[12]	values[0x1]	84	1		T204	3		T207	1		T205	1
all_pins[12]	transitions[0x0=>0x1]	70	1		T204	3		T207	1		T205	1
all_pins[12]	transitions[0x1=>0x0]	45	1		T204	2		T207	1		T209	1
all_pins[13]	values[0x0]	41929	1		T1	5		T2	4		T3	3
all_pins[13]	values[0x1]	59	1		T204	2		T207	1		T209	1
all_pins[13]	transitions[0x0=>0x1]	46	1		T204	2		T208	3		T205	1
all_pins[13]	transitions[0x1=>0x0]	65	1		T207	3		T208	2		T205	1
all_pins[14]	values[0x0]	41910	1		T1	5		T2	4		T3	3
all_pins[14]	values[0x1]	78	1		T207	4		T209	1		T208	2
all_pins[14]	transitions[0x0=>0x1]	52	1		T207	4		T209	1		T208	2
all_pins[14]	transitions[0x1=>0x0]	50	1		T204	3		T267	4		T268	1
all_pins[15]	values[0x0]	41912	1		T1	5		T2	4		T3	3
all_pins[15]	values[0x1]	76	1		T204	3		T271	1		T267	4
all_pins[15]	transitions[0x0=>0x1]	62	1		T204	3		T271	1		T267	1
all_pins[15]	transitions[0x1=>0x0]	61	1		T66	4		T67	4		T68	4
all_pins[16]	values[0x0]	41913	1		T1	5		T2	4		T3	3
all_pins[16]	values[0x1]	75	1		T66	4		T67	4		T68	4
all_pins[16]	transitions[0x0=>0x1]	62	1		T66	4		T67	4		T68	4
all_pins[16]	transitions[0x1=>0x0]	46	1		T52	1		T53	1		T204	2
all_pins[17]	values[0x0]	41929	1		T1	5		T2	4		T3	3
all_pins[17]	values[0x1]	59	1		T52	1		T53	1		T204	2
all_pins[17]	transitions[0x0=>0x1]	42	1		T52	1		T53	1		T204	1
all_pins[17]	transitions[0x1=>0x0]	108	1		T19	1		T78	1		T273	1