Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	302	1		T204	7		T207	7		T209	4
all_values[1]	302	1		T204	7		T207	7		T209	4
all_values[2]	302	1		T204	7		T207	7		T209	4
all_values[3]	302	1		T204	7		T207	7		T209	4
all_values[4]	302	1		T204	7		T207	7		T209	4
all_values[5]	302	1		T204	7		T207	7		T209	4
all_values[6]	302	1		T204	7		T207	7		T209	4
all_values[7]	302	1		T204	7		T207	7		T209	4
all_values[8]	302	1		T204	7		T207	7		T209	4
all_values[9]	302	1		T204	7		T207	7		T209	4
all_values[10]	302	1		T204	7		T207	7		T209	4
all_values[11]	302	1		T204	7		T207	7		T209	4
all_values[12]	302	1		T204	7		T207	7		T209	4
all_values[13]	302	1		T204	7		T207	7		T209	4
all_values[14]	302	1		T204	7		T207	7		T209	4
all_values[15]	302	1		T204	7		T207	7		T209	4
all_values[16]	302	1		T204	7		T207	7		T209	4
all_values[17]	302	1		T204	7		T207	7		T209	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2983	1		T204	72		T207	63		T209	52
auto[1]	2453	1		T204	54		T207	63		T209	20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	838	1		T204	14		T207	14		T209	6
auto[1]	4598	1		T204	112		T207	112		T209	66

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3157	1		T204	64		T207	72		T209	41
auto[1]	2279	1		T204	62		T207	54		T209	31

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	30	1		T208	1		T205	1		T267	3
all_values[0]	auto[0]	auto[0]	auto[1]	71	1		T204	2		T207	1		T209	3
all_values[0]	auto[0]	auto[1]	auto[0]	24	1		T208	1		T270	1		T274	1
all_values[0]	auto[0]	auto[1]	auto[1]	60	1		T207	3		T208	2		T206	1
all_values[0]	auto[1]	auto[0]	auto[1]	63	1		T204	3		T207	1		T209	1
all_values[0]	auto[1]	auto[1]	auto[1]	54	1		T204	2		T207	2		T206	2
all_values[1]	auto[0]	auto[0]	auto[0]	24	1		T208	3		T270	2		T274	1
all_values[1]	auto[0]	auto[0]	auto[1]	62	1		T204	2		T207	2		T209	1
all_values[1]	auto[0]	auto[1]	auto[0]	19	1		T208	1		T269	5		T275	1
all_values[1]	auto[0]	auto[1]	auto[1]	69	1		T204	1		T207	1		T209	1
all_values[1]	auto[1]	auto[0]	auto[1]	83	1		T204	3		T209	2		T206	3
all_values[1]	auto[1]	auto[1]	auto[1]	45	1		T204	1		T207	4		T208	1
all_values[2]	auto[0]	auto[0]	auto[0]	22	1		T204	3		T209	1		T206	1
all_values[2]	auto[0]	auto[0]	auto[1]	63	1		T270	3		T271	4		T267	2
all_values[2]	auto[0]	auto[1]	auto[0]	19	1		T204	2		T206	3		T268	2
all_values[2]	auto[0]	auto[1]	auto[1]	55	1		T204	1		T207	1		T209	1
all_values[2]	auto[1]	auto[0]	auto[1]	71	1		T207	3		T209	1		T208	2
all_values[2]	auto[1]	auto[1]	auto[1]	72	1		T204	1		T207	3		T209	1
all_values[3]	auto[0]	auto[0]	auto[0]	19	1		T268	1		T269	3		T276	1
all_values[3]	auto[0]	auto[0]	auto[1]	59	1		T204	1		T207	1		T209	1
all_values[3]	auto[0]	auto[1]	auto[0]	24	1		T205	2		T270	1		T275	1
all_values[3]	auto[0]	auto[1]	auto[1]	61	1		T207	2		T208	2		T206	1
all_values[3]	auto[1]	auto[0]	auto[1]	77	1		T204	3		T207	2		T209	3
all_values[3]	auto[1]	auto[1]	auto[1]	62	1		T204	3		T207	2		T205	1
all_values[4]	auto[0]	auto[0]	auto[0]	35	1		T204	1		T267	1		T268	1
all_values[4]	auto[0]	auto[0]	auto[1]	75	1		T204	1		T207	4		T209	2
all_values[4]	auto[0]	auto[1]	auto[0]	12	1		T271	1		T277	1		T278	2
all_values[4]	auto[0]	auto[1]	auto[1]	53	1		T204	1		T207	2		T205	2
all_values[4]	auto[1]	auto[0]	auto[1]	74	1		T204	2		T207	1		T209	2
all_values[4]	auto[1]	auto[1]	auto[1]	53	1		T204	2		T208	3		T205	1
all_values[5]	auto[0]	auto[0]	auto[0]	43	1		T207	1		T209	2		T208	1
all_values[5]	auto[0]	auto[0]	auto[1]	62	1		T204	1		T207	2		T209	1
all_values[5]	auto[0]	auto[1]	auto[0]	14	1		T208	1		T270	1		T276	2
all_values[5]	auto[0]	auto[1]	auto[1]	54	1		T204	2		T207	1		T205	1
all_values[5]	auto[1]	auto[0]	auto[1]	76	1		T204	4		T207	1		T209	1
all_values[5]	auto[1]	auto[1]	auto[1]	53	1		T207	2		T205	2		T270	2
all_values[6]	auto[0]	auto[0]	auto[0]	35	1		T204	1		T207	2		T208	1
all_values[6]	auto[0]	auto[0]	auto[1]	65	1		T209	2		T206	4		T270	1
all_values[6]	auto[0]	auto[1]	auto[0]	15	1		T204	1		T207	2		T205	1
all_values[6]	auto[0]	auto[1]	auto[1]	73	1		T204	2		T207	2		T208	3
all_values[6]	auto[1]	auto[0]	auto[1]	63	1		T204	1		T209	2		T208	3
all_values[6]	auto[1]	auto[1]	auto[1]	51	1		T204	2		T207	1		T205	2
all_values[7]	auto[0]	auto[0]	auto[0]	30	1		T207	1		T205	1		T267	1
all_values[7]	auto[0]	auto[0]	auto[1]	69	1		T204	1		T207	1		T209	2
all_values[7]	auto[0]	auto[1]	auto[0]	17	1		T205	3		T206	1		T269	1
all_values[7]	auto[0]	auto[1]	auto[1]	62	1		T204	1		T209	1		T208	2
all_values[7]	auto[1]	auto[0]	auto[1]	69	1		T204	3		T207	2		T209	1
all_values[7]	auto[1]	auto[1]	auto[1]	55	1		T204	2		T207	3		T208	1
all_values[8]	auto[0]	auto[0]	auto[0]	31	1		T208	2		T206	2		T268	1
all_values[8]	auto[0]	auto[0]	auto[1]	70	1		T204	1		T207	3		T208	2
all_values[8]	auto[0]	auto[1]	auto[0]	18	1		T208	1		T270	1		T271	1
all_values[8]	auto[0]	auto[1]	auto[1]	64	1		T204	2		T207	1		T209	2
all_values[8]	auto[1]	auto[0]	auto[1]	63	1		T204	1		T207	1		T209	1
all_values[8]	auto[1]	auto[1]	auto[1]	56	1		T204	3		T207	2		T209	1
all_values[9]	auto[0]	auto[0]	auto[0]	36	1		T207	1		T206	3		T271	1
all_values[9]	auto[0]	auto[0]	auto[1]	64	1		T207	2		T206	2		T270	1
all_values[9]	auto[0]	auto[1]	auto[0]	25	1		T274	1		T269	1		T275	1
all_values[9]	auto[0]	auto[1]	auto[1]	58	1		T204	3		T207	2		T209	3
all_values[9]	auto[1]	auto[0]	auto[1]	70	1		T204	2		T207	2		T209	1
all_values[9]	auto[1]	auto[1]	auto[1]	49	1		T204	2		T208	3		T205	2
all_values[10]	auto[0]	auto[0]	auto[0]	41	1		T209	1		T206	4		T271	1
all_values[10]	auto[0]	auto[0]	auto[1]	64	1		T204	3		T207	1		T209	1
all_values[10]	auto[0]	auto[1]	auto[0]	18	1		T207	3		T267	1		T277	1
all_values[10]	auto[0]	auto[1]	auto[1]	54	1		T204	1		T207	1		T208	1
all_values[10]	auto[1]	auto[0]	auto[1]	76	1		T204	2		T207	2		T209	2
all_values[10]	auto[1]	auto[1]	auto[1]	49	1		T204	1		T208	2		T205	1
all_values[11]	auto[0]	auto[0]	auto[0]	29	1		T207	2		T208	2		T267	1
all_values[11]	auto[0]	auto[0]	auto[1]	61	1		T204	1		T207	1		T209	1
all_values[11]	auto[0]	auto[1]	auto[0]	15	1		T277	3		T279	1		T280	1
all_values[11]	auto[0]	auto[1]	auto[1]	67	1		T204	3		T207	1		T209	1
all_values[11]	auto[1]	auto[0]	auto[1]	74	1		T204	2		T207	2		T209	2
all_values[11]	auto[1]	auto[1]	auto[1]	56	1		T204	1		T207	1		T205	3
all_values[12]	auto[0]	auto[0]	auto[0]	12	1		T209	1		T281	2		T282	1
all_values[12]	auto[0]	auto[0]	auto[1]	72	1		T204	1		T207	4		T208	2
all_values[12]	auto[0]	auto[1]	auto[0]	14	1		T206	2		T270	1		T271	3
all_values[12]	auto[0]	auto[1]	auto[1]	72	1		T204	2		T209	2		T208	3
all_values[12]	auto[1]	auto[0]	auto[1]	64	1		T204	4		T207	1		T208	1
all_values[12]	auto[1]	auto[1]	auto[1]	68	1		T207	2		T209	1		T208	1
all_values[13]	auto[0]	auto[0]	auto[0]	25	1		T208	1		T206	3		T270	1
all_values[13]	auto[0]	auto[0]	auto[1]	63	1		T204	2		T206	1		T270	1
all_values[13]	auto[0]	auto[1]	auto[0]	25	1		T205	1		T269	1		T275	1
all_values[13]	auto[0]	auto[1]	auto[1]	66	1		T204	2		T207	3		T209	2
all_values[13]	auto[1]	auto[0]	auto[1]	75	1		T204	1		T207	3		T209	1
all_values[13]	auto[1]	auto[1]	auto[1]	48	1		T204	2		T207	1		T209	1
all_values[14]	auto[0]	auto[0]	auto[0]	22	1		T204	1		T269	1		T283	1
all_values[14]	auto[0]	auto[0]	auto[1]	64	1		T204	2		T207	2		T209	2
all_values[14]	auto[0]	auto[1]	auto[0]	16	1		T269	2		T272	1		T284	2
all_values[14]	auto[0]	auto[1]	auto[1]	68	1		T204	2		T207	1		T208	3
all_values[14]	auto[1]	auto[0]	auto[1]	71	1		T204	1		T207	2		T209	2
all_values[14]	auto[1]	auto[1]	auto[1]	61	1		T204	1		T207	2		T208	2
all_values[15]	auto[0]	auto[0]	auto[0]	23	1		T207	1		T209	1		T208	1
all_values[15]	auto[0]	auto[0]	auto[1]	62	1		T204	2		T207	2		T209	2
all_values[15]	auto[0]	auto[1]	auto[0]	11	1		T208	1		T205	1		T269	1
all_values[15]	auto[0]	auto[1]	auto[1]	76	1		T204	1		T207	3		T205	1
all_values[15]	auto[1]	auto[0]	auto[1]	67	1		T204	3		T207	1		T209	1
all_values[15]	auto[1]	auto[1]	auto[1]	63	1		T204	1		T205	1		T206	2
all_values[16]	auto[0]	auto[0]	auto[0]	24	1		T204	2		T208	1		T267	1
all_values[16]	auto[0]	auto[0]	auto[1]	67	1		T204	3		T207	2		T208	1
all_values[16]	auto[0]	auto[1]	auto[0]	10	1		T271	1		T268	1		T284	1
all_values[16]	auto[0]	auto[1]	auto[1]	70	1		T204	1		T207	3		T209	1
all_values[16]	auto[1]	auto[0]	auto[1]	82	1		T204	1		T207	1		T209	1
all_values[16]	auto[1]	auto[1]	auto[1]	49	1		T207	1		T209	2		T205	1
all_values[17]	auto[0]	auto[0]	auto[0]	36	1		T204	3		T208	1		T206	1
all_values[17]	auto[0]	auto[0]	auto[1]	66	1		T204	1		T207	1		T209	3
all_values[17]	auto[0]	auto[1]	auto[0]	25	1		T207	1		T208	1		T268	3
all_values[17]	auto[0]	auto[1]	auto[1]	58	1		T204	1		T207	2		T208	1
all_values[17]	auto[1]	auto[0]	auto[1]	69	1		T204	1		T207	1		T209	1
all_values[17]	auto[1]	auto[1]	auto[1]	48	1		T204	1		T207	2		T208	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal