Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.81 97.86 93.79 97.44 76.56 96.29 98.17 96.58


Total test records in report: 2607
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T236 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2608968351 Jun 21 04:42:23 PM PDT 24 Jun 21 04:42:27 PM PDT 24 166424705 ps
T257 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.996144580 Jun 21 04:43:01 PM PDT 24 Jun 21 04:43:04 PM PDT 24 61358520 ps
T2519 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1362240335 Jun 21 04:42:44 PM PDT 24 Jun 21 04:42:47 PM PDT 24 34060469 ps
T278 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.908066989 Jun 21 04:43:05 PM PDT 24 Jun 21 04:43:08 PM PDT 24 39286753 ps
T2520 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1218485329 Jun 21 04:42:40 PM PDT 24 Jun 21 04:42:42 PM PDT 24 40108352 ps
T2521 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.858398314 Jun 21 04:43:03 PM PDT 24 Jun 21 04:43:06 PM PDT 24 262290302 ps
T289 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2189733798 Jun 21 04:43:02 PM PDT 24 Jun 21 04:43:07 PM PDT 24 594286855 ps
T2522 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3340743273 Jun 21 04:42:49 PM PDT 24 Jun 21 04:42:51 PM PDT 24 40023115 ps
T255 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1610898153 Jun 21 04:43:02 PM PDT 24 Jun 21 04:43:05 PM PDT 24 86484700 ps
T2523 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1882851388 Jun 21 04:42:32 PM PDT 24 Jun 21 04:42:34 PM PDT 24 132007935 ps
T2524 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2568431922 Jun 21 04:42:36 PM PDT 24 Jun 21 04:42:39 PM PDT 24 129300154 ps
T239 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4101222104 Jun 21 04:42:33 PM PDT 24 Jun 21 04:42:38 PM PDT 24 247860172 ps
T256 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.86348126 Jun 21 04:42:44 PM PDT 24 Jun 21 04:42:48 PM PDT 24 70631708 ps
T238 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2522528709 Jun 21 04:42:42 PM PDT 24 Jun 21 04:42:45 PM PDT 24 64951853 ps
T2525 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3883201668 Jun 21 04:42:34 PM PDT 24 Jun 21 04:42:41 PM PDT 24 68076602 ps
T2526 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3324035073 Jun 21 04:42:30 PM PDT 24 Jun 21 04:42:33 PM PDT 24 110001112 ps
T2527 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3926487992 Jun 21 04:43:04 PM PDT 24 Jun 21 04:43:07 PM PDT 24 103764529 ps
T2528 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1321649997 Jun 21 04:43:05 PM PDT 24 Jun 21 04:43:09 PM PDT 24 101686694 ps
T287 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3109754982 Jun 21 04:42:25 PM PDT 24 Jun 21 04:42:32 PM PDT 24 903223098 ps
T2529 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3643263264 Jun 21 04:42:24 PM PDT 24 Jun 21 04:42:28 PM PDT 24 63370091 ps
T2530 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2931011448 Jun 21 04:42:24 PM PDT 24 Jun 21 04:42:27 PM PDT 24 153879608 ps
T2531 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4263534926 Jun 21 04:42:31 PM PDT 24 Jun 21 04:42:36 PM PDT 24 177018855 ps
T282 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.626186713 Jun 21 04:42:30 PM PDT 24 Jun 21 04:42:33 PM PDT 24 43275903 ps
T2532 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3661044250 Jun 21 04:43:02 PM PDT 24 Jun 21 04:43:04 PM PDT 24 45964370 ps
T2533 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1964291134 Jun 21 04:42:38 PM PDT 24 Jun 21 04:42:46 PM PDT 24 904542672 ps
T2534 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2129917574 Jun 21 04:43:00 PM PDT 24 Jun 21 04:43:03 PM PDT 24 126206347 ps
T2535 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1633572522 Jun 21 04:42:55 PM PDT 24 Jun 21 04:43:01 PM PDT 24 38858364 ps
T2536 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2536721033 Jun 21 04:42:58 PM PDT 24 Jun 21 04:43:00 PM PDT 24 98538535 ps
T288 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1050416048 Jun 21 04:42:45 PM PDT 24 Jun 21 04:42:52 PM PDT 24 864790436 ps
T2537 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2787831583 Jun 21 04:42:18 PM PDT 24 Jun 21 04:42:20 PM PDT 24 223851246 ps
T234 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.869242206 Jun 21 04:42:49 PM PDT 24 Jun 21 04:42:54 PM PDT 24 428198158 ps
T2538 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1182195957 Jun 21 04:43:00 PM PDT 24 Jun 21 04:43:05 PM PDT 24 407206887 ps
T2539 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1942902021 Jun 21 04:42:42 PM PDT 24 Jun 21 04:42:44 PM PDT 24 60717908 ps
T235 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.595174279 Jun 21 04:42:23 PM PDT 24 Jun 21 04:42:30 PM PDT 24 930191720 ps
T2540 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.165508535 Jun 21 04:42:42 PM PDT 24 Jun 21 04:42:52 PM PDT 24 2487555117 ps
T2541 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4013928382 Jun 21 04:42:58 PM PDT 24 Jun 21 04:43:00 PM PDT 24 126260495 ps
T241 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.663999523 Jun 21 04:42:51 PM PDT 24 Jun 21 04:42:58 PM PDT 24 951126189 ps
T2542 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3130481495 Jun 21 04:42:22 PM PDT 24 Jun 21 04:42:25 PM PDT 24 98045402 ps
T279 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2469544725 Jun 21 04:42:49 PM PDT 24 Jun 21 04:42:53 PM PDT 24 51069750 ps
T291 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.203495779 Jun 21 04:42:51 PM PDT 24 Jun 21 04:42:58 PM PDT 24 789745796 ps
T2543 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1765409779 Jun 21 04:42:44 PM PDT 24 Jun 21 04:42:48 PM PDT 24 139811011 ps
T2544 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2070177555 Jun 21 04:42:23 PM PDT 24 Jun 21 04:42:26 PM PDT 24 281039918 ps
T2545 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1355151204 Jun 21 04:42:30 PM PDT 24 Jun 21 04:42:35 PM PDT 24 167615829 ps
T2546 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3618662370 Jun 21 04:42:32 PM PDT 24 Jun 21 04:42:35 PM PDT 24 66975712 ps
T2547 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3461727007 Jun 21 04:42:47 PM PDT 24 Jun 21 04:42:50 PM PDT 24 91592636 ps
T2548 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1368947192 Jun 21 04:42:59 PM PDT 24 Jun 21 04:43:05 PM PDT 24 264801981 ps
T2549 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.390705504 Jun 21 04:42:58 PM PDT 24 Jun 21 04:43:01 PM PDT 24 47889731 ps
T2550 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2999696968 Jun 21 04:42:23 PM PDT 24 Jun 21 04:42:25 PM PDT 24 131337388 ps
T280 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.638906597 Jun 21 04:42:46 PM PDT 24 Jun 21 04:42:49 PM PDT 24 48795521 ps
T2551 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2261306402 Jun 21 04:43:00 PM PDT 24 Jun 21 04:43:04 PM PDT 24 216082398 ps
T2552 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1844654212 Jun 21 04:42:46 PM PDT 24 Jun 21 04:42:50 PM PDT 24 177021630 ps
T2553 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2265551041 Jun 21 04:42:50 PM PDT 24 Jun 21 04:42:54 PM PDT 24 203403778 ps
T2554 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.4076005777 Jun 21 04:43:09 PM PDT 24 Jun 21 04:43:21 PM PDT 24 1793893224 ps
T2555 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1327611919 Jun 21 04:42:47 PM PDT 24 Jun 21 04:42:51 PM PDT 24 157459660 ps
T2556 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1100177890 Jun 21 04:42:48 PM PDT 24 Jun 21 04:42:52 PM PDT 24 194303083 ps
T2557 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3536876152 Jun 21 04:42:24 PM PDT 24 Jun 21 04:42:28 PM PDT 24 98990246 ps
T2558 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1132158206 Jun 21 04:42:23 PM PDT 24 Jun 21 04:42:28 PM PDT 24 157770825 ps
T2559 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2422969100 Jun 21 04:42:31 PM PDT 24 Jun 21 04:42:38 PM PDT 24 73391141 ps
T2560 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1271193710 Jun 21 04:42:55 PM PDT 24 Jun 21 04:42:58 PM PDT 24 102977620 ps
T2561 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1385691955 Jun 21 04:42:50 PM PDT 24 Jun 21 04:42:55 PM PDT 24 513118281 ps
T2562 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.91996394 Jun 21 04:42:29 PM PDT 24 Jun 21 04:42:32 PM PDT 24 159881984 ps
T2563 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.695652569 Jun 21 04:42:30 PM PDT 24 Jun 21 04:42:33 PM PDT 24 171781542 ps
T2564 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2502587687 Jun 21 04:42:30 PM PDT 24 Jun 21 04:42:37 PM PDT 24 99283269 ps
T2565 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3516171499 Jun 21 04:43:13 PM PDT 24 Jun 21 04:43:18 PM PDT 24 112695703 ps
T2566 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3494660112 Jun 21 04:42:25 PM PDT 24 Jun 21 04:42:28 PM PDT 24 78385657 ps
T2567 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1474129703 Jun 21 04:42:46 PM PDT 24 Jun 21 04:42:50 PM PDT 24 119076093 ps
T292 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3390957891 Jun 21 04:42:59 PM PDT 24 Jun 21 04:43:05 PM PDT 24 587855390 ps
T2568 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1715196316 Jun 21 04:42:41 PM PDT 24 Jun 21 04:42:42 PM PDT 24 67548340 ps
T2569 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2402656056 Jun 21 04:42:21 PM PDT 24 Jun 21 04:42:27 PM PDT 24 381281476 ps
T2570 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3760889195 Jun 21 04:42:46 PM PDT 24 Jun 21 04:42:54 PM PDT 24 1121290452 ps
T2571 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3780227939 Jun 21 04:42:50 PM PDT 24 Jun 21 04:42:53 PM PDT 24 35243400 ps
T2572 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.90586821 Jun 21 04:43:10 PM PDT 24 Jun 21 04:43:16 PM PDT 24 188366660 ps
T2573 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1589222998 Jun 21 04:42:56 PM PDT 24 Jun 21 04:43:00 PM PDT 24 762004798 ps
T2574 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3700287355 Jun 21 04:42:21 PM PDT 24 Jun 21 04:42:24 PM PDT 24 143773619 ps
T2575 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2015741673 Jun 21 04:43:14 PM PDT 24 Jun 21 04:43:19 PM PDT 24 36693786 ps
T2576 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.11840042 Jun 21 04:43:12 PM PDT 24 Jun 21 04:43:17 PM PDT 24 45289925 ps
T2577 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1873582952 Jun 21 04:43:23 PM PDT 24 Jun 21 04:43:29 PM PDT 24 59838876 ps
T2578 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.783400367 Jun 21 04:42:46 PM PDT 24 Jun 21 04:42:51 PM PDT 24 283143658 ps
T2579 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1074994668 Jun 21 04:43:09 PM PDT 24 Jun 21 04:43:14 PM PDT 24 77266514 ps
T2580 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1998413131 Jun 21 04:42:57 PM PDT 24 Jun 21 04:43:03 PM PDT 24 733025005 ps
T2581 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.854041806 Jun 21 04:42:42 PM PDT 24 Jun 21 04:42:45 PM PDT 24 244908967 ps
T2582 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1980517283 Jun 21 04:42:31 PM PDT 24 Jun 21 04:42:33 PM PDT 24 32794927 ps
T2583 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3625953603 Jun 21 04:42:35 PM PDT 24 Jun 21 04:42:38 PM PDT 24 43077526 ps
T2584 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2541493889 Jun 21 04:42:56 PM PDT 24 Jun 21 04:42:59 PM PDT 24 55348033 ps
T2585 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.460128151 Jun 21 04:42:43 PM PDT 24 Jun 21 04:42:45 PM PDT 24 69109814 ps
T2586 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3059669352 Jun 21 04:43:06 PM PDT 24 Jun 21 04:43:10 PM PDT 24 45349216 ps
T2587 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2312742900 Jun 21 04:42:34 PM PDT 24 Jun 21 04:42:37 PM PDT 24 99239061 ps
T2588 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.750887337 Jun 21 04:43:26 PM PDT 24 Jun 21 04:43:33 PM PDT 24 242682026 ps
T2589 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.980261490 Jun 21 04:42:23 PM PDT 24 Jun 21 04:42:28 PM PDT 24 416873645 ps
T2590 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.346035770 Jun 21 04:42:24 PM PDT 24 Jun 21 04:42:29 PM PDT 24 290231459 ps
T2591 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3773699545 Jun 21 04:42:36 PM PDT 24 Jun 21 04:42:38 PM PDT 24 64067989 ps
T2592 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3327305535 Jun 21 04:42:54 PM PDT 24 Jun 21 04:42:56 PM PDT 24 61992104 ps
T2593 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.985445087 Jun 21 04:42:45 PM PDT 24 Jun 21 04:42:54 PM PDT 24 101270723 ps
T2594 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.133655815 Jun 21 04:42:48 PM PDT 24 Jun 21 04:42:51 PM PDT 24 58848191 ps
T2595 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3138062702 Jun 21 04:42:38 PM PDT 24 Jun 21 04:42:43 PM PDT 24 134278263 ps
T2596 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3946280244 Jun 21 04:42:29 PM PDT 24 Jun 21 04:42:31 PM PDT 24 49656386 ps
T2597 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4007492961 Jun 21 04:42:34 PM PDT 24 Jun 21 04:42:38 PM PDT 24 103391649 ps
T2598 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2221775720 Jun 21 04:42:43 PM PDT 24 Jun 21 04:42:45 PM PDT 24 37571720 ps
T2599 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1003602262 Jun 21 04:42:31 PM PDT 24 Jun 21 04:42:33 PM PDT 24 55583379 ps
T2600 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2493622386 Jun 21 04:43:10 PM PDT 24 Jun 21 04:43:14 PM PDT 24 47551351 ps
T2601 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.479782847 Jun 21 04:42:24 PM PDT 24 Jun 21 04:42:28 PM PDT 24 95079754 ps
T2602 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3841818871 Jun 21 04:43:05 PM PDT 24 Jun 21 04:43:08 PM PDT 24 55074824 ps
T2603 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.535668584 Jun 21 04:42:30 PM PDT 24 Jun 21 04:42:33 PM PDT 24 119922281 ps
T2604 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.489003957 Jun 21 04:42:36 PM PDT 24 Jun 21 04:42:38 PM PDT 24 72609833 ps
T2605 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.415500519 Jun 21 04:42:35 PM PDT 24 Jun 21 04:42:39 PM PDT 24 169698052 ps
T2606 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.199922634 Jun 21 04:42:37 PM PDT 24 Jun 21 04:42:40 PM PDT 24 81491459 ps
T2607 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.540151068 Jun 21 04:42:45 PM PDT 24 Jun 21 04:42:48 PM PDT 24 72272935 ps

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3706895536
Short name T2
Test name
Test status
Simulation time 13368285232 ps
CPU time 14.97 seconds
Started Jun 21 04:59:59 PM PDT 24
Finished Jun 21 05:00:16 PM PDT 24
Peak memory 206092 kb
Host smart-feda5d08-9941-4ea0-8012-786c8aef5b08
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3706895536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3706895536
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_device_address.2035917446
Short name T73
Test name
Test status
Simulation time 16581225076 ps
CPU time 32.1 seconds
Started Jun 21 04:54:05 PM PDT 24
Finished Jun 21 04:54:38 PM PDT 24
Peak memory 206264 kb
Host smart-bdce8e34-50af-4128-9adc-ac8bfa3f98e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20359
17446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.2035917446
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.643272138
Short name T208
Test name
Test status
Simulation time 42741303 ps
CPU time 0.69 seconds
Started Jun 21 04:42:36 PM PDT 24
Finished Jun 21 04:42:38 PM PDT 24
Peak memory 204948 kb
Host smart-83a2c657-4c0d-4f19-a565-c1764577a509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=643272138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.643272138
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1964300691
Short name T203
Test name
Test status
Simulation time 854619400 ps
CPU time 5.01 seconds
Started Jun 21 04:42:41 PM PDT 24
Finished Jun 21 04:42:46 PM PDT 24
Peak memory 206096 kb
Host smart-9b1d89d2-9611-4592-ba20-bd458813a128
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1964300691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1964300691
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.759315787
Short name T27
Test name
Test status
Simulation time 521168549 ps
CPU time 1.6 seconds
Started Jun 21 04:58:37 PM PDT 24
Finished Jun 21 04:58:40 PM PDT 24
Peak memory 206216 kb
Host smart-f28a1524-7e11-4f91-b2c2-2083206b8126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75931
5787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.759315787
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3428193833
Short name T274
Test name
Test status
Simulation time 59564529 ps
CPU time 0.71 seconds
Started Jun 21 04:42:56 PM PDT 24
Finished Jun 21 04:42:57 PM PDT 24
Peak memory 205776 kb
Host smart-0d19eddd-61fe-46e4-a0ef-94bc9597f1ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3428193833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3428193833
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.3180167390
Short name T99
Test name
Test status
Simulation time 181342231 ps
CPU time 0.85 seconds
Started Jun 21 04:56:46 PM PDT 24
Finished Jun 21 04:56:49 PM PDT 24
Peak memory 206024 kb
Host smart-311217b4-49dd-4cde-982f-ec6a9186c779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31801
67390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.3180167390
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1851524634
Short name T79
Test name
Test status
Simulation time 220230347 ps
CPU time 0.87 seconds
Started Jun 21 05:00:09 PM PDT 24
Finished Jun 21 05:00:17 PM PDT 24
Peak memory 205972 kb
Host smart-d51bcb1f-0822-46ea-99fd-fecf64c5e523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18515
24634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1851524634
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.240488714
Short name T399
Test name
Test status
Simulation time 211115276 ps
CPU time 0.79 seconds
Started Jun 21 04:57:44 PM PDT 24
Finished Jun 21 04:57:47 PM PDT 24
Peak memory 206020 kb
Host smart-32f77b40-6a96-40e2-839d-78efc60e5f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24048
8714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.240488714
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4183505994
Short name T229
Test name
Test status
Simulation time 95956626 ps
CPU time 2.48 seconds
Started Jun 21 04:42:39 PM PDT 24
Finished Jun 21 04:42:43 PM PDT 24
Peak memory 214220 kb
Host smart-ce47966d-17b8-467e-89fc-4b8451c6bdb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4183505994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.4183505994
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1006992998
Short name T116
Test name
Test status
Simulation time 231345224 ps
CPU time 0.84 seconds
Started Jun 21 04:57:37 PM PDT 24
Finished Jun 21 04:57:38 PM PDT 24
Peak memory 205928 kb
Host smart-5050b5d1-1a96-4d5f-b60c-948356e6da12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10069
92998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1006992998
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.1110495613
Short name T56
Test name
Test status
Simulation time 14238087687 ps
CPU time 396.36 seconds
Started Jun 21 04:57:09 PM PDT 24
Finished Jun 21 05:03:48 PM PDT 24
Peak memory 206208 kb
Host smart-6cce656d-2026-4b37-a450-ae0c98052620
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1110495613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.1110495613
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.3894096336
Short name T13
Test name
Test status
Simulation time 23451079977 ps
CPU time 26.37 seconds
Started Jun 21 04:57:42 PM PDT 24
Finished Jun 21 04:58:09 PM PDT 24
Peak memory 206220 kb
Host smart-7686a0c9-2c3b-4713-bd8f-3573daeb1636
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3894096336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.3894096336
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.2417997354
Short name T37
Test name
Test status
Simulation time 24166891199 ps
CPU time 687.24 seconds
Started Jun 21 04:54:14 PM PDT 24
Finished Jun 21 05:05:44 PM PDT 24
Peak memory 205744 kb
Host smart-32849884-9adc-481f-a501-1aaa3b52f9c1
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2417997354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.2417997354
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.3595006486
Short name T165
Test name
Test status
Simulation time 319259125 ps
CPU time 1.14 seconds
Started Jun 21 04:57:33 PM PDT 24
Finished Jun 21 04:57:35 PM PDT 24
Peak memory 206024 kb
Host smart-6a9c7cfa-7e76-44ab-8117-dd37b72e502d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35950
06486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.3595006486
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2533774339
Short name T25
Test name
Test status
Simulation time 62254333 ps
CPU time 0.7 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 04:57:52 PM PDT 24
Peak memory 206032 kb
Host smart-121e45fd-beba-474a-b7ca-0d88908b585e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25337
74339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2533774339
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.110366633
Short name T154
Test name
Test status
Simulation time 7079721412 ps
CPU time 64.32 seconds
Started Jun 21 04:58:43 PM PDT 24
Finished Jun 21 04:59:48 PM PDT 24
Peak memory 206280 kb
Host smart-139204cd-b618-4503-906e-5d1ca591f311
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=110366633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.110366633
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.50049092
Short name T195
Test name
Test status
Simulation time 1833551094 ps
CPU time 2.45 seconds
Started Jun 21 04:53:21 PM PDT 24
Finished Jun 21 04:53:24 PM PDT 24
Peak memory 223836 kb
Host smart-7b85662b-d46e-41e1-9acd-2fd40a14d070
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=50049092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.50049092
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3661044250
Short name T2532
Test name
Test status
Simulation time 45964370 ps
CPU time 0.65 seconds
Started Jun 21 04:43:02 PM PDT 24
Finished Jun 21 04:43:04 PM PDT 24
Peak memory 205788 kb
Host smart-12542d1e-1fee-4736-80b9-1766f15d563c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3661044250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.3661044250
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.3023977590
Short name T71
Test name
Test status
Simulation time 327024936 ps
CPU time 1.07 seconds
Started Jun 21 04:53:20 PM PDT 24
Finished Jun 21 04:53:22 PM PDT 24
Peak memory 206024 kb
Host smart-4cc59748-5253-4194-8ceb-46b37e9f7845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30239
77590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.3023977590
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.2503458066
Short name T41
Test name
Test status
Simulation time 20166890166 ps
CPU time 17.7 seconds
Started Jun 21 04:53:13 PM PDT 24
Finished Jun 21 04:53:32 PM PDT 24
Peak memory 206092 kb
Host smart-dc88de85-682b-4995-897e-d520c3f597ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25034
58066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.2503458066
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2506613988
Short name T248
Test name
Test status
Simulation time 80732827 ps
CPU time 0.79 seconds
Started Jun 21 04:43:03 PM PDT 24
Finished Jun 21 04:43:06 PM PDT 24
Peak memory 205916 kb
Host smart-f63b9bca-6fcc-4c69-93fd-04b5e1aa3965
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2506613988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2506613988
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3961544567
Short name T271
Test name
Test status
Simulation time 110276512 ps
CPU time 0.72 seconds
Started Jun 21 04:42:55 PM PDT 24
Finished Jun 21 04:42:57 PM PDT 24
Peak memory 205056 kb
Host smart-6e32b6c9-ff7d-45a4-9151-5c63464d1cc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3961544567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3961544567
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.2549604518
Short name T89
Test name
Test status
Simulation time 161150373 ps
CPU time 0.83 seconds
Started Jun 21 04:53:26 PM PDT 24
Finished Jun 21 04:53:29 PM PDT 24
Peak memory 205964 kb
Host smart-2562c546-2407-4106-b856-6e957e33a47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25496
04518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.2549604518
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3016454081
Short name T295
Test name
Test status
Simulation time 157917139 ps
CPU time 0.81 seconds
Started Jun 21 05:00:15 PM PDT 24
Finished Jun 21 05:00:24 PM PDT 24
Peak memory 206028 kb
Host smart-7bf9879f-c388-43fa-b8fa-693c0e6d0562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30164
54081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3016454081
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.3076437852
Short name T5
Test name
Test status
Simulation time 19691071184 ps
CPU time 116.49 seconds
Started Jun 21 04:54:54 PM PDT 24
Finished Jun 21 04:56:53 PM PDT 24
Peak memory 206484 kb
Host smart-df8a1877-97bf-45ed-a3f8-ca46b307342e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3076437852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.3076437852
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2129917574
Short name T2534
Test name
Test status
Simulation time 126206347 ps
CPU time 0.74 seconds
Started Jun 21 04:43:00 PM PDT 24
Finished Jun 21 04:43:03 PM PDT 24
Peak memory 205800 kb
Host smart-abae25fb-aa68-495c-a641-d7098757caa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2129917574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2129917574
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3238376719
Short name T286
Test name
Test status
Simulation time 829302003 ps
CPU time 2.94 seconds
Started Jun 21 04:42:59 PM PDT 24
Finished Jun 21 04:43:04 PM PDT 24
Peak memory 206184 kb
Host smart-0de78981-3434-45cd-99fb-8a178cea2a50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3238376719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3238376719
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.3813257482
Short name T751
Test name
Test status
Simulation time 155926956 ps
CPU time 0.77 seconds
Started Jun 21 04:56:39 PM PDT 24
Finished Jun 21 04:56:42 PM PDT 24
Peak memory 205972 kb
Host smart-a2fee2ff-3a30-4051-b1f5-f3652a73959f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38132
57482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3813257482
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.3217044379
Short name T66
Test name
Test status
Simulation time 521252372 ps
CPU time 1.47 seconds
Started Jun 21 04:53:04 PM PDT 24
Finished Jun 21 04:53:07 PM PDT 24
Peak memory 205972 kb
Host smart-a10d0ca3-b7b7-4e20-98c4-de90670592e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32170
44379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.3217044379
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2608968351
Short name T236
Test name
Test status
Simulation time 166424705 ps
CPU time 2.07 seconds
Started Jun 21 04:42:23 PM PDT 24
Finished Jun 21 04:42:27 PM PDT 24
Peak memory 221028 kb
Host smart-aefda74f-0ead-4ed3-aecb-4c0e70ff8013
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2608968351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2608968351
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.4185227495
Short name T191
Test name
Test status
Simulation time 3595469604 ps
CPU time 4.38 seconds
Started Jun 21 04:54:29 PM PDT 24
Finished Jun 21 04:54:38 PM PDT 24
Peak memory 206264 kb
Host smart-d16d7cf5-700d-4b3f-a787-5f1d3fecd3f6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4185227495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.4185227495
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.3232346659
Short name T174
Test name
Test status
Simulation time 1306275878 ps
CPU time 2.85 seconds
Started Jun 21 04:54:32 PM PDT 24
Finished Jun 21 04:54:40 PM PDT 24
Peak memory 206172 kb
Host smart-5340b43b-9bf6-48f1-9b8b-2cb1b4b989e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32323
46659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.3232346659
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.3258318440
Short name T51
Test name
Test status
Simulation time 250638319 ps
CPU time 0.97 seconds
Started Jun 21 04:53:13 PM PDT 24
Finished Jun 21 04:53:16 PM PDT 24
Peak memory 205920 kb
Host smart-c9206b32-9188-421c-a1b2-b184325fc423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32583
18440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.3258318440
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1233330550
Short name T290
Test name
Test status
Simulation time 1056101761 ps
CPU time 4.44 seconds
Started Jun 21 04:42:47 PM PDT 24
Finished Jun 21 04:42:54 PM PDT 24
Peak memory 206184 kb
Host smart-8819636e-e7b0-4266-9927-f111fda3253c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1233330550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1233330550
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.1802717035
Short name T60
Test name
Test status
Simulation time 144056182 ps
CPU time 0.77 seconds
Started Jun 21 04:53:06 PM PDT 24
Finished Jun 21 04:53:09 PM PDT 24
Peak memory 205952 kb
Host smart-ad7c5d26-bdc0-469f-ba90-adccf5c1e848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18027
17035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.1802717035
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.133655815
Short name T2594
Test name
Test status
Simulation time 58848191 ps
CPU time 0.69 seconds
Started Jun 21 04:42:48 PM PDT 24
Finished Jun 21 04:42:51 PM PDT 24
Peak memory 205796 kb
Host smart-2987e23c-28db-475f-9dba-69db12ae5322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=133655815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.133655815
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.4095633422
Short name T159
Test name
Test status
Simulation time 24369769985 ps
CPU time 579.91 seconds
Started Jun 21 04:54:11 PM PDT 24
Finished Jun 21 05:03:52 PM PDT 24
Peak memory 206272 kb
Host smart-c47838e6-96dc-4675-aeb4-f5cadb1fd1f0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4095633422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.4095633422
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2092952870
Short name T30
Test name
Test status
Simulation time 39638945 ps
CPU time 0.63 seconds
Started Jun 21 04:56:55 PM PDT 24
Finished Jun 21 04:56:58 PM PDT 24
Peak memory 206036 kb
Host smart-294a08a2-4681-454d-a3e8-f82525e6cc6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20929
52870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2092952870
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1214931750
Short name T18
Test name
Test status
Simulation time 142313950 ps
CPU time 0.82 seconds
Started Jun 21 04:56:07 PM PDT 24
Finished Jun 21 04:56:10 PM PDT 24
Peak memory 206032 kb
Host smart-528670f6-a89b-4868-910d-7f5ba2c2247b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12149
31750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1214931750
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.783400367
Short name T2578
Test name
Test status
Simulation time 283143658 ps
CPU time 2.64 seconds
Started Jun 21 04:42:46 PM PDT 24
Finished Jun 21 04:42:51 PM PDT 24
Peak memory 221928 kb
Host smart-5ae5bedc-2974-46e4-9664-f0ad18acc5ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=783400367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.783400367
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3395237538
Short name T87
Test name
Test status
Simulation time 21248550144 ps
CPU time 50.89 seconds
Started Jun 21 04:53:15 PM PDT 24
Finished Jun 21 04:54:07 PM PDT 24
Peak memory 214552 kb
Host smart-c552a104-78b0-4fce-a246-2b3425fbdf8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33952
37538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3395237538
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.354315020
Short name T86
Test name
Test status
Simulation time 134807111 ps
CPU time 0.82 seconds
Started Jun 21 04:53:30 PM PDT 24
Finished Jun 21 04:53:33 PM PDT 24
Peak memory 205956 kb
Host smart-897ca41b-3374-41c0-b959-50edfd52b5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35431
5020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.354315020
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.2059170201
Short name T166
Test name
Test status
Simulation time 30458729951 ps
CPU time 757.7 seconds
Started Jun 21 04:53:45 PM PDT 24
Finished Jun 21 05:06:24 PM PDT 24
Peak memory 206204 kb
Host smart-b0af3714-6191-4989-9326-fae43838262c
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2059170201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.2059170201
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3806688574
Short name T77
Test name
Test status
Simulation time 184019883 ps
CPU time 1.9 seconds
Started Jun 21 04:56:55 PM PDT 24
Finished Jun 21 04:56:59 PM PDT 24
Peak memory 206104 kb
Host smart-4d6fbb3d-c72f-4524-90e9-a9a1508ed2b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38066
88574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3806688574
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.985402686
Short name T52
Test name
Test status
Simulation time 149665896 ps
CPU time 0.78 seconds
Started Jun 21 04:53:09 PM PDT 24
Finished Jun 21 04:53:10 PM PDT 24
Peak memory 205968 kb
Host smart-660babc4-ce40-419e-94dd-d305c9750fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98540
2686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.985402686
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.3842095354
Short name T63
Test name
Test status
Simulation time 4156631996 ps
CPU time 9.65 seconds
Started Jun 21 04:53:04 PM PDT 24
Finished Jun 21 04:53:15 PM PDT 24
Peak memory 206336 kb
Host smart-9f0120b6-df67-4978-9d44-74d12f0d23a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38420
95354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.3842095354
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.877180625
Short name T64
Test name
Test status
Simulation time 176917055 ps
CPU time 0.8 seconds
Started Jun 21 04:53:05 PM PDT 24
Finished Jun 21 04:53:07 PM PDT 24
Peak memory 206020 kb
Host smart-ab60aa46-a300-4276-9a2d-87a431923f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87718
0625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.877180625
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.2480210698
Short name T47
Test name
Test status
Simulation time 161099876 ps
CPU time 0.84 seconds
Started Jun 21 04:53:29 PM PDT 24
Finished Jun 21 04:53:33 PM PDT 24
Peak memory 205952 kb
Host smart-5bf260c7-022b-406a-9487-dafb40408e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24802
10698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.2480210698
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.108008257
Short name T438
Test name
Test status
Simulation time 4811312820 ps
CPU time 36.17 seconds
Started Jun 21 04:55:57 PM PDT 24
Finished Jun 21 04:56:35 PM PDT 24
Peak memory 206228 kb
Host smart-b2001661-3161-42ac-9490-be00d8254c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10800
8257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.108008257
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2526567442
Short name T910
Test name
Test status
Simulation time 21010905602 ps
CPU time 45.42 seconds
Started Jun 21 04:56:07 PM PDT 24
Finished Jun 21 04:56:55 PM PDT 24
Peak memory 206200 kb
Host smart-628282ba-177c-4722-8832-0acb29c36e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25265
67442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2526567442
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.595174279
Short name T235
Test name
Test status
Simulation time 930191720 ps
CPU time 5.08 seconds
Started Jun 21 04:42:23 PM PDT 24
Finished Jun 21 04:42:30 PM PDT 24
Peak memory 205272 kb
Host smart-e75b7ab7-b9ac-4662-a9e0-0b10368e1cf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=595174279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.595174279
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.869242206
Short name T234
Test name
Test status
Simulation time 428198158 ps
CPU time 2.6 seconds
Started Jun 21 04:42:49 PM PDT 24
Finished Jun 21 04:42:54 PM PDT 24
Peak memory 206152 kb
Host smart-a9f9ff45-af31-4f31-beb5-7e5b29abcfca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=869242206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.869242206
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.663999523
Short name T241
Test name
Test status
Simulation time 951126189 ps
CPU time 4.94 seconds
Started Jun 21 04:42:51 PM PDT 24
Finished Jun 21 04:42:58 PM PDT 24
Peak memory 206088 kb
Host smart-def63f42-9a6d-4a60-be20-665f0e656252
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=663999523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.663999523
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.1895646728
Short name T2260
Test name
Test status
Simulation time 1046275267 ps
CPU time 2.44 seconds
Started Jun 21 04:53:04 PM PDT 24
Finished Jun 21 04:53:08 PM PDT 24
Peak memory 206112 kb
Host smart-98fa8060-2e0c-4e24-9c3d-bccb779ae6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18956
46728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.1895646728
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2196069445
Short name T125
Test name
Test status
Simulation time 241674834 ps
CPU time 0.92 seconds
Started Jun 21 04:53:14 PM PDT 24
Finished Jun 21 04:53:16 PM PDT 24
Peak memory 205976 kb
Host smart-ef95f31d-f17c-484b-aee0-75c63619766d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21960
69445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2196069445
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.49146798
Short name T2125
Test name
Test status
Simulation time 370249869 ps
CPU time 1.18 seconds
Started Jun 21 04:53:14 PM PDT 24
Finished Jun 21 04:53:16 PM PDT 24
Peak memory 205976 kb
Host smart-83e82071-c771-47d9-9a2e-68e15b75e9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49146
798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.49146798
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.63441657
Short name T38
Test name
Test status
Simulation time 20053719802 ps
CPU time 161.81 seconds
Started Jun 21 04:53:15 PM PDT 24
Finished Jun 21 04:55:58 PM PDT 24
Peak memory 206360 kb
Host smart-fbac8361-76eb-45db-bb2a-cd6be553e284
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=63441657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.63441657
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3912859309
Short name T145
Test name
Test status
Simulation time 214531552 ps
CPU time 0.86 seconds
Started Jun 21 04:53:36 PM PDT 24
Finished Jun 21 04:53:39 PM PDT 24
Peak memory 206008 kb
Host smart-333b5b08-9860-4c30-8ece-005bd55137f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39128
59309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3912859309
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1829486743
Short name T140
Test name
Test status
Simulation time 202661386 ps
CPU time 0.89 seconds
Started Jun 21 04:55:40 PM PDT 24
Finished Jun 21 04:55:42 PM PDT 24
Peak memory 206024 kb
Host smart-51fb60bd-96dc-41d2-b298-830cf86b3da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18294
86743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1829486743
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1096387355
Short name T141
Test name
Test status
Simulation time 234015210 ps
CPU time 1.02 seconds
Started Jun 21 04:55:52 PM PDT 24
Finished Jun 21 04:55:54 PM PDT 24
Peak memory 206024 kb
Host smart-2b8afc2a-34d4-4ae6-8588-c9fd36b0610e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10963
87355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1096387355
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.278811624
Short name T120
Test name
Test status
Simulation time 198392092 ps
CPU time 0.88 seconds
Started Jun 21 04:56:06 PM PDT 24
Finished Jun 21 04:56:08 PM PDT 24
Peak memory 205956 kb
Host smart-393fd0da-9add-44cd-92b0-825e42c2d272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27881
1624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.278811624
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1980659357
Short name T128
Test name
Test status
Simulation time 164290217 ps
CPU time 0.84 seconds
Started Jun 21 04:56:39 PM PDT 24
Finished Jun 21 04:56:43 PM PDT 24
Peak memory 205972 kb
Host smart-31a1c54f-d058-40f9-9ab6-23f2a341133b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19806
59357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1980659357
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.184997999
Short name T134
Test name
Test status
Simulation time 186225234 ps
CPU time 0.81 seconds
Started Jun 21 04:56:46 PM PDT 24
Finished Jun 21 04:56:49 PM PDT 24
Peak memory 206020 kb
Host smart-833c1969-59cb-435b-a4b2-46435d9c5046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18499
7999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.184997999
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2275185347
Short name T124
Test name
Test status
Simulation time 181036590 ps
CPU time 0.82 seconds
Started Jun 21 04:56:56 PM PDT 24
Finished Jun 21 04:57:00 PM PDT 24
Peak memory 205924 kb
Host smart-78b725db-7a2a-4b53-a5b9-14897036e067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22751
85347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2275185347
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3488528745
Short name T1473
Test name
Test status
Simulation time 166245030 ps
CPU time 0.77 seconds
Started Jun 21 04:57:08 PM PDT 24
Finished Jun 21 04:57:11 PM PDT 24
Peak memory 206028 kb
Host smart-b26eb927-3483-441c-b2c9-5e3db777c88e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34885
28745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3488528745
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2038257277
Short name T132
Test name
Test status
Simulation time 198952697 ps
CPU time 1 seconds
Started Jun 21 04:58:03 PM PDT 24
Finished Jun 21 04:58:05 PM PDT 24
Peak memory 205960 kb
Host smart-7fd49d32-f561-4960-9405-50a2831092db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20382
57277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2038257277
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.100541126
Short name T147
Test name
Test status
Simulation time 232376319 ps
CPU time 0.88 seconds
Started Jun 21 04:59:03 PM PDT 24
Finished Jun 21 04:59:09 PM PDT 24
Peak memory 205960 kb
Host smart-c7e1e05f-6b4b-4471-8efd-5698dce8689f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10054
1126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.100541126
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1390922343
Short name T2507
Test name
Test status
Simulation time 155581803 ps
CPU time 3.33 seconds
Started Jun 21 04:42:24 PM PDT 24
Finished Jun 21 04:42:29 PM PDT 24
Peak memory 205812 kb
Host smart-e019839b-ad6c-4e5f-b3a6-933d5fb5e753
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1390922343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1390922343
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2802276569
Short name T249
Test name
Test status
Simulation time 343761898 ps
CPU time 3.8 seconds
Started Jun 21 04:42:37 PM PDT 24
Finished Jun 21 04:42:43 PM PDT 24
Peak memory 205296 kb
Host smart-d669524c-d37e-4ea5-8f43-ed2022a226b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2802276569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2802276569
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.86348126
Short name T256
Test name
Test status
Simulation time 70631708 ps
CPU time 0.91 seconds
Started Jun 21 04:42:44 PM PDT 24
Finished Jun 21 04:42:48 PM PDT 24
Peak memory 205924 kb
Host smart-0426329b-ad63-40ed-9b05-a279ace8b8dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=86348126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.86348126
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2931011448
Short name T2530
Test name
Test status
Simulation time 153879608 ps
CPU time 1.39 seconds
Started Jun 21 04:42:24 PM PDT 24
Finished Jun 21 04:42:27 PM PDT 24
Peak memory 213940 kb
Host smart-7b5eddba-d8f2-4ea8-9fe6-d2c3b84a1c26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931011448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2931011448
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2999696968
Short name T2550
Test name
Test status
Simulation time 131337388 ps
CPU time 0.87 seconds
Started Jun 21 04:42:23 PM PDT 24
Finished Jun 21 04:42:25 PM PDT 24
Peak memory 205464 kb
Host smart-50fc7cf5-060c-4d83-a209-f4fb5aa35ba6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2999696968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2999696968
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.985445087
Short name T2593
Test name
Test status
Simulation time 101270723 ps
CPU time 1.44 seconds
Started Jun 21 04:42:45 PM PDT 24
Finished Jun 21 04:42:54 PM PDT 24
Peak memory 214480 kb
Host smart-e91b2e0a-088f-49f9-afca-479839f9309d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=985445087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.985445087
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4263534926
Short name T2531
Test name
Test status
Simulation time 177018855 ps
CPU time 3.93 seconds
Started Jun 21 04:42:31 PM PDT 24
Finished Jun 21 04:42:36 PM PDT 24
Peak memory 206076 kb
Host smart-6cf56c74-f590-43a0-816f-0d3a3cd5f7f7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4263534926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.4263534926
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.695652569
Short name T2563
Test name
Test status
Simulation time 171781542 ps
CPU time 1.83 seconds
Started Jun 21 04:42:30 PM PDT 24
Finished Jun 21 04:42:33 PM PDT 24
Peak memory 206120 kb
Host smart-5969bf16-82cd-4cde-baa3-dcd08870013f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=695652569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.695652569
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1327611919
Short name T2555
Test name
Test status
Simulation time 157459660 ps
CPU time 2.06 seconds
Started Jun 21 04:42:47 PM PDT 24
Finished Jun 21 04:42:51 PM PDT 24
Peak memory 206172 kb
Host smart-4f983830-de57-4144-a405-c3683637ae5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1327611919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1327611919
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2074795298
Short name T242
Test name
Test status
Simulation time 130255629 ps
CPU time 3.36 seconds
Started Jun 21 04:42:23 PM PDT 24
Finished Jun 21 04:42:28 PM PDT 24
Peak memory 205836 kb
Host smart-79da0d04-4b4b-4b5a-a3e5-aa9e0576e1f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2074795298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2074795298
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.4076005777
Short name T2554
Test name
Test status
Simulation time 1793893224 ps
CPU time 9.01 seconds
Started Jun 21 04:43:09 PM PDT 24
Finished Jun 21 04:43:21 PM PDT 24
Peak memory 206184 kb
Host smart-05f2863c-dcbe-4050-b7f3-d5cda0d170c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4076005777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.4076005777
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2070177555
Short name T2544
Test name
Test status
Simulation time 281039918 ps
CPU time 1.13 seconds
Started Jun 21 04:42:23 PM PDT 24
Finished Jun 21 04:42:26 PM PDT 24
Peak memory 205080 kb
Host smart-00c53a38-1727-49e6-9318-182bc0596c2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2070177555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2070177555
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.91996394
Short name T2562
Test name
Test status
Simulation time 159881984 ps
CPU time 1.74 seconds
Started Jun 21 04:42:29 PM PDT 24
Finished Jun 21 04:42:32 PM PDT 24
Peak memory 214244 kb
Host smart-75e4c6b3-f63f-4731-b79b-25597e606838
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91996394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_
csr_mem_rw_with_rand_reset.91996394
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3946280244
Short name T2596
Test name
Test status
Simulation time 49656386 ps
CPU time 0.98 seconds
Started Jun 21 04:42:29 PM PDT 24
Finished Jun 21 04:42:31 PM PDT 24
Peak memory 206096 kb
Host smart-17b53085-c25b-49ff-a8b8-32070b08a839
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3946280244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3946280244
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.654203292
Short name T207
Test name
Test status
Simulation time 50588919 ps
CPU time 0.71 seconds
Started Jun 21 04:43:07 PM PDT 24
Finished Jun 21 04:43:10 PM PDT 24
Peak memory 205804 kb
Host smart-a9d84e83-b512-42db-b378-ccb925611131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=654203292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.654203292
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.535668584
Short name T2603
Test name
Test status
Simulation time 119922281 ps
CPU time 1.42 seconds
Started Jun 21 04:42:30 PM PDT 24
Finished Jun 21 04:42:33 PM PDT 24
Peak memory 214076 kb
Host smart-6ba19eec-c9f8-4158-8545-4c0776423717
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=535668584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.535668584
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1355151204
Short name T2545
Test name
Test status
Simulation time 167615829 ps
CPU time 4.09 seconds
Started Jun 21 04:42:30 PM PDT 24
Finished Jun 21 04:42:35 PM PDT 24
Peak memory 206140 kb
Host smart-0ba939dc-0c9e-4c81-8e30-9a4507eeb19e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1355151204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1355151204
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4013928382
Short name T2541
Test name
Test status
Simulation time 126260495 ps
CPU time 1.23 seconds
Started Jun 21 04:42:58 PM PDT 24
Finished Jun 21 04:43:00 PM PDT 24
Peak memory 206092 kb
Host smart-7f4c8749-b160-428b-a698-fcf35bae4380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4013928382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.4013928382
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.154619688
Short name T231
Test name
Test status
Simulation time 126391162 ps
CPU time 2.27 seconds
Started Jun 21 04:42:25 PM PDT 24
Finished Jun 21 04:42:29 PM PDT 24
Peak memory 214316 kb
Host smart-d06c53d9-d0dc-47a4-a22e-4a8d33cb5df7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=154619688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.154619688
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3719237259
Short name T285
Test name
Test status
Simulation time 565384133 ps
CPU time 3.97 seconds
Started Jun 21 04:42:27 PM PDT 24
Finished Jun 21 04:42:33 PM PDT 24
Peak memory 205288 kb
Host smart-a9c94611-4679-4930-8957-8f419539bf7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3719237259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3719237259
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2312742900
Short name T2587
Test name
Test status
Simulation time 99239061 ps
CPU time 1.26 seconds
Started Jun 21 04:42:34 PM PDT 24
Finished Jun 21 04:42:37 PM PDT 24
Peak memory 221540 kb
Host smart-aefd6032-0d02-4a62-a1ce-28addcef9a83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312742900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2312742900
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.765335798
Short name T254
Test name
Test status
Simulation time 57758035 ps
CPU time 1.02 seconds
Started Jun 21 04:42:28 PM PDT 24
Finished Jun 21 04:42:31 PM PDT 24
Peak memory 205220 kb
Host smart-452dc758-8071-4a3b-bda9-e01da02e9fb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=765335798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.765335798
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1724183344
Short name T204
Test name
Test status
Simulation time 87201393 ps
CPU time 0.7 seconds
Started Jun 21 04:42:37 PM PDT 24
Finished Jun 21 04:42:39 PM PDT 24
Peak memory 205796 kb
Host smart-52dcf358-51db-4eea-a624-b64f8d78f4ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1724183344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1724183344
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3324035073
Short name T2526
Test name
Test status
Simulation time 110001112 ps
CPU time 1.12 seconds
Started Jun 21 04:42:30 PM PDT 24
Finished Jun 21 04:42:33 PM PDT 24
Peak memory 204688 kb
Host smart-62f15b5b-852f-4312-ba72-e1d217bbd546
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3324035073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3324035073
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4101222104
Short name T239
Test name
Test status
Simulation time 247860172 ps
CPU time 2.72 seconds
Started Jun 21 04:42:33 PM PDT 24
Finished Jun 21 04:42:38 PM PDT 24
Peak memory 220920 kb
Host smart-9ac3f02e-18e6-4b93-b654-ade4ca813bd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4101222104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.4101222104
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1589222998
Short name T2573
Test name
Test status
Simulation time 762004798 ps
CPU time 3.08 seconds
Started Jun 21 04:42:56 PM PDT 24
Finished Jun 21 04:43:00 PM PDT 24
Peak memory 206100 kb
Host smart-f7f31237-d913-4887-a8c3-c3e1065d054a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1589222998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1589222998
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1132158206
Short name T2558
Test name
Test status
Simulation time 157770825 ps
CPU time 2.75 seconds
Started Jun 21 04:42:23 PM PDT 24
Finished Jun 21 04:42:28 PM PDT 24
Peak memory 213388 kb
Host smart-c4100d69-c786-4733-8e50-e9a9ed4bce34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132158206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1132158206
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3674958604
Short name T253
Test name
Test status
Simulation time 62586418 ps
CPU time 0.97 seconds
Started Jun 21 04:43:17 PM PDT 24
Finished Jun 21 04:43:22 PM PDT 24
Peak memory 206140 kb
Host smart-aac07af6-bba7-4879-a352-8a5ebcf3fa28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3674958604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3674958604
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2493622386
Short name T2600
Test name
Test status
Simulation time 47551351 ps
CPU time 0.65 seconds
Started Jun 21 04:43:10 PM PDT 24
Finished Jun 21 04:43:14 PM PDT 24
Peak memory 205804 kb
Host smart-5070d59b-7d3f-40cc-9581-b653712c8baf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2493622386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2493622386
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.4191701849
Short name T259
Test name
Test status
Simulation time 129378813 ps
CPU time 1.66 seconds
Started Jun 21 04:43:11 PM PDT 24
Finished Jun 21 04:43:16 PM PDT 24
Peak memory 206096 kb
Host smart-a3629a6c-a9c5-42e3-8502-f3bdcb652443
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4191701849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.4191701849
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3432716510
Short name T232
Test name
Test status
Simulation time 149137664 ps
CPU time 1.76 seconds
Started Jun 21 04:43:04 PM PDT 24
Finished Jun 21 04:43:07 PM PDT 24
Peak memory 214352 kb
Host smart-eeca096d-fe89-4919-8fbb-d9b0b2b02738
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3432716510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3432716510
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.273286386
Short name T2510
Test name
Test status
Simulation time 154706724 ps
CPU time 1.9 seconds
Started Jun 21 04:42:29 PM PDT 24
Finished Jun 21 04:42:32 PM PDT 24
Peak memory 214424 kb
Host smart-a1ed6b90-d170-4772-93f3-e6b12abcd57d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273286386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.273286386
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3461727007
Short name T2547
Test name
Test status
Simulation time 91592636 ps
CPU time 0.87 seconds
Started Jun 21 04:42:47 PM PDT 24
Finished Jun 21 04:42:50 PM PDT 24
Peak memory 205928 kb
Host smart-b227d33e-8e9d-4159-8444-6fba7808986d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3461727007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3461727007
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.540151068
Short name T2607
Test name
Test status
Simulation time 72272935 ps
CPU time 0.7 seconds
Started Jun 21 04:42:45 PM PDT 24
Finished Jun 21 04:42:48 PM PDT 24
Peak memory 205796 kb
Host smart-dea1feab-6640-4e84-8fe0-bd41fcc74b30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=540151068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.540151068
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2265551041
Short name T2553
Test name
Test status
Simulation time 203403778 ps
CPU time 1.59 seconds
Started Jun 21 04:42:50 PM PDT 24
Finished Jun 21 04:42:54 PM PDT 24
Peak memory 206164 kb
Host smart-1763d6e8-ff77-4edf-a423-1467f16b507a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2265551041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.2265551041
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3700287355
Short name T2574
Test name
Test status
Simulation time 143773619 ps
CPU time 1.68 seconds
Started Jun 21 04:42:21 PM PDT 24
Finished Jun 21 04:42:24 PM PDT 24
Peak memory 206116 kb
Host smart-0d313b1b-350a-4940-9c25-53b39935aee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3700287355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3700287355
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1385691955
Short name T2561
Test name
Test status
Simulation time 513118281 ps
CPU time 2.53 seconds
Started Jun 21 04:42:50 PM PDT 24
Finished Jun 21 04:42:55 PM PDT 24
Peak memory 206144 kb
Host smart-488aa4fa-f4bd-447d-ac45-811c2682d3e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1385691955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1385691955
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1373721054
Short name T2511
Test name
Test status
Simulation time 120453157 ps
CPU time 2.49 seconds
Started Jun 21 04:42:38 PM PDT 24
Finished Jun 21 04:42:42 PM PDT 24
Peak memory 222400 kb
Host smart-c99ba3e9-5b0c-4fcc-a124-31edb508878e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373721054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1373721054
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3841818871
Short name T2602
Test name
Test status
Simulation time 55074824 ps
CPU time 0.79 seconds
Started Jun 21 04:43:05 PM PDT 24
Finished Jun 21 04:43:08 PM PDT 24
Peak memory 205928 kb
Host smart-cfa9863a-556e-4411-97b6-67bfd9ba91c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3841818871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3841818871
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.390705504
Short name T2549
Test name
Test status
Simulation time 47889731 ps
CPU time 0.67 seconds
Started Jun 21 04:42:58 PM PDT 24
Finished Jun 21 04:43:01 PM PDT 24
Peak memory 205792 kb
Host smart-644a492b-c7a1-42ce-bcac-c185e0dbcd4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=390705504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.390705504
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1474129703
Short name T2567
Test name
Test status
Simulation time 119076093 ps
CPU time 1.53 seconds
Started Jun 21 04:42:46 PM PDT 24
Finished Jun 21 04:42:50 PM PDT 24
Peak memory 206084 kb
Host smart-df0cf1c1-a24e-476f-8c89-f2b18721d7ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1474129703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1474129703
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1873582952
Short name T2577
Test name
Test status
Simulation time 59838876 ps
CPU time 1.41 seconds
Started Jun 21 04:43:23 PM PDT 24
Finished Jun 21 04:43:29 PM PDT 24
Peak memory 206204 kb
Host smart-5ffdb3de-68fe-4649-ad86-b1b3003b8b8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1873582952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1873582952
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3109754982
Short name T287
Test name
Test status
Simulation time 903223098 ps
CPU time 4.85 seconds
Started Jun 21 04:42:25 PM PDT 24
Finished Jun 21 04:42:32 PM PDT 24
Peak memory 206268 kb
Host smart-303f5cf0-43a1-4ef0-8521-a32c2c772069
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3109754982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3109754982
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1920320898
Short name T240
Test name
Test status
Simulation time 142638722 ps
CPU time 1.92 seconds
Started Jun 21 04:42:42 PM PDT 24
Finished Jun 21 04:42:45 PM PDT 24
Peak memory 222380 kb
Host smart-2e3c6af5-73d9-4766-9ecd-b4d9135b391f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920320898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.1920320898
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3327305535
Short name T2592
Test name
Test status
Simulation time 61992104 ps
CPU time 0.84 seconds
Started Jun 21 04:42:54 PM PDT 24
Finished Jun 21 04:42:56 PM PDT 24
Peak memory 205924 kb
Host smart-9e8e0a58-c233-4d16-8208-d74dd935684e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3327305535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3327305535
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1362240335
Short name T2519
Test name
Test status
Simulation time 34060469 ps
CPU time 0.66 seconds
Started Jun 21 04:42:44 PM PDT 24
Finished Jun 21 04:42:47 PM PDT 24
Peak memory 205804 kb
Host smart-daa5816a-770d-41a0-b35a-0af4ed32c96d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1362240335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1362240335
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.858398314
Short name T2521
Test name
Test status
Simulation time 262290302 ps
CPU time 1.5 seconds
Started Jun 21 04:43:03 PM PDT 24
Finished Jun 21 04:43:06 PM PDT 24
Peak memory 206128 kb
Host smart-dee0a39a-e59c-4555-b096-80314a9b1d28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=858398314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.858398314
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1844654212
Short name T2552
Test name
Test status
Simulation time 177021630 ps
CPU time 1.89 seconds
Started Jun 21 04:42:46 PM PDT 24
Finished Jun 21 04:42:50 PM PDT 24
Peak memory 206204 kb
Host smart-f994c355-25b4-453c-b7e0-50824e5b1f56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1844654212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1844654212
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3390957891
Short name T292
Test name
Test status
Simulation time 587855390 ps
CPU time 4.04 seconds
Started Jun 21 04:42:59 PM PDT 24
Finished Jun 21 04:43:05 PM PDT 24
Peak memory 206092 kb
Host smart-7f730460-b6ff-419e-8fee-f9425301f588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3390957891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3390957891
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3801427202
Short name T266
Test name
Test status
Simulation time 118642649 ps
CPU time 1.29 seconds
Started Jun 21 04:42:47 PM PDT 24
Finished Jun 21 04:42:51 PM PDT 24
Peak memory 214424 kb
Host smart-19f602f4-df82-4c72-b845-f5a5a463a503
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801427202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.3801427202
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3007732707
Short name T201
Test name
Test status
Simulation time 79022759 ps
CPU time 0.96 seconds
Started Jun 21 04:43:10 PM PDT 24
Finished Jun 21 04:43:14 PM PDT 24
Peak memory 206148 kb
Host smart-cce7512f-1152-4511-92e5-a305c43e8853
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3007732707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3007732707
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.638906597
Short name T280
Test name
Test status
Simulation time 48795521 ps
CPU time 0.71 seconds
Started Jun 21 04:42:46 PM PDT 24
Finished Jun 21 04:42:49 PM PDT 24
Peak memory 205796 kb
Host smart-47eb2c2c-67f1-4cc4-9362-601649ba15f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=638906597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.638906597
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1882851388
Short name T2523
Test name
Test status
Simulation time 132007935 ps
CPU time 1.17 seconds
Started Jun 21 04:42:32 PM PDT 24
Finished Jun 21 04:42:34 PM PDT 24
Peak memory 206088 kb
Host smart-cdf1e1ea-7a7f-459d-b241-c3066158027a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1882851388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1882851388
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.479782847
Short name T2601
Test name
Test status
Simulation time 95079754 ps
CPU time 1.38 seconds
Started Jun 21 04:42:24 PM PDT 24
Finished Jun 21 04:42:28 PM PDT 24
Peak memory 213904 kb
Host smart-1535a551-e5bb-47e8-9176-bfb3672f64d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479782847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.479782847
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.4020285691
Short name T205
Test name
Test status
Simulation time 43740410 ps
CPU time 0.72 seconds
Started Jun 21 04:42:48 PM PDT 24
Finished Jun 21 04:42:51 PM PDT 24
Peak memory 205800 kb
Host smart-d1d2988c-637d-465e-87de-757725faf075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4020285691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.4020285691
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.548410137
Short name T264
Test name
Test status
Simulation time 295850590 ps
CPU time 1.5 seconds
Started Jun 21 04:43:12 PM PDT 24
Finished Jun 21 04:43:17 PM PDT 24
Peak memory 206164 kb
Host smart-0b3aef8b-510f-4d73-b6a8-351ae99d3f80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=548410137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.548410137
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2522528709
Short name T238
Test name
Test status
Simulation time 64951853 ps
CPU time 1.35 seconds
Started Jun 21 04:42:42 PM PDT 24
Finished Jun 21 04:42:45 PM PDT 24
Peak memory 206204 kb
Host smart-6fee61b4-942a-4d51-af06-f8674e57b9b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2522528709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2522528709
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2613135367
Short name T227
Test name
Test status
Simulation time 1083432780 ps
CPU time 3.47 seconds
Started Jun 21 04:42:38 PM PDT 24
Finished Jun 21 04:42:43 PM PDT 24
Peak memory 206164 kb
Host smart-ab977b2f-cda3-485c-9b95-6ca6682863cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2613135367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2613135367
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1100177890
Short name T2556
Test name
Test status
Simulation time 194303083 ps
CPU time 1.62 seconds
Started Jun 21 04:42:48 PM PDT 24
Finished Jun 21 04:42:52 PM PDT 24
Peak memory 214344 kb
Host smart-53b51682-4784-401d-a518-2b3824a89906
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100177890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1100177890
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1610898153
Short name T255
Test name
Test status
Simulation time 86484700 ps
CPU time 0.99 seconds
Started Jun 21 04:43:02 PM PDT 24
Finished Jun 21 04:43:05 PM PDT 24
Peak memory 206112 kb
Host smart-31fece4e-ea6e-4733-b459-a8ea54cf2cba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1610898153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1610898153
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.695383270
Short name T281
Test name
Test status
Simulation time 48443950 ps
CPU time 0.67 seconds
Started Jun 21 04:42:48 PM PDT 24
Finished Jun 21 04:42:51 PM PDT 24
Peak memory 205788 kb
Host smart-c44e3822-c1cc-4bd8-ab75-1471c605ee82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=695383270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.695383270
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1765409779
Short name T2543
Test name
Test status
Simulation time 139811011 ps
CPU time 1.48 seconds
Started Jun 21 04:42:44 PM PDT 24
Finished Jun 21 04:42:48 PM PDT 24
Peak memory 205308 kb
Host smart-d678c288-b246-43e2-9bcc-da5d0e2ec0da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1765409779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1765409779
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1271193710
Short name T2560
Test name
Test status
Simulation time 102977620 ps
CPU time 2.27 seconds
Started Jun 21 04:42:55 PM PDT 24
Finished Jun 21 04:42:58 PM PDT 24
Peak memory 214276 kb
Host smart-f91d48aa-1371-4317-b3e4-09afae086dde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271193710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1271193710
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1898923912
Short name T2512
Test name
Test status
Simulation time 82010741 ps
CPU time 0.82 seconds
Started Jun 21 04:42:50 PM PDT 24
Finished Jun 21 04:42:54 PM PDT 24
Peak memory 205916 kb
Host smart-db4dee8b-3307-4e5a-8ac4-2f593031eb60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1898923912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1898923912
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3625953603
Short name T2583
Test name
Test status
Simulation time 43077526 ps
CPU time 0.74 seconds
Started Jun 21 04:42:35 PM PDT 24
Finished Jun 21 04:42:38 PM PDT 24
Peak memory 204948 kb
Host smart-41293889-d329-4ad9-a822-84a0e6317aa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3625953603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3625953603
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3269393640
Short name T263
Test name
Test status
Simulation time 95404024 ps
CPU time 1.61 seconds
Started Jun 21 04:42:45 PM PDT 24
Finished Jun 21 04:42:49 PM PDT 24
Peak memory 206088 kb
Host smart-daef44cd-eaff-4c8d-90eb-d0106d732ba6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3269393640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3269393640
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.415500519
Short name T2605
Test name
Test status
Simulation time 169698052 ps
CPU time 1.94 seconds
Started Jun 21 04:42:35 PM PDT 24
Finished Jun 21 04:42:39 PM PDT 24
Peak memory 214044 kb
Host smart-e5ea9db9-afcc-4aa4-b0b0-efd2451ef38a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=415500519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.415500519
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3760889195
Short name T2570
Test name
Test status
Simulation time 1121290452 ps
CPU time 5.51 seconds
Started Jun 21 04:42:46 PM PDT 24
Finished Jun 21 04:42:54 PM PDT 24
Peak memory 206188 kb
Host smart-1d7163ba-411e-4fed-9cdb-36a82d1216ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3760889195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3760889195
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4007492961
Short name T2597
Test name
Test status
Simulation time 103391649 ps
CPU time 2.32 seconds
Started Jun 21 04:42:34 PM PDT 24
Finished Jun 21 04:42:38 PM PDT 24
Peak memory 213476 kb
Host smart-d9b88656-3cef-4e01-bf64-8117fe51e934
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007492961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.4007492961
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3516171499
Short name T2565
Test name
Test status
Simulation time 112695703 ps
CPU time 0.86 seconds
Started Jun 21 04:43:13 PM PDT 24
Finished Jun 21 04:43:18 PM PDT 24
Peak memory 205896 kb
Host smart-a37400fb-f39f-4045-9c02-1b7ea1bf3b4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3516171499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3516171499
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4184494322
Short name T269
Test name
Test status
Simulation time 41243288 ps
CPU time 0.69 seconds
Started Jun 21 04:42:59 PM PDT 24
Finished Jun 21 04:43:01 PM PDT 24
Peak memory 205792 kb
Host smart-49dd77b9-c7bf-4012-a229-08efa5940640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4184494322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.4184494322
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1455333814
Short name T260
Test name
Test status
Simulation time 333710049 ps
CPU time 1.6 seconds
Started Jun 21 04:43:01 PM PDT 24
Finished Jun 21 04:43:05 PM PDT 24
Peak memory 206140 kb
Host smart-5ecc607f-df08-4990-887c-2fabe9de83e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1455333814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1455333814
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3138062702
Short name T2595
Test name
Test status
Simulation time 134278263 ps
CPU time 3.22 seconds
Started Jun 21 04:42:38 PM PDT 24
Finished Jun 21 04:42:43 PM PDT 24
Peak memory 222448 kb
Host smart-e8f1abd9-e359-4416-9425-ff85173e8945
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3138062702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3138062702
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1050416048
Short name T288
Test name
Test status
Simulation time 864790436 ps
CPU time 4.93 seconds
Started Jun 21 04:42:45 PM PDT 24
Finished Jun 21 04:42:52 PM PDT 24
Peak memory 205832 kb
Host smart-3ec8a6f3-bf04-4815-aa9d-da9d199765b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1050416048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1050416048
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2409233970
Short name T251
Test name
Test status
Simulation time 210003947 ps
CPU time 2.17 seconds
Started Jun 21 04:42:24 PM PDT 24
Finished Jun 21 04:42:28 PM PDT 24
Peak memory 204876 kb
Host smart-91982d1d-1597-446c-b12f-538075a2988f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2409233970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2409233970
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4292124785
Short name T246
Test name
Test status
Simulation time 172050346 ps
CPU time 3.9 seconds
Started Jun 21 04:42:44 PM PDT 24
Finished Jun 21 04:42:49 PM PDT 24
Peak memory 205316 kb
Host smart-7176b965-fa2e-4945-b0b7-0fcfa67336aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4292124785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.4292124785
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1361726346
Short name T250
Test name
Test status
Simulation time 72967894 ps
CPU time 0.84 seconds
Started Jun 21 04:42:25 PM PDT 24
Finished Jun 21 04:42:28 PM PDT 24
Peak memory 205080 kb
Host smart-79ac3ee6-6e41-424d-a9d5-f3e564d643c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1361726346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1361726346
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3130481495
Short name T2542
Test name
Test status
Simulation time 98045402 ps
CPU time 1.21 seconds
Started Jun 21 04:42:22 PM PDT 24
Finished Jun 21 04:42:25 PM PDT 24
Peak memory 214916 kb
Host smart-cbba0a93-ec03-4c8b-a8b1-6b2b2ccbcac6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130481495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3130481495
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.935771114
Short name T262
Test name
Test status
Simulation time 54496624 ps
CPU time 0.84 seconds
Started Jun 21 04:42:25 PM PDT 24
Finished Jun 21 04:42:28 PM PDT 24
Peak memory 204400 kb
Host smart-99cc5691-d2a9-4370-971d-ef14945beac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=935771114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.935771114
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3494660112
Short name T2566
Test name
Test status
Simulation time 78385657 ps
CPU time 0.75 seconds
Started Jun 21 04:42:25 PM PDT 24
Finished Jun 21 04:42:28 PM PDT 24
Peak memory 204292 kb
Host smart-2458fda4-3aaf-4c0e-a7c7-49f4c8802356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3494660112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3494660112
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2541493889
Short name T2584
Test name
Test status
Simulation time 55348033 ps
CPU time 1.34 seconds
Started Jun 21 04:42:56 PM PDT 24
Finished Jun 21 04:42:59 PM PDT 24
Peak memory 214268 kb
Host smart-80c25583-24c1-4d53-bf4d-aa32cfd48ce7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2541493889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2541493889
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1998413131
Short name T2580
Test name
Test status
Simulation time 733025005 ps
CPU time 4.83 seconds
Started Jun 21 04:42:57 PM PDT 24
Finished Jun 21 04:43:03 PM PDT 24
Peak memory 206112 kb
Host smart-3c237e06-fe8e-4a39-900f-09b0a325158a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1998413131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1998413131
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3905148594
Short name T258
Test name
Test status
Simulation time 70149495 ps
CPU time 1.27 seconds
Started Jun 21 04:42:43 PM PDT 24
Finished Jun 21 04:42:46 PM PDT 24
Peak memory 205208 kb
Host smart-b64558b8-b44f-43d7-b48d-b73273064bd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3905148594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3905148594
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1884404058
Short name T200
Test name
Test status
Simulation time 197062614 ps
CPU time 2.41 seconds
Started Jun 21 04:42:29 PM PDT 24
Finished Jun 21 04:42:33 PM PDT 24
Peak memory 221812 kb
Host smart-1d169fe4-d07d-4a9b-82af-1c9cfa6da10c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1884404058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1884404058
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.980261490
Short name T2589
Test name
Test status
Simulation time 416873645 ps
CPU time 2.68 seconds
Started Jun 21 04:42:23 PM PDT 24
Finished Jun 21 04:42:28 PM PDT 24
Peak memory 204916 kb
Host smart-92241a3a-2a03-4fa7-86de-363102b666ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=980261490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.980261490
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.908066989
Short name T278
Test name
Test status
Simulation time 39286753 ps
CPU time 0.66 seconds
Started Jun 21 04:43:05 PM PDT 24
Finished Jun 21 04:43:08 PM PDT 24
Peak memory 205804 kb
Host smart-8e4e762d-65c4-4d40-ab4b-0939cfbf5c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=908066989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.908066989
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1538272848
Short name T209
Test name
Test status
Simulation time 76413674 ps
CPU time 0.68 seconds
Started Jun 21 04:43:15 PM PDT 24
Finished Jun 21 04:43:20 PM PDT 24
Peak memory 205800 kb
Host smart-7bfbbb6d-c054-4bbc-9342-8ee90335978b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1538272848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1538272848
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2440192603
Short name T2513
Test name
Test status
Simulation time 47048255 ps
CPU time 0.69 seconds
Started Jun 21 04:42:49 PM PDT 24
Finished Jun 21 04:42:52 PM PDT 24
Peak memory 205792 kb
Host smart-73b0517c-a611-49b1-b9aa-321c6b1908f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2440192603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2440192603
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.489003957
Short name T2604
Test name
Test status
Simulation time 72609833 ps
CPU time 0.72 seconds
Started Jun 21 04:42:36 PM PDT 24
Finished Jun 21 04:42:38 PM PDT 24
Peak memory 205472 kb
Host smart-fbd2a636-3513-41e5-a380-8556f9243cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=489003957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.489003957
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.722456259
Short name T277
Test name
Test status
Simulation time 31252522 ps
CPU time 0.67 seconds
Started Jun 21 04:43:03 PM PDT 24
Finished Jun 21 04:43:06 PM PDT 24
Peak memory 205800 kb
Host smart-61874b3d-4903-4eee-93b5-97a9d0de1800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=722456259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.722456259
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2268043520
Short name T275
Test name
Test status
Simulation time 37971762 ps
CPU time 0.72 seconds
Started Jun 21 04:42:58 PM PDT 24
Finished Jun 21 04:43:00 PM PDT 24
Peak memory 205824 kb
Host smart-2a3d2074-430e-4e5d-b70e-73c172be419a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2268043520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2268043520
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2422969100
Short name T2559
Test name
Test status
Simulation time 73391141 ps
CPU time 0.69 seconds
Started Jun 21 04:42:31 PM PDT 24
Finished Jun 21 04:42:38 PM PDT 24
Peak memory 205796 kb
Host smart-227e401e-d804-4689-92c3-512967d1c60b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2422969100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2422969100
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1218485329
Short name T2520
Test name
Test status
Simulation time 40108352 ps
CPU time 0.75 seconds
Started Jun 21 04:42:40 PM PDT 24
Finished Jun 21 04:42:42 PM PDT 24
Peak memory 204940 kb
Host smart-129fc2f5-0670-4ac4-ab3f-e5f38e2e0db3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1218485329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1218485329
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3780227939
Short name T2571
Test name
Test status
Simulation time 35243400 ps
CPU time 0.66 seconds
Started Jun 21 04:42:50 PM PDT 24
Finished Jun 21 04:42:53 PM PDT 24
Peak memory 205784 kb
Host smart-e94fabad-a50f-47fb-a846-37da5379fb41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3780227939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3780227939
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2402656056
Short name T2569
Test name
Test status
Simulation time 381281476 ps
CPU time 3.85 seconds
Started Jun 21 04:42:21 PM PDT 24
Finished Jun 21 04:42:27 PM PDT 24
Peak memory 205236 kb
Host smart-b6240936-f906-456f-a412-90a6b8ef0a80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2402656056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2402656056
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1964291134
Short name T2533
Test name
Test status
Simulation time 904542672 ps
CPU time 6.67 seconds
Started Jun 21 04:42:38 PM PDT 24
Finished Jun 21 04:42:46 PM PDT 24
Peak memory 206128 kb
Host smart-03abdbe9-4a58-430a-b510-3e0e643be11b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1964291134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1964291134
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3856566562
Short name T2516
Test name
Test status
Simulation time 130900666 ps
CPU time 0.84 seconds
Started Jun 21 04:42:32 PM PDT 24
Finished Jun 21 04:42:35 PM PDT 24
Peak memory 205080 kb
Host smart-466ae3ac-4080-4caf-aec8-ecc3159fd8ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3856566562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3856566562
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2261306402
Short name T2551
Test name
Test status
Simulation time 216082398 ps
CPU time 1.93 seconds
Started Jun 21 04:43:00 PM PDT 24
Finished Jun 21 04:43:04 PM PDT 24
Peak memory 214256 kb
Host smart-d37cc91c-290b-48d4-80d5-ad5335849ae7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261306402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2261306402
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.460128151
Short name T2585
Test name
Test status
Simulation time 69109814 ps
CPU time 0.93 seconds
Started Jun 21 04:42:43 PM PDT 24
Finished Jun 21 04:42:45 PM PDT 24
Peak memory 206152 kb
Host smart-b0969d67-ebef-4cd7-8e57-5d8b8765de98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=460128151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.460128151
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.626186713
Short name T282
Test name
Test status
Simulation time 43275903 ps
CPU time 0.72 seconds
Started Jun 21 04:42:30 PM PDT 24
Finished Jun 21 04:42:33 PM PDT 24
Peak memory 204436 kb
Host smart-62214863-26bb-4647-bc07-d0bba8ad7955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=626186713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.626186713
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3103436882
Short name T247
Test name
Test status
Simulation time 186394835 ps
CPU time 1.45 seconds
Started Jun 21 04:42:31 PM PDT 24
Finished Jun 21 04:42:34 PM PDT 24
Peak memory 213480 kb
Host smart-25097d0b-9d22-42db-8c4c-361a37b3a8a6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3103436882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3103436882
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2707203493
Short name T2509
Test name
Test status
Simulation time 480357205 ps
CPU time 4.09 seconds
Started Jun 21 04:42:33 PM PDT 24
Finished Jun 21 04:42:39 PM PDT 24
Peak memory 205260 kb
Host smart-6056b02c-9164-44d4-8658-5b70ac2b1102
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2707203493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2707203493
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3536876152
Short name T2557
Test name
Test status
Simulation time 98990246 ps
CPU time 1.12 seconds
Started Jun 21 04:42:24 PM PDT 24
Finished Jun 21 04:42:28 PM PDT 24
Peak memory 206128 kb
Host smart-b1dde582-5ae8-488d-92de-37dc5376464f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3536876152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3536876152
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.686840089
Short name T199
Test name
Test status
Simulation time 56697799 ps
CPU time 1.53 seconds
Started Jun 21 04:42:45 PM PDT 24
Finished Jun 21 04:42:48 PM PDT 24
Peak memory 206336 kb
Host smart-5f905d53-f61c-4133-8bd5-2af75e191f15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=686840089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.686840089
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1412796188
Short name T228
Test name
Test status
Simulation time 919774296 ps
CPU time 5.25 seconds
Started Jun 21 04:42:21 PM PDT 24
Finished Jun 21 04:42:28 PM PDT 24
Peak memory 206000 kb
Host smart-e206e08e-a21d-4475-888a-169773891f20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1412796188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1412796188
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1715196316
Short name T2568
Test name
Test status
Simulation time 67548340 ps
CPU time 0.68 seconds
Started Jun 21 04:42:41 PM PDT 24
Finished Jun 21 04:42:42 PM PDT 24
Peak memory 205792 kb
Host smart-27c8ca2f-8a2b-4fba-b800-6592018344b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1715196316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1715196316
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3059669352
Short name T2586
Test name
Test status
Simulation time 45349216 ps
CPU time 0.71 seconds
Started Jun 21 04:43:06 PM PDT 24
Finished Jun 21 04:43:10 PM PDT 24
Peak memory 205800 kb
Host smart-ef773ea1-f206-4bf7-b598-685a76872c2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3059669352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3059669352
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1917377910
Short name T284
Test name
Test status
Simulation time 93310818 ps
CPU time 0.73 seconds
Started Jun 21 04:43:04 PM PDT 24
Finished Jun 21 04:43:06 PM PDT 24
Peak memory 205804 kb
Host smart-032b993e-e7e6-4d9d-816e-5a218c3931c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1917377910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1917377910
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2597366426
Short name T270
Test name
Test status
Simulation time 32367768 ps
CPU time 0.7 seconds
Started Jun 21 04:42:42 PM PDT 24
Finished Jun 21 04:42:44 PM PDT 24
Peak memory 205804 kb
Host smart-cc9a2c5c-572b-4d29-a674-0c2b025fefca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2597366426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2597366426
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.11840042
Short name T2576
Test name
Test status
Simulation time 45289925 ps
CPU time 0.7 seconds
Started Jun 21 04:43:12 PM PDT 24
Finished Jun 21 04:43:17 PM PDT 24
Peak memory 205800 kb
Host smart-0169464b-8917-43d7-8634-a18d6fdd0a53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=11840042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.11840042
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2015741673
Short name T2575
Test name
Test status
Simulation time 36693786 ps
CPU time 0.64 seconds
Started Jun 21 04:43:14 PM PDT 24
Finished Jun 21 04:43:19 PM PDT 24
Peak memory 205804 kb
Host smart-a1c0d39b-7e72-4f8e-a56d-3c9b7d90cd38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2015741673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2015741673
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1633572522
Short name T2535
Test name
Test status
Simulation time 38858364 ps
CPU time 0.73 seconds
Started Jun 21 04:42:55 PM PDT 24
Finished Jun 21 04:43:01 PM PDT 24
Peak memory 205432 kb
Host smart-54f45a37-11d7-474e-9855-1b1ee53901b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1633572522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1633572522
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1983362209
Short name T252
Test name
Test status
Simulation time 425866472 ps
CPU time 3.58 seconds
Started Jun 21 04:42:18 PM PDT 24
Finished Jun 21 04:42:23 PM PDT 24
Peak memory 206076 kb
Host smart-4e4972b1-dc6a-43fb-9656-de8ea4bf0b27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1983362209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1983362209
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.165508535
Short name T2540
Test name
Test status
Simulation time 2487555117 ps
CPU time 8.82 seconds
Started Jun 21 04:42:42 PM PDT 24
Finished Jun 21 04:42:52 PM PDT 24
Peak memory 206172 kb
Host smart-3d7f3c8f-cfb1-43d1-bf6f-122ad8cc5bf1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=165508535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.165508535
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3883201668
Short name T2525
Test name
Test status
Simulation time 68076602 ps
CPU time 0.81 seconds
Started Jun 21 04:42:34 PM PDT 24
Finished Jun 21 04:42:41 PM PDT 24
Peak memory 205920 kb
Host smart-32516c0f-3bf3-4e06-b9f3-e73f87241d90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3883201668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3883201668
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1321649997
Short name T2528
Test name
Test status
Simulation time 101686694 ps
CPU time 2.25 seconds
Started Jun 21 04:43:05 PM PDT 24
Finished Jun 21 04:43:09 PM PDT 24
Peak memory 214324 kb
Host smart-b8583573-efff-4b2e-85bb-5e84f43dab8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321649997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1321649997
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3926487992
Short name T2527
Test name
Test status
Simulation time 103764529 ps
CPU time 0.78 seconds
Started Jun 21 04:43:04 PM PDT 24
Finished Jun 21 04:43:07 PM PDT 24
Peak memory 205896 kb
Host smart-88cc59c7-ac0f-4d0f-a94c-e10cb9a994ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3926487992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3926487992
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3836498016
Short name T2518
Test name
Test status
Simulation time 29096878 ps
CPU time 0.67 seconds
Started Jun 21 04:42:31 PM PDT 24
Finished Jun 21 04:42:34 PM PDT 24
Peak memory 204952 kb
Host smart-4daf361b-a3f0-482f-98e2-bf50bcbd7b3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3836498016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3836498016
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3643263264
Short name T2529
Test name
Test status
Simulation time 63370091 ps
CPU time 1.38 seconds
Started Jun 21 04:42:24 PM PDT 24
Finished Jun 21 04:42:28 PM PDT 24
Peak memory 214036 kb
Host smart-68e3c712-de2a-4f02-81ca-5ec5b6b55cf8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3643263264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3643263264
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3399223733
Short name T2517
Test name
Test status
Simulation time 365048380 ps
CPU time 2.67 seconds
Started Jun 21 04:42:29 PM PDT 24
Finished Jun 21 04:42:33 PM PDT 24
Peak memory 206120 kb
Host smart-d3fd9fa5-2983-41f4-8a37-799c2566afb1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3399223733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3399223733
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2536721033
Short name T2536
Test name
Test status
Simulation time 98538535 ps
CPU time 1.17 seconds
Started Jun 21 04:42:58 PM PDT 24
Finished Jun 21 04:43:00 PM PDT 24
Peak memory 206180 kb
Host smart-b89de8a1-7232-4532-8407-e5afd799c282
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2536721033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2536721033
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3637779487
Short name T230
Test name
Test status
Simulation time 124470963 ps
CPU time 3 seconds
Started Jun 21 04:42:21 PM PDT 24
Finished Jun 21 04:42:25 PM PDT 24
Peak memory 205308 kb
Host smart-1f307d56-b863-4c47-a09a-8dd94f446aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3637779487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3637779487
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.203495779
Short name T291
Test name
Test status
Simulation time 789745796 ps
CPU time 4.77 seconds
Started Jun 21 04:42:51 PM PDT 24
Finished Jun 21 04:42:58 PM PDT 24
Peak memory 206120 kb
Host smart-c85fa260-fffa-4a1e-8807-341ba8aab978
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=203495779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.203495779
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3291238552
Short name T268
Test name
Test status
Simulation time 41589059 ps
CPU time 0.68 seconds
Started Jun 21 04:43:04 PM PDT 24
Finished Jun 21 04:43:07 PM PDT 24
Peak memory 205800 kb
Host smart-f9161403-79c6-46b6-ae6d-f97c0248626f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3291238552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3291238552
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1835154889
Short name T206
Test name
Test status
Simulation time 95877568 ps
CPU time 0.72 seconds
Started Jun 21 04:43:18 PM PDT 24
Finished Jun 21 04:43:23 PM PDT 24
Peak memory 205800 kb
Host smart-a252c8f2-fc34-46e2-9cc3-aed4201e93c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1835154889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1835154889
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1244277439
Short name T276
Test name
Test status
Simulation time 48167422 ps
CPU time 0.7 seconds
Started Jun 21 04:43:04 PM PDT 24
Finished Jun 21 04:43:07 PM PDT 24
Peak memory 205800 kb
Host smart-82239770-99b8-4ba5-b32e-73e515d856d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1244277439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1244277439
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.920814787
Short name T272
Test name
Test status
Simulation time 45161527 ps
CPU time 0.68 seconds
Started Jun 21 04:43:11 PM PDT 24
Finished Jun 21 04:43:15 PM PDT 24
Peak memory 205800 kb
Host smart-f9e56790-56a6-4eba-ba7e-4a211565e30e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=920814787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.920814787
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.4261532773
Short name T2514
Test name
Test status
Simulation time 49281818 ps
CPU time 0.75 seconds
Started Jun 21 04:42:45 PM PDT 24
Finished Jun 21 04:42:49 PM PDT 24
Peak memory 205800 kb
Host smart-16f11b13-0a38-4860-a58e-08250657a270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4261532773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.4261532773
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3773699545
Short name T2591
Test name
Test status
Simulation time 64067989 ps
CPU time 0.8 seconds
Started Jun 21 04:42:36 PM PDT 24
Finished Jun 21 04:42:38 PM PDT 24
Peak memory 204952 kb
Host smart-3e4837c9-6831-471f-9162-986a7bc5aa0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3773699545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.3773699545
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3340743273
Short name T2522
Test name
Test status
Simulation time 40023115 ps
CPU time 0.65 seconds
Started Jun 21 04:42:49 PM PDT 24
Finished Jun 21 04:42:51 PM PDT 24
Peak memory 205796 kb
Host smart-f5a509bd-285f-404a-811e-69d38f9834d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3340743273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3340743273
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2469544725
Short name T279
Test name
Test status
Simulation time 51069750 ps
CPU time 0.71 seconds
Started Jun 21 04:42:49 PM PDT 24
Finished Jun 21 04:42:53 PM PDT 24
Peak memory 205800 kb
Host smart-28f7042b-3ed3-4532-bbb0-2810bbad849f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2469544725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2469544725
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2502587687
Short name T2564
Test name
Test status
Simulation time 99283269 ps
CPU time 0.73 seconds
Started Jun 21 04:42:30 PM PDT 24
Finished Jun 21 04:42:37 PM PDT 24
Peak memory 205804 kb
Host smart-1d8706f3-0ffe-4f3f-bc18-517b6a5d41ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2502587687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2502587687
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2221775720
Short name T2598
Test name
Test status
Simulation time 37571720 ps
CPU time 0.71 seconds
Started Jun 21 04:42:43 PM PDT 24
Finished Jun 21 04:42:45 PM PDT 24
Peak memory 204952 kb
Host smart-59305bff-093c-48e1-a615-88ee20f9f1a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2221775720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2221775720
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.854041806
Short name T2581
Test name
Test status
Simulation time 244908967 ps
CPU time 1.91 seconds
Started Jun 21 04:42:42 PM PDT 24
Finished Jun 21 04:42:45 PM PDT 24
Peak memory 214328 kb
Host smart-68d16990-3f33-4a7f-a33d-927ba0295ef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854041806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.854041806
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1942902021
Short name T2539
Test name
Test status
Simulation time 60717908 ps
CPU time 0.86 seconds
Started Jun 21 04:42:42 PM PDT 24
Finished Jun 21 04:42:44 PM PDT 24
Peak memory 205896 kb
Host smart-a2ed0529-3be8-4213-bc6d-39986891f14c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1942902021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1942902021
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1003602262
Short name T2599
Test name
Test status
Simulation time 55583379 ps
CPU time 0.72 seconds
Started Jun 21 04:42:31 PM PDT 24
Finished Jun 21 04:42:33 PM PDT 24
Peak memory 204948 kb
Host smart-4415810e-9a92-4363-8355-e86dd3ae26a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1003602262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1003602262
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2787831583
Short name T2537
Test name
Test status
Simulation time 223851246 ps
CPU time 1.22 seconds
Started Jun 21 04:42:18 PM PDT 24
Finished Jun 21 04:42:20 PM PDT 24
Peak memory 206032 kb
Host smart-6addbc65-a000-4477-a6b7-1068ea461a9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2787831583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2787831583
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2337543866
Short name T233
Test name
Test status
Simulation time 80209864 ps
CPU time 1.44 seconds
Started Jun 21 04:42:34 PM PDT 24
Finished Jun 21 04:42:37 PM PDT 24
Peak memory 221712 kb
Host smart-20daf63b-9c4a-48ae-b604-65543230a5b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2337543866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2337543866
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2189733798
Short name T289
Test name
Test status
Simulation time 594286855 ps
CPU time 3.03 seconds
Started Jun 21 04:43:02 PM PDT 24
Finished Jun 21 04:43:07 PM PDT 24
Peak memory 206160 kb
Host smart-0560a291-d68b-4911-ad86-49d70bda000e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2189733798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2189733798
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2010934571
Short name T237
Test name
Test status
Simulation time 157404388 ps
CPU time 1.36 seconds
Started Jun 21 04:42:36 PM PDT 24
Finished Jun 21 04:42:38 PM PDT 24
Peak memory 214256 kb
Host smart-c87e7dc8-bba1-468b-8571-90ca11cfa1dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010934571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2010934571
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2389270881
Short name T221
Test name
Test status
Simulation time 75098503 ps
CPU time 0.9 seconds
Started Jun 21 04:43:04 PM PDT 24
Finished Jun 21 04:43:07 PM PDT 24
Peak memory 205896 kb
Host smart-de958728-8aeb-43db-a43b-ed5225ab6cb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2389270881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2389270881
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.90586821
Short name T2572
Test name
Test status
Simulation time 188366660 ps
CPU time 1.12 seconds
Started Jun 21 04:43:10 PM PDT 24
Finished Jun 21 04:43:16 PM PDT 24
Peak memory 206104 kb
Host smart-a569b6c1-0234-43e3-b73b-3845c7ec801b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=90586821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.90586821
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1182195957
Short name T2538
Test name
Test status
Simulation time 407206887 ps
CPU time 2.55 seconds
Started Jun 21 04:43:00 PM PDT 24
Finished Jun 21 04:43:05 PM PDT 24
Peak memory 206100 kb
Host smart-1396cfdd-ed21-4681-8e17-84f066616ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1182195957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1182195957
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2568431922
Short name T2524
Test name
Test status
Simulation time 129300154 ps
CPU time 1.74 seconds
Started Jun 21 04:42:36 PM PDT 24
Finished Jun 21 04:42:39 PM PDT 24
Peak memory 214324 kb
Host smart-134cbb90-f05e-48d5-a8a6-b63156cc4b1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568431922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2568431922
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.199922634
Short name T2606
Test name
Test status
Simulation time 81491459 ps
CPU time 1 seconds
Started Jun 21 04:42:37 PM PDT 24
Finished Jun 21 04:42:40 PM PDT 24
Peak memory 206152 kb
Host smart-e3af10fc-b6f7-4f71-85c3-01ca82af8d9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=199922634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.199922634
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3147783041
Short name T267
Test name
Test status
Simulation time 45119921 ps
CPU time 0.68 seconds
Started Jun 21 04:42:31 PM PDT 24
Finished Jun 21 04:42:33 PM PDT 24
Peak memory 205592 kb
Host smart-421bf2f7-bb06-4883-9b22-80ee685c6fa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3147783041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3147783041
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.750887337
Short name T2588
Test name
Test status
Simulation time 242682026 ps
CPU time 1.31 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:43:33 PM PDT 24
Peak memory 206108 kb
Host smart-bc26682f-547c-4799-9e22-70bafc89676b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=750887337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.750887337
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1368947192
Short name T2548
Test name
Test status
Simulation time 264801981 ps
CPU time 2.97 seconds
Started Jun 21 04:42:59 PM PDT 24
Finished Jun 21 04:43:05 PM PDT 24
Peak memory 221924 kb
Host smart-5936585c-ae4e-475b-8d94-ff2aa1dd6001
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1368947192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1368947192
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1949010035
Short name T2508
Test name
Test status
Simulation time 115031358 ps
CPU time 2.33 seconds
Started Jun 21 04:42:25 PM PDT 24
Finished Jun 21 04:42:30 PM PDT 24
Peak memory 214184 kb
Host smart-99f3f849-b3b3-442b-bdca-eee0464e14f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949010035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1949010035
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.996144580
Short name T257
Test name
Test status
Simulation time 61358520 ps
CPU time 0.99 seconds
Started Jun 21 04:43:01 PM PDT 24
Finished Jun 21 04:43:04 PM PDT 24
Peak memory 206120 kb
Host smart-a34ae4ab-f909-43cc-88a7-9ef2ebb41119
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=996144580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.996144580
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1980517283
Short name T2582
Test name
Test status
Simulation time 32794927 ps
CPU time 0.65 seconds
Started Jun 21 04:42:31 PM PDT 24
Finished Jun 21 04:42:33 PM PDT 24
Peak memory 205640 kb
Host smart-2bd62156-339e-4e56-84cf-40ca141f239e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1980517283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1980517283
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3685399010
Short name T2515
Test name
Test status
Simulation time 104841387 ps
CPU time 1.45 seconds
Started Jun 21 04:42:24 PM PDT 24
Finished Jun 21 04:42:28 PM PDT 24
Peak memory 204544 kb
Host smart-fd91682e-7731-4b94-a93d-bf80d233d6fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3685399010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3685399010
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3618662370
Short name T2546
Test name
Test status
Simulation time 66975712 ps
CPU time 1.55 seconds
Started Jun 21 04:42:32 PM PDT 24
Finished Jun 21 04:42:35 PM PDT 24
Peak memory 205264 kb
Host smart-e0cd6805-294f-44ff-acab-f0588bc6cf9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3618662370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3618662370
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.346035770
Short name T2590
Test name
Test status
Simulation time 290231459 ps
CPU time 2.41 seconds
Started Jun 21 04:42:24 PM PDT 24
Finished Jun 21 04:42:29 PM PDT 24
Peak memory 204492 kb
Host smart-6d40c496-669a-4c6d-8b4e-ff320c10394c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=346035770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.346035770
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.653240419
Short name T202
Test name
Test status
Simulation time 202867503 ps
CPU time 1.78 seconds
Started Jun 21 04:42:35 PM PDT 24
Finished Jun 21 04:42:38 PM PDT 24
Peak memory 213996 kb
Host smart-c1bcbff0-4278-4e2f-8d2a-1bf4f52a0457
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653240419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.653240419
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1696294769
Short name T261
Test name
Test status
Simulation time 57306121 ps
CPU time 0.85 seconds
Started Jun 21 04:42:24 PM PDT 24
Finished Jun 21 04:42:27 PM PDT 24
Peak memory 205100 kb
Host smart-00e6a481-6050-4b05-bb5f-a5c92f016115
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1696294769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1696294769
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.202010523
Short name T283
Test name
Test status
Simulation time 53585406 ps
CPU time 0.75 seconds
Started Jun 21 04:42:46 PM PDT 24
Finished Jun 21 04:42:49 PM PDT 24
Peak memory 204948 kb
Host smart-6d51374b-74d7-42e1-ab40-9be2ddb1099e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=202010523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.202010523
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1074994668
Short name T2579
Test name
Test status
Simulation time 77266514 ps
CPU time 1.33 seconds
Started Jun 21 04:43:09 PM PDT 24
Finished Jun 21 04:43:14 PM PDT 24
Peak memory 206116 kb
Host smart-f3ca1911-55de-48e0-b52b-6e8ee6440f1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1074994668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1074994668
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.260134049
Short name T198
Test name
Test status
Simulation time 172535603 ps
CPU time 1.61 seconds
Started Jun 21 04:43:08 PM PDT 24
Finished Jun 21 04:43:19 PM PDT 24
Peak memory 214352 kb
Host smart-f1902f44-2e19-4a14-b0d3-43a73fa8adc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=260134049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.260134049
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.705533615
Short name T1118
Test name
Test status
Simulation time 3722559328 ps
CPU time 4.97 seconds
Started Jun 21 04:53:04 PM PDT 24
Finished Jun 21 04:53:10 PM PDT 24
Peak memory 206348 kb
Host smart-04511fb8-156a-4315-a9b2-3de058ca6d36
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=705533615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.705533615
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.1411030832
Short name T1030
Test name
Test status
Simulation time 13470107571 ps
CPU time 15.37 seconds
Started Jun 21 04:53:03 PM PDT 24
Finished Jun 21 04:53:20 PM PDT 24
Peak memory 206200 kb
Host smart-3ac2f4be-40b9-4074-bf21-dfdc9d70bbd2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1411030832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.1411030832
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.821821296
Short name T445
Test name
Test status
Simulation time 23347570895 ps
CPU time 27.91 seconds
Started Jun 21 04:53:04 PM PDT 24
Finished Jun 21 04:53:34 PM PDT 24
Peak memory 206332 kb
Host smart-64fab775-6b12-4a65-b2b7-c9b9026ff2fc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=821821296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.821821296
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3854146868
Short name T1930
Test name
Test status
Simulation time 155597802 ps
CPU time 0.83 seconds
Started Jun 21 04:53:04 PM PDT 24
Finished Jun 21 04:53:05 PM PDT 24
Peak memory 206028 kb
Host smart-7c92989e-4c1f-45cc-aed5-ce312a4fd073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38541
46868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3854146868
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.3116505643
Short name T1391
Test name
Test status
Simulation time 160226876 ps
CPU time 0.75 seconds
Started Jun 21 04:53:07 PM PDT 24
Finished Jun 21 04:53:09 PM PDT 24
Peak memory 205968 kb
Host smart-67163519-e16f-46f2-91aa-1fe1a0579208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31165
05643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.3116505643
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.2918268419
Short name T183
Test name
Test status
Simulation time 426996532 ps
CPU time 1.31 seconds
Started Jun 21 04:53:06 PM PDT 24
Finished Jun 21 04:53:09 PM PDT 24
Peak memory 205928 kb
Host smart-8a0f7026-25f3-4c37-a60b-18eaba119786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29182
68419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.2918268419
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_device_address.2805045065
Short name T1849
Test name
Test status
Simulation time 15776060296 ps
CPU time 30.41 seconds
Started Jun 21 04:53:05 PM PDT 24
Finished Jun 21 04:53:37 PM PDT 24
Peak memory 206212 kb
Host smart-5d30418d-f1de-45e8-b584-e1e200e4123a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28050
45065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.2805045065
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.2649505493
Short name T1012
Test name
Test status
Simulation time 378959209 ps
CPU time 1.26 seconds
Started Jun 21 04:53:05 PM PDT 24
Finished Jun 21 04:53:08 PM PDT 24
Peak memory 205968 kb
Host smart-f08f5586-f8dc-493c-b3c0-353a26113751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26495
05493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.2649505493
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.246752361
Short name T1995
Test name
Test status
Simulation time 141381455 ps
CPU time 0.75 seconds
Started Jun 21 04:53:05 PM PDT 24
Finished Jun 21 04:53:07 PM PDT 24
Peak memory 205984 kb
Host smart-125b79c8-8d16-400f-ac87-2615f3be1fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24675
2361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.246752361
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.505706243
Short name T1465
Test name
Test status
Simulation time 5108587105 ps
CPU time 41.22 seconds
Started Jun 21 04:53:06 PM PDT 24
Finished Jun 21 04:53:49 PM PDT 24
Peak memory 206224 kb
Host smart-103030d5-0951-40a2-89ec-b07ecbc91537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50570
6243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.505706243
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.154288079
Short name T2136
Test name
Test status
Simulation time 96146980 ps
CPU time 0.73 seconds
Started Jun 21 04:53:04 PM PDT 24
Finished Jun 21 04:53:06 PM PDT 24
Peak memory 205920 kb
Host smart-9a52e5b2-79bc-49d5-89c7-b170b9ac6979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15428
8079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.154288079
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.2419462452
Short name T389
Test name
Test status
Simulation time 931450008 ps
CPU time 2.13 seconds
Started Jun 21 04:53:04 PM PDT 24
Finished Jun 21 04:53:07 PM PDT 24
Peak memory 206256 kb
Host smart-260bac53-42a6-4cca-be61-bb26c678ee9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24194
62452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.2419462452
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.570451730
Short name T1737
Test name
Test status
Simulation time 221580705 ps
CPU time 1.26 seconds
Started Jun 21 04:53:05 PM PDT 24
Finished Jun 21 04:53:07 PM PDT 24
Peak memory 206284 kb
Host smart-48f368ab-4738-4421-984e-d04cf3c2685d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57045
1730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.570451730
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.346461162
Short name T2025
Test name
Test status
Simulation time 203698444 ps
CPU time 0.85 seconds
Started Jun 21 04:53:26 PM PDT 24
Finished Jun 21 04:53:28 PM PDT 24
Peak memory 205964 kb
Host smart-c16f0303-5e21-4ff2-b940-ccb6593132fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34646
1162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.346461162
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.520681873
Short name T2062
Test name
Test status
Simulation time 173665108 ps
CPU time 0.81 seconds
Started Jun 21 04:53:26 PM PDT 24
Finished Jun 21 04:53:29 PM PDT 24
Peak memory 205956 kb
Host smart-e38a36ca-e9d9-4518-8baf-36ce8a8ac29b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52068
1873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.520681873
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2527369060
Short name T1834
Test name
Test status
Simulation time 225536180 ps
CPU time 0.89 seconds
Started Jun 21 04:53:06 PM PDT 24
Finished Jun 21 04:53:09 PM PDT 24
Peak memory 206028 kb
Host smart-3677addf-f4fa-4246-a7cd-2eee6aa7a8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25273
69060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2527369060
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.407377600
Short name T2019
Test name
Test status
Simulation time 4943566961 ps
CPU time 139.29 seconds
Started Jun 21 04:53:04 PM PDT 24
Finished Jun 21 04:55:24 PM PDT 24
Peak memory 206264 kb
Host smart-b4f7378b-6823-48cf-9a51-d9e813b358e7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=407377600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.407377600
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3168405461
Short name T689
Test name
Test status
Simulation time 229444450 ps
CPU time 0.9 seconds
Started Jun 21 04:53:05 PM PDT 24
Finished Jun 21 04:53:07 PM PDT 24
Peak memory 205968 kb
Host smart-d1d81453-398c-4f71-8b4b-0700f09b4c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31684
05461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3168405461
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.4040039092
Short name T68
Test name
Test status
Simulation time 452222448 ps
CPU time 1.33 seconds
Started Jun 21 04:53:07 PM PDT 24
Finished Jun 21 04:53:09 PM PDT 24
Peak memory 205964 kb
Host smart-6ea11e2d-794c-4c8f-a5ad-126eedc45f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40400
39092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.4040039092
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.3240213525
Short name T2299
Test name
Test status
Simulation time 23345258171 ps
CPU time 22.89 seconds
Started Jun 21 04:53:08 PM PDT 24
Finished Jun 21 04:53:32 PM PDT 24
Peak memory 206028 kb
Host smart-359c4f71-9e6b-4c0e-9e91-19c3c37a5e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32402
13525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.3240213525
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.2257261674
Short name T1435
Test name
Test status
Simulation time 3289927068 ps
CPU time 3.63 seconds
Started Jun 21 04:53:04 PM PDT 24
Finished Jun 21 04:53:08 PM PDT 24
Peak memory 206040 kb
Host smart-0f79ae34-9ac6-4f07-8245-95368d145d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22572
61674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.2257261674
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.1055032625
Short name T443
Test name
Test status
Simulation time 4200726988 ps
CPU time 30.14 seconds
Started Jun 21 04:53:12 PM PDT 24
Finished Jun 21 04:53:43 PM PDT 24
Peak memory 206232 kb
Host smart-7f05c70f-e896-468e-ae33-29c5c864a869
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1055032625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.1055032625
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.3956177284
Short name T1062
Test name
Test status
Simulation time 308792612 ps
CPU time 1.01 seconds
Started Jun 21 04:53:19 PM PDT 24
Finished Jun 21 04:53:21 PM PDT 24
Peak memory 206028 kb
Host smart-c4916041-f1ae-4718-95f8-3a90cf6e5ad1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3956177284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.3956177284
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.4151489225
Short name T1332
Test name
Test status
Simulation time 188981714 ps
CPU time 0.83 seconds
Started Jun 21 04:53:04 PM PDT 24
Finished Jun 21 04:53:07 PM PDT 24
Peak memory 206008 kb
Host smart-f2bc2060-ed55-47b4-8224-bf987f3c3830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41514
89225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.4151489225
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2978987717
Short name T1232
Test name
Test status
Simulation time 5017345251 ps
CPU time 136.33 seconds
Started Jun 21 04:53:15 PM PDT 24
Finished Jun 21 04:55:33 PM PDT 24
Peak memory 206264 kb
Host smart-d6578614-6ae7-49c7-ad6b-f2ae99191551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29789
87717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2978987717
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.2500939121
Short name T2252
Test name
Test status
Simulation time 11075680333 ps
CPU time 105.72 seconds
Started Jun 21 04:53:12 PM PDT 24
Finished Jun 21 04:54:59 PM PDT 24
Peak memory 206276 kb
Host smart-db900640-d3d2-424c-b495-64be0a71f72c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2500939121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.2500939121
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1808869325
Short name T684
Test name
Test status
Simulation time 220153733 ps
CPU time 0.85 seconds
Started Jun 21 04:53:20 PM PDT 24
Finished Jun 21 04:53:22 PM PDT 24
Peak memory 205976 kb
Host smart-e1e3a9d5-3ba0-4fcf-ba2f-a42b059e8e14
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1808869325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1808869325
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.4078556052
Short name T2098
Test name
Test status
Simulation time 223982998 ps
CPU time 0.86 seconds
Started Jun 21 04:53:06 PM PDT 24
Finished Jun 21 04:53:09 PM PDT 24
Peak memory 206044 kb
Host smart-a742e4e2-247b-4fc2-9c27-15ad95410e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40785
56052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.4078556052
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1259947111
Short name T67
Test name
Test status
Simulation time 402995885 ps
CPU time 1.19 seconds
Started Jun 21 04:53:12 PM PDT 24
Finished Jun 21 04:53:13 PM PDT 24
Peak memory 205936 kb
Host smart-7de14d31-4f74-4864-ad6a-daec70e91f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12599
47111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1259947111
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3017699690
Short name T1870
Test name
Test status
Simulation time 142423845 ps
CPU time 0.77 seconds
Started Jun 21 04:53:12 PM PDT 24
Finished Jun 21 04:53:14 PM PDT 24
Peak memory 205948 kb
Host smart-a925b953-d59a-41ec-a14e-c4eb2cade087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30176
99690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3017699690
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.325630006
Short name T641
Test name
Test status
Simulation time 152109709 ps
CPU time 0.8 seconds
Started Jun 21 04:53:15 PM PDT 24
Finished Jun 21 04:53:17 PM PDT 24
Peak memory 205956 kb
Host smart-0e62066e-1ae0-4d8a-b991-80537c0eb519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32563
0006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.325630006
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.284784385
Short name T2132
Test name
Test status
Simulation time 180351124 ps
CPU time 0.8 seconds
Started Jun 21 04:53:13 PM PDT 24
Finished Jun 21 04:53:15 PM PDT 24
Peak memory 206048 kb
Host smart-e373ae95-22da-4e21-9086-1cfb35322957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28478
4385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.284784385
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3485999002
Short name T406
Test name
Test status
Simulation time 213983234 ps
CPU time 0.83 seconds
Started Jun 21 04:53:18 PM PDT 24
Finished Jun 21 04:53:19 PM PDT 24
Peak memory 206016 kb
Host smart-227969f6-cfe2-4377-a280-d24fcd31a732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34859
99002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3485999002
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.3732525071
Short name T631
Test name
Test status
Simulation time 255983296 ps
CPU time 0.94 seconds
Started Jun 21 04:53:19 PM PDT 24
Finished Jun 21 04:53:21 PM PDT 24
Peak memory 205964 kb
Host smart-1a422b9f-feb9-481e-8e01-8c971d934098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37325
25071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.3732525071
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.1230494972
Short name T2447
Test name
Test status
Simulation time 255562072 ps
CPU time 0.95 seconds
Started Jun 21 04:53:21 PM PDT 24
Finished Jun 21 04:53:23 PM PDT 24
Peak memory 206048 kb
Host smart-a6aaff97-c8bc-4ed4-9b5a-dd802e3c7005
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1230494972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.1230494972
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2981452884
Short name T853
Test name
Test status
Simulation time 146126406 ps
CPU time 0.77 seconds
Started Jun 21 04:53:19 PM PDT 24
Finished Jun 21 04:53:21 PM PDT 24
Peak memory 205984 kb
Host smart-9201efb9-6054-4ad3-9ec1-0c9ccb3ed399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29814
52884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2981452884
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.588982534
Short name T1664
Test name
Test status
Simulation time 64733347 ps
CPU time 0.66 seconds
Started Jun 21 04:53:21 PM PDT 24
Finished Jun 21 04:53:23 PM PDT 24
Peak memory 205968 kb
Host smart-da98c431-005a-4f81-b9fc-5819aa0ca8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58898
2534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.588982534
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.3440123422
Short name T587
Test name
Test status
Simulation time 156830557 ps
CPU time 0.84 seconds
Started Jun 21 04:53:13 PM PDT 24
Finished Jun 21 04:53:15 PM PDT 24
Peak memory 206036 kb
Host smart-52f0f605-3467-4fbe-b395-db1aaad01d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34401
23422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3440123422
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.827425395
Short name T2330
Test name
Test status
Simulation time 199322227 ps
CPU time 0.81 seconds
Started Jun 21 04:53:14 PM PDT 24
Finished Jun 21 04:53:17 PM PDT 24
Peak memory 205964 kb
Host smart-85eda97d-f334-4983-af46-01ca876101ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82742
5395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.827425395
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2896318685
Short name T1113
Test name
Test status
Simulation time 11753531593 ps
CPU time 330.11 seconds
Started Jun 21 04:53:14 PM PDT 24
Finished Jun 21 04:58:46 PM PDT 24
Peak memory 206292 kb
Host smart-5c7d5986-a4f5-4fdb-a1cf-0791bd6ad9cc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2896318685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2896318685
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.1695145420
Short name T1532
Test name
Test status
Simulation time 14843675031 ps
CPU time 105.54 seconds
Started Jun 21 04:53:12 PM PDT 24
Finished Jun 21 04:54:59 PM PDT 24
Peak memory 206264 kb
Host smart-ddbc1184-488a-479d-ab1d-e07b238d9142
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1695145420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.1695145420
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.72842508
Short name T1527
Test name
Test status
Simulation time 11984512087 ps
CPU time 236.32 seconds
Started Jun 21 04:53:14 PM PDT 24
Finished Jun 21 04:57:12 PM PDT 24
Peak memory 206220 kb
Host smart-34602a9b-5935-4775-bc0e-2abeea4cad37
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=72842508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.72842508
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.1509031640
Short name T1123
Test name
Test status
Simulation time 244652200 ps
CPU time 0.95 seconds
Started Jun 21 04:53:26 PM PDT 24
Finished Jun 21 04:53:29 PM PDT 24
Peak memory 205972 kb
Host smart-b504177a-7e2b-453c-9edb-265b8a57dfe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15090
31640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.1509031640
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.1304944494
Short name T2084
Test name
Test status
Simulation time 164192516 ps
CPU time 0.86 seconds
Started Jun 21 04:53:12 PM PDT 24
Finished Jun 21 04:53:14 PM PDT 24
Peak memory 206044 kb
Host smart-4238c788-8242-4402-b9ed-dc515a44f03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13049
44494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.1304944494
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.1446468640
Short name T2076
Test name
Test status
Simulation time 174163217 ps
CPU time 0.76 seconds
Started Jun 21 04:53:20 PM PDT 24
Finished Jun 21 04:53:22 PM PDT 24
Peak memory 206016 kb
Host smart-71045588-4bf2-4d54-bcbb-6dbff3ae6358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14464
68640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.1446468640
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.2349616238
Short name T1048
Test name
Test status
Simulation time 185076975 ps
CPU time 0.76 seconds
Started Jun 21 04:53:18 PM PDT 24
Finished Jun 21 04:53:19 PM PDT 24
Peak memory 205984 kb
Host smart-3effe9fa-f3ab-4e6a-b509-0018fd9c8b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23496
16238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.2349616238
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1005891914
Short name T1653
Test name
Test status
Simulation time 223144154 ps
CPU time 0.93 seconds
Started Jun 21 04:53:03 PM PDT 24
Finished Jun 21 04:53:05 PM PDT 24
Peak memory 206028 kb
Host smart-f7faf87c-71e4-4684-81cc-32523c1b7009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10058
91914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1005891914
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.792940355
Short name T1977
Test name
Test status
Simulation time 8042117452 ps
CPU time 222.66 seconds
Started Jun 21 04:53:15 PM PDT 24
Finished Jun 21 04:56:59 PM PDT 24
Peak memory 206220 kb
Host smart-6bc0cb49-4aae-4a1e-b4eb-f3a96de34ff2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=792940355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.792940355
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1418277059
Short name T452
Test name
Test status
Simulation time 190612357 ps
CPU time 0.87 seconds
Started Jun 21 04:53:20 PM PDT 24
Finished Jun 21 04:53:22 PM PDT 24
Peak memory 205928 kb
Host smart-793a4f98-d2bf-4b73-9daf-d772dbb2dc92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14182
77059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1418277059
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2682569576
Short name T544
Test name
Test status
Simulation time 162049110 ps
CPU time 0.78 seconds
Started Jun 21 04:53:13 PM PDT 24
Finished Jun 21 04:53:14 PM PDT 24
Peak memory 206020 kb
Host smart-9cb3223a-7c6e-4d9b-ad79-aa90a0bc7a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26825
69576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2682569576
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.2686710453
Short name T2192
Test name
Test status
Simulation time 14047167347 ps
CPU time 130.07 seconds
Started Jun 21 04:53:14 PM PDT 24
Finished Jun 21 04:55:25 PM PDT 24
Peak memory 206140 kb
Host smart-1131541c-3efb-403e-b5ee-234345443377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26867
10453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.2686710453
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.2756574673
Short name T1195
Test name
Test status
Simulation time 4045559323 ps
CPU time 5.14 seconds
Started Jun 21 04:53:22 PM PDT 24
Finished Jun 21 04:53:28 PM PDT 24
Peak memory 206212 kb
Host smart-2f78dcec-3756-406c-a5ac-088820b020f4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2756574673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.2756574673
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.926539704
Short name T2280
Test name
Test status
Simulation time 13376639983 ps
CPU time 12.15 seconds
Started Jun 21 04:53:26 PM PDT 24
Finished Jun 21 04:53:40 PM PDT 24
Peak memory 206092 kb
Host smart-f7ca43c9-0f6c-4c9b-bfaa-3771e9d5a70b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=926539704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.926539704
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.1621090908
Short name T1643
Test name
Test status
Simulation time 23295220731 ps
CPU time 24.57 seconds
Started Jun 21 04:53:29 PM PDT 24
Finished Jun 21 04:53:56 PM PDT 24
Peak memory 206088 kb
Host smart-c5060fce-55c2-488a-af5a-177fb07cd81a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1621090908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.1621090908
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3523044567
Short name T1846
Test name
Test status
Simulation time 175950146 ps
CPU time 0.84 seconds
Started Jun 21 04:53:27 PM PDT 24
Finished Jun 21 04:53:31 PM PDT 24
Peak memory 206012 kb
Host smart-14bc88a5-9a8c-4128-8bfe-bb724e69d42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35230
44567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3523044567
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.2643122352
Short name T2307
Test name
Test status
Simulation time 206552136 ps
CPU time 0.84 seconds
Started Jun 21 04:53:27 PM PDT 24
Finished Jun 21 04:53:31 PM PDT 24
Peak memory 205968 kb
Host smart-1a720731-6599-4e0b-8f31-d4e205d62d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26431
22352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2643122352
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.1216934023
Short name T977
Test name
Test status
Simulation time 528422172 ps
CPU time 1.53 seconds
Started Jun 21 04:53:27 PM PDT 24
Finished Jun 21 04:53:31 PM PDT 24
Peak memory 206220 kb
Host smart-9656d030-3548-4e27-9f84-f12c1aaca716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12169
34023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.1216934023
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1901956677
Short name T2242
Test name
Test status
Simulation time 820592371 ps
CPU time 2.02 seconds
Started Jun 21 04:53:26 PM PDT 24
Finished Jun 21 04:53:30 PM PDT 24
Peak memory 206208 kb
Host smart-dd9b7323-b8eb-4ff7-85cf-b8169e72e9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19019
56677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1901956677
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.2838507268
Short name T1252
Test name
Test status
Simulation time 15877240929 ps
CPU time 30.11 seconds
Started Jun 21 04:53:28 PM PDT 24
Finished Jun 21 04:54:01 PM PDT 24
Peak memory 206260 kb
Host smart-2faf4704-280b-45e6-9915-88a49795c536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28385
07268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2838507268
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2411985526
Short name T2322
Test name
Test status
Simulation time 421777531 ps
CPU time 1.19 seconds
Started Jun 21 04:53:29 PM PDT 24
Finished Jun 21 04:53:33 PM PDT 24
Peak memory 205956 kb
Host smart-7fcfd812-4a9f-4acd-befb-55f452578189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24119
85526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2411985526
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.1778770620
Short name T2361
Test name
Test status
Simulation time 140606488 ps
CPU time 0.82 seconds
Started Jun 21 04:53:29 PM PDT 24
Finished Jun 21 04:53:32 PM PDT 24
Peak memory 205924 kb
Host smart-4854efab-8b65-4efe-a954-9cca0e48ad0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17787
70620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.1778770620
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.2743067267
Short name T2074
Test name
Test status
Simulation time 78111098 ps
CPU time 0.69 seconds
Started Jun 21 04:53:29 PM PDT 24
Finished Jun 21 04:53:32 PM PDT 24
Peak memory 206136 kb
Host smart-5d3b3b3a-c1ec-4485-9df6-81572af1b2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27430
67267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2743067267
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.2508418399
Short name T1645
Test name
Test status
Simulation time 783846129 ps
CPU time 1.94 seconds
Started Jun 21 04:53:27 PM PDT 24
Finished Jun 21 04:53:32 PM PDT 24
Peak memory 206212 kb
Host smart-9a59ad09-beac-452d-a838-fa71c0d8b309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25084
18399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.2508418399
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1746487245
Short name T579
Test name
Test status
Simulation time 486272100 ps
CPU time 2.68 seconds
Started Jun 21 04:53:27 PM PDT 24
Finished Jun 21 04:53:31 PM PDT 24
Peak memory 206196 kb
Host smart-7be759b0-d25b-4e50-87a5-fc2ba4c44f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17464
87245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1746487245
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.1590181947
Short name T884
Test name
Test status
Simulation time 247099431 ps
CPU time 0.94 seconds
Started Jun 21 04:53:46 PM PDT 24
Finished Jun 21 04:53:48 PM PDT 24
Peak memory 206004 kb
Host smart-63078075-6c48-4485-8aef-dd7c70ab7def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15901
81947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1590181947
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3279343508
Short name T979
Test name
Test status
Simulation time 140963130 ps
CPU time 0.72 seconds
Started Jun 21 04:53:47 PM PDT 24
Finished Jun 21 04:53:49 PM PDT 24
Peak memory 205972 kb
Host smart-981b6fbd-f388-4eae-b272-376173b52f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32793
43508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3279343508
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2336180125
Short name T463
Test name
Test status
Simulation time 241566678 ps
CPU time 0.94 seconds
Started Jun 21 04:53:27 PM PDT 24
Finished Jun 21 04:53:31 PM PDT 24
Peak memory 205976 kb
Host smart-b0e0c86a-1fef-4b4a-8ad4-2a17cc5f311a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23361
80125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2336180125
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.1924514184
Short name T2234
Test name
Test status
Simulation time 244562362 ps
CPU time 0.85 seconds
Started Jun 21 04:53:29 PM PDT 24
Finished Jun 21 04:53:33 PM PDT 24
Peak memory 205948 kb
Host smart-2c402860-540a-44bc-acf8-d03575258226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19245
14184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.1924514184
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.3167669362
Short name T1505
Test name
Test status
Simulation time 23343277750 ps
CPU time 29.48 seconds
Started Jun 21 04:53:28 PM PDT 24
Finished Jun 21 04:54:01 PM PDT 24
Peak memory 206032 kb
Host smart-9a2c0fdf-0322-409b-8705-5958df3554e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31676
69362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.3167669362
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1674105753
Short name T1050
Test name
Test status
Simulation time 3298878610 ps
CPU time 4.2 seconds
Started Jun 21 04:53:28 PM PDT 24
Finished Jun 21 04:53:36 PM PDT 24
Peak memory 206088 kb
Host smart-faa51aa8-ceaa-42c0-9b02-a827f2cce7a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16741
05753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1674105753
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1768024102
Short name T491
Test name
Test status
Simulation time 8597764212 ps
CPU time 68.09 seconds
Started Jun 21 04:53:37 PM PDT 24
Finished Jun 21 04:54:47 PM PDT 24
Peak memory 206264 kb
Host smart-23af8260-53fd-4d29-a74d-15465ddc21b8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1768024102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.1768024102
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.1049910728
Short name T914
Test name
Test status
Simulation time 308749139 ps
CPU time 0.95 seconds
Started Jun 21 04:53:46 PM PDT 24
Finished Jun 21 04:53:49 PM PDT 24
Peak memory 206052 kb
Host smart-4584df73-ceb2-452e-a7cf-4135654c9c99
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1049910728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.1049910728
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1774937255
Short name T1593
Test name
Test status
Simulation time 194072548 ps
CPU time 0.85 seconds
Started Jun 21 04:53:26 PM PDT 24
Finished Jun 21 04:53:28 PM PDT 24
Peak memory 206000 kb
Host smart-492cdb7e-7511-4b26-950a-5fb73df3cd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17749
37255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1774937255
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.1464907349
Short name T1206
Test name
Test status
Simulation time 4366099028 ps
CPU time 40.63 seconds
Started Jun 21 04:53:37 PM PDT 24
Finished Jun 21 04:54:20 PM PDT 24
Peak memory 206252 kb
Host smart-fa37d6fe-32c0-46bb-9b0e-6640510fa8b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14649
07349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.1464907349
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.2992960299
Short name T1445
Test name
Test status
Simulation time 14080840617 ps
CPU time 131.71 seconds
Started Jun 21 04:53:37 PM PDT 24
Finished Jun 21 04:55:50 PM PDT 24
Peak memory 206364 kb
Host smart-1384bada-cbba-4286-9402-3199b8d5708c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2992960299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.2992960299
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.2327044088
Short name T354
Test name
Test status
Simulation time 176640048 ps
CPU time 0.79 seconds
Started Jun 21 04:53:46 PM PDT 24
Finished Jun 21 04:53:49 PM PDT 24
Peak memory 206048 kb
Host smart-b555a9ca-d83d-41ff-8b78-2dccb50acf8c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2327044088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.2327044088
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.967806311
Short name T1441
Test name
Test status
Simulation time 206390487 ps
CPU time 0.84 seconds
Started Jun 21 04:53:36 PM PDT 24
Finished Jun 21 04:53:38 PM PDT 24
Peak memory 206148 kb
Host smart-b8acbaab-808e-4e2c-b8a6-595dd0678c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96780
6311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.967806311
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3920580998
Short name T1660
Test name
Test status
Simulation time 216153357 ps
CPU time 0.88 seconds
Started Jun 21 04:53:35 PM PDT 24
Finished Jun 21 04:53:37 PM PDT 24
Peak memory 206024 kb
Host smart-64214ef2-d5e9-4e28-b9ae-008bbc9dbff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39205
80998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3920580998
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.1743324305
Short name T1673
Test name
Test status
Simulation time 225662357 ps
CPU time 0.83 seconds
Started Jun 21 04:53:40 PM PDT 24
Finished Jun 21 04:53:42 PM PDT 24
Peak memory 205968 kb
Host smart-8148b840-ff17-40aa-8f82-de5c4cbf9bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17433
24305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.1743324305
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1445117360
Short name T2235
Test name
Test status
Simulation time 185310538 ps
CPU time 0.84 seconds
Started Jun 21 04:53:35 PM PDT 24
Finished Jun 21 04:53:37 PM PDT 24
Peak memory 205972 kb
Host smart-9419c552-ae8f-4822-b05f-ba14ba58097d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14451
17360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1445117360
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1745897258
Short name T2328
Test name
Test status
Simulation time 156344088 ps
CPU time 0.76 seconds
Started Jun 21 04:53:47 PM PDT 24
Finished Jun 21 04:53:49 PM PDT 24
Peak memory 206024 kb
Host smart-6b05953a-b1b4-4e63-96d9-922c4905eb16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17458
97258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1745897258
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.3426243322
Short name T1434
Test name
Test status
Simulation time 216787411 ps
CPU time 0.91 seconds
Started Jun 21 04:53:46 PM PDT 24
Finished Jun 21 04:53:49 PM PDT 24
Peak memory 206048 kb
Host smart-0191cd56-ada3-4346-8712-5ed25997a5de
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3426243322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.3426243322
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3167647990
Short name T2387
Test name
Test status
Simulation time 147445858 ps
CPU time 0.77 seconds
Started Jun 21 04:53:45 PM PDT 24
Finished Jun 21 04:53:47 PM PDT 24
Peak memory 205956 kb
Host smart-c8a9ca6f-8254-4d02-86f8-ea879c67b5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31676
47990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3167647990
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.370581457
Short name T2356
Test name
Test status
Simulation time 58999802 ps
CPU time 0.68 seconds
Started Jun 21 04:53:47 PM PDT 24
Finished Jun 21 04:53:49 PM PDT 24
Peak memory 206024 kb
Host smart-97268dde-d8fe-4932-aa0f-5b681c56b0c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37058
1457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.370581457
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2586567626
Short name T1292
Test name
Test status
Simulation time 18518537119 ps
CPU time 42.48 seconds
Started Jun 21 04:53:35 PM PDT 24
Finished Jun 21 04:54:19 PM PDT 24
Peak memory 206284 kb
Host smart-7689de2c-7a39-4798-bd98-bffa0a8e7015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25865
67626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2586567626
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.296439166
Short name T1952
Test name
Test status
Simulation time 183025257 ps
CPU time 0.81 seconds
Started Jun 21 04:53:36 PM PDT 24
Finished Jun 21 04:53:38 PM PDT 24
Peak memory 205968 kb
Host smart-f350465f-8e72-45b6-89f9-41046539c3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29643
9166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.296439166
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1748143605
Short name T394
Test name
Test status
Simulation time 246116461 ps
CPU time 0.87 seconds
Started Jun 21 04:53:40 PM PDT 24
Finished Jun 21 04:53:42 PM PDT 24
Peak memory 205964 kb
Host smart-54513f33-d5e0-4b73-a361-4bc362676705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17481
43605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1748143605
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2490793606
Short name T1926
Test name
Test status
Simulation time 15350206074 ps
CPU time 327.08 seconds
Started Jun 21 04:53:36 PM PDT 24
Finished Jun 21 04:59:04 PM PDT 24
Peak memory 206308 kb
Host smart-347c0331-6747-4fe7-9e9e-70923637539f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2490793606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2490793606
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2472591275
Short name T1487
Test name
Test status
Simulation time 19711982090 ps
CPU time 539.98 seconds
Started Jun 21 04:53:46 PM PDT 24
Finished Jun 21 05:02:47 PM PDT 24
Peak memory 206292 kb
Host smart-0ffba5ee-a1b9-4f2c-a6b6-6586974afa23
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2472591275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2472591275
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.2447147967
Short name T2433
Test name
Test status
Simulation time 35454238987 ps
CPU time 925.86 seconds
Started Jun 21 04:53:46 PM PDT 24
Finished Jun 21 05:09:13 PM PDT 24
Peak memory 206220 kb
Host smart-51d16603-97d7-43fa-a5c6-48183dc74dd9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2447147967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.2447147967
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3143256899
Short name T1474
Test name
Test status
Simulation time 209537448 ps
CPU time 0.86 seconds
Started Jun 21 04:53:46 PM PDT 24
Finished Jun 21 04:53:49 PM PDT 24
Peak memory 206008 kb
Host smart-23ddf9a7-8a27-461a-9fe3-6aa3dbffbeab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31432
56899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3143256899
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.1087334873
Short name T1861
Test name
Test status
Simulation time 176176403 ps
CPU time 0.83 seconds
Started Jun 21 04:53:44 PM PDT 24
Finished Jun 21 04:53:46 PM PDT 24
Peak memory 206036 kb
Host smart-4b243cb8-4aef-4947-97af-d541260ba10b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10873
34873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.1087334873
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.2796986449
Short name T1025
Test name
Test status
Simulation time 151087026 ps
CPU time 0.78 seconds
Started Jun 21 04:53:46 PM PDT 24
Finished Jun 21 04:53:49 PM PDT 24
Peak memory 206148 kb
Host smart-c2009e6a-dd95-464c-8c8d-e0a6863899ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27969
86449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.2796986449
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.881816794
Short name T196
Test name
Test status
Simulation time 592615576 ps
CPU time 1.39 seconds
Started Jun 21 04:53:48 PM PDT 24
Finished Jun 21 04:53:51 PM PDT 24
Peak memory 223836 kb
Host smart-2920ef1d-47f8-4d10-83a6-29afd8f5b51d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=881816794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.881816794
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.2554710625
Short name T50
Test name
Test status
Simulation time 368234225 ps
CPU time 1.16 seconds
Started Jun 21 04:53:45 PM PDT 24
Finished Jun 21 04:53:47 PM PDT 24
Peak memory 206008 kb
Host smart-a1bfd79e-b86d-49bd-8870-c538e053df18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25547
10625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.2554710625
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2138463753
Short name T348
Test name
Test status
Simulation time 150508750 ps
CPU time 0.75 seconds
Started Jun 21 04:53:44 PM PDT 24
Finished Jun 21 04:53:46 PM PDT 24
Peak memory 206012 kb
Host smart-c08fca23-00ae-43d0-a951-901cd18a10ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21384
63753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2138463753
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1727386621
Short name T2293
Test name
Test status
Simulation time 164930100 ps
CPU time 0.82 seconds
Started Jun 21 04:53:44 PM PDT 24
Finished Jun 21 04:53:46 PM PDT 24
Peak memory 205984 kb
Host smart-3d737cf3-d01c-430f-bd52-6eb93baab7c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17273
86621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1727386621
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3250184321
Short name T1621
Test name
Test status
Simulation time 233342616 ps
CPU time 0.99 seconds
Started Jun 21 04:53:20 PM PDT 24
Finished Jun 21 04:53:22 PM PDT 24
Peak memory 206024 kb
Host smart-ce8fe926-0cda-47d6-9a52-e343ca49deb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32501
84321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3250184321
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.3462511430
Short name T297
Test name
Test status
Simulation time 12759659117 ps
CPU time 343.94 seconds
Started Jun 21 04:53:45 PM PDT 24
Finished Jun 21 04:59:31 PM PDT 24
Peak memory 206232 kb
Host smart-66097f38-dbbe-4305-8e52-ef3a423dc5ae
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3462511430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.3462511430
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2030635267
Short name T1615
Test name
Test status
Simulation time 208627244 ps
CPU time 0.81 seconds
Started Jun 21 04:53:46 PM PDT 24
Finished Jun 21 04:53:48 PM PDT 24
Peak memory 205968 kb
Host smart-43041e73-af9e-4e6c-a262-814e6a05917d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20306
35267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2030635267
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3225509494
Short name T2215
Test name
Test status
Simulation time 193311225 ps
CPU time 0.84 seconds
Started Jun 21 04:53:43 PM PDT 24
Finished Jun 21 04:53:45 PM PDT 24
Peak memory 205964 kb
Host smart-678a731d-3acb-43c1-8182-7441484b6983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32255
09494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3225509494
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.3929179343
Short name T356
Test name
Test status
Simulation time 14633911582 ps
CPU time 142.41 seconds
Started Jun 21 04:53:44 PM PDT 24
Finished Jun 21 04:56:07 PM PDT 24
Peak memory 206152 kb
Host smart-f721e293-a953-484c-8054-a4e114f747a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39291
79343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.3929179343
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.3437008670
Short name T1355
Test name
Test status
Simulation time 4050579660 ps
CPU time 4.78 seconds
Started Jun 21 04:55:43 PM PDT 24
Finished Jun 21 04:55:48 PM PDT 24
Peak memory 206044 kb
Host smart-db615c99-e641-44f8-94a1-b57b5dee4884
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3437008670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.3437008670
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.2667240535
Short name T12
Test name
Test status
Simulation time 13538206353 ps
CPU time 16.38 seconds
Started Jun 21 04:55:37 PM PDT 24
Finished Jun 21 04:55:54 PM PDT 24
Peak memory 206296 kb
Host smart-6768b125-63eb-4b0f-81d8-8465a64db081
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2667240535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.2667240535
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.2922227403
Short name T958
Test name
Test status
Simulation time 23331644768 ps
CPU time 21.04 seconds
Started Jun 21 04:55:39 PM PDT 24
Finished Jun 21 04:56:01 PM PDT 24
Peak memory 206188 kb
Host smart-7dd869d3-8353-4198-8a04-9c0239bd1305
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2922227403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.2922227403
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3061438679
Short name T321
Test name
Test status
Simulation time 149589996 ps
CPU time 0.79 seconds
Started Jun 21 04:55:43 PM PDT 24
Finished Jun 21 04:55:46 PM PDT 24
Peak memory 206028 kb
Host smart-80cd31dd-549c-470d-af37-b9720b28d00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30614
38679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3061438679
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.1161568414
Short name T1628
Test name
Test status
Simulation time 187463801 ps
CPU time 0.78 seconds
Started Jun 21 04:55:38 PM PDT 24
Finished Jun 21 04:55:40 PM PDT 24
Peak memory 205972 kb
Host smart-9006a621-f635-4801-9a48-bcd7af865555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11615
68414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.1161568414
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.2244673298
Short name T1824
Test name
Test status
Simulation time 154098751 ps
CPU time 0.8 seconds
Started Jun 21 04:55:39 PM PDT 24
Finished Jun 21 04:55:41 PM PDT 24
Peak memory 206000 kb
Host smart-00b288e7-3712-4115-ad65-f5bbb56af243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22446
73298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.2244673298
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2606039321
Short name T2149
Test name
Test status
Simulation time 574521818 ps
CPU time 1.43 seconds
Started Jun 21 04:55:38 PM PDT 24
Finished Jun 21 04:55:41 PM PDT 24
Peak memory 206004 kb
Host smart-f980cd06-95f3-4af5-8981-f65df2e5c763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26060
39321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2606039321
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.3961640235
Short name T997
Test name
Test status
Simulation time 10567514122 ps
CPU time 22.97 seconds
Started Jun 21 04:55:38 PM PDT 24
Finished Jun 21 04:56:03 PM PDT 24
Peak memory 206196 kb
Host smart-afba043e-5efe-4ba9-899a-e4dffbf429b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39616
40235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.3961640235
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.3191253272
Short name T1146
Test name
Test status
Simulation time 499476521 ps
CPU time 1.49 seconds
Started Jun 21 04:55:42 PM PDT 24
Finished Jun 21 04:55:44 PM PDT 24
Peak memory 205972 kb
Host smart-01ebc8bc-5a80-49e7-be50-2679d36452eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31912
53272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.3191253272
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.1269961573
Short name T1496
Test name
Test status
Simulation time 145802320 ps
CPU time 0.79 seconds
Started Jun 21 04:55:37 PM PDT 24
Finished Jun 21 04:55:38 PM PDT 24
Peak memory 206024 kb
Host smart-09486cf0-2c7e-4a36-a617-0cd4f208251f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12699
61573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.1269961573
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.4074813804
Short name T2155
Test name
Test status
Simulation time 28557087 ps
CPU time 0.66 seconds
Started Jun 21 04:55:38 PM PDT 24
Finished Jun 21 04:55:40 PM PDT 24
Peak memory 206012 kb
Host smart-0c4dfd35-c468-4568-b37b-a8baa80d74e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40748
13804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.4074813804
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2348010553
Short name T1157
Test name
Test status
Simulation time 841289791 ps
CPU time 2.22 seconds
Started Jun 21 04:55:38 PM PDT 24
Finished Jun 21 04:55:41 PM PDT 24
Peak memory 206264 kb
Host smart-a929eabb-fe33-479c-a86b-d72f85e88d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23480
10553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2348010553
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3017230258
Short name T1396
Test name
Test status
Simulation time 235663873 ps
CPU time 1.33 seconds
Started Jun 21 04:55:43 PM PDT 24
Finished Jun 21 04:55:46 PM PDT 24
Peak memory 206116 kb
Host smart-838a62b6-9031-474e-8f60-cf39244577b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30172
30258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3017230258
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.851404822
Short name T1736
Test name
Test status
Simulation time 185142957 ps
CPU time 0.85 seconds
Started Jun 21 04:55:50 PM PDT 24
Finished Jun 21 04:55:53 PM PDT 24
Peak memory 206008 kb
Host smart-33e86c51-e524-436a-ab3f-d344ed0f0c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85140
4822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.851404822
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.259281466
Short name T1548
Test name
Test status
Simulation time 165448819 ps
CPU time 0.81 seconds
Started Jun 21 04:55:48 PM PDT 24
Finished Jun 21 04:55:50 PM PDT 24
Peak memory 205916 kb
Host smart-0ab319c1-8769-4b38-8b43-b8ebbf4045f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25928
1466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.259281466
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2126730344
Short name T1
Test name
Test status
Simulation time 286727974 ps
CPU time 0.92 seconds
Started Jun 21 04:55:43 PM PDT 24
Finished Jun 21 04:55:46 PM PDT 24
Peak memory 206024 kb
Host smart-abd1c773-2f2a-4613-8e89-f47705063f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21267
30344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2126730344
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.1526317479
Short name T1677
Test name
Test status
Simulation time 165088254 ps
CPU time 0.81 seconds
Started Jun 21 04:55:40 PM PDT 24
Finished Jun 21 04:55:42 PM PDT 24
Peak memory 205948 kb
Host smart-5dfea404-363a-4fb3-a295-198dfb0fc914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15263
17479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.1526317479
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.2704604419
Short name T1250
Test name
Test status
Simulation time 23308829788 ps
CPU time 24.07 seconds
Started Jun 21 04:55:43 PM PDT 24
Finished Jun 21 04:56:09 PM PDT 24
Peak memory 205852 kb
Host smart-9ab3a1de-e68a-4a51-9d84-774448e6dfd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27046
04419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.2704604419
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.552087292
Short name T391
Test name
Test status
Simulation time 3300010500 ps
CPU time 3.9 seconds
Started Jun 21 04:55:37 PM PDT 24
Finished Jun 21 04:55:42 PM PDT 24
Peak memory 206084 kb
Host smart-4f396773-a7f7-482c-adc9-9f6a9ccec631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55208
7292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.552087292
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.659963049
Short name T1819
Test name
Test status
Simulation time 6269723944 ps
CPU time 43.9 seconds
Started Jun 21 04:55:43 PM PDT 24
Finished Jun 21 04:56:29 PM PDT 24
Peak memory 206360 kb
Host smart-b0cf2605-9ea9-40e7-92bb-10f8ee966259
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=659963049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.659963049
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.2569126698
Short name T331
Test name
Test status
Simulation time 234748363 ps
CPU time 0.94 seconds
Started Jun 21 04:55:50 PM PDT 24
Finished Jun 21 04:55:53 PM PDT 24
Peak memory 206048 kb
Host smart-5891ff63-e606-4290-8c42-b67ede13e97e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2569126698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.2569126698
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3613238408
Short name T343
Test name
Test status
Simulation time 192504578 ps
CPU time 0.86 seconds
Started Jun 21 04:55:37 PM PDT 24
Finished Jun 21 04:55:39 PM PDT 24
Peak memory 206048 kb
Host smart-42b2f4d1-dc8f-4740-a4c1-f3af429096ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36132
38408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3613238408
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.4036020187
Short name T1987
Test name
Test status
Simulation time 8502586733 ps
CPU time 66.69 seconds
Started Jun 21 04:55:39 PM PDT 24
Finished Jun 21 04:56:47 PM PDT 24
Peak memory 206148 kb
Host smart-bb9d8e3a-fb76-4f53-b01e-cf02ae25b706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40360
20187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.4036020187
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.475796954
Short name T873
Test name
Test status
Simulation time 10924226412 ps
CPU time 310.24 seconds
Started Jun 21 04:55:42 PM PDT 24
Finished Jun 21 05:00:53 PM PDT 24
Peak memory 206212 kb
Host smart-59b7d94d-30bb-406b-b700-0b6c003c4c53
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=475796954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.475796954
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1496121982
Short name T1729
Test name
Test status
Simulation time 167827469 ps
CPU time 0.77 seconds
Started Jun 21 04:55:46 PM PDT 24
Finished Jun 21 04:55:48 PM PDT 24
Peak memory 206028 kb
Host smart-d6f0c183-38fb-40c8-a797-7eab30bd5a68
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1496121982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1496121982
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.933543530
Short name T340
Test name
Test status
Simulation time 163452466 ps
CPU time 0.78 seconds
Started Jun 21 04:55:39 PM PDT 24
Finished Jun 21 04:55:41 PM PDT 24
Peak memory 206024 kb
Host smart-e64cfce9-5a30-44f4-a6a9-461899346bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93354
3530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.933543530
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.1737241494
Short name T2110
Test name
Test status
Simulation time 158373459 ps
CPU time 0.81 seconds
Started Jun 21 04:55:37 PM PDT 24
Finished Jun 21 04:55:39 PM PDT 24
Peak memory 206000 kb
Host smart-771fa910-5f84-47f9-a4ff-a99853475835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17372
41494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.1737241494
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.4000180126
Short name T2220
Test name
Test status
Simulation time 157099232 ps
CPU time 0.81 seconds
Started Jun 21 04:55:43 PM PDT 24
Finished Jun 21 04:55:45 PM PDT 24
Peak memory 205972 kb
Host smart-82ff1167-a270-44a2-98ec-55ab7b9781d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40001
80126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.4000180126
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2563225071
Short name T1793
Test name
Test status
Simulation time 154758793 ps
CPU time 0.82 seconds
Started Jun 21 04:55:38 PM PDT 24
Finished Jun 21 04:55:40 PM PDT 24
Peak memory 205976 kb
Host smart-19650487-4205-404a-a1c1-fb900ac36559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25632
25071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2563225071
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.2059154389
Short name T2315
Test name
Test status
Simulation time 152226748 ps
CPU time 0.78 seconds
Started Jun 21 04:55:49 PM PDT 24
Finished Jun 21 04:55:51 PM PDT 24
Peak memory 205964 kb
Host smart-47be1479-7028-47a8-967a-f69e9b591a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20591
54389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.2059154389
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.365636680
Short name T2218
Test name
Test status
Simulation time 202346089 ps
CPU time 0.87 seconds
Started Jun 21 04:55:39 PM PDT 24
Finished Jun 21 04:55:41 PM PDT 24
Peak memory 205976 kb
Host smart-66886822-9156-4502-b880-107ebfa8780a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=365636680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.365636680
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1590990623
Short name T743
Test name
Test status
Simulation time 177950408 ps
CPU time 0.8 seconds
Started Jun 21 04:55:37 PM PDT 24
Finished Jun 21 04:55:38 PM PDT 24
Peak memory 206032 kb
Host smart-774e2b93-3441-48fc-a8d7-858a55bc7d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15909
90623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1590990623
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2950434422
Short name T1511
Test name
Test status
Simulation time 34343541 ps
CPU time 0.64 seconds
Started Jun 21 04:55:49 PM PDT 24
Finished Jun 21 04:55:52 PM PDT 24
Peak memory 206032 kb
Host smart-4b5fccb8-ee94-45a6-a2bf-dfd910fd0784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29504
34422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2950434422
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.123559222
Short name T1863
Test name
Test status
Simulation time 14309188158 ps
CPU time 33.58 seconds
Started Jun 21 04:55:42 PM PDT 24
Finished Jun 21 04:56:16 PM PDT 24
Peak memory 206352 kb
Host smart-bc7dd3bf-ce7f-4ec0-8b51-787d7a45b43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12355
9222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.123559222
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2206539993
Short name T1222
Test name
Test status
Simulation time 183673831 ps
CPU time 0.86 seconds
Started Jun 21 04:55:43 PM PDT 24
Finished Jun 21 04:55:45 PM PDT 24
Peak memory 205976 kb
Host smart-9f809a85-4658-4425-bc74-86a08f280059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22065
39993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2206539993
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2334472060
Short name T885
Test name
Test status
Simulation time 211208315 ps
CPU time 0.88 seconds
Started Jun 21 04:55:38 PM PDT 24
Finished Jun 21 04:55:39 PM PDT 24
Peak memory 205964 kb
Host smart-851a43d4-1296-4826-b6d6-9d0a58f31254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23344
72060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2334472060
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.3009132962
Short name T329
Test name
Test status
Simulation time 247133622 ps
CPU time 0.85 seconds
Started Jun 21 04:55:46 PM PDT 24
Finished Jun 21 04:55:48 PM PDT 24
Peak memory 205956 kb
Host smart-7024602e-0883-4abb-ac95-7c71f97558d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30091
32962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.3009132962
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.1644772811
Short name T1879
Test name
Test status
Simulation time 191204732 ps
CPU time 0.77 seconds
Started Jun 21 04:55:38 PM PDT 24
Finished Jun 21 04:55:40 PM PDT 24
Peak memory 205996 kb
Host smart-91db685c-44e8-4a6f-8b2e-17cb4eed5650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16447
72811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.1644772811
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.950909734
Short name T1429
Test name
Test status
Simulation time 140639707 ps
CPU time 0.81 seconds
Started Jun 21 04:55:40 PM PDT 24
Finished Jun 21 04:55:42 PM PDT 24
Peak memory 206028 kb
Host smart-b814c5be-9238-486d-99c9-e03cd1f01966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95090
9734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.950909734
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2679237024
Short name T1028
Test name
Test status
Simulation time 176615553 ps
CPU time 0.87 seconds
Started Jun 21 04:55:46 PM PDT 24
Finished Jun 21 04:55:48 PM PDT 24
Peak memory 205952 kb
Host smart-194b0452-a0a2-4d6a-b924-a3ebacc87a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26792
37024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2679237024
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.325270403
Short name T2295
Test name
Test status
Simulation time 229605941 ps
CPU time 0.86 seconds
Started Jun 21 04:55:43 PM PDT 24
Finished Jun 21 04:55:46 PM PDT 24
Peak memory 206040 kb
Host smart-d7bb66d5-36d8-4217-93b0-dc7947cac0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32527
0403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.325270403
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3395099720
Short name T723
Test name
Test status
Simulation time 199411083 ps
CPU time 0.86 seconds
Started Jun 21 04:55:43 PM PDT 24
Finished Jun 21 04:55:46 PM PDT 24
Peak memory 205856 kb
Host smart-99294a2f-9e7d-4f1b-9893-2c7bef3d597a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33950
99720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3395099720
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.991766724
Short name T2167
Test name
Test status
Simulation time 5661360032 ps
CPU time 156.45 seconds
Started Jun 21 04:55:43 PM PDT 24
Finished Jun 21 04:58:22 PM PDT 24
Peak memory 206280 kb
Host smart-48af3d07-8649-4388-90bc-7723beda4e24
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=991766724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.991766724
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2512663998
Short name T468
Test name
Test status
Simulation time 190383991 ps
CPU time 0.85 seconds
Started Jun 21 04:55:38 PM PDT 24
Finished Jun 21 04:55:41 PM PDT 24
Peak memory 205968 kb
Host smart-55d0d3da-1316-4ad1-ad7b-5f75d144cabe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25126
63998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2512663998
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1089465953
Short name T1967
Test name
Test status
Simulation time 183757387 ps
CPU time 0.86 seconds
Started Jun 21 04:55:43 PM PDT 24
Finished Jun 21 04:55:45 PM PDT 24
Peak memory 205960 kb
Host smart-1712e411-f32b-43dc-985d-d13c63fbe0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10894
65953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1089465953
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.2977654710
Short name T555
Test name
Test status
Simulation time 7443935814 ps
CPU time 73.24 seconds
Started Jun 21 04:55:39 PM PDT 24
Finished Jun 21 04:56:53 PM PDT 24
Peak memory 206284 kb
Host smart-bdb5915d-faf3-4fdb-bc79-8152ef2d2d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29776
54710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.2977654710
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.364462825
Short name T1008
Test name
Test status
Simulation time 3456909480 ps
CPU time 4.16 seconds
Started Jun 21 04:55:48 PM PDT 24
Finished Jun 21 04:55:54 PM PDT 24
Peak memory 206240 kb
Host smart-6d1b490f-4a84-459d-af65-1dc7b8f0ca08
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=364462825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.364462825
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.274254494
Short name T2394
Test name
Test status
Simulation time 13395802459 ps
CPU time 12.66 seconds
Started Jun 21 04:55:48 PM PDT 24
Finished Jun 21 04:56:02 PM PDT 24
Peak memory 206088 kb
Host smart-3863f31b-cb5b-466c-a04c-eb314e22f423
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=274254494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.274254494
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.4155413549
Short name T363
Test name
Test status
Simulation time 23442933366 ps
CPU time 24.57 seconds
Started Jun 21 04:55:47 PM PDT 24
Finished Jun 21 04:56:13 PM PDT 24
Peak memory 206264 kb
Host smart-4cf56d5e-0e36-48ac-a498-5c2e2382b9c9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4155413549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.4155413549
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2103212200
Short name T1100
Test name
Test status
Simulation time 263686676 ps
CPU time 0.88 seconds
Started Jun 21 04:55:48 PM PDT 24
Finished Jun 21 04:55:50 PM PDT 24
Peak memory 206052 kb
Host smart-b77819d7-31f4-4ad4-9093-40abae7a6958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21032
12200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2103212200
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.3597862817
Short name T1537
Test name
Test status
Simulation time 204453881 ps
CPU time 0.84 seconds
Started Jun 21 04:55:45 PM PDT 24
Finished Jun 21 04:55:47 PM PDT 24
Peak memory 206024 kb
Host smart-3d14a3f7-a3b4-4049-a708-0f00dc5c31a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35978
62817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.3597862817
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.3433858644
Short name T1170
Test name
Test status
Simulation time 519770609 ps
CPU time 1.51 seconds
Started Jun 21 04:55:46 PM PDT 24
Finished Jun 21 04:55:49 PM PDT 24
Peak memory 206004 kb
Host smart-439318a3-07f6-465f-a9fe-7193612f0b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34338
58644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.3433858644
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.933128932
Short name T1486
Test name
Test status
Simulation time 632684948 ps
CPU time 1.48 seconds
Started Jun 21 04:55:47 PM PDT 24
Finished Jun 21 04:55:51 PM PDT 24
Peak memory 206048 kb
Host smart-19f5ccb3-ce36-4e05-83b7-80319589601b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93312
8932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.933128932
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.4006713676
Short name T1326
Test name
Test status
Simulation time 22163371580 ps
CPU time 40.62 seconds
Started Jun 21 04:55:57 PM PDT 24
Finished Jun 21 04:56:39 PM PDT 24
Peak memory 206316 kb
Host smart-252039d1-5dc2-4251-a6f9-7d5ea8184ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40067
13676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.4006713676
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.303666763
Short name T2151
Test name
Test status
Simulation time 339573213 ps
CPU time 1.17 seconds
Started Jun 21 04:55:47 PM PDT 24
Finished Jun 21 04:55:50 PM PDT 24
Peak memory 206028 kb
Host smart-3642d5d8-e10c-4870-95b7-e78b335fba10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30366
6763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.303666763
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.6496141
Short name T1900
Test name
Test status
Simulation time 143728783 ps
CPU time 0.77 seconds
Started Jun 21 04:55:47 PM PDT 24
Finished Jun 21 04:55:50 PM PDT 24
Peak memory 206024 kb
Host smart-739eaf29-4740-427f-96ac-6a218fe558de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64961
41 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.6496141
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2103064306
Short name T925
Test name
Test status
Simulation time 30703159 ps
CPU time 0.65 seconds
Started Jun 21 04:55:46 PM PDT 24
Finished Jun 21 04:55:48 PM PDT 24
Peak memory 206024 kb
Host smart-40b32f43-71cf-4aff-bd04-db3de7f80f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21030
64306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2103064306
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1802050784
Short name T1214
Test name
Test status
Simulation time 905163523 ps
CPU time 2.12 seconds
Started Jun 21 04:55:49 PM PDT 24
Finished Jun 21 04:55:52 PM PDT 24
Peak memory 206256 kb
Host smart-873db5a0-87e6-458d-89ae-0dd118e2f78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18020
50784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1802050784
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.210385564
Short name T659
Test name
Test status
Simulation time 294351332 ps
CPU time 1.86 seconds
Started Jun 21 04:55:48 PM PDT 24
Finished Jun 21 04:55:52 PM PDT 24
Peak memory 206220 kb
Host smart-c035c4ac-8811-47ce-b242-5dd28d131528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21038
5564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.210385564
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1787397228
Short name T1402
Test name
Test status
Simulation time 200519798 ps
CPU time 0.98 seconds
Started Jun 21 04:56:00 PM PDT 24
Finished Jun 21 04:56:03 PM PDT 24
Peak memory 206024 kb
Host smart-fbd77d66-335f-423e-afd3-54d52cab924d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17873
97228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1787397228
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3627703852
Short name T326
Test name
Test status
Simulation time 162533778 ps
CPU time 0.79 seconds
Started Jun 21 04:55:58 PM PDT 24
Finished Jun 21 04:56:00 PM PDT 24
Peak memory 205916 kb
Host smart-231ecdd7-8444-40f5-8137-c518009dc9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36277
03852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3627703852
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2309163718
Short name T1745
Test name
Test status
Simulation time 211652078 ps
CPU time 0.91 seconds
Started Jun 21 04:55:48 PM PDT 24
Finished Jun 21 04:55:50 PM PDT 24
Peak memory 205920 kb
Host smart-3595d6f6-5961-4691-8f73-89670d0e9e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23091
63718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2309163718
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1891684779
Short name T440
Test name
Test status
Simulation time 182002360 ps
CPU time 0.9 seconds
Started Jun 21 04:55:47 PM PDT 24
Finished Jun 21 04:55:50 PM PDT 24
Peak memory 206144 kb
Host smart-b972ebe4-8b45-4d50-97e9-5a7d17f8b2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18916
84779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1891684779
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.3824806294
Short name T2316
Test name
Test status
Simulation time 23274065681 ps
CPU time 21.62 seconds
Started Jun 21 04:55:51 PM PDT 24
Finished Jun 21 04:56:14 PM PDT 24
Peak memory 206052 kb
Host smart-f238d847-b738-4a2a-a71b-fa0b129468a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38248
06294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.3824806294
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.1344159144
Short name T2338
Test name
Test status
Simulation time 3344092317 ps
CPU time 3.83 seconds
Started Jun 21 04:55:49 PM PDT 24
Finished Jun 21 04:55:55 PM PDT 24
Peak memory 205996 kb
Host smart-83ea1a53-a834-4266-8546-3e89361eb913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13441
59144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1344159144
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.648131579
Short name T1873
Test name
Test status
Simulation time 7992902069 ps
CPU time 78.72 seconds
Started Jun 21 04:55:46 PM PDT 24
Finished Jun 21 04:57:06 PM PDT 24
Peak memory 206272 kb
Host smart-59baa152-865c-4180-b4ea-df36419aaffd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=648131579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.648131579
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.665409452
Short name T1060
Test name
Test status
Simulation time 264357853 ps
CPU time 1.01 seconds
Started Jun 21 04:55:57 PM PDT 24
Finished Jun 21 04:55:59 PM PDT 24
Peak memory 206004 kb
Host smart-1e0517ef-04f2-4024-b1b2-e86a69749db3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=665409452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.665409452
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1096814233
Short name T2079
Test name
Test status
Simulation time 194719024 ps
CPU time 0.87 seconds
Started Jun 21 04:55:51 PM PDT 24
Finished Jun 21 04:55:53 PM PDT 24
Peak memory 206032 kb
Host smart-b745d3a4-ca7d-4e86-8451-b6e8c376c390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10968
14233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1096814233
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.3187741363
Short name T1266
Test name
Test status
Simulation time 6228879136 ps
CPU time 46.25 seconds
Started Jun 21 04:55:47 PM PDT 24
Finished Jun 21 04:56:35 PM PDT 24
Peak memory 206176 kb
Host smart-055f084e-9306-495c-a8b4-a60f417e11dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31877
41363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.3187741363
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.802387207
Short name T383
Test name
Test status
Simulation time 4963814081 ps
CPU time 137.28 seconds
Started Jun 21 04:55:48 PM PDT 24
Finished Jun 21 04:58:07 PM PDT 24
Peak memory 206224 kb
Host smart-b3304be4-85f8-4ae1-b495-aba9c849dcae
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=802387207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.802387207
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.3551581604
Short name T550
Test name
Test status
Simulation time 180173764 ps
CPU time 0.83 seconds
Started Jun 21 04:55:55 PM PDT 24
Finished Jun 21 04:55:57 PM PDT 24
Peak memory 205996 kb
Host smart-4532b10d-9411-4021-8e3f-d135a47f7424
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3551581604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.3551581604
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3539395401
Short name T539
Test name
Test status
Simulation time 155664344 ps
CPU time 0.74 seconds
Started Jun 21 04:55:46 PM PDT 24
Finished Jun 21 04:55:48 PM PDT 24
Peak memory 205952 kb
Host smart-5d6c1e4f-52b8-4b83-9a9e-0732aeda968b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35393
95401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3539395401
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.4088668412
Short name T2175
Test name
Test status
Simulation time 224823207 ps
CPU time 0.86 seconds
Started Jun 21 04:55:50 PM PDT 24
Finished Jun 21 04:55:53 PM PDT 24
Peak memory 205996 kb
Host smart-174429e9-dfd8-4d75-afc1-21d0bbd41091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40886
68412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.4088668412
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.4020792944
Short name T417
Test name
Test status
Simulation time 145457324 ps
CPU time 0.82 seconds
Started Jun 21 04:55:46 PM PDT 24
Finished Jun 21 04:55:48 PM PDT 24
Peak memory 206140 kb
Host smart-89764c45-ff19-4438-a0a5-80ac7011493f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40207
92944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.4020792944
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.4161984345
Short name T1335
Test name
Test status
Simulation time 186792624 ps
CPU time 0.94 seconds
Started Jun 21 04:55:47 PM PDT 24
Finished Jun 21 04:55:50 PM PDT 24
Peak memory 205992 kb
Host smart-16abec08-faba-4215-a836-cd64dacd61a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41619
84345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.4161984345
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3369714843
Short name T928
Test name
Test status
Simulation time 162638679 ps
CPU time 0.8 seconds
Started Jun 21 04:55:57 PM PDT 24
Finished Jun 21 04:56:00 PM PDT 24
Peak memory 206032 kb
Host smart-b114d49f-7e87-4b9f-828c-98d45af41871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33697
14843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3369714843
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.2592860300
Short name T2248
Test name
Test status
Simulation time 208688629 ps
CPU time 0.88 seconds
Started Jun 21 04:56:00 PM PDT 24
Finished Jun 21 04:56:03 PM PDT 24
Peak memory 206044 kb
Host smart-b2ab1089-a966-460d-a882-e4c4d5c56d87
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2592860300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.2592860300
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.1296207493
Short name T1844
Test name
Test status
Simulation time 192709431 ps
CPU time 0.8 seconds
Started Jun 21 04:55:57 PM PDT 24
Finished Jun 21 04:55:59 PM PDT 24
Peak memory 206028 kb
Host smart-65162d79-7705-43ed-a3e2-8f49939ee52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12962
07493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.1296207493
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3296168844
Short name T32
Test name
Test status
Simulation time 47229010 ps
CPU time 0.69 seconds
Started Jun 21 04:55:57 PM PDT 24
Finished Jun 21 04:55:58 PM PDT 24
Peak memory 206012 kb
Host smart-ba43676f-5447-4965-bc94-1540106acb72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32961
68844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3296168844
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.4077778885
Short name T1698
Test name
Test status
Simulation time 17353533079 ps
CPU time 37.6 seconds
Started Jun 21 04:55:51 PM PDT 24
Finished Jun 21 04:56:30 PM PDT 24
Peak memory 206364 kb
Host smart-5a99a6df-f651-4ce1-b7b7-f153a26c6798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40777
78885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.4077778885
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1418875194
Short name T776
Test name
Test status
Simulation time 221812528 ps
CPU time 0.91 seconds
Started Jun 21 04:55:48 PM PDT 24
Finished Jun 21 04:55:51 PM PDT 24
Peak memory 205984 kb
Host smart-2beefe61-1c41-4903-a525-7d34a16bd75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14188
75194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1418875194
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1113473991
Short name T1775
Test name
Test status
Simulation time 212979804 ps
CPU time 0.93 seconds
Started Jun 21 04:55:50 PM PDT 24
Finished Jun 21 04:55:53 PM PDT 24
Peak memory 205964 kb
Host smart-7055bf2f-ec0b-4550-870c-e3a8de8d6575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11134
73991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1113473991
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.3873162497
Short name T1002
Test name
Test status
Simulation time 187134791 ps
CPU time 0.86 seconds
Started Jun 21 04:55:58 PM PDT 24
Finished Jun 21 04:56:01 PM PDT 24
Peak memory 206008 kb
Host smart-fb2823bc-1ec4-488b-baba-e4180aa5abaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38731
62497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.3873162497
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.2011252109
Short name T2472
Test name
Test status
Simulation time 159518684 ps
CPU time 0.79 seconds
Started Jun 21 04:55:47 PM PDT 24
Finished Jun 21 04:55:49 PM PDT 24
Peak memory 206044 kb
Host smart-efa48d9f-716f-45f0-906c-11d1a99266f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20112
52109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.2011252109
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1980570752
Short name T70
Test name
Test status
Simulation time 179653755 ps
CPU time 0.87 seconds
Started Jun 21 04:55:48 PM PDT 24
Finished Jun 21 04:55:51 PM PDT 24
Peak memory 206076 kb
Host smart-c35929e2-6481-486e-a8e5-ba3d489c6981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19805
70752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1980570752
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.4226802417
Short name T2128
Test name
Test status
Simulation time 155679448 ps
CPU time 0.77 seconds
Started Jun 21 04:55:58 PM PDT 24
Finished Jun 21 04:56:02 PM PDT 24
Peak memory 206020 kb
Host smart-39cb7f89-bc2d-443e-9eea-298703ac3d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42268
02417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.4226802417
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.912037910
Short name T692
Test name
Test status
Simulation time 173800298 ps
CPU time 0.87 seconds
Started Jun 21 04:55:49 PM PDT 24
Finished Jun 21 04:55:52 PM PDT 24
Peak memory 205952 kb
Host smart-ecfb4c5c-49d3-4e26-81a1-9ae6348a0002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91203
7910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.912037910
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.4276946126
Short name T1245
Test name
Test status
Simulation time 216926866 ps
CPU time 0.95 seconds
Started Jun 21 04:55:47 PM PDT 24
Finished Jun 21 04:55:49 PM PDT 24
Peak memory 206028 kb
Host smart-6b9fbe8b-36b2-4087-a9c3-239cef9cf97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42769
46126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.4276946126
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.2742272220
Short name T2141
Test name
Test status
Simulation time 13213634458 ps
CPU time 370.95 seconds
Started Jun 21 04:55:51 PM PDT 24
Finished Jun 21 05:02:03 PM PDT 24
Peak memory 206240 kb
Host smart-47ec0906-bd5f-49e0-9432-4bcfc827d203
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2742272220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.2742272220
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1086125119
Short name T2039
Test name
Test status
Simulation time 194761312 ps
CPU time 0.81 seconds
Started Jun 21 04:55:58 PM PDT 24
Finished Jun 21 04:56:01 PM PDT 24
Peak memory 205968 kb
Host smart-055d253d-5c19-44c3-8572-7e3ab776dd5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10861
25119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1086125119
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.2729500019
Short name T436
Test name
Test status
Simulation time 167404201 ps
CPU time 0.84 seconds
Started Jun 21 04:55:47 PM PDT 24
Finished Jun 21 04:55:50 PM PDT 24
Peak memory 206024 kb
Host smart-63068852-2651-4a15-97dd-7f85193d3d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27295
00019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.2729500019
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1307349012
Short name T1705
Test name
Test status
Simulation time 4518232628 ps
CPU time 125.3 seconds
Started Jun 21 04:55:50 PM PDT 24
Finished Jun 21 04:57:57 PM PDT 24
Peak memory 206220 kb
Host smart-01b544a3-6444-434d-9202-1eb23045d17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13073
49012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1307349012
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.1263330226
Short name T1031
Test name
Test status
Simulation time 3525516151 ps
CPU time 4.24 seconds
Started Jun 21 04:55:57 PM PDT 24
Finished Jun 21 04:56:03 PM PDT 24
Peak memory 206036 kb
Host smart-80cab981-1cf3-438f-8165-c2a2fe129893
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1263330226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.1263330226
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.4144825
Short name T1630
Test name
Test status
Simulation time 13386386549 ps
CPU time 14.89 seconds
Started Jun 21 04:56:00 PM PDT 24
Finished Jun 21 04:56:17 PM PDT 24
Peak memory 206260 kb
Host smart-e972590d-121a-4f62-9e2d-e49452043d1a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4144825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.4144825
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.788253415
Short name T561
Test name
Test status
Simulation time 23493293151 ps
CPU time 24.14 seconds
Started Jun 21 04:55:59 PM PDT 24
Finished Jun 21 04:56:26 PM PDT 24
Peak memory 206228 kb
Host smart-0d9c0e60-714a-4411-a981-b67e5700df7c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=788253415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.788253415
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.686848644
Short name T1137
Test name
Test status
Simulation time 142331931 ps
CPU time 0.72 seconds
Started Jun 21 04:55:54 PM PDT 24
Finished Jun 21 04:55:56 PM PDT 24
Peak memory 205972 kb
Host smart-4c55af6d-8774-49b6-ad24-e47f1c5f7607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68684
8644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.686848644
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1389571682
Short name T1784
Test name
Test status
Simulation time 192871317 ps
CPU time 0.88 seconds
Started Jun 21 04:55:58 PM PDT 24
Finished Jun 21 04:56:02 PM PDT 24
Peak memory 206024 kb
Host smart-3e42c7bc-069e-4268-b4df-e2fae2835312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13895
71682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1389571682
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.510826498
Short name T1072
Test name
Test status
Simulation time 574358680 ps
CPU time 1.73 seconds
Started Jun 21 04:56:04 PM PDT 24
Finished Jun 21 04:56:06 PM PDT 24
Peak memory 206256 kb
Host smart-c002b942-f5d5-44ee-b4c1-d02e637ff714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51082
6498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.510826498
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.1882723374
Short name T2056
Test name
Test status
Simulation time 1216596652 ps
CPU time 2.56 seconds
Started Jun 21 04:56:00 PM PDT 24
Finished Jun 21 04:56:04 PM PDT 24
Peak memory 206256 kb
Host smart-86c7a5e7-4ae1-42c4-994b-827bafac143b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18827
23374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.1882723374
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.2562360206
Short name T1528
Test name
Test status
Simulation time 6639897997 ps
CPU time 12.44 seconds
Started Jun 21 04:55:56 PM PDT 24
Finished Jun 21 04:56:10 PM PDT 24
Peak memory 206296 kb
Host smart-f591e3e2-ed52-430c-9b90-906728915785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25623
60206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.2562360206
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.1028294589
Short name T650
Test name
Test status
Simulation time 508144494 ps
CPU time 1.51 seconds
Started Jun 21 04:56:00 PM PDT 24
Finished Jun 21 04:56:04 PM PDT 24
Peak memory 205996 kb
Host smart-a1818e77-51ba-4ce4-900e-b730be85f6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10282
94589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.1028294589
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3127628502
Short name T1568
Test name
Test status
Simulation time 142032623 ps
CPU time 0.79 seconds
Started Jun 21 04:55:56 PM PDT 24
Finished Jun 21 04:55:57 PM PDT 24
Peak memory 206016 kb
Host smart-e33c5c6b-97dd-4644-b765-405dad00c5bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31276
28502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3127628502
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.1150355544
Short name T2033
Test name
Test status
Simulation time 65563348 ps
CPU time 0.69 seconds
Started Jun 21 04:55:57 PM PDT 24
Finished Jun 21 04:55:59 PM PDT 24
Peak memory 205960 kb
Host smart-cff3836d-c3c0-49f3-b739-bfa86e3a575b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11503
55544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1150355544
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2035742298
Short name T1174
Test name
Test status
Simulation time 1047440547 ps
CPU time 2.24 seconds
Started Jun 21 04:55:57 PM PDT 24
Finished Jun 21 04:56:00 PM PDT 24
Peak memory 206236 kb
Host smart-b805b5e1-e462-4b83-9b27-6dbd1e671f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20357
42298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2035742298
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.4015100260
Short name T1171
Test name
Test status
Simulation time 279710842 ps
CPU time 2.03 seconds
Started Jun 21 04:55:56 PM PDT 24
Finished Jun 21 04:55:59 PM PDT 24
Peak memory 206216 kb
Host smart-afda82ca-be25-419b-bf18-90660d4839c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40151
00260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.4015100260
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3831259130
Short name T1937
Test name
Test status
Simulation time 252770037 ps
CPU time 0.93 seconds
Started Jun 21 04:56:06 PM PDT 24
Finished Jun 21 04:56:07 PM PDT 24
Peak memory 205952 kb
Host smart-9f721a06-b564-4dca-b4a0-66f7ed18e895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38312
59130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3831259130
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.4210630883
Short name T2227
Test name
Test status
Simulation time 207903630 ps
CPU time 0.8 seconds
Started Jun 21 04:56:10 PM PDT 24
Finished Jun 21 04:56:13 PM PDT 24
Peak memory 205784 kb
Host smart-9f09f9c9-3b5d-4c1a-be76-8d98a09974ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42106
30883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.4210630883
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.4268634072
Short name T1354
Test name
Test status
Simulation time 223530761 ps
CPU time 0.89 seconds
Started Jun 21 04:55:55 PM PDT 24
Finished Jun 21 04:55:56 PM PDT 24
Peak memory 205960 kb
Host smart-8363bf2b-68a4-4989-8dd8-8d596e610b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42686
34072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.4268634072
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.1767417543
Short name T1397
Test name
Test status
Simulation time 197591455 ps
CPU time 0.86 seconds
Started Jun 21 04:55:57 PM PDT 24
Finished Jun 21 04:56:00 PM PDT 24
Peak memory 206020 kb
Host smart-dc8bffed-e5f0-47eb-bb9e-b9110a0cbdad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17674
17543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.1767417543
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.436661042
Short name T1415
Test name
Test status
Simulation time 23363428660 ps
CPU time 24.47 seconds
Started Jun 21 04:55:59 PM PDT 24
Finished Jun 21 04:56:26 PM PDT 24
Peak memory 205972 kb
Host smart-447b6ae3-7dc8-4210-a696-6345ac6ed662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43666
1042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.436661042
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.3197664059
Short name T352
Test name
Test status
Simulation time 3344141644 ps
CPU time 4.21 seconds
Started Jun 21 04:55:58 PM PDT 24
Finished Jun 21 04:56:06 PM PDT 24
Peak memory 206084 kb
Host smart-d5296ed6-0d6e-4740-90d0-9bfff880f7dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31976
64059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.3197664059
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.4004369426
Short name T546
Test name
Test status
Simulation time 10068385806 ps
CPU time 269.69 seconds
Started Jun 21 04:55:56 PM PDT 24
Finished Jun 21 05:00:26 PM PDT 24
Peak memory 206212 kb
Host smart-f82e60ea-a5f4-42a3-891a-1dbbae6811d5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4004369426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.4004369426
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.3071359665
Short name T1386
Test name
Test status
Simulation time 254792465 ps
CPU time 0.88 seconds
Started Jun 21 04:56:09 PM PDT 24
Finished Jun 21 04:56:12 PM PDT 24
Peak memory 205956 kb
Host smart-caeb2f98-4b34-4c77-bf40-1e9e9e241d52
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3071359665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.3071359665
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1048012851
Short name T2404
Test name
Test status
Simulation time 186323099 ps
CPU time 0.86 seconds
Started Jun 21 04:55:58 PM PDT 24
Finished Jun 21 04:56:02 PM PDT 24
Peak memory 205948 kb
Host smart-bea066a0-d715-4585-a0bc-031a41ffbc25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10480
12851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1048012851
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.4003384788
Short name T1088
Test name
Test status
Simulation time 10385385790 ps
CPU time 100.09 seconds
Started Jun 21 04:55:59 PM PDT 24
Finished Jun 21 04:57:42 PM PDT 24
Peak memory 206264 kb
Host smart-f4faa712-5081-46a3-9004-b43c6263be37
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4003384788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.4003384788
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.947699002
Short name T852
Test name
Test status
Simulation time 169068232 ps
CPU time 0.88 seconds
Started Jun 21 04:56:06 PM PDT 24
Finished Jun 21 04:56:08 PM PDT 24
Peak memory 205996 kb
Host smart-1cac8ad3-ec92-4044-8789-3898c4f77548
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=947699002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.947699002
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.3975447600
Short name T1047
Test name
Test status
Simulation time 138731709 ps
CPU time 0.8 seconds
Started Jun 21 04:55:57 PM PDT 24
Finished Jun 21 04:56:00 PM PDT 24
Peak memory 205936 kb
Host smart-2abf9a79-3080-442b-84f4-601148ca1d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39754
47600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.3975447600
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.4099147549
Short name T559
Test name
Test status
Simulation time 196347009 ps
CPU time 0.9 seconds
Started Jun 21 04:56:06 PM PDT 24
Finished Jun 21 04:56:09 PM PDT 24
Peak memory 206024 kb
Host smart-487fdc93-a181-4ac4-8265-1b3f4e7d293a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40991
47549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.4099147549
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2611362850
Short name T1734
Test name
Test status
Simulation time 168069819 ps
CPU time 0.89 seconds
Started Jun 21 04:56:08 PM PDT 24
Finished Jun 21 04:56:11 PM PDT 24
Peak memory 205928 kb
Host smart-92c6d031-8a20-4239-8758-88eac49ecf98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26113
62850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2611362850
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3903179354
Short name T1495
Test name
Test status
Simulation time 230470710 ps
CPU time 0.84 seconds
Started Jun 21 04:56:06 PM PDT 24
Finished Jun 21 04:56:09 PM PDT 24
Peak memory 206040 kb
Host smart-c786cee5-11ff-4121-b722-492113d6b148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39031
79354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3903179354
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1343597740
Short name T881
Test name
Test status
Simulation time 148070094 ps
CPU time 0.82 seconds
Started Jun 21 04:56:07 PM PDT 24
Finished Jun 21 04:56:10 PM PDT 24
Peak memory 205924 kb
Host smart-9b497ed8-1f1c-4b22-89ac-cb22aaa38acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13435
97740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1343597740
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.3659446691
Short name T368
Test name
Test status
Simulation time 242830116 ps
CPU time 1 seconds
Started Jun 21 04:56:07 PM PDT 24
Finished Jun 21 04:56:10 PM PDT 24
Peak memory 205932 kb
Host smart-b4f60830-6f70-4b9d-a52a-a8a92bc00230
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3659446691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.3659446691
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.769900804
Short name T575
Test name
Test status
Simulation time 36593100 ps
CPU time 0.64 seconds
Started Jun 21 04:56:06 PM PDT 24
Finished Jun 21 04:56:07 PM PDT 24
Peak memory 206032 kb
Host smart-c29d51a8-7a43-49f7-9413-7f08b7317ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76990
0804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.769900804
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3893662807
Short name T1411
Test name
Test status
Simulation time 167164100 ps
CPU time 0.82 seconds
Started Jun 21 04:56:08 PM PDT 24
Finished Jun 21 04:56:11 PM PDT 24
Peak memory 205964 kb
Host smart-1c282eaf-4720-4367-a3bf-8c0871f36a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38936
62807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3893662807
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2475334665
Short name T382
Test name
Test status
Simulation time 201614582 ps
CPU time 0.84 seconds
Started Jun 21 04:56:05 PM PDT 24
Finished Jun 21 04:56:07 PM PDT 24
Peak memory 205932 kb
Host smart-fce18dc1-9b15-4b69-b023-7af30c475418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24753
34665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2475334665
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.19007558
Short name T1297
Test name
Test status
Simulation time 227771972 ps
CPU time 0.86 seconds
Started Jun 21 04:56:08 PM PDT 24
Finished Jun 21 04:56:11 PM PDT 24
Peak memory 205956 kb
Host smart-6a19624b-79a9-445e-9405-9e660b0ff90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19007
558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.19007558
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.982253232
Short name T1125
Test name
Test status
Simulation time 191484998 ps
CPU time 0.87 seconds
Started Jun 21 04:56:12 PM PDT 24
Finished Jun 21 04:56:15 PM PDT 24
Peak memory 206044 kb
Host smart-0e09b880-c086-45a5-8b06-9be2ef6928de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98225
3232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.982253232
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.1212498275
Short name T557
Test name
Test status
Simulation time 189882704 ps
CPU time 0.83 seconds
Started Jun 21 04:56:09 PM PDT 24
Finished Jun 21 04:56:12 PM PDT 24
Peak memory 206020 kb
Host smart-5791e204-21cc-4edd-b68e-4f6f92c43db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12124
98275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.1212498275
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3156494702
Short name T1103
Test name
Test status
Simulation time 150399451 ps
CPU time 0.71 seconds
Started Jun 21 04:56:07 PM PDT 24
Finished Jun 21 04:56:09 PM PDT 24
Peak memory 205964 kb
Host smart-a1086c5c-fe7a-4a84-a118-332f7f0e364f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31564
94702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3156494702
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3383078013
Short name T1614
Test name
Test status
Simulation time 155871234 ps
CPU time 0.83 seconds
Started Jun 21 04:56:10 PM PDT 24
Finished Jun 21 04:56:13 PM PDT 24
Peak memory 206144 kb
Host smart-64306128-26f5-4328-bf42-b64392678d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33830
78013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3383078013
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3312967184
Short name T2368
Test name
Test status
Simulation time 184753205 ps
CPU time 0.85 seconds
Started Jun 21 04:55:59 PM PDT 24
Finished Jun 21 04:56:02 PM PDT 24
Peak memory 206008 kb
Host smart-01d08b1f-ba44-45e7-b20c-9d0e07fae8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33129
67184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3312967184
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.3663754223
Short name T1609
Test name
Test status
Simulation time 14181571259 ps
CPU time 100.8 seconds
Started Jun 21 04:56:08 PM PDT 24
Finished Jun 21 04:57:51 PM PDT 24
Peak memory 206232 kb
Host smart-4dafc079-2454-41c9-a3d1-761b2cae907b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3663754223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3663754223
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.4166186990
Short name T1346
Test name
Test status
Simulation time 178603547 ps
CPU time 0.83 seconds
Started Jun 21 04:56:09 PM PDT 24
Finished Jun 21 04:56:12 PM PDT 24
Peak memory 205972 kb
Host smart-81398231-c09d-44e9-b79a-0f0adc67a026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41661
86990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.4166186990
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1941455219
Short name T2435
Test name
Test status
Simulation time 178767926 ps
CPU time 0.78 seconds
Started Jun 21 04:56:07 PM PDT 24
Finished Jun 21 04:56:10 PM PDT 24
Peak memory 205968 kb
Host smart-9ca7d0c2-0885-4f97-8029-8c97ef405d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19414
55219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1941455219
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.3626975065
Short name T2281
Test name
Test status
Simulation time 8504590026 ps
CPU time 248.37 seconds
Started Jun 21 04:56:06 PM PDT 24
Finished Jun 21 05:00:15 PM PDT 24
Peak memory 206248 kb
Host smart-6718b73f-c3a1-4f8f-9caf-8ed5c5b80551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36269
75065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3626975065
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.1062327531
Short name T2160
Test name
Test status
Simulation time 3538162139 ps
CPU time 4.16 seconds
Started Jun 21 04:56:11 PM PDT 24
Finished Jun 21 04:56:17 PM PDT 24
Peak memory 206356 kb
Host smart-2c3ee2f1-66c3-4b07-879b-6d2cb793c6c1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1062327531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.1062327531
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3819021271
Short name T2416
Test name
Test status
Simulation time 13390294823 ps
CPU time 11.79 seconds
Started Jun 21 04:56:09 PM PDT 24
Finished Jun 21 04:56:23 PM PDT 24
Peak memory 206092 kb
Host smart-dfabdd5b-2984-48a0-b727-aae634245bcc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3819021271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3819021271
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.1948465437
Short name T815
Test name
Test status
Simulation time 23446472371 ps
CPU time 24.81 seconds
Started Jun 21 04:56:07 PM PDT 24
Finished Jun 21 04:56:33 PM PDT 24
Peak memory 206196 kb
Host smart-7485eabb-1563-4615-8e69-61300a15eee4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1948465437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.1948465437
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3987318178
Short name T1529
Test name
Test status
Simulation time 158849131 ps
CPU time 0.82 seconds
Started Jun 21 04:56:12 PM PDT 24
Finished Jun 21 04:56:15 PM PDT 24
Peak memory 206024 kb
Host smart-ff2f8532-7ead-4111-8c38-e9188050ea6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39873
18178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3987318178
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3185066466
Short name T1610
Test name
Test status
Simulation time 187619352 ps
CPU time 0.92 seconds
Started Jun 21 04:56:08 PM PDT 24
Finished Jun 21 04:56:11 PM PDT 24
Peak memory 206024 kb
Host smart-0bdc447d-ff56-4695-8c9e-ac4144687bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31850
66466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3185066466
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3292449907
Short name T1204
Test name
Test status
Simulation time 514986854 ps
CPU time 1.55 seconds
Started Jun 21 04:56:08 PM PDT 24
Finished Jun 21 04:56:12 PM PDT 24
Peak memory 206216 kb
Host smart-dd32c965-235e-4617-89d4-dc29b97a02b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32924
49907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3292449907
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3045719447
Short name T2351
Test name
Test status
Simulation time 532687432 ps
CPU time 1.38 seconds
Started Jun 21 04:56:12 PM PDT 24
Finished Jun 21 04:56:15 PM PDT 24
Peak memory 206028 kb
Host smart-5a2645eb-1e53-46b6-89ae-a50f3d303d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30457
19447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3045719447
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.3501327658
Short name T2086
Test name
Test status
Simulation time 9102932415 ps
CPU time 16.74 seconds
Started Jun 21 04:56:09 PM PDT 24
Finished Jun 21 04:56:28 PM PDT 24
Peak memory 206344 kb
Host smart-a1d02f68-24b9-443c-8241-74f66017d305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35013
27658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.3501327658
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.1760912270
Short name T190
Test name
Test status
Simulation time 388205063 ps
CPU time 1.18 seconds
Started Jun 21 04:56:07 PM PDT 24
Finished Jun 21 04:56:11 PM PDT 24
Peak memory 206008 kb
Host smart-db99962b-4fdc-4914-9bc9-687949828e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17609
12270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1760912270
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.1312492894
Short name T855
Test name
Test status
Simulation time 136146333 ps
CPU time 0.76 seconds
Started Jun 21 04:56:10 PM PDT 24
Finished Jun 21 04:56:13 PM PDT 24
Peak memory 205960 kb
Host smart-000926a7-436e-4e2d-a895-23bf22059eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13124
92894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.1312492894
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.4141399994
Short name T1973
Test name
Test status
Simulation time 87838611 ps
CPU time 0.65 seconds
Started Jun 21 04:56:06 PM PDT 24
Finished Jun 21 04:56:09 PM PDT 24
Peak memory 206012 kb
Host smart-0169838a-726c-44c1-a952-9a3f89dd5472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41413
99994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.4141399994
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2095935567
Short name T1006
Test name
Test status
Simulation time 986763968 ps
CPU time 2.43 seconds
Started Jun 21 04:56:07 PM PDT 24
Finished Jun 21 04:56:12 PM PDT 24
Peak memory 206216 kb
Host smart-24242dbf-0e98-41eb-9037-a30f6f0de5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20959
35567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2095935567
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.74546712
Short name T1145
Test name
Test status
Simulation time 219233080 ps
CPU time 1.4 seconds
Started Jun 21 04:56:06 PM PDT 24
Finished Jun 21 04:56:08 PM PDT 24
Peak memory 206164 kb
Host smart-1fbcffb2-b2e4-4dfc-8cb5-46ece866a4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74546
712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.74546712
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2878689514
Short name T1534
Test name
Test status
Simulation time 215592559 ps
CPU time 0.93 seconds
Started Jun 21 04:56:13 PM PDT 24
Finished Jun 21 04:56:16 PM PDT 24
Peak memory 206024 kb
Host smart-144961f2-06c4-47b6-a34f-b5c5c16b9f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28786
89514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2878689514
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.747666370
Short name T1359
Test name
Test status
Simulation time 147961617 ps
CPU time 0.74 seconds
Started Jun 21 04:56:19 PM PDT 24
Finished Jun 21 04:56:21 PM PDT 24
Peak memory 206016 kb
Host smart-abce9fcb-7eba-433b-98bd-9426f4b428eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74766
6370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.747666370
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1922526004
Short name T1541
Test name
Test status
Simulation time 235215341 ps
CPU time 0.94 seconds
Started Jun 21 04:56:07 PM PDT 24
Finished Jun 21 04:56:11 PM PDT 24
Peak memory 206032 kb
Host smart-6fa3f06d-9f8f-4a51-8022-143f96065029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19225
26004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1922526004
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1866228134
Short name T1177
Test name
Test status
Simulation time 239763526 ps
CPU time 0.89 seconds
Started Jun 21 04:56:11 PM PDT 24
Finished Jun 21 04:56:14 PM PDT 24
Peak memory 206020 kb
Host smart-e8146822-0ce7-4abf-a51a-e8596025c164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18662
28134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1866228134
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.3290167235
Short name T890
Test name
Test status
Simulation time 23282362183 ps
CPU time 22.6 seconds
Started Jun 21 04:56:10 PM PDT 24
Finished Jun 21 04:56:35 PM PDT 24
Peak memory 205856 kb
Host smart-4dbcaff0-e974-482c-8548-cb1de3636ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32901
67235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3290167235
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.1202483237
Short name T1970
Test name
Test status
Simulation time 3320603971 ps
CPU time 3.84 seconds
Started Jun 21 04:56:08 PM PDT 24
Finished Jun 21 04:56:14 PM PDT 24
Peak memory 206088 kb
Host smart-7656547b-a10b-44d7-9139-4c4a79a85a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12024
83237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.1202483237
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.117684110
Short name T1238
Test name
Test status
Simulation time 3739475658 ps
CPU time 34.72 seconds
Started Jun 21 04:56:07 PM PDT 24
Finished Jun 21 04:56:44 PM PDT 24
Peak memory 206156 kb
Host smart-8b6cd671-1693-49c7-a09c-35e91f5cf39a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=117684110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.117684110
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.2313739747
Short name T1131
Test name
Test status
Simulation time 267620392 ps
CPU time 0.87 seconds
Started Jun 21 04:56:12 PM PDT 24
Finished Jun 21 04:56:14 PM PDT 24
Peak memory 205996 kb
Host smart-e1cecac1-75fb-40f3-9156-a1a5d4fb1d53
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2313739747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.2313739747
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3386318600
Short name T2466
Test name
Test status
Simulation time 241309981 ps
CPU time 0.9 seconds
Started Jun 21 04:56:07 PM PDT 24
Finished Jun 21 04:56:11 PM PDT 24
Peak memory 206060 kb
Host smart-160f2906-d282-45ca-a117-763e3f9ae3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33863
18600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3386318600
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.373092334
Short name T2341
Test name
Test status
Simulation time 10660551968 ps
CPU time 303.59 seconds
Started Jun 21 04:56:08 PM PDT 24
Finished Jun 21 05:01:14 PM PDT 24
Peak memory 206196 kb
Host smart-509442fd-b220-4460-a3dd-179a02cca291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37309
2334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.373092334
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.3183080022
Short name T1361
Test name
Test status
Simulation time 4701543556 ps
CPU time 45.73 seconds
Started Jun 21 04:56:08 PM PDT 24
Finished Jun 21 04:56:56 PM PDT 24
Peak memory 206272 kb
Host smart-4e0eb180-3ba8-4801-9e8a-883ae8337028
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3183080022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.3183080022
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.668486533
Short name T313
Test name
Test status
Simulation time 147534989 ps
CPU time 0.78 seconds
Started Jun 21 04:56:18 PM PDT 24
Finished Jun 21 04:56:20 PM PDT 24
Peak memory 206048 kb
Host smart-7b2058d6-3b0f-4f1c-825e-ed835d3deb17
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=668486533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.668486533
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2918551523
Short name T1498
Test name
Test status
Simulation time 168172707 ps
CPU time 0.77 seconds
Started Jun 21 04:56:07 PM PDT 24
Finished Jun 21 04:56:10 PM PDT 24
Peak memory 205996 kb
Host smart-ec966d0f-5ff2-4331-afb7-f3b266742dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29185
51523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2918551523
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3883166566
Short name T122
Test name
Test status
Simulation time 208384914 ps
CPU time 0.87 seconds
Started Jun 21 04:56:07 PM PDT 24
Finished Jun 21 04:56:10 PM PDT 24
Peak memory 206004 kb
Host smart-2ab3024d-195b-4709-9c89-5090cba1c636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38831
66566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3883166566
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.2971030063
Short name T1788
Test name
Test status
Simulation time 188152906 ps
CPU time 0.87 seconds
Started Jun 21 04:56:08 PM PDT 24
Finished Jun 21 04:56:12 PM PDT 24
Peak memory 206140 kb
Host smart-e229a69f-df28-4283-acd9-ddb31b447ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29710
30063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.2971030063
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3667888126
Short name T1648
Test name
Test status
Simulation time 181371352 ps
CPU time 0.83 seconds
Started Jun 21 04:56:12 PM PDT 24
Finished Jun 21 04:56:14 PM PDT 24
Peak memory 206024 kb
Host smart-d6c365ea-1181-479e-b6b1-0adab4db706f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36678
88126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3667888126
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.242517697
Short name T1772
Test name
Test status
Simulation time 163125431 ps
CPU time 0.79 seconds
Started Jun 21 04:56:09 PM PDT 24
Finished Jun 21 04:56:12 PM PDT 24
Peak memory 206048 kb
Host smart-fa83bd27-7aee-40ba-a2af-9d3c093a6bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24251
7697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.242517697
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2415166994
Short name T714
Test name
Test status
Simulation time 176340209 ps
CPU time 0.83 seconds
Started Jun 21 04:56:13 PM PDT 24
Finished Jun 21 04:56:16 PM PDT 24
Peak memory 205996 kb
Host smart-94f3bf44-6695-49fb-8f74-9f536c6a5c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24151
66994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2415166994
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.1512116143
Short name T44
Test name
Test status
Simulation time 204109900 ps
CPU time 0.92 seconds
Started Jun 21 04:56:15 PM PDT 24
Finished Jun 21 04:56:18 PM PDT 24
Peak memory 206044 kb
Host smart-c23c2f25-0e94-41b9-a2d8-53c3ba74709c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1512116143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.1512116143
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.2815907245
Short name T1499
Test name
Test status
Simulation time 150014139 ps
CPU time 0.84 seconds
Started Jun 21 04:56:19 PM PDT 24
Finished Jun 21 04:56:21 PM PDT 24
Peak memory 206032 kb
Host smart-a5f03703-e677-476d-a46f-a3d7e60c4cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28159
07245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.2815907245
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1666970641
Short name T24
Test name
Test status
Simulation time 40666668 ps
CPU time 0.67 seconds
Started Jun 21 04:56:13 PM PDT 24
Finished Jun 21 04:56:17 PM PDT 24
Peak memory 206016 kb
Host smart-39b16532-c0f9-4ee6-b293-cb311cefe018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16669
70641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1666970641
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2715000846
Short name T718
Test name
Test status
Simulation time 19838231143 ps
CPU time 45.48 seconds
Started Jun 21 04:56:08 PM PDT 24
Finished Jun 21 04:56:56 PM PDT 24
Peak memory 206368 kb
Host smart-9bdddacb-c15b-4997-b9a5-a1ca9d621969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27150
00846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2715000846
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2188565186
Short name T948
Test name
Test status
Simulation time 235311759 ps
CPU time 0.93 seconds
Started Jun 21 04:56:11 PM PDT 24
Finished Jun 21 04:56:14 PM PDT 24
Peak memory 206028 kb
Host smart-0fe8f862-9742-4dec-a996-fd733fc1d591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21885
65186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2188565186
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2438367085
Short name T551
Test name
Test status
Simulation time 190034415 ps
CPU time 0.89 seconds
Started Jun 21 04:56:13 PM PDT 24
Finished Jun 21 04:56:16 PM PDT 24
Peak memory 205920 kb
Host smart-5507bfe9-0eef-40e4-8680-660b1f3893a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24383
67085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2438367085
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.2386167883
Short name T1015
Test name
Test status
Simulation time 252541343 ps
CPU time 0.91 seconds
Started Jun 21 04:56:14 PM PDT 24
Finished Jun 21 04:56:18 PM PDT 24
Peak memory 205972 kb
Host smart-22e9de7a-67a6-4116-b987-e51ffb4969e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23861
67883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.2386167883
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.3605544382
Short name T848
Test name
Test status
Simulation time 194876312 ps
CPU time 0.92 seconds
Started Jun 21 04:56:12 PM PDT 24
Finished Jun 21 04:56:15 PM PDT 24
Peak memory 206048 kb
Host smart-e43628ca-854c-4e23-a981-b425470fddfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36055
44382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.3605544382
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.1402867171
Short name T724
Test name
Test status
Simulation time 165439794 ps
CPU time 0.9 seconds
Started Jun 21 04:56:20 PM PDT 24
Finished Jun 21 04:56:22 PM PDT 24
Peak memory 206016 kb
Host smart-57153875-146c-49ab-a0dd-be741342dd9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14028
67171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.1402867171
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.274022862
Short name T2107
Test name
Test status
Simulation time 153351210 ps
CPU time 0.8 seconds
Started Jun 21 04:56:15 PM PDT 24
Finished Jun 21 04:56:18 PM PDT 24
Peak memory 206000 kb
Host smart-ce41e184-2a07-4de7-be54-647dd5df6635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27402
2862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.274022862
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.793034089
Short name T2492
Test name
Test status
Simulation time 195096221 ps
CPU time 0.8 seconds
Started Jun 21 04:56:14 PM PDT 24
Finished Jun 21 04:56:17 PM PDT 24
Peak memory 206040 kb
Host smart-dad9089c-fb5f-4e73-9ba8-3f8265dc9e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79303
4089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.793034089
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.370185424
Short name T835
Test name
Test status
Simulation time 226536431 ps
CPU time 0.91 seconds
Started Jun 21 04:56:12 PM PDT 24
Finished Jun 21 04:56:15 PM PDT 24
Peak memory 206028 kb
Host smart-60e888e6-e773-42ea-9691-253bef44aee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37018
5424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.370185424
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.2101571216
Short name T1983
Test name
Test status
Simulation time 12151869615 ps
CPU time 350.2 seconds
Started Jun 21 04:56:13 PM PDT 24
Finished Jun 21 05:02:06 PM PDT 24
Peak memory 206232 kb
Host smart-9864e739-640f-42c2-9f16-413d16dbf2f2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2101571216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.2101571216
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.4161798604
Short name T2465
Test name
Test status
Simulation time 197334550 ps
CPU time 0.88 seconds
Started Jun 21 04:56:22 PM PDT 24
Finished Jun 21 04:56:24 PM PDT 24
Peak memory 206032 kb
Host smart-4f0e4b41-764b-45d9-97e0-de8661bd65cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41617
98604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.4161798604
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.3929943107
Short name T2050
Test name
Test status
Simulation time 150532175 ps
CPU time 0.79 seconds
Started Jun 21 04:56:14 PM PDT 24
Finished Jun 21 04:56:18 PM PDT 24
Peak memory 205952 kb
Host smart-807cafd3-627a-4b31-b894-fedc86f13fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39299
43107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3929943107
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.4150219152
Short name T1508
Test name
Test status
Simulation time 6483341511 ps
CPU time 62.66 seconds
Started Jun 21 04:56:13 PM PDT 24
Finished Jun 21 04:57:17 PM PDT 24
Peak memory 206184 kb
Host smart-ca6d4462-dcaf-41da-9876-e880846053ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41502
19152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.4150219152
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.1355683940
Short name T7
Test name
Test status
Simulation time 4300898732 ps
CPU time 5.13 seconds
Started Jun 21 04:56:14 PM PDT 24
Finished Jun 21 04:56:21 PM PDT 24
Peak memory 206268 kb
Host smart-66277df0-116a-44e1-a36f-02708ddabc81
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1355683940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.1355683940
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.3439638262
Short name T2417
Test name
Test status
Simulation time 13362620032 ps
CPU time 12.6 seconds
Started Jun 21 04:56:17 PM PDT 24
Finished Jun 21 04:56:31 PM PDT 24
Peak memory 205992 kb
Host smart-2dd2dc56-e764-477c-933b-84b8e4cf4534
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3439638262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3439638262
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.297561070
Short name T837
Test name
Test status
Simulation time 23316731991 ps
CPU time 23.94 seconds
Started Jun 21 04:56:16 PM PDT 24
Finished Jun 21 04:56:42 PM PDT 24
Peak memory 206400 kb
Host smart-3379b4b7-7e9b-47a6-ae79-1e252c139b73
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=297561070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.297561070
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.1432770336
Short name T1259
Test name
Test status
Simulation time 194065567 ps
CPU time 0.83 seconds
Started Jun 21 04:56:18 PM PDT 24
Finished Jun 21 04:56:20 PM PDT 24
Peak memory 205928 kb
Host smart-6e8a50dc-1594-4748-8bd1-f966a1389245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14327
70336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1432770336
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.1649627899
Short name T1365
Test name
Test status
Simulation time 144278271 ps
CPU time 0.73 seconds
Started Jun 21 04:56:15 PM PDT 24
Finished Jun 21 04:56:18 PM PDT 24
Peak memory 206076 kb
Host smart-edb4cc94-6996-48e7-abee-d39e62cd9601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16496
27899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.1649627899
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.2756099788
Short name T521
Test name
Test status
Simulation time 261949930 ps
CPU time 0.97 seconds
Started Jun 21 04:56:14 PM PDT 24
Finished Jun 21 04:56:18 PM PDT 24
Peak memory 206004 kb
Host smart-ff99f8b6-daa1-4546-acc5-a0b8dd4a6098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27560
99788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.2756099788
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2693171667
Short name T993
Test name
Test status
Simulation time 1349060716 ps
CPU time 3.31 seconds
Started Jun 21 04:56:21 PM PDT 24
Finished Jun 21 04:56:25 PM PDT 24
Peak memory 206268 kb
Host smart-9f419eee-9816-424a-9d3a-bf16b3758933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26931
71667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2693171667
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.3885424274
Short name T762
Test name
Test status
Simulation time 7190735579 ps
CPU time 13.69 seconds
Started Jun 21 04:56:21 PM PDT 24
Finished Jun 21 04:56:36 PM PDT 24
Peak memory 206332 kb
Host smart-87bd39f9-f4d7-4c9c-a79c-8db017378c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38854
24274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.3885424274
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.3831278551
Short name T1294
Test name
Test status
Simulation time 461581433 ps
CPU time 1.5 seconds
Started Jun 21 04:56:18 PM PDT 24
Finished Jun 21 04:56:21 PM PDT 24
Peak memory 205928 kb
Host smart-500906d3-8555-4de0-a29b-56e1b1c6c153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38312
78551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3831278551
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2646754476
Short name T1087
Test name
Test status
Simulation time 143795776 ps
CPU time 0.77 seconds
Started Jun 21 04:56:13 PM PDT 24
Finished Jun 21 04:56:17 PM PDT 24
Peak memory 206020 kb
Host smart-9f67737f-9a17-4126-88bd-61955915eb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26467
54476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2646754476
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1372679173
Short name T2325
Test name
Test status
Simulation time 97750147 ps
CPU time 0.71 seconds
Started Jun 21 04:56:14 PM PDT 24
Finished Jun 21 04:56:17 PM PDT 24
Peak memory 205964 kb
Host smart-4b4e0367-78d8-4ca8-bd57-0cfaabbf8ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13726
79173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1372679173
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1730585101
Short name T522
Test name
Test status
Simulation time 879150547 ps
CPU time 2.1 seconds
Started Jun 21 04:56:13 PM PDT 24
Finished Jun 21 04:56:17 PM PDT 24
Peak memory 206168 kb
Host smart-4b516ddb-9132-4233-8a66-14b2f6025b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17305
85101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1730585101
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3291338160
Short name T2487
Test name
Test status
Simulation time 152675902 ps
CPU time 1.35 seconds
Started Jun 21 04:56:15 PM PDT 24
Finished Jun 21 04:56:19 PM PDT 24
Peak memory 206144 kb
Host smart-3a6c389b-a444-4dc2-b261-3c53ca139232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32913
38160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3291338160
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.2369174182
Short name T645
Test name
Test status
Simulation time 157966151 ps
CPU time 0.82 seconds
Started Jun 21 04:56:25 PM PDT 24
Finished Jun 21 04:56:28 PM PDT 24
Peak memory 205996 kb
Host smart-2fcf38c2-ce49-45fa-88b9-c636f22a3420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23691
74182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2369174182
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3899412379
Short name T2016
Test name
Test status
Simulation time 145485119 ps
CPU time 0.75 seconds
Started Jun 21 04:56:27 PM PDT 24
Finished Jun 21 04:56:29 PM PDT 24
Peak memory 206016 kb
Host smart-001b43fa-edd8-43a8-8b1b-89b95776630a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38994
12379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3899412379
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2142595770
Short name T396
Test name
Test status
Simulation time 240947719 ps
CPU time 0.91 seconds
Started Jun 21 04:56:15 PM PDT 24
Finished Jun 21 04:56:18 PM PDT 24
Peak memory 206024 kb
Host smart-b45f89b0-e9d4-4ef3-8fcf-1d049b91bf94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21425
95770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2142595770
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.71929994
Short name T2470
Test name
Test status
Simulation time 224979406 ps
CPU time 0.88 seconds
Started Jun 21 04:56:15 PM PDT 24
Finished Jun 21 04:56:18 PM PDT 24
Peak memory 206028 kb
Host smart-46a8f944-92e2-4b94-83a1-aa03bad53fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71929
994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.71929994
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.3888245431
Short name T937
Test name
Test status
Simulation time 23286805308 ps
CPU time 23.23 seconds
Started Jun 21 04:56:13 PM PDT 24
Finished Jun 21 04:56:38 PM PDT 24
Peak memory 206020 kb
Host smart-05d41a15-d9f9-46f8-a008-f4abe88d5515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38882
45431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.3888245431
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.3709073038
Short name T2040
Test name
Test status
Simulation time 3331203308 ps
CPU time 3.94 seconds
Started Jun 21 04:56:16 PM PDT 24
Finished Jun 21 04:56:22 PM PDT 24
Peak memory 206140 kb
Host smart-c1304eb0-271f-45d5-8d4f-285aaabce054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37090
73038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3709073038
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.2221184531
Short name T2422
Test name
Test status
Simulation time 14623685155 ps
CPU time 417.5 seconds
Started Jun 21 04:56:24 PM PDT 24
Finished Jun 21 05:03:23 PM PDT 24
Peak memory 206252 kb
Host smart-ba96348a-67b8-4c50-9d06-797cebf9a841
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2221184531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.2221184531
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.3709043526
Short name T786
Test name
Test status
Simulation time 250314184 ps
CPU time 0.9 seconds
Started Jun 21 04:56:27 PM PDT 24
Finished Jun 21 04:56:29 PM PDT 24
Peak memory 206048 kb
Host smart-43ae68d3-e63b-4d29-a78e-1ba606ed8ea9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3709043526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.3709043526
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.176661758
Short name T2103
Test name
Test status
Simulation time 189951458 ps
CPU time 0.98 seconds
Started Jun 21 04:56:20 PM PDT 24
Finished Jun 21 04:56:22 PM PDT 24
Peak memory 206052 kb
Host smart-afc809f3-0a17-469e-892e-548e2e609671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17666
1758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.176661758
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3450194520
Short name T1702
Test name
Test status
Simulation time 7076705870 ps
CPU time 199.61 seconds
Started Jun 21 04:56:29 PM PDT 24
Finished Jun 21 04:59:49 PM PDT 24
Peak memory 206140 kb
Host smart-a119c6cd-7d91-449f-9c61-0d03d02b31eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34501
94520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3450194520
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2776070991
Short name T651
Test name
Test status
Simulation time 10283932090 ps
CPU time 91.95 seconds
Started Jun 21 04:56:26 PM PDT 24
Finished Jun 21 04:58:00 PM PDT 24
Peak memory 206252 kb
Host smart-7379f7d4-3f2f-4598-ae9d-3b778aa9668f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2776070991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2776070991
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.760530249
Short name T2502
Test name
Test status
Simulation time 226505062 ps
CPU time 0.86 seconds
Started Jun 21 04:56:24 PM PDT 24
Finished Jun 21 04:56:26 PM PDT 24
Peak memory 205992 kb
Host smart-d12c03f2-36d1-45de-b5f3-f73f6923ecaa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=760530249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.760530249
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3485327407
Short name T2244
Test name
Test status
Simulation time 150128452 ps
CPU time 0.76 seconds
Started Jun 21 04:56:20 PM PDT 24
Finished Jun 21 04:56:21 PM PDT 24
Peak memory 206032 kb
Host smart-ca410fbc-d997-44a4-964f-166cc949cc8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34853
27407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3485327407
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.913978332
Short name T121
Test name
Test status
Simulation time 175325340 ps
CPU time 0.84 seconds
Started Jun 21 04:56:25 PM PDT 24
Finished Jun 21 04:56:28 PM PDT 24
Peak memory 206020 kb
Host smart-ed726ab9-f33c-4596-9b96-278ca1cb6a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91397
8332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.913978332
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.2141624013
Short name T1420
Test name
Test status
Simulation time 186947097 ps
CPU time 0.83 seconds
Started Jun 21 04:56:25 PM PDT 24
Finished Jun 21 04:56:27 PM PDT 24
Peak memory 205960 kb
Host smart-372e9696-49cc-43fd-9b56-f803f6dfcc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21416
24013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.2141624013
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.4178703934
Short name T596
Test name
Test status
Simulation time 204072265 ps
CPU time 0.89 seconds
Started Jun 21 04:56:27 PM PDT 24
Finished Jun 21 04:56:30 PM PDT 24
Peak memory 206004 kb
Host smart-fde6b7e6-5c43-42c8-8a90-dc9a34fd1f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41787
03934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.4178703934
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.959215505
Short name T216
Test name
Test status
Simulation time 231800107 ps
CPU time 0.85 seconds
Started Jun 21 04:56:28 PM PDT 24
Finished Jun 21 04:56:30 PM PDT 24
Peak memory 206024 kb
Host smart-788fa8e0-a92a-49ed-85e8-596c5231610e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95921
5505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.959215505
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3440160907
Short name T182
Test name
Test status
Simulation time 178143265 ps
CPU time 0.79 seconds
Started Jun 21 04:56:27 PM PDT 24
Finished Jun 21 04:56:30 PM PDT 24
Peak memory 206048 kb
Host smart-52663a8f-e50a-41a4-a383-41c35f0844b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34401
60907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3440160907
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.3796092220
Short name T1457
Test name
Test status
Simulation time 271204830 ps
CPU time 0.93 seconds
Started Jun 21 04:56:26 PM PDT 24
Finished Jun 21 04:56:29 PM PDT 24
Peak memory 205996 kb
Host smart-fb77e838-05cc-4012-8bf0-cb53029a4527
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3796092220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.3796092220
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1464155086
Short name T2221
Test name
Test status
Simulation time 175791389 ps
CPU time 0.78 seconds
Started Jun 21 04:56:25 PM PDT 24
Finished Jun 21 04:56:28 PM PDT 24
Peak memory 205944 kb
Host smart-8b0ba9a9-1fe6-4525-84f6-d605a811122e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14641
55086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1464155086
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.344242293
Short name T1665
Test name
Test status
Simulation time 35571481 ps
CPU time 0.68 seconds
Started Jun 21 04:56:24 PM PDT 24
Finished Jun 21 04:56:26 PM PDT 24
Peak memory 206028 kb
Host smart-f2735e47-d493-4657-bc71-b59b1704d219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34424
2293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.344242293
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.986019276
Short name T1914
Test name
Test status
Simulation time 14574948862 ps
CPU time 30.31 seconds
Started Jun 21 04:56:26 PM PDT 24
Finished Jun 21 04:56:59 PM PDT 24
Peak memory 206356 kb
Host smart-0ffba2e4-6411-43af-bea3-36a612302622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98601
9276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.986019276
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3085259903
Short name T1752
Test name
Test status
Simulation time 189999258 ps
CPU time 0.83 seconds
Started Jun 21 04:56:27 PM PDT 24
Finished Jun 21 04:56:30 PM PDT 24
Peak memory 205976 kb
Host smart-dc3d73da-756c-430b-9a5a-bd3a9aeac56e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30852
59903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3085259903
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.799749746
Short name T1878
Test name
Test status
Simulation time 215473334 ps
CPU time 0.92 seconds
Started Jun 21 04:56:25 PM PDT 24
Finished Jun 21 04:56:27 PM PDT 24
Peak memory 206000 kb
Host smart-a8a56347-5265-4b0d-b60f-7c9162c3a34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79974
9746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.799749746
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.1669106351
Short name T938
Test name
Test status
Simulation time 228576233 ps
CPU time 0.95 seconds
Started Jun 21 04:56:26 PM PDT 24
Finished Jun 21 04:56:29 PM PDT 24
Peak memory 206152 kb
Host smart-51dbf16b-3d51-4dba-a250-0b2438678054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16691
06351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.1669106351
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.3224394389
Short name T956
Test name
Test status
Simulation time 196717017 ps
CPU time 0.82 seconds
Started Jun 21 04:56:26 PM PDT 24
Finished Jun 21 04:56:29 PM PDT 24
Peak memory 205948 kb
Host smart-fe394ad5-9275-4f29-badb-399654959bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32243
94389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.3224394389
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.695638285
Short name T613
Test name
Test status
Simulation time 183242361 ps
CPU time 0.81 seconds
Started Jun 21 04:56:24 PM PDT 24
Finished Jun 21 04:56:26 PM PDT 24
Peak memory 205928 kb
Host smart-3a60345f-22db-4790-adec-2e3a29e6c5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69563
8285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.695638285
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.4117371015
Short name T655
Test name
Test status
Simulation time 162854899 ps
CPU time 0.78 seconds
Started Jun 21 04:56:29 PM PDT 24
Finished Jun 21 04:56:31 PM PDT 24
Peak memory 205924 kb
Host smart-470225d0-e0d1-4015-a440-c0befdbaa686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41173
71015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.4117371015
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3317060954
Short name T334
Test name
Test status
Simulation time 164882475 ps
CPU time 0.79 seconds
Started Jun 21 04:56:27 PM PDT 24
Finished Jun 21 04:56:29 PM PDT 24
Peak memory 206024 kb
Host smart-c80866c7-fb86-4c19-b70d-cbedeba28e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33170
60954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3317060954
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2824708112
Short name T1301
Test name
Test status
Simulation time 220012583 ps
CPU time 0.92 seconds
Started Jun 21 04:56:15 PM PDT 24
Finished Jun 21 04:56:19 PM PDT 24
Peak memory 206080 kb
Host smart-c7ead489-c156-495e-ade9-349caae19df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28247
08112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2824708112
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.3567150415
Short name T2112
Test name
Test status
Simulation time 12848651569 ps
CPU time 97.33 seconds
Started Jun 21 04:56:25 PM PDT 24
Finished Jun 21 04:58:05 PM PDT 24
Peak memory 206260 kb
Host smart-d3f30a12-8780-474a-88a8-08a5a101a7a7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3567150415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.3567150415
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.1319621411
Short name T2391
Test name
Test status
Simulation time 211291775 ps
CPU time 0.87 seconds
Started Jun 21 04:56:25 PM PDT 24
Finished Jun 21 04:56:28 PM PDT 24
Peak memory 206028 kb
Host smart-5e53035d-7987-4153-afbf-5150148d8b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13196
21411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.1319621411
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1006117572
Short name T791
Test name
Test status
Simulation time 158182957 ps
CPU time 0.83 seconds
Started Jun 21 04:56:24 PM PDT 24
Finished Jun 21 04:56:26 PM PDT 24
Peak memory 206000 kb
Host smart-d875f8b8-b422-4757-9d2c-d4d2f5eaeea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10061
17572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1006117572
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.1357655985
Short name T1865
Test name
Test status
Simulation time 10322509806 ps
CPU time 284.44 seconds
Started Jun 21 04:56:26 PM PDT 24
Finished Jun 21 05:01:12 PM PDT 24
Peak memory 206276 kb
Host smart-c01bf9de-d8ed-4215-8bb2-46f7073eb5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13576
55985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.1357655985
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2702165091
Short name T876
Test name
Test status
Simulation time 3997982748 ps
CPU time 5.78 seconds
Started Jun 21 04:56:26 PM PDT 24
Finished Jun 21 04:56:34 PM PDT 24
Peak memory 206316 kb
Host smart-42da7ce6-3eb9-409e-bec6-1df712cefd7a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2702165091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.2702165091
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.2663088778
Short name T1652
Test name
Test status
Simulation time 13427050347 ps
CPU time 12.87 seconds
Started Jun 21 04:56:26 PM PDT 24
Finished Jun 21 04:56:41 PM PDT 24
Peak memory 206260 kb
Host smart-be23ab34-7239-4b29-b8d6-99a0b3429002
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2663088778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.2663088778
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.950305317
Short name T464
Test name
Test status
Simulation time 23379079844 ps
CPU time 22.85 seconds
Started Jun 21 04:56:27 PM PDT 24
Finished Jun 21 04:56:51 PM PDT 24
Peak memory 206088 kb
Host smart-a97994ac-8135-46bd-b571-c12013ff6ff9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=950305317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.950305317
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1476654044
Short name T497
Test name
Test status
Simulation time 188169725 ps
CPU time 0.83 seconds
Started Jun 21 04:56:25 PM PDT 24
Finished Jun 21 04:56:28 PM PDT 24
Peak memory 205956 kb
Host smart-8d5c20f2-4fca-4ca3-85b9-d29a746ea110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14766
54044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1476654044
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.588122020
Short name T1104
Test name
Test status
Simulation time 148049389 ps
CPU time 0.79 seconds
Started Jun 21 04:56:38 PM PDT 24
Finished Jun 21 04:56:41 PM PDT 24
Peak memory 205948 kb
Host smart-776fdd7c-b2aa-4e15-a41a-3ab687e5a006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58812
2020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.588122020
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.4068423547
Short name T172
Test name
Test status
Simulation time 321363917 ps
CPU time 1.09 seconds
Started Jun 21 04:56:34 PM PDT 24
Finished Jun 21 04:56:36 PM PDT 24
Peak memory 205972 kb
Host smart-c2def808-b494-40ca-8aae-4d4f3663ed1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40684
23547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.4068423547
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2568773005
Short name T176
Test name
Test status
Simulation time 1080293006 ps
CPU time 2.53 seconds
Started Jun 21 04:56:35 PM PDT 24
Finished Jun 21 04:56:38 PM PDT 24
Peak memory 206308 kb
Host smart-aff45330-cba2-440c-8016-15039df5e191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25687
73005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2568773005
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3761033185
Short name T1257
Test name
Test status
Simulation time 8145489093 ps
CPU time 17.5 seconds
Started Jun 21 04:56:39 PM PDT 24
Finished Jun 21 04:56:58 PM PDT 24
Peak memory 206076 kb
Host smart-d626607a-fc7b-4437-bd84-cc00e6fd721d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37610
33185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3761033185
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3647737390
Short name T2254
Test name
Test status
Simulation time 477666649 ps
CPU time 1.52 seconds
Started Jun 21 04:56:38 PM PDT 24
Finished Jun 21 04:56:41 PM PDT 24
Peak memory 206028 kb
Host smart-2219d536-15b8-4139-9582-9160f4d8f063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36477
37390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3647737390
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.1470997483
Short name T536
Test name
Test status
Simulation time 197945832 ps
CPU time 0.79 seconds
Started Jun 21 04:56:35 PM PDT 24
Finished Jun 21 04:56:36 PM PDT 24
Peak memory 205960 kb
Host smart-c49d804d-f116-4e80-982a-2d510352e028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14709
97483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1470997483
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.1924596870
Short name T879
Test name
Test status
Simulation time 54798590 ps
CPU time 0.69 seconds
Started Jun 21 04:56:36 PM PDT 24
Finished Jun 21 04:56:37 PM PDT 24
Peak memory 206016 kb
Host smart-a2afca93-e7cc-4703-a723-cdd2b9650a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19245
96870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1924596870
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.1690453069
Short name T907
Test name
Test status
Simulation time 739498973 ps
CPU time 1.8 seconds
Started Jun 21 04:56:41 PM PDT 24
Finished Jun 21 04:56:45 PM PDT 24
Peak memory 206208 kb
Host smart-3e79e35a-e3c5-4b85-809f-e6e19eac1239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16904
53069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.1690453069
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3277745702
Short name T1367
Test name
Test status
Simulation time 348335776 ps
CPU time 2.19 seconds
Started Jun 21 04:56:37 PM PDT 24
Finished Jun 21 04:56:41 PM PDT 24
Peak memory 206272 kb
Host smart-7d2d0f33-132d-4809-a175-13616c95a988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32777
45702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3277745702
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2799350571
Short name T676
Test name
Test status
Simulation time 228710163 ps
CPU time 0.92 seconds
Started Jun 21 04:56:41 PM PDT 24
Finished Jun 21 04:56:44 PM PDT 24
Peak memory 205960 kb
Host smart-79b94811-2bdf-4238-a3b5-61f320464857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27993
50571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2799350571
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2066614979
Short name T1624
Test name
Test status
Simulation time 180477867 ps
CPU time 0.79 seconds
Started Jun 21 04:56:39 PM PDT 24
Finished Jun 21 04:56:42 PM PDT 24
Peak memory 205960 kb
Host smart-6a4a9efa-4200-4cd6-90b7-763b9827486d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20666
14979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2066614979
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1473553635
Short name T922
Test name
Test status
Simulation time 169355801 ps
CPU time 0.82 seconds
Started Jun 21 04:56:36 PM PDT 24
Finished Jun 21 04:56:37 PM PDT 24
Peak memory 206016 kb
Host smart-001ce274-a45d-450a-b85d-02b5a6eb4779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14735
53635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1473553635
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.3474481378
Short name T1545
Test name
Test status
Simulation time 4729897048 ps
CPU time 34.68 seconds
Started Jun 21 04:56:38 PM PDT 24
Finished Jun 21 04:57:15 PM PDT 24
Peak memory 206264 kb
Host smart-6cada790-ed5c-491e-93aa-c7c09ffef345
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3474481378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.3474481378
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.634851835
Short name T1178
Test name
Test status
Simulation time 171944439 ps
CPU time 0.82 seconds
Started Jun 21 04:56:39 PM PDT 24
Finished Jun 21 04:56:42 PM PDT 24
Peak memory 205952 kb
Host smart-1dbcc297-ab8c-468f-b838-1a5d95f02b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63485
1835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.634851835
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.3061944034
Short name T541
Test name
Test status
Simulation time 23332995685 ps
CPU time 26.4 seconds
Started Jun 21 04:56:37 PM PDT 24
Finished Jun 21 04:57:05 PM PDT 24
Peak memory 206080 kb
Host smart-c17b2bc2-f5dc-4f21-af06-d9442707d5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30619
44034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.3061944034
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.3983508092
Short name T964
Test name
Test status
Simulation time 3302526385 ps
CPU time 4.46 seconds
Started Jun 21 04:56:38 PM PDT 24
Finished Jun 21 04:56:44 PM PDT 24
Peak memory 206060 kb
Host smart-8885b4c4-213d-477d-9395-c0336cab3c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39835
08092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.3983508092
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.1681988496
Short name T798
Test name
Test status
Simulation time 4509815102 ps
CPU time 126.04 seconds
Started Jun 21 04:56:38 PM PDT 24
Finished Jun 21 04:58:47 PM PDT 24
Peak memory 205964 kb
Host smart-19589a18-1ce0-4a52-b63c-d25a45a1a52d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1681988496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.1681988496
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.1942182038
Short name T2437
Test name
Test status
Simulation time 278439106 ps
CPU time 1.04 seconds
Started Jun 21 04:56:37 PM PDT 24
Finished Jun 21 04:56:40 PM PDT 24
Peak memory 206048 kb
Host smart-fd90b81b-1eea-4aa7-8508-52d5d31b0978
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1942182038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.1942182038
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3930446257
Short name T2378
Test name
Test status
Simulation time 218230663 ps
CPU time 0.9 seconds
Started Jun 21 04:56:35 PM PDT 24
Finished Jun 21 04:56:37 PM PDT 24
Peak memory 205980 kb
Host smart-1968b49e-16ab-48bb-9884-fa535c845d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39304
46257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3930446257
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.2948624259
Short name T737
Test name
Test status
Simulation time 9144345926 ps
CPU time 63.78 seconds
Started Jun 21 04:56:39 PM PDT 24
Finished Jun 21 04:57:45 PM PDT 24
Peak memory 206276 kb
Host smart-ac9eae37-1305-4fc8-b511-92b213f9d8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29486
24259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.2948624259
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.2586302259
Short name T974
Test name
Test status
Simulation time 4620623877 ps
CPU time 42.08 seconds
Started Jun 21 04:56:42 PM PDT 24
Finished Jun 21 04:57:26 PM PDT 24
Peak memory 205644 kb
Host smart-e57c09e6-954e-49fd-9601-70dd442d1e4d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2586302259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.2586302259
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.3335837026
Short name T294
Test name
Test status
Simulation time 205473686 ps
CPU time 0.91 seconds
Started Jun 21 04:56:39 PM PDT 24
Finished Jun 21 04:56:42 PM PDT 24
Peak memory 206048 kb
Host smart-1b274ec5-4bdc-4012-b060-735f109da652
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3335837026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3335837026
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.628048959
Short name T867
Test name
Test status
Simulation time 152190821 ps
CPU time 0.78 seconds
Started Jun 21 04:56:37 PM PDT 24
Finished Jun 21 04:56:39 PM PDT 24
Peak memory 206012 kb
Host smart-c95f23aa-b8b2-4806-8deb-27461657f98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62804
8959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.628048959
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2206594119
Short name T1592
Test name
Test status
Simulation time 170071061 ps
CPU time 0.82 seconds
Started Jun 21 04:56:40 PM PDT 24
Finished Jun 21 04:56:43 PM PDT 24
Peak memory 206020 kb
Host smart-0bf5fa9e-78f8-42c9-9828-679dda849eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22065
94119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2206594119
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.273615380
Short name T1971
Test name
Test status
Simulation time 168673697 ps
CPU time 0.84 seconds
Started Jun 21 04:56:39 PM PDT 24
Finished Jun 21 04:56:42 PM PDT 24
Peak memory 205944 kb
Host smart-fb2d73e2-d3a9-4123-93b2-9ad31ff711b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27361
5380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.273615380
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.767750564
Short name T304
Test name
Test status
Simulation time 175175102 ps
CPU time 0.8 seconds
Started Jun 21 04:56:36 PM PDT 24
Finished Jun 21 04:56:38 PM PDT 24
Peak memory 205960 kb
Host smart-a73e411a-ac60-418d-bdd3-9e218d023e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76775
0564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.767750564
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2363004571
Short name T850
Test name
Test status
Simulation time 148550393 ps
CPU time 0.73 seconds
Started Jun 21 04:56:37 PM PDT 24
Finished Jun 21 04:56:40 PM PDT 24
Peak memory 205992 kb
Host smart-26184dcc-c456-4cf4-904a-deb7746fde91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23630
04571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2363004571
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.1200016478
Short name T2379
Test name
Test status
Simulation time 254771805 ps
CPU time 0.99 seconds
Started Jun 21 04:56:36 PM PDT 24
Finished Jun 21 04:56:38 PM PDT 24
Peak memory 205984 kb
Host smart-d93c5ceb-cbf7-4284-ad29-89002f555144
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1200016478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.1200016478
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.156031497
Short name T2028
Test name
Test status
Simulation time 145295139 ps
CPU time 0.78 seconds
Started Jun 21 04:56:38 PM PDT 24
Finished Jun 21 04:56:41 PM PDT 24
Peak memory 206044 kb
Host smart-ce9a300f-322d-453a-98de-d8a9b6eb1f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15603
1497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.156031497
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.423781405
Short name T1515
Test name
Test status
Simulation time 35053054 ps
CPU time 0.66 seconds
Started Jun 21 04:56:38 PM PDT 24
Finished Jun 21 04:56:41 PM PDT 24
Peak memory 205736 kb
Host smart-17b32778-7dc2-4495-978a-93a206982bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42378
1405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.423781405
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2345012797
Short name T2459
Test name
Test status
Simulation time 9591653260 ps
CPU time 22.74 seconds
Started Jun 21 04:56:37 PM PDT 24
Finished Jun 21 04:57:01 PM PDT 24
Peak memory 206316 kb
Host smart-a20b6a38-8177-4bc6-bded-6f42774ab24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23450
12797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2345012797
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.206921892
Short name T569
Test name
Test status
Simulation time 145287161 ps
CPU time 0.78 seconds
Started Jun 21 04:56:38 PM PDT 24
Finished Jun 21 04:56:40 PM PDT 24
Peak memory 205752 kb
Host smart-336d0696-5bba-4dc4-886f-69533d9554ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20692
1892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.206921892
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.472992506
Short name T2085
Test name
Test status
Simulation time 293180272 ps
CPU time 0.93 seconds
Started Jun 21 04:56:38 PM PDT 24
Finished Jun 21 04:56:41 PM PDT 24
Peak memory 205808 kb
Host smart-8997e5f8-7322-4c32-8d7c-700bbb32037c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47299
2506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.472992506
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.3938051508
Short name T299
Test name
Test status
Simulation time 285422849 ps
CPU time 0.95 seconds
Started Jun 21 04:56:39 PM PDT 24
Finished Jun 21 04:56:42 PM PDT 24
Peak memory 205932 kb
Host smart-59e8cfce-f51e-4cb9-ab71-c6bf2aca3b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39380
51508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3938051508
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.4092236064
Short name T740
Test name
Test status
Simulation time 195823183 ps
CPU time 0.88 seconds
Started Jun 21 04:56:40 PM PDT 24
Finished Jun 21 04:56:43 PM PDT 24
Peak memory 205540 kb
Host smart-b3510bf9-c0b2-4b5d-b110-ad987d6647ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40922
36064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.4092236064
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.2182218804
Short name T1748
Test name
Test status
Simulation time 148224003 ps
CPU time 0.8 seconds
Started Jun 21 04:56:38 PM PDT 24
Finished Jun 21 04:56:41 PM PDT 24
Peak memory 206012 kb
Host smart-a0fca464-cc52-464f-bafd-98f2de8301b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21822
18804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2182218804
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2420073738
Short name T2090
Test name
Test status
Simulation time 153750569 ps
CPU time 0.78 seconds
Started Jun 21 04:56:37 PM PDT 24
Finished Jun 21 04:56:39 PM PDT 24
Peak memory 206040 kb
Host smart-fc07eeac-fb1f-495d-b332-b18fffd1e66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24200
73738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2420073738
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.828963472
Short name T1657
Test name
Test status
Simulation time 146456532 ps
CPU time 0.79 seconds
Started Jun 21 04:56:38 PM PDT 24
Finished Jun 21 04:56:40 PM PDT 24
Peak memory 205940 kb
Host smart-5693097e-9658-4165-901f-31bcda16e935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82896
3472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.828963472
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3085833220
Short name T1345
Test name
Test status
Simulation time 224331231 ps
CPU time 0.91 seconds
Started Jun 21 04:56:25 PM PDT 24
Finished Jun 21 04:56:28 PM PDT 24
Peak memory 206028 kb
Host smart-bdee046b-e99e-4b1b-b8ac-055c4ba074b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30858
33220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3085833220
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.225127570
Short name T2381
Test name
Test status
Simulation time 8888050285 ps
CPU time 233.17 seconds
Started Jun 21 04:56:38 PM PDT 24
Finished Jun 21 05:00:33 PM PDT 24
Peak memory 206180 kb
Host smart-7d853d0e-63f9-4b2b-b053-f48eb014d34f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=225127570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.225127570
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.2695874646
Short name T680
Test name
Test status
Simulation time 148648844 ps
CPU time 0.79 seconds
Started Jun 21 04:56:41 PM PDT 24
Finished Jun 21 04:56:44 PM PDT 24
Peak memory 206080 kb
Host smart-9abcb24f-0968-436b-9f86-e8039a195c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26958
74646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2695874646
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3716816608
Short name T398
Test name
Test status
Simulation time 151614435 ps
CPU time 0.83 seconds
Started Jun 21 04:56:41 PM PDT 24
Finished Jun 21 04:56:44 PM PDT 24
Peak memory 205956 kb
Host smart-8a857ad6-2aac-41fa-9602-d83176409467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37168
16608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3716816608
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.2924193584
Short name T607
Test name
Test status
Simulation time 12528949563 ps
CPU time 93.72 seconds
Started Jun 21 04:56:40 PM PDT 24
Finished Jun 21 04:58:16 PM PDT 24
Peak memory 206148 kb
Host smart-7f5bd7d9-8a95-47bd-81ac-655d841c9ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29241
93584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.2924193584
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.2449340918
Short name T486
Test name
Test status
Simulation time 3610309659 ps
CPU time 4.38 seconds
Started Jun 21 04:56:37 PM PDT 24
Finished Jun 21 04:56:43 PM PDT 24
Peak memory 206012 kb
Host smart-60158ffc-b4b4-4836-a1df-f347fb1407af
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2449340918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.2449340918
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.3298822880
Short name T1312
Test name
Test status
Simulation time 13504864124 ps
CPU time 12.38 seconds
Started Jun 21 04:56:39 PM PDT 24
Finished Jun 21 04:56:54 PM PDT 24
Peak memory 206212 kb
Host smart-d7c85858-ce3b-4aa7-8e0d-424a6073dee2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3298822880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.3298822880
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.701357406
Short name T496
Test name
Test status
Simulation time 23434121001 ps
CPU time 21.14 seconds
Started Jun 21 04:56:39 PM PDT 24
Finished Jun 21 04:57:03 PM PDT 24
Peak memory 206256 kb
Host smart-d069294b-d388-415d-a9cc-aa6abfd60577
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=701357406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.701357406
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.1098634852
Short name T966
Test name
Test status
Simulation time 158931741 ps
CPU time 0.84 seconds
Started Jun 21 04:56:41 PM PDT 24
Finished Jun 21 04:56:44 PM PDT 24
Peak memory 206080 kb
Host smart-0b507ecd-9932-4e3a-a2e3-8b44ec223c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10986
34852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1098634852
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.3125856458
Short name T672
Test name
Test status
Simulation time 464152631 ps
CPU time 1.49 seconds
Started Jun 21 04:56:42 PM PDT 24
Finished Jun 21 04:56:46 PM PDT 24
Peak memory 205508 kb
Host smart-54844688-cab6-4288-b625-5247f5547d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31258
56458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.3125856458
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.483844568
Short name T107
Test name
Test status
Simulation time 982117551 ps
CPU time 2.19 seconds
Started Jun 21 04:56:40 PM PDT 24
Finished Jun 21 04:56:44 PM PDT 24
Peak memory 205776 kb
Host smart-4f736743-726b-4a19-9947-a7a7cb9b4be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48384
4568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.483844568
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.2901825340
Short name T2162
Test name
Test status
Simulation time 17027935540 ps
CPU time 30.49 seconds
Started Jun 21 04:56:38 PM PDT 24
Finished Jun 21 04:57:11 PM PDT 24
Peak memory 206312 kb
Host smart-2bd9582d-de7f-4f1c-9ab4-8a4e73538a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29018
25340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.2901825340
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.569365559
Short name T779
Test name
Test status
Simulation time 504367225 ps
CPU time 1.55 seconds
Started Jun 21 04:56:36 PM PDT 24
Finished Jun 21 04:56:38 PM PDT 24
Peak memory 205960 kb
Host smart-8b606b1a-e879-4913-b8da-7232c872caa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56936
5559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.569365559
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.878814128
Short name T781
Test name
Test status
Simulation time 153468894 ps
CPU time 0.76 seconds
Started Jun 21 04:56:37 PM PDT 24
Finished Jun 21 04:56:39 PM PDT 24
Peak memory 205976 kb
Host smart-76897caa-c793-49da-8420-2b3b6c1ba834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87881
4128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.878814128
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.3671999133
Short name T2210
Test name
Test status
Simulation time 44189641 ps
CPU time 0.72 seconds
Started Jun 21 04:56:40 PM PDT 24
Finished Jun 21 04:56:43 PM PDT 24
Peak memory 205952 kb
Host smart-0b2d8d34-5743-42d9-8967-6f061ac65354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36719
99133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3671999133
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1243489634
Short name T1296
Test name
Test status
Simulation time 948369662 ps
CPU time 2.53 seconds
Started Jun 21 04:56:36 PM PDT 24
Finished Jun 21 04:56:40 PM PDT 24
Peak memory 206184 kb
Host smart-57eb34f1-848c-4872-a700-816650b5b07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12434
89634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1243489634
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3343496200
Short name T532
Test name
Test status
Simulation time 191826732 ps
CPU time 1.66 seconds
Started Jun 21 04:56:39 PM PDT 24
Finished Jun 21 04:56:43 PM PDT 24
Peak memory 206124 kb
Host smart-916481d0-0abe-4488-a222-d8a9b235bc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33434
96200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3343496200
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1249189717
Short name T113
Test name
Test status
Simulation time 224856682 ps
CPU time 0.93 seconds
Started Jun 21 04:56:46 PM PDT 24
Finished Jun 21 04:56:49 PM PDT 24
Peak memory 206004 kb
Host smart-b387ac2f-5788-4346-8a2b-de25dd0ce153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12491
89717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1249189717
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.67765366
Short name T2317
Test name
Test status
Simulation time 148659160 ps
CPU time 0.74 seconds
Started Jun 21 04:56:49 PM PDT 24
Finished Jun 21 04:56:51 PM PDT 24
Peak memory 205960 kb
Host smart-9b45b326-095d-4909-9d25-8ada588e643e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67765
366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.67765366
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.3067654472
Short name T2097
Test name
Test status
Simulation time 209925241 ps
CPU time 0.87 seconds
Started Jun 21 04:56:36 PM PDT 24
Finished Jun 21 04:56:38 PM PDT 24
Peak memory 205984 kb
Host smart-10ae43d8-ee31-4b5d-893c-57c2115646aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30676
54472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.3067654472
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.1964929386
Short name T1999
Test name
Test status
Simulation time 7230561760 ps
CPU time 207.34 seconds
Started Jun 21 04:56:39 PM PDT 24
Finished Jun 21 05:00:09 PM PDT 24
Peak memory 206192 kb
Host smart-95e8d4dc-6b03-4770-9b7f-97e5aa7425c1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1964929386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.1964929386
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3880946571
Short name T862
Test name
Test status
Simulation time 241687925 ps
CPU time 0.9 seconds
Started Jun 21 04:56:39 PM PDT 24
Finished Jun 21 04:56:42 PM PDT 24
Peak memory 206028 kb
Host smart-6a20b6e8-10e2-427a-89ee-c0e1db574d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38809
46571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3880946571
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.1230370230
Short name T694
Test name
Test status
Simulation time 23292257825 ps
CPU time 25.32 seconds
Started Jun 21 04:56:40 PM PDT 24
Finished Jun 21 04:57:07 PM PDT 24
Peak memory 206088 kb
Host smart-1030d816-754b-4a76-b77b-63ad1f00782a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12303
70230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.1230370230
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1720431354
Short name T2430
Test name
Test status
Simulation time 3336849997 ps
CPU time 4.47 seconds
Started Jun 21 04:56:47 PM PDT 24
Finished Jun 21 04:56:53 PM PDT 24
Peak memory 206084 kb
Host smart-60dff073-b92f-4702-9cbf-9d64accc8e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17204
31354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1720431354
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1553883803
Short name T475
Test name
Test status
Simulation time 10984274282 ps
CPU time 102.63 seconds
Started Jun 21 04:56:47 PM PDT 24
Finished Jun 21 04:58:32 PM PDT 24
Peak memory 206272 kb
Host smart-853eb685-75dd-491a-81a5-c42d337abe09
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1553883803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1553883803
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.2952946891
Short name T1558
Test name
Test status
Simulation time 274479314 ps
CPU time 0.95 seconds
Started Jun 21 04:56:49 PM PDT 24
Finished Jun 21 04:56:52 PM PDT 24
Peak memory 205988 kb
Host smart-d04e9020-be2c-456b-9258-3253cf058cfc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2952946891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.2952946891
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1789744723
Short name T2121
Test name
Test status
Simulation time 206609532 ps
CPU time 0.86 seconds
Started Jun 21 04:56:50 PM PDT 24
Finished Jun 21 04:56:52 PM PDT 24
Peak memory 205900 kb
Host smart-7d81a43b-6e47-467b-83fa-f8ad89ecd793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17897
44723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1789744723
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.2763031221
Short name T1958
Test name
Test status
Simulation time 10011838594 ps
CPU time 104.14 seconds
Started Jun 21 04:56:44 PM PDT 24
Finished Jun 21 04:58:29 PM PDT 24
Peak memory 206228 kb
Host smart-cecbb0b0-78ef-40e3-aaf8-d61cae9355d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27630
31221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.2763031221
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1978271525
Short name T1557
Test name
Test status
Simulation time 4875619876 ps
CPU time 36.24 seconds
Started Jun 21 04:56:43 PM PDT 24
Finished Jun 21 04:57:21 PM PDT 24
Peak memory 206272 kb
Host smart-9ddd3c07-9e0f-451d-b66d-cfa0ef74de0a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1978271525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1978271525
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.3136897202
Short name T957
Test name
Test status
Simulation time 166006678 ps
CPU time 0.75 seconds
Started Jun 21 04:56:45 PM PDT 24
Finished Jun 21 04:56:47 PM PDT 24
Peak memory 206044 kb
Host smart-e82fc5e5-856f-412a-874a-ec951cd44216
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3136897202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3136897202
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.610327288
Short name T1974
Test name
Test status
Simulation time 163866573 ps
CPU time 0.82 seconds
Started Jun 21 04:56:45 PM PDT 24
Finished Jun 21 04:56:48 PM PDT 24
Peak memory 205976 kb
Host smart-e03ac37e-626c-47a4-9e32-4b926124fe69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61032
7288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.610327288
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2456668430
Short name T2241
Test name
Test status
Simulation time 182794878 ps
CPU time 0.87 seconds
Started Jun 21 04:56:44 PM PDT 24
Finished Jun 21 04:56:46 PM PDT 24
Peak memory 205956 kb
Host smart-dba9234b-18c2-497d-a8dd-0350ae6b7822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24566
68430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2456668430
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3639682746
Short name T869
Test name
Test status
Simulation time 194760715 ps
CPU time 0.85 seconds
Started Jun 21 04:56:45 PM PDT 24
Finished Jun 21 04:56:47 PM PDT 24
Peak memory 205984 kb
Host smart-8fc757b8-586e-479d-82f4-13f904fb5e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36396
82746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3639682746
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3104088318
Short name T507
Test name
Test status
Simulation time 205624255 ps
CPU time 0.87 seconds
Started Jun 21 04:56:49 PM PDT 24
Finished Jun 21 04:56:52 PM PDT 24
Peak memory 205868 kb
Host smart-23c6922b-ca9a-4458-8d53-12dd9b41393f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31040
88318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3104088318
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.251865813
Short name T1098
Test name
Test status
Simulation time 245641689 ps
CPU time 0.94 seconds
Started Jun 21 04:56:47 PM PDT 24
Finished Jun 21 04:56:49 PM PDT 24
Peak memory 205984 kb
Host smart-c70fa631-c5c1-457a-b108-69cfa76b9728
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=251865813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.251865813
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1143032104
Short name T2029
Test name
Test status
Simulation time 142406959 ps
CPU time 0.75 seconds
Started Jun 21 04:56:43 PM PDT 24
Finished Jun 21 04:56:46 PM PDT 24
Peak memory 206012 kb
Host smart-423adf53-427c-45dc-9a05-42a587965b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11430
32104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1143032104
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.4279320257
Short name T772
Test name
Test status
Simulation time 37256064 ps
CPU time 0.71 seconds
Started Jun 21 04:56:49 PM PDT 24
Finished Jun 21 04:56:51 PM PDT 24
Peak memory 205928 kb
Host smart-85fcdd5e-b984-4e25-be0f-d96b4b8bcc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42793
20257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.4279320257
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1704892261
Short name T2111
Test name
Test status
Simulation time 10632994055 ps
CPU time 24.67 seconds
Started Jun 21 04:56:49 PM PDT 24
Finished Jun 21 04:57:15 PM PDT 24
Peak memory 206252 kb
Host smart-591d13dc-c062-4330-be8d-b6df5df8adb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17048
92261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1704892261
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2544147461
Short name T1535
Test name
Test status
Simulation time 174356937 ps
CPU time 0.86 seconds
Started Jun 21 04:56:49 PM PDT 24
Finished Jun 21 04:56:52 PM PDT 24
Peak memory 205968 kb
Host smart-fac8968a-f1bd-4dbb-b6b3-04ecc65e6190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25441
47461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2544147461
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3564433076
Short name T2259
Test name
Test status
Simulation time 188089774 ps
CPU time 0.98 seconds
Started Jun 21 04:56:45 PM PDT 24
Finished Jun 21 04:56:47 PM PDT 24
Peak memory 205972 kb
Host smart-5b48e1ad-efcc-43dd-8aa6-06bf7ef4677a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35644
33076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3564433076
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.4044597444
Short name T1038
Test name
Test status
Simulation time 204230845 ps
CPU time 0.94 seconds
Started Jun 21 04:56:48 PM PDT 24
Finished Jun 21 04:56:50 PM PDT 24
Peak memory 205972 kb
Host smart-8296d222-db5d-43db-9836-67998c1dff3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40445
97444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.4044597444
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.2858651896
Short name T1067
Test name
Test status
Simulation time 161696630 ps
CPU time 0.79 seconds
Started Jun 21 04:56:45 PM PDT 24
Finished Jun 21 04:56:47 PM PDT 24
Peak memory 206024 kb
Host smart-5712fd5c-0240-49ca-b991-4d3b67abbf61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28586
51896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.2858651896
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.2085860930
Short name T1349
Test name
Test status
Simulation time 146557838 ps
CPU time 0.75 seconds
Started Jun 21 04:56:45 PM PDT 24
Finished Jun 21 04:56:47 PM PDT 24
Peak memory 205924 kb
Host smart-2ae8dec3-05b3-4386-9d0c-3967b5b8434f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20858
60930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.2085860930
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3969937116
Short name T1197
Test name
Test status
Simulation time 142150158 ps
CPU time 0.73 seconds
Started Jun 21 04:56:47 PM PDT 24
Finished Jun 21 04:56:49 PM PDT 24
Peak memory 206016 kb
Host smart-6ed05afb-be20-4263-b5d9-35e37c2d8709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39699
37116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3969937116
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3559217475
Short name T1107
Test name
Test status
Simulation time 149770909 ps
CPU time 0.74 seconds
Started Jun 21 04:56:46 PM PDT 24
Finished Jun 21 04:56:49 PM PDT 24
Peak memory 206024 kb
Host smart-0dd8d15e-4737-49f4-b346-bc2e6dc8bf93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35592
17475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3559217475
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2944814930
Short name T2129
Test name
Test status
Simulation time 234382566 ps
CPU time 0.93 seconds
Started Jun 21 04:56:38 PM PDT 24
Finished Jun 21 04:56:41 PM PDT 24
Peak memory 206028 kb
Host smart-608127a5-2715-421b-9de1-941c90e6ebea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29448
14930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2944814930
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.1410421125
Short name T1212
Test name
Test status
Simulation time 8879845282 ps
CPU time 66.56 seconds
Started Jun 21 04:56:49 PM PDT 24
Finished Jun 21 04:57:57 PM PDT 24
Peak memory 206212 kb
Host smart-731d12b1-5c6e-4e26-b431-6743e65c1939
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1410421125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.1410421125
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.847273632
Short name T1965
Test name
Test status
Simulation time 159359729 ps
CPU time 0.76 seconds
Started Jun 21 04:56:46 PM PDT 24
Finished Jun 21 04:56:48 PM PDT 24
Peak memory 206024 kb
Host smart-87919f2f-88f4-4f5f-a705-50ab43d9b9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84727
3632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.847273632
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3877547720
Short name T1281
Test name
Test status
Simulation time 178936840 ps
CPU time 0.74 seconds
Started Jun 21 04:56:46 PM PDT 24
Finished Jun 21 04:56:48 PM PDT 24
Peak memory 206024 kb
Host smart-8b0780a9-fa1a-436f-bc6f-f572c43c9805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38775
47720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3877547720
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2314905781
Short name T1211
Test name
Test status
Simulation time 9258102346 ps
CPU time 83.21 seconds
Started Jun 21 04:56:48 PM PDT 24
Finished Jun 21 04:58:13 PM PDT 24
Peak memory 206192 kb
Host smart-5c983465-4855-4651-8c05-250a4bde27d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23149
05781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2314905781
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1229761052
Short name T789
Test name
Test status
Simulation time 4349257020 ps
CPU time 4.66 seconds
Started Jun 21 04:56:47 PM PDT 24
Finished Jun 21 04:56:53 PM PDT 24
Peak memory 206316 kb
Host smart-6bd2188a-9540-4fb0-a9b6-4fa84ccef3cd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1229761052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.1229761052
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.289135130
Short name T408
Test name
Test status
Simulation time 13407007948 ps
CPU time 14.14 seconds
Started Jun 21 04:56:47 PM PDT 24
Finished Jun 21 04:57:03 PM PDT 24
Peak memory 206252 kb
Host smart-70a23c66-e7cd-49b0-b3b5-bcd09a09e036
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=289135130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.289135130
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.4109682360
Short name T610
Test name
Test status
Simulation time 23363679248 ps
CPU time 22.35 seconds
Started Jun 21 04:56:45 PM PDT 24
Finished Jun 21 04:57:09 PM PDT 24
Peak memory 206044 kb
Host smart-a7a9716b-955e-4055-ac2f-deb8e351d9e6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4109682360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.4109682360
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3466090708
Short name T612
Test name
Test status
Simulation time 170923156 ps
CPU time 0.8 seconds
Started Jun 21 04:56:49 PM PDT 24
Finished Jun 21 04:56:51 PM PDT 24
Peak memory 205960 kb
Host smart-c2a93f41-e0cd-4e23-aeb8-93e8d3c76b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34660
90708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3466090708
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.2076256025
Short name T1300
Test name
Test status
Simulation time 158926412 ps
CPU time 0.77 seconds
Started Jun 21 04:56:47 PM PDT 24
Finished Jun 21 04:56:49 PM PDT 24
Peak memory 205956 kb
Host smart-93195903-1402-47b0-b311-6c2c1c9e5f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20762
56025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.2076256025
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1467396261
Short name T2440
Test name
Test status
Simulation time 412632580 ps
CPU time 1.41 seconds
Started Jun 21 04:56:43 PM PDT 24
Finished Jun 21 04:56:46 PM PDT 24
Peak memory 206024 kb
Host smart-afa89adb-60a9-4cba-b720-45bb357befce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14673
96261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1467396261
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1659081627
Short name T105
Test name
Test status
Simulation time 578865992 ps
CPU time 1.47 seconds
Started Jun 21 04:56:49 PM PDT 24
Finished Jun 21 04:56:52 PM PDT 24
Peak memory 205968 kb
Host smart-3b1199a0-bccc-4432-893a-9d851cce6d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16590
81627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1659081627
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.4151354281
Short name T1020
Test name
Test status
Simulation time 13179780190 ps
CPU time 24.1 seconds
Started Jun 21 04:56:45 PM PDT 24
Finished Jun 21 04:57:11 PM PDT 24
Peak memory 206328 kb
Host smart-51e10227-3208-4774-a1cd-5a5aff46827c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41513
54281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.4151354281
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.1639197665
Short name T1577
Test name
Test status
Simulation time 372000456 ps
CPU time 1.18 seconds
Started Jun 21 04:56:44 PM PDT 24
Finished Jun 21 04:56:46 PM PDT 24
Peak memory 205936 kb
Host smart-dc24db77-89c5-4d2d-a41f-3c259ab7c0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16391
97665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.1639197665
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2953267907
Short name T1904
Test name
Test status
Simulation time 149316176 ps
CPU time 0.76 seconds
Started Jun 21 04:56:46 PM PDT 24
Finished Jun 21 04:56:48 PM PDT 24
Peak memory 206048 kb
Host smart-6d082874-c560-4adc-8cb7-b70c03848d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29532
67907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2953267907
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.2345322225
Short name T473
Test name
Test status
Simulation time 34396853 ps
CPU time 0.66 seconds
Started Jun 21 04:56:49 PM PDT 24
Finished Jun 21 04:56:51 PM PDT 24
Peak memory 205960 kb
Host smart-3d5b9c46-9f9a-49d4-ad25-437cb1621368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23453
22225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2345322225
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.936660810
Short name T2337
Test name
Test status
Simulation time 802465096 ps
CPU time 1.88 seconds
Started Jun 21 04:56:46 PM PDT 24
Finished Jun 21 04:56:50 PM PDT 24
Peak memory 206256 kb
Host smart-970f4957-f8e1-4e92-be17-e7cacdeefa21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93666
0810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.936660810
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3703441858
Short name T1619
Test name
Test status
Simulation time 330323217 ps
CPU time 1.99 seconds
Started Jun 21 04:56:47 PM PDT 24
Finished Jun 21 04:56:50 PM PDT 24
Peak memory 206248 kb
Host smart-92c0ece6-1bb4-49e3-8b24-9c566d7c8dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37034
41858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3703441858
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.558987903
Short name T1455
Test name
Test status
Simulation time 171969615 ps
CPU time 0.78 seconds
Started Jun 21 04:56:57 PM PDT 24
Finished Jun 21 04:57:01 PM PDT 24
Peak memory 205940 kb
Host smart-41918a0a-2d8a-4487-a6b5-953e740c8d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55898
7903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.558987903
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2357445798
Short name T732
Test name
Test status
Simulation time 183602660 ps
CPU time 0.81 seconds
Started Jun 21 04:56:59 PM PDT 24
Finished Jun 21 04:57:03 PM PDT 24
Peak memory 205964 kb
Host smart-a61059f9-9b5f-4324-b427-a6df36381cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23574
45798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2357445798
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.899614536
Short name T1291
Test name
Test status
Simulation time 191531974 ps
CPU time 0.85 seconds
Started Jun 21 04:56:49 PM PDT 24
Finished Jun 21 04:56:51 PM PDT 24
Peak memory 205988 kb
Host smart-f5adaa3b-589a-4288-bdda-b49b75e65ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89961
4536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.899614536
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.3767097986
Short name T2319
Test name
Test status
Simulation time 5869661799 ps
CPU time 160.51 seconds
Started Jun 21 04:56:46 PM PDT 24
Finished Jun 21 04:59:28 PM PDT 24
Peak memory 206244 kb
Host smart-d9dd683e-c610-410e-9188-fbdfa03ab81d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3767097986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.3767097986
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.1591849728
Short name T923
Test name
Test status
Simulation time 231322430 ps
CPU time 0.95 seconds
Started Jun 21 04:56:59 PM PDT 24
Finished Jun 21 04:57:04 PM PDT 24
Peak memory 205968 kb
Host smart-c249449b-17d9-4cdc-8c00-f846810f9697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15918
49728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.1591849728
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.931799005
Short name T1910
Test name
Test status
Simulation time 23315472100 ps
CPU time 25.8 seconds
Started Jun 21 04:56:54 PM PDT 24
Finished Jun 21 04:57:21 PM PDT 24
Peak memory 206084 kb
Host smart-4ace9d2d-cdaa-48be-9021-162d97c680a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93179
9005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.931799005
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.3256304920
Short name T1220
Test name
Test status
Simulation time 3285465064 ps
CPU time 4.62 seconds
Started Jun 21 04:56:54 PM PDT 24
Finished Jun 21 04:57:00 PM PDT 24
Peak memory 206068 kb
Host smart-d3949d4f-da48-4f82-844e-2363fee04e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32563
04920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.3256304920
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.733288434
Short name T1040
Test name
Test status
Simulation time 6510122526 ps
CPU time 64.68 seconds
Started Jun 21 04:56:55 PM PDT 24
Finished Jun 21 04:58:02 PM PDT 24
Peak memory 206368 kb
Host smart-4a43c0b6-84bf-4f42-801a-4722faa00a9e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=733288434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.733288434
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.1454390725
Short name T622
Test name
Test status
Simulation time 234056821 ps
CPU time 0.9 seconds
Started Jun 21 04:56:53 PM PDT 24
Finished Jun 21 04:56:56 PM PDT 24
Peak memory 205992 kb
Host smart-e8200b5d-3566-4f80-ba91-6a3674a32d48
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1454390725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.1454390725
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2111568716
Short name T1959
Test name
Test status
Simulation time 211573521 ps
CPU time 0.87 seconds
Started Jun 21 04:56:55 PM PDT 24
Finished Jun 21 04:56:58 PM PDT 24
Peak memory 206008 kb
Host smart-38882ce0-8d01-40c7-b9c7-b52def30a48e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21115
68716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2111568716
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.2533240302
Short name T1777
Test name
Test status
Simulation time 4382665714 ps
CPU time 33.83 seconds
Started Jun 21 04:56:56 PM PDT 24
Finished Jun 21 04:57:33 PM PDT 24
Peak memory 206248 kb
Host smart-8e7c441d-fe88-483f-ac52-f8176bfd75ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25332
40302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.2533240302
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3603374017
Short name T520
Test name
Test status
Simulation time 6766183452 ps
CPU time 194.04 seconds
Started Jun 21 04:56:55 PM PDT 24
Finished Jun 21 05:00:11 PM PDT 24
Peak memory 206184 kb
Host smart-53ea10f1-8ffe-495f-9272-e584d6d9935c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3603374017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3603374017
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.474517639
Short name T483
Test name
Test status
Simulation time 183753239 ps
CPU time 0.84 seconds
Started Jun 21 04:56:59 PM PDT 24
Finished Jun 21 04:57:03 PM PDT 24
Peak memory 205956 kb
Host smart-7387bb1b-66b9-4894-8fd6-487a1070374e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=474517639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.474517639
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1584635991
Short name T371
Test name
Test status
Simulation time 148508404 ps
CPU time 0.9 seconds
Started Jun 21 04:56:58 PM PDT 24
Finished Jun 21 04:57:02 PM PDT 24
Peak memory 205968 kb
Host smart-8e597cf4-bf06-4d80-ae0b-01feeb8d2e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15846
35991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1584635991
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.2876558912
Short name T975
Test name
Test status
Simulation time 202529455 ps
CPU time 0.91 seconds
Started Jun 21 04:56:54 PM PDT 24
Finished Jun 21 04:56:56 PM PDT 24
Peak memory 205924 kb
Host smart-a4ab6e20-5af2-4b49-b280-90e96b3e47e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28765
58912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2876558912
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1069120800
Short name T2154
Test name
Test status
Simulation time 172275960 ps
CPU time 0.77 seconds
Started Jun 21 04:56:55 PM PDT 24
Finished Jun 21 04:56:58 PM PDT 24
Peak memory 205932 kb
Host smart-fae65d81-d067-4d14-981b-556016bc21fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10691
20800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1069120800
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.356426091
Short name T2445
Test name
Test status
Simulation time 166906580 ps
CPU time 0.84 seconds
Started Jun 21 04:56:55 PM PDT 24
Finished Jun 21 04:56:58 PM PDT 24
Peak memory 205996 kb
Host smart-04bd8fbe-56f9-42c2-86ec-d723e325ee9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35642
6091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.356426091
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1989693949
Short name T2489
Test name
Test status
Simulation time 200511695 ps
CPU time 0.82 seconds
Started Jun 21 04:56:58 PM PDT 24
Finished Jun 21 04:57:03 PM PDT 24
Peak memory 206024 kb
Host smart-dd6d420c-8d7b-443a-8545-26c7311d369a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19896
93949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1989693949
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.3670733485
Short name T2010
Test name
Test status
Simulation time 234513497 ps
CPU time 0.93 seconds
Started Jun 21 04:56:55 PM PDT 24
Finished Jun 21 04:56:58 PM PDT 24
Peak memory 206068 kb
Host smart-ebc2ea94-35e2-4d8a-bf9f-23be32f00171
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3670733485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.3670733485
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1069335740
Short name T385
Test name
Test status
Simulation time 153304051 ps
CPU time 0.75 seconds
Started Jun 21 04:56:58 PM PDT 24
Finished Jun 21 04:57:02 PM PDT 24
Peak memory 205980 kb
Host smart-932c275b-25c4-46a0-8227-cdc69cc9c2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10693
35740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1069335740
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3157107978
Short name T490
Test name
Test status
Simulation time 7069286642 ps
CPU time 17.99 seconds
Started Jun 21 04:56:55 PM PDT 24
Finished Jun 21 04:57:16 PM PDT 24
Peak memory 206264 kb
Host smart-59a86a39-59c8-408c-a47d-a6a752ba2f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31571
07978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3157107978
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.284673022
Short name T2486
Test name
Test status
Simulation time 185077406 ps
CPU time 0.85 seconds
Started Jun 21 04:56:56 PM PDT 24
Finished Jun 21 04:57:00 PM PDT 24
Peak memory 205608 kb
Host smart-f257d0d9-0f6a-41be-9c4d-1c2266606b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28467
3022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.284673022
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.158344386
Short name T1242
Test name
Test status
Simulation time 190571768 ps
CPU time 0.83 seconds
Started Jun 21 04:56:54 PM PDT 24
Finished Jun 21 04:56:57 PM PDT 24
Peak memory 206020 kb
Host smart-f5a2b134-b8d0-49bf-a5d7-fc6499538878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15834
4386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.158344386
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.2951425282
Short name T915
Test name
Test status
Simulation time 223227621 ps
CPU time 0.94 seconds
Started Jun 21 04:56:55 PM PDT 24
Finished Jun 21 04:56:59 PM PDT 24
Peak memory 205936 kb
Host smart-7029bcce-e7f5-40c3-98a5-674cce60a190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29514
25282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.2951425282
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1367879002
Short name T518
Test name
Test status
Simulation time 196820320 ps
CPU time 0.94 seconds
Started Jun 21 04:56:54 PM PDT 24
Finished Jun 21 04:56:56 PM PDT 24
Peak memory 206044 kb
Host smart-382712a3-825d-47e3-93cc-40ee78acbf65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13678
79002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1367879002
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.2329100563
Short name T90
Test name
Test status
Simulation time 163967540 ps
CPU time 0.87 seconds
Started Jun 21 04:56:59 PM PDT 24
Finished Jun 21 04:57:03 PM PDT 24
Peak memory 205944 kb
Host smart-02eb34bb-243c-4582-b26e-0eb1a33161db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23291
00563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.2329100563
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.4230205431
Short name T750
Test name
Test status
Simulation time 148456286 ps
CPU time 0.77 seconds
Started Jun 21 04:56:53 PM PDT 24
Finished Jun 21 04:56:55 PM PDT 24
Peak memory 206012 kb
Host smart-3c1327f4-b42e-41d6-b98c-ea702bb3cf23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42302
05431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.4230205431
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3140978628
Short name T1649
Test name
Test status
Simulation time 148281021 ps
CPU time 0.73 seconds
Started Jun 21 04:56:53 PM PDT 24
Finished Jun 21 04:56:55 PM PDT 24
Peak memory 206004 kb
Host smart-dd242b99-79dd-40a9-86b7-58eecfd2f14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31409
78628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3140978628
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2720949697
Short name T307
Test name
Test status
Simulation time 243054534 ps
CPU time 0.93 seconds
Started Jun 21 04:56:46 PM PDT 24
Finished Jun 21 04:56:49 PM PDT 24
Peak memory 206020 kb
Host smart-9568d8b7-660f-4703-a28e-281c67197555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27209
49697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2720949697
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.4070673901
Short name T609
Test name
Test status
Simulation time 12136802134 ps
CPU time 113.34 seconds
Started Jun 21 04:56:55 PM PDT 24
Finished Jun 21 04:58:51 PM PDT 24
Peak memory 206336 kb
Host smart-70dec683-f359-442b-aa61-64100ff34914
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4070673901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.4070673901
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3052357665
Short name T17
Test name
Test status
Simulation time 187020828 ps
CPU time 0.8 seconds
Started Jun 21 04:56:56 PM PDT 24
Finished Jun 21 04:57:00 PM PDT 24
Peak memory 206028 kb
Host smart-6f70758e-64ee-4a99-b012-0d0801190ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30523
57665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3052357665
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.1821253864
Short name T390
Test name
Test status
Simulation time 178907832 ps
CPU time 0.81 seconds
Started Jun 21 04:56:58 PM PDT 24
Finished Jun 21 04:57:02 PM PDT 24
Peak memory 205916 kb
Host smart-ace5ea22-bd86-49fc-b8dc-6adcb80b64ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18212
53864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1821253864
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.704625873
Short name T1625
Test name
Test status
Simulation time 14008238411 ps
CPU time 408.35 seconds
Started Jun 21 04:56:55 PM PDT 24
Finished Jun 21 05:03:45 PM PDT 24
Peak memory 206228 kb
Host smart-cef29cb6-e6f2-40de-a8dd-11c58da9626a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70462
5873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.704625873
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.1348376532
Short name T904
Test name
Test status
Simulation time 4186848804 ps
CPU time 5.91 seconds
Started Jun 21 04:56:58 PM PDT 24
Finished Jun 21 04:57:08 PM PDT 24
Peak memory 206172 kb
Host smart-b7972521-1283-435f-8b06-7069e24952ce
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1348376532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.1348376532
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1963203833
Short name T2500
Test name
Test status
Simulation time 13335210311 ps
CPU time 12.95 seconds
Started Jun 21 04:56:58 PM PDT 24
Finished Jun 21 04:57:15 PM PDT 24
Peak memory 205972 kb
Host smart-bf34af4b-c798-44a8-9690-0c9c2ad1ae5a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1963203833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1963203833
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.2049626704
Short name T1525
Test name
Test status
Simulation time 23301496661 ps
CPU time 28.03 seconds
Started Jun 21 04:56:58 PM PDT 24
Finished Jun 21 04:57:30 PM PDT 24
Peak memory 206120 kb
Host smart-a2e59ffd-4778-4f36-b560-6ac0fcc433da
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2049626704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.2049626704
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2402911396
Short name T592
Test name
Test status
Simulation time 150876959 ps
CPU time 0.83 seconds
Started Jun 21 04:56:58 PM PDT 24
Finished Jun 21 04:57:02 PM PDT 24
Peak memory 205960 kb
Host smart-39b1dabc-3b52-43d4-957e-bce65e07638e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24029
11396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2402911396
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.712518665
Short name T2269
Test name
Test status
Simulation time 152008969 ps
CPU time 0.73 seconds
Started Jun 21 04:56:57 PM PDT 24
Finished Jun 21 04:57:01 PM PDT 24
Peak memory 205968 kb
Host smart-3fe68b10-7348-4328-bcca-ee3d20dd2a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71251
8665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.712518665
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.3099857670
Short name T1595
Test name
Test status
Simulation time 493418298 ps
CPU time 1.37 seconds
Started Jun 21 04:56:55 PM PDT 24
Finished Jun 21 04:56:59 PM PDT 24
Peak memory 206024 kb
Host smart-c1425cea-9488-4364-9608-8c9c5ee93e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30998
57670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3099857670
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1859325988
Short name T2365
Test name
Test status
Simulation time 662378131 ps
CPU time 1.81 seconds
Started Jun 21 04:56:57 PM PDT 24
Finished Jun 21 04:57:02 PM PDT 24
Peak memory 206028 kb
Host smart-a074c8a7-a5b1-43ec-bad9-7e66e0f2684c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18593
25988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1859325988
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.1461554857
Short name T1996
Test name
Test status
Simulation time 10651177648 ps
CPU time 20.16 seconds
Started Jun 21 04:56:59 PM PDT 24
Finished Jun 21 04:57:22 PM PDT 24
Peak memory 206312 kb
Host smart-31b30bd8-2f09-4b1f-a45e-3db22cdb641a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14615
54857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.1461554857
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.565841844
Short name T1811
Test name
Test status
Simulation time 459186067 ps
CPU time 1.4 seconds
Started Jun 21 04:56:56 PM PDT 24
Finished Jun 21 04:57:01 PM PDT 24
Peak memory 206028 kb
Host smart-d5b81670-a1f0-4c7a-9da9-5d28c10ec823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56584
1844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.565841844
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.47277690
Short name T1507
Test name
Test status
Simulation time 203061444 ps
CPU time 0.88 seconds
Started Jun 21 04:56:54 PM PDT 24
Finished Jun 21 04:56:57 PM PDT 24
Peak memory 206024 kb
Host smart-243bb02d-c6f1-4ddc-a5f5-2ee86dac6425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47277
690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.47277690
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1103797498
Short name T1896
Test name
Test status
Simulation time 48309383 ps
CPU time 0.68 seconds
Started Jun 21 04:56:57 PM PDT 24
Finished Jun 21 04:57:01 PM PDT 24
Peak memory 206140 kb
Host smart-f79c4fc6-286e-4469-9690-ad32af3eff01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11037
97498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1103797498
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.2023742317
Short name T1850
Test name
Test status
Simulation time 1044866294 ps
CPU time 2.29 seconds
Started Jun 21 04:56:59 PM PDT 24
Finished Jun 21 04:57:05 PM PDT 24
Peak memory 206104 kb
Host smart-cce722ae-be2d-4086-8b6d-eca68478d145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20237
42317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2023742317
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.640959722
Short name T1855
Test name
Test status
Simulation time 205944285 ps
CPU time 0.93 seconds
Started Jun 21 04:57:04 PM PDT 24
Finished Jun 21 04:57:08 PM PDT 24
Peak memory 205968 kb
Host smart-945bb5f5-37e7-4335-a8d3-78b0eae382c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64095
9722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.640959722
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.328989114
Short name T708
Test name
Test status
Simulation time 139918731 ps
CPU time 0.73 seconds
Started Jun 21 04:57:05 PM PDT 24
Finished Jun 21 04:57:08 PM PDT 24
Peak memory 205996 kb
Host smart-7fd79dde-25cc-4d4b-8c7a-7bc1d2ada60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32898
9114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.328989114
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3333804793
Short name T589
Test name
Test status
Simulation time 249709245 ps
CPU time 0.95 seconds
Started Jun 21 04:56:54 PM PDT 24
Finished Jun 21 04:56:56 PM PDT 24
Peak memory 206024 kb
Host smart-8c31537f-c1d3-4ba2-b15a-8c55c7872697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33338
04793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3333804793
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.3365872734
Short name T1426
Test name
Test status
Simulation time 296567305 ps
CPU time 0.99 seconds
Started Jun 21 04:56:57 PM PDT 24
Finished Jun 21 04:57:02 PM PDT 24
Peak memory 205920 kb
Host smart-52ce3700-579e-43e1-a1c4-2eda6dfbe3b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33658
72734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3365872734
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1261450746
Short name T416
Test name
Test status
Simulation time 23324659700 ps
CPU time 22.65 seconds
Started Jun 21 04:56:56 PM PDT 24
Finished Jun 21 04:57:22 PM PDT 24
Peak memory 206004 kb
Host smart-822c2272-ec4c-44b2-90e9-5dafdb5e37c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12614
50746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1261450746
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.4017716953
Short name T1544
Test name
Test status
Simulation time 3310674128 ps
CPU time 4.52 seconds
Started Jun 21 04:56:59 PM PDT 24
Finished Jun 21 04:57:06 PM PDT 24
Peak memory 206040 kb
Host smart-7d6a3164-247d-4efc-aba0-d3563b476a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40177
16953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.4017716953
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.3956121586
Short name T2176
Test name
Test status
Simulation time 10160159893 ps
CPU time 72.76 seconds
Started Jun 21 04:56:57 PM PDT 24
Finished Jun 21 04:58:13 PM PDT 24
Peak memory 206160 kb
Host smart-bfeab99f-4a3e-4bac-9b2e-cbbd9ce4fd77
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3956121586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.3956121586
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.3468468389
Short name T767
Test name
Test status
Simulation time 245215910 ps
CPU time 0.89 seconds
Started Jun 21 04:57:06 PM PDT 24
Finished Jun 21 04:57:09 PM PDT 24
Peak memory 206028 kb
Host smart-8d35ac3f-89b6-4ce9-bb1d-64ec2595c631
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3468468389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3468468389
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2905634345
Short name T1966
Test name
Test status
Simulation time 197412446 ps
CPU time 0.84 seconds
Started Jun 21 04:56:56 PM PDT 24
Finished Jun 21 04:57:00 PM PDT 24
Peak memory 205668 kb
Host smart-647a12ae-daaa-4f37-bc49-c5303b3adaa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29056
34345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2905634345
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.2379856021
Short name T311
Test name
Test status
Simulation time 13197501305 ps
CPU time 126.54 seconds
Started Jun 21 04:56:58 PM PDT 24
Finished Jun 21 04:59:08 PM PDT 24
Peak memory 206364 kb
Host smart-b41eb169-e890-4431-92f2-c82b2a63d2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23798
56021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.2379856021
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.4264413037
Short name T1981
Test name
Test status
Simulation time 9882249409 ps
CPU time 72.58 seconds
Started Jun 21 04:56:58 PM PDT 24
Finished Jun 21 04:58:15 PM PDT 24
Peak memory 206360 kb
Host smart-622bcf56-696a-4253-8c12-4b25bf42926e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4264413037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.4264413037
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.3456190559
Short name T2080
Test name
Test status
Simulation time 200042562 ps
CPU time 0.89 seconds
Started Jun 21 04:57:04 PM PDT 24
Finished Jun 21 04:57:07 PM PDT 24
Peak memory 206048 kb
Host smart-82c7ea6c-cc31-4bc1-81cf-33176f976396
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3456190559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.3456190559
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.364174608
Short name T1803
Test name
Test status
Simulation time 172042452 ps
CPU time 0.82 seconds
Started Jun 21 04:56:57 PM PDT 24
Finished Jun 21 04:57:01 PM PDT 24
Peak memory 205948 kb
Host smart-a8f9df7a-0b4e-4b52-9cd3-c2147210a751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36417
4608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.364174608
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.674223438
Short name T1591
Test name
Test status
Simulation time 175575916 ps
CPU time 0.83 seconds
Started Jun 21 04:57:02 PM PDT 24
Finished Jun 21 04:57:06 PM PDT 24
Peak memory 206000 kb
Host smart-a1617de7-65e5-4c98-a104-5af983b5f929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67422
3438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.674223438
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.3295670438
Short name T2026
Test name
Test status
Simulation time 176639328 ps
CPU time 0.82 seconds
Started Jun 21 04:57:02 PM PDT 24
Finished Jun 21 04:57:06 PM PDT 24
Peak memory 206000 kb
Host smart-27871467-c767-4e23-9f3e-c89d62a7b3a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32956
70438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.3295670438
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1276661307
Short name T21
Test name
Test status
Simulation time 174459508 ps
CPU time 0.77 seconds
Started Jun 21 04:56:56 PM PDT 24
Finished Jun 21 04:57:00 PM PDT 24
Peak memory 206024 kb
Host smart-b6511957-cce7-4638-95ad-27fea5280587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12766
61307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1276661307
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2491960121
Short name T1659
Test name
Test status
Simulation time 151162758 ps
CPU time 0.89 seconds
Started Jun 21 04:56:57 PM PDT 24
Finished Jun 21 04:57:02 PM PDT 24
Peak memory 205976 kb
Host smart-f29c617b-ef1f-48d5-b9ac-53712afabb9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24919
60121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2491960121
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2021919082
Short name T929
Test name
Test status
Simulation time 201942211 ps
CPU time 0.84 seconds
Started Jun 21 04:57:04 PM PDT 24
Finished Jun 21 04:57:08 PM PDT 24
Peak memory 206024 kb
Host smart-f7bbe2f9-a4e3-4f3d-9ffc-04e0fbc17ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20219
19082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2021919082
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.435159882
Short name T1493
Test name
Test status
Simulation time 239264048 ps
CPU time 0.95 seconds
Started Jun 21 04:57:02 PM PDT 24
Finished Jun 21 04:57:06 PM PDT 24
Peak memory 206028 kb
Host smart-7b1f9a23-b561-4032-ba49-3eeca65b593f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=435159882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.435159882
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3695787641
Short name T744
Test name
Test status
Simulation time 177467184 ps
CPU time 0.81 seconds
Started Jun 21 04:57:03 PM PDT 24
Finished Jun 21 04:57:07 PM PDT 24
Peak memory 205968 kb
Host smart-f1cbcf4e-e211-4026-af72-30ed3d803b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36957
87641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3695787641
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3764103731
Short name T1994
Test name
Test status
Simulation time 39712530 ps
CPU time 0.64 seconds
Started Jun 21 04:57:09 PM PDT 24
Finished Jun 21 04:57:12 PM PDT 24
Peak memory 205976 kb
Host smart-b930d80e-3adc-465e-b641-08ccc10246b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37641
03731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3764103731
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2559259776
Short name T2360
Test name
Test status
Simulation time 16286955676 ps
CPU time 39.05 seconds
Started Jun 21 04:56:56 PM PDT 24
Finished Jun 21 04:57:38 PM PDT 24
Peak memory 206216 kb
Host smart-f06c754c-defb-4950-8427-5b17d3610987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25592
59776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2559259776
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.4003596110
Short name T1586
Test name
Test status
Simulation time 185600917 ps
CPU time 0.86 seconds
Started Jun 21 04:56:56 PM PDT 24
Finished Jun 21 04:57:00 PM PDT 24
Peak memory 206028 kb
Host smart-be2e9561-700c-4d0e-a9d5-df0f7bee67c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40035
96110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.4003596110
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.4178007156
Short name T428
Test name
Test status
Simulation time 158870215 ps
CPU time 0.82 seconds
Started Jun 21 04:56:56 PM PDT 24
Finished Jun 21 04:57:01 PM PDT 24
Peak memory 206020 kb
Host smart-a40e1733-7c58-4a46-a81e-97a3fe07b49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41780
07156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.4178007156
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3094551484
Short name T1919
Test name
Test status
Simulation time 191565875 ps
CPU time 0.84 seconds
Started Jun 21 04:57:00 PM PDT 24
Finished Jun 21 04:57:04 PM PDT 24
Peak memory 206028 kb
Host smart-f6bde6ed-581b-4a30-a3b5-a501b9a8a814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30945
51484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3094551484
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.3611112603
Short name T2262
Test name
Test status
Simulation time 196683234 ps
CPU time 0.84 seconds
Started Jun 21 04:56:57 PM PDT 24
Finished Jun 21 04:57:02 PM PDT 24
Peak memory 206044 kb
Host smart-ab6102c9-309e-4846-968d-31955606a21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36111
12603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.3611112603
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2967213844
Short name T785
Test name
Test status
Simulation time 181603649 ps
CPU time 0.87 seconds
Started Jun 21 04:57:02 PM PDT 24
Finished Jun 21 04:57:06 PM PDT 24
Peak memory 206020 kb
Host smart-c101f3e4-2a68-40a8-8954-fddde6486d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29672
13844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2967213844
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.166376925
Short name T534
Test name
Test status
Simulation time 151723197 ps
CPU time 0.75 seconds
Started Jun 21 04:57:08 PM PDT 24
Finished Jun 21 04:57:11 PM PDT 24
Peak memory 205964 kb
Host smart-90837238-f597-449f-8ee9-7e6371fdd75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16637
6925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.166376925
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.766937917
Short name T1779
Test name
Test status
Simulation time 151123210 ps
CPU time 0.79 seconds
Started Jun 21 04:57:00 PM PDT 24
Finished Jun 21 04:57:04 PM PDT 24
Peak memory 206040 kb
Host smart-ce2f59fb-d6e9-4d8c-b30b-79426ff6ed2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76693
7917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.766937917
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2146973539
Short name T504
Test name
Test status
Simulation time 248110238 ps
CPU time 0.93 seconds
Started Jun 21 04:56:59 PM PDT 24
Finished Jun 21 04:57:04 PM PDT 24
Peak memory 205904 kb
Host smart-3c18ff3f-7fd4-4210-96fa-10f8221e2510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21469
73539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2146973539
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.1082948741
Short name T1566
Test name
Test status
Simulation time 9385752590 ps
CPU time 67.63 seconds
Started Jun 21 04:57:04 PM PDT 24
Finished Jun 21 04:58:15 PM PDT 24
Peak memory 206244 kb
Host smart-a1b686b4-903b-442c-81e2-6abfaa447642
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1082948741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.1082948741
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1704697129
Short name T309
Test name
Test status
Simulation time 180444870 ps
CPU time 0.85 seconds
Started Jun 21 04:57:01 PM PDT 24
Finished Jun 21 04:57:05 PM PDT 24
Peak memory 205928 kb
Host smart-f1f63f02-7cef-401c-ae96-cad5594b519a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17046
97129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1704697129
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1844413478
Short name T1451
Test name
Test status
Simulation time 193232313 ps
CPU time 0.8 seconds
Started Jun 21 04:57:10 PM PDT 24
Finished Jun 21 04:57:13 PM PDT 24
Peak memory 205964 kb
Host smart-01eb6a05-127a-411e-a5dc-143828197a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18444
13478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1844413478
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.3708282423
Short name T1825
Test name
Test status
Simulation time 14361357351 ps
CPU time 135.31 seconds
Started Jun 21 04:57:09 PM PDT 24
Finished Jun 21 04:59:26 PM PDT 24
Peak memory 206204 kb
Host smart-3c26df8f-030a-4b96-831f-8e435ca3364c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37082
82423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.3708282423
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.418274
Short name T2239
Test name
Test status
Simulation time 4192807854 ps
CPU time 4.75 seconds
Started Jun 21 04:57:00 PM PDT 24
Finished Jun 21 04:57:08 PM PDT 24
Peak memory 206412 kb
Host smart-86ec5ba1-fc04-4489-a1ef-a06de12aa070
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=418274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.418274
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3984080446
Short name T1217
Test name
Test status
Simulation time 13373380894 ps
CPU time 15.79 seconds
Started Jun 21 04:57:05 PM PDT 24
Finished Jun 21 04:57:23 PM PDT 24
Peak memory 206092 kb
Host smart-60a4fe35-5c8d-4ab4-8ba6-26740e9576ef
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3984080446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3984080446
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.1620411575
Short name T653
Test name
Test status
Simulation time 23374256270 ps
CPU time 26.85 seconds
Started Jun 21 04:57:05 PM PDT 24
Finished Jun 21 04:57:34 PM PDT 24
Peak memory 206036 kb
Host smart-ec7e2812-1970-4e69-8c4c-1ea0177cdc8b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1620411575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.1620411575
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.987961591
Short name T1639
Test name
Test status
Simulation time 153978159 ps
CPU time 0.75 seconds
Started Jun 21 04:57:08 PM PDT 24
Finished Jun 21 04:57:11 PM PDT 24
Peak memory 205964 kb
Host smart-48ec9b73-ceb0-44cc-aac5-df188851a7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98796
1591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.987961591
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.3298908596
Short name T2275
Test name
Test status
Simulation time 162629212 ps
CPU time 0.77 seconds
Started Jun 21 04:57:04 PM PDT 24
Finished Jun 21 04:57:08 PM PDT 24
Peak memory 205972 kb
Host smart-4873e1e4-d95b-4d6d-bacc-02846d86a889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32989
08596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.3298908596
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.1600682227
Short name T1990
Test name
Test status
Simulation time 283532918 ps
CPU time 1.07 seconds
Started Jun 21 04:57:03 PM PDT 24
Finished Jun 21 04:57:07 PM PDT 24
Peak memory 205964 kb
Host smart-30e17389-7880-4f59-bb69-f26898b47371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16006
82227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.1600682227
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2246938753
Short name T882
Test name
Test status
Simulation time 1349734823 ps
CPU time 2.93 seconds
Started Jun 21 04:57:03 PM PDT 24
Finished Jun 21 04:57:08 PM PDT 24
Peak memory 206216 kb
Host smart-630010f4-7130-4692-b569-8c2e2c900448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22469
38753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2246938753
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.543237713
Short name T2367
Test name
Test status
Simulation time 9733298215 ps
CPU time 19.29 seconds
Started Jun 21 04:57:04 PM PDT 24
Finished Jun 21 04:57:26 PM PDT 24
Peak memory 206276 kb
Host smart-c2e1dd35-baea-4798-82c3-393a256809e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54323
7713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.543237713
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3452545715
Short name T2229
Test name
Test status
Simulation time 437297543 ps
CPU time 1.36 seconds
Started Jun 21 04:57:06 PM PDT 24
Finished Jun 21 04:57:10 PM PDT 24
Peak memory 205976 kb
Host smart-15b220d1-46cf-4348-8b66-1ef1124eb949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34525
45715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3452545715
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.1150312104
Short name T658
Test name
Test status
Simulation time 195989633 ps
CPU time 0.79 seconds
Started Jun 21 04:57:10 PM PDT 24
Finished Jun 21 04:57:13 PM PDT 24
Peak memory 206000 kb
Host smart-db5d11db-676b-42c2-9627-0e395c5c6022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11503
12104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1150312104
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2965458394
Short name T469
Test name
Test status
Simulation time 66616854 ps
CPU time 0.67 seconds
Started Jun 21 04:57:05 PM PDT 24
Finished Jun 21 04:57:08 PM PDT 24
Peak memory 205960 kb
Host smart-244a7afe-1ce5-41bd-ae8b-ea29f0635f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29654
58394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2965458394
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.869526224
Short name T630
Test name
Test status
Simulation time 870029051 ps
CPU time 2.01 seconds
Started Jun 21 04:57:03 PM PDT 24
Finished Jun 21 04:57:08 PM PDT 24
Peak memory 206216 kb
Host smart-5cc5ddd0-5796-412f-b3f5-24f405b0a281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86952
6224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.869526224
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.12865918
Short name T441
Test name
Test status
Simulation time 220497436 ps
CPU time 1.95 seconds
Started Jun 21 04:57:02 PM PDT 24
Finished Jun 21 04:57:07 PM PDT 24
Peak memory 206248 kb
Host smart-9ff8892a-69ac-4bda-95f4-4b3993dd9597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12865
918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.12865918
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.1791877212
Short name T1809
Test name
Test status
Simulation time 214900807 ps
CPU time 0.87 seconds
Started Jun 21 04:57:08 PM PDT 24
Finished Jun 21 04:57:11 PM PDT 24
Peak memory 206024 kb
Host smart-a0749896-2bc1-43bb-ada8-4eda8f6e3e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17918
77212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1791877212
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.202189804
Short name T302
Test name
Test status
Simulation time 186854516 ps
CPU time 0.79 seconds
Started Jun 21 04:57:08 PM PDT 24
Finished Jun 21 04:57:11 PM PDT 24
Peak memory 206000 kb
Host smart-f78e76ba-4515-4a44-a788-49620394da1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20218
9804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.202189804
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3762341848
Short name T1570
Test name
Test status
Simulation time 173212525 ps
CPU time 0.8 seconds
Started Jun 21 04:57:04 PM PDT 24
Finished Jun 21 04:57:08 PM PDT 24
Peak memory 205964 kb
Host smart-2a6f7d9e-1085-4922-9477-ff29d211299a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37623
41848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3762341848
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1856581834
Short name T1448
Test name
Test status
Simulation time 174902667 ps
CPU time 0.86 seconds
Started Jun 21 04:57:09 PM PDT 24
Finished Jun 21 04:57:12 PM PDT 24
Peak memory 206000 kb
Host smart-d709aa2e-484f-420f-ada8-486d77478b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18565
81834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1856581834
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3937002143
Short name T1710
Test name
Test status
Simulation time 23286135217 ps
CPU time 28.99 seconds
Started Jun 21 04:57:10 PM PDT 24
Finished Jun 21 04:57:42 PM PDT 24
Peak memory 206024 kb
Host smart-6c8ea24f-fd56-4e48-8635-88e9f284ed34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39370
02143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3937002143
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.320760790
Short name T1314
Test name
Test status
Simulation time 3308821155 ps
CPU time 4.57 seconds
Started Jun 21 04:57:02 PM PDT 24
Finished Jun 21 04:57:10 PM PDT 24
Peak memory 206084 kb
Host smart-cda209a1-65f3-4329-8cca-3bff8391339e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32076
0790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.320760790
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.2270387695
Short name T833
Test name
Test status
Simulation time 4951888876 ps
CPU time 35.13 seconds
Started Jun 21 04:57:11 PM PDT 24
Finished Jun 21 04:57:49 PM PDT 24
Peak memory 206176 kb
Host smart-4b4632df-143f-46b7-89a3-ff8c43e9a172
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2270387695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.2270387695
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.1703933007
Short name T1696
Test name
Test status
Simulation time 253280787 ps
CPU time 0.94 seconds
Started Jun 21 04:57:11 PM PDT 24
Finished Jun 21 04:57:14 PM PDT 24
Peak memory 205988 kb
Host smart-83254246-8ece-4644-bcc1-48a334988593
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1703933007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.1703933007
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3944542595
Short name T2321
Test name
Test status
Simulation time 246123932 ps
CPU time 0.95 seconds
Started Jun 21 04:57:03 PM PDT 24
Finished Jun 21 04:57:06 PM PDT 24
Peak memory 206036 kb
Host smart-adcf6a31-f5f3-480c-bffd-5a7901a278f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39445
42595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3944542595
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.178323351
Short name T1735
Test name
Test status
Simulation time 4954943169 ps
CPU time 133.89 seconds
Started Jun 21 04:57:02 PM PDT 24
Finished Jun 21 04:59:18 PM PDT 24
Peak memory 206248 kb
Host smart-731c1dc2-4982-4ea1-94ea-4d2f985436aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17832
3351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.178323351
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.3238115762
Short name T500
Test name
Test status
Simulation time 6437154220 ps
CPU time 178.58 seconds
Started Jun 21 04:57:04 PM PDT 24
Finished Jun 21 05:00:06 PM PDT 24
Peak memory 206196 kb
Host smart-a21f5e17-bcf4-4973-a1ce-abcdff06a667
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3238115762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.3238115762
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.870476512
Short name T2064
Test name
Test status
Simulation time 196798613 ps
CPU time 0.83 seconds
Started Jun 21 04:57:08 PM PDT 24
Finished Jun 21 04:57:11 PM PDT 24
Peak memory 205960 kb
Host smart-f9278323-6737-480a-8fb6-3c09115cb3b8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=870476512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.870476512
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2328259052
Short name T2070
Test name
Test status
Simulation time 173409854 ps
CPU time 0.85 seconds
Started Jun 21 04:57:01 PM PDT 24
Finished Jun 21 04:57:05 PM PDT 24
Peak memory 206028 kb
Host smart-d178f0fd-b447-48b0-96e4-132cca63c2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23282
59052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2328259052
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2011705921
Short name T814
Test name
Test status
Simulation time 161091858 ps
CPU time 0.87 seconds
Started Jun 21 04:57:07 PM PDT 24
Finished Jun 21 04:57:10 PM PDT 24
Peak memory 206016 kb
Host smart-defbf165-4ec2-44df-a4c0-a9304cffe0f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20117
05921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2011705921
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.301698766
Short name T1492
Test name
Test status
Simulation time 191265927 ps
CPU time 0.79 seconds
Started Jun 21 04:57:07 PM PDT 24
Finished Jun 21 04:57:10 PM PDT 24
Peak memory 205956 kb
Host smart-5395545a-d877-49b0-b813-66d505bcd4d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30169
8766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.301698766
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2202146478
Short name T2421
Test name
Test status
Simulation time 180094635 ps
CPU time 0.79 seconds
Started Jun 21 04:57:07 PM PDT 24
Finished Jun 21 04:57:10 PM PDT 24
Peak memory 205956 kb
Host smart-855a757d-83aa-4817-a14f-8024be7ead16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22021
46478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2202146478
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3804282271
Short name T495
Test name
Test status
Simulation time 151027127 ps
CPU time 0.8 seconds
Started Jun 21 04:57:14 PM PDT 24
Finished Jun 21 04:57:16 PM PDT 24
Peak memory 206048 kb
Host smart-f474cbef-9b17-4782-bd41-d051b0188e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38042
82271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3804282271
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.1625572802
Short name T1350
Test name
Test status
Simulation time 321817346 ps
CPU time 1.05 seconds
Started Jun 21 04:57:09 PM PDT 24
Finished Jun 21 04:57:12 PM PDT 24
Peak memory 206044 kb
Host smart-f045213a-9565-4242-bc4e-8c2159656bf8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1625572802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.1625572802
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.108307825
Short name T1358
Test name
Test status
Simulation time 150380554 ps
CPU time 0.76 seconds
Started Jun 21 04:57:10 PM PDT 24
Finished Jun 21 04:57:13 PM PDT 24
Peak memory 205968 kb
Host smart-7206315f-49c0-4ff0-b73d-eade9c27487b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10830
7825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.108307825
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2692628413
Short name T409
Test name
Test status
Simulation time 41847624 ps
CPU time 0.67 seconds
Started Jun 21 04:57:09 PM PDT 24
Finished Jun 21 04:57:12 PM PDT 24
Peak memory 206032 kb
Host smart-81c4a260-48ae-465d-abe5-991739324559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26926
28413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2692628413
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.560746745
Short name T2345
Test name
Test status
Simulation time 8506385323 ps
CPU time 19.06 seconds
Started Jun 21 04:57:07 PM PDT 24
Finished Jun 21 04:57:29 PM PDT 24
Peak memory 206296 kb
Host smart-9ab30494-efa5-4716-aa26-f9c46dbde4c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56074
6745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.560746745
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.1622503752
Short name T553
Test name
Test status
Simulation time 198987516 ps
CPU time 0.9 seconds
Started Jun 21 04:57:08 PM PDT 24
Finished Jun 21 04:57:11 PM PDT 24
Peak memory 205928 kb
Host smart-9c270025-1932-4358-8051-d7e64cd1c42b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16225
03752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1622503752
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.639420005
Short name T1141
Test name
Test status
Simulation time 172929763 ps
CPU time 0.8 seconds
Started Jun 21 04:57:10 PM PDT 24
Finished Jun 21 04:57:13 PM PDT 24
Peak memory 206024 kb
Host smart-6dbe9772-044e-4101-94d6-6cce32598ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63942
0005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.639420005
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.333662150
Short name T28
Test name
Test status
Simulation time 215857858 ps
CPU time 0.88 seconds
Started Jun 21 04:57:09 PM PDT 24
Finished Jun 21 04:57:12 PM PDT 24
Peak memory 206024 kb
Host smart-c20875d0-8cf4-40a6-b32d-c0583fc4798d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33366
2150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.333662150
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.2863253328
Short name T1453
Test name
Test status
Simulation time 178812219 ps
CPU time 0.88 seconds
Started Jun 21 04:57:07 PM PDT 24
Finished Jun 21 04:57:10 PM PDT 24
Peak memory 206044 kb
Host smart-14494ee4-becd-4155-a328-acd9de3080f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28632
53328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.2863253328
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.3363344877
Short name T599
Test name
Test status
Simulation time 147589905 ps
CPU time 0.77 seconds
Started Jun 21 04:57:09 PM PDT 24
Finished Jun 21 04:57:12 PM PDT 24
Peak memory 206016 kb
Host smart-823b7a33-42ae-4233-a031-00cd7fba6229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33633
44877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.3363344877
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2202996911
Short name T345
Test name
Test status
Simulation time 163331791 ps
CPU time 0.74 seconds
Started Jun 21 04:57:12 PM PDT 24
Finished Jun 21 04:57:14 PM PDT 24
Peak memory 205964 kb
Host smart-e455b90f-d5ac-48a2-bc61-c421a8291f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22029
96911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2202996911
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2187356499
Short name T619
Test name
Test status
Simulation time 146808130 ps
CPU time 0.82 seconds
Started Jun 21 04:57:08 PM PDT 24
Finished Jun 21 04:57:11 PM PDT 24
Peak memory 206144 kb
Host smart-cc96f71a-91a9-487f-8662-2af53a14bf89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21873
56499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2187356499
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.4051914555
Short name T930
Test name
Test status
Simulation time 248328584 ps
CPU time 0.98 seconds
Started Jun 21 04:57:01 PM PDT 24
Finished Jun 21 04:57:05 PM PDT 24
Peak memory 205928 kb
Host smart-5a933862-75e6-4321-9c80-42a5b11e79f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40519
14555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.4051914555
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.3584050219
Short name T151
Test name
Test status
Simulation time 11036615600 ps
CPU time 80.36 seconds
Started Jun 21 04:57:08 PM PDT 24
Finished Jun 21 04:58:31 PM PDT 24
Peak memory 206212 kb
Host smart-7af86d90-3d1b-42db-9dc9-c319caed1b4d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3584050219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.3584050219
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2905822730
Short name T955
Test name
Test status
Simulation time 192741318 ps
CPU time 0.78 seconds
Started Jun 21 04:57:10 PM PDT 24
Finished Jun 21 04:57:13 PM PDT 24
Peak memory 205980 kb
Host smart-a2519ec6-41d0-4736-8d66-93b40812c126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29058
22730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2905822730
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.2761784532
Short name T1716
Test name
Test status
Simulation time 189710362 ps
CPU time 0.84 seconds
Started Jun 21 04:57:12 PM PDT 24
Finished Jun 21 04:57:15 PM PDT 24
Peak memory 205920 kb
Host smart-4a524278-6100-4c10-a95f-f4a1b620992b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27617
84532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.2761784532
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.934061692
Short name T1384
Test name
Test status
Simulation time 8177707659 ps
CPU time 73.65 seconds
Started Jun 21 04:57:09 PM PDT 24
Finished Jun 21 04:58:25 PM PDT 24
Peak memory 206332 kb
Host smart-55791a51-bce8-4483-a9e6-8f5993332f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93406
1692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.934061692
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.1646693607
Short name T691
Test name
Test status
Simulation time 4121129430 ps
CPU time 5.26 seconds
Started Jun 21 04:53:45 PM PDT 24
Finished Jun 21 04:53:52 PM PDT 24
Peak memory 206108 kb
Host smart-bfdcada0-95e1-4cec-b52e-ce79bc4f0c29
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1646693607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.1646693607
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.3581356368
Short name T1774
Test name
Test status
Simulation time 13368592919 ps
CPU time 13.66 seconds
Started Jun 21 04:53:46 PM PDT 24
Finished Jun 21 04:54:01 PM PDT 24
Peak memory 206240 kb
Host smart-79d414ab-760d-4835-b72c-d97b403332c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3581356368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.3581356368
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.965293887
Short name T14
Test name
Test status
Simulation time 23423968236 ps
CPU time 26.34 seconds
Started Jun 21 04:53:45 PM PDT 24
Finished Jun 21 04:54:12 PM PDT 24
Peak memory 206128 kb
Host smart-ae7e44d3-7c44-4a1a-a5f6-ebf4ef73b4c1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=965293887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.965293887
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.379832773
Short name T1818
Test name
Test status
Simulation time 153084035 ps
CPU time 0.79 seconds
Started Jun 21 04:53:44 PM PDT 24
Finished Jun 21 04:53:45 PM PDT 24
Peak memory 206024 kb
Host smart-2b98af5b-e857-49a7-a1cd-dd850b1f56d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37983
2773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.379832773
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.1370742515
Short name T45
Test name
Test status
Simulation time 192397590 ps
CPU time 0.83 seconds
Started Jun 21 04:53:53 PM PDT 24
Finished Jun 21 04:53:55 PM PDT 24
Peak memory 206024 kb
Host smart-19979914-8aca-4c21-8125-65ad44f5c2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13707
42515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.1370742515
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.206174100
Short name T62
Test name
Test status
Simulation time 169978919 ps
CPU time 0.76 seconds
Started Jun 21 04:53:50 PM PDT 24
Finished Jun 21 04:53:52 PM PDT 24
Peak memory 206024 kb
Host smart-a30d3d8a-3cb5-4976-8cce-f3a669bab748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20617
4100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.206174100
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.3950140208
Short name T1289
Test name
Test status
Simulation time 208724496 ps
CPU time 0.86 seconds
Started Jun 21 04:53:47 PM PDT 24
Finished Jun 21 04:53:49 PM PDT 24
Peak memory 205928 kb
Host smart-a4b74786-8ea1-43fd-a08b-ff519442f05b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39501
40208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.3950140208
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.373861104
Short name T757
Test name
Test status
Simulation time 282982621 ps
CPU time 1.06 seconds
Started Jun 21 04:53:50 PM PDT 24
Finished Jun 21 04:53:52 PM PDT 24
Peak memory 206028 kb
Host smart-1f85b0cf-d830-46ad-8375-12b4cd7e9b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37386
1104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.373861104
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.453546362
Short name T2314
Test name
Test status
Simulation time 1086282491 ps
CPU time 2.27 seconds
Started Jun 21 04:53:49 PM PDT 24
Finished Jun 21 04:53:52 PM PDT 24
Peak memory 206192 kb
Host smart-5827da90-0fe5-4e6d-8e62-f936aea9f08c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45354
6362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.453546362
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.690745733
Short name T1086
Test name
Test status
Simulation time 7867830533 ps
CPU time 13.5 seconds
Started Jun 21 04:53:49 PM PDT 24
Finished Jun 21 04:54:03 PM PDT 24
Peak memory 206244 kb
Host smart-174ae50f-bc17-4ff3-8fb4-eafcadd2c03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69074
5733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.690745733
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.3851478396
Short name T1490
Test name
Test status
Simulation time 449586849 ps
CPU time 1.38 seconds
Started Jun 21 04:53:49 PM PDT 24
Finished Jun 21 04:53:51 PM PDT 24
Peak memory 205952 kb
Host smart-b1f1be4a-d487-47ee-9989-7ef7603a057d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38514
78396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.3851478396
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2528431816
Short name T1456
Test name
Test status
Simulation time 145194098 ps
CPU time 0.74 seconds
Started Jun 21 04:53:49 PM PDT 24
Finished Jun 21 04:53:50 PM PDT 24
Peak memory 206028 kb
Host smart-0142cf0a-5dce-4eb1-9411-05519d2d2ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25284
31816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2528431816
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.1795013402
Short name T2156
Test name
Test status
Simulation time 45328985 ps
CPU time 0.7 seconds
Started Jun 21 04:53:51 PM PDT 24
Finished Jun 21 04:53:52 PM PDT 24
Peak memory 206016 kb
Host smart-9b851733-29ab-43f4-9ace-d4531674c72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17950
13402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1795013402
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1504679295
Short name T2060
Test name
Test status
Simulation time 880168802 ps
CPU time 1.96 seconds
Started Jun 21 04:53:50 PM PDT 24
Finished Jun 21 04:53:53 PM PDT 24
Peak memory 206272 kb
Host smart-a7096ccc-8a5c-4b94-aef8-668781b98a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15046
79295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1504679295
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.836218403
Short name T2058
Test name
Test status
Simulation time 390989603 ps
CPU time 2.48 seconds
Started Jun 21 04:53:53 PM PDT 24
Finished Jun 21 04:53:57 PM PDT 24
Peak memory 206168 kb
Host smart-d9d55978-0b97-414f-8e04-397141e53115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83621
8403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.836218403
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.108703118
Short name T114
Test name
Test status
Simulation time 190918001 ps
CPU time 0.89 seconds
Started Jun 21 04:53:57 PM PDT 24
Finished Jun 21 04:54:00 PM PDT 24
Peak memory 206024 kb
Host smart-6be3e4d6-17ac-4563-bca5-6ad15ded715d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10870
3118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.108703118
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.63369047
Short name T1306
Test name
Test status
Simulation time 145895547 ps
CPU time 0.75 seconds
Started Jun 21 04:53:57 PM PDT 24
Finished Jun 21 04:53:59 PM PDT 24
Peak memory 206000 kb
Host smart-627e5f44-9a7d-4460-b4ef-273918bf5b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63369
047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.63369047
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2751301024
Short name T1690
Test name
Test status
Simulation time 226801035 ps
CPU time 0.9 seconds
Started Jun 21 04:53:53 PM PDT 24
Finished Jun 21 04:53:55 PM PDT 24
Peak memory 205940 kb
Host smart-18d5051a-ff44-421b-8b9e-271ac097a3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27513
01024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2751301024
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.1659952673
Short name T101
Test name
Test status
Simulation time 13722126225 ps
CPU time 385.22 seconds
Started Jun 21 04:53:50 PM PDT 24
Finished Jun 21 05:00:17 PM PDT 24
Peak memory 206208 kb
Host smart-69ea3aee-fdff-4c25-9401-9ab724c076c2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1659952673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.1659952673
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.722116257
Short name T590
Test name
Test status
Simulation time 267895307 ps
CPU time 0.9 seconds
Started Jun 21 04:53:54 PM PDT 24
Finished Jun 21 04:53:56 PM PDT 24
Peak memory 206028 kb
Host smart-4d5c636f-4a6d-45d5-938c-22847be7599d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72211
6257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.722116257
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.3301546486
Short name T782
Test name
Test status
Simulation time 23315651570 ps
CPU time 22.72 seconds
Started Jun 21 04:53:54 PM PDT 24
Finished Jun 21 04:54:18 PM PDT 24
Peak memory 205992 kb
Host smart-6c63cab4-d1b5-4578-84a9-270c842af9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33015
46486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.3301546486
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.2326319372
Short name T1679
Test name
Test status
Simulation time 3330568283 ps
CPU time 3.87 seconds
Started Jun 21 04:53:52 PM PDT 24
Finished Jun 21 04:53:58 PM PDT 24
Peak memory 205988 kb
Host smart-693231ac-99ec-4e51-8c6e-e55c0b315764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23263
19372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.2326319372
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.2256696432
Short name T1728
Test name
Test status
Simulation time 5983131227 ps
CPU time 164.27 seconds
Started Jun 21 04:53:49 PM PDT 24
Finished Jun 21 04:56:34 PM PDT 24
Peak memory 206212 kb
Host smart-f4e7ebe5-06c4-406f-a391-39236b384079
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2256696432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.2256696432
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.1916006479
Short name T2000
Test name
Test status
Simulation time 273149824 ps
CPU time 0.96 seconds
Started Jun 21 04:53:57 PM PDT 24
Finished Jun 21 04:53:59 PM PDT 24
Peak memory 206052 kb
Host smart-08de26d8-8a73-452a-bdbd-aedce94b405d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1916006479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.1916006479
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2275603026
Short name T1579
Test name
Test status
Simulation time 196779391 ps
CPU time 0.88 seconds
Started Jun 21 04:53:50 PM PDT 24
Finished Jun 21 04:53:52 PM PDT 24
Peak memory 206000 kb
Host smart-5803e710-2d5a-4620-ad9b-d3b00cc016aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22756
03026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2275603026
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.2901144005
Short name T2441
Test name
Test status
Simulation time 4042788101 ps
CPU time 113.39 seconds
Started Jun 21 04:53:54 PM PDT 24
Finished Jun 21 04:55:48 PM PDT 24
Peak memory 205920 kb
Host smart-f3bb6d2a-3b3f-48fb-a9b8-1ca73aa1ffe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29011
44005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.2901144005
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1577579487
Short name T1713
Test name
Test status
Simulation time 7673941592 ps
CPU time 74.61 seconds
Started Jun 21 04:53:53 PM PDT 24
Finished Jun 21 04:55:09 PM PDT 24
Peak memory 206024 kb
Host smart-e2710678-29c9-4af5-8c56-ec11d355550b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1577579487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1577579487
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.4031370686
Short name T924
Test name
Test status
Simulation time 151967312 ps
CPU time 0.81 seconds
Started Jun 21 04:53:55 PM PDT 24
Finished Jun 21 04:53:57 PM PDT 24
Peak memory 206048 kb
Host smart-fbd1d387-afec-4f32-8a7d-4c6705ef056c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4031370686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.4031370686
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2007422423
Short name T1274
Test name
Test status
Simulation time 212553484 ps
CPU time 0.85 seconds
Started Jun 21 04:53:49 PM PDT 24
Finished Jun 21 04:53:50 PM PDT 24
Peak memory 205996 kb
Host smart-5a1cbcc0-afa3-48c1-b8fc-47e4cbb69065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20074
22423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2007422423
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2293930047
Short name T136
Test name
Test status
Simulation time 236603012 ps
CPU time 0.9 seconds
Started Jun 21 04:53:53 PM PDT 24
Finished Jun 21 04:53:55 PM PDT 24
Peak memory 205920 kb
Host smart-2152ee0a-a8bc-4cf1-880b-ad9e1d4d4473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22939
30047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2293930047
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2292519927
Short name T1976
Test name
Test status
Simulation time 225011790 ps
CPU time 0.84 seconds
Started Jun 21 04:53:52 PM PDT 24
Finished Jun 21 04:53:54 PM PDT 24
Peak memory 206028 kb
Host smart-09ec1238-e334-457f-9645-d37da1cc2613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22925
19927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2292519927
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3773624383
Short name T705
Test name
Test status
Simulation time 210737083 ps
CPU time 0.83 seconds
Started Jun 21 04:53:50 PM PDT 24
Finished Jun 21 04:53:51 PM PDT 24
Peak memory 206144 kb
Host smart-38947964-2f79-45cc-af0b-61af366f0546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37736
24383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3773624383
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2487720708
Short name T2003
Test name
Test status
Simulation time 204945917 ps
CPU time 0.89 seconds
Started Jun 21 04:53:53 PM PDT 24
Finished Jun 21 04:53:55 PM PDT 24
Peak memory 205932 kb
Host smart-785d6ed3-43c5-4d2d-9ef1-400665119322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24877
20708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2487720708
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1521246238
Short name T1124
Test name
Test status
Simulation time 146568098 ps
CPU time 0.78 seconds
Started Jun 21 04:53:58 PM PDT 24
Finished Jun 21 04:54:00 PM PDT 24
Peak memory 205968 kb
Host smart-46092bfa-9fdb-4038-88fe-dc52665395e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15212
46238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1521246238
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.3115412686
Short name T2114
Test name
Test status
Simulation time 189327589 ps
CPU time 0.89 seconds
Started Jun 21 04:53:57 PM PDT 24
Finished Jun 21 04:53:58 PM PDT 24
Peak memory 205996 kb
Host smart-3608e06b-b0b5-408e-a83b-8abfb1eb3f2e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3115412686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.3115412686
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.37013049
Short name T1744
Test name
Test status
Simulation time 148559560 ps
CPU time 0.75 seconds
Started Jun 21 04:53:57 PM PDT 24
Finished Jun 21 04:53:59 PM PDT 24
Peak memory 205992 kb
Host smart-878f6dc9-7d44-4899-bcd9-fc891d6569c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37013
049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.37013049
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2627205262
Short name T1820
Test name
Test status
Simulation time 99495497 ps
CPU time 0.7 seconds
Started Jun 21 04:53:56 PM PDT 24
Finished Jun 21 04:53:57 PM PDT 24
Peak memory 206036 kb
Host smart-93447031-e248-42ff-a304-21dee13faaad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26272
05262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2627205262
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.610768783
Short name T995
Test name
Test status
Simulation time 13183681278 ps
CPU time 29.26 seconds
Started Jun 21 04:53:53 PM PDT 24
Finished Jun 21 04:54:23 PM PDT 24
Peak memory 206196 kb
Host smart-4913327a-3c7a-48b1-aa3f-763ad9804a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61076
8783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.610768783
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1150658588
Short name T2286
Test name
Test status
Simulation time 180580699 ps
CPU time 0.82 seconds
Started Jun 21 04:53:52 PM PDT 24
Finished Jun 21 04:53:54 PM PDT 24
Peak memory 205932 kb
Host smart-973f0343-e902-4c91-b139-3261e7438721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11506
58588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1150658588
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.4246824939
Short name T2350
Test name
Test status
Simulation time 246854111 ps
CPU time 0.93 seconds
Started Jun 21 04:53:50 PM PDT 24
Finished Jun 21 04:53:52 PM PDT 24
Peak memory 206024 kb
Host smart-a839e423-3854-46a7-a6aa-b19868742718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42468
24939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.4246824939
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.4101359656
Short name T1601
Test name
Test status
Simulation time 10750232937 ps
CPU time 73.28 seconds
Started Jun 21 04:53:52 PM PDT 24
Finished Jun 21 04:55:07 PM PDT 24
Peak memory 206316 kb
Host smart-89f46652-ddfe-4c92-bb19-427914f14040
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4101359656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.4101359656
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.1061522989
Short name T163
Test name
Test status
Simulation time 10489275169 ps
CPU time 181.25 seconds
Started Jun 21 04:53:53 PM PDT 24
Finished Jun 21 04:56:55 PM PDT 24
Peak memory 206252 kb
Host smart-9b7abecf-b833-40b5-a289-e870de725e68
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1061522989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.1061522989
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.1994366824
Short name T1925
Test name
Test status
Simulation time 36293207921 ps
CPU time 922.69 seconds
Started Jun 21 04:53:53 PM PDT 24
Finished Jun 21 05:09:17 PM PDT 24
Peak memory 206252 kb
Host smart-12d826c2-da10-45c9-8710-96186fa55145
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1994366824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.1994366824
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.1908421842
Short name T2157
Test name
Test status
Simulation time 196702000 ps
CPU time 0.82 seconds
Started Jun 21 04:53:58 PM PDT 24
Finished Jun 21 04:54:00 PM PDT 24
Peak memory 205976 kb
Host smart-2f4ad88d-7364-4f5a-8c29-08665c514016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19084
21842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1908421842
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.3602866675
Short name T1263
Test name
Test status
Simulation time 188535211 ps
CPU time 0.95 seconds
Started Jun 21 04:53:53 PM PDT 24
Finished Jun 21 04:53:55 PM PDT 24
Peak memory 205944 kb
Host smart-72375243-256c-4dc2-b798-83d11675d7cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36028
66675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.3602866675
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.2602779121
Short name T1484
Test name
Test status
Simulation time 171592931 ps
CPU time 0.8 seconds
Started Jun 21 04:53:57 PM PDT 24
Finished Jun 21 04:53:59 PM PDT 24
Peak memory 206008 kb
Host smart-26f57a17-747d-4c79-9b22-596bf5c78cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26027
79121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.2602779121
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1025444605
Short name T197
Test name
Test status
Simulation time 446306108 ps
CPU time 1.34 seconds
Started Jun 21 04:53:58 PM PDT 24
Finished Jun 21 04:54:01 PM PDT 24
Peak memory 224864 kb
Host smart-478e4b70-eb14-44f1-a924-840efa313b2a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1025444605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1025444605
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.480088489
Short name T49
Test name
Test status
Simulation time 512397039 ps
CPU time 1.4 seconds
Started Jun 21 04:53:50 PM PDT 24
Finished Jun 21 04:53:53 PM PDT 24
Peak memory 205992 kb
Host smart-1e5c1a5b-a615-4140-93ed-8c71e4856adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48008
8489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.480088489
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1680291646
Short name T556
Test name
Test status
Simulation time 149732068 ps
CPU time 0.76 seconds
Started Jun 21 04:53:58 PM PDT 24
Finished Jun 21 04:54:00 PM PDT 24
Peak memory 205924 kb
Host smart-914d9193-fba2-452f-9e85-ead0c0694da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16802
91646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1680291646
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.40900020
Short name T2116
Test name
Test status
Simulation time 155134217 ps
CPU time 0.77 seconds
Started Jun 21 04:53:56 PM PDT 24
Finished Jun 21 04:53:58 PM PDT 24
Peak memory 205976 kb
Host smart-c2884e8b-a7b9-44c4-9f1a-9c63991f76f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40900
020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.40900020
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.1935294287
Short name T2236
Test name
Test status
Simulation time 277149199 ps
CPU time 0.97 seconds
Started Jun 21 04:53:45 PM PDT 24
Finished Jun 21 04:53:47 PM PDT 24
Peak memory 205964 kb
Host smart-5e0abf4d-787a-4ba2-a09d-037c7581a229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19352
94287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1935294287
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.384137739
Short name T1997
Test name
Test status
Simulation time 5721334058 ps
CPU time 50.98 seconds
Started Jun 21 04:53:53 PM PDT 24
Finished Jun 21 04:54:45 PM PDT 24
Peak memory 206276 kb
Host smart-ff2fdf60-84bf-44ae-89c6-c883be9614a2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=384137739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.384137739
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.680387475
Short name T1278
Test name
Test status
Simulation time 176508007 ps
CPU time 0.86 seconds
Started Jun 21 04:53:55 PM PDT 24
Finished Jun 21 04:53:57 PM PDT 24
Peak memory 206032 kb
Host smart-3c346355-5abb-456e-be4e-6f574cd0270a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68038
7475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.680387475
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1677527941
Short name T1256
Test name
Test status
Simulation time 161150999 ps
CPU time 0.77 seconds
Started Jun 21 04:53:51 PM PDT 24
Finished Jun 21 04:53:52 PM PDT 24
Peak memory 205964 kb
Host smart-7f679473-c08c-4247-886f-dc645a58553c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16775
27941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1677527941
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.795176850
Short name T1064
Test name
Test status
Simulation time 9668334868 ps
CPU time 77.3 seconds
Started Jun 21 04:53:58 PM PDT 24
Finished Jun 21 04:55:16 PM PDT 24
Peak memory 206256 kb
Host smart-4374b885-ca31-4a5b-a0c8-c53ce9165acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79517
6850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.795176850
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.1147119245
Short name T1481
Test name
Test status
Simulation time 12462894141 ps
CPU time 227.05 seconds
Started Jun 21 04:53:57 PM PDT 24
Finished Jun 21 04:57:45 PM PDT 24
Peak memory 206212 kb
Host smart-b7af20bb-f934-4b43-97b8-776c93d32689
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1147119245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.1147119245
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.894617108
Short name T1726
Test name
Test status
Simulation time 4278805210 ps
CPU time 4.63 seconds
Started Jun 21 04:57:09 PM PDT 24
Finished Jun 21 04:57:16 PM PDT 24
Peak memory 206040 kb
Host smart-0ba24b76-48ed-427b-8bbf-38cc889df1e6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=894617108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.894617108
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.3579894407
Short name T2408
Test name
Test status
Simulation time 13424047486 ps
CPU time 14.05 seconds
Started Jun 21 04:57:12 PM PDT 24
Finished Jun 21 04:57:28 PM PDT 24
Peak memory 206040 kb
Host smart-96584e48-85fc-41c6-8ce3-729a4910d3f0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3579894407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.3579894407
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1227334573
Short name T774
Test name
Test status
Simulation time 23346589701 ps
CPU time 22.9 seconds
Started Jun 21 04:57:08 PM PDT 24
Finished Jun 21 04:57:33 PM PDT 24
Peak memory 206148 kb
Host smart-7e8e2d0c-d6a5-4869-a51d-1f65fd91f22e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1227334573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.1227334573
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.106662691
Short name T365
Test name
Test status
Simulation time 177008812 ps
CPU time 0.86 seconds
Started Jun 21 04:57:09 PM PDT 24
Finished Jun 21 04:57:13 PM PDT 24
Peak memory 206028 kb
Host smart-91ed1f6a-8d70-46a7-aa28-662eb34cdac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10666
2691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.106662691
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.2525838945
Short name T57
Test name
Test status
Simulation time 165685233 ps
CPU time 0.8 seconds
Started Jun 21 04:57:09 PM PDT 24
Finished Jun 21 04:57:13 PM PDT 24
Peak memory 205996 kb
Host smart-bc4a2cb5-5698-4119-a117-cd2a03724713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25258
38945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.2525838945
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.3960372457
Short name T181
Test name
Test status
Simulation time 333413391 ps
CPU time 1.19 seconds
Started Jun 21 04:57:09 PM PDT 24
Finished Jun 21 04:57:13 PM PDT 24
Peak memory 205972 kb
Host smart-cb6edba3-5e60-44e9-9c6d-eccc96465d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39603
72457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.3960372457
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.3609193737
Short name T1786
Test name
Test status
Simulation time 678726462 ps
CPU time 1.7 seconds
Started Jun 21 04:57:09 PM PDT 24
Finished Jun 21 04:57:13 PM PDT 24
Peak memory 206128 kb
Host smart-79df9006-0e34-4a30-80da-b8d1f2799d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36091
93737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.3609193737
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.4289489156
Short name T1329
Test name
Test status
Simulation time 20558133165 ps
CPU time 42.79 seconds
Started Jun 21 04:57:10 PM PDT 24
Finished Jun 21 04:57:55 PM PDT 24
Peak memory 206312 kb
Host smart-629d33ca-29a3-4b3f-8be2-535de60f386b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42894
89156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.4289489156
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.3521847316
Short name T519
Test name
Test status
Simulation time 463850570 ps
CPU time 1.56 seconds
Started Jun 21 04:57:18 PM PDT 24
Finished Jun 21 04:57:21 PM PDT 24
Peak memory 206084 kb
Host smart-937d0f75-407a-448d-aaf3-99e6a07327df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35218
47316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3521847316
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2913074660
Short name T2418
Test name
Test status
Simulation time 146719053 ps
CPU time 0.77 seconds
Started Jun 21 04:57:18 PM PDT 24
Finished Jun 21 04:57:20 PM PDT 24
Peak memory 206140 kb
Host smart-459c7c84-e1b5-4b51-bc13-47c8c4634fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29130
74660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2913074660
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.765184122
Short name T1155
Test name
Test status
Simulation time 30267069 ps
CPU time 0.65 seconds
Started Jun 21 04:57:17 PM PDT 24
Finished Jun 21 04:57:19 PM PDT 24
Peak memory 206020 kb
Host smart-b125cc3c-dafe-4406-88ff-4cdf13d5a902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76518
4122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.765184122
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.502857728
Short name T537
Test name
Test status
Simulation time 849206368 ps
CPU time 2.18 seconds
Started Jun 21 04:57:16 PM PDT 24
Finished Jun 21 04:57:19 PM PDT 24
Peak memory 206204 kb
Host smart-a84ced4f-2d0b-4bbf-9d48-1b2dfe743131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50285
7728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.502857728
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2335213512
Short name T403
Test name
Test status
Simulation time 334268983 ps
CPU time 2.49 seconds
Started Jun 21 04:57:18 PM PDT 24
Finished Jun 21 04:57:22 PM PDT 24
Peak memory 206208 kb
Host smart-403071c0-c671-424d-9707-6de9818d2ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23352
13512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2335213512
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3423731306
Short name T1840
Test name
Test status
Simulation time 220414380 ps
CPU time 0.91 seconds
Started Jun 21 04:57:24 PM PDT 24
Finished Jun 21 04:57:26 PM PDT 24
Peak memory 206028 kb
Host smart-395414b6-c9ee-4be9-a13e-c2019cf0fee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34237
31306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3423731306
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3628025802
Short name T296
Test name
Test status
Simulation time 163264095 ps
CPU time 0.89 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:57:29 PM PDT 24
Peak memory 205916 kb
Host smart-a13687ee-1921-404a-a3b9-c0781be98bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36280
25802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3628025802
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1776365628
Short name T1262
Test name
Test status
Simulation time 167383848 ps
CPU time 0.85 seconds
Started Jun 21 04:57:18 PM PDT 24
Finished Jun 21 04:57:20 PM PDT 24
Peak memory 205972 kb
Host smart-e89ff5c6-a5a2-499b-a7c9-e4ccf73bc6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17763
65628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1776365628
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3894371845
Short name T1479
Test name
Test status
Simulation time 169021969 ps
CPU time 0.84 seconds
Started Jun 21 04:57:19 PM PDT 24
Finished Jun 21 04:57:21 PM PDT 24
Peak memory 205044 kb
Host smart-76877bb3-790f-4840-85e9-9133a75a8412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38943
71845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3894371845
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.2841323495
Short name T2398
Test name
Test status
Simulation time 23332939269 ps
CPU time 28.74 seconds
Started Jun 21 04:57:16 PM PDT 24
Finished Jun 21 04:57:45 PM PDT 24
Peak memory 205988 kb
Host smart-ad67e269-795d-4d2a-b596-a304bece5fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28413
23495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.2841323495
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.3682187030
Short name T1782
Test name
Test status
Simulation time 3343770792 ps
CPU time 3.5 seconds
Started Jun 21 04:57:17 PM PDT 24
Finished Jun 21 04:57:22 PM PDT 24
Peak memory 206024 kb
Host smart-1c19f8db-7e8a-4d3e-95d8-b1b72177bcf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36821
87030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.3682187030
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2972864614
Short name T2474
Test name
Test status
Simulation time 5886200835 ps
CPU time 171.68 seconds
Started Jun 21 04:57:17 PM PDT 24
Finished Jun 21 05:00:10 PM PDT 24
Peak memory 206304 kb
Host smart-7eefecd0-d0a4-4d5f-a376-e376316b2747
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2972864614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2972864614
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.3604404402
Short name T2285
Test name
Test status
Simulation time 276336821 ps
CPU time 1.03 seconds
Started Jun 21 04:57:24 PM PDT 24
Finished Jun 21 04:57:26 PM PDT 24
Peak memory 206028 kb
Host smart-89fcdf34-e2ae-4c14-a9a1-42724560b6a1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3604404402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.3604404402
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1956025712
Short name T2205
Test name
Test status
Simulation time 195930043 ps
CPU time 0.85 seconds
Started Jun 21 04:57:15 PM PDT 24
Finished Jun 21 04:57:17 PM PDT 24
Peak memory 206036 kb
Host smart-35e457e0-9a71-4c93-8868-0c2fc7f28560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19560
25712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1956025712
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3516148998
Short name T1477
Test name
Test status
Simulation time 6584548389 ps
CPU time 181.16 seconds
Started Jun 21 04:57:18 PM PDT 24
Finished Jun 21 05:00:20 PM PDT 24
Peak memory 206176 kb
Host smart-b068cfcd-d05c-4439-be2b-5d9c56d91121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35161
48998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3516148998
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.555660106
Short name T1986
Test name
Test status
Simulation time 9404840141 ps
CPU time 251.45 seconds
Started Jun 21 04:57:18 PM PDT 24
Finished Jun 21 05:01:31 PM PDT 24
Peak memory 206172 kb
Host smart-bec8222c-60b1-4ef8-bea4-14856114503a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=555660106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.555660106
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1593266560
Short name T818
Test name
Test status
Simulation time 171352610 ps
CPU time 0.79 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:57:29 PM PDT 24
Peak memory 205992 kb
Host smart-120bc435-249c-45bc-befe-d089d20bf188
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1593266560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1593266560
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.880618042
Short name T2124
Test name
Test status
Simulation time 152611232 ps
CPU time 0.83 seconds
Started Jun 21 04:57:18 PM PDT 24
Finished Jun 21 04:57:20 PM PDT 24
Peak memory 205960 kb
Host smart-df6ce160-d4ae-462b-a65d-639070553aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88061
8042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.880618042
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1390924639
Short name T2083
Test name
Test status
Simulation time 224519678 ps
CPU time 0.83 seconds
Started Jun 21 04:57:15 PM PDT 24
Finished Jun 21 04:57:17 PM PDT 24
Peak memory 205972 kb
Host smart-bb816efa-75b8-46d6-92df-b501c269a19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13909
24639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1390924639
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.1797792852
Short name T2108
Test name
Test status
Simulation time 162432557 ps
CPU time 0.8 seconds
Started Jun 21 04:57:17 PM PDT 24
Finished Jun 21 04:57:19 PM PDT 24
Peak memory 206020 kb
Host smart-877ea38e-c7d3-40ec-a8d3-757bd8263a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17977
92852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.1797792852
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.4210615670
Short name T1261
Test name
Test status
Simulation time 174105265 ps
CPU time 0.78 seconds
Started Jun 21 04:57:16 PM PDT 24
Finished Jun 21 04:57:17 PM PDT 24
Peak memory 205964 kb
Host smart-f8e8adf2-6806-4cd3-9889-613a3bb5359b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42106
15670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.4210615670
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.981000025
Short name T1606
Test name
Test status
Simulation time 230015360 ps
CPU time 0.93 seconds
Started Jun 21 04:57:18 PM PDT 24
Finished Jun 21 04:57:20 PM PDT 24
Peak memory 205920 kb
Host smart-86c05f6b-6a74-4ce8-a2b6-1df7529c944d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98100
0025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.981000025
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.1929101827
Short name T621
Test name
Test status
Simulation time 164076532 ps
CPU time 0.82 seconds
Started Jun 21 04:57:24 PM PDT 24
Finished Jun 21 04:57:26 PM PDT 24
Peak memory 205932 kb
Host smart-3f4de990-7cdc-4662-89a2-7e74e8d6930a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19291
01827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1929101827
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.2982867082
Short name T960
Test name
Test status
Simulation time 236491422 ps
CPU time 0.92 seconds
Started Jun 21 04:57:18 PM PDT 24
Finished Jun 21 04:57:20 PM PDT 24
Peak memory 206000 kb
Host smart-aa5ecc6f-545b-4386-9b6e-aa1c35f5b124
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2982867082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.2982867082
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3268086134
Short name T1374
Test name
Test status
Simulation time 137663262 ps
CPU time 0.72 seconds
Started Jun 21 04:57:23 PM PDT 24
Finished Jun 21 04:57:25 PM PDT 24
Peak memory 205980 kb
Host smart-0c333c09-bb67-4d63-bd6d-f0c7d144e7a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32680
86134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3268086134
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2058474262
Short name T34
Test name
Test status
Simulation time 52535263 ps
CPU time 0.71 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:57:29 PM PDT 24
Peak memory 206028 kb
Host smart-c3290147-be0e-42a3-93e7-f61650c9d70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20584
74262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2058474262
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1861167508
Short name T1106
Test name
Test status
Simulation time 14362603052 ps
CPU time 30.95 seconds
Started Jun 21 04:57:16 PM PDT 24
Finished Jun 21 04:57:48 PM PDT 24
Peak memory 206276 kb
Host smart-750e495e-d495-47f9-a1af-3f8f8cfa09c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18611
67508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1861167508
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1736897366
Short name T826
Test name
Test status
Simulation time 175182654 ps
CPU time 0.83 seconds
Started Jun 21 04:57:17 PM PDT 24
Finished Jun 21 04:57:19 PM PDT 24
Peak memory 206024 kb
Host smart-c48d0597-8c3f-4786-9e4b-b4cfb7521af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17368
97366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1736897366
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2877643444
Short name T574
Test name
Test status
Simulation time 196053048 ps
CPU time 0.83 seconds
Started Jun 21 04:57:16 PM PDT 24
Finished Jun 21 04:57:18 PM PDT 24
Peak memory 206048 kb
Host smart-ce2e710c-8342-4f97-b113-b5ec1415d895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28776
43444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2877643444
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3621540917
Short name T402
Test name
Test status
Simulation time 178829332 ps
CPU time 0.84 seconds
Started Jun 21 04:57:28 PM PDT 24
Finished Jun 21 04:57:32 PM PDT 24
Peak memory 205928 kb
Host smart-ad8051a6-1b22-4f40-870f-715a3bcea0b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36215
40917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3621540917
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.1575943969
Short name T508
Test name
Test status
Simulation time 192159864 ps
CPU time 0.85 seconds
Started Jun 21 04:57:17 PM PDT 24
Finished Jun 21 04:57:20 PM PDT 24
Peak memory 206004 kb
Host smart-f472402e-8ddc-4198-9b06-07ac563e24f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15759
43969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.1575943969
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.1035697184
Short name T42
Test name
Test status
Simulation time 157387884 ps
CPU time 0.75 seconds
Started Jun 21 04:57:17 PM PDT 24
Finished Jun 21 04:57:19 PM PDT 24
Peak memory 205960 kb
Host smart-9c81c943-3d34-4cd9-8861-89e444a56858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10356
97184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.1035697184
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1255222676
Short name T1140
Test name
Test status
Simulation time 205716358 ps
CPU time 0.83 seconds
Started Jun 21 04:57:27 PM PDT 24
Finished Jun 21 04:57:31 PM PDT 24
Peak memory 206140 kb
Host smart-82a62042-f01e-40bf-b0e3-f809f058958b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12552
22676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1255222676
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2702018551
Short name T97
Test name
Test status
Simulation time 151840839 ps
CPU time 0.76 seconds
Started Jun 21 04:57:16 PM PDT 24
Finished Jun 21 04:57:18 PM PDT 24
Peak memory 205964 kb
Host smart-6ffdfb37-b335-4492-aa91-1a9eecc385df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27020
18551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2702018551
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1353009352
Short name T2451
Test name
Test status
Simulation time 223362543 ps
CPU time 0.93 seconds
Started Jun 21 04:57:10 PM PDT 24
Finished Jun 21 04:57:13 PM PDT 24
Peak memory 205976 kb
Host smart-41e0f112-cf88-4a84-8f4a-60a27dc6d990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13530
09352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1353009352
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.978091820
Short name T1470
Test name
Test status
Simulation time 9978175039 ps
CPU time 279.53 seconds
Started Jun 21 04:57:17 PM PDT 24
Finished Jun 21 05:01:57 PM PDT 24
Peak memory 206188 kb
Host smart-0d242c91-642e-4910-9879-32c2e5ebefbb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=978091820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.978091820
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1641813899
Short name T1247
Test name
Test status
Simulation time 161524487 ps
CPU time 0.85 seconds
Started Jun 21 04:57:19 PM PDT 24
Finished Jun 21 04:57:21 PM PDT 24
Peak memory 204900 kb
Host smart-fb384ee7-da2b-49f8-a6d8-c5abc432b73a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16418
13899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1641813899
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1804662512
Short name T777
Test name
Test status
Simulation time 188500081 ps
CPU time 0.8 seconds
Started Jun 21 04:57:19 PM PDT 24
Finished Jun 21 04:57:21 PM PDT 24
Peak memory 205956 kb
Host smart-dbdecd2f-d09c-4267-84e9-175883dac0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18046
62512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1804662512
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.2565938121
Short name T1604
Test name
Test status
Simulation time 7454023328 ps
CPU time 209.02 seconds
Started Jun 21 04:57:18 PM PDT 24
Finished Jun 21 05:00:48 PM PDT 24
Peak memory 206248 kb
Host smart-7e2ba076-92d3-4c39-8f8f-a4f0e84968db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25659
38121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.2565938121
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3383484760
Short name T1033
Test name
Test status
Simulation time 4036008014 ps
CPU time 4.77 seconds
Started Jun 21 04:57:25 PM PDT 24
Finished Jun 21 04:57:31 PM PDT 24
Peak memory 206048 kb
Host smart-782b9a08-d081-4849-934d-ef595b1f2c63
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3383484760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.3383484760
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3990739425
Short name T2334
Test name
Test status
Simulation time 13331019752 ps
CPU time 13.43 seconds
Started Jun 21 04:57:27 PM PDT 24
Finished Jun 21 04:57:43 PM PDT 24
Peak memory 206288 kb
Host smart-361a1795-e6a2-48d7-8b12-a5349d6c9b29
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3990739425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3990739425
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.1745840573
Short name T1815
Test name
Test status
Simulation time 23460152951 ps
CPU time 23.92 seconds
Started Jun 21 04:57:28 PM PDT 24
Finished Jun 21 04:57:55 PM PDT 24
Peak memory 206276 kb
Host smart-18d04955-f6c4-47ff-b705-421d923e14fd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1745840573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.1745840573
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2053904021
Short name T903
Test name
Test status
Simulation time 205432981 ps
CPU time 0.81 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:57:28 PM PDT 24
Peak memory 206020 kb
Host smart-b30849e8-8b1e-4745-9db6-1b7ca0b7325d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20539
04021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2053904021
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.3028390982
Short name T1097
Test name
Test status
Simulation time 146357903 ps
CPU time 0.81 seconds
Started Jun 21 04:57:29 PM PDT 24
Finished Jun 21 04:57:32 PM PDT 24
Peak memory 205924 kb
Host smart-b26ba8cd-6dc2-417d-9cfa-35a3c653bac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30283
90982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.3028390982
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.2316978917
Short name T2443
Test name
Test status
Simulation time 211328127 ps
CPU time 0.91 seconds
Started Jun 21 04:57:24 PM PDT 24
Finished Jun 21 04:57:26 PM PDT 24
Peak memory 205996 kb
Host smart-3f11fb61-8e72-441a-acd2-801f25817a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23169
78917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.2316978917
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.352378305
Short name T961
Test name
Test status
Simulation time 1073853004 ps
CPU time 2.37 seconds
Started Jun 21 04:57:24 PM PDT 24
Finished Jun 21 04:57:28 PM PDT 24
Peak memory 206292 kb
Host smart-8300d3de-3802-4770-a2f1-caea74f252b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35237
8305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.352378305
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.610932374
Short name T1001
Test name
Test status
Simulation time 6669679997 ps
CPU time 14.69 seconds
Started Jun 21 04:57:25 PM PDT 24
Finished Jun 21 04:57:41 PM PDT 24
Peak memory 206312 kb
Host smart-a05ceb73-c800-4724-b7f1-eee46ad251ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61093
2374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.610932374
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.1772648391
Short name T614
Test name
Test status
Simulation time 339376584 ps
CPU time 1.22 seconds
Started Jun 21 04:57:24 PM PDT 24
Finished Jun 21 04:57:26 PM PDT 24
Peak memory 206028 kb
Host smart-2c89a5df-38cb-442c-ba73-9f7849f867c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17726
48391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.1772648391
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.988624669
Short name T527
Test name
Test status
Simulation time 145846121 ps
CPU time 0.76 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:57:28 PM PDT 24
Peak memory 206016 kb
Host smart-7086dae8-6fb8-41d1-84be-7381a8645c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98862
4669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.988624669
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2562581578
Short name T1410
Test name
Test status
Simulation time 58024797 ps
CPU time 0.66 seconds
Started Jun 21 04:57:28 PM PDT 24
Finished Jun 21 04:57:32 PM PDT 24
Peak memory 205956 kb
Host smart-0810daf9-0eb3-4abc-b7b4-fd2fbdf2d88b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25625
81578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2562581578
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3964825976
Short name T2370
Test name
Test status
Simulation time 801641269 ps
CPU time 2.13 seconds
Started Jun 21 04:57:27 PM PDT 24
Finished Jun 21 04:57:31 PM PDT 24
Peak memory 206208 kb
Host smart-7af1e025-3e08-4c54-8dee-56af949dd892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39648
25976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3964825976
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1063940820
Short name T531
Test name
Test status
Simulation time 252319924 ps
CPU time 1.6 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:57:29 PM PDT 24
Peak memory 206196 kb
Host smart-82de07a9-1e5f-49b1-a9d1-5c94553444d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10639
40820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1063940820
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.2603678369
Short name T366
Test name
Test status
Simulation time 191670845 ps
CPU time 0.87 seconds
Started Jun 21 04:57:32 PM PDT 24
Finished Jun 21 04:57:34 PM PDT 24
Peak memory 205960 kb
Host smart-f37e8bd8-4e37-46d0-b79f-5ca31faf256c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26036
78369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2603678369
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2375770277
Short name T1425
Test name
Test status
Simulation time 148711708 ps
CPU time 0.81 seconds
Started Jun 21 04:57:28 PM PDT 24
Finished Jun 21 04:57:32 PM PDT 24
Peak memory 206072 kb
Host smart-2bf1b623-8aab-4994-b73e-7f2d6f347116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23757
70277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2375770277
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.395342412
Short name T778
Test name
Test status
Simulation time 205730796 ps
CPU time 0.96 seconds
Started Jun 21 04:57:24 PM PDT 24
Finished Jun 21 04:57:26 PM PDT 24
Peak memory 206044 kb
Host smart-e799f771-2c99-4a45-8388-f7f86cebf3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39534
2412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.395342412
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.2564034004
Short name T889
Test name
Test status
Simulation time 187334125 ps
CPU time 0.88 seconds
Started Jun 21 04:57:24 PM PDT 24
Finished Jun 21 04:57:26 PM PDT 24
Peak memory 206000 kb
Host smart-68fe243d-082a-4942-b313-95a04b571c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25640
34004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.2564034004
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.1638853928
Short name T1627
Test name
Test status
Simulation time 23299980076 ps
CPU time 22.46 seconds
Started Jun 21 04:57:28 PM PDT 24
Finished Jun 21 04:57:53 PM PDT 24
Peak memory 205992 kb
Host smart-8ff183cb-3125-44b4-853e-155cf2f40f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16388
53928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.1638853928
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.2247426786
Short name T1922
Test name
Test status
Simulation time 3330232797 ps
CPU time 3.8 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:57:31 PM PDT 24
Peak memory 206028 kb
Host smart-63a6edc4-7ad8-4949-85a5-dd9d7f78f8a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22474
26786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.2247426786
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.3969923789
Short name T703
Test name
Test status
Simulation time 9004129921 ps
CPU time 85.1 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:58:53 PM PDT 24
Peak memory 206292 kb
Host smart-0c15ca80-d9ba-46f9-8332-9036d324adbd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3969923789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.3969923789
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.1927038981
Short name T616
Test name
Test status
Simulation time 263526791 ps
CPU time 0.94 seconds
Started Jun 21 04:57:29 PM PDT 24
Finished Jun 21 04:57:32 PM PDT 24
Peak memory 205600 kb
Host smart-c5f34a35-50e9-4995-856b-91899a69b4c9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1927038981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.1927038981
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3568100490
Short name T2462
Test name
Test status
Simulation time 190763847 ps
CPU time 0.88 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:57:29 PM PDT 24
Peak memory 205992 kb
Host smart-d1425f6a-5e7a-4d4d-923b-bc0eba7ca5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35681
00490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3568100490
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.1653727369
Short name T458
Test name
Test status
Simulation time 8536038671 ps
CPU time 82.89 seconds
Started Jun 21 04:57:28 PM PDT 24
Finished Jun 21 04:58:54 PM PDT 24
Peak memory 206228 kb
Host smart-5131ee5b-0748-45d1-b4d4-24c77cefd1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16537
27369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.1653727369
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.2976083475
Short name T1889
Test name
Test status
Simulation time 8916119072 ps
CPU time 64.15 seconds
Started Jun 21 04:57:32 PM PDT 24
Finished Jun 21 04:58:37 PM PDT 24
Peak memory 206276 kb
Host smart-7906bde9-839b-40da-9dee-f56e5cea6422
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2976083475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.2976083475
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1719124805
Short name T1912
Test name
Test status
Simulation time 208388078 ps
CPU time 0.83 seconds
Started Jun 21 04:57:28 PM PDT 24
Finished Jun 21 04:57:31 PM PDT 24
Peak memory 206028 kb
Host smart-a86779e5-f392-4165-b18c-5eb5cb808c4f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1719124805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1719124805
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1623697060
Short name T1984
Test name
Test status
Simulation time 157758838 ps
CPU time 0.76 seconds
Started Jun 21 04:57:24 PM PDT 24
Finished Jun 21 04:57:26 PM PDT 24
Peak memory 205932 kb
Host smart-e95a58c7-7f86-44d8-b4c1-704756c4cdf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16236
97060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1623697060
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3233793235
Short name T2180
Test name
Test status
Simulation time 195772497 ps
CPU time 0.86 seconds
Started Jun 21 04:57:24 PM PDT 24
Finished Jun 21 04:57:25 PM PDT 24
Peak memory 205968 kb
Host smart-df6d2b1f-41b7-4054-badd-7671e87920c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32337
93235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3233793235
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.551073368
Short name T1305
Test name
Test status
Simulation time 148163253 ps
CPU time 0.75 seconds
Started Jun 21 04:57:27 PM PDT 24
Finished Jun 21 04:57:29 PM PDT 24
Peak memory 205956 kb
Host smart-eded23be-a456-412c-9927-0da7cc11a30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55107
3368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.551073368
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3072478496
Short name T501
Test name
Test status
Simulation time 194032715 ps
CPU time 0.85 seconds
Started Jun 21 04:57:24 PM PDT 24
Finished Jun 21 04:57:26 PM PDT 24
Peak memory 206004 kb
Host smart-7a0f2f5d-b137-4c93-9a7a-ae95cf7bfc8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30724
78496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3072478496
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3293417371
Short name T704
Test name
Test status
Simulation time 220538161 ps
CPU time 0.86 seconds
Started Jun 21 04:57:25 PM PDT 24
Finished Jun 21 04:57:28 PM PDT 24
Peak memory 205956 kb
Host smart-35479307-7248-4bc1-b42a-f72e4fe4b07c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32934
17371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3293417371
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.473042026
Short name T687
Test name
Test status
Simulation time 147010544 ps
CPU time 0.77 seconds
Started Jun 21 04:57:27 PM PDT 24
Finished Jun 21 04:57:30 PM PDT 24
Peak memory 205984 kb
Host smart-aa254c44-042e-417b-a4e5-52633bcdb95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47304
2026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.473042026
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.3139927816
Short name T1158
Test name
Test status
Simulation time 230839156 ps
CPU time 1 seconds
Started Jun 21 04:57:27 PM PDT 24
Finished Jun 21 04:57:30 PM PDT 24
Peak memory 206008 kb
Host smart-bdaa2cbe-ae06-457b-97f4-0261ba0836bd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3139927816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3139927816
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.418343847
Short name T1743
Test name
Test status
Simulation time 157841493 ps
CPU time 0.75 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:57:28 PM PDT 24
Peak memory 205988 kb
Host smart-28fe0663-514f-4e23-b35b-6ee64e21879b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41834
3847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.418343847
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1137814763
Short name T807
Test name
Test status
Simulation time 35038854 ps
CPU time 0.71 seconds
Started Jun 21 04:57:28 PM PDT 24
Finished Jun 21 04:57:31 PM PDT 24
Peak memory 205940 kb
Host smart-06bc1043-9173-4066-9747-fe0d0e80e184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11378
14763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1137814763
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.521677783
Short name T2188
Test name
Test status
Simulation time 18789062584 ps
CPU time 47.32 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:58:15 PM PDT 24
Peak memory 206320 kb
Host smart-55000a45-76c8-4145-91bd-8c9f88075cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52167
7783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.521677783
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.343964853
Short name T1424
Test name
Test status
Simulation time 178341640 ps
CPU time 0.92 seconds
Started Jun 21 04:57:23 PM PDT 24
Finished Jun 21 04:57:25 PM PDT 24
Peak memory 205976 kb
Host smart-b24b6a94-b52a-4d15-bb5e-246f0624d630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34396
4853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.343964853
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.854650552
Short name T2348
Test name
Test status
Simulation time 217702335 ps
CPU time 0.95 seconds
Started Jun 21 04:57:34 PM PDT 24
Finished Jun 21 04:57:36 PM PDT 24
Peak memory 205956 kb
Host smart-16c4087f-b35f-43df-b7e3-a56351022be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85465
0552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.854650552
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.4135877852
Short name T863
Test name
Test status
Simulation time 230164604 ps
CPU time 0.85 seconds
Started Jun 21 04:57:29 PM PDT 24
Finished Jun 21 04:57:32 PM PDT 24
Peak memory 205644 kb
Host smart-f2ca4101-b197-410a-890f-719731a8be93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41358
77852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.4135877852
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.3346858254
Short name T794
Test name
Test status
Simulation time 168673946 ps
CPU time 0.81 seconds
Started Jun 21 04:57:27 PM PDT 24
Finished Jun 21 04:57:30 PM PDT 24
Peak memory 205972 kb
Host smart-f8bac038-9e5d-49b8-8837-849d9d2bcf44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33468
58254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.3346858254
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2751119914
Short name T1172
Test name
Test status
Simulation time 194502445 ps
CPU time 0.81 seconds
Started Jun 21 04:57:32 PM PDT 24
Finished Jun 21 04:57:34 PM PDT 24
Peak memory 205952 kb
Host smart-9be2e0e4-c3ba-4aec-8bb1-51b5e90e6f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27511
19914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2751119914
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2109930110
Short name T1888
Test name
Test status
Simulation time 141308369 ps
CPU time 0.71 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:57:29 PM PDT 24
Peak memory 205960 kb
Host smart-30b48ed8-64cc-4310-84a9-086dae4d0a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21099
30110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2109930110
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2779849911
Short name T2347
Test name
Test status
Simulation time 145113996 ps
CPU time 0.77 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:57:29 PM PDT 24
Peak memory 205964 kb
Host smart-fb00f9f0-9863-496f-a311-78e31367bf26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27798
49911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2779849911
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1196250117
Short name T872
Test name
Test status
Simulation time 226868465 ps
CPU time 0.96 seconds
Started Jun 21 04:57:29 PM PDT 24
Finished Jun 21 04:57:32 PM PDT 24
Peak memory 205952 kb
Host smart-7a668f82-fd2c-4605-91bb-b7f9972cd3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11962
50117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1196250117
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.3813705455
Short name T411
Test name
Test status
Simulation time 6640232827 ps
CPU time 171.31 seconds
Started Jun 21 04:57:29 PM PDT 24
Finished Jun 21 05:00:23 PM PDT 24
Peak memory 206164 kb
Host smart-9b797821-135f-4486-a3d0-9774db737bb2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3813705455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.3813705455
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1591975448
Short name T2386
Test name
Test status
Simulation time 176640127 ps
CPU time 0.85 seconds
Started Jun 21 04:57:29 PM PDT 24
Finished Jun 21 04:57:32 PM PDT 24
Peak memory 205936 kb
Host smart-97c6c4f6-ae8b-4fe2-a19c-5ab0cbeeffff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15919
75448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1591975448
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.2949262352
Short name T2115
Test name
Test status
Simulation time 157347691 ps
CPU time 0.84 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:57:29 PM PDT 24
Peak memory 205960 kb
Host smart-faef1faf-e9a4-4231-9ca4-25cf33209694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29492
62352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2949262352
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.1531692134
Short name T369
Test name
Test status
Simulation time 6772046041 ps
CPU time 201.66 seconds
Started Jun 21 04:57:28 PM PDT 24
Finished Jun 21 05:00:53 PM PDT 24
Peak memory 206248 kb
Host smart-7dfd4832-4e7d-4d20-a36e-80fc7890cfb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15316
92134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.1531692134
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2533522117
Short name T578
Test name
Test status
Simulation time 4096131335 ps
CPU time 4.75 seconds
Started Jun 21 04:57:27 PM PDT 24
Finished Jun 21 04:57:35 PM PDT 24
Peak memory 206296 kb
Host smart-d0b8376b-4d9c-4fc8-a647-1a7226006c57
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2533522117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.2533522117
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.2521922040
Short name T864
Test name
Test status
Simulation time 13352870217 ps
CPU time 13.94 seconds
Started Jun 21 04:57:29 PM PDT 24
Finished Jun 21 04:57:45 PM PDT 24
Peak memory 206016 kb
Host smart-f7841dd3-e14b-4ac6-8a65-8b6d378127f3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2521922040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.2521922040
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1035998227
Short name T1571
Test name
Test status
Simulation time 23376182634 ps
CPU time 23.83 seconds
Started Jun 21 04:57:26 PM PDT 24
Finished Jun 21 04:57:51 PM PDT 24
Peak memory 206080 kb
Host smart-41c88082-5102-4987-8883-ccd40cd33dd7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1035998227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.1035998227
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.631904471
Short name T1018
Test name
Test status
Simulation time 162002746 ps
CPU time 0.78 seconds
Started Jun 21 04:57:29 PM PDT 24
Finished Jun 21 04:57:32 PM PDT 24
Peak memory 205968 kb
Host smart-b8b3374f-ae8f-4bcf-b1ac-341806be9f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63190
4471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.631904471
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.3263342107
Short name T1307
Test name
Test status
Simulation time 154262365 ps
CPU time 0.75 seconds
Started Jun 21 04:57:34 PM PDT 24
Finished Jun 21 04:57:36 PM PDT 24
Peak memory 205968 kb
Host smart-21ace890-391c-4375-84dc-92c75552c923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32633
42107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.3263342107
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.202158372
Short name T1687
Test name
Test status
Simulation time 1072629212 ps
CPU time 2.69 seconds
Started Jun 21 04:57:33 PM PDT 24
Finished Jun 21 04:57:37 PM PDT 24
Peak memory 206248 kb
Host smart-84b94f0f-9e9f-4d43-9d8c-ae63e5964670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20215
8372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.202158372
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.4052733516
Short name T506
Test name
Test status
Simulation time 11068057575 ps
CPU time 18.89 seconds
Started Jun 21 04:57:46 PM PDT 24
Finished Jun 21 04:58:09 PM PDT 24
Peak memory 206344 kb
Host smart-2d02f7ce-decb-4f6c-a4d9-a668b266c236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40527
33516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.4052733516
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.3808439653
Short name T2006
Test name
Test status
Simulation time 456009278 ps
CPU time 1.48 seconds
Started Jun 21 04:57:32 PM PDT 24
Finished Jun 21 04:57:35 PM PDT 24
Peak memory 206020 kb
Host smart-a3081429-3e2f-4e09-a04c-1185cef3391e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38084
39653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.3808439653
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_enable.838538999
Short name T1895
Test name
Test status
Simulation time 34746180 ps
CPU time 0.66 seconds
Started Jun 21 04:57:35 PM PDT 24
Finished Jun 21 04:57:37 PM PDT 24
Peak memory 205916 kb
Host smart-caf77a9e-9d62-4f0e-a20e-8e7e3f74f97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83853
8999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.838538999
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.2391144242
Short name T459
Test name
Test status
Simulation time 1021321322 ps
CPU time 2.12 seconds
Started Jun 21 04:57:34 PM PDT 24
Finished Jun 21 04:57:38 PM PDT 24
Peak memory 206196 kb
Host smart-847d83c8-ab85-4ea1-b235-8dbbc900fee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23911
44242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.2391144242
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1424040554
Short name T1338
Test name
Test status
Simulation time 197188685 ps
CPU time 1.25 seconds
Started Jun 21 04:57:35 PM PDT 24
Finished Jun 21 04:57:38 PM PDT 24
Peak memory 206204 kb
Host smart-15024b3e-4c79-437e-996f-ba910600df8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14240
40554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1424040554
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.2517900067
Short name T2232
Test name
Test status
Simulation time 235073554 ps
CPU time 0.88 seconds
Started Jun 21 04:57:34 PM PDT 24
Finished Jun 21 04:57:37 PM PDT 24
Peak memory 206020 kb
Host smart-b66bc5eb-386a-47c1-b1b8-b4d882ba95e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25179
00067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.2517900067
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1853405680
Short name T846
Test name
Test status
Simulation time 193110499 ps
CPU time 0.81 seconds
Started Jun 21 04:57:34 PM PDT 24
Finished Jun 21 04:57:37 PM PDT 24
Peak memory 205916 kb
Host smart-f61cab17-12b2-4cfb-83f9-e95c6a1098d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18534
05680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1853405680
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.133485037
Short name T1651
Test name
Test status
Simulation time 234954318 ps
CPU time 0.9 seconds
Started Jun 21 04:57:47 PM PDT 24
Finished Jun 21 04:57:51 PM PDT 24
Peak memory 206024 kb
Host smart-ac44e6c0-158b-40f7-b4f9-67b0e3b67399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13348
5037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.133485037
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3187792921
Short name T55
Test name
Test status
Simulation time 241049490 ps
CPU time 0.92 seconds
Started Jun 21 04:57:46 PM PDT 24
Finished Jun 21 04:57:51 PM PDT 24
Peak memory 206020 kb
Host smart-3db994c6-df0b-410b-8142-040b0fcb7e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31877
92921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3187792921
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3941673942
Short name T1662
Test name
Test status
Simulation time 23303268752 ps
CPU time 23.92 seconds
Started Jun 21 04:57:34 PM PDT 24
Finished Jun 21 04:58:00 PM PDT 24
Peak memory 206208 kb
Host smart-7db6eda9-8095-41d0-a03f-ac82917581f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39416
73942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3941673942
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.839300084
Short name T1732
Test name
Test status
Simulation time 3282258730 ps
CPU time 3.6 seconds
Started Jun 21 04:57:35 PM PDT 24
Finished Jun 21 04:57:40 PM PDT 24
Peak memory 206068 kb
Host smart-02b489da-6aa2-4e58-8c01-11ff0d066c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83930
0084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.839300084
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.3663718424
Short name T1830
Test name
Test status
Simulation time 6887189600 ps
CPU time 183.98 seconds
Started Jun 21 04:57:44 PM PDT 24
Finished Jun 21 05:00:50 PM PDT 24
Peak memory 206272 kb
Host smart-7be1e20d-5f4d-4578-ba10-810f686e11cd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3663718424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.3663718424
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.4110779127
Short name T1399
Test name
Test status
Simulation time 234604961 ps
CPU time 0.88 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 04:57:53 PM PDT 24
Peak memory 205988 kb
Host smart-3aaf2cc6-46cf-4efe-837a-f03689fad06f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4110779127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.4110779127
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1334368707
Short name T494
Test name
Test status
Simulation time 222967557 ps
CPU time 0.85 seconds
Started Jun 21 04:57:44 PM PDT 24
Finished Jun 21 04:57:47 PM PDT 24
Peak memory 206052 kb
Host smart-a118a884-197a-4bf7-ba75-9607f3cedfac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13343
68707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1334368707
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.3531392154
Short name T1723
Test name
Test status
Simulation time 12547180015 ps
CPU time 352.12 seconds
Started Jun 21 04:57:34 PM PDT 24
Finished Jun 21 05:03:28 PM PDT 24
Peak memory 206248 kb
Host smart-02588848-ca9b-46aa-87e2-4abfa764dbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35313
92154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.3531392154
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.2974690551
Short name T322
Test name
Test status
Simulation time 9517218648 ps
CPU time 65.08 seconds
Started Jun 21 04:57:46 PM PDT 24
Finished Jun 21 04:58:54 PM PDT 24
Peak memory 206304 kb
Host smart-f8f75217-8265-4edb-ab8b-4d37a3408abb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2974690551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.2974690551
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.526590736
Short name T339
Test name
Test status
Simulation time 151278151 ps
CPU time 0.73 seconds
Started Jun 21 04:57:33 PM PDT 24
Finished Jun 21 04:57:35 PM PDT 24
Peak memory 205992 kb
Host smart-37f49a98-fa83-4d83-a71c-94f20765a889
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=526590736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.526590736
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3788914876
Short name T2036
Test name
Test status
Simulation time 165334242 ps
CPU time 0.81 seconds
Started Jun 21 04:57:34 PM PDT 24
Finished Jun 21 04:57:36 PM PDT 24
Peak memory 205960 kb
Host smart-372807ae-7c76-4752-980d-4428bc5fd009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37889
14876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3788914876
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.4272596689
Short name T1193
Test name
Test status
Simulation time 184313408 ps
CPU time 0.86 seconds
Started Jun 21 04:57:44 PM PDT 24
Finished Jun 21 04:57:47 PM PDT 24
Peak memory 206024 kb
Host smart-c5316a30-d4f7-4bbb-92f1-12f4eb5f1860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42725
96689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.4272596689
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2020933666
Short name T1179
Test name
Test status
Simulation time 208890203 ps
CPU time 0.97 seconds
Started Jun 21 04:57:34 PM PDT 24
Finished Jun 21 04:57:37 PM PDT 24
Peak memory 206024 kb
Host smart-14ec25e1-22f2-431e-8cbd-b66eaa5f4e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20209
33666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2020933666
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2519617438
Short name T1753
Test name
Test status
Simulation time 182518268 ps
CPU time 0.85 seconds
Started Jun 21 04:57:34 PM PDT 24
Finished Jun 21 04:57:36 PM PDT 24
Peak memory 206036 kb
Host smart-a5304fd8-668f-4e08-8a80-ddf707605959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25196
17438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2519617438
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.2232033208
Short name T2375
Test name
Test status
Simulation time 203158573 ps
CPU time 0.88 seconds
Started Jun 21 04:57:34 PM PDT 24
Finished Jun 21 04:57:37 PM PDT 24
Peak memory 206024 kb
Host smart-7030cce1-ce71-4fd9-b0ce-bf8803065f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22320
33208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.2232033208
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.3045493381
Short name T153
Test name
Test status
Simulation time 237552254 ps
CPU time 0.92 seconds
Started Jun 21 04:57:41 PM PDT 24
Finished Jun 21 04:57:43 PM PDT 24
Peak memory 205944 kb
Host smart-47cd5da9-3fbe-41bf-9813-7e5c097f0498
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3045493381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.3045493381
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.13911495
Short name T376
Test name
Test status
Simulation time 158926226 ps
CPU time 0.8 seconds
Started Jun 21 04:57:35 PM PDT 24
Finished Jun 21 04:57:37 PM PDT 24
Peak memory 206036 kb
Host smart-67b27c2f-0fd3-47a4-8e20-583c56280a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13911
495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.13911495
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1611798360
Short name T1480
Test name
Test status
Simulation time 41609537 ps
CPU time 0.63 seconds
Started Jun 21 04:57:46 PM PDT 24
Finished Jun 21 04:57:49 PM PDT 24
Peak memory 206036 kb
Host smart-dcf278da-e213-4511-b125-5006b89605f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16117
98360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1611798360
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.4114077279
Short name T1189
Test name
Test status
Simulation time 22428382946 ps
CPU time 50.47 seconds
Started Jun 21 04:57:34 PM PDT 24
Finished Jun 21 04:58:27 PM PDT 24
Peak memory 206264 kb
Host smart-f3a71c3e-55a1-467a-9d6f-295d0f2fbff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41140
77279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.4114077279
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.818975173
Short name T19
Test name
Test status
Simulation time 203841925 ps
CPU time 0.86 seconds
Started Jun 21 04:57:44 PM PDT 24
Finished Jun 21 04:57:46 PM PDT 24
Peak memory 206024 kb
Host smart-a8e811c8-0984-4097-9444-34d7b8cb7e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81897
5173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.818975173
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1397826376
Short name T2130
Test name
Test status
Simulation time 186975637 ps
CPU time 0.79 seconds
Started Jun 21 04:57:44 PM PDT 24
Finished Jun 21 04:57:46 PM PDT 24
Peak memory 206020 kb
Host smart-8476dc98-f2c7-41ee-9949-bcd2babaf77a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13978
26376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1397826376
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.283525174
Short name T1260
Test name
Test status
Simulation time 208447632 ps
CPU time 0.87 seconds
Started Jun 21 04:57:33 PM PDT 24
Finished Jun 21 04:57:35 PM PDT 24
Peak memory 205936 kb
Host smart-79e07a74-d2a1-415d-b0ab-064d87ef27a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28352
5174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.283525174
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.1130743611
Short name T421
Test name
Test status
Simulation time 173310770 ps
CPU time 0.81 seconds
Started Jun 21 04:57:45 PM PDT 24
Finished Jun 21 04:57:48 PM PDT 24
Peak memory 206044 kb
Host smart-cd782aa8-3cfd-469a-9428-15f1dc352bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11307
43611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.1130743611
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.280882852
Short name T809
Test name
Test status
Simulation time 142157453 ps
CPU time 0.71 seconds
Started Jun 21 04:57:46 PM PDT 24
Finished Jun 21 04:57:49 PM PDT 24
Peak memory 206024 kb
Host smart-43d1cacf-5ca2-427a-8c06-ef70ac75de18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28088
2852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.280882852
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3501464026
Short name T2414
Test name
Test status
Simulation time 162678054 ps
CPU time 0.8 seconds
Started Jun 21 04:57:33 PM PDT 24
Finished Jun 21 04:57:35 PM PDT 24
Peak memory 205968 kb
Host smart-2296f87c-8fe1-4dcf-9b12-2f538d52ec19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35014
64026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3501464026
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1288007172
Short name T346
Test name
Test status
Simulation time 148978531 ps
CPU time 0.77 seconds
Started Jun 21 04:57:45 PM PDT 24
Finished Jun 21 04:57:48 PM PDT 24
Peak memory 206024 kb
Host smart-1a25bf01-fd2e-40a5-84de-fbb4ad34826c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12880
07172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1288007172
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1875979407
Short name T2140
Test name
Test status
Simulation time 184836082 ps
CPU time 0.89 seconds
Started Jun 21 04:57:28 PM PDT 24
Finished Jun 21 04:57:31 PM PDT 24
Peak memory 205936 kb
Host smart-5c8f97b2-ecc8-46c0-8bc4-2af5ea5447d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18759
79407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1875979407
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.714159930
Short name T628
Test name
Test status
Simulation time 8925990135 ps
CPU time 252.09 seconds
Started Jun 21 04:57:47 PM PDT 24
Finished Jun 21 05:02:02 PM PDT 24
Peak memory 206280 kb
Host smart-6f4cd26a-dfc3-4b04-b43b-80a1862c1857
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=714159930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.714159930
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3971113572
Short name T1322
Test name
Test status
Simulation time 205295218 ps
CPU time 0.85 seconds
Started Jun 21 04:57:34 PM PDT 24
Finished Jun 21 04:57:37 PM PDT 24
Peak memory 206032 kb
Host smart-b748cff8-0779-4442-8b6a-fa667ec445ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39711
13572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3971113572
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.3233634903
Short name T2399
Test name
Test status
Simulation time 191451589 ps
CPU time 0.82 seconds
Started Jun 21 04:57:45 PM PDT 24
Finished Jun 21 04:57:49 PM PDT 24
Peak memory 206020 kb
Host smart-8a093dbe-0da3-4799-8d31-19bced3dcdce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32336
34903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.3233634903
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3831789137
Short name T2301
Test name
Test status
Simulation time 5848578828 ps
CPU time 42.05 seconds
Started Jun 21 04:57:32 PM PDT 24
Finished Jun 21 04:58:15 PM PDT 24
Peak memory 206316 kb
Host smart-7732c5f1-4581-4dd6-a06c-170799cf1f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38317
89137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3831789137
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3595301020
Short name T10
Test name
Test status
Simulation time 3711300510 ps
CPU time 4.11 seconds
Started Jun 21 04:57:42 PM PDT 24
Finished Jun 21 04:57:48 PM PDT 24
Peak memory 206196 kb
Host smart-75784c75-f087-46c7-bf53-18d42612625a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3595301020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.3595301020
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.565352543
Short name T449
Test name
Test status
Simulation time 13361233067 ps
CPU time 12.38 seconds
Started Jun 21 04:57:43 PM PDT 24
Finished Jun 21 04:57:57 PM PDT 24
Peak memory 206084 kb
Host smart-4a160704-e312-4bfb-9354-918121da766c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=565352543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.565352543
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.4059015685
Short name T866
Test name
Test status
Simulation time 177131362 ps
CPU time 0.81 seconds
Started Jun 21 04:57:41 PM PDT 24
Finished Jun 21 04:57:43 PM PDT 24
Peak memory 206024 kb
Host smart-bc5a7c9b-9931-4130-b634-bbd8e8ba167d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40590
15685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.4059015685
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.657682501
Short name T764
Test name
Test status
Simulation time 146342133 ps
CPU time 0.78 seconds
Started Jun 21 04:57:43 PM PDT 24
Finished Jun 21 04:57:46 PM PDT 24
Peak memory 206076 kb
Host smart-d1bf2aa3-c298-43a8-b6f1-3f11f1e5486f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65768
2501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.657682501
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.1062981388
Short name T906
Test name
Test status
Simulation time 497992998 ps
CPU time 1.49 seconds
Started Jun 21 04:57:41 PM PDT 24
Finished Jun 21 04:57:43 PM PDT 24
Peak memory 206144 kb
Host smart-a3d0dfc6-d57d-4736-a17c-2b3b195d9a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10629
81388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.1062981388
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1362225934
Short name T1668
Test name
Test status
Simulation time 1311838113 ps
CPU time 2.95 seconds
Started Jun 21 04:57:41 PM PDT 24
Finished Jun 21 04:57:46 PM PDT 24
Peak memory 206188 kb
Host smart-d18481a8-93ca-496d-9630-960c3a7ad455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13622
25934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1362225934
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.1328996858
Short name T1944
Test name
Test status
Simulation time 22939300632 ps
CPU time 47.75 seconds
Started Jun 21 04:57:43 PM PDT 24
Finished Jun 21 04:58:33 PM PDT 24
Peak memory 206368 kb
Host smart-b6df62ab-5792-4fd1-8032-6e684c66303e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13289
96858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.1328996858
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.3187213076
Short name T695
Test name
Test status
Simulation time 374844485 ps
CPU time 1.15 seconds
Started Jun 21 04:57:44 PM PDT 24
Finished Jun 21 04:57:47 PM PDT 24
Peak memory 205928 kb
Host smart-c1b5e56a-463b-4151-8e26-1226c23ac8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31872
13076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.3187213076
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.3621260023
Short name T734
Test name
Test status
Simulation time 152250736 ps
CPU time 0.77 seconds
Started Jun 21 04:57:46 PM PDT 24
Finished Jun 21 04:57:49 PM PDT 24
Peak memory 205956 kb
Host smart-4615abde-5313-4b30-917f-16e0aa995cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36212
60023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.3621260023
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2658795118
Short name T1066
Test name
Test status
Simulation time 62346930 ps
CPU time 0.67 seconds
Started Jun 21 04:57:45 PM PDT 24
Finished Jun 21 04:57:48 PM PDT 24
Peak memory 206016 kb
Host smart-f528097b-1b64-4d11-950a-ea6bbcc9b097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26587
95118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2658795118
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.4205401465
Short name T679
Test name
Test status
Simulation time 720252566 ps
CPU time 1.87 seconds
Started Jun 21 04:57:43 PM PDT 24
Finished Jun 21 04:57:47 PM PDT 24
Peak memory 206256 kb
Host smart-5f3cdaa3-6033-454f-8472-f5aa705dcfe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42054
01465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.4205401465
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.4167345169
Short name T189
Test name
Test status
Simulation time 392917253 ps
CPU time 2.42 seconds
Started Jun 21 04:57:41 PM PDT 24
Finished Jun 21 04:57:45 PM PDT 24
Peak memory 206224 kb
Host smart-fedff476-89ca-4999-b35e-853d13ce1d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41673
45169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.4167345169
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.2341361146
Short name T1459
Test name
Test status
Simulation time 268895879 ps
CPU time 0.88 seconds
Started Jun 21 04:57:47 PM PDT 24
Finished Jun 21 04:57:51 PM PDT 24
Peak memory 205964 kb
Host smart-f80f9fcd-9386-4e8a-9f96-5b9d37f77abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23413
61146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2341361146
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.557555990
Short name T2327
Test name
Test status
Simulation time 142389890 ps
CPU time 0.75 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 04:57:53 PM PDT 24
Peak memory 205828 kb
Host smart-d6d997fd-25e6-4f3e-8686-4664b4b42079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55755
5990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.557555990
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3776403924
Short name T457
Test name
Test status
Simulation time 237453333 ps
CPU time 0.89 seconds
Started Jun 21 04:57:45 PM PDT 24
Finished Jun 21 04:57:48 PM PDT 24
Peak memory 206028 kb
Host smart-e36dd9dd-1336-4c3c-b3e3-7945ce19d838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37764
03924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3776403924
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1910778008
Short name T1881
Test name
Test status
Simulation time 186753910 ps
CPU time 0.86 seconds
Started Jun 21 04:57:42 PM PDT 24
Finished Jun 21 04:57:44 PM PDT 24
Peak memory 206016 kb
Host smart-15b9ca4c-f990-4db7-946a-c75c6ba7f732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19107
78008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1910778008
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.1093057132
Short name T1236
Test name
Test status
Simulation time 23339114155 ps
CPU time 22.69 seconds
Started Jun 21 04:57:40 PM PDT 24
Finished Jun 21 04:58:04 PM PDT 24
Peak memory 206020 kb
Host smart-b6e567ba-7dcc-4cc1-847a-52da0b4ad5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10930
57132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.1093057132
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3160563064
Short name T1248
Test name
Test status
Simulation time 3287432815 ps
CPU time 3.69 seconds
Started Jun 21 04:57:45 PM PDT 24
Finished Jun 21 04:57:51 PM PDT 24
Peak memory 206084 kb
Host smart-0fcf6a96-7b8a-48d7-ba42-c2dbab8d6c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31605
63064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3160563064
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.2502956594
Short name T1908
Test name
Test status
Simulation time 4481129236 ps
CPU time 121.21 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 04:59:53 PM PDT 24
Peak memory 206272 kb
Host smart-506ea281-1635-4662-9f4c-6a767a357ed4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2502956594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.2502956594
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.3826267293
Short name T726
Test name
Test status
Simulation time 230573340 ps
CPU time 0.87 seconds
Started Jun 21 04:57:43 PM PDT 24
Finished Jun 21 04:57:46 PM PDT 24
Peak memory 206048 kb
Host smart-597cf4e2-2e9d-4e42-91da-d405e2260731
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3826267293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.3826267293
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1638408579
Short name T2309
Test name
Test status
Simulation time 191702115 ps
CPU time 0.88 seconds
Started Jun 21 04:57:43 PM PDT 24
Finished Jun 21 04:57:45 PM PDT 24
Peak memory 206036 kb
Host smart-655bee6f-d99d-46fe-8e61-3b9da0fb81b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16384
08579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1638408579
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.409264355
Short name T1127
Test name
Test status
Simulation time 8207782934 ps
CPU time 233.31 seconds
Started Jun 21 04:57:44 PM PDT 24
Finished Jun 21 05:01:39 PM PDT 24
Peak memory 206148 kb
Host smart-01b7e0f2-e3a3-4e26-b508-fbcba5e93038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40926
4355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.409264355
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.2467917341
Short name T2453
Test name
Test status
Simulation time 12346834983 ps
CPU time 114.01 seconds
Started Jun 21 04:57:43 PM PDT 24
Finished Jun 21 04:59:39 PM PDT 24
Peak memory 206268 kb
Host smart-03025d98-01e5-4a6f-b209-53fa7c3f1b1a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2467917341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.2467917341
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.2724884844
Short name T897
Test name
Test status
Simulation time 157207840 ps
CPU time 0.78 seconds
Started Jun 21 04:57:42 PM PDT 24
Finished Jun 21 04:57:44 PM PDT 24
Peak memory 205976 kb
Host smart-099176d8-0fb1-45d8-9655-ea714f0d1fb6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2724884844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.2724884844
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3519075808
Short name T1581
Test name
Test status
Simulation time 168193876 ps
CPU time 0.82 seconds
Started Jun 21 04:57:44 PM PDT 24
Finished Jun 21 04:57:48 PM PDT 24
Peak memory 206032 kb
Host smart-089be48a-5236-4585-8815-e091a78a29c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35190
75808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3519075808
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.892391572
Short name T119
Test name
Test status
Simulation time 205193264 ps
CPU time 0.85 seconds
Started Jun 21 04:57:46 PM PDT 24
Finished Jun 21 04:57:49 PM PDT 24
Peak memory 205956 kb
Host smart-42235d61-3ec3-4a61-95c9-9dbd144b1753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89239
1572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.892391572
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.110328618
Short name T98
Test name
Test status
Simulation time 165200203 ps
CPU time 0.78 seconds
Started Jun 21 04:57:41 PM PDT 24
Finished Jun 21 04:57:42 PM PDT 24
Peak memory 206004 kb
Host smart-9ed741e4-0d69-4391-a027-1fb6231dff33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11032
8618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.110328618
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.4220389272
Short name T1331
Test name
Test status
Simulation time 151346616 ps
CPU time 0.78 seconds
Started Jun 21 04:57:42 PM PDT 24
Finished Jun 21 04:57:45 PM PDT 24
Peak memory 206020 kb
Host smart-e32bffc4-8f57-4afa-9abb-93b8cdb9cb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42203
89272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.4220389272
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.458497153
Short name T344
Test name
Test status
Simulation time 206833338 ps
CPU time 0.8 seconds
Started Jun 21 04:57:46 PM PDT 24
Finished Jun 21 04:57:50 PM PDT 24
Peak memory 206024 kb
Host smart-ae395ab3-9f2c-4ea6-9589-8178d393438e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45849
7153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.458497153
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.678175230
Short name T169
Test name
Test status
Simulation time 154029257 ps
CPU time 0.74 seconds
Started Jun 21 04:57:41 PM PDT 24
Finished Jun 21 04:57:43 PM PDT 24
Peak memory 205972 kb
Host smart-9c0aa2a3-b1e2-420a-8f3e-0a7d9d44785c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67817
5230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.678175230
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1885921903
Short name T1599
Test name
Test status
Simulation time 277803730 ps
CPU time 1.03 seconds
Started Jun 21 04:57:44 PM PDT 24
Finished Jun 21 04:57:47 PM PDT 24
Peak memory 205944 kb
Host smart-6f1130f3-7b89-489d-9782-5c7f2907b71f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1885921903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1885921903
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.2622928049
Short name T451
Test name
Test status
Simulation time 147584429 ps
CPU time 0.74 seconds
Started Jun 21 04:57:45 PM PDT 24
Finished Jun 21 04:57:49 PM PDT 24
Peak memory 206028 kb
Host smart-9aee0c9b-ad1e-4e8c-b6b0-6d2db4fddf3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26229
28049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.2622928049
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2868484455
Short name T1955
Test name
Test status
Simulation time 35629050 ps
CPU time 0.71 seconds
Started Jun 21 04:57:46 PM PDT 24
Finished Jun 21 04:57:50 PM PDT 24
Peak memory 205968 kb
Host smart-f3ec467c-9652-4203-884c-170d6c98dc98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28684
84455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2868484455
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2360660578
Short name T830
Test name
Test status
Simulation time 7259276908 ps
CPU time 14.94 seconds
Started Jun 21 04:57:40 PM PDT 24
Finished Jun 21 04:57:56 PM PDT 24
Peak memory 206336 kb
Host smart-4fd7931e-ac0f-4c04-a14a-8692b5d0b6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23606
60578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2360660578
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1388527030
Short name T693
Test name
Test status
Simulation time 206362425 ps
CPU time 0.83 seconds
Started Jun 21 04:57:41 PM PDT 24
Finished Jun 21 04:57:43 PM PDT 24
Peak memory 205964 kb
Host smart-656789d7-d971-40a1-9a47-bd01ec7dbc43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13885
27030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1388527030
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3407147322
Short name T2405
Test name
Test status
Simulation time 205741368 ps
CPU time 0.83 seconds
Started Jun 21 04:57:40 PM PDT 24
Finished Jun 21 04:57:42 PM PDT 24
Peak memory 205960 kb
Host smart-c7be6f57-5939-455f-8d9e-25d3823c62d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34071
47322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3407147322
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.3775807210
Short name T2190
Test name
Test status
Simulation time 183475195 ps
CPU time 0.79 seconds
Started Jun 21 04:57:45 PM PDT 24
Finished Jun 21 04:57:48 PM PDT 24
Peak memory 206028 kb
Host smart-6d61b6e8-4ef9-485c-8ed2-ea31d81c7373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37758
07210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.3775807210
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.835590314
Short name T2484
Test name
Test status
Simulation time 155098656 ps
CPU time 0.85 seconds
Started Jun 21 04:57:44 PM PDT 24
Finished Jun 21 04:57:46 PM PDT 24
Peak memory 205940 kb
Host smart-8afc3dd0-5af3-42f3-98c2-86b6fe5332c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83559
0314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.835590314
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.727717676
Short name T985
Test name
Test status
Simulation time 182801537 ps
CPU time 0.83 seconds
Started Jun 21 04:57:42 PM PDT 24
Finished Jun 21 04:57:44 PM PDT 24
Peak memory 206028 kb
Host smart-3bd80c61-5b32-418b-aa0d-909cbc5a481e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72771
7676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.727717676
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.563629668
Short name T2331
Test name
Test status
Simulation time 168545979 ps
CPU time 0.77 seconds
Started Jun 21 04:57:47 PM PDT 24
Finished Jun 21 04:57:52 PM PDT 24
Peak memory 205964 kb
Host smart-6f50fddc-b75a-4713-b2d9-668d2e2e1ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56362
9668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.563629668
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3491185028
Short name T2212
Test name
Test status
Simulation time 177271397 ps
CPU time 0.79 seconds
Started Jun 21 04:57:46 PM PDT 24
Finished Jun 21 04:57:50 PM PDT 24
Peak memory 206028 kb
Host smart-aa86af14-edaa-41d0-aa8f-519cdbb27ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34911
85028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3491185028
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.2502415520
Short name T2488
Test name
Test status
Simulation time 225617248 ps
CPU time 0.95 seconds
Started Jun 21 04:57:45 PM PDT 24
Finished Jun 21 04:57:49 PM PDT 24
Peak memory 206028 kb
Host smart-1b24b7f7-6e42-43fb-9c17-bf71290ef23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25024
15520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2502415520
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.4006003099
Short name T1985
Test name
Test status
Simulation time 12716546861 ps
CPU time 91.02 seconds
Started Jun 21 04:57:42 PM PDT 24
Finished Jun 21 04:59:15 PM PDT 24
Peak memory 206168 kb
Host smart-e90489f0-5d7d-42c4-a506-e92fd4935da6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4006003099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.4006003099
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3815403302
Short name T1378
Test name
Test status
Simulation time 171805252 ps
CPU time 0.8 seconds
Started Jun 21 04:57:47 PM PDT 24
Finished Jun 21 04:57:51 PM PDT 24
Peak memory 206032 kb
Host smart-1a954f41-d9d9-4a1c-a300-5e1b92d3fb12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38154
03302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3815403302
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.2626199154
Short name T1826
Test name
Test status
Simulation time 206760067 ps
CPU time 0.84 seconds
Started Jun 21 04:57:43 PM PDT 24
Finished Jun 21 04:57:46 PM PDT 24
Peak memory 206020 kb
Host smart-e9c955b7-607b-45fe-a747-9e033839df0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26261
99154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2626199154
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.4259838185
Short name T1795
Test name
Test status
Simulation time 2836893619 ps
CPU time 76.75 seconds
Started Jun 21 04:57:47 PM PDT 24
Finished Jun 21 04:59:06 PM PDT 24
Peak memory 206248 kb
Host smart-59fedc78-fe38-4b5c-ae74-b481ff18dc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42598
38185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.4259838185
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.2473182933
Short name T1669
Test name
Test status
Simulation time 4453906046 ps
CPU time 5.01 seconds
Started Jun 21 04:57:44 PM PDT 24
Finished Jun 21 04:57:51 PM PDT 24
Peak memory 206008 kb
Host smart-68751f61-3b0f-476a-8703-58e3bef22165
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2473182933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.2473182933
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.3548123446
Short name T1514
Test name
Test status
Simulation time 13388056468 ps
CPU time 15.5 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 04:58:08 PM PDT 24
Peak memory 205932 kb
Host smart-3643a5b5-a7e2-4818-b7a4-3c669f87eaa3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3548123446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.3548123446
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.3347490173
Short name T1589
Test name
Test status
Simulation time 23406740949 ps
CPU time 21.1 seconds
Started Jun 21 04:57:47 PM PDT 24
Finished Jun 21 04:58:11 PM PDT 24
Peak memory 206264 kb
Host smart-75b01009-9f35-43bc-801e-73c9494dadce
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3347490173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.3347490173
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3551894259
Short name T646
Test name
Test status
Simulation time 173289923 ps
CPU time 0.82 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 04:57:52 PM PDT 24
Peak memory 206028 kb
Host smart-4d228c65-1177-4d12-848d-9dfe81f37297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35518
94259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3551894259
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.1201907544
Short name T1582
Test name
Test status
Simulation time 232032775 ps
CPU time 0.86 seconds
Started Jun 21 04:57:50 PM PDT 24
Finished Jun 21 04:57:56 PM PDT 24
Peak memory 205964 kb
Host smart-92e7ddba-3e2b-4a40-9a06-4923e448ce4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12019
07544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.1201907544
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.2131267839
Short name T2169
Test name
Test status
Simulation time 203793589 ps
CPU time 0.88 seconds
Started Jun 21 04:57:50 PM PDT 24
Finished Jun 21 04:57:54 PM PDT 24
Peak memory 206024 kb
Host smart-341a7538-954b-48de-bd87-971a90d53243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21312
67839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.2131267839
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.2848860549
Short name T2104
Test name
Test status
Simulation time 322711235 ps
CPU time 1 seconds
Started Jun 21 04:57:50 PM PDT 24
Finished Jun 21 04:57:56 PM PDT 24
Peak memory 206028 kb
Host smart-c35ac3a5-4311-483c-910e-027518851de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28488
60549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.2848860549
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.1453678031
Short name T186
Test name
Test status
Simulation time 12874734668 ps
CPU time 24.88 seconds
Started Jun 21 04:57:51 PM PDT 24
Finished Jun 21 04:58:20 PM PDT 24
Peak memory 206292 kb
Host smart-1f59c17c-d5d9-4456-94ff-3f36f6e65512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14536
78031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.1453678031
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.3230571316
Short name T2481
Test name
Test status
Simulation time 459948381 ps
CPU time 1.32 seconds
Started Jun 21 04:57:46 PM PDT 24
Finished Jun 21 04:57:50 PM PDT 24
Peak memory 206000 kb
Host smart-849a4642-6a00-4c2a-8184-a83494f2da99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32305
71316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.3230571316
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.1750513254
Short name T2150
Test name
Test status
Simulation time 148396644 ps
CPU time 0.78 seconds
Started Jun 21 04:57:50 PM PDT 24
Finished Jun 21 04:57:55 PM PDT 24
Peak memory 206048 kb
Host smart-3ddfe372-52bd-4525-9d59-a95e2854759b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17505
13254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1750513254
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.2270141296
Short name T2023
Test name
Test status
Simulation time 58784101 ps
CPU time 0.66 seconds
Started Jun 21 04:57:49 PM PDT 24
Finished Jun 21 04:57:54 PM PDT 24
Peak memory 206016 kb
Host smart-9aab18c1-cbe9-401d-95fd-c95aa3bdaab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22701
41296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2270141296
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.743942286
Short name T1700
Test name
Test status
Simulation time 822223174 ps
CPU time 1.98 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 04:57:53 PM PDT 24
Peak memory 206164 kb
Host smart-71250070-f6a3-461d-a9f0-15a2271e8752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74394
2286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.743942286
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3247617186
Short name T1560
Test name
Test status
Simulation time 156181505 ps
CPU time 1.33 seconds
Started Jun 21 04:57:51 PM PDT 24
Finished Jun 21 04:57:56 PM PDT 24
Peak memory 206160 kb
Host smart-0a900bd6-df0c-4d87-b57f-5f27c2bc06b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32476
17186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3247617186
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3600024874
Short name T715
Test name
Test status
Simulation time 168408582 ps
CPU time 0.81 seconds
Started Jun 21 04:57:50 PM PDT 24
Finished Jun 21 04:57:55 PM PDT 24
Peak memory 206020 kb
Host smart-91880918-c094-4151-954a-874f992f7a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36000
24874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3600024874
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.777391288
Short name T1290
Test name
Test status
Simulation time 139725064 ps
CPU time 0.79 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 04:57:53 PM PDT 24
Peak memory 205928 kb
Host smart-fa6df721-62dd-4151-8377-72c4c02855a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77739
1288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.777391288
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.935171730
Short name T820
Test name
Test status
Simulation time 232048152 ps
CPU time 0.91 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 04:57:53 PM PDT 24
Peak memory 206024 kb
Host smart-8f927f93-a560-42c0-902b-0832b7d0c6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93517
1730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.935171730
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.510505272
Short name T1142
Test name
Test status
Simulation time 235821796 ps
CPU time 0.9 seconds
Started Jun 21 04:57:53 PM PDT 24
Finished Jun 21 04:57:58 PM PDT 24
Peak memory 205968 kb
Host smart-bb9a1f09-f7f2-4e77-9696-37aa628cf16b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51050
5272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.510505272
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.3680822398
Short name T1432
Test name
Test status
Simulation time 23301831117 ps
CPU time 23.56 seconds
Started Jun 21 04:57:47 PM PDT 24
Finished Jun 21 04:58:13 PM PDT 24
Peak memory 206092 kb
Host smart-759e1c4b-d8a6-43c5-8a8e-a7c72ca54bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36808
22398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.3680822398
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.3010272566
Short name T2179
Test name
Test status
Simulation time 3265472120 ps
CPU time 3.94 seconds
Started Jun 21 04:57:52 PM PDT 24
Finished Jun 21 04:58:00 PM PDT 24
Peak memory 206088 kb
Host smart-ce8ebaba-0387-4bbf-a0df-3e4edf180391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30102
72566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.3010272566
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.618134340
Short name T2412
Test name
Test status
Simulation time 13627084185 ps
CPU time 383.38 seconds
Started Jun 21 04:57:51 PM PDT 24
Finished Jun 21 05:04:18 PM PDT 24
Peak memory 206252 kb
Host smart-c393f6f6-5b41-4356-82be-7fc3fa6e69fa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=618134340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.618134340
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.172914082
Short name T562
Test name
Test status
Simulation time 247311381 ps
CPU time 0.86 seconds
Started Jun 21 04:57:52 PM PDT 24
Finished Jun 21 04:57:57 PM PDT 24
Peak memory 206052 kb
Host smart-aa4036b9-7d4b-4ca4-ac3b-f1ad08172ba4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=172914082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.172914082
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.773345711
Short name T2147
Test name
Test status
Simulation time 195748252 ps
CPU time 0.87 seconds
Started Jun 21 04:57:49 PM PDT 24
Finished Jun 21 04:57:53 PM PDT 24
Peak memory 206052 kb
Host smart-4ef448eb-53cb-44c7-ab60-1d3d410166cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77334
5711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.773345711
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.3859223599
Short name T2250
Test name
Test status
Simulation time 11106599050 ps
CPU time 104.19 seconds
Started Jun 21 04:57:47 PM PDT 24
Finished Jun 21 04:59:35 PM PDT 24
Peak memory 206152 kb
Host smart-23021b38-808c-4452-a229-70cea850922c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38592
23599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.3859223599
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.2439623117
Short name T1941
Test name
Test status
Simulation time 10460611962 ps
CPU time 284.41 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 05:02:36 PM PDT 24
Peak memory 206212 kb
Host smart-f4fb752c-bdf9-4c4d-a360-5c317bc23e24
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2439623117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.2439623117
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3849655243
Short name T1706
Test name
Test status
Simulation time 167843755 ps
CPU time 0.83 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 04:57:53 PM PDT 24
Peak memory 206028 kb
Host smart-cfa3da0c-2bbb-48ff-956f-4eeb1f83beda
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3849655243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3849655243
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2589735998
Short name T1712
Test name
Test status
Simulation time 166173399 ps
CPU time 0.79 seconds
Started Jun 21 04:57:52 PM PDT 24
Finished Jun 21 04:57:56 PM PDT 24
Peak memory 205988 kb
Host smart-8c2d0454-e5f6-46b6-bd10-b81961230a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25897
35998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2589735998
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.568538188
Short name T138
Test name
Test status
Simulation time 229178940 ps
CPU time 0.9 seconds
Started Jun 21 04:57:50 PM PDT 24
Finished Jun 21 04:57:55 PM PDT 24
Peak memory 206020 kb
Host smart-63760e54-584f-4445-9cb3-3e1594fd5c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56853
8188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.568538188
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.351376498
Short name T1093
Test name
Test status
Simulation time 201463156 ps
CPU time 0.87 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 04:57:53 PM PDT 24
Peak memory 205972 kb
Host smart-a7663632-5363-47c4-b65f-04fc682820dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35137
6498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.351376498
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.407251132
Short name T712
Test name
Test status
Simulation time 195540202 ps
CPU time 0.82 seconds
Started Jun 21 04:57:50 PM PDT 24
Finished Jun 21 04:57:55 PM PDT 24
Peak memory 206000 kb
Host smart-b84e4f55-dcae-42ed-842e-ffec36bbe05f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40725
1132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.407251132
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.983397688
Short name T474
Test name
Test status
Simulation time 178969124 ps
CPU time 0.83 seconds
Started Jun 21 04:57:50 PM PDT 24
Finished Jun 21 04:57:54 PM PDT 24
Peak memory 205920 kb
Host smart-401620da-81d6-4ec3-927a-dc2c7b72a1a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98339
7688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.983397688
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2652121097
Short name T891
Test name
Test status
Simulation time 149804004 ps
CPU time 0.78 seconds
Started Jun 21 04:57:50 PM PDT 24
Finished Jun 21 04:57:55 PM PDT 24
Peak memory 206024 kb
Host smart-092c14a6-defe-4886-a8f7-c235828c8074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26521
21097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2652121097
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.405562895
Short name T1147
Test name
Test status
Simulation time 233655665 ps
CPU time 0.95 seconds
Started Jun 21 04:57:50 PM PDT 24
Finished Jun 21 04:57:54 PM PDT 24
Peak memory 206048 kb
Host smart-c102adca-995b-465c-8ea5-e983f878a339
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=405562895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.405562895
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2486134416
Short name T2501
Test name
Test status
Simulation time 159775138 ps
CPU time 0.74 seconds
Started Jun 21 04:57:52 PM PDT 24
Finished Jun 21 04:57:57 PM PDT 24
Peak memory 205968 kb
Host smart-bb4a1d6c-ba74-41b5-9f7b-3a7ea18cb80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24861
34416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2486134416
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.106427718
Short name T1564
Test name
Test status
Simulation time 20121189910 ps
CPU time 45.5 seconds
Started Jun 21 04:57:53 PM PDT 24
Finished Jun 21 04:58:43 PM PDT 24
Peak memory 206228 kb
Host smart-14853234-7af1-4454-b9e7-15e27b9bc46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10642
7718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.106427718
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.4227532130
Short name T1013
Test name
Test status
Simulation time 151149783 ps
CPU time 0.83 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 04:57:53 PM PDT 24
Peak memory 206028 kb
Host smart-00d3705e-5dbd-488d-9459-d775ec99dfc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42275
32130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.4227532130
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3414997932
Short name T1373
Test name
Test status
Simulation time 185004913 ps
CPU time 0.83 seconds
Started Jun 21 04:57:52 PM PDT 24
Finished Jun 21 04:57:57 PM PDT 24
Peak memory 205904 kb
Host smart-8341ea91-2f5d-4d48-8c4a-f9fcbd87a5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34149
97932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3414997932
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.616915778
Short name T707
Test name
Test status
Simulation time 240086697 ps
CPU time 0.96 seconds
Started Jun 21 04:57:49 PM PDT 24
Finished Jun 21 04:57:53 PM PDT 24
Peak memory 206024 kb
Host smart-c4dfc512-9b6a-4427-b4eb-ea95ceba2fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61691
5778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.616915778
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3122337931
Short name T298
Test name
Test status
Simulation time 182973721 ps
CPU time 0.84 seconds
Started Jun 21 04:57:49 PM PDT 24
Finished Jun 21 04:57:54 PM PDT 24
Peak memory 206084 kb
Host smart-cfcd2f5a-c0ea-469c-a5c2-d3eb4829701b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31223
37931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3122337931
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3856331963
Short name T2432
Test name
Test status
Simulation time 138739587 ps
CPU time 0.79 seconds
Started Jun 21 04:57:51 PM PDT 24
Finished Jun 21 04:57:56 PM PDT 24
Peak memory 205956 kb
Host smart-71457217-16ce-459f-aec3-37444c21d96e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38563
31963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3856331963
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.2605325298
Short name T677
Test name
Test status
Simulation time 149824841 ps
CPU time 0.78 seconds
Started Jun 21 04:57:50 PM PDT 24
Finished Jun 21 04:57:55 PM PDT 24
Peak memory 206016 kb
Host smart-dfc841b8-5f47-4931-bb40-5e10b23a0fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26053
25298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2605325298
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2538455979
Short name T96
Test name
Test status
Simulation time 148953264 ps
CPU time 0.79 seconds
Started Jun 21 04:57:53 PM PDT 24
Finished Jun 21 04:57:57 PM PDT 24
Peak memory 206024 kb
Host smart-f5cbee03-5405-439a-b487-973e18a75699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25384
55979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2538455979
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1392768912
Short name T2203
Test name
Test status
Simulation time 245901599 ps
CPU time 1.01 seconds
Started Jun 21 04:57:42 PM PDT 24
Finished Jun 21 04:57:44 PM PDT 24
Peak memory 205976 kb
Host smart-57c1f98b-5eef-4f0a-82dd-7cf19b676dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13927
68912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1392768912
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.1381576955
Short name T759
Test name
Test status
Simulation time 10401230722 ps
CPU time 73.38 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 04:59:05 PM PDT 24
Peak memory 206316 kb
Host smart-2fe91746-d071-4bee-8fe2-f79a66a0dc7b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1381576955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.1381576955
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1110991784
Short name T763
Test name
Test status
Simulation time 162598015 ps
CPU time 0.79 seconds
Started Jun 21 04:57:48 PM PDT 24
Finished Jun 21 04:57:52 PM PDT 24
Peak memory 206008 kb
Host smart-9e6e5ffb-a996-4db8-bc07-7f32ed6f66c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11109
91784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1110991784
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2518537434
Short name T1761
Test name
Test status
Simulation time 174952382 ps
CPU time 0.77 seconds
Started Jun 21 04:57:52 PM PDT 24
Finished Jun 21 04:57:57 PM PDT 24
Peak memory 206020 kb
Host smart-5389ba38-6e6a-4be9-8384-c7ac442f2202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25185
37434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2518537434
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.733318331
Short name T1806
Test name
Test status
Simulation time 14592314233 ps
CPU time 107.53 seconds
Started Jun 21 04:57:49 PM PDT 24
Finished Jun 21 04:59:41 PM PDT 24
Peak memory 206332 kb
Host smart-0f7fe22f-05e9-4e50-9563-e3c813d86c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73331
8331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.733318331
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.2701677969
Short name T1150
Test name
Test status
Simulation time 3526058749 ps
CPU time 4.01 seconds
Started Jun 21 04:57:53 PM PDT 24
Finished Jun 21 04:58:01 PM PDT 24
Peak memory 206108 kb
Host smart-7ee0b1b4-5537-4417-8da0-84f71a307da5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2701677969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.2701677969
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.1511776920
Short name T2092
Test name
Test status
Simulation time 13350338609 ps
CPU time 13.67 seconds
Started Jun 21 04:57:50 PM PDT 24
Finished Jun 21 04:58:07 PM PDT 24
Peak memory 206208 kb
Host smart-6a1cfcbd-25c4-44dc-9645-4a5637a46adb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1511776920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1511776920
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.4003586296
Short name T2017
Test name
Test status
Simulation time 23350011777 ps
CPU time 22.86 seconds
Started Jun 21 04:57:54 PM PDT 24
Finished Jun 21 04:58:21 PM PDT 24
Peak memory 206036 kb
Host smart-549e8550-72db-476d-8ccd-972eb1bf0362
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4003586296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.4003586296
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2241864664
Short name T793
Test name
Test status
Simulation time 160912953 ps
CPU time 0.79 seconds
Started Jun 21 04:57:50 PM PDT 24
Finished Jun 21 04:57:55 PM PDT 24
Peak memory 206148 kb
Host smart-cf56890a-c2fb-493f-93a4-e568a469f9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22418
64664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2241864664
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.582432723
Short name T1241
Test name
Test status
Simulation time 186637696 ps
CPU time 0.77 seconds
Started Jun 21 04:57:52 PM PDT 24
Finished Jun 21 04:57:57 PM PDT 24
Peak memory 205972 kb
Host smart-03e429bb-545b-47f9-8970-650b53b4c54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58243
2723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.582432723
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.3546119630
Short name T74
Test name
Test status
Simulation time 176125900 ps
CPU time 0.83 seconds
Started Jun 21 04:57:54 PM PDT 24
Finished Jun 21 04:57:59 PM PDT 24
Peak memory 205972 kb
Host smart-71f0b1a9-9509-49f4-9c5e-2d4a69e56ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35461
19630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.3546119630
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2923004974
Short name T2182
Test name
Test status
Simulation time 1098242145 ps
CPU time 2.37 seconds
Started Jun 21 04:57:53 PM PDT 24
Finished Jun 21 04:57:59 PM PDT 24
Peak memory 206172 kb
Host smart-bef91151-50cd-47f2-9ac0-1909b17dcdc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29230
04974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2923004974
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.2446922722
Short name T1223
Test name
Test status
Simulation time 16525911805 ps
CPU time 29.13 seconds
Started Jun 21 04:57:53 PM PDT 24
Finished Jun 21 04:58:26 PM PDT 24
Peak memory 206300 kb
Host smart-059e5c1e-032d-4e2c-a3c2-689ed89663f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24469
22722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.2446922722
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.1684782580
Short name T423
Test name
Test status
Simulation time 424322094 ps
CPU time 1.31 seconds
Started Jun 21 04:57:52 PM PDT 24
Finished Jun 21 04:57:57 PM PDT 24
Peak memory 206028 kb
Host smart-fed21ce7-f254-42b1-9cb9-136670d6cb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16847
82580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.1684782580
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.3636800244
Short name T1390
Test name
Test status
Simulation time 153151620 ps
CPU time 0.75 seconds
Started Jun 21 04:57:52 PM PDT 24
Finished Jun 21 04:57:56 PM PDT 24
Peak memory 205976 kb
Host smart-e8be3388-64ea-46f1-bb21-f1b8fd2c82e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36368
00244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.3636800244
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.429493781
Short name T465
Test name
Test status
Simulation time 53500445 ps
CPU time 0.68 seconds
Started Jun 21 04:57:51 PM PDT 24
Finished Jun 21 04:57:56 PM PDT 24
Peak memory 205956 kb
Host smart-5f99c23d-b05b-4623-922d-0036ac9191f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42949
3781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.429493781
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1642676916
Short name T1255
Test name
Test status
Simulation time 917634750 ps
CPU time 2.39 seconds
Started Jun 21 04:57:53 PM PDT 24
Finished Jun 21 04:57:59 PM PDT 24
Peak memory 206132 kb
Host smart-d83312bf-a5c2-411c-a29f-f8364966ffd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16426
76916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1642676916
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2961123818
Short name T2041
Test name
Test status
Simulation time 193571198 ps
CPU time 2.2 seconds
Started Jun 21 04:57:51 PM PDT 24
Finished Jun 21 04:57:57 PM PDT 24
Peak memory 206216 kb
Host smart-cbc05f6b-3af0-4d49-bccd-33e4ef010143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29611
23818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2961123818
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3189667214
Short name T387
Test name
Test status
Simulation time 185932485 ps
CPU time 0.83 seconds
Started Jun 21 04:57:57 PM PDT 24
Finished Jun 21 04:58:01 PM PDT 24
Peak memory 205928 kb
Host smart-3e837c3c-e7d5-45dd-9f71-f62cc40586e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31896
67214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3189667214
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1678061801
Short name T2066
Test name
Test status
Simulation time 147379623 ps
CPU time 0.8 seconds
Started Jun 21 04:57:56 PM PDT 24
Finished Jun 21 04:58:01 PM PDT 24
Peak memory 205968 kb
Host smart-08e8e930-619e-491d-adfd-34900d6ab309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16780
61801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1678061801
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3563387758
Short name T1447
Test name
Test status
Simulation time 200831626 ps
CPU time 0.88 seconds
Started Jun 21 04:57:56 PM PDT 24
Finished Jun 21 04:58:01 PM PDT 24
Peak memory 206024 kb
Host smart-c84dad15-085e-4ecc-8611-25e39cb43aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35633
87758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3563387758
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.2276880004
Short name T1671
Test name
Test status
Simulation time 159039301 ps
CPU time 0.78 seconds
Started Jun 21 04:57:55 PM PDT 24
Finished Jun 21 04:58:00 PM PDT 24
Peak memory 205972 kb
Host smart-c7ff98ae-4f08-45f1-a9dc-1201be789d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22768
80004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2276880004
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.175284453
Short name T1516
Test name
Test status
Simulation time 23385236667 ps
CPU time 24.45 seconds
Started Jun 21 04:57:55 PM PDT 24
Finished Jun 21 04:58:24 PM PDT 24
Peak memory 206088 kb
Host smart-d0c91dfb-2303-4830-a8f5-4b80d38caac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17528
4453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.175284453
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1525179984
Short name T1551
Test name
Test status
Simulation time 3340663598 ps
CPU time 3.73 seconds
Started Jun 21 04:57:55 PM PDT 24
Finished Jun 21 04:58:02 PM PDT 24
Peak memory 206028 kb
Host smart-6dff2cff-06db-4e90-a56d-0195dc2ebc0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15251
79984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1525179984
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3806860569
Short name T2222
Test name
Test status
Simulation time 8403838030 ps
CPU time 217.66 seconds
Started Jun 21 04:57:57 PM PDT 24
Finished Jun 21 05:01:38 PM PDT 24
Peak memory 206220 kb
Host smart-f8cd6bbb-75ca-461b-8bf5-f41ce255bc9d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3806860569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3806860569
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.2088703739
Short name T1616
Test name
Test status
Simulation time 238690471 ps
CPU time 0.92 seconds
Started Jun 21 04:57:58 PM PDT 24
Finished Jun 21 04:58:02 PM PDT 24
Peak memory 205988 kb
Host smart-df2df31c-81e9-4605-b57f-d2efc2c9ed80
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2088703739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.2088703739
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2792439668
Short name T1422
Test name
Test status
Simulation time 212438898 ps
CPU time 0.86 seconds
Started Jun 21 04:57:55 PM PDT 24
Finished Jun 21 04:58:00 PM PDT 24
Peak memory 206008 kb
Host smart-9b2d0687-e0d6-4aec-bf61-51d337678edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27924
39668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2792439668
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2184746445
Short name T404
Test name
Test status
Simulation time 5485760181 ps
CPU time 51.17 seconds
Started Jun 21 04:57:56 PM PDT 24
Finished Jun 21 04:58:50 PM PDT 24
Peak memory 206248 kb
Host smart-46cdbb61-8339-4df1-b72b-b6b14804cc1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21847
46445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2184746445
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.3601972840
Short name T2089
Test name
Test status
Simulation time 9488036148 ps
CPU time 269.69 seconds
Started Jun 21 04:57:56 PM PDT 24
Finished Jun 21 05:02:29 PM PDT 24
Peak memory 206200 kb
Host smart-dd9f907d-fb21-418f-a420-02b0e1e0a07b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3601972840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.3601972840
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2627700124
Short name T1790
Test name
Test status
Simulation time 177615405 ps
CPU time 0.81 seconds
Started Jun 21 04:57:57 PM PDT 24
Finished Jun 21 04:58:01 PM PDT 24
Peak memory 206048 kb
Host smart-6b151280-eb08-4d05-93b3-c8044d3ea081
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2627700124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2627700124
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.461277906
Short name T844
Test name
Test status
Simulation time 140481514 ps
CPU time 0.74 seconds
Started Jun 21 04:57:53 PM PDT 24
Finished Jun 21 04:57:57 PM PDT 24
Peak memory 205996 kb
Host smart-0f27767d-73ce-461e-be66-3db15105659c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46127
7906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.461277906
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1796707143
Short name T123
Test name
Test status
Simulation time 190767502 ps
CPU time 0.87 seconds
Started Jun 21 04:57:56 PM PDT 24
Finished Jun 21 04:58:00 PM PDT 24
Peak memory 205948 kb
Host smart-3125c57f-9807-4af6-8f86-e141f602ce19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17967
07143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1796707143
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.196541776
Short name T1675
Test name
Test status
Simulation time 145565661 ps
CPU time 0.82 seconds
Started Jun 21 04:58:00 PM PDT 24
Finished Jun 21 04:58:02 PM PDT 24
Peak memory 205964 kb
Host smart-9626adbd-0385-407e-9d7f-41d6a5fc922c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19654
1776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.196541776
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2707063726
Short name T1073
Test name
Test status
Simulation time 178610181 ps
CPU time 0.8 seconds
Started Jun 21 04:57:57 PM PDT 24
Finished Jun 21 04:58:01 PM PDT 24
Peak memory 206024 kb
Host smart-1141869a-b8a1-4b32-bfeb-e0e6c289d83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27070
63726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2707063726
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3668666120
Short name T1052
Test name
Test status
Simulation time 169912980 ps
CPU time 0.82 seconds
Started Jun 21 04:57:57 PM PDT 24
Finished Jun 21 04:58:01 PM PDT 24
Peak memory 206040 kb
Host smart-655916ab-213b-46e1-a09d-cd151c874c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36686
66120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3668666120
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2882410141
Short name T1936
Test name
Test status
Simulation time 148265492 ps
CPU time 0.8 seconds
Started Jun 21 04:57:55 PM PDT 24
Finished Jun 21 04:57:59 PM PDT 24
Peak memory 205948 kb
Host smart-08ae44c0-c2f5-4c8a-94e2-7cba1366a5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28824
10141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2882410141
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.4183366010
Short name T1543
Test name
Test status
Simulation time 256509019 ps
CPU time 0.99 seconds
Started Jun 21 04:57:57 PM PDT 24
Finished Jun 21 04:58:01 PM PDT 24
Peak memory 205972 kb
Host smart-20ab423f-ad16-4bcb-a04f-407e65337b3b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4183366010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.4183366010
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3143546749
Short name T896
Test name
Test status
Simulation time 143574449 ps
CPU time 0.74 seconds
Started Jun 21 04:57:57 PM PDT 24
Finished Jun 21 04:58:01 PM PDT 24
Peak memory 206044 kb
Host smart-48c2353f-ba1d-4a69-8a2f-22fdbb233c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31435
46749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3143546749
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.4115754336
Short name T1853
Test name
Test status
Simulation time 38650370 ps
CPU time 0.65 seconds
Started Jun 21 04:57:55 PM PDT 24
Finished Jun 21 04:58:00 PM PDT 24
Peak memory 205972 kb
Host smart-88aa6a08-59cb-4d4d-bb79-498894bdec07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41157
54336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.4115754336
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.313356024
Short name T160
Test name
Test status
Simulation time 16235843212 ps
CPU time 36.88 seconds
Started Jun 21 04:57:56 PM PDT 24
Finished Jun 21 04:58:36 PM PDT 24
Peak memory 206376 kb
Host smart-1efdb360-d763-4ed4-bdc4-f132f3cbed99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31335
6024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.313356024
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.3219036645
Short name T1428
Test name
Test status
Simulation time 167202968 ps
CPU time 0.79 seconds
Started Jun 21 04:57:56 PM PDT 24
Finished Jun 21 04:58:01 PM PDT 24
Peak memory 206028 kb
Host smart-568f21e2-0bed-4fe5-8984-b5922df0b130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32190
36645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.3219036645
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1272871370
Short name T1746
Test name
Test status
Simulation time 186057553 ps
CPU time 0.91 seconds
Started Jun 21 04:57:59 PM PDT 24
Finished Jun 21 04:58:02 PM PDT 24
Peak memory 206024 kb
Host smart-e1f58dcb-0ada-42ac-a1d0-203fdd68d1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12728
71370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1272871370
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.1724862600
Short name T1583
Test name
Test status
Simulation time 211949901 ps
CPU time 0.86 seconds
Started Jun 21 04:57:56 PM PDT 24
Finished Jun 21 04:58:00 PM PDT 24
Peak memory 206028 kb
Host smart-5063a3f1-362d-4976-a4e0-1cc7db7e3a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17248
62600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.1724862600
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.469505692
Short name T1607
Test name
Test status
Simulation time 174399712 ps
CPU time 0.78 seconds
Started Jun 21 04:57:57 PM PDT 24
Finished Jun 21 04:58:01 PM PDT 24
Peak memory 205936 kb
Host smart-f1d56a96-ad02-4558-843f-60d96a0c76f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46950
5692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.469505692
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.3244431932
Short name T2233
Test name
Test status
Simulation time 169383692 ps
CPU time 0.78 seconds
Started Jun 21 04:57:56 PM PDT 24
Finished Jun 21 04:58:01 PM PDT 24
Peak memory 206016 kb
Host smart-ef5d7fd2-4eeb-479b-9fab-fdb6ed1e5f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32444
31932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3244431932
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1884136545
Short name T305
Test name
Test status
Simulation time 140989937 ps
CPU time 0.75 seconds
Started Jun 21 04:57:55 PM PDT 24
Finished Jun 21 04:57:59 PM PDT 24
Peak memory 205964 kb
Host smart-2789bdbe-1b5b-4f17-a859-fc979cec330c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18841
36545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1884136545
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1511133083
Short name T2014
Test name
Test status
Simulation time 211892020 ps
CPU time 0.82 seconds
Started Jun 21 04:57:56 PM PDT 24
Finished Jun 21 04:58:00 PM PDT 24
Peak memory 205972 kb
Host smart-a8e76109-a839-4c44-87b4-f8b5d92baf53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15111
33083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1511133083
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2060107476
Short name T2263
Test name
Test status
Simulation time 187672242 ps
CPU time 0.88 seconds
Started Jun 21 04:57:49 PM PDT 24
Finished Jun 21 04:57:54 PM PDT 24
Peak memory 205928 kb
Host smart-513039fb-ac78-4da6-92cc-10a8699aa643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20601
07476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2060107476
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.13274235
Short name T1872
Test name
Test status
Simulation time 7491637501 ps
CPU time 210.53 seconds
Started Jun 21 04:57:54 PM PDT 24
Finished Jun 21 05:01:29 PM PDT 24
Peak memory 206316 kb
Host smart-6c1dffdb-d8b5-42f3-b797-0c8bc5f35560
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=13274235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.13274235
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.44903766
Short name T1353
Test name
Test status
Simulation time 205298853 ps
CPU time 0.83 seconds
Started Jun 21 04:57:57 PM PDT 24
Finished Jun 21 04:58:01 PM PDT 24
Peak memory 205972 kb
Host smart-3986e9b8-5c74-4e5e-b56d-e691c39a0312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44903
766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.44903766
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1962910532
Short name T1302
Test name
Test status
Simulation time 189174277 ps
CPU time 0.81 seconds
Started Jun 21 04:57:55 PM PDT 24
Finished Jun 21 04:57:59 PM PDT 24
Peak memory 205968 kb
Host smart-c75759b2-179a-4d6e-a702-e11085898054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19629
10532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1962910532
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.272013462
Short name T1960
Test name
Test status
Simulation time 13329948423 ps
CPU time 127.28 seconds
Started Jun 21 04:57:55 PM PDT 24
Finished Jun 21 05:00:06 PM PDT 24
Peak memory 206292 kb
Host smart-fe7a3476-f203-4790-9354-4a3c00cffd02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27201
3462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.272013462
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2132932723
Short name T1403
Test name
Test status
Simulation time 3794799532 ps
CPU time 4.26 seconds
Started Jun 21 04:58:04 PM PDT 24
Finished Jun 21 04:58:10 PM PDT 24
Peak memory 206084 kb
Host smart-af1279f3-f293-4c80-b418-1bb4e0576254
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2132932723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.2132932723
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.1288924227
Short name T2065
Test name
Test status
Simulation time 13331624745 ps
CPU time 12.16 seconds
Started Jun 21 04:58:05 PM PDT 24
Finished Jun 21 04:58:19 PM PDT 24
Peak memory 206124 kb
Host smart-ebbfd303-cae5-4bd3-8e46-c04cb7f7554a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1288924227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.1288924227
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.65223270
Short name T976
Test name
Test status
Simulation time 23305569098 ps
CPU time 22.1 seconds
Started Jun 21 04:58:02 PM PDT 24
Finished Jun 21 04:58:25 PM PDT 24
Peak memory 206084 kb
Host smart-757c9618-5993-4452-a0b1-d4fbf6097802
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=65223270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.65223270
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1127922911
Short name T1443
Test name
Test status
Simulation time 183727362 ps
CPU time 0.91 seconds
Started Jun 21 04:58:03 PM PDT 24
Finished Jun 21 04:58:05 PM PDT 24
Peak memory 205964 kb
Host smart-83ee6b7b-cd7c-4550-a8ce-d8ff867dec27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11279
22911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1127922911
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.2495161775
Short name T1968
Test name
Test status
Simulation time 147811327 ps
CPU time 0.75 seconds
Started Jun 21 04:58:04 PM PDT 24
Finished Jun 21 04:58:07 PM PDT 24
Peak memory 206024 kb
Host smart-da950002-143c-4373-b1ea-a2ef9f08e0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24951
61775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.2495161775
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.3100609454
Short name T2266
Test name
Test status
Simulation time 380138435 ps
CPU time 1.25 seconds
Started Jun 21 04:58:04 PM PDT 24
Finished Jun 21 04:58:07 PM PDT 24
Peak memory 206004 kb
Host smart-96f33640-6e28-4edb-bccd-4288ad06cd2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31006
09454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.3100609454
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.1427270885
Short name T1641
Test name
Test status
Simulation time 724767489 ps
CPU time 1.75 seconds
Started Jun 21 04:58:05 PM PDT 24
Finished Jun 21 04:58:08 PM PDT 24
Peak memory 206220 kb
Host smart-0414a684-857e-44f3-a69c-425b7b9e1596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14272
70885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.1427270885
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.19243500
Short name T1240
Test name
Test status
Simulation time 15939172025 ps
CPU time 33.48 seconds
Started Jun 21 04:58:04 PM PDT 24
Finished Jun 21 04:58:39 PM PDT 24
Peak memory 206248 kb
Host smart-e5783616-64fd-40d4-acf7-38c51b930de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19243
500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.19243500
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.1762031701
Short name T1883
Test name
Test status
Simulation time 312761193 ps
CPU time 1.14 seconds
Started Jun 21 04:58:02 PM PDT 24
Finished Jun 21 04:58:03 PM PDT 24
Peak memory 205924 kb
Host smart-7befe804-6ec1-4b7e-8e3f-e623a0f4e388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17620
31701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1762031701
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2515164437
Short name T909
Test name
Test status
Simulation time 139101397 ps
CPU time 0.79 seconds
Started Jun 21 04:58:03 PM PDT 24
Finished Jun 21 04:58:05 PM PDT 24
Peak memory 206140 kb
Host smart-65dea94a-b873-4d39-b46f-c933a2327115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25151
64437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2515164437
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1488050342
Short name T1208
Test name
Test status
Simulation time 49389731 ps
CPU time 0.65 seconds
Started Jun 21 04:58:04 PM PDT 24
Finished Jun 21 04:58:06 PM PDT 24
Peak memory 206040 kb
Host smart-3659a993-aa1b-456a-94dc-8983cc2d03a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14880
50342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1488050342
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.959230509
Short name T2303
Test name
Test status
Simulation time 854186915 ps
CPU time 2.18 seconds
Started Jun 21 04:58:03 PM PDT 24
Finished Jun 21 04:58:06 PM PDT 24
Peak memory 206136 kb
Host smart-4c3b32c3-be01-4680-bfc1-14b1432542c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95923
0509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.959230509
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1198449309
Short name T1938
Test name
Test status
Simulation time 177420812 ps
CPU time 1.48 seconds
Started Jun 21 04:58:03 PM PDT 24
Finished Jun 21 04:58:05 PM PDT 24
Peak memory 206160 kb
Host smart-e3cb7373-0c51-4093-b478-a2ab7f476de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11984
49309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1198449309
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3196567034
Short name T430
Test name
Test status
Simulation time 229642420 ps
CPU time 0.86 seconds
Started Jun 21 04:58:12 PM PDT 24
Finished Jun 21 04:58:16 PM PDT 24
Peak memory 205960 kb
Host smart-179f5fe4-ac4c-483c-b155-453f8f30e214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31965
67034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3196567034
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2426249766
Short name T1686
Test name
Test status
Simulation time 151159394 ps
CPU time 0.79 seconds
Started Jun 21 04:58:13 PM PDT 24
Finished Jun 21 04:58:17 PM PDT 24
Peak memory 205960 kb
Host smart-8260f1df-4327-43b4-8fd3-4b8067728678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24262
49766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2426249766
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2195986250
Short name T2434
Test name
Test status
Simulation time 193797608 ps
CPU time 0.84 seconds
Started Jun 21 04:58:04 PM PDT 24
Finished Jun 21 04:58:07 PM PDT 24
Peak memory 205964 kb
Host smart-0f2bfb04-58ab-4df9-a16f-9dc7322b25ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21959
86250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2195986250
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.2056859556
Short name T2096
Test name
Test status
Simulation time 230166743 ps
CPU time 0.89 seconds
Started Jun 21 04:58:04 PM PDT 24
Finished Jun 21 04:58:08 PM PDT 24
Peak memory 205920 kb
Host smart-83796438-b2fa-4092-9126-9e7a6cb01587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20568
59556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.2056859556
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3128611506
Short name T1757
Test name
Test status
Simulation time 23271259497 ps
CPU time 23.8 seconds
Started Jun 21 04:58:03 PM PDT 24
Finished Jun 21 04:58:28 PM PDT 24
Peak memory 206084 kb
Host smart-9c0774f2-e911-4d31-8076-f3e9c66050d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31286
11506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3128611506
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1700333139
Short name T698
Test name
Test status
Simulation time 3325669860 ps
CPU time 3.61 seconds
Started Jun 21 04:58:03 PM PDT 24
Finished Jun 21 04:58:07 PM PDT 24
Peak memory 206036 kb
Host smart-12fe8737-b89c-4aa5-9ae5-5bbaf9a96ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17003
33139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1700333139
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.2589721590
Short name T802
Test name
Test status
Simulation time 10779701180 ps
CPU time 308.53 seconds
Started Jun 21 04:58:03 PM PDT 24
Finished Jun 21 05:03:12 PM PDT 24
Peak memory 206212 kb
Host smart-b1578a9a-46cc-49e5-b0ab-68d9fd03e60a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2589721590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.2589721590
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.444405794
Short name T306
Test name
Test status
Simulation time 237412978 ps
CPU time 1 seconds
Started Jun 21 04:58:12 PM PDT 24
Finished Jun 21 04:58:16 PM PDT 24
Peak memory 205956 kb
Host smart-b866dab3-8025-4b42-a0d9-462b8a67f587
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=444405794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.444405794
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2296166860
Short name T1857
Test name
Test status
Simulation time 196629943 ps
CPU time 0.95 seconds
Started Jun 21 04:58:05 PM PDT 24
Finished Jun 21 04:58:08 PM PDT 24
Peak memory 205972 kb
Host smart-4a900a97-9e7f-4c0f-84eb-45ace1a24c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22961
66860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2296166860
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.1665760925
Short name T1722
Test name
Test status
Simulation time 11928383573 ps
CPU time 82.51 seconds
Started Jun 21 04:58:04 PM PDT 24
Finished Jun 21 04:59:28 PM PDT 24
Peak memory 206264 kb
Host smart-940224ab-ed2f-4cca-bc98-663ca87fee6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16657
60925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.1665760925
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.3355529685
Short name T83
Test name
Test status
Simulation time 8973481433 ps
CPU time 247.38 seconds
Started Jun 21 04:58:05 PM PDT 24
Finished Jun 21 05:02:14 PM PDT 24
Peak memory 206272 kb
Host smart-c2125c67-cd99-4431-864e-bb0f34d02902
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3355529685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.3355529685
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.938620519
Short name T1352
Test name
Test status
Simulation time 200058027 ps
CPU time 0.89 seconds
Started Jun 21 04:58:13 PM PDT 24
Finished Jun 21 04:58:17 PM PDT 24
Peak memory 205972 kb
Host smart-c6c7d5ca-c7cc-4cf6-aa65-90edf261897d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=938620519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.938620519
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1187890448
Short name T2047
Test name
Test status
Simulation time 163929656 ps
CPU time 0.78 seconds
Started Jun 21 04:58:04 PM PDT 24
Finished Jun 21 04:58:07 PM PDT 24
Peak memory 205956 kb
Host smart-bdd6ab2a-7e3f-4f89-9005-412dff1a89d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11878
90448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1187890448
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.2201735863
Short name T1929
Test name
Test status
Simulation time 182440327 ps
CPU time 0.8 seconds
Started Jun 21 04:58:04 PM PDT 24
Finished Jun 21 04:58:07 PM PDT 24
Peak memory 206000 kb
Host smart-8b5c1a05-853a-4668-a9f6-ceac17bad212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22017
35863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.2201735863
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3035241016
Short name T488
Test name
Test status
Simulation time 191196882 ps
CPU time 0.84 seconds
Started Jun 21 04:58:03 PM PDT 24
Finished Jun 21 04:58:05 PM PDT 24
Peak memory 206032 kb
Host smart-82ce5463-fd6e-46ed-83fb-deafe4959c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30352
41016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3035241016
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3657049176
Short name T548
Test name
Test status
Simulation time 187241034 ps
CPU time 0.84 seconds
Started Jun 21 04:58:05 PM PDT 24
Finished Jun 21 04:58:08 PM PDT 24
Peak memory 205980 kb
Host smart-51ad0135-2019-41fa-9571-eb0e877a7b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36570
49176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3657049176
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1240333598
Short name T1369
Test name
Test status
Simulation time 158797916 ps
CPU time 0.78 seconds
Started Jun 21 04:58:09 PM PDT 24
Finished Jun 21 04:58:11 PM PDT 24
Peak memory 205964 kb
Host smart-73c8e8cb-cf3a-40bf-b597-80b6954e5106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12403
33598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1240333598
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1320511254
Short name T913
Test name
Test status
Simulation time 249841470 ps
CPU time 1.04 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:58:13 PM PDT 24
Peak memory 205972 kb
Host smart-cc6788ac-6b62-4efe-a576-3f9aeaa90c55
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1320511254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1320511254
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.3433928645
Short name T1051
Test name
Test status
Simulation time 171541827 ps
CPU time 0.78 seconds
Started Jun 21 04:58:10 PM PDT 24
Finished Jun 21 04:58:12 PM PDT 24
Peak memory 205980 kb
Host smart-8424dd68-3d0b-4788-bf14-9ebe0af1750a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34339
28645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.3433928645
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3726656046
Short name T2055
Test name
Test status
Simulation time 63466674 ps
CPU time 0.71 seconds
Started Jun 21 04:58:14 PM PDT 24
Finished Jun 21 04:58:17 PM PDT 24
Peak memory 205936 kb
Host smart-07881cef-45af-4e8d-994a-4024a03762f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37266
56046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3726656046
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.4010633615
Short name T1226
Test name
Test status
Simulation time 18090332000 ps
CPU time 40.51 seconds
Started Jun 21 04:58:03 PM PDT 24
Finished Jun 21 04:58:44 PM PDT 24
Peak memory 206288 kb
Host smart-fb260891-20fe-4de8-a2c8-96e179615c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40106
33615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.4010633615
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1343713576
Short name T273
Test name
Test status
Simulation time 182364723 ps
CPU time 0.97 seconds
Started Jun 21 04:58:01 PM PDT 24
Finished Jun 21 04:58:03 PM PDT 24
Peak memory 206004 kb
Host smart-6e719a67-c6c4-4862-947a-2f6c18f15f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13437
13576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1343713576
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1314230897
Short name T860
Test name
Test status
Simulation time 161262458 ps
CPU time 0.74 seconds
Started Jun 21 04:58:03 PM PDT 24
Finished Jun 21 04:58:05 PM PDT 24
Peak memory 205968 kb
Host smart-c3cc2430-c592-47fa-909c-e16a1990f7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13142
30897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1314230897
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2247677064
Short name T1776
Test name
Test status
Simulation time 209325388 ps
CPU time 0.97 seconds
Started Jun 21 04:58:13 PM PDT 24
Finished Jun 21 04:58:17 PM PDT 24
Peak memory 205932 kb
Host smart-5623c7a0-bd41-44ce-90ed-52f0e92ec010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22476
77064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2247677064
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.660109350
Short name T2320
Test name
Test status
Simulation time 167442620 ps
CPU time 0.82 seconds
Started Jun 21 04:58:04 PM PDT 24
Finished Jun 21 04:58:06 PM PDT 24
Peak memory 205952 kb
Host smart-11f90c58-875d-4f63-accf-91c39206e4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66010
9350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.660109350
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.4136485689
Short name T69
Test name
Test status
Simulation time 218995899 ps
CPU time 0.82 seconds
Started Jun 21 04:58:12 PM PDT 24
Finished Jun 21 04:58:16 PM PDT 24
Peak memory 206028 kb
Host smart-a8fe9870-54cc-4f25-ba0a-268d005cefe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41364
85689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.4136485689
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.942446821
Short name T2289
Test name
Test status
Simulation time 199945289 ps
CPU time 0.84 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:58:14 PM PDT 24
Peak memory 205960 kb
Host smart-9beb5eee-3133-404a-8034-5a3a26af4757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94244
6821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.942446821
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.942691543
Short name T1133
Test name
Test status
Simulation time 154788077 ps
CPU time 0.78 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:58:14 PM PDT 24
Peak memory 205980 kb
Host smart-a0e65e9e-86a2-4404-ad4d-d7add38e35ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94269
1543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.942691543
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.801856943
Short name T1552
Test name
Test status
Simulation time 211709038 ps
CPU time 0.89 seconds
Started Jun 21 04:57:52 PM PDT 24
Finished Jun 21 04:57:57 PM PDT 24
Peak memory 206028 kb
Host smart-6e4537d4-05af-41ad-b3b9-1a09584fa285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80185
6943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.801856943
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.1651134539
Short name T1184
Test name
Test status
Simulation time 12947747566 ps
CPU time 114.82 seconds
Started Jun 21 04:58:05 PM PDT 24
Finished Jun 21 05:00:02 PM PDT 24
Peak memory 206236 kb
Host smart-14b43af7-5142-4a72-8e86-417edd06eb5b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1651134539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.1651134539
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1391814065
Short name T1148
Test name
Test status
Simulation time 150616100 ps
CPU time 0.91 seconds
Started Jun 21 04:58:16 PM PDT 24
Finished Jun 21 04:58:18 PM PDT 24
Peak memory 205968 kb
Host smart-e07af305-837a-4e43-9d3e-d5f1eacae8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13918
14065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1391814065
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1838847593
Short name T353
Test name
Test status
Simulation time 192437668 ps
CPU time 0.81 seconds
Started Jun 21 04:58:13 PM PDT 24
Finished Jun 21 04:58:16 PM PDT 24
Peak memory 206012 kb
Host smart-af50b807-4484-4dfd-8e44-e4c05515b337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18388
47593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1838847593
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.3139180390
Short name T883
Test name
Test status
Simulation time 8828808276 ps
CPU time 88.11 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:59:40 PM PDT 24
Peak memory 206244 kb
Host smart-29fe49e6-5381-4c0d-9e8d-10cf018d965e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31391
80390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.3139180390
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.148745915
Short name T2332
Test name
Test status
Simulation time 3869893164 ps
CPU time 4.92 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:58:19 PM PDT 24
Peak memory 206260 kb
Host smart-542e1120-8a60-4e6d-98dd-2e1486a6d995
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=148745915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.148745915
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.1109830116
Short name T2100
Test name
Test status
Simulation time 13336040289 ps
CPU time 16.47 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:58:31 PM PDT 24
Peak memory 206032 kb
Host smart-b894eac8-cc63-4916-b30e-d906037c9f2e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1109830116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.1109830116
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.1565810892
Short name T461
Test name
Test status
Simulation time 23427227273 ps
CPU time 25.62 seconds
Started Jun 21 04:58:16 PM PDT 24
Finished Jun 21 04:58:43 PM PDT 24
Peak memory 206204 kb
Host smart-2a683b50-e49a-4065-8ab7-6d160ba16cb8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1565810892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.1565810892
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1880312335
Short name T870
Test name
Test status
Simulation time 172798654 ps
CPU time 0.8 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:58:15 PM PDT 24
Peak memory 206024 kb
Host smart-cd79ddad-b33f-4e0d-bd53-e55e635eaeb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18803
12335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1880312335
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2792509045
Short name T828
Test name
Test status
Simulation time 154727332 ps
CPU time 0.8 seconds
Started Jun 21 04:58:15 PM PDT 24
Finished Jun 21 04:58:18 PM PDT 24
Peak memory 205976 kb
Host smart-d26445a0-1513-42d1-b5af-94b598d8f7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27925
09045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2792509045
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.3597233911
Short name T969
Test name
Test status
Simulation time 561578280 ps
CPU time 1.57 seconds
Started Jun 21 04:58:12 PM PDT 24
Finished Jun 21 04:58:16 PM PDT 24
Peak memory 206272 kb
Host smart-82620e8b-d4fc-4415-a772-6aad2b8357ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35972
33911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.3597233911
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.1610178848
Short name T962
Test name
Test status
Simulation time 689135913 ps
CPU time 1.67 seconds
Started Jun 21 04:58:13 PM PDT 24
Finished Jun 21 04:58:18 PM PDT 24
Peak memory 205972 kb
Host smart-bebcf1cf-ad0b-4cb0-a166-8dc97dc9e52e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16101
78848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.1610178848
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.2329055070
Short name T94
Test name
Test status
Simulation time 20500248627 ps
CPU time 39.26 seconds
Started Jun 21 04:58:15 PM PDT 24
Finished Jun 21 04:58:56 PM PDT 24
Peak memory 206304 kb
Host smart-ea875a91-507d-40b8-b2b1-ceb93fabc9e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23290
55070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.2329055070
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.268072115
Short name T1230
Test name
Test status
Simulation time 410810340 ps
CPU time 1.36 seconds
Started Jun 21 04:58:09 PM PDT 24
Finished Jun 21 04:58:11 PM PDT 24
Peak memory 206028 kb
Host smart-c7bba4cf-2f3e-4d0e-a1f1-7353d697f938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26807
2115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.268072115
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1830793784
Short name T2364
Test name
Test status
Simulation time 138788802 ps
CPU time 0.8 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:58:15 PM PDT 24
Peak memory 206004 kb
Host smart-3a6358c4-ebdb-4d0c-bf56-62c1a4f422c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18307
93784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1830793784
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.1645151638
Short name T2352
Test name
Test status
Simulation time 52328703 ps
CPU time 0.65 seconds
Started Jun 21 04:58:15 PM PDT 24
Finished Jun 21 04:58:18 PM PDT 24
Peak memory 205952 kb
Host smart-f612d241-974e-4ee8-8d5c-3b84228b15d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16451
51638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.1645151638
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3102064276
Short name T682
Test name
Test status
Simulation time 757006585 ps
CPU time 1.91 seconds
Started Jun 21 04:58:13 PM PDT 24
Finished Jun 21 04:58:18 PM PDT 24
Peak memory 206312 kb
Host smart-d4eae5dc-d810-460b-9baf-6da7e99565e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31020
64276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3102064276
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3588304440
Short name T2093
Test name
Test status
Simulation time 206515409 ps
CPU time 1.9 seconds
Started Jun 21 04:58:10 PM PDT 24
Finished Jun 21 04:58:12 PM PDT 24
Peak memory 206084 kb
Host smart-8aad120e-9d00-4ba8-98a9-e05bfd0363cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35883
04440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3588304440
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1816780321
Short name T1717
Test name
Test status
Simulation time 191621528 ps
CPU time 0.84 seconds
Started Jun 21 04:58:19 PM PDT 24
Finished Jun 21 04:58:21 PM PDT 24
Peak memory 205960 kb
Host smart-17a82002-c3b1-42d8-b37b-94ff5c30724c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18167
80321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1816780321
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.584241083
Short name T857
Test name
Test status
Simulation time 153343561 ps
CPU time 0.82 seconds
Started Jun 21 04:58:18 PM PDT 24
Finished Jun 21 04:58:21 PM PDT 24
Peak memory 205952 kb
Host smart-0be7bdd4-0e87-420c-9e47-6aad021ab80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58424
1083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.584241083
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1442416133
Short name T2308
Test name
Test status
Simulation time 228790121 ps
CPU time 0.91 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:58:14 PM PDT 24
Peak memory 205968 kb
Host smart-b0656124-ac7d-4bc8-8b12-8bb02a08421a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14424
16133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1442416133
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.937167423
Short name T220
Test name
Test status
Simulation time 17935326123 ps
CPU time 126.13 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 05:00:19 PM PDT 24
Peak memory 206364 kb
Host smart-1d01a646-5f20-4b04-a9ec-5da4333b36bb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=937167423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.937167423
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.1473603958
Short name T1588
Test name
Test status
Simulation time 182128996 ps
CPU time 0.82 seconds
Started Jun 21 04:58:12 PM PDT 24
Finished Jun 21 04:58:16 PM PDT 24
Peak memory 205984 kb
Host smart-c5dcfd14-9b48-42d6-8a96-a5036be937d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14736
03958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.1473603958
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.2004283896
Short name T581
Test name
Test status
Simulation time 23291665801 ps
CPU time 22.33 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:58:36 PM PDT 24
Peak memory 206084 kb
Host smart-aa21e69c-86aa-4799-8925-0b9dea64a367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20042
83896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.2004283896
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.3979748976
Short name T2313
Test name
Test status
Simulation time 3374656680 ps
CPU time 4.26 seconds
Started Jun 21 04:58:13 PM PDT 24
Finished Jun 21 04:58:20 PM PDT 24
Peak memory 205988 kb
Host smart-5814782d-5a77-47bd-a2ef-97255e7f8210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39797
48976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.3979748976
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.3290127333
Short name T2245
Test name
Test status
Simulation time 5181342409 ps
CPU time 47.93 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:59:01 PM PDT 24
Peak memory 206268 kb
Host smart-eabb279d-180c-409b-9e2a-81f0863840be
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3290127333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.3290127333
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.2053252942
Short name T2288
Test name
Test status
Simulation time 255559744 ps
CPU time 0.93 seconds
Started Jun 21 04:58:21 PM PDT 24
Finished Jun 21 04:58:23 PM PDT 24
Peak memory 206048 kb
Host smart-cda15bfe-c0f7-4e6f-b529-2059912ac513
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2053252942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.2053252942
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.78254839
Short name T1876
Test name
Test status
Simulation time 192969274 ps
CPU time 0.86 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:58:13 PM PDT 24
Peak memory 205996 kb
Host smart-bc0ff254-0718-4c60-9e08-f17f5389d3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78254
839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.78254839
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.2495107077
Short name T570
Test name
Test status
Simulation time 5282591720 ps
CPU time 51.5 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:59:04 PM PDT 24
Peak memory 206228 kb
Host smart-1582d904-5ed8-4bf5-9d72-a89a3432bb18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24951
07077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.2495107077
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.4163025475
Short name T1216
Test name
Test status
Simulation time 5014581537 ps
CPU time 36.9 seconds
Started Jun 21 04:58:12 PM PDT 24
Finished Jun 21 04:58:52 PM PDT 24
Peak memory 206200 kb
Host smart-8c1dcde5-c657-4834-8486-98584b2c4bfd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4163025475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.4163025475
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.2896482293
Short name T2385
Test name
Test status
Simulation time 170428797 ps
CPU time 0.8 seconds
Started Jun 21 04:58:20 PM PDT 24
Finished Jun 21 04:58:22 PM PDT 24
Peak memory 205988 kb
Host smart-ae740045-d614-4aec-ac8b-1cf1dabce1f9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2896482293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.2896482293
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2485781634
Short name T656
Test name
Test status
Simulation time 210387960 ps
CPU time 0.81 seconds
Started Jun 21 04:58:14 PM PDT 24
Finished Jun 21 04:58:17 PM PDT 24
Peak memory 205992 kb
Host smart-57e40027-1bb3-4bd2-8ce9-c5dafc538ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24857
81634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2485781634
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3239619344
Short name T137
Test name
Test status
Simulation time 205760569 ps
CPU time 0.94 seconds
Started Jun 21 04:58:10 PM PDT 24
Finished Jun 21 04:58:12 PM PDT 24
Peak memory 205972 kb
Host smart-8feb3daf-007d-46cb-8e59-9ac1f6a79a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32396
19344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3239619344
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.1456822718
Short name T2343
Test name
Test status
Simulation time 157842904 ps
CPU time 0.78 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:58:14 PM PDT 24
Peak memory 205992 kb
Host smart-2aefcbaf-487c-4336-9395-fe33164b549c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14568
22718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.1456822718
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1077380799
Short name T1175
Test name
Test status
Simulation time 157754046 ps
CPU time 0.8 seconds
Started Jun 21 04:58:16 PM PDT 24
Finished Jun 21 04:58:19 PM PDT 24
Peak memory 206024 kb
Host smart-4093ac06-51a2-420b-8bb7-07fdb0a24bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10773
80799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1077380799
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3689819543
Short name T374
Test name
Test status
Simulation time 213918653 ps
CPU time 0.88 seconds
Started Jun 21 04:58:14 PM PDT 24
Finished Jun 21 04:58:17 PM PDT 24
Peak memory 205944 kb
Host smart-a49b1aba-be0c-4562-aff8-cf061d84d316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36898
19543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3689819543
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.49767057
Short name T1980
Test name
Test status
Simulation time 151205343 ps
CPU time 0.78 seconds
Started Jun 21 04:58:18 PM PDT 24
Finished Jun 21 04:58:20 PM PDT 24
Peak memory 205984 kb
Host smart-a1745474-e324-4af5-be57-d0a29e695055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49767
057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.49767057
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.613852302
Short name T939
Test name
Test status
Simulation time 273510004 ps
CPU time 0.99 seconds
Started Jun 21 04:58:14 PM PDT 24
Finished Jun 21 04:58:17 PM PDT 24
Peak memory 205948 kb
Host smart-57f47ccb-99ee-42b9-a24f-39b2e313e5c7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=613852302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.613852302
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.995763856
Short name T856
Test name
Test status
Simulation time 138759227 ps
CPU time 0.79 seconds
Started Jun 21 04:58:12 PM PDT 24
Finished Jun 21 04:58:16 PM PDT 24
Peak memory 206044 kb
Host smart-7cc8e7e1-c57d-4780-ab5e-b4ddaa59b4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99576
3856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.995763856
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.310799869
Short name T1348
Test name
Test status
Simulation time 40392786 ps
CPU time 0.67 seconds
Started Jun 21 04:58:20 PM PDT 24
Finished Jun 21 04:58:22 PM PDT 24
Peak memory 205980 kb
Host smart-ea61a1a4-9bf3-4590-b51c-6ea37635c4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31079
9869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.310799869
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.4231239392
Short name T177
Test name
Test status
Simulation time 19238728429 ps
CPU time 45.37 seconds
Started Jun 21 04:58:12 PM PDT 24
Finished Jun 21 04:59:01 PM PDT 24
Peak memory 214572 kb
Host smart-11d7b7f0-c667-4ea3-90bc-5df291f4c166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42312
39392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.4231239392
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.4163663345
Short name T400
Test name
Test status
Simulation time 202837803 ps
CPU time 0.89 seconds
Started Jun 21 04:58:12 PM PDT 24
Finished Jun 21 04:58:16 PM PDT 24
Peak memory 205952 kb
Host smart-86b511de-a90d-4695-a576-629590723ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41636
63345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.4163663345
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.747509381
Short name T788
Test name
Test status
Simulation time 191927895 ps
CPU time 0.85 seconds
Started Jun 21 04:58:12 PM PDT 24
Finished Jun 21 04:58:16 PM PDT 24
Peak memory 205964 kb
Host smart-a09300f0-c2d6-4862-8186-90432502662d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74750
9381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.747509381
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.3374694978
Short name T2172
Test name
Test status
Simulation time 177304168 ps
CPU time 0.82 seconds
Started Jun 21 04:58:18 PM PDT 24
Finished Jun 21 04:58:20 PM PDT 24
Peak memory 206008 kb
Host smart-2f829909-6635-45f0-ae1c-1ec8aba6c9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33746
94978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.3374694978
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.3502176836
Short name T467
Test name
Test status
Simulation time 174182870 ps
CPU time 0.82 seconds
Started Jun 21 04:58:12 PM PDT 24
Finished Jun 21 04:58:16 PM PDT 24
Peak memory 205992 kb
Host smart-495974b8-4fe1-4b5f-9016-e1cbd9ebcc80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35021
76836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.3502176836
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.56268945
Short name T1007
Test name
Test status
Simulation time 205266710 ps
CPU time 0.85 seconds
Started Jun 21 04:58:12 PM PDT 24
Finished Jun 21 04:58:16 PM PDT 24
Peak memory 205988 kb
Host smart-713e9d87-a5d0-4f74-a56d-84f1ade8b749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56268
945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.56268945
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.159447348
Short name T439
Test name
Test status
Simulation time 158581762 ps
CPU time 0.8 seconds
Started Jun 21 04:58:16 PM PDT 24
Finished Jun 21 04:58:19 PM PDT 24
Peak memory 205964 kb
Host smart-ccc4ff39-a0ec-4b7b-bff7-df8a98aafbe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15944
7348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.159447348
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.958317893
Short name T2168
Test name
Test status
Simulation time 161321369 ps
CPU time 0.75 seconds
Started Jun 21 04:58:14 PM PDT 24
Finished Jun 21 04:58:17 PM PDT 24
Peak memory 205980 kb
Host smart-57a26dd0-35e1-472b-b60c-e4daf7638902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95831
7893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.958317893
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.257758034
Short name T1892
Test name
Test status
Simulation time 182399576 ps
CPU time 0.85 seconds
Started Jun 21 04:58:11 PM PDT 24
Finished Jun 21 04:58:15 PM PDT 24
Peak memory 205928 kb
Host smart-0a5f19f0-6737-449e-a521-86552462cab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25775
8034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.257758034
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.34495884
Short name T1120
Test name
Test status
Simulation time 12070506807 ps
CPU time 86.1 seconds
Started Jun 21 04:58:14 PM PDT 24
Finished Jun 21 04:59:43 PM PDT 24
Peak memory 206204 kb
Host smart-2f5c646c-7096-4b4c-b30d-26a9d38e9745
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=34495884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.34495884
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1143208682
Short name T538
Test name
Test status
Simulation time 160844665 ps
CPU time 0.75 seconds
Started Jun 21 04:58:13 PM PDT 24
Finished Jun 21 04:58:16 PM PDT 24
Peak memory 205976 kb
Host smart-d248726e-dedb-4f5a-822b-92a236626b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11432
08682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1143208682
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.3097938658
Short name T425
Test name
Test status
Simulation time 205224884 ps
CPU time 0.86 seconds
Started Jun 21 04:58:16 PM PDT 24
Finished Jun 21 04:58:18 PM PDT 24
Peak memory 205936 kb
Host smart-7d76b0f3-3827-4fe7-b5c6-228985b8b82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30979
38658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.3097938658
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1757681741
Short name T1733
Test name
Test status
Simulation time 8657628715 ps
CPU time 238.73 seconds
Started Jun 21 04:58:13 PM PDT 24
Finished Jun 21 05:02:14 PM PDT 24
Peak memory 206300 kb
Host smart-bf7907e7-a8e6-4508-bf7e-50aeccffeed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17576
81741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1757681741
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.3213921872
Short name T2061
Test name
Test status
Simulation time 4144079051 ps
CPU time 4.61 seconds
Started Jun 21 04:58:21 PM PDT 24
Finished Jun 21 04:58:27 PM PDT 24
Peak memory 206276 kb
Host smart-e4c1ff61-b504-42de-bbf3-4477adceb260
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3213921872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.3213921872
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.499712543
Short name T499
Test name
Test status
Simulation time 13345546778 ps
CPU time 13.9 seconds
Started Jun 21 04:58:21 PM PDT 24
Finished Jun 21 04:58:36 PM PDT 24
Peak memory 206036 kb
Host smart-ce9508d1-35c5-4419-a212-ca08fa60533b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=499712543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.499712543
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.1125867097
Short name T999
Test name
Test status
Simulation time 23379520983 ps
CPU time 23.07 seconds
Started Jun 21 04:58:18 PM PDT 24
Finished Jun 21 04:58:42 PM PDT 24
Peak memory 206088 kb
Host smart-1d5d97c4-1436-49e4-97b7-159ec28c4a13
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1125867097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.1125867097
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2589751474
Short name T605
Test name
Test status
Simulation time 158635460 ps
CPU time 0.91 seconds
Started Jun 21 04:58:24 PM PDT 24
Finished Jun 21 04:58:25 PM PDT 24
Peak memory 206020 kb
Host smart-ec26be63-7aef-4a65-90f5-6d4b5d928d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25897
51474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2589751474
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3965018497
Short name T1817
Test name
Test status
Simulation time 167277719 ps
CPU time 0.85 seconds
Started Jun 21 04:58:21 PM PDT 24
Finished Jun 21 04:58:23 PM PDT 24
Peak memory 205924 kb
Host smart-e5aaac33-17d5-440d-9978-775fe1b8d985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39650
18497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3965018497
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.3414452774
Short name T185
Test name
Test status
Simulation time 310379322 ps
CPU time 1.05 seconds
Started Jun 21 04:58:18 PM PDT 24
Finished Jun 21 04:58:20 PM PDT 24
Peak memory 206020 kb
Host smart-70cc7480-204d-4471-a0c6-54e25499894c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34144
52774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.3414452774
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.3393982918
Short name T2225
Test name
Test status
Simulation time 697990284 ps
CPU time 1.98 seconds
Started Jun 21 04:58:19 PM PDT 24
Finished Jun 21 04:58:23 PM PDT 24
Peak memory 206256 kb
Host smart-8aa95ba4-6a32-405d-8055-7848d17e28ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33939
82918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.3393982918
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.3676770477
Short name T2273
Test name
Test status
Simulation time 21108978658 ps
CPU time 38.71 seconds
Started Jun 21 04:58:18 PM PDT 24
Finished Jun 21 04:58:58 PM PDT 24
Peak memory 206164 kb
Host smart-0e90d270-ea7d-42df-af78-0f7e5bfcb0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36767
70477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.3676770477
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.314077917
Short name T1602
Test name
Test status
Simulation time 410118334 ps
CPU time 1.27 seconds
Started Jun 21 04:58:18 PM PDT 24
Finished Jun 21 04:58:20 PM PDT 24
Peak memory 206028 kb
Host smart-127756f0-d4ef-4c23-95b6-a3c51894414f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31407
7917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.314077917
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.3576737696
Short name T1703
Test name
Test status
Simulation time 165040119 ps
CPU time 0.77 seconds
Started Jun 21 04:58:19 PM PDT 24
Finished Jun 21 04:58:21 PM PDT 24
Peak memory 205928 kb
Host smart-f68c7f05-dc81-4e4f-a6cd-e4933847a295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35767
37696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.3576737696
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.2616158066
Short name T709
Test name
Test status
Simulation time 76402889 ps
CPU time 0.69 seconds
Started Jun 21 04:58:23 PM PDT 24
Finished Jun 21 04:58:25 PM PDT 24
Peak memory 205964 kb
Host smart-38a785fd-93ae-498d-9a61-68204c848362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26161
58066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.2616158066
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1714570807
Short name T770
Test name
Test status
Simulation time 890894502 ps
CPU time 2.12 seconds
Started Jun 21 04:58:19 PM PDT 24
Finished Jun 21 04:58:22 PM PDT 24
Peak memory 206188 kb
Host smart-8942dfd8-4000-4688-a73e-adeb6e4257cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17145
70807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1714570807
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1690284028
Short name T1364
Test name
Test status
Simulation time 297786266 ps
CPU time 2.18 seconds
Started Jun 21 04:58:21 PM PDT 24
Finished Jun 21 04:58:25 PM PDT 24
Peak memory 206172 kb
Host smart-00f871ff-7f2b-4d16-83cc-ce10a2908296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16902
84028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1690284028
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.4267759067
Short name T1867
Test name
Test status
Simulation time 185254332 ps
CPU time 0.89 seconds
Started Jun 21 04:58:26 PM PDT 24
Finished Jun 21 04:58:28 PM PDT 24
Peak memory 206020 kb
Host smart-5bb34445-c3d7-4a9d-8c1c-5ee862a69399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42677
59067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.4267759067
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.373736014
Short name T2483
Test name
Test status
Simulation time 143578604 ps
CPU time 0.75 seconds
Started Jun 21 04:58:31 PM PDT 24
Finished Jun 21 04:58:34 PM PDT 24
Peak memory 206020 kb
Host smart-ebf44765-8132-4712-9350-f60187adaed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37373
6014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.373736014
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3407630641
Short name T377
Test name
Test status
Simulation time 197143863 ps
CPU time 0.89 seconds
Started Jun 21 04:58:18 PM PDT 24
Finished Jun 21 04:58:20 PM PDT 24
Peak memory 205936 kb
Host smart-ecd6075f-8af2-4b90-a514-c86f6e40107f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34076
30641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3407630641
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2546553700
Short name T2137
Test name
Test status
Simulation time 191099721 ps
CPU time 0.86 seconds
Started Jun 21 04:58:18 PM PDT 24
Finished Jun 21 04:58:20 PM PDT 24
Peak memory 205960 kb
Host smart-a7c95ee5-61c6-4ec7-9495-37f8dd8d2a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25465
53700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2546553700
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.1244412437
Short name T355
Test name
Test status
Simulation time 23345841156 ps
CPU time 24.1 seconds
Started Jun 21 04:58:19 PM PDT 24
Finished Jun 21 04:58:45 PM PDT 24
Peak memory 206080 kb
Host smart-4afcc02a-12fc-4ff3-9aab-0e5fae05c5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12444
12437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.1244412437
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.1507765487
Short name T638
Test name
Test status
Simulation time 3380666502 ps
CPU time 4.16 seconds
Started Jun 21 04:58:18 PM PDT 24
Finished Jun 21 04:58:23 PM PDT 24
Peak memory 206112 kb
Host smart-77ea512d-1ed9-40d3-ae77-771fd49ad584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15077
65487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1507765487
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3939666195
Short name T1442
Test name
Test status
Simulation time 7141697904 ps
CPU time 70.92 seconds
Started Jun 21 04:58:27 PM PDT 24
Finished Jun 21 04:59:39 PM PDT 24
Peak memory 206272 kb
Host smart-5e6b5bdb-b0e1-4b3c-a47d-fb3e3ae92ad6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3939666195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3939666195
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.1416593057
Short name T310
Test name
Test status
Simulation time 250603664 ps
CPU time 0.94 seconds
Started Jun 21 04:58:31 PM PDT 24
Finished Jun 21 04:58:34 PM PDT 24
Peak memory 205984 kb
Host smart-7398bb90-baed-4396-b63a-a61e25613a49
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1416593057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.1416593057
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3983906265
Short name T1635
Test name
Test status
Simulation time 267976864 ps
CPU time 0.91 seconds
Started Jun 21 04:58:19 PM PDT 24
Finished Jun 21 04:58:21 PM PDT 24
Peak memory 206032 kb
Host smart-a96c0a55-d78e-4d9f-ad0f-99da2a42903b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39839
06265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3983906265
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2783777738
Short name T2035
Test name
Test status
Simulation time 9334775400 ps
CPU time 268 seconds
Started Jun 21 04:58:27 PM PDT 24
Finished Jun 21 05:02:56 PM PDT 24
Peak memory 206188 kb
Host smart-355eae12-02c5-4c7a-bfe3-4ee190e53374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27837
77738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2783777738
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.1279172992
Short name T1164
Test name
Test status
Simulation time 4449116604 ps
CPU time 123.98 seconds
Started Jun 21 04:58:30 PM PDT 24
Finished Jun 21 05:00:36 PM PDT 24
Peak memory 206272 kb
Host smart-2f1a2808-c5d5-42f9-a69d-a73cb41e9a82
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1279172992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.1279172992
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.546994978
Short name T1771
Test name
Test status
Simulation time 153627471 ps
CPU time 0.78 seconds
Started Jun 21 04:58:31 PM PDT 24
Finished Jun 21 04:58:34 PM PDT 24
Peak memory 205988 kb
Host smart-3ec14ee2-824a-4508-9e27-2c91b1628d84
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=546994978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.546994978
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.282091611
Short name T435
Test name
Test status
Simulation time 177322984 ps
CPU time 0.8 seconds
Started Jun 21 04:58:28 PM PDT 24
Finished Jun 21 04:58:30 PM PDT 24
Peak memory 205992 kb
Host smart-3d932b1a-b164-44ac-a637-f37b15642cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28209
1611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.282091611
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1234922519
Short name T143
Test name
Test status
Simulation time 235437135 ps
CPU time 0.88 seconds
Started Jun 21 04:58:25 PM PDT 24
Finished Jun 21 04:58:27 PM PDT 24
Peak memory 205968 kb
Host smart-cfe526ca-17b3-4d2a-8290-523d2047f63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12349
22519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1234922519
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.2918463628
Short name T686
Test name
Test status
Simulation time 158857951 ps
CPU time 0.86 seconds
Started Jun 21 04:58:30 PM PDT 24
Finished Jun 21 04:58:33 PM PDT 24
Peak memory 206020 kb
Host smart-e056ab15-e689-4260-a62e-f7ca3ea9f4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29184
63628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.2918463628
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3166900428
Short name T315
Test name
Test status
Simulation time 197316830 ps
CPU time 0.83 seconds
Started Jun 21 04:58:28 PM PDT 24
Finished Jun 21 04:58:30 PM PDT 24
Peak memory 205932 kb
Host smart-3421bc33-5e32-41b8-b601-63ff86604ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31669
00428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3166900428
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.4052233606
Short name T1884
Test name
Test status
Simulation time 143002884 ps
CPU time 0.81 seconds
Started Jun 21 04:58:28 PM PDT 24
Finished Jun 21 04:58:30 PM PDT 24
Peak memory 205984 kb
Host smart-21329769-94d2-4175-95cd-b64071f0feb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40522
33606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.4052233606
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1711831193
Short name T1418
Test name
Test status
Simulation time 173709440 ps
CPU time 0.82 seconds
Started Jun 21 04:58:27 PM PDT 24
Finished Jun 21 04:58:29 PM PDT 24
Peak memory 206004 kb
Host smart-4c08cf7f-a689-4f98-a760-76b7532b0b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17118
31193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1711831193
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.1777764731
Short name T2429
Test name
Test status
Simulation time 218012422 ps
CPU time 0.9 seconds
Started Jun 21 04:58:30 PM PDT 24
Finished Jun 21 04:58:33 PM PDT 24
Peak memory 205948 kb
Host smart-f6ef1628-2723-4213-82c9-a685190a182e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1777764731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.1777764731
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3349993609
Short name T194
Test name
Test status
Simulation time 163459803 ps
CPU time 0.73 seconds
Started Jun 21 04:58:31 PM PDT 24
Finished Jun 21 04:58:33 PM PDT 24
Peak memory 205964 kb
Host smart-f01b59cc-3c13-488f-9ab0-9864b243719f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33499
93609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3349993609
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.734441025
Short name T2018
Test name
Test status
Simulation time 31711621 ps
CPU time 0.66 seconds
Started Jun 21 04:58:25 PM PDT 24
Finished Jun 21 04:58:27 PM PDT 24
Peak memory 206032 kb
Host smart-e8bf73bd-4c7d-4342-baf0-58cf07778445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73444
1025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.734441025
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1025955530
Short name T624
Test name
Test status
Simulation time 16969574259 ps
CPU time 37.91 seconds
Started Jun 21 04:58:27 PM PDT 24
Finished Jun 21 04:59:06 PM PDT 24
Peak memory 206256 kb
Host smart-6cfe1cad-a31a-48af-b117-4966973f56e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10259
55530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1025955530
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2757402829
Short name T558
Test name
Test status
Simulation time 183849089 ps
CPU time 0.89 seconds
Started Jun 21 04:58:32 PM PDT 24
Finished Jun 21 04:58:35 PM PDT 24
Peak memory 206028 kb
Host smart-fc08da40-b290-43f3-a6af-8303c6972e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27574
02829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2757402829
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2062178431
Short name T2230
Test name
Test status
Simulation time 273997593 ps
CPU time 0.94 seconds
Started Jun 21 04:58:29 PM PDT 24
Finished Jun 21 04:58:32 PM PDT 24
Peak memory 206024 kb
Host smart-98e54108-99b9-473c-86da-dd9be38a865d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20621
78431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2062178431
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.4137361729
Short name T998
Test name
Test status
Simulation time 199032401 ps
CPU time 0.85 seconds
Started Jun 21 04:58:30 PM PDT 24
Finished Jun 21 04:58:32 PM PDT 24
Peak memory 206028 kb
Host smart-16efe8d2-4c76-4e71-9638-d0c6154f3e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41373
61729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.4137361729
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3099308486
Short name T640
Test name
Test status
Simulation time 181861711 ps
CPU time 0.86 seconds
Started Jun 21 04:58:29 PM PDT 24
Finished Jun 21 04:58:32 PM PDT 24
Peak memory 206004 kb
Host smart-f93e01bd-a9eb-4b38-93c1-1e00e07ecfb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30993
08486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3099308486
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3091689170
Short name T444
Test name
Test status
Simulation time 175202460 ps
CPU time 0.82 seconds
Started Jun 21 04:58:26 PM PDT 24
Finished Jun 21 04:58:28 PM PDT 24
Peak memory 206028 kb
Host smart-ed61a321-cd51-4ee9-ad14-0b06a69ea514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30916
89170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3091689170
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.4015454458
Short name T401
Test name
Test status
Simulation time 160292111 ps
CPU time 0.81 seconds
Started Jun 21 04:58:28 PM PDT 24
Finished Jun 21 04:58:31 PM PDT 24
Peak memory 205960 kb
Host smart-100c7192-f9e4-477e-89ac-a5d34ff35309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40154
54458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.4015454458
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1833439094
Short name T1567
Test name
Test status
Simulation time 153570094 ps
CPU time 0.8 seconds
Started Jun 21 04:58:27 PM PDT 24
Finished Jun 21 04:58:29 PM PDT 24
Peak memory 206004 kb
Host smart-8695bd9a-74c4-4db5-bb6e-353c1bd82058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18334
39094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1833439094
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2337298734
Short name T1229
Test name
Test status
Simulation time 252218103 ps
CPU time 1.05 seconds
Started Jun 21 04:58:20 PM PDT 24
Finished Jun 21 04:58:22 PM PDT 24
Peak memory 205956 kb
Host smart-dde05631-cc07-43df-976c-b883f6601be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23372
98734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2337298734
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.4034066533
Short name T702
Test name
Test status
Simulation time 8978661199 ps
CPU time 253.87 seconds
Started Jun 21 04:58:30 PM PDT 24
Finished Jun 21 05:02:45 PM PDT 24
Peak memory 206160 kb
Host smart-49bf4c58-9469-4213-8d19-91c94b3c485a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4034066533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.4034066533
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3278622107
Short name T839
Test name
Test status
Simulation time 183408863 ps
CPU time 0.89 seconds
Started Jun 21 04:58:26 PM PDT 24
Finished Jun 21 04:58:27 PM PDT 24
Peak memory 206036 kb
Host smart-02d7d526-9f69-494a-80dd-a06b1be0adf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32786
22107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3278622107
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.3398735620
Short name T2359
Test name
Test status
Simulation time 181581881 ps
CPU time 0.81 seconds
Started Jun 21 04:58:29 PM PDT 24
Finished Jun 21 04:58:32 PM PDT 24
Peak memory 206000 kb
Host smart-0595955a-bd38-48ce-924b-e69b62bcbe94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33987
35620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.3398735620
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3869079381
Short name T1163
Test name
Test status
Simulation time 10497692394 ps
CPU time 294.37 seconds
Started Jun 21 04:58:30 PM PDT 24
Finished Jun 21 05:03:27 PM PDT 24
Peak memory 206252 kb
Host smart-4664c1c3-3442-404a-9e41-4d195a475339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38690
79381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3869079381
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1513142964
Short name T1778
Test name
Test status
Simulation time 3614316579 ps
CPU time 5.11 seconds
Started Jun 21 04:58:26 PM PDT 24
Finished Jun 21 04:58:32 PM PDT 24
Peak memory 206316 kb
Host smart-5d1a13fc-6038-4533-888b-b18646336dd5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1513142964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1513142964
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.555951259
Short name T1612
Test name
Test status
Simulation time 13361164438 ps
CPU time 11.95 seconds
Started Jun 21 04:58:27 PM PDT 24
Finished Jun 21 04:58:40 PM PDT 24
Peak memory 206152 kb
Host smart-723f1e03-a7fa-4e7d-8a7c-b809d6ba9e44
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=555951259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.555951259
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.393836799
Short name T643
Test name
Test status
Simulation time 23347555500 ps
CPU time 21.24 seconds
Started Jun 21 04:58:26 PM PDT 24
Finished Jun 21 04:58:49 PM PDT 24
Peak memory 206196 kb
Host smart-041d92bb-badf-4a54-b346-5ea5d4bb8f13
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=393836799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.393836799
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2759794780
Short name T1758
Test name
Test status
Simulation time 202257116 ps
CPU time 0.91 seconds
Started Jun 21 04:58:26 PM PDT 24
Finished Jun 21 04:58:28 PM PDT 24
Peak memory 205968 kb
Host smart-6d0b78a0-1d7e-4c2c-a493-daa9615c1026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27597
94780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2759794780
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.761955585
Short name T23
Test name
Test status
Simulation time 149341676 ps
CPU time 0.74 seconds
Started Jun 21 04:58:25 PM PDT 24
Finished Jun 21 04:58:27 PM PDT 24
Peak memory 205964 kb
Host smart-3c233444-90d7-4429-a7f3-68f554653895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76195
5585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.761955585
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.838661660
Short name T1688
Test name
Test status
Simulation time 187214183 ps
CPU time 0.87 seconds
Started Jun 21 04:58:30 PM PDT 24
Finished Jun 21 04:58:32 PM PDT 24
Peak memory 205968 kb
Host smart-4ae0a453-1774-4d8f-baad-e654ec93f7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83866
1660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.838661660
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.1792423218
Short name T902
Test name
Test status
Simulation time 511314545 ps
CPU time 1.47 seconds
Started Jun 21 04:58:25 PM PDT 24
Finished Jun 21 04:58:27 PM PDT 24
Peak memory 205936 kb
Host smart-a38d4287-68bb-4834-8a17-32c849db2383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17924
23218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.1792423218
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.1603289518
Short name T91
Test name
Test status
Simulation time 15515980015 ps
CPU time 28.88 seconds
Started Jun 21 04:58:28 PM PDT 24
Finished Jun 21 04:58:58 PM PDT 24
Peak memory 206268 kb
Host smart-f60dfd41-dd60-4874-a3cc-35ca8c429fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16032
89518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.1603289518
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.586776196
Short name T1520
Test name
Test status
Simulation time 467872712 ps
CPU time 1.38 seconds
Started Jun 21 04:58:27 PM PDT 24
Finished Jun 21 04:58:29 PM PDT 24
Peak memory 205964 kb
Host smart-7de1d615-4829-477b-be1c-221bab0d520f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58677
6196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.586776196
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.1403611946
Short name T1950
Test name
Test status
Simulation time 160624640 ps
CPU time 0.78 seconds
Started Jun 21 04:58:28 PM PDT 24
Finished Jun 21 04:58:30 PM PDT 24
Peak memory 206028 kb
Host smart-0f08ef2b-a6ff-48e9-9cc2-06669cbe7da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14036
11946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1403611946
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.3604174313
Short name T1489
Test name
Test status
Simulation time 80232393 ps
CPU time 0.77 seconds
Started Jun 21 04:58:31 PM PDT 24
Finished Jun 21 04:58:34 PM PDT 24
Peak memory 205916 kb
Host smart-2a9d6b33-4925-4a4d-a158-216f5ef704ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36041
74313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3604174313
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.1100718255
Short name T1647
Test name
Test status
Simulation time 992368945 ps
CPU time 2.59 seconds
Started Jun 21 04:58:29 PM PDT 24
Finished Jun 21 04:58:33 PM PDT 24
Peak memory 206136 kb
Host smart-52d7273c-db5a-4821-854f-dddb22cd1927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11007
18255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.1100718255
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3400441952
Short name T1205
Test name
Test status
Simulation time 184879244 ps
CPU time 1.27 seconds
Started Jun 21 04:58:31 PM PDT 24
Finished Jun 21 04:58:34 PM PDT 24
Peak memory 206256 kb
Host smart-f3e9b358-bf43-46c5-9625-f402e9627458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34004
41952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3400441952
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.2129558493
Short name T1272
Test name
Test status
Simulation time 163873800 ps
CPU time 0.85 seconds
Started Jun 21 04:58:38 PM PDT 24
Finished Jun 21 04:58:41 PM PDT 24
Peak memory 205968 kb
Host smart-feac78df-1bb6-493b-8ab7-0cc983cd8a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21295
58493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2129558493
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.3358046771
Short name T80
Test name
Test status
Simulation time 141747942 ps
CPU time 0.78 seconds
Started Jun 21 04:58:38 PM PDT 24
Finished Jun 21 04:58:41 PM PDT 24
Peak memory 206016 kb
Host smart-4892ba5d-9bc8-4540-aef2-3d6e9d862d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33580
46771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3358046771
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.2241511477
Short name T1488
Test name
Test status
Simulation time 281558063 ps
CPU time 0.92 seconds
Started Jun 21 04:58:27 PM PDT 24
Finished Jun 21 04:58:29 PM PDT 24
Peak memory 206024 kb
Host smart-aba6d8b2-1f63-4088-9154-6caf562aa120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22415
11477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2241511477
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.4107871313
Short name T1235
Test name
Test status
Simulation time 203516991 ps
CPU time 0.87 seconds
Started Jun 21 04:58:30 PM PDT 24
Finished Jun 21 04:58:32 PM PDT 24
Peak memory 205944 kb
Host smart-29323a82-fa35-4805-86ab-d73c02c555be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41078
71313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.4107871313
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.3479186667
Short name T1565
Test name
Test status
Simulation time 23341622914 ps
CPU time 21.29 seconds
Started Jun 21 04:58:31 PM PDT 24
Finished Jun 21 04:58:55 PM PDT 24
Peak memory 205988 kb
Host smart-f31bc18b-b656-4213-81eb-63067dd03283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34791
86667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.3479186667
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.31236131
Short name T1956
Test name
Test status
Simulation time 3325938302 ps
CPU time 3.54 seconds
Started Jun 21 04:58:24 PM PDT 24
Finished Jun 21 04:58:28 PM PDT 24
Peak memory 206092 kb
Host smart-3ba49ef9-17d2-44f7-97b7-ec993e8d2af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31236
131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.31236131
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.4179215758
Short name T152
Test name
Test status
Simulation time 6143118038 ps
CPU time 170.79 seconds
Started Jun 21 04:58:26 PM PDT 24
Finished Jun 21 05:01:17 PM PDT 24
Peak memory 206288 kb
Host smart-756c0759-4e82-430f-8797-1f205a2af62a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4179215758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.4179215758
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.491725928
Short name T845
Test name
Test status
Simulation time 244684313 ps
CPU time 0.92 seconds
Started Jun 21 04:58:40 PM PDT 24
Finished Jun 21 04:58:43 PM PDT 24
Peak memory 205948 kb
Host smart-574b68e6-f3c4-4854-af66-b3dffddef41e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=491725928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.491725928
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2303326718
Short name T1851
Test name
Test status
Simulation time 208084848 ps
CPU time 0.89 seconds
Started Jun 21 04:58:28 PM PDT 24
Finished Jun 21 04:58:31 PM PDT 24
Peak memory 205936 kb
Host smart-6ad2f756-45b2-420b-a880-54e853ef780d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23033
26718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2303326718
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.2590186003
Short name T1942
Test name
Test status
Simulation time 8686052281 ps
CPU time 232.91 seconds
Started Jun 21 04:58:29 PM PDT 24
Finished Jun 21 05:02:24 PM PDT 24
Peak memory 206220 kb
Host smart-48032014-ec9a-4743-9ac1-1e93212c42d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25901
86003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.2590186003
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.973274346
Short name T1400
Test name
Test status
Simulation time 15395615234 ps
CPU time 106.23 seconds
Started Jun 21 04:58:31 PM PDT 24
Finished Jun 21 05:00:19 PM PDT 24
Peak memory 206296 kb
Host smart-ef5970ec-8706-4d30-b026-5f247bae3f36
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=973274346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.973274346
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.331916519
Short name T1800
Test name
Test status
Simulation time 150823506 ps
CPU time 0.81 seconds
Started Jun 21 04:58:40 PM PDT 24
Finished Jun 21 04:58:43 PM PDT 24
Peak memory 205996 kb
Host smart-5490050e-7f45-4c35-b388-0b47ecb1cfa0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=331916519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.331916519
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1826676274
Short name T611
Test name
Test status
Simulation time 140405188 ps
CPU time 0.83 seconds
Started Jun 21 04:58:28 PM PDT 24
Finished Jun 21 04:58:30 PM PDT 24
Peak memory 205980 kb
Host smart-d85dc7bb-e8f8-4225-8ca4-f0ba4338d840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18266
76274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1826676274
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3671642891
Short name T117
Test name
Test status
Simulation time 189123799 ps
CPU time 0.86 seconds
Started Jun 21 04:58:34 PM PDT 24
Finished Jun 21 04:58:36 PM PDT 24
Peak memory 206020 kb
Host smart-d54d249a-9b0e-4d71-ab81-01bbf94b38ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36716
42891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3671642891
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.2291677321
Short name T1398
Test name
Test status
Simulation time 157241033 ps
CPU time 0.82 seconds
Started Jun 21 04:58:38 PM PDT 24
Finished Jun 21 04:58:41 PM PDT 24
Peak memory 205968 kb
Host smart-e1d0ec74-fc1e-428c-b763-2287c36486d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22916
77321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2291677321
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.758799648
Short name T1691
Test name
Test status
Simulation time 183181920 ps
CPU time 0.75 seconds
Started Jun 21 04:58:39 PM PDT 24
Finished Jun 21 04:58:42 PM PDT 24
Peak memory 206020 kb
Host smart-9b714985-742c-4b96-83c7-20e6d4aef9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75879
9648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.758799648
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.475903469
Short name T597
Test name
Test status
Simulation time 158977413 ps
CPU time 0.83 seconds
Started Jun 21 04:58:38 PM PDT 24
Finished Jun 21 04:58:41 PM PDT 24
Peak memory 205960 kb
Host smart-c6ab0372-2ca6-494e-b300-fe6a0c298f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47590
3469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.475903469
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2902580345
Short name T690
Test name
Test status
Simulation time 166991604 ps
CPU time 0.8 seconds
Started Jun 21 04:58:41 PM PDT 24
Finished Jun 21 04:58:44 PM PDT 24
Peak memory 206020 kb
Host smart-b77c48c7-6aa9-4360-b5b0-e6c08ed2c401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29025
80345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2902580345
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.2441709161
Short name T973
Test name
Test status
Simulation time 248818618 ps
CPU time 0.95 seconds
Started Jun 21 04:58:39 PM PDT 24
Finished Jun 21 04:58:43 PM PDT 24
Peak memory 206040 kb
Host smart-ff9dbd8a-ef15-457b-8a70-6e4e5d797ae5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2441709161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.2441709161
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1230010244
Short name T1871
Test name
Test status
Simulation time 143197537 ps
CPU time 0.78 seconds
Started Jun 21 04:58:36 PM PDT 24
Finished Jun 21 04:58:37 PM PDT 24
Peak memory 206032 kb
Host smart-046db9d9-a946-4c95-9db8-b5c19ee90efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12300
10244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1230010244
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2303605526
Short name T2312
Test name
Test status
Simulation time 43957853 ps
CPU time 0.71 seconds
Started Jun 21 04:58:40 PM PDT 24
Finished Jun 21 04:58:43 PM PDT 24
Peak memory 206032 kb
Host smart-68f9b7ea-ccad-4f73-a072-6c9c9569fd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23036
05526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2303605526
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.941220967
Short name T965
Test name
Test status
Simulation time 18303634891 ps
CPU time 39.19 seconds
Started Jun 21 04:58:37 PM PDT 24
Finished Jun 21 04:59:18 PM PDT 24
Peak memory 206356 kb
Host smart-7e4086b9-70a7-45aa-bb98-8b0879bfaa47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94122
0967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.941220967
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.2108806082
Short name T1449
Test name
Test status
Simulation time 175219317 ps
CPU time 0.84 seconds
Started Jun 21 04:58:36 PM PDT 24
Finished Jun 21 04:58:38 PM PDT 24
Peak memory 206004 kb
Host smart-4437e583-f51d-48d1-8f7a-d5fe95d38c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21088
06082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2108806082
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.739710604
Short name T1328
Test name
Test status
Simulation time 185190764 ps
CPU time 0.84 seconds
Started Jun 21 04:58:40 PM PDT 24
Finished Jun 21 04:58:43 PM PDT 24
Peak memory 205920 kb
Host smart-a9eb617a-fb35-448c-8826-456d0b65659a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73971
0604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.739710604
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.742022736
Short name T660
Test name
Test status
Simulation time 215902800 ps
CPU time 0.92 seconds
Started Jun 21 04:58:38 PM PDT 24
Finished Jun 21 04:58:41 PM PDT 24
Peak memory 205964 kb
Host smart-4b084555-68a6-4e26-b000-fe5997b635b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74202
2736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.742022736
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.3486894583
Short name T773
Test name
Test status
Simulation time 175520178 ps
CPU time 0.82 seconds
Started Jun 21 04:58:36 PM PDT 24
Finished Jun 21 04:58:39 PM PDT 24
Peak memory 206048 kb
Host smart-75b4fe7f-7660-45b6-9d44-498dd7ee54cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34868
94583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.3486894583
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.1084167549
Short name T823
Test name
Test status
Simulation time 168915188 ps
CPU time 0.77 seconds
Started Jun 21 04:58:35 PM PDT 24
Finished Jun 21 04:58:36 PM PDT 24
Peak memory 205964 kb
Host smart-171bead8-4aa6-425f-b91b-7b90d88a5860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10841
67549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.1084167549
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2002075443
Short name T1580
Test name
Test status
Simulation time 150839184 ps
CPU time 0.8 seconds
Started Jun 21 04:58:39 PM PDT 24
Finished Jun 21 04:58:41 PM PDT 24
Peak memory 205956 kb
Host smart-99d4eaa4-cad5-43ad-b8fe-fcd05e821137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20020
75443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2002075443
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2764752271
Short name T2144
Test name
Test status
Simulation time 161755475 ps
CPU time 0.81 seconds
Started Jun 21 04:58:42 PM PDT 24
Finished Jun 21 04:58:44 PM PDT 24
Peak memory 205964 kb
Host smart-4fb329bb-16cb-4f3f-95cc-43225fcc7d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27647
52271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2764752271
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2477027752
Short name T2037
Test name
Test status
Simulation time 222975705 ps
CPU time 1.04 seconds
Started Jun 21 04:58:29 PM PDT 24
Finished Jun 21 04:58:31 PM PDT 24
Peak memory 205976 kb
Host smart-b098f2d2-3ab4-4e30-b0ee-bf330d6d3618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24770
27752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2477027752
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.730771941
Short name T2457
Test name
Test status
Simulation time 11382055977 ps
CPU time 77.53 seconds
Started Jun 21 04:58:36 PM PDT 24
Finished Jun 21 04:59:55 PM PDT 24
Peak memory 206280 kb
Host smart-1f51c83d-f27c-423c-8e9f-c7cbc549f61f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=730771941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.730771941
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.499234619
Short name T543
Test name
Test status
Simulation time 160647591 ps
CPU time 0.81 seconds
Started Jun 21 04:58:37 PM PDT 24
Finished Jun 21 04:58:39 PM PDT 24
Peak memory 206004 kb
Host smart-8e4c62a4-9374-42ac-a70e-1cdef9fd8925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49923
4619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.499234619
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2657981341
Short name T2323
Test name
Test status
Simulation time 184648494 ps
CPU time 0.89 seconds
Started Jun 21 04:58:36 PM PDT 24
Finished Jun 21 04:58:39 PM PDT 24
Peak memory 206144 kb
Host smart-c5c780c3-2122-4714-8c82-d297fb335166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26579
81341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2657981341
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.1471339296
Short name T1468
Test name
Test status
Simulation time 10589743242 ps
CPU time 281.21 seconds
Started Jun 21 04:58:42 PM PDT 24
Finished Jun 21 05:03:25 PM PDT 24
Peak memory 206184 kb
Host smart-ebd8211c-f8b7-44bf-be08-87be64456e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14713
39296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.1471339296
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.4089691144
Short name T739
Test name
Test status
Simulation time 3442977050 ps
CPU time 4.29 seconds
Started Jun 21 04:54:00 PM PDT 24
Finished Jun 21 04:54:05 PM PDT 24
Peak memory 206236 kb
Host smart-49e5f417-8d6d-4715-9ed6-5c7f2da9bda2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4089691144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.4089691144
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.4048840998
Short name T1044
Test name
Test status
Simulation time 13358721172 ps
CPU time 11.9 seconds
Started Jun 21 04:53:57 PM PDT 24
Finished Jun 21 04:54:10 PM PDT 24
Peak memory 206200 kb
Host smart-9a11085c-aa79-4953-a29d-e3fd4e5d917a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4048840998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.4048840998
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.269557363
Short name T1319
Test name
Test status
Simulation time 23343561327 ps
CPU time 23.72 seconds
Started Jun 21 04:53:58 PM PDT 24
Finished Jun 21 04:54:23 PM PDT 24
Peak memory 206032 kb
Host smart-a566d186-67a0-49a0-b0b5-69438fec3f54
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=269557363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.269557363
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.89887344
Short name T1293
Test name
Test status
Simulation time 156862107 ps
CPU time 0.77 seconds
Started Jun 21 04:53:57 PM PDT 24
Finished Jun 21 04:53:58 PM PDT 24
Peak memory 205964 kb
Host smart-699f3f71-eadb-49c7-8831-b15376590de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89887
344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.89887344
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.2246294907
Short name T46
Test name
Test status
Simulation time 162002857 ps
CPU time 0.82 seconds
Started Jun 21 04:53:57 PM PDT 24
Finished Jun 21 04:54:00 PM PDT 24
Peak memory 205964 kb
Host smart-ecfc7ade-026a-458c-90b6-6e082b902740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22462
94907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.2246294907
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.4125471062
Short name T82
Test name
Test status
Simulation time 148926571 ps
CPU time 0.78 seconds
Started Jun 21 04:53:59 PM PDT 24
Finished Jun 21 04:54:01 PM PDT 24
Peak memory 205992 kb
Host smart-6feaf8b7-3beb-4d64-ae7e-aa44fc3b2e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41254
71062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.4125471062
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.2416546185
Short name T226
Test name
Test status
Simulation time 179677992 ps
CPU time 0.81 seconds
Started Jun 21 04:53:59 PM PDT 24
Finished Jun 21 04:54:01 PM PDT 24
Peak memory 206008 kb
Host smart-3639946c-89e4-4ada-9934-65b3d9205e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24165
46185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.2416546185
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.1734320896
Short name T1724
Test name
Test status
Simulation time 465520528 ps
CPU time 1.42 seconds
Started Jun 21 04:54:10 PM PDT 24
Finished Jun 21 04:54:12 PM PDT 24
Peak memory 206048 kb
Host smart-8220cbdd-9a60-4033-b2dd-346db08a13e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17343
20896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.1734320896
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.399808581
Short name T2454
Test name
Test status
Simulation time 784282976 ps
CPU time 2.05 seconds
Started Jun 21 04:54:06 PM PDT 24
Finished Jun 21 04:54:09 PM PDT 24
Peak memory 206240 kb
Host smart-9a200faf-f7e5-492e-b8ff-a942d541506b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39980
8581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.399808581
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.3213398694
Short name T761
Test name
Test status
Simulation time 321938132 ps
CPU time 1.07 seconds
Started Jun 21 04:54:07 PM PDT 24
Finished Jun 21 04:54:09 PM PDT 24
Peak memory 205976 kb
Host smart-b0eccb96-0896-44a8-ac93-5c2d13833e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32133
98694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3213398694
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.859721478
Short name T2461
Test name
Test status
Simulation time 148589841 ps
CPU time 0.82 seconds
Started Jun 21 04:54:04 PM PDT 24
Finished Jun 21 04:54:06 PM PDT 24
Peak memory 205968 kb
Host smart-9c157a5c-26d6-4a91-9e9d-ae4c8614b62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85972
1478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.859721478
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1392147813
Short name T1766
Test name
Test status
Simulation time 38130549 ps
CPU time 0.66 seconds
Started Jun 21 04:54:11 PM PDT 24
Finished Jun 21 04:54:13 PM PDT 24
Peak memory 206044 kb
Host smart-4ea84f04-eb1d-47b6-a8b1-8b3cacd7f184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13921
47813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1392147813
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3851557179
Short name T912
Test name
Test status
Simulation time 675376099 ps
CPU time 1.82 seconds
Started Jun 21 04:54:06 PM PDT 24
Finished Jun 21 04:54:08 PM PDT 24
Peak memory 206120 kb
Host smart-2f48f7a9-d61c-47a6-8342-18808207291c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38515
57179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3851557179
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3849353885
Short name T1071
Test name
Test status
Simulation time 178821181 ps
CPU time 1.28 seconds
Started Jun 21 04:54:10 PM PDT 24
Finished Jun 21 04:54:13 PM PDT 24
Peak memory 206188 kb
Host smart-381de20b-6b6c-4ac6-b351-401fb72d2ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38493
53885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3849353885
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1720588506
Short name T980
Test name
Test status
Simulation time 197512533 ps
CPU time 0.86 seconds
Started Jun 21 04:54:12 PM PDT 24
Finished Jun 21 04:54:15 PM PDT 24
Peak memory 205972 kb
Host smart-1933d83f-7030-4813-ad4d-5bbd04bb972e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17205
88506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1720588506
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2649844411
Short name T2021
Test name
Test status
Simulation time 195606597 ps
CPU time 0.83 seconds
Started Jun 21 04:54:12 PM PDT 24
Finished Jun 21 04:54:15 PM PDT 24
Peak memory 206020 kb
Host smart-9a3d3787-d121-4290-8e7c-c4c591336e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26498
44411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2649844411
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.533095236
Short name T1330
Test name
Test status
Simulation time 199728103 ps
CPU time 0.89 seconds
Started Jun 21 04:54:05 PM PDT 24
Finished Jun 21 04:54:07 PM PDT 24
Peak memory 206024 kb
Host smart-dbcfa700-0157-475c-a95d-eef45c238d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53309
5236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.533095236
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.132325729
Short name T1948
Test name
Test status
Simulation time 19128378038 ps
CPU time 549.28 seconds
Started Jun 21 04:54:10 PM PDT 24
Finished Jun 21 05:03:21 PM PDT 24
Peak memory 206236 kb
Host smart-f5a38803-1e12-4651-b096-4d1019c79054
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=132325729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.132325729
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.806679025
Short name T2499
Test name
Test status
Simulation time 212307554 ps
CPU time 0.84 seconds
Started Jun 21 04:54:10 PM PDT 24
Finished Jun 21 04:54:11 PM PDT 24
Peak memory 206000 kb
Host smart-460884a6-0533-462e-9c59-14a693dbb746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80667
9025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.806679025
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.3993308729
Short name T585
Test name
Test status
Simulation time 23317249770 ps
CPU time 22.47 seconds
Started Jun 21 04:54:11 PM PDT 24
Finished Jun 21 04:54:35 PM PDT 24
Peak memory 206096 kb
Host smart-da1550a5-2335-46c8-acf2-6156c6980d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39933
08729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.3993308729
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2356705998
Short name T1277
Test name
Test status
Simulation time 3287172735 ps
CPU time 3.91 seconds
Started Jun 21 04:54:08 PM PDT 24
Finished Jun 21 04:54:13 PM PDT 24
Peak memory 206040 kb
Host smart-bb296bb5-0665-4111-acd5-2eef3e8f695b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23567
05998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2356705998
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.3425555932
Short name T2071
Test name
Test status
Simulation time 6320332207 ps
CPU time 173.49 seconds
Started Jun 21 04:54:11 PM PDT 24
Finished Jun 21 04:57:07 PM PDT 24
Peak memory 206296 kb
Host smart-273ac46a-94aa-4fb1-80dc-d443499020c7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3425555932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.3425555932
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.2382221713
Short name T2170
Test name
Test status
Simulation time 239248089 ps
CPU time 0.88 seconds
Started Jun 21 04:54:13 PM PDT 24
Finished Jun 21 04:54:17 PM PDT 24
Peak memory 206084 kb
Host smart-4e90e288-ee3d-4fe5-946a-c0b2523cd6fe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2382221713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.2382221713
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1051714270
Short name T586
Test name
Test status
Simulation time 206667085 ps
CPU time 0.85 seconds
Started Jun 21 04:54:10 PM PDT 24
Finished Jun 21 04:54:11 PM PDT 24
Peak memory 206024 kb
Host smart-62035785-be5e-4396-8dbc-a4d7046e6d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10517
14270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1051714270
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.683546909
Short name T429
Test name
Test status
Simulation time 6459182025 ps
CPU time 175.67 seconds
Started Jun 21 04:54:08 PM PDT 24
Finished Jun 21 04:57:04 PM PDT 24
Peak memory 206216 kb
Host smart-4ff1403d-1f54-4c2c-bdfc-ca0eef164985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68354
6909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.683546909
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.3537239803
Short name T2402
Test name
Test status
Simulation time 5732784102 ps
CPU time 55.12 seconds
Started Jun 21 04:54:06 PM PDT 24
Finished Jun 21 04:55:02 PM PDT 24
Peak memory 206264 kb
Host smart-5355e1f6-237d-4c46-adc7-746b1f833cf3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3537239803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.3537239803
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.173873097
Short name T1049
Test name
Test status
Simulation time 163092943 ps
CPU time 0.85 seconds
Started Jun 21 04:54:14 PM PDT 24
Finished Jun 21 04:54:17 PM PDT 24
Peak memory 206028 kb
Host smart-1f232556-5333-421a-a218-0de2d4d39fa9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=173873097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.173873097
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2503542368
Short name T2213
Test name
Test status
Simulation time 148244351 ps
CPU time 0.79 seconds
Started Jun 21 04:54:10 PM PDT 24
Finished Jun 21 04:54:12 PM PDT 24
Peak memory 206020 kb
Host smart-5d74ccd7-b6a5-40dd-b129-3624b48b73dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25035
42368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2503542368
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1967608145
Short name T2052
Test name
Test status
Simulation time 254483964 ps
CPU time 0.91 seconds
Started Jun 21 04:54:06 PM PDT 24
Finished Jun 21 04:54:08 PM PDT 24
Peak memory 206028 kb
Host smart-285f66ff-59f8-4d52-a31f-cf31271b368f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19676
08145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1967608145
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.1945290093
Short name T790
Test name
Test status
Simulation time 146846522 ps
CPU time 0.78 seconds
Started Jun 21 04:54:06 PM PDT 24
Finished Jun 21 04:54:08 PM PDT 24
Peak memory 205920 kb
Host smart-fadd3bf4-16e9-422b-b2fc-c5479c48d942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19452
90093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.1945290093
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.4183233262
Short name T668
Test name
Test status
Simulation time 179336989 ps
CPU time 0.83 seconds
Started Jun 21 04:54:10 PM PDT 24
Finished Jun 21 04:54:12 PM PDT 24
Peak memory 206052 kb
Host smart-b4f10a5c-d7fd-4206-8cba-fac589888fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41832
33262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.4183233262
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2013958197
Short name T1387
Test name
Test status
Simulation time 163760051 ps
CPU time 0.83 seconds
Started Jun 21 04:54:05 PM PDT 24
Finished Jun 21 04:54:06 PM PDT 24
Peak memory 206024 kb
Host smart-2597b5f3-12f7-440f-a0cf-c6895d03ff5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20139
58197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2013958197
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3287639980
Short name T1362
Test name
Test status
Simulation time 157122494 ps
CPU time 0.78 seconds
Started Jun 21 04:54:13 PM PDT 24
Finished Jun 21 04:54:16 PM PDT 24
Peak memory 206024 kb
Host smart-3f2f341e-5621-4340-a5fd-a82352c79f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32876
39980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3287639980
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.2009650957
Short name T731
Test name
Test status
Simulation time 255687033 ps
CPU time 0.95 seconds
Started Jun 21 04:54:11 PM PDT 24
Finished Jun 21 04:54:14 PM PDT 24
Peak memory 206048 kb
Host smart-80c0753a-3f0c-44f9-8e7c-d08d38336e7c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2009650957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.2009650957
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.3180016916
Short name T1324
Test name
Test status
Simulation time 134926497 ps
CPU time 0.82 seconds
Started Jun 21 04:54:12 PM PDT 24
Finished Jun 21 04:54:15 PM PDT 24
Peak memory 205988 kb
Host smart-c1b2e1f7-d429-416c-af14-e3804a4f0b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31800
16916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3180016916
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.3875430518
Short name T2411
Test name
Test status
Simulation time 33788419 ps
CPU time 0.65 seconds
Started Jun 21 04:54:12 PM PDT 24
Finished Jun 21 04:54:14 PM PDT 24
Peak memory 206032 kb
Host smart-dce6d6af-1035-459f-9812-309881735bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38754
30518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.3875430518
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.109599627
Short name T1838
Test name
Test status
Simulation time 7604857928 ps
CPU time 16.03 seconds
Started Jun 21 04:54:14 PM PDT 24
Finished Jun 21 04:54:32 PM PDT 24
Peak memory 206228 kb
Host smart-3a0961e2-6bee-4fb1-9e57-14bf2a011fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10959
9627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.109599627
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2072073453
Short name T1379
Test name
Test status
Simulation time 178086963 ps
CPU time 0.82 seconds
Started Jun 21 04:54:14 PM PDT 24
Finished Jun 21 04:54:17 PM PDT 24
Peak memory 205648 kb
Host smart-b8c0637e-1b49-4d23-ba06-dfa73ba2b40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20720
73453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2072073453
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3788994345
Short name T2178
Test name
Test status
Simulation time 154686262 ps
CPU time 0.77 seconds
Started Jun 21 04:54:13 PM PDT 24
Finished Jun 21 04:54:16 PM PDT 24
Peak memory 205952 kb
Host smart-944e4a14-e7c0-4cb6-8091-39c0d5b4d8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37889
94345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3788994345
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.1035059557
Short name T1701
Test name
Test status
Simulation time 10873226692 ps
CPU time 202.01 seconds
Started Jun 21 04:54:11 PM PDT 24
Finished Jun 21 04:57:35 PM PDT 24
Peak memory 206288 kb
Host smart-152d861d-3e98-496e-a86b-50f277660953
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1035059557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.1035059557
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2589231484
Short name T1727
Test name
Test status
Simulation time 21626223550 ps
CPU time 515.89 seconds
Started Jun 21 04:54:12 PM PDT 24
Finished Jun 21 05:02:50 PM PDT 24
Peak memory 206260 kb
Host smart-63c0c7eb-cfa9-4f25-8974-68659ac55c5b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2589231484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2589231484
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.2183082899
Short name T2164
Test name
Test status
Simulation time 214863560 ps
CPU time 0.86 seconds
Started Jun 21 04:54:11 PM PDT 24
Finished Jun 21 04:54:14 PM PDT 24
Peak memory 205936 kb
Host smart-c0c20b20-7f6d-475f-89e9-55df79544666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21830
82899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.2183082899
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.539505941
Short name T700
Test name
Test status
Simulation time 178572949 ps
CPU time 0.82 seconds
Started Jun 21 04:54:11 PM PDT 24
Finished Jun 21 04:54:14 PM PDT 24
Peak memory 206148 kb
Host smart-9db8582a-8c07-43db-9f55-831861b8f1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53950
5941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.539505941
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.2974653255
Short name T1738
Test name
Test status
Simulation time 177806397 ps
CPU time 0.8 seconds
Started Jun 21 04:54:13 PM PDT 24
Finished Jun 21 04:54:16 PM PDT 24
Peak memory 205972 kb
Host smart-5bf66f76-b118-4579-9337-32e67c47f5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29746
53255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.2974653255
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2866246090
Short name T210
Test name
Test status
Simulation time 559388851 ps
CPU time 1.35 seconds
Started Jun 21 04:54:20 PM PDT 24
Finished Jun 21 04:54:23 PM PDT 24
Peak memory 223884 kb
Host smart-a61ca75d-f0b5-4411-a881-bb72294534f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2866246090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2866246090
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.2370230091
Short name T566
Test name
Test status
Simulation time 420413207 ps
CPU time 1.47 seconds
Started Jun 21 04:54:11 PM PDT 24
Finished Jun 21 04:54:15 PM PDT 24
Peak memory 205944 kb
Host smart-a95c3246-5001-4ddd-8a44-87e2fe430e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23702
30091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.2370230091
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3420743376
Short name T1755
Test name
Test status
Simulation time 186600523 ps
CPU time 0.8 seconds
Started Jun 21 04:54:11 PM PDT 24
Finished Jun 21 04:54:13 PM PDT 24
Peak memory 205980 kb
Host smart-7c50d095-e562-4b7d-a7a1-a3617fe2d5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34207
43376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3420743376
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2203203129
Short name T2247
Test name
Test status
Simulation time 149608412 ps
CPU time 0.75 seconds
Started Jun 21 04:54:13 PM PDT 24
Finished Jun 21 04:54:16 PM PDT 24
Peak memory 205984 kb
Host smart-fb697565-4fbf-4e7d-91fd-ea36a2711251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22032
03129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2203203129
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2534731816
Short name T218
Test name
Test status
Simulation time 222636053 ps
CPU time 0.9 seconds
Started Jun 21 04:53:57 PM PDT 24
Finished Jun 21 04:53:59 PM PDT 24
Peak memory 206028 kb
Host smart-b10bb016-b174-4aa9-85f6-d3b7e4921909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25347
31816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2534731816
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.1764763216
Short name T1720
Test name
Test status
Simulation time 3349884282 ps
CPU time 30.22 seconds
Started Jun 21 04:54:14 PM PDT 24
Finished Jun 21 04:54:46 PM PDT 24
Peak memory 206304 kb
Host smart-2ec58d4e-0de8-4541-8bd7-294dab5e60a9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1764763216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.1764763216
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.2088258650
Short name T1169
Test name
Test status
Simulation time 176688310 ps
CPU time 0.77 seconds
Started Jun 21 04:54:13 PM PDT 24
Finished Jun 21 04:54:16 PM PDT 24
Peak memory 205976 kb
Host smart-e4a13ca9-d493-4710-984e-2ca7a2343bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20882
58650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.2088258650
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.1240122973
Short name T2467
Test name
Test status
Simulation time 183722324 ps
CPU time 0.81 seconds
Started Jun 21 04:54:11 PM PDT 24
Finished Jun 21 04:54:13 PM PDT 24
Peak memory 206000 kb
Host smart-79088141-4795-431c-9d8a-0755c3bb6d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12401
22973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.1240122973
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2474062385
Short name T1168
Test name
Test status
Simulation time 6315676643 ps
CPU time 43.45 seconds
Started Jun 21 04:54:12 PM PDT 24
Finished Jun 21 04:54:57 PM PDT 24
Peak memory 206284 kb
Host smart-baa7a3f7-1610-489c-8bd2-dd309d47f6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24740
62385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2474062385
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.2373606686
Short name T1708
Test name
Test status
Simulation time 4011154837 ps
CPU time 4.43 seconds
Started Jun 21 04:58:36 PM PDT 24
Finished Jun 21 04:58:41 PM PDT 24
Peak memory 206244 kb
Host smart-4591095d-557d-4f33-807d-4d047db72d85
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2373606686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.2373606686
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.3269958337
Short name T2503
Test name
Test status
Simulation time 13348571099 ps
CPU time 14.4 seconds
Started Jun 21 04:58:35 PM PDT 24
Finished Jun 21 04:58:50 PM PDT 24
Peak memory 206004 kb
Host smart-e8a0daf1-ae98-49c1-890a-18a9a1999715
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3269958337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.3269958337
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.819759688
Short name T766
Test name
Test status
Simulation time 23438243064 ps
CPU time 22.88 seconds
Started Jun 21 04:58:36 PM PDT 24
Finished Jun 21 04:59:00 PM PDT 24
Peak memory 206296 kb
Host smart-282e798b-f7b2-4d77-9eea-f9c67cc09f8b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=819759688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.819759688
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.578380454
Short name T2072
Test name
Test status
Simulation time 198469143 ps
CPU time 0.86 seconds
Started Jun 21 04:58:42 PM PDT 24
Finished Jun 21 04:58:44 PM PDT 24
Peak memory 205944 kb
Host smart-88110f67-74b7-45d0-ac70-a35fb2225565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57838
0454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.578380454
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.3174437823
Short name T2206
Test name
Test status
Simulation time 207013231 ps
CPU time 0.83 seconds
Started Jun 21 04:58:37 PM PDT 24
Finished Jun 21 04:58:39 PM PDT 24
Peak memory 205948 kb
Host smart-f5b58761-b929-4edf-b4a2-a23c72fd8b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31744
37823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.3174437823
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.1758914771
Short name T843
Test name
Test status
Simulation time 540105095 ps
CPU time 1.46 seconds
Started Jun 21 04:58:40 PM PDT 24
Finished Jun 21 04:58:44 PM PDT 24
Peak memory 206028 kb
Host smart-fd265541-3e65-4d29-9c59-9ed673f7468d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17589
14771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.1758914771
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.4881056
Short name T945
Test name
Test status
Simulation time 19654529747 ps
CPU time 37.39 seconds
Started Jun 21 04:58:35 PM PDT 24
Finished Jun 21 04:59:13 PM PDT 24
Peak memory 206248 kb
Host smart-d083ab39-d7ed-4e0b-8a83-9b8e28b21f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48810
56 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.4881056
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.91853272
Short name T325
Test name
Test status
Simulation time 354662093 ps
CPU time 1.2 seconds
Started Jun 21 04:58:38 PM PDT 24
Finished Jun 21 04:58:41 PM PDT 24
Peak memory 206028 kb
Host smart-b08ea428-8f78-4aa7-acb0-0ed9dd56d16c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91853
272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.91853272
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3263785053
Short name T35
Test name
Test status
Simulation time 141381028 ps
CPU time 0.73 seconds
Started Jun 21 04:58:43 PM PDT 24
Finished Jun 21 04:58:45 PM PDT 24
Peak memory 206020 kb
Host smart-97932b37-6d58-44c3-915d-b9dd4e479dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32637
85053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3263785053
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.476978689
Short name T2253
Test name
Test status
Simulation time 30602167 ps
CPU time 0.66 seconds
Started Jun 21 04:58:38 PM PDT 24
Finished Jun 21 04:58:41 PM PDT 24
Peak memory 205960 kb
Host smart-a0cb4fce-84b9-46aa-a6de-bf9b4ee172e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47697
8689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.476978689
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.1127028131
Short name T1813
Test name
Test status
Simulation time 963802618 ps
CPU time 2.09 seconds
Started Jun 21 04:58:37 PM PDT 24
Finished Jun 21 04:58:41 PM PDT 24
Peak memory 206276 kb
Host smart-bd6583f5-3a4f-4e23-bfb6-686b9f17035f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11270
28131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.1127028131
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.675421349
Short name T2257
Test name
Test status
Simulation time 314919420 ps
CPU time 2.09 seconds
Started Jun 21 04:58:40 PM PDT 24
Finished Jun 21 04:58:45 PM PDT 24
Peak memory 206264 kb
Host smart-18d7809f-ef9a-4bfd-8d61-dcd8c1b2aeab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67542
1349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.675421349
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.665979084
Short name T1099
Test name
Test status
Simulation time 228835029 ps
CPU time 0.93 seconds
Started Jun 21 04:58:51 PM PDT 24
Finished Jun 21 04:58:53 PM PDT 24
Peak memory 206020 kb
Host smart-1dd7a63d-f5ed-467a-988f-2369131439aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66597
9084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.665979084
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.4178887161
Short name T1524
Test name
Test status
Simulation time 182167522 ps
CPU time 0.8 seconds
Started Jun 21 04:58:46 PM PDT 24
Finished Jun 21 04:58:50 PM PDT 24
Peak memory 205984 kb
Host smart-069f0ec6-c170-4f0f-8f63-2b65079715d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41788
87161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.4178887161
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.3947035561
Short name T1034
Test name
Test status
Simulation time 180332074 ps
CPU time 0.81 seconds
Started Jun 21 04:58:43 PM PDT 24
Finished Jun 21 04:58:45 PM PDT 24
Peak memory 206020 kb
Host smart-b2fb105c-e7f6-43ed-a806-186226cabad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39470
35561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3947035561
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1180562197
Short name T1325
Test name
Test status
Simulation time 236759888 ps
CPU time 0.92 seconds
Started Jun 21 04:58:40 PM PDT 24
Finished Jun 21 04:58:43 PM PDT 24
Peak memory 205776 kb
Host smart-c4ca0123-a332-4881-9d55-a6a705a332ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11805
62197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1180562197
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.135053884
Short name T1165
Test name
Test status
Simulation time 23291464982 ps
CPU time 21.86 seconds
Started Jun 21 04:58:36 PM PDT 24
Finished Jun 21 04:59:00 PM PDT 24
Peak memory 206016 kb
Host smart-7f255f13-4d5d-48b8-abe2-05a2b9a1014a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13505
3884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.135053884
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.4269809742
Short name T2310
Test name
Test status
Simulation time 3285707579 ps
CPU time 4.39 seconds
Started Jun 21 04:58:38 PM PDT 24
Finished Jun 21 04:58:44 PM PDT 24
Peak memory 206088 kb
Host smart-9479eba5-ef05-4e1d-9f7c-888e8d84083b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42698
09742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.4269809742
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.2714422208
Short name T1517
Test name
Test status
Simulation time 6944514524 ps
CPU time 50.21 seconds
Started Jun 21 04:58:39 PM PDT 24
Finished Jun 21 04:59:31 PM PDT 24
Peak memory 206264 kb
Host smart-1bcb7c2d-7563-4abb-ae5a-2c52c5e4ebc8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2714422208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.2714422208
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.3587668361
Short name T312
Test name
Test status
Simulation time 260329543 ps
CPU time 0.98 seconds
Started Jun 21 04:58:51 PM PDT 24
Finished Jun 21 04:58:53 PM PDT 24
Peak memory 206044 kb
Host smart-fc17b344-bd45-404b-898d-3213e061e01e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3587668361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.3587668361
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2877709923
Short name T351
Test name
Test status
Simulation time 199634692 ps
CPU time 0.89 seconds
Started Jun 21 04:58:38 PM PDT 24
Finished Jun 21 04:58:41 PM PDT 24
Peak memory 205964 kb
Host smart-1bb62b90-8f46-49ac-a4bb-4be82db3de78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28777
09923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2877709923
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.1903316059
Short name T2127
Test name
Test status
Simulation time 12586887134 ps
CPU time 85.54 seconds
Started Jun 21 04:58:40 PM PDT 24
Finished Jun 21 05:00:08 PM PDT 24
Peak memory 206056 kb
Host smart-81f99d37-5807-4351-82c2-2a46ee14c24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19033
16059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.1903316059
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.1025272960
Short name T874
Test name
Test status
Simulation time 14826359348 ps
CPU time 136.86 seconds
Started Jun 21 04:58:41 PM PDT 24
Finished Jun 21 05:01:00 PM PDT 24
Peak memory 206284 kb
Host smart-77a205fb-9120-4ca1-8e01-ad526f4ea0e3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1025272960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.1025272960
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.2365610502
Short name T1406
Test name
Test status
Simulation time 171481006 ps
CPU time 0.84 seconds
Started Jun 21 04:58:45 PM PDT 24
Finished Jun 21 04:58:48 PM PDT 24
Peak memory 206028 kb
Host smart-0255455c-5384-4441-939b-22fcba1a79f5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2365610502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.2365610502
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3930649181
Short name T1070
Test name
Test status
Simulation time 141607786 ps
CPU time 0.79 seconds
Started Jun 21 04:58:37 PM PDT 24
Finished Jun 21 04:58:39 PM PDT 24
Peak memory 205936 kb
Host smart-3d1492b8-c8e2-4c3e-909f-16f591a89523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39306
49181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3930649181
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3799563430
Short name T127
Test name
Test status
Simulation time 216979371 ps
CPU time 0.89 seconds
Started Jun 21 04:58:37 PM PDT 24
Finished Jun 21 04:58:40 PM PDT 24
Peak memory 206024 kb
Host smart-cfd181bc-c605-4c06-a53b-8e68ee7b37f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37995
63430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3799563430
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3385185913
Short name T471
Test name
Test status
Simulation time 156590367 ps
CPU time 0.79 seconds
Started Jun 21 04:58:36 PM PDT 24
Finished Jun 21 04:58:38 PM PDT 24
Peak memory 206000 kb
Host smart-2c893f1f-258a-440d-a36c-c13719726080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33851
85913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3385185913
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1428351790
Short name T919
Test name
Test status
Simulation time 240399101 ps
CPU time 0.85 seconds
Started Jun 21 04:58:36 PM PDT 24
Finished Jun 21 04:58:38 PM PDT 24
Peak memory 206024 kb
Host smart-7f51256c-db44-466e-ac77-b356c6fb673a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14283
51790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1428351790
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3310992828
Short name T2455
Test name
Test status
Simulation time 170923663 ps
CPU time 0.83 seconds
Started Jun 21 04:58:36 PM PDT 24
Finished Jun 21 04:58:38 PM PDT 24
Peak memory 206144 kb
Host smart-18063cec-6b2f-46f3-be95-1b6c14ae705b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33109
92828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3310992828
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.1886720590
Short name T1166
Test name
Test status
Simulation time 255084863 ps
CPU time 0.87 seconds
Started Jun 21 04:58:47 PM PDT 24
Finished Jun 21 04:58:50 PM PDT 24
Peak memory 206020 kb
Host smart-7ac56105-ce50-4ccc-8864-edbaa02af5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18867
20590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.1886720590
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.3001297565
Short name T2393
Test name
Test status
Simulation time 246194063 ps
CPU time 0.97 seconds
Started Jun 21 04:58:49 PM PDT 24
Finished Jun 21 04:58:52 PM PDT 24
Peak memory 205984 kb
Host smart-b885e6ff-488f-43fd-a392-8c6cefa45f83
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3001297565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.3001297565
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2143964066
Short name T1207
Test name
Test status
Simulation time 140232288 ps
CPU time 0.82 seconds
Started Jun 21 04:58:47 PM PDT 24
Finished Jun 21 04:58:50 PM PDT 24
Peak memory 205936 kb
Host smart-679fbd20-e241-4448-aefc-6cb50f261221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21439
64066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2143964066
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2492359683
Short name T1650
Test name
Test status
Simulation time 48108422 ps
CPU time 0.66 seconds
Started Jun 21 04:58:46 PM PDT 24
Finished Jun 21 04:58:48 PM PDT 24
Peak memory 205980 kb
Host smart-602cfd33-8b9c-429e-a6e4-14b25bb81c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24923
59683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2492359683
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3987539974
Short name T1921
Test name
Test status
Simulation time 7820897150 ps
CPU time 17.31 seconds
Started Jun 21 04:58:40 PM PDT 24
Finished Jun 21 04:59:00 PM PDT 24
Peak memory 206364 kb
Host smart-6e283f3c-f448-4385-9e84-1cf5d1e24c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39875
39974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3987539974
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2318524356
Short name T2431
Test name
Test status
Simulation time 195120668 ps
CPU time 0.85 seconds
Started Jun 21 04:58:37 PM PDT 24
Finished Jun 21 04:58:40 PM PDT 24
Peak memory 206028 kb
Host smart-ac40baf6-9886-4072-a724-65eda056d7a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23185
24356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2318524356
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2763577447
Short name T1433
Test name
Test status
Simulation time 154348581 ps
CPU time 0.86 seconds
Started Jun 21 04:58:40 PM PDT 24
Finished Jun 21 04:58:43 PM PDT 24
Peak memory 206020 kb
Host smart-988154eb-ee41-4908-8a14-ecd931037840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27635
77447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2763577447
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.2332119251
Short name T736
Test name
Test status
Simulation time 203917822 ps
CPU time 0.89 seconds
Started Jun 21 04:58:48 PM PDT 24
Finished Jun 21 04:58:51 PM PDT 24
Peak memory 206028 kb
Host smart-cfd8ee5a-73ba-43a3-92fe-3e50107cd533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23321
19251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.2332119251
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.427173712
Short name T665
Test name
Test status
Simulation time 220933485 ps
CPU time 0.85 seconds
Started Jun 21 04:58:39 PM PDT 24
Finished Jun 21 04:58:41 PM PDT 24
Peak memory 206024 kb
Host smart-cef5a136-5e32-47d3-8c69-71705ec3f4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42717
3712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.427173712
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2274273379
Short name T2428
Test name
Test status
Simulation time 194103717 ps
CPU time 0.81 seconds
Started Jun 21 04:58:45 PM PDT 24
Finished Jun 21 04:58:48 PM PDT 24
Peak memory 205920 kb
Host smart-772831e6-b77e-48e9-a556-fd9090137f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22742
73379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2274273379
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1961680533
Short name T1416
Test name
Test status
Simulation time 146125916 ps
CPU time 0.78 seconds
Started Jun 21 04:58:52 PM PDT 24
Finished Jun 21 04:58:55 PM PDT 24
Peak memory 205964 kb
Host smart-cdfa8981-75f9-4cdf-9b84-482249de3ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19616
80533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1961680533
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3640833689
Short name T2199
Test name
Test status
Simulation time 148435523 ps
CPU time 0.8 seconds
Started Jun 21 04:58:45 PM PDT 24
Finished Jun 21 04:58:47 PM PDT 24
Peak memory 206004 kb
Host smart-a002fceb-32e6-48ed-b06c-95e0141a174d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36408
33689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3640833689
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.386382228
Short name T1036
Test name
Test status
Simulation time 219933796 ps
CPU time 0.92 seconds
Started Jun 21 04:58:38 PM PDT 24
Finished Jun 21 04:58:40 PM PDT 24
Peak memory 205968 kb
Host smart-5eaf6d98-e052-4519-b77e-0a1dd7ea3551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38638
2228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.386382228
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3427631515
Short name T2134
Test name
Test status
Simulation time 190863080 ps
CPU time 0.85 seconds
Started Jun 21 04:58:58 PM PDT 24
Finished Jun 21 04:59:02 PM PDT 24
Peak memory 206028 kb
Host smart-ae0c4c9d-c8b4-474b-9855-c6fa6f1a5804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34276
31515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3427631515
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3477555400
Short name T1836
Test name
Test status
Simulation time 157308231 ps
CPU time 0.79 seconds
Started Jun 21 04:58:48 PM PDT 24
Finished Jun 21 04:58:51 PM PDT 24
Peak memory 206140 kb
Host smart-4eecf8e4-1bdb-46e6-87c6-f8b7a087419c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34775
55400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3477555400
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.2657157144
Short name T1366
Test name
Test status
Simulation time 5215841414 ps
CPU time 145.31 seconds
Started Jun 21 04:58:52 PM PDT 24
Finished Jun 21 05:01:20 PM PDT 24
Peak memory 206188 kb
Host smart-0831cd0f-4219-44ed-b97a-72b1879abba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26571
57144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.2657157144
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.2976441400
Short name T460
Test name
Test status
Simulation time 4107088862 ps
CPU time 5.49 seconds
Started Jun 21 04:58:56 PM PDT 24
Finished Jun 21 04:59:04 PM PDT 24
Peak memory 206108 kb
Host smart-06bdb7a5-36a7-4723-80d0-51a50b02b67b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2976441400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.2976441400
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.1994665683
Short name T593
Test name
Test status
Simulation time 13356465539 ps
CPU time 13.12 seconds
Started Jun 21 04:58:47 PM PDT 24
Finished Jun 21 04:59:03 PM PDT 24
Peak memory 206176 kb
Host smart-cceb89b0-9fcc-4c35-91db-fdb4742e23ca
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1994665683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.1994665683
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.99430547
Short name T514
Test name
Test status
Simulation time 23422201964 ps
CPU time 22.9 seconds
Started Jun 21 04:58:44 PM PDT 24
Finished Jun 21 04:59:08 PM PDT 24
Peak memory 206024 kb
Host smart-9e4577fb-00d0-471f-8788-4a48aa4f8a67
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=99430547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.99430547
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2487046311
Short name T455
Test name
Test status
Simulation time 173083037 ps
CPU time 0.76 seconds
Started Jun 21 04:58:51 PM PDT 24
Finished Jun 21 04:58:54 PM PDT 24
Peak memory 206032 kb
Host smart-314bcb7d-12b1-4f94-a635-8461fb973e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24870
46311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2487046311
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1503572126
Short name T1918
Test name
Test status
Simulation time 147751444 ps
CPU time 0.77 seconds
Started Jun 21 04:58:46 PM PDT 24
Finished Jun 21 04:58:49 PM PDT 24
Peak memory 206004 kb
Host smart-4bc95637-3cb7-478c-ab07-06378b77fa8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15035
72126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1503572126
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.3547183216
Short name T986
Test name
Test status
Simulation time 385886232 ps
CPU time 1.27 seconds
Started Jun 21 04:58:45 PM PDT 24
Finished Jun 21 04:58:47 PM PDT 24
Peak memory 206024 kb
Host smart-703fcbb5-62d6-435f-b705-a33c5e0ce79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35471
83216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.3547183216
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.376576722
Short name T2238
Test name
Test status
Simulation time 715389674 ps
CPU time 1.75 seconds
Started Jun 21 04:58:46 PM PDT 24
Finished Jun 21 04:58:50 PM PDT 24
Peak memory 205944 kb
Host smart-50446eef-f97a-4fb6-929e-162977e3d2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37657
6722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.376576722
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.310129091
Short name T1839
Test name
Test status
Simulation time 17241363350 ps
CPU time 33.36 seconds
Started Jun 21 04:58:45 PM PDT 24
Finished Jun 21 04:59:19 PM PDT 24
Peak memory 206172 kb
Host smart-d2a83f9e-c3f4-4ec1-bd9d-343d7f6bf24f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31012
9091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.310129091
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.2622892901
Short name T626
Test name
Test status
Simulation time 440284554 ps
CPU time 1.52 seconds
Started Jun 21 04:58:46 PM PDT 24
Finished Jun 21 04:58:50 PM PDT 24
Peak memory 206008 kb
Host smart-a8d721d3-c659-4ba6-aaed-e136bc709d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26228
92901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.2622892901
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.1806834200
Short name T1091
Test name
Test status
Simulation time 138024169 ps
CPU time 0.76 seconds
Started Jun 21 04:58:58 PM PDT 24
Finished Jun 21 04:59:01 PM PDT 24
Peak memory 206020 kb
Host smart-c5246e79-acb9-4517-8e0b-ac21efed66f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18068
34200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.1806834200
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.1008802925
Short name T1080
Test name
Test status
Simulation time 38367465 ps
CPU time 0.7 seconds
Started Jun 21 04:58:47 PM PDT 24
Finished Jun 21 04:58:50 PM PDT 24
Peak memory 205952 kb
Host smart-605b00b4-9db0-4b7c-a4e0-c9e3a614f71f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10088
02925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1008802925
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.4203201218
Short name T1108
Test name
Test status
Simulation time 960105799 ps
CPU time 2.12 seconds
Started Jun 21 04:58:45 PM PDT 24
Finished Jun 21 04:58:48 PM PDT 24
Peak memory 206204 kb
Host smart-a74ec2d7-62fe-4c74-816d-85a7d6fe526a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42032
01218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.4203201218
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.4189016386
Short name T2264
Test name
Test status
Simulation time 187989919 ps
CPU time 1.98 seconds
Started Jun 21 04:58:46 PM PDT 24
Finished Jun 21 04:58:50 PM PDT 24
Peak memory 206224 kb
Host smart-54af8376-18a9-404b-b746-a9e63f406398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41890
16386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.4189016386
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.4172332869
Short name T405
Test name
Test status
Simulation time 203814609 ps
CPU time 0.84 seconds
Started Jun 21 04:58:47 PM PDT 24
Finished Jun 21 04:58:50 PM PDT 24
Peak memory 206028 kb
Host smart-d8fc9901-587b-4548-9343-e468bb5ef61a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41723
32869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.4172332869
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2404439907
Short name T2344
Test name
Test status
Simulation time 148259633 ps
CPU time 0.8 seconds
Started Jun 21 04:58:50 PM PDT 24
Finished Jun 21 04:58:53 PM PDT 24
Peak memory 206016 kb
Host smart-e4d1d852-8193-45a3-ad8f-095e3c3cf9f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24044
39907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2404439907
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2946043167
Short name T1731
Test name
Test status
Simulation time 231133365 ps
CPU time 0.86 seconds
Started Jun 21 04:58:51 PM PDT 24
Finished Jun 21 04:58:54 PM PDT 24
Peak memory 205800 kb
Host smart-a055e114-e5ff-4194-9270-648edef9e67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29460
43167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2946043167
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.4063026844
Short name T953
Test name
Test status
Simulation time 5474966589 ps
CPU time 153.85 seconds
Started Jun 21 04:58:45 PM PDT 24
Finished Jun 21 05:01:21 PM PDT 24
Peak memory 206320 kb
Host smart-f7c577ee-fe7c-4543-bd3a-6944087a1272
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4063026844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.4063026844
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.2152397380
Short name T1372
Test name
Test status
Simulation time 219123408 ps
CPU time 0.85 seconds
Started Jun 21 04:58:46 PM PDT 24
Finished Jun 21 04:58:50 PM PDT 24
Peak memory 205960 kb
Host smart-5d70b5d8-4640-4693-9b47-7d63d59b982e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21523
97380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.2152397380
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.2770659092
Short name T1740
Test name
Test status
Simulation time 23326940802 ps
CPU time 28.16 seconds
Started Jun 21 04:58:46 PM PDT 24
Finished Jun 21 04:59:16 PM PDT 24
Peak memory 206020 kb
Host smart-9ab2fa72-0bec-4027-a9a6-b3814f57b64a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27706
59092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.2770659092
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1654744512
Short name T1452
Test name
Test status
Simulation time 3289363437 ps
CPU time 3.72 seconds
Started Jun 21 04:58:46 PM PDT 24
Finished Jun 21 04:58:51 PM PDT 24
Peak memory 206068 kb
Host smart-5c6a0758-894c-4cb0-9736-f958e13c5b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16547
44512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1654744512
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.443721548
Short name T2506
Test name
Test status
Simulation time 4380701612 ps
CPU time 30.58 seconds
Started Jun 21 04:58:47 PM PDT 24
Finished Jun 21 04:59:20 PM PDT 24
Peak memory 206236 kb
Host smart-64297c2b-4150-42f5-bf3b-b1bdd2fe92aa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=443721548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.443721548
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2840261986
Short name T2113
Test name
Test status
Simulation time 249343258 ps
CPU time 0.89 seconds
Started Jun 21 04:58:58 PM PDT 24
Finished Jun 21 04:59:01 PM PDT 24
Peak memory 206048 kb
Host smart-6806aba2-85c5-47c3-b06c-6dfe86cd2095
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2840261986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2840261986
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3100152888
Short name T76
Test name
Test status
Simulation time 183095598 ps
CPU time 0.82 seconds
Started Jun 21 04:58:51 PM PDT 24
Finished Jun 21 04:58:54 PM PDT 24
Peak memory 206040 kb
Host smart-8513e6ff-9e2c-4417-b346-54bede0bd335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31001
52888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3100152888
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.1248601979
Short name T880
Test name
Test status
Simulation time 3886978937 ps
CPU time 27.17 seconds
Started Jun 21 04:58:46 PM PDT 24
Finished Jun 21 04:59:15 PM PDT 24
Peak memory 206264 kb
Host smart-95d388ef-6010-46a1-a0d6-3eeef42b97c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12486
01979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.1248601979
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.3251894412
Short name T1176
Test name
Test status
Simulation time 9295792193 ps
CPU time 68.69 seconds
Started Jun 21 04:58:47 PM PDT 24
Finished Jun 21 04:59:58 PM PDT 24
Peak memory 206280 kb
Host smart-02e933bb-a243-4014-866f-76f248e5d968
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3251894412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.3251894412
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.3791865430
Short name T1559
Test name
Test status
Simulation time 183559807 ps
CPU time 0.8 seconds
Started Jun 21 04:58:50 PM PDT 24
Finished Jun 21 04:58:53 PM PDT 24
Peak memory 206048 kb
Host smart-adf4e84f-8d2c-43d6-967d-568753f23f8b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3791865430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3791865430
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2459076435
Short name T2119
Test name
Test status
Simulation time 153572722 ps
CPU time 0.78 seconds
Started Jun 21 04:58:45 PM PDT 24
Finished Jun 21 04:58:47 PM PDT 24
Peak memory 205932 kb
Host smart-1fb54bf3-d46b-4bb9-9d47-7d0b5e481242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24590
76435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2459076435
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.3960925788
Short name T131
Test name
Test status
Simulation time 258071341 ps
CPU time 0.9 seconds
Started Jun 21 04:58:51 PM PDT 24
Finished Jun 21 04:58:53 PM PDT 24
Peak memory 206024 kb
Host smart-41e7004a-3f20-4b44-b9d8-11090ec020e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39609
25788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.3960925788
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3384191281
Short name T565
Test name
Test status
Simulation time 150751428 ps
CPU time 0.81 seconds
Started Jun 21 04:58:45 PM PDT 24
Finished Jun 21 04:58:46 PM PDT 24
Peak memory 205956 kb
Host smart-ee97731e-371d-4aa1-a77e-20e85ac1eb66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33841
91281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3384191281
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1027177293
Short name T2216
Test name
Test status
Simulation time 197739766 ps
CPU time 0.81 seconds
Started Jun 21 04:58:46 PM PDT 24
Finished Jun 21 04:58:49 PM PDT 24
Peak memory 205928 kb
Host smart-812260bb-3ed5-4a6b-8b69-f74839b8d5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10271
77293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1027177293
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.4033702628
Short name T942
Test name
Test status
Simulation time 187052632 ps
CPU time 0.8 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:57 PM PDT 24
Peak memory 206036 kb
Host smart-21b1da0f-757e-47e0-a9d6-7bab2a96a657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40337
02628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.4033702628
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3645567662
Short name T1663
Test name
Test status
Simulation time 142769919 ps
CPU time 0.81 seconds
Started Jun 21 04:58:46 PM PDT 24
Finished Jun 21 04:58:50 PM PDT 24
Peak memory 205960 kb
Host smart-91e590a8-f5df-4e91-8714-61b3d4afc6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36455
67662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3645567662
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.231231345
Short name T1167
Test name
Test status
Simulation time 203503773 ps
CPU time 0.88 seconds
Started Jun 21 04:58:55 PM PDT 24
Finished Jun 21 04:58:59 PM PDT 24
Peak memory 206048 kb
Host smart-328e2ae2-1701-435b-9db5-b8f14b536579
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=231231345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.231231345
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.656402785
Short name T1951
Test name
Test status
Simulation time 151801576 ps
CPU time 0.78 seconds
Started Jun 21 04:58:48 PM PDT 24
Finished Jun 21 04:58:51 PM PDT 24
Peak memory 206148 kb
Host smart-134c0222-0394-4981-9187-94f6bbce64f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65640
2785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.656402785
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3616676323
Short name T1381
Test name
Test status
Simulation time 40088183 ps
CPU time 0.65 seconds
Started Jun 21 04:58:51 PM PDT 24
Finished Jun 21 04:58:54 PM PDT 24
Peak memory 205836 kb
Host smart-c264d3ff-687a-460d-95bd-d0901e093de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36166
76323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3616676323
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.415269953
Short name T170
Test name
Test status
Simulation time 8262327556 ps
CPU time 17.45 seconds
Started Jun 21 04:58:58 PM PDT 24
Finished Jun 21 04:59:18 PM PDT 24
Peak memory 206284 kb
Host smart-efebaac9-1268-4726-ae2b-ddd2542ed165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41526
9953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.415269953
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.610349146
Short name T358
Test name
Test status
Simulation time 257338051 ps
CPU time 1.01 seconds
Started Jun 21 04:58:52 PM PDT 24
Finished Jun 21 04:58:55 PM PDT 24
Peak memory 205972 kb
Host smart-9f279321-cdfe-4e37-899a-7816dbce3ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61034
9146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.610349146
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.4190978256
Short name T1814
Test name
Test status
Simulation time 200783104 ps
CPU time 0.87 seconds
Started Jun 21 04:59:02 PM PDT 24
Finished Jun 21 04:59:06 PM PDT 24
Peak memory 205968 kb
Host smart-8d827e78-7a31-4f42-977a-8162386ce5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41909
78256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.4190978256
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.2849487501
Short name T728
Test name
Test status
Simulation time 189536026 ps
CPU time 0.8 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:56 PM PDT 24
Peak memory 206028 kb
Host smart-e2f9f5d7-5d6a-4330-9d35-e5aca77aad19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28494
87501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.2849487501
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.2156074011
Short name T1336
Test name
Test status
Simulation time 162009457 ps
CPU time 0.8 seconds
Started Jun 21 04:58:49 PM PDT 24
Finished Jun 21 04:58:51 PM PDT 24
Peak memory 206048 kb
Host smart-520c73b0-1e46-4595-bebf-c3252dcbcd8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21560
74011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.2156074011
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3235840952
Short name T2143
Test name
Test status
Simulation time 145378750 ps
CPU time 0.75 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:57 PM PDT 24
Peak memory 206016 kb
Host smart-8c16e73c-467c-4c53-abb9-d1a454962cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32358
40952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3235840952
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.2638357689
Short name T1042
Test name
Test status
Simulation time 183687260 ps
CPU time 0.84 seconds
Started Jun 21 04:58:47 PM PDT 24
Finished Jun 21 04:58:50 PM PDT 24
Peak memory 205956 kb
Host smart-964b0aac-9376-4ecf-96a7-c603b872c643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26383
57689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2638357689
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3603304185
Short name T1909
Test name
Test status
Simulation time 149980770 ps
CPU time 0.79 seconds
Started Jun 21 04:58:49 PM PDT 24
Finished Jun 21 04:58:52 PM PDT 24
Peak memory 205964 kb
Host smart-40aacb56-251b-4d60-b4de-8856fee251a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36033
04185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3603304185
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.188195035
Short name T968
Test name
Test status
Simulation time 202034577 ps
CPU time 0.94 seconds
Started Jun 21 04:58:47 PM PDT 24
Finished Jun 21 04:58:51 PM PDT 24
Peak memory 205940 kb
Host smart-bd2b4f41-7d8e-4ce2-9925-44e77e95ce92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18819
5035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.188195035
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.141341141
Short name T2198
Test name
Test status
Simulation time 14009044875 ps
CPU time 386.13 seconds
Started Jun 21 04:58:56 PM PDT 24
Finished Jun 21 05:05:25 PM PDT 24
Peak memory 206280 kb
Host smart-fce7f540-fc59-492d-9ee7-6ff90c93943c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=141341141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.141341141
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.675239675
Short name T2048
Test name
Test status
Simulation time 201947184 ps
CPU time 0.82 seconds
Started Jun 21 04:58:52 PM PDT 24
Finished Jun 21 04:58:55 PM PDT 24
Peak memory 205960 kb
Host smart-7d7d30ed-9789-4f0c-977c-c265bed9c38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67523
9675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.675239675
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1782361435
Short name T1423
Test name
Test status
Simulation time 178710979 ps
CPU time 0.77 seconds
Started Jun 21 04:58:54 PM PDT 24
Finished Jun 21 04:58:58 PM PDT 24
Peak memory 206020 kb
Host smart-f34343b8-5912-4ba4-8e52-0664f2acac5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17823
61435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1782361435
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1428415122
Short name T2300
Test name
Test status
Simulation time 7064583135 ps
CPU time 204.03 seconds
Started Jun 21 04:58:46 PM PDT 24
Finished Jun 21 05:02:12 PM PDT 24
Peak memory 206256 kb
Host smart-c77a55ca-d067-4222-9524-c0e6e7e3e109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14284
15122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1428415122
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2792283395
Short name T1227
Test name
Test status
Simulation time 4033715287 ps
CPU time 4.76 seconds
Started Jun 21 04:58:51 PM PDT 24
Finished Jun 21 04:58:57 PM PDT 24
Peak memory 206108 kb
Host smart-43265b97-e4b8-4724-a5a8-7b27527e468b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2792283395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.2792283395
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.851562696
Short name T803
Test name
Test status
Simulation time 13395327577 ps
CPU time 12.28 seconds
Started Jun 21 04:58:49 PM PDT 24
Finished Jun 21 04:59:03 PM PDT 24
Peak memory 206092 kb
Host smart-09c7f8cf-19b9-4d11-aaa6-d5722f3ff235
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=851562696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.851562696
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.1555132296
Short name T2353
Test name
Test status
Simulation time 23370430275 ps
CPU time 29.54 seconds
Started Jun 21 04:58:51 PM PDT 24
Finished Jun 21 04:59:23 PM PDT 24
Peak memory 206240 kb
Host smart-aaf6cd27-24d7-418c-a0aa-ccd39d560690
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1555132296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.1555132296
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3563143302
Short name T156
Test name
Test status
Simulation time 151269677 ps
CPU time 0.82 seconds
Started Jun 21 04:58:50 PM PDT 24
Finished Jun 21 04:58:53 PM PDT 24
Peak memory 206020 kb
Host smart-04aa1d3d-5735-4ccd-9d8d-acd81e14256d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35631
43302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3563143302
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.1338227713
Short name T2126
Test name
Test status
Simulation time 190732785 ps
CPU time 0.85 seconds
Started Jun 21 04:58:51 PM PDT 24
Finished Jun 21 04:58:53 PM PDT 24
Peak memory 205972 kb
Host smart-bbfcb771-d484-40f8-8615-e6f939f517dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13382
27713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.1338227713
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.2813162656
Short name T780
Test name
Test status
Simulation time 297463119 ps
CPU time 1.1 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:57 PM PDT 24
Peak memory 205980 kb
Host smart-e362ccd6-f5e2-478f-aa64-9984307bd43d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28131
62656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.2813162656
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3354513174
Short name T1313
Test name
Test status
Simulation time 829286933 ps
CPU time 1.97 seconds
Started Jun 21 04:58:54 PM PDT 24
Finished Jun 21 04:58:59 PM PDT 24
Peak memory 206020 kb
Host smart-6ee9add1-3d27-41c6-9610-28b740d62cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33545
13174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3354513174
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.221720470
Short name T1692
Test name
Test status
Simulation time 14713666883 ps
CPU time 29.39 seconds
Started Jun 21 04:58:54 PM PDT 24
Finished Jun 21 04:59:26 PM PDT 24
Peak memory 206176 kb
Host smart-25c097ef-c893-4d25-af5b-596af1b101f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22172
0470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.221720470
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.3284897301
Short name T1533
Test name
Test status
Simulation time 481790801 ps
CPU time 1.44 seconds
Started Jun 21 04:58:54 PM PDT 24
Finished Jun 21 04:58:59 PM PDT 24
Peak memory 206000 kb
Host smart-52870e6c-158d-4b29-a75d-c36c22fa3d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32848
97301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.3284897301
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.1896803517
Short name T1847
Test name
Test status
Simulation time 158156017 ps
CPU time 0.76 seconds
Started Jun 21 04:58:54 PM PDT 24
Finished Jun 21 04:58:58 PM PDT 24
Peak memory 205996 kb
Host smart-90052678-284e-4f3c-a895-70ef20ece265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18968
03517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1896803517
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.3934403741
Short name T485
Test name
Test status
Simulation time 36066737 ps
CPU time 0.64 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:56 PM PDT 24
Peak memory 205972 kb
Host smart-fd739479-b0f5-4fd1-b70f-f8e21ee24995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39344
03741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3934403741
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.2494595857
Short name T2153
Test name
Test status
Simulation time 860693789 ps
CPU time 2.05 seconds
Started Jun 21 04:58:54 PM PDT 24
Finished Jun 21 04:58:59 PM PDT 24
Peak memory 206160 kb
Host smart-55d8ff8f-d0e0-4a38-8c04-3e584c10da5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24945
95857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.2494595857
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1754305206
Short name T1368
Test name
Test status
Simulation time 155598998 ps
CPU time 1.14 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:56 PM PDT 24
Peak memory 206204 kb
Host smart-5723bb17-d209-461c-a8d2-575ee61da2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17543
05206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1754305206
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.2042301225
Short name T1085
Test name
Test status
Simulation time 183690743 ps
CPU time 0.84 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:56 PM PDT 24
Peak memory 205924 kb
Host smart-6f100a62-ca29-4f32-bc35-2f00829d043b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20423
01225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.2042301225
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3486582827
Short name T1920
Test name
Test status
Simulation time 143303021 ps
CPU time 0.77 seconds
Started Jun 21 04:58:55 PM PDT 24
Finished Jun 21 04:58:59 PM PDT 24
Peak memory 205960 kb
Host smart-0feb8289-1276-4e2d-bb70-e9d7dec6054a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34865
82827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3486582827
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1693400183
Short name T1471
Test name
Test status
Simulation time 221934822 ps
CPU time 0.91 seconds
Started Jun 21 04:58:47 PM PDT 24
Finished Jun 21 04:58:51 PM PDT 24
Peak memory 205972 kb
Host smart-1942957d-855e-4410-b39f-3dade2f12458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16934
00183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1693400183
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2160276311
Short name T2069
Test name
Test status
Simulation time 249602866 ps
CPU time 0.88 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:57 PM PDT 24
Peak memory 205976 kb
Host smart-5f6ebec4-e490-423c-8cf6-14063683fc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21602
76311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2160276311
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.3857300488
Short name T1009
Test name
Test status
Simulation time 23274268009 ps
CPU time 25.32 seconds
Started Jun 21 04:58:55 PM PDT 24
Finished Jun 21 04:59:24 PM PDT 24
Peak memory 206036 kb
Host smart-7f283b86-76e5-46fe-b578-941e7cf3c818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38573
00488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.3857300488
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.469432280
Short name T2442
Test name
Test status
Simulation time 3295419866 ps
CPU time 4.15 seconds
Started Jun 21 04:58:56 PM PDT 24
Finished Jun 21 04:59:03 PM PDT 24
Peak memory 206028 kb
Host smart-8a566ef6-db43-44a7-8f2b-47dfc6868bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46943
2280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.469432280
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.1064858308
Short name T1210
Test name
Test status
Simulation time 7461964818 ps
CPU time 72.96 seconds
Started Jun 21 04:58:55 PM PDT 24
Finished Jun 21 05:00:11 PM PDT 24
Peak memory 206240 kb
Host smart-15854000-c4ca-415d-b328-0990d344364a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1064858308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.1064858308
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.3530132636
Short name T1279
Test name
Test status
Simulation time 244566095 ps
CPU time 0.84 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 04:59:05 PM PDT 24
Peak memory 205964 kb
Host smart-0dc0e45e-7887-454a-8d6c-cc9b7c0dd5a1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3530132636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.3530132636
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2026748116
Short name T2067
Test name
Test status
Simulation time 215310197 ps
CPU time 0.87 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 04:59:05 PM PDT 24
Peak memory 205984 kb
Host smart-cd51309e-23b7-4734-81e6-800631f2343c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20267
48116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2026748116
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.262560358
Short name T330
Test name
Test status
Simulation time 5743654258 ps
CPU time 160.01 seconds
Started Jun 21 04:59:01 PM PDT 24
Finished Jun 21 05:01:45 PM PDT 24
Peak memory 206148 kb
Host smart-fbca7a76-a745-4a54-9134-d3f59c5cb7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26256
0358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.262560358
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.3258691288
Short name T1196
Test name
Test status
Simulation time 7018508972 ps
CPU time 199.11 seconds
Started Jun 21 04:59:13 PM PDT 24
Finished Jun 21 05:02:35 PM PDT 24
Peak memory 206252 kb
Host smart-732d62b5-acd7-496f-a865-091419d1321b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3258691288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.3258691288
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.4230959721
Short name T1026
Test name
Test status
Simulation time 153414011 ps
CPU time 0.78 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 04:59:03 PM PDT 24
Peak memory 205992 kb
Host smart-fecd4191-1e09-42d5-87c2-bcdc5a8de6a6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4230959721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.4230959721
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2448723534
Short name T1704
Test name
Test status
Simulation time 154468539 ps
CPU time 0.83 seconds
Started Jun 21 04:58:56 PM PDT 24
Finished Jun 21 04:59:00 PM PDT 24
Peak memory 205980 kb
Host smart-1fe4ba74-19a7-4bb0-b40c-8cdc23c81a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24487
23534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2448723534
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1106220998
Short name T139
Test name
Test status
Simulation time 232209662 ps
CPU time 0.91 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:56 PM PDT 24
Peak memory 206024 kb
Host smart-6c0554f9-5ab4-4514-b7b6-714d06a93b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11062
20998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1106220998
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.446408026
Short name T1629
Test name
Test status
Simulation time 185964567 ps
CPU time 0.78 seconds
Started Jun 21 04:58:52 PM PDT 24
Finished Jun 21 04:58:55 PM PDT 24
Peak memory 205976 kb
Host smart-ea086b9e-b8ee-45cb-be19-55c721380a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44640
8026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.446408026
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3953358435
Short name T990
Test name
Test status
Simulation time 160046149 ps
CPU time 0.78 seconds
Started Jun 21 04:58:58 PM PDT 24
Finished Jun 21 04:59:01 PM PDT 24
Peak memory 205972 kb
Host smart-aa34d9eb-26c2-4f78-a440-b4c63bc18668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39533
58435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3953358435
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.2760779683
Short name T1298
Test name
Test status
Simulation time 187482385 ps
CPU time 0.86 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:57 PM PDT 24
Peak memory 205980 kb
Host smart-668ed977-5ccd-4909-af59-f90d5e2f9b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27607
79683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.2760779683
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3030849785
Short name T711
Test name
Test status
Simulation time 147045060 ps
CPU time 0.79 seconds
Started Jun 21 04:58:52 PM PDT 24
Finished Jun 21 04:59:00 PM PDT 24
Peak memory 206020 kb
Host smart-ecf9c430-74bc-43ed-8f69-df53b174d9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30308
49785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3030849785
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.2832725561
Short name T1383
Test name
Test status
Simulation time 199628837 ps
CPU time 0.91 seconds
Started Jun 21 04:58:59 PM PDT 24
Finished Jun 21 04:59:03 PM PDT 24
Peak memory 205944 kb
Host smart-42f0bba3-a806-4fdb-b54d-ad93664a73ed
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2832725561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2832725561
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.1770708252
Short name T2131
Test name
Test status
Simulation time 163784816 ps
CPU time 0.76 seconds
Started Jun 21 04:58:59 PM PDT 24
Finished Jun 21 04:59:02 PM PDT 24
Peak memory 205980 kb
Host smart-bd73c2c9-5b62-4e57-9376-32ba56879cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17707
08252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.1770708252
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1033193676
Short name T1843
Test name
Test status
Simulation time 69829432 ps
CPU time 0.67 seconds
Started Jun 21 04:59:01 PM PDT 24
Finished Jun 21 04:59:06 PM PDT 24
Peak memory 205976 kb
Host smart-50b6634a-863f-4afa-adce-b6022a70d867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10331
93676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1033193676
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3555402878
Short name T88
Test name
Test status
Simulation time 19374607219 ps
CPU time 47.07 seconds
Started Jun 21 04:58:55 PM PDT 24
Finished Jun 21 04:59:45 PM PDT 24
Peak memory 206272 kb
Host smart-3f332239-01d2-48d1-80b5-59483637f24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35554
02878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3555402878
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.2069310198
Short name T796
Test name
Test status
Simulation time 182360705 ps
CPU time 0.88 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:57 PM PDT 24
Peak memory 205932 kb
Host smart-25ab6b50-d1f3-4679-b603-26590136d8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20693
10198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2069310198
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.1545557009
Short name T2369
Test name
Test status
Simulation time 186902031 ps
CPU time 0.82 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:56 PM PDT 24
Peak memory 205948 kb
Host smart-a1e8eced-ab41-4fb9-b90e-5018727170b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15455
57009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1545557009
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.2904570044
Short name T362
Test name
Test status
Simulation time 226961093 ps
CPU time 0.82 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 04:59:05 PM PDT 24
Peak memory 205976 kb
Host smart-84d2309d-26ae-4f46-887e-0b6df3b4b3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29045
70044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.2904570044
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.1207055920
Short name T2223
Test name
Test status
Simulation time 212357699 ps
CPU time 0.84 seconds
Started Jun 21 04:58:54 PM PDT 24
Finished Jun 21 04:58:58 PM PDT 24
Peak memory 205980 kb
Host smart-7d128090-1bbd-4807-89eb-ed3c7c9b98e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12070
55920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.1207055920
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.690031131
Short name T378
Test name
Test status
Simulation time 138824627 ps
CPU time 0.74 seconds
Started Jun 21 04:58:58 PM PDT 24
Finished Jun 21 04:59:01 PM PDT 24
Peak memory 206028 kb
Host smart-3c2e6587-77a0-47c0-9f0c-3e54673e968b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69003
1131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.690031131
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2315842215
Short name T2094
Test name
Test status
Simulation time 148856801 ps
CPU time 0.76 seconds
Started Jun 21 04:58:54 PM PDT 24
Finished Jun 21 04:58:57 PM PDT 24
Peak memory 205952 kb
Host smart-084fd67a-e5c0-40fe-8a7e-054a758fd4a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23158
42215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2315842215
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2701109752
Short name T316
Test name
Test status
Simulation time 199852594 ps
CPU time 0.87 seconds
Started Jun 21 04:58:55 PM PDT 24
Finished Jun 21 04:58:59 PM PDT 24
Peak memory 206020 kb
Host smart-80b33831-ed70-4435-91ab-161d62e8d558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27011
09752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2701109752
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2111734041
Short name T2202
Test name
Test status
Simulation time 192790456 ps
CPU time 0.86 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 04:59:05 PM PDT 24
Peak memory 205896 kb
Host smart-3098d1e7-0b5d-448e-b997-e8968497796e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21117
34041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2111734041
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.3822527706
Short name T1522
Test name
Test status
Simulation time 13521726253 ps
CPU time 382.6 seconds
Started Jun 21 04:58:56 PM PDT 24
Finished Jun 21 05:05:22 PM PDT 24
Peak memory 206268 kb
Host smart-aa7fdb55-a2b0-4abc-a073-bc2eccacdfe2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3822527706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.3822527706
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1569271827
Short name T510
Test name
Test status
Simulation time 177561851 ps
CPU time 0.85 seconds
Started Jun 21 04:58:52 PM PDT 24
Finished Jun 21 04:58:55 PM PDT 24
Peak memory 206012 kb
Host smart-220a0e40-ced8-40a6-93a3-d394f485d03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15692
71827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1569271827
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.2222669170
Short name T1045
Test name
Test status
Simulation time 240486468 ps
CPU time 0.88 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:57 PM PDT 24
Peak memory 205984 kb
Host smart-991bd63c-d817-43b8-877c-ad4f85899764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22226
69170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2222669170
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.203133695
Short name T1711
Test name
Test status
Simulation time 10183886751 ps
CPU time 68.18 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 05:00:12 PM PDT 24
Peak memory 206284 kb
Host smart-62c8007c-03c4-4636-be3a-f6c7221fe7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20313
3695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.203133695
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.1098855568
Short name T2034
Test name
Test status
Simulation time 4322623762 ps
CPU time 5.29 seconds
Started Jun 21 04:58:54 PM PDT 24
Finished Jun 21 04:59:03 PM PDT 24
Peak memory 206288 kb
Host smart-9f07acd4-b99f-4064-bc8f-bb8ce010ac15
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1098855568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.1098855568
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3960890219
Short name T11
Test name
Test status
Simulation time 13355331009 ps
CPU time 13.26 seconds
Started Jun 21 04:58:54 PM PDT 24
Finished Jun 21 04:59:11 PM PDT 24
Peak memory 206240 kb
Host smart-bcdee6b9-fb50-48c9-9458-9ab140fdc9e0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3960890219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3960890219
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.4248230677
Short name T2444
Test name
Test status
Simulation time 23370924827 ps
CPU time 22.78 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 04:59:26 PM PDT 24
Peak memory 206088 kb
Host smart-e142fc29-ac75-491e-9b93-2210d929fcca
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4248230677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.4248230677
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.2173462514
Short name T861
Test name
Test status
Simulation time 242159962 ps
CPU time 0.85 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 04:59:05 PM PDT 24
Peak memory 205872 kb
Host smart-b5074db8-3495-4229-a127-203301f0f9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21734
62514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.2173462514
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.115042383
Short name T1978
Test name
Test status
Simulation time 139738166 ps
CPU time 0.74 seconds
Started Jun 21 04:58:52 PM PDT 24
Finished Jun 21 04:58:55 PM PDT 24
Peak memory 205988 kb
Host smart-4e2d35ca-4914-495c-bf18-dee8d024eab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11504
2383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.115042383
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.288630614
Short name T1024
Test name
Test status
Simulation time 356852497 ps
CPU time 1.21 seconds
Started Jun 21 04:58:57 PM PDT 24
Finished Jun 21 04:59:01 PM PDT 24
Peak memory 205972 kb
Host smart-91fc5434-7805-45fa-b2a2-383ff9f94a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28863
0614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.288630614
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.509287828
Short name T639
Test name
Test status
Simulation time 903820520 ps
CPU time 2.2 seconds
Started Jun 21 04:59:01 PM PDT 24
Finished Jun 21 04:59:07 PM PDT 24
Peak memory 206272 kb
Host smart-8b5e4b12-30d4-43d7-ba00-657527116d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50928
7828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.509287828
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.1938444802
Short name T1412
Test name
Test status
Simulation time 20763737619 ps
CPU time 38.71 seconds
Started Jun 21 04:59:01 PM PDT 24
Finished Jun 21 04:59:44 PM PDT 24
Peak memory 206264 kb
Host smart-3cd199f0-0297-451a-84d6-b556439f5594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19384
44802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.1938444802
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.2437289809
Short name T696
Test name
Test status
Simulation time 288968351 ps
CPU time 1.23 seconds
Started Jun 21 04:58:57 PM PDT 24
Finished Jun 21 04:59:01 PM PDT 24
Peak memory 205976 kb
Host smart-4d890e33-dde1-4400-be86-08f2a5b07c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24372
89809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.2437289809
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.786659544
Short name T1076
Test name
Test status
Simulation time 156762016 ps
CPU time 0.78 seconds
Started Jun 21 04:58:56 PM PDT 24
Finished Jun 21 04:59:00 PM PDT 24
Peak memory 205972 kb
Host smart-527ab113-73b5-47eb-8601-3aa6d6163d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78665
9544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.786659544
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.1038489078
Short name T413
Test name
Test status
Simulation time 89398496 ps
CPU time 0.75 seconds
Started Jun 21 04:59:02 PM PDT 24
Finished Jun 21 04:59:07 PM PDT 24
Peak memory 205916 kb
Host smart-843f2a96-bd39-4722-a149-54a25570b261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10384
89078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1038489078
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.3011969215
Short name T1180
Test name
Test status
Simulation time 817435395 ps
CPU time 2.09 seconds
Started Jun 21 04:59:04 PM PDT 24
Finished Jun 21 04:59:10 PM PDT 24
Peak memory 206176 kb
Host smart-55b9dbce-4b3f-4ade-82c1-e58bb06cac4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30119
69215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.3011969215
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1912659355
Short name T188
Test name
Test status
Simulation time 415878737 ps
CPU time 2.43 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:58 PM PDT 24
Peak memory 206208 kb
Host smart-e5b0b490-5655-4571-9468-dc338525cd2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19126
59355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1912659355
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2017374515
Short name T2193
Test name
Test status
Simulation time 231269964 ps
CPU time 0.89 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 04:59:05 PM PDT 24
Peak memory 206080 kb
Host smart-6934a3f5-79be-49fc-9c92-8e23427117a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20173
74515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2017374515
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.505296125
Short name T1598
Test name
Test status
Simulation time 171423404 ps
CPU time 0.82 seconds
Started Jun 21 04:59:02 PM PDT 24
Finished Jun 21 04:59:07 PM PDT 24
Peak memory 205932 kb
Host smart-d233392b-886f-4745-a20a-860151e228df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50529
6125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.505296125
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.195586156
Short name T1856
Test name
Test status
Simulation time 191110316 ps
CPU time 0.86 seconds
Started Jun 21 04:58:53 PM PDT 24
Finished Jun 21 04:58:57 PM PDT 24
Peak memory 205964 kb
Host smart-89ea9283-c586-4006-8fc8-21c0f0a2bc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19558
6156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.195586156
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.104177011
Short name T1751
Test name
Test status
Simulation time 11005138664 ps
CPU time 305.37 seconds
Started Jun 21 04:58:57 PM PDT 24
Finished Jun 21 05:04:05 PM PDT 24
Peak memory 206136 kb
Host smart-5d189edd-9ed3-4ed2-b9fb-5d03e1c5cc31
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=104177011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.104177011
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.54278916
Short name T528
Test name
Test status
Simulation time 167443147 ps
CPU time 0.82 seconds
Started Jun 21 04:58:55 PM PDT 24
Finished Jun 21 04:58:59 PM PDT 24
Peak memory 206024 kb
Host smart-db9cde59-a0ff-407a-97b7-5abf72ab9828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54278
916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.54278916
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.653151714
Short name T877
Test name
Test status
Simulation time 23336529926 ps
CPU time 20.45 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 04:59:24 PM PDT 24
Peak memory 206028 kb
Host smart-ec466b80-e721-4088-962f-04999f4d1bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65315
1714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.653151714
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3750147532
Short name T2498
Test name
Test status
Simulation time 3304724236 ps
CPU time 4.12 seconds
Started Jun 21 04:59:03 PM PDT 24
Finished Jun 21 04:59:12 PM PDT 24
Peak memory 205992 kb
Host smart-297f9ba3-630b-41e5-a571-af4b93332da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37501
47532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3750147532
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.3965113173
Short name T1000
Test name
Test status
Simulation time 3937181722 ps
CPU time 27.47 seconds
Started Jun 21 04:59:05 PM PDT 24
Finished Jun 21 04:59:37 PM PDT 24
Peak memory 206296 kb
Host smart-fed004bb-2e45-4358-93ca-0ecc850805a5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3965113173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.3965113173
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.2682647614
Short name T1572
Test name
Test status
Simulation time 251536156 ps
CPU time 0.9 seconds
Started Jun 21 04:59:06 PM PDT 24
Finished Jun 21 04:59:11 PM PDT 24
Peak memory 205956 kb
Host smart-713502a8-b47b-484d-8135-9dcca3f90d9e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2682647614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.2682647614
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1545804252
Short name T1603
Test name
Test status
Simulation time 240441526 ps
CPU time 0.94 seconds
Started Jun 21 04:59:01 PM PDT 24
Finished Jun 21 04:59:06 PM PDT 24
Peak memory 205980 kb
Host smart-e8b193ae-a417-4a39-8bdc-21a71ccf9e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15458
04252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1545804252
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.2834977690
Short name T2109
Test name
Test status
Simulation time 4362013442 ps
CPU time 29.69 seconds
Started Jun 21 04:59:01 PM PDT 24
Finished Jun 21 04:59:34 PM PDT 24
Peak memory 206296 kb
Host smart-484588e6-f260-4361-a577-5be85fd11bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28349
77690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.2834977690
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.3246397049
Short name T1132
Test name
Test status
Simulation time 3733713884 ps
CPU time 102.85 seconds
Started Jun 21 04:59:03 PM PDT 24
Finished Jun 21 05:00:50 PM PDT 24
Peak memory 206176 kb
Host smart-049822ff-8709-410b-a3fd-168293c6f1bf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3246397049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.3246397049
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.843760920
Short name T1219
Test name
Test status
Simulation time 162607596 ps
CPU time 0.93 seconds
Started Jun 21 04:59:02 PM PDT 24
Finished Jun 21 04:59:07 PM PDT 24
Peak memory 205960 kb
Host smart-efaaeeb3-2d70-4a56-ac54-d2777824bcf2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=843760920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.843760920
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2322426672
Short name T1685
Test name
Test status
Simulation time 149309759 ps
CPU time 0.76 seconds
Started Jun 21 04:58:59 PM PDT 24
Finished Jun 21 04:59:02 PM PDT 24
Peak memory 206088 kb
Host smart-6e7517a8-e73a-49f8-b39f-bcfddb6f0878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23224
26672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2322426672
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.852192358
Short name T2068
Test name
Test status
Simulation time 165895384 ps
CPU time 0.81 seconds
Started Jun 21 04:59:13 PM PDT 24
Finished Jun 21 04:59:17 PM PDT 24
Peak memory 206004 kb
Host smart-2089c289-f848-4354-80f0-f7d16f3e5537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85219
2358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.852192358
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2156090895
Short name T1600
Test name
Test status
Simulation time 168482538 ps
CPU time 0.79 seconds
Started Jun 21 04:59:01 PM PDT 24
Finished Jun 21 04:59:06 PM PDT 24
Peak memory 205964 kb
Host smart-19a65ff8-fd28-4ebe-b1bb-8d663ee94c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21560
90895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2156090895
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.4110579189
Short name T2291
Test name
Test status
Simulation time 153188722 ps
CPU time 0.79 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 04:59:05 PM PDT 24
Peak memory 206004 kb
Host smart-2cf3748d-d6d1-4f2d-a796-46f9e6955df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41105
79189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.4110579189
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2882369279
Short name T2042
Test name
Test status
Simulation time 150487568 ps
CPU time 0.78 seconds
Started Jun 21 04:59:03 PM PDT 24
Finished Jun 21 04:59:08 PM PDT 24
Peak memory 206048 kb
Host smart-d37dcc93-9824-4fef-8691-c765dd701706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28823
69279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2882369279
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.2233215479
Short name T1370
Test name
Test status
Simulation time 218415913 ps
CPU time 0.93 seconds
Started Jun 21 04:59:01 PM PDT 24
Finished Jun 21 04:59:06 PM PDT 24
Peak memory 205980 kb
Host smart-8022b60d-0015-4636-a809-65487ff7638e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2233215479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.2233215479
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.279395055
Short name T1885
Test name
Test status
Simulation time 173204473 ps
CPU time 0.79 seconds
Started Jun 21 04:59:09 PM PDT 24
Finished Jun 21 04:59:12 PM PDT 24
Peak memory 205876 kb
Host smart-fd626e1a-8f3d-4494-ba32-09242cbc5229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27939
5055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.279395055
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.289152800
Short name T1375
Test name
Test status
Simulation time 46613885 ps
CPU time 0.64 seconds
Started Jun 21 04:59:02 PM PDT 24
Finished Jun 21 04:59:06 PM PDT 24
Peak memory 206028 kb
Host smart-d59d16a1-e34e-490e-b832-5474b8ea1431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28915
2800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.289152800
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.2564995816
Short name T1963
Test name
Test status
Simulation time 13492299559 ps
CPU time 29.71 seconds
Started Jun 21 04:59:03 PM PDT 24
Finished Jun 21 04:59:37 PM PDT 24
Peak memory 206264 kb
Host smart-088ab7da-1644-4ebc-9a61-d36cc53f9152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25649
95816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.2564995816
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.77572180
Short name T981
Test name
Test status
Simulation time 140837316 ps
CPU time 0.77 seconds
Started Jun 21 04:59:15 PM PDT 24
Finished Jun 21 04:59:19 PM PDT 24
Peak memory 205932 kb
Host smart-42292cb5-a5a9-437b-882e-203ca398e8ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77572
180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.77572180
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1673152607
Short name T1187
Test name
Test status
Simulation time 239451646 ps
CPU time 0.95 seconds
Started Jun 21 04:59:04 PM PDT 24
Finished Jun 21 04:59:09 PM PDT 24
Peak memory 206024 kb
Host smart-09d50bda-2549-4027-a9f4-ac5eec9dfce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16731
52607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1673152607
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.1152951659
Short name T1464
Test name
Test status
Simulation time 292677344 ps
CPU time 0.99 seconds
Started Jun 21 04:59:03 PM PDT 24
Finished Jun 21 04:59:08 PM PDT 24
Peak memory 205980 kb
Host smart-0d2339ea-6669-413e-824a-3629cb2d98db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11529
51659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.1152951659
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.2305533924
Short name T2078
Test name
Test status
Simulation time 192714926 ps
CPU time 0.87 seconds
Started Jun 21 04:59:02 PM PDT 24
Finished Jun 21 04:59:06 PM PDT 24
Peak memory 206040 kb
Host smart-d8c78c6d-785b-414f-8fa0-3b659fd13f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23055
33924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.2305533924
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.4245029672
Short name T685
Test name
Test status
Simulation time 169614833 ps
CPU time 0.76 seconds
Started Jun 21 04:59:03 PM PDT 24
Finished Jun 21 04:59:09 PM PDT 24
Peak memory 206000 kb
Host smart-0282f8b4-efda-4fb3-a81d-eac7bcc98e33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42450
29672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.4245029672
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2916832278
Short name T1081
Test name
Test status
Simulation time 159481157 ps
CPU time 0.81 seconds
Started Jun 21 04:59:03 PM PDT 24
Finished Jun 21 04:59:07 PM PDT 24
Peak memory 205928 kb
Host smart-395531ba-2010-40ed-99fc-8a0a40b4b334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29168
32278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2916832278
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.825082481
Short name T2171
Test name
Test status
Simulation time 171708723 ps
CPU time 0.81 seconds
Started Jun 21 04:59:09 PM PDT 24
Finished Jun 21 04:59:12 PM PDT 24
Peak memory 205788 kb
Host smart-13e707fc-0e2d-4f95-9de0-0239c0dc70ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82508
2481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.825082481
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2680961719
Short name T1992
Test name
Test status
Simulation time 250011571 ps
CPU time 0.95 seconds
Started Jun 21 04:58:54 PM PDT 24
Finished Jun 21 04:58:58 PM PDT 24
Peak memory 206032 kb
Host smart-6f6713d1-5245-4e67-960b-285f97fea5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26809
61719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2680961719
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.3795009623
Short name T978
Test name
Test status
Simulation time 10565137561 ps
CPU time 80.26 seconds
Started Jun 21 04:59:01 PM PDT 24
Finished Jun 21 05:00:25 PM PDT 24
Peak memory 206200 kb
Host smart-55d5fb73-bdff-4d7d-96fc-a3f53754a369
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3795009623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.3795009623
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.3300953574
Short name T2424
Test name
Test status
Simulation time 169736601 ps
CPU time 0.8 seconds
Started Jun 21 04:58:59 PM PDT 24
Finished Jun 21 04:59:02 PM PDT 24
Peak memory 205972 kb
Host smart-04a9ce77-b48c-4db1-85e2-b00c15c2aa0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33009
53574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.3300953574
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.4111610869
Short name T898
Test name
Test status
Simulation time 153083159 ps
CPU time 0.82 seconds
Started Jun 21 04:59:18 PM PDT 24
Finished Jun 21 04:59:26 PM PDT 24
Peak memory 205996 kb
Host smart-f4e3dcff-70c6-413b-955a-ebbda8edef41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41116
10869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.4111610869
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3203274481
Short name T1833
Test name
Test status
Simulation time 9662859192 ps
CPU time 70.1 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 05:00:14 PM PDT 24
Peak memory 206336 kb
Host smart-52455992-cb13-446a-beb1-8155fdb77d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32032
74481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3203274481
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.902979053
Short name T1538
Test name
Test status
Simulation time 4195382619 ps
CPU time 4.97 seconds
Started Jun 21 04:59:01 PM PDT 24
Finished Jun 21 04:59:10 PM PDT 24
Peak memory 206344 kb
Host smart-21cb6b12-9adc-45d5-8245-b4283760b460
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=902979053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.902979053
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.4203684467
Short name T478
Test name
Test status
Simulation time 13413742118 ps
CPU time 15.28 seconds
Started Jun 21 04:58:58 PM PDT 24
Finished Jun 21 04:59:16 PM PDT 24
Peak memory 206252 kb
Host smart-cb8c7177-b48e-4494-a7be-3bcbac02502d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4203684467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.4203684467
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.3955573302
Short name T2208
Test name
Test status
Simulation time 23336780399 ps
CPU time 27.57 seconds
Started Jun 21 04:59:02 PM PDT 24
Finished Jun 21 04:59:33 PM PDT 24
Peak memory 206240 kb
Host smart-7ed985b8-0fbb-4b59-9ede-437115396476
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3955573302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.3955573302
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3698235321
Short name T1476
Test name
Test status
Simulation time 174482390 ps
CPU time 0.78 seconds
Started Jun 21 04:59:13 PM PDT 24
Finished Jun 21 04:59:17 PM PDT 24
Peak memory 206004 kb
Host smart-e924c9db-2741-448e-9f6c-be4e1b51d6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36982
35321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3698235321
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.3717911984
Short name T59
Test name
Test status
Simulation time 158842472 ps
CPU time 0.78 seconds
Started Jun 21 04:59:01 PM PDT 24
Finished Jun 21 04:59:06 PM PDT 24
Peak memory 206024 kb
Host smart-b21347e3-19fd-4f53-bbf7-34f5d90dcbcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37179
11984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.3717911984
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.2371050444
Short name T1286
Test name
Test status
Simulation time 236465173 ps
CPU time 0.93 seconds
Started Jun 21 04:59:18 PM PDT 24
Finished Jun 21 04:59:22 PM PDT 24
Peak memory 206036 kb
Host smart-33e1a594-2791-43e8-9c46-7d2cff3c67a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23710
50444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.2371050444
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.355598834
Short name T600
Test name
Test status
Simulation time 599430947 ps
CPU time 1.47 seconds
Started Jun 21 04:59:01 PM PDT 24
Finished Jun 21 04:59:06 PM PDT 24
Peak memory 205944 kb
Host smart-ea24c36e-75d1-49ca-9c93-13c6610c30ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35559
8834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.355598834
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.3247208212
Short name T95
Test name
Test status
Simulation time 6021622182 ps
CPU time 12.37 seconds
Started Jun 21 04:59:18 PM PDT 24
Finished Jun 21 04:59:33 PM PDT 24
Peak memory 206220 kb
Host smart-5c680e7a-8fc0-4afe-aa09-b2a01631ba62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32472
08212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.3247208212
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.2450416595
Short name T327
Test name
Test status
Simulation time 488628453 ps
CPU time 1.44 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 04:59:06 PM PDT 24
Peak memory 206008 kb
Host smart-bb71422e-18a4-4b91-af7f-1d6bb67fae2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24504
16595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.2450416595
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.2839967496
Short name T487
Test name
Test status
Simulation time 148807927 ps
CPU time 0.75 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 04:59:04 PM PDT 24
Peak memory 206020 kb
Host smart-2c27c085-bdc6-4d2c-b0b4-5b7bd2ffb615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28399
67496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2839967496
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.534473894
Short name T336
Test name
Test status
Simulation time 24190982 ps
CPU time 0.67 seconds
Started Jun 21 04:59:02 PM PDT 24
Finished Jun 21 04:59:07 PM PDT 24
Peak memory 206016 kb
Host smart-26fe7f8e-e530-4f03-99f9-85a472ab8718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53447
3894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.534473894
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.1102644118
Short name T1632
Test name
Test status
Simulation time 776454770 ps
CPU time 2.08 seconds
Started Jun 21 04:59:08 PM PDT 24
Finished Jun 21 04:59:13 PM PDT 24
Peak memory 206168 kb
Host smart-acd13756-d5c1-4ee6-9b38-4356f33e5538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11026
44118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.1102644118
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1310138044
Short name T1509
Test name
Test status
Simulation time 214698216 ps
CPU time 2.17 seconds
Started Jun 21 04:59:00 PM PDT 24
Finished Jun 21 04:59:06 PM PDT 24
Peak memory 206176 kb
Host smart-bdb39de8-e3b0-471e-888c-4bc75ebd8492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13101
38044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1310138044
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.4226581293
Short name T2415
Test name
Test status
Simulation time 249379779 ps
CPU time 0.92 seconds
Started Jun 21 04:59:09 PM PDT 24
Finished Jun 21 04:59:12 PM PDT 24
Peak memory 205924 kb
Host smart-061b953f-b01d-48e7-90af-f763ee7cd2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42265
81293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.4226581293
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2102035689
Short name T1304
Test name
Test status
Simulation time 155878174 ps
CPU time 0.81 seconds
Started Jun 21 04:59:10 PM PDT 24
Finished Jun 21 04:59:13 PM PDT 24
Peak memory 205964 kb
Host smart-e9730203-f38b-48db-b953-d1867eefe2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21020
35689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2102035689
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.3626810941
Short name T303
Test name
Test status
Simulation time 212811802 ps
CPU time 0.89 seconds
Started Jun 21 04:59:03 PM PDT 24
Finished Jun 21 04:59:08 PM PDT 24
Peak memory 205964 kb
Host smart-cead114a-48dc-4e08-8f91-dc5208e22bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36268
10941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.3626810941
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.1741274589
Short name T2426
Test name
Test status
Simulation time 257491414 ps
CPU time 0.89 seconds
Started Jun 21 04:59:14 PM PDT 24
Finished Jun 21 04:59:18 PM PDT 24
Peak memory 205928 kb
Host smart-c5109d25-9b42-4741-ae24-cff8ba5a43a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17412
74589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.1741274589
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.3049176785
Short name T1693
Test name
Test status
Simulation time 23344364441 ps
CPU time 26.24 seconds
Started Jun 21 04:59:10 PM PDT 24
Finished Jun 21 04:59:39 PM PDT 24
Peak memory 206024 kb
Host smart-3787a2ca-36ea-4d98-b557-43dc34506641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30491
76785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.3049176785
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.3630433733
Short name T1460
Test name
Test status
Simulation time 3322114016 ps
CPU time 3.77 seconds
Started Jun 21 04:59:10 PM PDT 24
Finished Jun 21 04:59:16 PM PDT 24
Peak memory 206088 kb
Host smart-289d662a-c1c0-44c0-af6e-18a3e1f537aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36304
33733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3630433733
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3257659134
Short name T447
Test name
Test status
Simulation time 5272399233 ps
CPU time 52.93 seconds
Started Jun 21 04:59:18 PM PDT 24
Finished Jun 21 05:00:14 PM PDT 24
Peak memory 206220 kb
Host smart-23ab56ac-f96f-4b2a-8ece-efe671d99f51
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3257659134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3257659134
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.431069700
Short name T418
Test name
Test status
Simulation time 242511817 ps
CPU time 0.93 seconds
Started Jun 21 04:59:10 PM PDT 24
Finished Jun 21 04:59:14 PM PDT 24
Peak memory 205988 kb
Host smart-19ce297f-db01-4d2d-b920-ceeeb38bada2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=431069700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.431069700
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1944775183
Short name T2449
Test name
Test status
Simulation time 194842208 ps
CPU time 0.87 seconds
Started Jun 21 04:59:12 PM PDT 24
Finished Jun 21 04:59:15 PM PDT 24
Peak memory 206152 kb
Host smart-1326aaad-9605-46c8-97f5-792b84ad6816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19447
75183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1944775183
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.1853030571
Short name T2044
Test name
Test status
Simulation time 5692551090 ps
CPU time 41.23 seconds
Started Jun 21 04:59:14 PM PDT 24
Finished Jun 21 04:59:59 PM PDT 24
Peak memory 206224 kb
Host smart-608b1e3f-33a8-4fd1-a3d4-49baf2f6a1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18530
30571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.1853030571
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.2776260941
Short name T1192
Test name
Test status
Simulation time 14322719222 ps
CPU time 135.57 seconds
Started Jun 21 04:59:10 PM PDT 24
Finished Jun 21 05:01:28 PM PDT 24
Peak memory 206284 kb
Host smart-b725ca1e-3032-49f3-9393-342beeec3274
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2776260941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.2776260941
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.2533543437
Short name T888
Test name
Test status
Simulation time 204384545 ps
CPU time 0.85 seconds
Started Jun 21 04:59:14 PM PDT 24
Finished Jun 21 04:59:18 PM PDT 24
Peak memory 206048 kb
Host smart-2aada12e-5774-40f8-b341-2b42f7773f17
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2533543437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.2533543437
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3126453679
Short name T476
Test name
Test status
Simulation time 146888075 ps
CPU time 0.8 seconds
Started Jun 21 04:59:14 PM PDT 24
Finished Jun 21 04:59:18 PM PDT 24
Peak memory 206048 kb
Host smart-fd1f52ca-d75d-4de8-bcce-114677207107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31264
53679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3126453679
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2102235027
Short name T144
Test name
Test status
Simulation time 216808003 ps
CPU time 0.86 seconds
Started Jun 21 04:59:15 PM PDT 24
Finished Jun 21 04:59:19 PM PDT 24
Peak memory 205972 kb
Host smart-79f4f345-c8da-4529-83d1-38bc5f645dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21022
35027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2102235027
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.131732818
Short name T911
Test name
Test status
Simulation time 197451376 ps
CPU time 0.84 seconds
Started Jun 21 04:59:11 PM PDT 24
Finished Jun 21 04:59:14 PM PDT 24
Peak memory 206004 kb
Host smart-2de725eb-bcac-41da-98ae-7110c9bf6ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13173
2818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.131732818
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2888502637
Short name T431
Test name
Test status
Simulation time 211173948 ps
CPU time 0.85 seconds
Started Jun 21 04:59:13 PM PDT 24
Finished Jun 21 04:59:16 PM PDT 24
Peak memory 206028 kb
Host smart-2b5558e3-e05e-4383-8090-6560f60875d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28885
02637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2888502637
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2195539565
Short name T2407
Test name
Test status
Simulation time 156071376 ps
CPU time 0.76 seconds
Started Jun 21 04:59:12 PM PDT 24
Finished Jun 21 04:59:15 PM PDT 24
Peak memory 206020 kb
Host smart-f82717d3-733d-40d3-a7d9-29b57b6c3793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21955
39565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2195539565
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.1504429527
Short name T1010
Test name
Test status
Simulation time 143313279 ps
CPU time 0.76 seconds
Started Jun 21 04:59:11 PM PDT 24
Finished Jun 21 04:59:14 PM PDT 24
Peak memory 206024 kb
Host smart-6c16fd12-52c0-4a29-8b69-94d56adea318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15044
29527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.1504429527
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.533475534
Short name T1646
Test name
Test status
Simulation time 215011061 ps
CPU time 0.88 seconds
Started Jun 21 04:59:10 PM PDT 24
Finished Jun 21 04:59:13 PM PDT 24
Peak memory 206056 kb
Host smart-fdd5252d-092f-4e64-932b-0e5b9cd8f4d0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=533475534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.533475534
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1343615825
Short name T2002
Test name
Test status
Simulation time 153764872 ps
CPU time 0.77 seconds
Started Jun 21 04:59:10 PM PDT 24
Finished Jun 21 04:59:13 PM PDT 24
Peak memory 205940 kb
Host smart-7c751e84-ff65-4ccb-9cb6-b222b9e2ccbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13436
15825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1343615825
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1074736810
Short name T811
Test name
Test status
Simulation time 38125120 ps
CPU time 0.7 seconds
Started Jun 21 04:59:12 PM PDT 24
Finished Jun 21 04:59:15 PM PDT 24
Peak memory 205976 kb
Host smart-612e4c40-6e1a-441a-8244-af9849d5ee9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10747
36810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1074736810
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3735117371
Short name T577
Test name
Test status
Simulation time 18009743357 ps
CPU time 39.43 seconds
Started Jun 21 04:59:11 PM PDT 24
Finished Jun 21 04:59:53 PM PDT 24
Peak memory 206272 kb
Host smart-5662dc9b-169f-4eaa-a4d2-f90455cb74a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37351
17371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3735117371
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.192512930
Short name T1901
Test name
Test status
Simulation time 189839083 ps
CPU time 0.86 seconds
Started Jun 21 04:59:18 PM PDT 24
Finished Jun 21 04:59:22 PM PDT 24
Peak memory 206024 kb
Host smart-2b9483c5-0ecb-4a1f-a25c-cc540ddfdb7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19251
2930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.192512930
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3812166920
Short name T632
Test name
Test status
Simulation time 241128822 ps
CPU time 0.9 seconds
Started Jun 21 04:59:09 PM PDT 24
Finished Jun 21 04:59:12 PM PDT 24
Peak memory 205992 kb
Host smart-313c154f-dda8-4534-9461-5ada247ded05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38121
66920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3812166920
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3899513198
Short name T1721
Test name
Test status
Simulation time 260397408 ps
CPU time 0.98 seconds
Started Jun 21 04:59:11 PM PDT 24
Finished Jun 21 04:59:15 PM PDT 24
Peak memory 206032 kb
Host smart-e660de4b-ed29-472a-bb9d-8edcff570843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38995
13198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3899513198
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.3728079308
Short name T2383
Test name
Test status
Simulation time 178640275 ps
CPU time 0.79 seconds
Started Jun 21 04:59:16 PM PDT 24
Finished Jun 21 04:59:20 PM PDT 24
Peak memory 205944 kb
Host smart-70df05e8-6f6b-4ebe-8f8c-e61397ce661b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37280
79308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.3728079308
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.187837249
Short name T1276
Test name
Test status
Simulation time 246950821 ps
CPU time 0.86 seconds
Started Jun 21 04:59:13 PM PDT 24
Finished Jun 21 04:59:18 PM PDT 24
Peak memory 206028 kb
Host smart-beb5c49f-62f3-4893-a663-cff9f3bca465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18783
7249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.187837249
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1707689158
Short name T1860
Test name
Test status
Simulation time 209210796 ps
CPU time 0.83 seconds
Started Jun 21 04:59:12 PM PDT 24
Finished Jun 21 04:59:15 PM PDT 24
Peak memory 205956 kb
Host smart-8f18ee01-a773-486d-b4d0-304419a4a1c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17076
89158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1707689158
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2278705299
Short name T1385
Test name
Test status
Simulation time 177591978 ps
CPU time 0.8 seconds
Started Jun 21 04:59:16 PM PDT 24
Finished Jun 21 04:59:20 PM PDT 24
Peak memory 205924 kb
Host smart-f81a9769-38fc-46d3-bd44-55dd2d638906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22787
05299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2278705299
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2161655296
Short name T43
Test name
Test status
Simulation time 238937140 ps
CPU time 0.89 seconds
Started Jun 21 04:59:18 PM PDT 24
Finished Jun 21 04:59:22 PM PDT 24
Peak memory 206028 kb
Host smart-e446129f-b393-4f72-b593-48294c1a94f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21616
55296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2161655296
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.308893279
Short name T1961
Test name
Test status
Simulation time 3885970496 ps
CPU time 29.05 seconds
Started Jun 21 04:59:11 PM PDT 24
Finished Jun 21 04:59:42 PM PDT 24
Peak memory 206296 kb
Host smart-c84bc3f7-eec9-4edd-aaaa-d9dbaa605e0b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=308893279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.308893279
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2715707787
Short name T525
Test name
Test status
Simulation time 182334720 ps
CPU time 0.8 seconds
Started Jun 21 04:59:13 PM PDT 24
Finished Jun 21 04:59:17 PM PDT 24
Peak memory 206032 kb
Host smart-e7a92195-5aa6-4c0a-93fd-ac80e2f6a998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27157
07787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2715707787
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.2955579362
Short name T484
Test name
Test status
Simulation time 171488778 ps
CPU time 0.76 seconds
Started Jun 21 04:59:09 PM PDT 24
Finished Jun 21 04:59:12 PM PDT 24
Peak memory 205964 kb
Host smart-da242d0e-6b68-4a00-a9b7-e837d05ea51a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29555
79362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.2955579362
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.2034863270
Short name T1186
Test name
Test status
Simulation time 14402676399 ps
CPU time 137.57 seconds
Started Jun 21 04:59:08 PM PDT 24
Finished Jun 21 05:01:28 PM PDT 24
Peak memory 206260 kb
Host smart-f4deeedf-0620-4f07-b6c7-4fad863f1dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20348
63270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.2034863270
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2170259522
Short name T8
Test name
Test status
Simulation time 3712230051 ps
CPU time 4.17 seconds
Started Jun 21 04:59:13 PM PDT 24
Finished Jun 21 04:59:20 PM PDT 24
Peak memory 206348 kb
Host smart-22774411-8352-401d-a6d8-d03474115ba8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2170259522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.2170259522
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.1512297099
Short name T753
Test name
Test status
Simulation time 13411162007 ps
CPU time 13.47 seconds
Started Jun 21 04:59:08 PM PDT 24
Finished Jun 21 04:59:25 PM PDT 24
Peak memory 206028 kb
Host smart-3ddadc3c-5a43-4f3c-8d72-6eaa46962cdb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1512297099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.1512297099
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.794776712
Short name T947
Test name
Test status
Simulation time 23347347093 ps
CPU time 27.62 seconds
Started Jun 21 04:59:14 PM PDT 24
Finished Jun 21 04:59:46 PM PDT 24
Peak memory 206084 kb
Host smart-07e552e9-2acf-43a9-9f1c-51f7e31e59df
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=794776712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.794776712
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3074747685
Short name T384
Test name
Test status
Simulation time 155093784 ps
CPU time 0.78 seconds
Started Jun 21 04:59:14 PM PDT 24
Finished Jun 21 04:59:19 PM PDT 24
Peak memory 205964 kb
Host smart-6eca2148-d83a-4168-a1a1-0d5f1eee96a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30747
47685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3074747685
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.2951411597
Short name T661
Test name
Test status
Simulation time 161974208 ps
CPU time 0.79 seconds
Started Jun 21 04:59:12 PM PDT 24
Finished Jun 21 04:59:15 PM PDT 24
Peak memory 205956 kb
Host smart-543531a2-a7da-4fc5-b88c-7852e55991c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29514
11597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.2951411597
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2003136737
Short name T1898
Test name
Test status
Simulation time 305398942 ps
CPU time 1.17 seconds
Started Jun 21 04:59:13 PM PDT 24
Finished Jun 21 04:59:17 PM PDT 24
Peak memory 206020 kb
Host smart-a13257fa-6bad-480f-983d-e8983b840728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20031
36737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2003136737
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.891240107
Short name T2324
Test name
Test status
Simulation time 1423893125 ps
CPU time 3.04 seconds
Started Jun 21 04:59:16 PM PDT 24
Finished Jun 21 04:59:22 PM PDT 24
Peak memory 206172 kb
Host smart-78c8b97f-ff5b-4f55-a842-06aab69d1643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89124
0107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.891240107
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.1549865825
Short name T1059
Test name
Test status
Simulation time 10178709716 ps
CPU time 20.5 seconds
Started Jun 21 04:59:13 PM PDT 24
Finished Jun 21 04:59:36 PM PDT 24
Peak memory 206416 kb
Host smart-bc906eac-4162-4d53-a8f8-14d246c3ff7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15498
65825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.1549865825
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.4239256697
Short name T1392
Test name
Test status
Simulation time 478040585 ps
CPU time 1.38 seconds
Started Jun 21 04:59:11 PM PDT 24
Finished Jun 21 04:59:15 PM PDT 24
Peak memory 205968 kb
Host smart-ef2cb521-73fe-4bd1-93d5-dcb15e2653ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42392
56697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.4239256697
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.248677543
Short name T395
Test name
Test status
Simulation time 154828913 ps
CPU time 0.75 seconds
Started Jun 21 04:59:14 PM PDT 24
Finished Jun 21 04:59:18 PM PDT 24
Peak memory 206020 kb
Host smart-16904314-4407-4ffd-80bd-693a9e0b5be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24867
7543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.248677543
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.920902373
Short name T1555
Test name
Test status
Simulation time 37859244 ps
CPU time 0.68 seconds
Started Jun 21 04:59:16 PM PDT 24
Finished Jun 21 04:59:20 PM PDT 24
Peak memory 205960 kb
Host smart-b3cd6e91-832d-42c0-a740-854eacaf8abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92090
2373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.920902373
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3825710008
Short name T2240
Test name
Test status
Simulation time 582286267 ps
CPU time 1.67 seconds
Started Jun 21 04:59:15 PM PDT 24
Finished Jun 21 04:59:20 PM PDT 24
Peak memory 206176 kb
Host smart-031a74d7-6a23-4dec-8d4d-088b0cbe6572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38257
10008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3825710008
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1817042270
Short name T1221
Test name
Test status
Simulation time 175357488 ps
CPU time 1.61 seconds
Started Jun 21 04:59:23 PM PDT 24
Finished Jun 21 04:59:27 PM PDT 24
Peak memory 206268 kb
Host smart-af19022b-ba0a-4e8b-9f78-66751d12afee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18170
42270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1817042270
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2397906274
Short name T1063
Test name
Test status
Simulation time 222815134 ps
CPU time 0.92 seconds
Started Jun 21 04:59:20 PM PDT 24
Finished Jun 21 04:59:24 PM PDT 24
Peak memory 206024 kb
Host smart-2bae44e0-c536-4c62-8d9b-4ada91c8644c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23979
06274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2397906274
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1685083323
Short name T1417
Test name
Test status
Simulation time 148136216 ps
CPU time 0.84 seconds
Started Jun 21 04:59:20 PM PDT 24
Finished Jun 21 04:59:23 PM PDT 24
Peak memory 206136 kb
Host smart-5e57538e-648b-4aec-9002-4c8efa8f1ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16850
83323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1685083323
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2089815408
Short name T1773
Test name
Test status
Simulation time 290185550 ps
CPU time 1.03 seconds
Started Jun 21 04:59:22 PM PDT 24
Finished Jun 21 04:59:25 PM PDT 24
Peak memory 205972 kb
Host smart-a5a84772-088d-4a76-847e-f1994693684b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20898
15408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2089815408
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.3971311514
Short name T2340
Test name
Test status
Simulation time 205986591 ps
CPU time 0.91 seconds
Started Jun 21 04:59:16 PM PDT 24
Finished Jun 21 04:59:20 PM PDT 24
Peak memory 205948 kb
Host smart-9c64dc6e-fe63-48e9-8e1b-e9f93578549d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39713
11514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3971311514
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.210421306
Short name T1079
Test name
Test status
Simulation time 23374672275 ps
CPU time 21.9 seconds
Started Jun 21 04:59:17 PM PDT 24
Finished Jun 21 04:59:42 PM PDT 24
Peak memory 206008 kb
Host smart-51132370-ea07-4daf-b485-1cf5f8295ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21042
1306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.210421306
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.236452354
Short name T1363
Test name
Test status
Simulation time 3319242959 ps
CPU time 3.68 seconds
Started Jun 21 04:59:19 PM PDT 24
Finished Jun 21 04:59:25 PM PDT 24
Peak memory 205988 kb
Host smart-160428ab-8ec6-48fa-ab83-8972dd7c99c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23645
2354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.236452354
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.1070650759
Short name T608
Test name
Test status
Simulation time 7074571384 ps
CPU time 192.25 seconds
Started Jun 21 04:59:23 PM PDT 24
Finished Jun 21 05:02:38 PM PDT 24
Peak memory 206272 kb
Host smart-84c676ee-6aa3-4be2-81d8-d05407375626
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1070650759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.1070650759
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2690661601
Short name T688
Test name
Test status
Simulation time 243285375 ps
CPU time 0.94 seconds
Started Jun 21 04:59:24 PM PDT 24
Finished Jun 21 04:59:27 PM PDT 24
Peak memory 205984 kb
Host smart-19969e46-200b-4d38-8251-67d2f954e2ab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2690661601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2690661601
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2149797526
Short name T554
Test name
Test status
Simulation time 213428681 ps
CPU time 0.88 seconds
Started Jun 21 04:59:15 PM PDT 24
Finished Jun 21 04:59:20 PM PDT 24
Peak memory 206016 kb
Host smart-369ee8bc-51e9-4ead-a367-a5d053c2b821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21497
97526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2149797526
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.2493093102
Short name T1501
Test name
Test status
Simulation time 5788162992 ps
CPU time 57.42 seconds
Started Jun 21 04:59:24 PM PDT 24
Finished Jun 21 05:00:24 PM PDT 24
Peak memory 206184 kb
Host smart-8e0fd349-3394-400c-8b77-67b8929b959e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24930
93102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.2493093102
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2121535510
Short name T1829
Test name
Test status
Simulation time 10241081467 ps
CPU time 76.19 seconds
Started Jun 21 04:59:18 PM PDT 24
Finished Jun 21 05:00:37 PM PDT 24
Peak memory 206264 kb
Host smart-ffad3ca2-c97c-4d23-8dce-2dcc0cd0d234
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2121535510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2121535510
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.4212729932
Short name T2468
Test name
Test status
Simulation time 198760233 ps
CPU time 0.8 seconds
Started Jun 21 04:59:22 PM PDT 24
Finished Jun 21 04:59:26 PM PDT 24
Peak memory 206028 kb
Host smart-68fc40c1-c06d-43ed-a07a-754e5a10ebfa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4212729932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.4212729932
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2813924346
Short name T1868
Test name
Test status
Simulation time 174781765 ps
CPU time 0.82 seconds
Started Jun 21 04:59:24 PM PDT 24
Finished Jun 21 04:59:28 PM PDT 24
Peak memory 206032 kb
Host smart-99fe108b-27b4-48be-b67e-a9fe227b8ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28139
24346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2813924346
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.1889997032
Short name T2420
Test name
Test status
Simulation time 218825246 ps
CPU time 0.91 seconds
Started Jun 21 04:59:20 PM PDT 24
Finished Jun 21 04:59:23 PM PDT 24
Peak memory 205972 kb
Host smart-98a39db8-a77b-4efa-95a7-8f0cd12dcf50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18899
97032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.1889997032
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.2343932757
Short name T951
Test name
Test status
Simulation time 186114879 ps
CPU time 0.87 seconds
Started Jun 21 04:59:24 PM PDT 24
Finished Jun 21 04:59:27 PM PDT 24
Peak memory 206024 kb
Host smart-5846fa27-0a84-4196-b7ab-c995335fa045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23439
32757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.2343932757
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3968351334
Short name T783
Test name
Test status
Simulation time 177160232 ps
CPU time 0.84 seconds
Started Jun 21 04:59:23 PM PDT 24
Finished Jun 21 04:59:28 PM PDT 24
Peak memory 206024 kb
Host smart-b18dd36f-a085-4ab1-b762-a1ae53f30190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39683
51334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3968351334
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1846862701
Short name T949
Test name
Test status
Simulation time 165870661 ps
CPU time 0.8 seconds
Started Jun 21 04:59:22 PM PDT 24
Finished Jun 21 04:59:25 PM PDT 24
Peak memory 206040 kb
Host smart-a73ec211-35c8-4037-be2f-f1daa4a59817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18468
62701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1846862701
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.566554814
Short name T1808
Test name
Test status
Simulation time 156432962 ps
CPU time 0.8 seconds
Started Jun 21 04:59:15 PM PDT 24
Finished Jun 21 04:59:19 PM PDT 24
Peak memory 206024 kb
Host smart-12e0f03e-2752-49c8-8e6f-aeb94dabe43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56655
4814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.566554814
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.1706262470
Short name T1913
Test name
Test status
Simulation time 196198283 ps
CPU time 0.86 seconds
Started Jun 21 04:59:19 PM PDT 24
Finished Jun 21 04:59:22 PM PDT 24
Peak memory 205992 kb
Host smart-38ac291e-0d24-4c3c-adb9-96a6adce9e69
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1706262470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.1706262470
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.2224544468
Short name T2249
Test name
Test status
Simulation time 224112400 ps
CPU time 0.84 seconds
Started Jun 21 04:59:16 PM PDT 24
Finished Jun 21 04:59:20 PM PDT 24
Peak memory 206056 kb
Host smart-cbc53835-2a3e-4914-bc52-5ed36271df10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22245
44468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2224544468
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.999980049
Short name T963
Test name
Test status
Simulation time 42194910 ps
CPU time 0.69 seconds
Started Jun 21 04:59:22 PM PDT 24
Finished Jun 21 04:59:25 PM PDT 24
Peak memory 205944 kb
Host smart-33de9399-d982-49d5-86dc-41d0b1f9baf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99998
0049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.999980049
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.3970356715
Short name T171
Test name
Test status
Simulation time 12660770839 ps
CPU time 25.94 seconds
Started Jun 21 04:59:20 PM PDT 24
Finished Jun 21 04:59:48 PM PDT 24
Peak memory 206188 kb
Host smart-8465a121-5211-4d61-bb78-68df8d5a7873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39703
56715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.3970356715
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1318083633
Short name T1739
Test name
Test status
Simulation time 189065269 ps
CPU time 0.88 seconds
Started Jun 21 04:59:18 PM PDT 24
Finished Jun 21 04:59:22 PM PDT 24
Peak memory 206024 kb
Host smart-b8d57dfd-7e31-4948-af42-7b72f646fd45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13180
83633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1318083633
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2604649055
Short name T2045
Test name
Test status
Simulation time 256800325 ps
CPU time 0.91 seconds
Started Jun 21 04:59:20 PM PDT 24
Finished Jun 21 04:59:24 PM PDT 24
Peak memory 206004 kb
Host smart-fd4735c4-89a8-4663-ab17-869eb10457dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26046
49055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2604649055
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.1431847879
Short name T754
Test name
Test status
Simulation time 237317120 ps
CPU time 0.89 seconds
Started Jun 21 04:59:21 PM PDT 24
Finished Jun 21 04:59:24 PM PDT 24
Peak memory 205964 kb
Host smart-cfa16ff3-9a8d-44d3-8ee6-699f63015943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14318
47879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.1431847879
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.3565446701
Short name T2425
Test name
Test status
Simulation time 199454870 ps
CPU time 0.85 seconds
Started Jun 21 04:59:17 PM PDT 24
Finished Jun 21 04:59:21 PM PDT 24
Peak memory 206048 kb
Host smart-4e7b81f1-1ac8-4f99-b199-d188cdbc830e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35654
46701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3565446701
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2058492970
Short name T335
Test name
Test status
Simulation time 173543286 ps
CPU time 0.81 seconds
Started Jun 21 04:59:17 PM PDT 24
Finished Jun 21 04:59:20 PM PDT 24
Peak memory 206020 kb
Host smart-01ff8ddb-bcc7-461a-82f4-0635dfd262d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20584
92970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2058492970
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1438117793
Short name T545
Test name
Test status
Simulation time 149717138 ps
CPU time 0.84 seconds
Started Jun 21 04:59:18 PM PDT 24
Finished Jun 21 04:59:22 PM PDT 24
Peak memory 205960 kb
Host smart-8938d146-272d-4982-86e4-73bb16e2c24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14381
17793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1438117793
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1271620200
Short name T524
Test name
Test status
Simulation time 145991977 ps
CPU time 0.79 seconds
Started Jun 21 04:59:22 PM PDT 24
Finished Jun 21 04:59:25 PM PDT 24
Peak memory 206004 kb
Host smart-109bfd17-2707-454b-9172-1eb002241524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12716
20200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1271620200
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3215273181
Short name T2105
Test name
Test status
Simulation time 241347808 ps
CPU time 0.97 seconds
Started Jun 21 04:59:12 PM PDT 24
Finished Jun 21 04:59:16 PM PDT 24
Peak memory 205968 kb
Host smart-d353d21c-8bbb-4496-b6eb-e1bef9c0c5ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32152
73181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3215273181
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.3559332967
Short name T800
Test name
Test status
Simulation time 6156253873 ps
CPU time 172.45 seconds
Started Jun 21 04:59:17 PM PDT 24
Finished Jun 21 05:02:12 PM PDT 24
Peak memory 206168 kb
Host smart-8dd1fdbb-1170-49b5-83b9-4e73e26d6871
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3559332967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.3559332967
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.531282071
Short name T2336
Test name
Test status
Simulation time 178337587 ps
CPU time 0.78 seconds
Started Jun 21 04:59:21 PM PDT 24
Finished Jun 21 04:59:24 PM PDT 24
Peak memory 205960 kb
Host smart-26eb95c4-c447-473e-9706-a3551c34a544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53128
2071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.531282071
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3504531753
Short name T1401
Test name
Test status
Simulation time 167089230 ps
CPU time 0.83 seconds
Started Jun 21 04:59:17 PM PDT 24
Finished Jun 21 04:59:21 PM PDT 24
Peak memory 206016 kb
Host smart-cf70a884-4e08-4ee7-abb6-863b026398b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35045
31753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3504531753
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.1794329235
Short name T2298
Test name
Test status
Simulation time 3206621407 ps
CPU time 23.53 seconds
Started Jun 21 04:59:22 PM PDT 24
Finished Jun 21 04:59:48 PM PDT 24
Peak memory 206308 kb
Host smart-dfe08fef-2b75-4a60-a1ae-a8079e98f7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17943
29235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1794329235
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.1351947140
Short name T2401
Test name
Test status
Simulation time 4233728953 ps
CPU time 5.04 seconds
Started Jun 21 04:59:16 PM PDT 24
Finished Jun 21 04:59:24 PM PDT 24
Peak memory 206108 kb
Host smart-4e5f6edb-d942-4698-a096-581a5264c600
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1351947140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.1351947140
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.3081087872
Short name T193
Test name
Test status
Simulation time 13402928561 ps
CPU time 13.81 seconds
Started Jun 21 04:59:15 PM PDT 24
Finished Jun 21 04:59:33 PM PDT 24
Peak memory 206088 kb
Host smart-71ec02b2-2e7d-404e-a6ef-521889f17124
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3081087872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.3081087872
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.2620077611
Short name T2005
Test name
Test status
Simulation time 23355747301 ps
CPU time 22.33 seconds
Started Jun 21 04:59:21 PM PDT 24
Finished Jun 21 04:59:45 PM PDT 24
Peak memory 206276 kb
Host smart-fb831de4-2c67-40ee-8382-971af9bf444d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2620077611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.2620077611
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2568472214
Short name T1201
Test name
Test status
Simulation time 151346627 ps
CPU time 0.76 seconds
Started Jun 21 04:59:19 PM PDT 24
Finished Jun 21 04:59:22 PM PDT 24
Peak memory 206080 kb
Host smart-2f809333-bfbd-463a-8f3a-9490bd358184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25684
72214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2568472214
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3826394866
Short name T992
Test name
Test status
Simulation time 146081798 ps
CPU time 0.78 seconds
Started Jun 21 04:59:18 PM PDT 24
Finished Jun 21 04:59:22 PM PDT 24
Peak memory 205948 kb
Host smart-fbec9c6a-2f53-43a3-8f35-bb0208f2e8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38263
94866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3826394866
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.669229370
Short name T1810
Test name
Test status
Simulation time 385323686 ps
CPU time 1.35 seconds
Started Jun 21 04:59:19 PM PDT 24
Finished Jun 21 04:59:23 PM PDT 24
Peak memory 205932 kb
Host smart-ac6d79c5-c0e5-4272-a07b-5f261365f090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66922
9370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.669229370
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.4272522738
Short name T175
Test name
Test status
Simulation time 1434298647 ps
CPU time 2.99 seconds
Started Jun 21 04:59:27 PM PDT 24
Finished Jun 21 04:59:32 PM PDT 24
Peak memory 206172 kb
Host smart-89cd7051-6398-4791-b14b-5eef990f9547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42725
22738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.4272522738
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.1903706822
Short name T771
Test name
Test status
Simulation time 10958856347 ps
CPU time 22.34 seconds
Started Jun 21 04:59:23 PM PDT 24
Finished Jun 21 04:59:47 PM PDT 24
Peak memory 206332 kb
Host smart-771f237c-0107-4ed1-a837-618ec2eb78ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19037
06822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.1903706822
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.4214262242
Short name T1891
Test name
Test status
Simulation time 511611574 ps
CPU time 1.5 seconds
Started Jun 21 04:59:25 PM PDT 24
Finished Jun 21 04:59:30 PM PDT 24
Peak memory 205928 kb
Host smart-5119b5b9-55c6-4453-9742-cd5d66992a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42142
62242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.4214262242
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.3784506796
Short name T1562
Test name
Test status
Simulation time 139772896 ps
CPU time 0.84 seconds
Started Jun 21 04:59:26 PM PDT 24
Finished Jun 21 04:59:30 PM PDT 24
Peak memory 205932 kb
Host smart-70f6da00-0e15-42fd-9805-f5a1fe1f3366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37845
06796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.3784506796
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.1195404457
Short name T1897
Test name
Test status
Simulation time 35739138 ps
CPU time 0.64 seconds
Started Jun 21 04:59:25 PM PDT 24
Finished Jun 21 04:59:28 PM PDT 24
Peak memory 206016 kb
Host smart-ce11ec2f-7cce-4647-ac75-50f26f6b05de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11954
04457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1195404457
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2717704988
Short name T580
Test name
Test status
Simulation time 874327919 ps
CPU time 1.94 seconds
Started Jun 21 04:59:29 PM PDT 24
Finished Jun 21 04:59:33 PM PDT 24
Peak memory 206072 kb
Host smart-91b459df-c3c0-4baf-96ed-ef4d46e38cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27177
04988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2717704988
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1549776221
Short name T1149
Test name
Test status
Simulation time 206086488 ps
CPU time 1.28 seconds
Started Jun 21 04:59:26 PM PDT 24
Finished Jun 21 04:59:30 PM PDT 24
Peak memory 206196 kb
Host smart-0e3da7f5-555a-49d9-82e0-436cf89bdccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15497
76221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1549776221
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.267502573
Short name T2305
Test name
Test status
Simulation time 241840403 ps
CPU time 0.88 seconds
Started Jun 21 04:59:26 PM PDT 24
Finished Jun 21 04:59:30 PM PDT 24
Peak memory 205488 kb
Host smart-e3b80a35-57bb-48a3-a1dc-655b613234c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26750
2573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.267502573
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.4259450269
Short name T1882
Test name
Test status
Simulation time 162197412 ps
CPU time 0.74 seconds
Started Jun 21 04:59:23 PM PDT 24
Finished Jun 21 04:59:27 PM PDT 24
Peak memory 206016 kb
Host smart-b3b0887a-1c9f-464b-8a72-c8d4c3ab5c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42594
50269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.4259450269
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.542145647
Short name T381
Test name
Test status
Simulation time 241900786 ps
CPU time 0.93 seconds
Started Jun 21 04:59:25 PM PDT 24
Finished Jun 21 04:59:29 PM PDT 24
Peak memory 206024 kb
Host smart-aee51b49-0c3a-4677-aa54-763a67ae80af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54214
5647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.542145647
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.11136110
Short name T657
Test name
Test status
Simulation time 216161426 ps
CPU time 0.92 seconds
Started Jun 21 04:59:25 PM PDT 24
Finished Jun 21 04:59:29 PM PDT 24
Peak memory 205976 kb
Host smart-8b2d218e-b350-4d9e-bea1-3f891a586296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11136
110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.11136110
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.1122729296
Short name T1243
Test name
Test status
Simulation time 23345870520 ps
CPU time 21.79 seconds
Started Jun 21 04:59:29 PM PDT 24
Finished Jun 21 04:59:53 PM PDT 24
Peak memory 206084 kb
Host smart-b13c7fb0-dacf-4e94-a3ca-f45822c6ba04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11227
29296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.1122729296
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.4047289226
Short name T215
Test name
Test status
Simulation time 3342289100 ps
CPU time 3.5 seconds
Started Jun 21 04:59:24 PM PDT 24
Finished Jun 21 04:59:30 PM PDT 24
Peak memory 206088 kb
Host smart-33a2ab0a-656d-4416-87ce-b2397aab66c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40472
89226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.4047289226
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.2844487977
Short name T1183
Test name
Test status
Simulation time 9209053346 ps
CPU time 63.88 seconds
Started Jun 21 04:59:29 PM PDT 24
Finished Jun 21 05:00:35 PM PDT 24
Peak memory 206256 kb
Host smart-177a498a-2e99-45f8-8ab3-f6b834e4d7ba
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2844487977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.2844487977
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.803714222
Short name T1597
Test name
Test status
Simulation time 246091559 ps
CPU time 0.94 seconds
Started Jun 21 04:59:24 PM PDT 24
Finished Jun 21 04:59:28 PM PDT 24
Peak memory 206028 kb
Host smart-b555d601-c664-4ed5-baf9-05c6eb427fb0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=803714222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.803714222
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.912703292
Short name T1785
Test name
Test status
Simulation time 218124216 ps
CPU time 0.91 seconds
Started Jun 21 04:59:25 PM PDT 24
Finished Jun 21 04:59:29 PM PDT 24
Peak memory 206052 kb
Host smart-d13b878b-48d0-46cb-b92d-ae159c5ab254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91270
3292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.912703292
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.141557405
Short name T926
Test name
Test status
Simulation time 8936665426 ps
CPU time 247.55 seconds
Started Jun 21 04:59:24 PM PDT 24
Finished Jun 21 05:03:34 PM PDT 24
Peak memory 206164 kb
Host smart-6e3e0a49-be69-4771-8b09-60ff41d861aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14155
7405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.141557405
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.2777372351
Short name T448
Test name
Test status
Simulation time 7915030643 ps
CPU time 220.84 seconds
Started Jun 21 04:59:25 PM PDT 24
Finished Jun 21 05:03:09 PM PDT 24
Peak memory 206272 kb
Host smart-da8dd8c3-0133-4876-8551-4436828b872c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2777372351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.2777372351
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.1792386444
Short name T2494
Test name
Test status
Simulation time 157511082 ps
CPU time 0.84 seconds
Started Jun 21 04:59:27 PM PDT 24
Finished Jun 21 04:59:31 PM PDT 24
Peak memory 205580 kb
Host smart-8d2898cf-78b6-44ce-b2a6-8340f41018da
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1792386444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.1792386444
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.1774066543
Short name T477
Test name
Test status
Simulation time 146487611 ps
CPU time 0.78 seconds
Started Jun 21 04:59:28 PM PDT 24
Finished Jun 21 04:59:31 PM PDT 24
Peak memory 205968 kb
Host smart-23ee06d6-4d1f-45d0-9af0-0fb6572c0a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17740
66543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.1774066543
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2982063491
Short name T149
Test name
Test status
Simulation time 184364141 ps
CPU time 0.8 seconds
Started Jun 21 04:59:25 PM PDT 24
Finished Jun 21 04:59:29 PM PDT 24
Peak memory 206024 kb
Host smart-89e9b213-be85-4166-8d1f-2802b40d67b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29820
63491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2982063491
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.445571526
Short name T1576
Test name
Test status
Simulation time 196765178 ps
CPU time 0.85 seconds
Started Jun 21 04:59:26 PM PDT 24
Finished Jun 21 04:59:30 PM PDT 24
Peak memory 205116 kb
Host smart-9d5e6384-9d68-4fbf-bd74-1173766368b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44557
1526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.445571526
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3555338278
Short name T1906
Test name
Test status
Simulation time 200142929 ps
CPU time 0.82 seconds
Started Jun 21 04:59:26 PM PDT 24
Finished Jun 21 04:59:30 PM PDT 24
Peak memory 205964 kb
Host smart-767c8823-9543-4983-b421-29977ad0ce1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35553
38278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3555338278
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1607973772
Short name T1854
Test name
Test status
Simulation time 209068681 ps
CPU time 0.89 seconds
Started Jun 21 04:59:25 PM PDT 24
Finished Jun 21 04:59:29 PM PDT 24
Peak memory 206020 kb
Host smart-b8492599-61cc-4d58-b2ec-530b0d60f669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16079
73772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1607973772
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3376908140
Short name T1246
Test name
Test status
Simulation time 146876223 ps
CPU time 0.79 seconds
Started Jun 21 04:59:29 PM PDT 24
Finished Jun 21 04:59:31 PM PDT 24
Peak memory 206020 kb
Host smart-fb70433f-a2d7-4e7d-9114-1a5c0c5bcb8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33769
08140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3376908140
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.959359135
Short name T2409
Test name
Test status
Simulation time 176520059 ps
CPU time 0.83 seconds
Started Jun 21 04:59:24 PM PDT 24
Finished Jun 21 04:59:28 PM PDT 24
Peak memory 205984 kb
Host smart-4684c73f-2610-4d17-8b19-f4367e4e6591
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=959359135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.959359135
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.2719499530
Short name T36
Test name
Test status
Simulation time 153587768 ps
CPU time 0.81 seconds
Started Jun 21 04:59:23 PM PDT 24
Finished Jun 21 04:59:26 PM PDT 24
Peak memory 206004 kb
Host smart-822daf5d-9646-4202-9d99-575d44b99db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27194
99530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.2719499530
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.31379356
Short name T1119
Test name
Test status
Simulation time 69899641 ps
CPU time 0.71 seconds
Started Jun 21 04:59:23 PM PDT 24
Finished Jun 21 04:59:26 PM PDT 24
Peak memory 206012 kb
Host smart-cf149fb0-e81a-4478-b9e5-ec878a4b5415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31379
356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.31379356
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3041432134
Short name T2152
Test name
Test status
Simulation time 20591633872 ps
CPU time 45.7 seconds
Started Jun 21 04:59:25 PM PDT 24
Finished Jun 21 05:00:13 PM PDT 24
Peak memory 206316 kb
Host smart-be1cb418-111c-41c2-9f45-940f8985ff7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30414
32134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3041432134
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.351975872
Short name T493
Test name
Test status
Simulation time 166107344 ps
CPU time 0.83 seconds
Started Jun 21 04:59:25 PM PDT 24
Finished Jun 21 04:59:29 PM PDT 24
Peak memory 206028 kb
Host smart-677cc524-dda1-48bf-a04c-4b1b0d7774f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35197
5872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.351975872
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1895298910
Short name T2439
Test name
Test status
Simulation time 214357469 ps
CPU time 0.88 seconds
Started Jun 21 04:59:26 PM PDT 24
Finished Jun 21 04:59:30 PM PDT 24
Peak memory 205968 kb
Host smart-f1f5184f-2dad-4444-b0bd-ca9770b5d524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18952
98910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1895298910
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.2792230385
Short name T954
Test name
Test status
Simulation time 189610426 ps
CPU time 0.81 seconds
Started Jun 21 04:59:28 PM PDT 24
Finished Jun 21 04:59:31 PM PDT 24
Peak memory 205968 kb
Host smart-b556c836-01be-48b3-bcba-a3461b69adbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27922
30385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.2792230385
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.2981737439
Short name T1347
Test name
Test status
Simulation time 208155548 ps
CPU time 0.89 seconds
Started Jun 21 04:59:23 PM PDT 24
Finished Jun 21 04:59:28 PM PDT 24
Peak memory 205984 kb
Host smart-e3130f76-13a4-4372-9a44-bf284de94a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29817
37439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.2981737439
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2096310400
Short name T670
Test name
Test status
Simulation time 254633758 ps
CPU time 0.87 seconds
Started Jun 21 04:59:25 PM PDT 24
Finished Jun 21 04:59:29 PM PDT 24
Peak memory 206016 kb
Host smart-05d175e6-bdeb-435e-9f2d-999b01081916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20963
10400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2096310400
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.2645810514
Short name T446
Test name
Test status
Simulation time 145006337 ps
CPU time 0.77 seconds
Started Jun 21 04:59:23 PM PDT 24
Finished Jun 21 04:59:27 PM PDT 24
Peak memory 205952 kb
Host smart-fcce68dc-8ba7-43ed-b109-bbc7942f79ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26458
10514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.2645810514
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1510206988
Short name T338
Test name
Test status
Simulation time 152600891 ps
CPU time 0.82 seconds
Started Jun 21 04:59:25 PM PDT 24
Finished Jun 21 04:59:29 PM PDT 24
Peak memory 206028 kb
Host smart-7bd6dbbf-f2ee-4525-bab8-65d867797752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15102
06988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1510206988
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2952896654
Short name T2261
Test name
Test status
Simulation time 233211648 ps
CPU time 1.01 seconds
Started Jun 21 04:59:15 PM PDT 24
Finished Jun 21 04:59:20 PM PDT 24
Peak memory 205972 kb
Host smart-4e793bd9-2d30-4563-90c9-a1fd135c806f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29528
96654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2952896654
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.3044523778
Short name T1747
Test name
Test status
Simulation time 4374603814 ps
CPU time 123.71 seconds
Started Jun 21 04:59:25 PM PDT 24
Finished Jun 21 05:01:32 PM PDT 24
Peak memory 206160 kb
Host smart-4dfb3e4a-04e4-4931-ad5b-a4b0ee751fdb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3044523778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.3044523778
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1266958409
Short name T572
Test name
Test status
Simulation time 178349456 ps
CPU time 0.8 seconds
Started Jun 21 04:59:26 PM PDT 24
Finished Jun 21 04:59:29 PM PDT 24
Peak memory 205968 kb
Host smart-d3e0409b-1ea7-4a6c-900d-d5af057ede64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12669
58409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1266958409
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.549620233
Short name T453
Test name
Test status
Simulation time 182699935 ps
CPU time 0.8 seconds
Started Jun 21 04:59:25 PM PDT 24
Finished Jun 21 04:59:29 PM PDT 24
Peak memory 205924 kb
Host smart-5fcc05ed-dedf-4611-a19f-2b656fb39470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54962
0233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.549620233
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.2171129702
Short name T1218
Test name
Test status
Simulation time 3033251547 ps
CPU time 79.54 seconds
Started Jun 21 04:59:26 PM PDT 24
Finished Jun 21 05:00:49 PM PDT 24
Peak memory 205604 kb
Host smart-b138e853-fa71-4c61-9fd5-7ecb963b798b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21711
29702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.2171129702
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3337947520
Short name T1128
Test name
Test status
Simulation time 3931842458 ps
CPU time 4.41 seconds
Started Jun 21 04:59:27 PM PDT 24
Finished Jun 21 04:59:34 PM PDT 24
Peak memory 205732 kb
Host smart-7c9892f2-efb0-4e12-98cf-e16e51999b94
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3337947520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.3337947520
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.2009675985
Short name T2051
Test name
Test status
Simulation time 13381248158 ps
CPU time 12.34 seconds
Started Jun 21 04:59:30 PM PDT 24
Finished Jun 21 04:59:44 PM PDT 24
Peak memory 206100 kb
Host smart-19e279f2-8a59-46f0-a67b-ba52e2ed8845
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2009675985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.2009675985
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.1329923439
Short name T2297
Test name
Test status
Simulation time 23512397297 ps
CPU time 22.49 seconds
Started Jun 21 04:59:31 PM PDT 24
Finished Jun 21 04:59:54 PM PDT 24
Peak memory 206248 kb
Host smart-39fd1db3-a0ed-4066-93e3-4ef03fc1bff4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1329923439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.1329923439
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1681521924
Short name T489
Test name
Test status
Simulation time 156191218 ps
CPU time 0.78 seconds
Started Jun 21 04:59:30 PM PDT 24
Finished Jun 21 04:59:32 PM PDT 24
Peak memory 206028 kb
Host smart-8ac46a6f-5747-4150-b50f-c1a41f8c6bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16815
21924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1681521924
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.1273819897
Short name T2243
Test name
Test status
Simulation time 159439115 ps
CPU time 0.79 seconds
Started Jun 21 04:59:44 PM PDT 24
Finished Jun 21 04:59:47 PM PDT 24
Peak memory 206024 kb
Host smart-0d67af23-b315-4e15-a519-2d3efc881f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12738
19897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.1273819897
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.1421200659
Short name T112
Test name
Test status
Simulation time 345626375 ps
CPU time 1.29 seconds
Started Jun 21 04:59:35 PM PDT 24
Finished Jun 21 04:59:37 PM PDT 24
Peak memory 205932 kb
Host smart-b40a0634-8972-4560-aa32-562fa717adff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14212
00659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.1421200659
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.180701809
Short name T1633
Test name
Test status
Simulation time 307137570 ps
CPU time 0.97 seconds
Started Jun 21 04:59:43 PM PDT 24
Finished Jun 21 04:59:46 PM PDT 24
Peak memory 205956 kb
Host smart-9ed6bcf3-d972-4905-9439-23d64dd45528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18070
1809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.180701809
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.3617511787
Short name T1139
Test name
Test status
Simulation time 23648071210 ps
CPU time 47.68 seconds
Started Jun 21 04:59:29 PM PDT 24
Finished Jun 21 05:00:19 PM PDT 24
Peak memory 206260 kb
Host smart-ec278dbf-bf5a-40e8-9d27-b1f416230837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36175
11787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.3617511787
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.3670225070
Short name T920
Test name
Test status
Simulation time 419991348 ps
CPU time 1.42 seconds
Started Jun 21 04:59:37 PM PDT 24
Finished Jun 21 04:59:39 PM PDT 24
Peak memory 205928 kb
Host smart-fecf137e-a8a9-4594-9ac9-6440c143116c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36702
25070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.3670225070
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2676010949
Short name T2274
Test name
Test status
Simulation time 138152161 ps
CPU time 0.74 seconds
Started Jun 21 04:59:32 PM PDT 24
Finished Jun 21 04:59:35 PM PDT 24
Peak memory 205996 kb
Host smart-993d84bd-dcf5-4262-b0de-a6d899afb7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26760
10949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2676010949
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.473040186
Short name T2389
Test name
Test status
Simulation time 41516863 ps
CPU time 0.69 seconds
Started Jun 21 04:59:47 PM PDT 24
Finished Jun 21 04:59:50 PM PDT 24
Peak memory 206016 kb
Host smart-5f560525-d8e0-44ae-9f85-d4b7c2d7340f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47304
0186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.473040186
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.1992728352
Short name T825
Test name
Test status
Simulation time 913769592 ps
CPU time 2.22 seconds
Started Jun 21 04:59:48 PM PDT 24
Finished Jun 21 04:59:53 PM PDT 24
Peak memory 206220 kb
Host smart-e9c72989-2bdb-41ec-8701-8499ac4b28bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19927
28352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.1992728352
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2077479875
Short name T1574
Test name
Test status
Simulation time 146619514 ps
CPU time 1.37 seconds
Started Jun 21 04:59:35 PM PDT 24
Finished Jun 21 04:59:38 PM PDT 24
Peak memory 206296 kb
Host smart-862e9ef0-f5fc-42de-950b-1236ab24f50f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20774
79875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2077479875
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2198761095
Short name T505
Test name
Test status
Simulation time 189293523 ps
CPU time 0.83 seconds
Started Jun 21 04:59:35 PM PDT 24
Finished Jun 21 04:59:37 PM PDT 24
Peak memory 205968 kb
Host smart-1aba2350-2c95-4ecb-b143-ee6f127428f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21987
61095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2198761095
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1999509631
Short name T697
Test name
Test status
Simulation time 159471133 ps
CPU time 0.78 seconds
Started Jun 21 04:59:34 PM PDT 24
Finished Jun 21 04:59:36 PM PDT 24
Peak memory 205972 kb
Host smart-c3f854e7-9e32-4cb3-b90d-df33b0e0195c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19995
09631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1999509631
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.811907119
Short name T1862
Test name
Test status
Simulation time 227101911 ps
CPU time 0.95 seconds
Started Jun 21 04:59:53 PM PDT 24
Finished Jun 21 04:59:57 PM PDT 24
Peak memory 206024 kb
Host smart-c82d1f79-f370-40ce-9f2e-b98be755cfe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81190
7119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.811907119
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.1645882585
Short name T1310
Test name
Test status
Simulation time 5453094764 ps
CPU time 50.46 seconds
Started Jun 21 04:59:35 PM PDT 24
Finished Jun 21 05:00:26 PM PDT 24
Peak memory 206260 kb
Host smart-7445bb54-ca9e-46a0-a0cc-c15e16fd29db
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1645882585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.1645882585
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.1717400100
Short name T2007
Test name
Test status
Simulation time 185466395 ps
CPU time 0.8 seconds
Started Jun 21 04:59:32 PM PDT 24
Finished Jun 21 04:59:35 PM PDT 24
Peak memory 206020 kb
Host smart-9540d333-e547-4b9f-bc25-93fef6742107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17174
00100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.1717400100
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.166492896
Short name T1342
Test name
Test status
Simulation time 23343331085 ps
CPU time 22.49 seconds
Started Jun 21 04:59:44 PM PDT 24
Finished Jun 21 05:00:09 PM PDT 24
Peak memory 206084 kb
Host smart-01983a09-ae09-4a02-8453-43264d8d9d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16649
2896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.166492896
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.3719520827
Short name T2456
Test name
Test status
Simulation time 3279478277 ps
CPU time 3.89 seconds
Started Jun 21 04:59:47 PM PDT 24
Finished Jun 21 04:59:53 PM PDT 24
Peak memory 206084 kb
Host smart-2e75c188-1646-475a-b937-5c5b167ed6b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37195
20827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3719520827
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3283004244
Short name T664
Test name
Test status
Simulation time 9255884799 ps
CPU time 263.08 seconds
Started Jun 21 04:59:34 PM PDT 24
Finished Jun 21 05:03:59 PM PDT 24
Peak memory 206236 kb
Host smart-919db2fd-f305-40cb-ac0a-028da2a681e0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3283004244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3283004244
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.80379752
Short name T1153
Test name
Test status
Simulation time 271345070 ps
CPU time 0.93 seconds
Started Jun 21 04:59:32 PM PDT 24
Finished Jun 21 04:59:35 PM PDT 24
Peak memory 206048 kb
Host smart-f1144294-dc5a-40e2-84a9-bbda95d568ed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=80379752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.80379752
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2454306689
Short name T1927
Test name
Test status
Simulation time 212981444 ps
CPU time 0.9 seconds
Started Jun 21 04:59:43 PM PDT 24
Finished Jun 21 04:59:46 PM PDT 24
Peak memory 206032 kb
Host smart-ed8a27ed-5427-4eba-bf7f-5997bfdbb1e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24543
06689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2454306689
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.1545734637
Short name T2102
Test name
Test status
Simulation time 11830105133 ps
CPU time 330.16 seconds
Started Jun 21 04:59:35 PM PDT 24
Finished Jun 21 05:05:06 PM PDT 24
Peak memory 206236 kb
Host smart-d530d347-d01e-478d-baf3-89e2f517e76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15457
34637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.1545734637
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.2583997323
Short name T1130
Test name
Test status
Simulation time 12645462625 ps
CPU time 85.13 seconds
Started Jun 21 04:59:33 PM PDT 24
Finished Jun 21 05:01:00 PM PDT 24
Peak memory 206224 kb
Host smart-555bc9df-2588-46a3-b85f-b29bd33f2647
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2583997323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.2583997323
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.1234423604
Short name T415
Test name
Test status
Simulation time 150061788 ps
CPU time 0.84 seconds
Started Jun 21 04:59:34 PM PDT 24
Finished Jun 21 04:59:36 PM PDT 24
Peak memory 205952 kb
Host smart-d748eef9-153d-4e5e-b6b8-457ee28c454a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1234423604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1234423604
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.305375860
Short name T1069
Test name
Test status
Simulation time 173821647 ps
CPU time 0.79 seconds
Started Jun 21 04:59:39 PM PDT 24
Finished Jun 21 04:59:42 PM PDT 24
Peak memory 205952 kb
Host smart-42793e8f-57b0-4941-bb1e-7b6c3412bd25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30537
5860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.305375860
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.726293615
Short name T146
Test name
Test status
Simulation time 188704705 ps
CPU time 0.81 seconds
Started Jun 21 04:59:32 PM PDT 24
Finished Jun 21 04:59:34 PM PDT 24
Peak memory 205996 kb
Host smart-49947841-ddce-45e6-81f3-89e29151a822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72629
3615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.726293615
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.2727577848
Short name T760
Test name
Test status
Simulation time 222808371 ps
CPU time 0.84 seconds
Started Jun 21 04:59:45 PM PDT 24
Finished Jun 21 04:59:48 PM PDT 24
Peak memory 206020 kb
Host smart-cfc41132-af82-4d66-b793-82e61605a6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27275
77848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.2727577848
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.2205608836
Short name T219
Test name
Test status
Simulation time 165611395 ps
CPU time 0.79 seconds
Started Jun 21 04:59:31 PM PDT 24
Finished Jun 21 04:59:33 PM PDT 24
Peak memory 206000 kb
Host smart-b2a54a8a-f3e0-4bbd-8cc9-d0df8c9a8d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22056
08836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.2205608836
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3588795090
Short name T1005
Test name
Test status
Simulation time 207550392 ps
CPU time 0.85 seconds
Started Jun 21 04:59:35 PM PDT 24
Finished Jun 21 04:59:37 PM PDT 24
Peak memory 206044 kb
Host smart-c30c2159-ba23-4f37-bd74-c9f73eec3eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35887
95090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3588795090
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.459452731
Short name T1975
Test name
Test status
Simulation time 173312857 ps
CPU time 0.87 seconds
Started Jun 21 04:59:43 PM PDT 24
Finished Jun 21 04:59:45 PM PDT 24
Peak memory 206024 kb
Host smart-fe1e8872-b94a-40b4-bd13-a4060dcab77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45945
2731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.459452731
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.1872720196
Short name T427
Test name
Test status
Simulation time 238644611 ps
CPU time 0.97 seconds
Started Jun 21 04:59:33 PM PDT 24
Finished Jun 21 04:59:35 PM PDT 24
Peak memory 205984 kb
Host smart-bb82b690-e294-4e5e-b3c4-b5f490d5f842
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1872720196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.1872720196
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.728039740
Short name T533
Test name
Test status
Simulation time 145273543 ps
CPU time 0.75 seconds
Started Jun 21 04:59:41 PM PDT 24
Finished Jun 21 04:59:45 PM PDT 24
Peak memory 206048 kb
Host smart-3beefeef-6b68-443d-94da-54ebda91ef59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72803
9740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.728039740
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.188779675
Short name T2304
Test name
Test status
Simulation time 43351971 ps
CPU time 0.65 seconds
Started Jun 21 04:59:33 PM PDT 24
Finished Jun 21 04:59:35 PM PDT 24
Peak memory 205972 kb
Host smart-7c9035e9-f8c1-4efb-8f19-4ff1cddc9b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18877
9675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.188779675
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1220296867
Short name T72
Test name
Test status
Simulation time 12899875484 ps
CPU time 28.09 seconds
Started Jun 21 04:59:32 PM PDT 24
Finished Jun 21 05:00:02 PM PDT 24
Peak memory 206304 kb
Host smart-5f706045-743e-4ee3-a5e1-7149e8c820e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12202
96867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1220296867
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.1418268430
Short name T2139
Test name
Test status
Simulation time 154312485 ps
CPU time 0.78 seconds
Started Jun 21 04:59:31 PM PDT 24
Finished Jun 21 04:59:33 PM PDT 24
Peak memory 205968 kb
Host smart-a4490542-580f-464b-b21e-136eea787e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14182
68430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.1418268430
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.4019541820
Short name T347
Test name
Test status
Simulation time 169231139 ps
CPU time 0.78 seconds
Started Jun 21 04:59:33 PM PDT 24
Finished Jun 21 04:59:35 PM PDT 24
Peak memory 205988 kb
Host smart-9061d14a-d588-484f-962b-01c6209e246d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40195
41820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.4019541820
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.1904128163
Short name T380
Test name
Test status
Simulation time 200150913 ps
CPU time 0.85 seconds
Started Jun 21 04:59:53 PM PDT 24
Finished Jun 21 04:59:57 PM PDT 24
Peak memory 206008 kb
Host smart-e049fc09-62f5-4478-a08c-80665844f173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19041
28163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.1904128163
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3525834824
Short name T2219
Test name
Test status
Simulation time 216807752 ps
CPU time 0.91 seconds
Started Jun 21 04:59:31 PM PDT 24
Finished Jun 21 04:59:33 PM PDT 24
Peak memory 205988 kb
Host smart-874537f6-ec13-4944-8593-88a076793b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35258
34824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3525834824
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.541748502
Short name T1039
Test name
Test status
Simulation time 142147912 ps
CPU time 0.81 seconds
Started Jun 21 04:59:31 PM PDT 24
Finished Jun 21 04:59:33 PM PDT 24
Peak memory 206004 kb
Host smart-91461d7e-2045-4644-a5af-71e25ecde4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54174
8502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.541748502
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.1967455438
Short name T2063
Test name
Test status
Simulation time 185420712 ps
CPU time 0.84 seconds
Started Jun 21 04:59:40 PM PDT 24
Finished Jun 21 04:59:44 PM PDT 24
Peak memory 206000 kb
Host smart-8b91582d-2f4c-4204-a734-dbe178632bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19674
55438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.1967455438
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1156703035
Short name T1154
Test name
Test status
Simulation time 151242509 ps
CPU time 0.77 seconds
Started Jun 21 04:59:30 PM PDT 24
Finished Jun 21 04:59:32 PM PDT 24
Peak memory 206004 kb
Host smart-8e0569df-8d51-4c71-8634-53faa6ae98c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11567
03035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1156703035
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.218854548
Short name T1578
Test name
Test status
Simulation time 236160443 ps
CPU time 0.94 seconds
Started Jun 21 04:59:29 PM PDT 24
Finished Jun 21 04:59:31 PM PDT 24
Peak memory 206028 kb
Host smart-f4818172-1927-473b-803a-ca52f3d3a996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21885
4548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.218854548
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.1577139713
Short name T1143
Test name
Test status
Simulation time 6792632348 ps
CPU time 61.62 seconds
Started Jun 21 04:59:35 PM PDT 24
Finished Jun 21 05:00:37 PM PDT 24
Peak memory 206280 kb
Host smart-8e2dc7cf-3119-4f42-aa5d-bdab19bf12f3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1577139713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.1577139713
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1288278325
Short name T1356
Test name
Test status
Simulation time 157531195 ps
CPU time 0.77 seconds
Started Jun 21 04:59:44 PM PDT 24
Finished Jun 21 04:59:48 PM PDT 24
Peak memory 206028 kb
Host smart-9ada8f02-1b41-438d-86a5-ddcf17956746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12882
78325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1288278325
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3947430173
Short name T1284
Test name
Test status
Simulation time 199711693 ps
CPU time 0.84 seconds
Started Jun 21 04:59:32 PM PDT 24
Finished Jun 21 04:59:35 PM PDT 24
Peak memory 205968 kb
Host smart-ab58c36e-58bc-44c4-902e-983544644878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39474
30173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3947430173
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3021072409
Short name T675
Test name
Test status
Simulation time 6838730140 ps
CPU time 197.54 seconds
Started Jun 21 04:59:30 PM PDT 24
Finished Jun 21 05:02:49 PM PDT 24
Peak memory 206176 kb
Host smart-27899f4a-4fee-4bb6-a94d-2ecfd84248ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30210
72409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3021072409
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1756767647
Short name T1055
Test name
Test status
Simulation time 4364623673 ps
CPU time 4.88 seconds
Started Jun 21 04:59:35 PM PDT 24
Finished Jun 21 04:59:41 PM PDT 24
Peak memory 206432 kb
Host smart-6d8e0f4a-58ba-4c68-929d-e9943694a69a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1756767647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1756767647
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.2067162841
Short name T710
Test name
Test status
Simulation time 13379776292 ps
CPU time 12.74 seconds
Started Jun 21 04:59:48 PM PDT 24
Finished Jun 21 05:00:03 PM PDT 24
Peak memory 206244 kb
Host smart-5812c003-b6d5-4449-b86e-f65daa752d2a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2067162841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.2067162841
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.4088772881
Short name T472
Test name
Test status
Simulation time 23380017777 ps
CPU time 25.01 seconds
Started Jun 21 04:59:46 PM PDT 24
Finished Jun 21 05:00:13 PM PDT 24
Peak memory 206092 kb
Host smart-ae7a2a2f-c489-4236-a40c-85492b8cad9c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4088772881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.4088772881
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.563539321
Short name T1029
Test name
Test status
Simulation time 178773995 ps
CPU time 0.79 seconds
Started Jun 21 04:59:46 PM PDT 24
Finished Jun 21 04:59:49 PM PDT 24
Peak memory 206020 kb
Host smart-c4632292-6506-49ff-954c-989b3d299fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56353
9321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.563539321
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.1262474265
Short name T602
Test name
Test status
Simulation time 154857714 ps
CPU time 0.78 seconds
Started Jun 21 04:59:50 PM PDT 24
Finished Jun 21 04:59:53 PM PDT 24
Peak memory 206036 kb
Host smart-96ea9b44-016e-44c9-8a9c-e79e65ff0839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12624
74265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.1262474265
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.3421653259
Short name T699
Test name
Test status
Simulation time 562121219 ps
CPU time 1.67 seconds
Started Jun 21 04:59:39 PM PDT 24
Finished Jun 21 04:59:43 PM PDT 24
Peak memory 206192 kb
Host smart-5e60d1d4-7b84-462d-b6cd-f826968822fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34216
53259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.3421653259
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.306406325
Short name T1482
Test name
Test status
Simulation time 355852109 ps
CPU time 1.11 seconds
Started Jun 21 04:59:38 PM PDT 24
Finished Jun 21 04:59:41 PM PDT 24
Peak memory 206040 kb
Host smart-5186195b-4496-4683-aeba-981f1928bf5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30640
6325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.306406325
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3235163447
Short name T187
Test name
Test status
Simulation time 7560044414 ps
CPU time 15.55 seconds
Started Jun 21 04:59:41 PM PDT 24
Finished Jun 21 04:59:59 PM PDT 24
Peak memory 206356 kb
Host smart-71401067-dea4-4636-a2a9-27ade45e15e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32351
63447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3235163447
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2011561537
Short name T564
Test name
Test status
Simulation time 382493493 ps
CPU time 1.16 seconds
Started Jun 21 04:59:48 PM PDT 24
Finished Jun 21 04:59:51 PM PDT 24
Peak memory 206008 kb
Host smart-b9f64a69-3e14-4892-9a91-30e5c3f7a292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20115
61537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2011561537
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3304559633
Short name T2043
Test name
Test status
Simulation time 186402761 ps
CPU time 0.78 seconds
Started Jun 21 04:59:50 PM PDT 24
Finished Jun 21 04:59:53 PM PDT 24
Peak memory 206016 kb
Host smart-9e15348f-71ae-4c5b-b82d-3d451b17244d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33045
59633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3304559633
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.2817471263
Short name T2174
Test name
Test status
Simulation time 41685788 ps
CPU time 0.66 seconds
Started Jun 21 04:59:51 PM PDT 24
Finished Jun 21 04:59:54 PM PDT 24
Peak memory 205960 kb
Host smart-4fc4eb9a-e1f1-45c3-b540-c41887fed704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28174
71263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2817471263
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2977233388
Short name T2377
Test name
Test status
Simulation time 937656517 ps
CPU time 1.96 seconds
Started Jun 21 04:59:37 PM PDT 24
Finished Jun 21 04:59:40 PM PDT 24
Peak memory 206168 kb
Host smart-a17d05ba-5784-4cc8-96f4-84fc29728e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29772
33388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2977233388
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1690985580
Short name T2282
Test name
Test status
Simulation time 198114215 ps
CPU time 1.21 seconds
Started Jun 21 04:59:49 PM PDT 24
Finished Jun 21 04:59:52 PM PDT 24
Peak memory 206180 kb
Host smart-71dc2e75-f8e9-429c-85f0-743f186aa31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16909
85580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1690985580
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.514327298
Short name T1215
Test name
Test status
Simulation time 156263258 ps
CPU time 0.81 seconds
Started Jun 21 04:59:52 PM PDT 24
Finished Jun 21 04:59:56 PM PDT 24
Peak memory 205972 kb
Host smart-62a0ede0-0540-42f0-a9a5-029767668e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51432
7298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.514327298
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2943825796
Short name T1622
Test name
Test status
Simulation time 166332336 ps
CPU time 0.78 seconds
Started Jun 21 04:59:41 PM PDT 24
Finished Jun 21 04:59:45 PM PDT 24
Peak memory 206016 kb
Host smart-9d32ac1c-adbe-48f1-98d3-5ba2f7f68862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29438
25796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2943825796
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1188166303
Short name T1613
Test name
Test status
Simulation time 183634470 ps
CPU time 0.9 seconds
Started Jun 21 04:59:41 PM PDT 24
Finished Jun 21 04:59:45 PM PDT 24
Peak memory 206024 kb
Host smart-9a32e081-db5d-4258-82db-5fab4b37a1dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11881
66303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1188166303
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.2999034289
Short name T2473
Test name
Test status
Simulation time 5344632309 ps
CPU time 39.09 seconds
Started Jun 21 04:59:51 PM PDT 24
Finished Jun 21 05:00:32 PM PDT 24
Peak memory 206212 kb
Host smart-9b6b180c-9f5f-4876-8241-3feb2e98f4a4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2999034289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.2999034289
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.38328960
Short name T1156
Test name
Test status
Simulation time 273350914 ps
CPU time 1 seconds
Started Jun 21 04:59:38 PM PDT 24
Finished Jun 21 04:59:40 PM PDT 24
Peak memory 206040 kb
Host smart-46cbbfca-9c28-43c8-bf32-1d0c377e58b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38328
960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.38328960
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.4128439533
Short name T1823
Test name
Test status
Simulation time 23291776434 ps
CPU time 24.09 seconds
Started Jun 21 04:59:39 PM PDT 24
Finished Jun 21 05:00:04 PM PDT 24
Peak memory 205992 kb
Host smart-9e38b6f3-1059-4338-aac6-dd6315ed7e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41284
39533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.4128439533
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.1566628611
Short name T1377
Test name
Test status
Simulation time 3341484907 ps
CPU time 3.79 seconds
Started Jun 21 04:59:54 PM PDT 24
Finished Jun 21 05:00:01 PM PDT 24
Peak memory 206032 kb
Host smart-b63aea16-e7c3-4196-a334-467eb1a2f0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15666
28611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.1566628611
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3632457126
Short name T513
Test name
Test status
Simulation time 8538159616 ps
CPU time 80.07 seconds
Started Jun 21 04:59:39 PM PDT 24
Finished Jun 21 05:01:00 PM PDT 24
Peak memory 206272 kb
Host smart-502b2b7a-9c3f-4477-b149-145ef72a464f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3632457126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3632457126
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.3642928038
Short name T817
Test name
Test status
Simulation time 319648380 ps
CPU time 1 seconds
Started Jun 21 04:59:41 PM PDT 24
Finished Jun 21 04:59:44 PM PDT 24
Peak memory 206028 kb
Host smart-ce700941-044d-49b6-941e-024cab95a312
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3642928038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.3642928038
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3885640866
Short name T2177
Test name
Test status
Simulation time 193039698 ps
CPU time 0.89 seconds
Started Jun 21 04:59:49 PM PDT 24
Finished Jun 21 04:59:52 PM PDT 24
Peak memory 205944 kb
Host smart-1dd83a6e-2263-457f-9431-00318a2f21df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38856
40866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3885640866
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.2327429876
Short name T1299
Test name
Test status
Simulation time 11050096317 ps
CPU time 88.49 seconds
Started Jun 21 04:59:38 PM PDT 24
Finished Jun 21 05:01:08 PM PDT 24
Peak memory 206216 kb
Host smart-c63616aa-da97-4e2d-9b3b-98c6f373213b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23274
29876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.2327429876
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.24624082
Short name T1759
Test name
Test status
Simulation time 5950400463 ps
CPU time 158.23 seconds
Started Jun 21 04:59:53 PM PDT 24
Finished Jun 21 05:02:35 PM PDT 24
Peak memory 206272 kb
Host smart-9cc442fd-f46b-440f-8422-8167d59b4395
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=24624082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.24624082
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.357456602
Short name T1485
Test name
Test status
Simulation time 153724360 ps
CPU time 0.81 seconds
Started Jun 21 04:59:50 PM PDT 24
Finished Jun 21 04:59:53 PM PDT 24
Peak memory 206048 kb
Host smart-56339153-d980-4e4c-b728-23ceee9c444d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=357456602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.357456602
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.4110674326
Short name T1437
Test name
Test status
Simulation time 184516784 ps
CPU time 0.82 seconds
Started Jun 21 04:59:39 PM PDT 24
Finished Jun 21 04:59:42 PM PDT 24
Peak memory 206008 kb
Host smart-5dcc57fc-50db-4ba6-9abb-abaa3c450124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41106
74326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.4110674326
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.636520660
Short name T142
Test name
Test status
Simulation time 243517653 ps
CPU time 0.92 seconds
Started Jun 21 04:59:39 PM PDT 24
Finished Jun 21 04:59:42 PM PDT 24
Peak memory 205996 kb
Host smart-f9c4fb8f-b165-4dcb-a301-7a1e9000ff94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63652
0660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.636520660
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.3936164246
Short name T1084
Test name
Test status
Simulation time 195575286 ps
CPU time 0.85 seconds
Started Jun 21 04:59:40 PM PDT 24
Finished Jun 21 04:59:43 PM PDT 24
Peak memory 205972 kb
Host smart-5aeac09f-ca5a-4234-974c-ce7694febb8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39361
64246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.3936164246
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1106013450
Short name T742
Test name
Test status
Simulation time 158607531 ps
CPU time 0.78 seconds
Started Jun 21 04:59:49 PM PDT 24
Finished Jun 21 04:59:51 PM PDT 24
Peak memory 206076 kb
Host smart-fdbd0306-a1b4-4fe1-8112-13e57e1e926b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11060
13450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1106013450
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.776967591
Short name T1519
Test name
Test status
Simulation time 166823872 ps
CPU time 0.82 seconds
Started Jun 21 04:59:39 PM PDT 24
Finished Jun 21 04:59:41 PM PDT 24
Peak memory 205960 kb
Host smart-b4c17c69-9ba6-4236-943f-93426a414ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77696
7591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.776967591
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.816878824
Short name T2335
Test name
Test status
Simulation time 183004699 ps
CPU time 0.78 seconds
Started Jun 21 04:59:41 PM PDT 24
Finished Jun 21 04:59:44 PM PDT 24
Peak memory 206024 kb
Host smart-4af9addb-b4a8-4deb-bb12-a9ffc8dfe335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81687
8824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.816878824
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.716983788
Short name T1666
Test name
Test status
Simulation time 194110612 ps
CPU time 0.9 seconds
Started Jun 21 04:59:42 PM PDT 24
Finished Jun 21 04:59:45 PM PDT 24
Peak memory 205988 kb
Host smart-38efd5c1-5735-4225-9b0c-d58efe9fa5e9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=716983788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.716983788
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3191533627
Short name T1939
Test name
Test status
Simulation time 162646258 ps
CPU time 0.82 seconds
Started Jun 21 04:59:52 PM PDT 24
Finished Jun 21 04:59:55 PM PDT 24
Peak memory 206028 kb
Host smart-565473e1-ce42-44fe-abb7-3c8e048e3167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31915
33627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3191533627
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1832736636
Short name T481
Test name
Test status
Simulation time 57603000 ps
CPU time 0.66 seconds
Started Jun 21 04:59:51 PM PDT 24
Finished Jun 21 04:59:55 PM PDT 24
Peak memory 205980 kb
Host smart-05c18da3-ca5e-4bb1-843b-cbe55629a625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18327
36636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1832736636
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.78659188
Short name T1750
Test name
Test status
Simulation time 12097540870 ps
CPU time 27.46 seconds
Started Jun 21 04:59:41 PM PDT 24
Finished Jun 21 05:00:11 PM PDT 24
Peak memory 206256 kb
Host smart-c7c0f863-9ed9-4f83-b61a-f7a9d993cb89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78659
188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.78659188
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3121744624
Short name T683
Test name
Test status
Simulation time 225615575 ps
CPU time 0.89 seconds
Started Jun 21 04:59:40 PM PDT 24
Finished Jun 21 04:59:43 PM PDT 24
Peak memory 205928 kb
Host smart-7806fdeb-a338-4ab0-902c-f46b5a784639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31217
44624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3121744624
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1864158836
Short name T984
Test name
Test status
Simulation time 245840297 ps
CPU time 0.96 seconds
Started Jun 21 04:59:41 PM PDT 24
Finished Jun 21 04:59:44 PM PDT 24
Peak memory 205968 kb
Host smart-40520fb7-cec3-4095-b0e4-5ce6fd6a5cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18641
58836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1864158836
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.4084890038
Short name T1121
Test name
Test status
Simulation time 220362150 ps
CPU time 0.85 seconds
Started Jun 21 04:59:41 PM PDT 24
Finished Jun 21 04:59:44 PM PDT 24
Peak memory 205956 kb
Host smart-ab0bea89-0f4d-4ec8-85cb-f1bdb6fae570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40848
90038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.4084890038
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3018863814
Short name T2228
Test name
Test status
Simulation time 155653490 ps
CPU time 0.83 seconds
Started Jun 21 04:59:54 PM PDT 24
Finished Jun 21 04:59:58 PM PDT 24
Peak memory 206044 kb
Host smart-2e6d454d-8c83-478f-b69b-d67b7d6d3967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30188
63814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3018863814
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1493411846
Short name T900
Test name
Test status
Simulation time 170602800 ps
CPU time 0.92 seconds
Started Jun 21 04:59:53 PM PDT 24
Finished Jun 21 04:59:57 PM PDT 24
Peak memory 205996 kb
Host smart-943e3cad-cb1b-479a-9b0f-ba15b1f062d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14934
11846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1493411846
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2933903287
Short name T892
Test name
Test status
Simulation time 154375738 ps
CPU time 0.76 seconds
Started Jun 21 04:59:53 PM PDT 24
Finished Jun 21 04:59:57 PM PDT 24
Peak memory 206016 kb
Host smart-708abaae-a39f-46a0-97c4-832072b53f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29339
03287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2933903287
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1273269495
Short name T1019
Test name
Test status
Simulation time 144489971 ps
CPU time 0.76 seconds
Started Jun 21 04:59:39 PM PDT 24
Finished Jun 21 04:59:41 PM PDT 24
Peak memory 205924 kb
Host smart-84d39efc-40c5-46ca-a3ac-7df2c16ced84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12732
69495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1273269495
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1099573116
Short name T627
Test name
Test status
Simulation time 192904112 ps
CPU time 0.9 seconds
Started Jun 21 04:59:32 PM PDT 24
Finished Jun 21 04:59:35 PM PDT 24
Peak memory 206028 kb
Host smart-bca236da-c3ce-471e-b988-fdac6d5e5127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10995
73116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1099573116
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.929280769
Short name T1816
Test name
Test status
Simulation time 3893642073 ps
CPU time 34.47 seconds
Started Jun 21 04:59:40 PM PDT 24
Finished Jun 21 05:00:16 PM PDT 24
Peak memory 206468 kb
Host smart-05d3e97f-9e15-436e-bea3-5e8074ea3137
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=929280769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.929280769
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2435173578
Short name T2357
Test name
Test status
Simulation time 183679130 ps
CPU time 0.81 seconds
Started Jun 21 04:59:52 PM PDT 24
Finished Jun 21 04:59:55 PM PDT 24
Peak memory 206032 kb
Host smart-959ec14b-2637-4055-a2a3-a27540c1d14d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24351
73578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2435173578
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.3507721821
Short name T2460
Test name
Test status
Simulation time 189085541 ps
CPU time 0.82 seconds
Started Jun 21 04:59:41 PM PDT 24
Finished Jun 21 04:59:44 PM PDT 24
Peak memory 205960 kb
Host smart-635eeb93-f33e-45fa-b82c-a5ede7cb804e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35077
21821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3507721821
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.2430734774
Short name T1502
Test name
Test status
Simulation time 7739807342 ps
CPU time 70.82 seconds
Started Jun 21 04:59:39 PM PDT 24
Finished Jun 21 05:00:51 PM PDT 24
Peak memory 206260 kb
Host smart-e82669ca-10d2-448a-a3e4-64a45583ec7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24307
34774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.2430734774
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.900989800
Short name T666
Test name
Test status
Simulation time 4165124637 ps
CPU time 4.66 seconds
Started Jun 21 04:59:49 PM PDT 24
Finished Jun 21 04:59:56 PM PDT 24
Peak memory 206268 kb
Host smart-856b4dff-334a-4805-b154-b502ae205682
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=900989800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.900989800
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.3218518501
Short name T1754
Test name
Test status
Simulation time 13374120389 ps
CPU time 12.66 seconds
Started Jun 21 04:59:55 PM PDT 24
Finished Jun 21 05:00:11 PM PDT 24
Peak memory 206124 kb
Host smart-4f42ca8d-6f5b-4870-9159-8f35bf2e2b83
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3218518501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.3218518501
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.2556201833
Short name T2366
Test name
Test status
Simulation time 23379785923 ps
CPU time 27.68 seconds
Started Jun 21 04:59:53 PM PDT 24
Finished Jun 21 05:00:24 PM PDT 24
Peak memory 206336 kb
Host smart-88803005-5021-4e91-b25f-5906aca38478
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2556201833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.2556201833
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.103622498
Short name T1799
Test name
Test status
Simulation time 195686110 ps
CPU time 0.82 seconds
Started Jun 21 04:59:49 PM PDT 24
Finished Jun 21 04:59:52 PM PDT 24
Peak memory 205964 kb
Host smart-f03202ff-1dbb-4a18-94f7-bddc736398f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10362
2498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.103622498
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.4138932347
Short name T58
Test name
Test status
Simulation time 202127788 ps
CPU time 0.81 seconds
Started Jun 21 04:59:39 PM PDT 24
Finished Jun 21 04:59:42 PM PDT 24
Peak memory 205964 kb
Host smart-cb1dce03-98d0-4937-b8a0-e504d6dfdc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41389
32347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.4138932347
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.4000416038
Short name T2395
Test name
Test status
Simulation time 382809113 ps
CPU time 1.23 seconds
Started Jun 21 04:59:49 PM PDT 24
Finished Jun 21 04:59:52 PM PDT 24
Peak memory 205968 kb
Host smart-500b9f12-1eaf-4f71-b65c-d48377151830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40004
16038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.4000416038
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.2967920828
Short name T108
Test name
Test status
Simulation time 1463576142 ps
CPU time 3.03 seconds
Started Jun 21 04:59:39 PM PDT 24
Finished Jun 21 04:59:45 PM PDT 24
Peak memory 206348 kb
Host smart-f67177f8-0a15-4455-9b26-d0ea58304692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29679
20828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.2967920828
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.4275707878
Short name T93
Test name
Test status
Simulation time 17526007789 ps
CPU time 30.04 seconds
Started Jun 21 04:59:40 PM PDT 24
Finished Jun 21 05:00:13 PM PDT 24
Peak memory 206300 kb
Host smart-6e69e809-eced-40f4-a5ef-39aba71739a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42757
07878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.4275707878
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.862909423
Short name T1494
Test name
Test status
Simulation time 477977751 ps
CPU time 1.34 seconds
Started Jun 21 04:59:43 PM PDT 24
Finished Jun 21 04:59:47 PM PDT 24
Peak memory 206008 kb
Host smart-872fa09a-f6fe-429c-ae16-d3f1ce046bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86290
9423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.862909423
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2353956538
Short name T2355
Test name
Test status
Simulation time 139557843 ps
CPU time 0.85 seconds
Started Jun 21 04:59:44 PM PDT 24
Finished Jun 21 04:59:47 PM PDT 24
Peak memory 205968 kb
Host smart-1a268f0b-3763-4c04-a995-b47e99418e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23539
56538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2353956538
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.345436431
Short name T2082
Test name
Test status
Simulation time 43275442 ps
CPU time 0.65 seconds
Started Jun 21 04:59:53 PM PDT 24
Finished Jun 21 04:59:56 PM PDT 24
Peak memory 205960 kb
Host smart-071e7473-ab55-4a6b-8b55-f3f9a98e50ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34543
6431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.345436431
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.2286561899
Short name T1542
Test name
Test status
Simulation time 937157444 ps
CPU time 2.21 seconds
Started Jun 21 04:59:45 PM PDT 24
Finished Jun 21 04:59:49 PM PDT 24
Peak memory 206236 kb
Host smart-6931fa5a-d683-4502-b924-795336ae62de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22865
61899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.2286561899
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3040677024
Short name T2200
Test name
Test status
Simulation time 172382527 ps
CPU time 1.85 seconds
Started Jun 21 04:59:46 PM PDT 24
Finished Jun 21 04:59:50 PM PDT 24
Peak memory 206168 kb
Host smart-74911d4a-30dd-47d0-8849-0b2308db4851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30406
77024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3040677024
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.623332067
Short name T1787
Test name
Test status
Simulation time 201746877 ps
CPU time 0.92 seconds
Started Jun 21 05:00:04 PM PDT 24
Finished Jun 21 05:00:09 PM PDT 24
Peak memory 205936 kb
Host smart-9cb86bf7-33bf-4cc3-bf44-bf01688b71bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62333
2067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.623332067
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1465346680
Short name T361
Test name
Test status
Simulation time 146626049 ps
CPU time 0.81 seconds
Started Jun 21 04:59:47 PM PDT 24
Finished Jun 21 04:59:50 PM PDT 24
Peak memory 205996 kb
Host smart-403dcc1d-7af7-47ec-93fb-08a498e43793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14653
46680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1465346680
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.621253416
Short name T420
Test name
Test status
Simulation time 176827638 ps
CPU time 0.85 seconds
Started Jun 21 04:59:49 PM PDT 24
Finished Jun 21 04:59:52 PM PDT 24
Peak memory 205976 kb
Host smart-d8d748ed-e5e8-4909-8a27-8511f68c8ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62125
3416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.621253416
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.1600442141
Short name T2196
Test name
Test status
Simulation time 210466810 ps
CPU time 0.92 seconds
Started Jun 21 05:00:06 PM PDT 24
Finished Jun 21 05:00:12 PM PDT 24
Peak memory 206000 kb
Host smart-ab9795eb-d078-4cae-9a97-e4766a1e9bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16004
42141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.1600442141
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.3158509891
Short name T663
Test name
Test status
Simulation time 23333120026 ps
CPU time 24.81 seconds
Started Jun 21 04:59:48 PM PDT 24
Finished Jun 21 05:00:15 PM PDT 24
Peak memory 206208 kb
Host smart-03d690a1-665d-4a60-ab80-5a3ab45f410f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31585
09891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.3158509891
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.761626078
Short name T375
Test name
Test status
Simulation time 3347959662 ps
CPU time 3.95 seconds
Started Jun 21 04:59:45 PM PDT 24
Finished Jun 21 04:59:51 PM PDT 24
Peak memory 206028 kb
Host smart-ce808d3e-6f1c-4f6f-b01d-3b08e8d0f16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76162
6078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.761626078
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.4052957330
Short name T1781
Test name
Test status
Simulation time 14203214803 ps
CPU time 401.44 seconds
Started Jun 21 04:59:52 PM PDT 24
Finished Jun 21 05:06:37 PM PDT 24
Peak memory 206300 kb
Host smart-6871409c-3e08-412e-8a77-fad9c67955d5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4052957330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.4052957330
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.2118289557
Short name T2463
Test name
Test status
Simulation time 270954748 ps
CPU time 0.99 seconds
Started Jun 21 05:00:00 PM PDT 24
Finished Jun 21 05:00:03 PM PDT 24
Peak memory 205988 kb
Host smart-51466c83-58bd-41ea-b9db-92dd56544b32
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2118289557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.2118289557
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2505810297
Short name T502
Test name
Test status
Simulation time 209697907 ps
CPU time 0.91 seconds
Started Jun 21 04:59:45 PM PDT 24
Finished Jun 21 04:59:48 PM PDT 24
Peak memory 206000 kb
Host smart-757ee918-f9ec-417a-9a62-9697d0d81ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25058
10297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2505810297
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.1933118278
Short name T1845
Test name
Test status
Simulation time 5827920828 ps
CPU time 159.84 seconds
Started Jun 21 04:59:55 PM PDT 24
Finished Jun 21 05:02:38 PM PDT 24
Peak memory 206196 kb
Host smart-a3fe5353-3214-40e6-957f-336775602383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19331
18278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.1933118278
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.51893781
Short name T1563
Test name
Test status
Simulation time 3228420894 ps
CPU time 30.81 seconds
Started Jun 21 04:59:51 PM PDT 24
Finished Jun 21 05:00:25 PM PDT 24
Peak memory 206212 kb
Host smart-fcaac024-6791-498b-aab0-84d5f144a680
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=51893781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.51893781
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.1624573471
Short name T649
Test name
Test status
Simulation time 177204435 ps
CPU time 0.85 seconds
Started Jun 21 04:59:54 PM PDT 24
Finished Jun 21 04:59:59 PM PDT 24
Peak memory 205960 kb
Host smart-8e676cac-2524-4aee-9872-1587dbbdfb2e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1624573471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.1624573471
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.2758747128
Short name T1869
Test name
Test status
Simulation time 150974842 ps
CPU time 0.79 seconds
Started Jun 21 04:59:53 PM PDT 24
Finished Jun 21 04:59:57 PM PDT 24
Peak memory 205976 kb
Host smart-a54a16dc-6b1f-49b5-93f3-1c3e731b522e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27587
47128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2758747128
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.4098547084
Short name T1283
Test name
Test status
Simulation time 179504730 ps
CPU time 0.89 seconds
Started Jun 21 04:59:56 PM PDT 24
Finished Jun 21 05:00:00 PM PDT 24
Peak memory 205920 kb
Host smart-3eebcb7f-98f5-47ca-82c2-7660c00afe04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40985
47084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.4098547084
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1001670984
Short name T1268
Test name
Test status
Simulation time 208562664 ps
CPU time 0.89 seconds
Started Jun 21 04:59:52 PM PDT 24
Finished Jun 21 04:59:56 PM PDT 24
Peak memory 206020 kb
Host smart-9647b44a-5e8d-4971-aaa7-05ac23bf757a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10016
70984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1001670984
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.523395624
Short name T300
Test name
Test status
Simulation time 188592937 ps
CPU time 0.82 seconds
Started Jun 21 04:59:50 PM PDT 24
Finished Jun 21 04:59:53 PM PDT 24
Peak memory 205976 kb
Host smart-b24afdfc-b66e-4de1-89a7-5c8671e6a282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52339
5624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.523395624
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2892848427
Short name T1623
Test name
Test status
Simulation time 235910397 ps
CPU time 0.88 seconds
Started Jun 21 05:00:02 PM PDT 24
Finished Jun 21 05:00:06 PM PDT 24
Peak memory 206024 kb
Host smart-edd3d289-3569-4265-9b20-6a13c03ff888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28928
48427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2892848427
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1698938189
Short name T1547
Test name
Test status
Simulation time 156902467 ps
CPU time 0.81 seconds
Started Jun 21 04:59:47 PM PDT 24
Finished Jun 21 04:59:49 PM PDT 24
Peak memory 206000 kb
Host smart-ffc45690-2eb0-4311-86a9-e2b7a726a9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16989
38189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1698938189
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.3484398992
Short name T1209
Test name
Test status
Simulation time 263207791 ps
CPU time 0.92 seconds
Started Jun 21 04:59:49 PM PDT 24
Finished Jun 21 04:59:52 PM PDT 24
Peak memory 206044 kb
Host smart-480558a6-1e2a-4d9d-b7e5-53c0a744c0c9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3484398992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3484398992
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3401049348
Short name T1767
Test name
Test status
Simulation time 161573903 ps
CPU time 0.78 seconds
Started Jun 21 04:59:44 PM PDT 24
Finished Jun 21 04:59:47 PM PDT 24
Peak memory 206028 kb
Host smart-15cc03bc-3f0d-444a-a526-a766f81663a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34010
49348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3401049348
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.4220660384
Short name T982
Test name
Test status
Simulation time 82059284 ps
CPU time 0.7 seconds
Started Jun 21 04:59:44 PM PDT 24
Finished Jun 21 04:59:47 PM PDT 24
Peak memory 206036 kb
Host smart-faa76320-5957-47ba-94ad-79c86c2b95e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42206
60384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.4220660384
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3201469555
Short name T265
Test name
Test status
Simulation time 12315066262 ps
CPU time 26.58 seconds
Started Jun 21 04:59:52 PM PDT 24
Finished Jun 21 05:00:22 PM PDT 24
Peak memory 206284 kb
Host smart-634a70da-b675-4dcd-8bf3-8dff458af749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32014
69555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3201469555
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.898958108
Short name T1832
Test name
Test status
Simulation time 140787996 ps
CPU time 0.78 seconds
Started Jun 21 05:00:02 PM PDT 24
Finished Jun 21 05:00:06 PM PDT 24
Peak memory 206080 kb
Host smart-6db78516-05c1-48be-9c30-f6a116de5240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89895
8108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.898958108
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1576255542
Short name T1046
Test name
Test status
Simulation time 284825862 ps
CPU time 0.92 seconds
Started Jun 21 04:59:52 PM PDT 24
Finished Jun 21 04:59:56 PM PDT 24
Peak memory 205924 kb
Host smart-af61bec5-82ee-4be7-a2a9-be5123a92cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15762
55542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1576255542
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.163989690
Short name T3
Test name
Test status
Simulation time 208556028 ps
CPU time 0.87 seconds
Started Jun 21 04:59:52 PM PDT 24
Finished Jun 21 04:59:56 PM PDT 24
Peak memory 205924 kb
Host smart-ee062e2f-b7c6-43fb-bdf0-ddd9c63060cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16398
9690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.163989690
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.1055366542
Short name T393
Test name
Test status
Simulation time 146080170 ps
CPU time 0.76 seconds
Started Jun 21 04:59:51 PM PDT 24
Finished Jun 21 04:59:55 PM PDT 24
Peak memory 205960 kb
Host smart-168a889e-b739-4ed1-b548-c6c9d44562c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10553
66542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.1055366542
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2738324272
Short name T2184
Test name
Test status
Simulation time 198518065 ps
CPU time 0.81 seconds
Started Jun 21 04:59:49 PM PDT 24
Finished Jun 21 04:59:52 PM PDT 24
Peak memory 205976 kb
Host smart-3f368d3c-401f-4cfa-82c2-ec89d65cebc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27383
24272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2738324272
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3962515898
Short name T1191
Test name
Test status
Simulation time 210712088 ps
CPU time 0.8 seconds
Started Jun 21 04:59:45 PM PDT 24
Finished Jun 21 04:59:48 PM PDT 24
Peak memory 205956 kb
Host smart-8f55c114-814f-4b72-b7d2-6dfa30c32718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39625
15898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3962515898
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.600532107
Short name T2271
Test name
Test status
Simulation time 182656491 ps
CPU time 0.9 seconds
Started Jun 21 04:59:46 PM PDT 24
Finished Jun 21 04:59:48 PM PDT 24
Peak memory 205964 kb
Host smart-b4dd2859-c961-44de-9c36-045588887af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60053
2107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.600532107
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2017067231
Short name T1730
Test name
Test status
Simulation time 199596794 ps
CPU time 0.96 seconds
Started Jun 21 04:59:53 PM PDT 24
Finished Jun 21 04:59:57 PM PDT 24
Peak memory 206016 kb
Host smart-89b2e066-291e-424e-86c8-008e9a89df02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20170
67231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2017067231
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.879770598
Short name T2231
Test name
Test status
Simulation time 10974893666 ps
CPU time 102.31 seconds
Started Jun 21 05:00:04 PM PDT 24
Finished Jun 21 05:01:51 PM PDT 24
Peak memory 206280 kb
Host smart-2456ea5d-70e3-43a9-aa92-952feb0d93d0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=879770598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.879770598
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.852461794
Short name T1117
Test name
Test status
Simulation time 231611992 ps
CPU time 0.91 seconds
Started Jun 21 04:59:47 PM PDT 24
Finished Jun 21 04:59:50 PM PDT 24
Peak memory 206048 kb
Host smart-5589cab3-0d52-4328-a78f-701065564828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85246
1794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.852461794
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.171412489
Short name T2031
Test name
Test status
Simulation time 229738828 ps
CPU time 0.82 seconds
Started Jun 21 04:59:46 PM PDT 24
Finished Jun 21 04:59:49 PM PDT 24
Peak memory 206004 kb
Host smart-d7c26c1d-1318-4f91-8905-a1b7fc622c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17141
2489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.171412489
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.1024534537
Short name T1513
Test name
Test status
Simulation time 7597597182 ps
CPU time 57.34 seconds
Started Jun 21 04:59:51 PM PDT 24
Finished Jun 21 05:00:51 PM PDT 24
Peak memory 206224 kb
Host smart-8b196fd9-cba5-450f-9766-086feb17b804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10245
34537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.1024534537
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.2874080474
Short name T2469
Test name
Test status
Simulation time 4453040640 ps
CPU time 5.14 seconds
Started Jun 21 04:54:22 PM PDT 24
Finished Jun 21 04:54:30 PM PDT 24
Peak memory 206356 kb
Host smart-8f8bc12a-604d-42e4-98aa-a9e436372da3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2874080474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.2874080474
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.1788391796
Short name T15
Test name
Test status
Simulation time 13322153190 ps
CPU time 12.48 seconds
Started Jun 21 04:54:20 PM PDT 24
Finished Jun 21 04:54:35 PM PDT 24
Peak memory 206280 kb
Host smart-f6a9716a-a8e3-4fd9-bb1f-ce29e90316fb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1788391796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1788391796
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3587150976
Short name T1852
Test name
Test status
Simulation time 23308090879 ps
CPU time 21.39 seconds
Started Jun 21 04:54:21 PM PDT 24
Finished Jun 21 04:54:45 PM PDT 24
Peak memory 206268 kb
Host smart-b489a097-2c5c-476a-93c8-46f30952867e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3587150976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.3587150976
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3152792638
Short name T971
Test name
Test status
Simulation time 188055674 ps
CPU time 0.85 seconds
Started Jun 21 04:54:22 PM PDT 24
Finished Jun 21 04:54:26 PM PDT 24
Peak memory 206028 kb
Host smart-de7c6166-721c-4562-ae14-92293078a678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31527
92638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3152792638
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.372658700
Short name T53
Test name
Test status
Simulation time 189134602 ps
CPU time 0.82 seconds
Started Jun 21 04:54:21 PM PDT 24
Finished Jun 21 04:54:24 PM PDT 24
Peak memory 205948 kb
Host smart-f0b1c4bc-9180-4212-bbf3-60211c59d3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37265
8700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.372658700
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.2055237958
Short name T61
Test name
Test status
Simulation time 139911967 ps
CPU time 0.76 seconds
Started Jun 21 04:54:21 PM PDT 24
Finished Jun 21 04:54:23 PM PDT 24
Peak memory 206016 kb
Host smart-383888ad-e75b-4eb5-ad7b-974ea8d9b9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20552
37958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2055237958
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3134375235
Short name T921
Test name
Test status
Simulation time 156929992 ps
CPU time 0.76 seconds
Started Jun 21 04:54:21 PM PDT 24
Finished Jun 21 04:54:23 PM PDT 24
Peak memory 206028 kb
Host smart-4542f501-da4d-4386-806e-2c3a550402c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31343
75235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3134375235
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.1379319280
Short name T1126
Test name
Test status
Simulation time 342078075 ps
CPU time 1.18 seconds
Started Jun 21 04:54:21 PM PDT 24
Finished Jun 21 04:54:24 PM PDT 24
Peak memory 205936 kb
Host smart-007ea7c5-c3e4-47cf-b053-d55f02317be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13793
19280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.1379319280
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.2831710852
Short name T1199
Test name
Test status
Simulation time 812794029 ps
CPU time 1.95 seconds
Started Jun 21 04:54:21 PM PDT 24
Finished Jun 21 04:54:25 PM PDT 24
Peak memory 206248 kb
Host smart-0053c8c0-3c90-4229-999c-1c1eb18f19bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28317
10852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.2831710852
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.1730752656
Short name T1427
Test name
Test status
Simulation time 16955579048 ps
CPU time 30.87 seconds
Started Jun 21 04:54:21 PM PDT 24
Finished Jun 21 04:54:55 PM PDT 24
Peak memory 206332 kb
Host smart-2f6f1ec6-6d51-43ce-bde3-59214e87695c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17307
52656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.1730752656
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.826623196
Short name T466
Test name
Test status
Simulation time 334222432 ps
CPU time 1.17 seconds
Started Jun 21 04:54:21 PM PDT 24
Finished Jun 21 04:54:24 PM PDT 24
Peak memory 206008 kb
Host smart-0e56ddfb-cba1-4e40-804a-f9d91d111ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82662
3196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.826623196
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3802017768
Short name T941
Test name
Test status
Simulation time 166402079 ps
CPU time 0.77 seconds
Started Jun 21 04:54:24 PM PDT 24
Finished Jun 21 04:54:27 PM PDT 24
Peak memory 206144 kb
Host smart-c6f2ebf8-0408-4721-beb2-3696bbe22658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38020
17768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3802017768
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.2691577400
Short name T2057
Test name
Test status
Simulation time 40649655 ps
CPU time 0.66 seconds
Started Jun 21 04:54:22 PM PDT 24
Finished Jun 21 04:54:26 PM PDT 24
Peak memory 205956 kb
Host smart-6550c408-7a48-45ae-b4f3-8f8856c4dc66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26915
77400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2691577400
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3468493785
Short name T629
Test name
Test status
Simulation time 1003882784 ps
CPU time 2.39 seconds
Started Jun 21 04:54:23 PM PDT 24
Finished Jun 21 04:54:28 PM PDT 24
Peak memory 206212 kb
Host smart-716ca3ea-b845-48a9-89e5-17bb4b7c4c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34684
93785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3468493785
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2230569821
Short name T1144
Test name
Test status
Simulation time 372634929 ps
CPU time 2.28 seconds
Started Jun 21 04:54:20 PM PDT 24
Finished Jun 21 04:54:24 PM PDT 24
Peak memory 206232 kb
Host smart-07c32e70-04b0-49b7-88c4-486e003bbbad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22305
69821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2230569821
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3034133090
Short name T834
Test name
Test status
Simulation time 189056683 ps
CPU time 0.79 seconds
Started Jun 21 04:54:28 PM PDT 24
Finished Jun 21 04:54:31 PM PDT 24
Peak memory 205964 kb
Host smart-d02a1a28-2274-425e-9bff-7f1af46f5326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30341
33090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3034133090
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.452737046
Short name T1935
Test name
Test status
Simulation time 196690905 ps
CPU time 0.79 seconds
Started Jun 21 04:54:29 PM PDT 24
Finished Jun 21 04:54:33 PM PDT 24
Peak memory 205964 kb
Host smart-65fa71c0-560a-4eba-9e0e-cf0886bc1244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45273
7046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.452737046
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2151547306
Short name T2497
Test name
Test status
Simulation time 182329281 ps
CPU time 0.92 seconds
Started Jun 21 04:54:21 PM PDT 24
Finished Jun 21 04:54:23 PM PDT 24
Peak memory 206016 kb
Host smart-e970451e-63f5-4eb4-bb05-b9736545be54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21515
47306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2151547306
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.3048835182
Short name T102
Test name
Test status
Simulation time 5587479482 ps
CPU time 38.35 seconds
Started Jun 21 04:54:31 PM PDT 24
Finished Jun 21 04:55:14 PM PDT 24
Peak memory 206180 kb
Host smart-65eae8bd-640b-4532-a52b-e73c9537d94b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3048835182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.3048835182
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3088443439
Short name T749
Test name
Test status
Simulation time 305870392 ps
CPU time 1.02 seconds
Started Jun 21 04:54:31 PM PDT 24
Finished Jun 21 04:54:37 PM PDT 24
Peak memory 206000 kb
Host smart-78941d6f-f75a-4d05-b241-1286a2285c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30884
43439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3088443439
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.3292027991
Short name T2046
Test name
Test status
Simulation time 23306154500 ps
CPU time 20.51 seconds
Started Jun 21 04:54:30 PM PDT 24
Finished Jun 21 04:54:55 PM PDT 24
Peak memory 206084 kb
Host smart-6275d207-e32b-4865-8fcf-23776ba9b652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32920
27991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.3292027991
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.2245005792
Short name T634
Test name
Test status
Simulation time 3344916746 ps
CPU time 4.54 seconds
Started Jun 21 04:54:30 PM PDT 24
Finished Jun 21 04:54:39 PM PDT 24
Peak memory 206032 kb
Host smart-2d65b2ee-e344-460e-8936-d7b831065cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22450
05792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2245005792
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.3416163002
Short name T388
Test name
Test status
Simulation time 10694942366 ps
CPU time 283.72 seconds
Started Jun 21 04:54:29 PM PDT 24
Finished Jun 21 04:59:17 PM PDT 24
Peak memory 206304 kb
Host smart-73a1b774-82e7-42cc-a395-56ebc44de6a4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3416163002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.3416163002
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.1601337382
Short name T1185
Test name
Test status
Simulation time 238572612 ps
CPU time 0.95 seconds
Started Jun 21 04:54:28 PM PDT 24
Finished Jun 21 04:54:31 PM PDT 24
Peak memory 206048 kb
Host smart-9744aadd-8df5-4930-83fa-16ae1914eb03
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1601337382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.1601337382
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1989849026
Short name T2226
Test name
Test status
Simulation time 206974215 ps
CPU time 0.87 seconds
Started Jun 21 04:54:30 PM PDT 24
Finished Jun 21 04:54:34 PM PDT 24
Peak memory 206052 kb
Host smart-2121f838-415b-4592-ab0d-23a158009bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19898
49026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1989849026
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.2177827516
Short name T787
Test name
Test status
Simulation time 10139042610 ps
CPU time 88.42 seconds
Started Jun 21 04:54:29 PM PDT 24
Finished Jun 21 04:56:01 PM PDT 24
Peak memory 206216 kb
Host smart-0d13114a-0d9d-4b1c-8e25-f6f5bdd58541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21778
27516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.2177827516
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.2912524083
Short name T4
Test name
Test status
Simulation time 9468358382 ps
CPU time 250.84 seconds
Started Jun 21 04:54:29 PM PDT 24
Finished Jun 21 04:58:42 PM PDT 24
Peak memory 206260 kb
Host smart-3ef2f4f4-924c-4ba1-9889-d076e182237e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2912524083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2912524083
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.469393177
Short name T1463
Test name
Test status
Simulation time 146914865 ps
CPU time 0.78 seconds
Started Jun 21 04:54:30 PM PDT 24
Finished Jun 21 04:54:35 PM PDT 24
Peak memory 206060 kb
Host smart-f8e8a7ec-6f32-47a6-8a9c-fef1ad4ce77b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=469393177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.469393177
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.68696671
Short name T2410
Test name
Test status
Simulation time 159670137 ps
CPU time 0.82 seconds
Started Jun 21 04:54:32 PM PDT 24
Finished Jun 21 04:54:37 PM PDT 24
Peak memory 205980 kb
Host smart-8b3ad522-4310-45ea-96fd-30f0dbede0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68696
671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.68696671
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.1049141748
Short name T126
Test name
Test status
Simulation time 210121825 ps
CPU time 0.84 seconds
Started Jun 21 04:54:31 PM PDT 24
Finished Jun 21 04:54:36 PM PDT 24
Peak memory 205928 kb
Host smart-121137ac-bcf6-4d18-ab13-82eab30aea14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10491
41748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1049141748
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.1305716209
Short name T509
Test name
Test status
Simulation time 206300761 ps
CPU time 0.88 seconds
Started Jun 21 04:54:31 PM PDT 24
Finished Jun 21 04:54:37 PM PDT 24
Peak memory 205952 kb
Host smart-0d6ad0ab-2d54-496c-b560-ac969bf478c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13057
16209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1305716209
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2072187056
Short name T1682
Test name
Test status
Simulation time 187564354 ps
CPU time 0.84 seconds
Started Jun 21 04:54:30 PM PDT 24
Finished Jun 21 04:54:35 PM PDT 24
Peak memory 205968 kb
Host smart-2bdcdb81-0e4b-47e4-8a46-e7e2d46cca80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20721
87056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2072187056
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2224523921
Short name T1181
Test name
Test status
Simulation time 185004091 ps
CPU time 0.81 seconds
Started Jun 21 04:54:30 PM PDT 24
Finished Jun 21 04:54:36 PM PDT 24
Peak memory 206004 kb
Host smart-1a9048cc-2a2d-4622-b006-e98c4e65cfaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22245
23921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2224523921
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.509133120
Short name T1017
Test name
Test status
Simulation time 158517018 ps
CPU time 0.78 seconds
Started Jun 21 04:54:30 PM PDT 24
Finished Jun 21 04:54:35 PM PDT 24
Peak memory 205972 kb
Host smart-22f9f115-1bef-400c-bd26-a737921c3f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50913
3120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.509133120
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.2914586655
Short name T2490
Test name
Test status
Simulation time 223623871 ps
CPU time 0.95 seconds
Started Jun 21 04:54:29 PM PDT 24
Finished Jun 21 04:54:32 PM PDT 24
Peak memory 205988 kb
Host smart-a0831040-5608-4f2c-b061-ae5cf283926b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2914586655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.2914586655
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2566024344
Short name T730
Test name
Test status
Simulation time 147213580 ps
CPU time 0.83 seconds
Started Jun 21 04:54:34 PM PDT 24
Finished Jun 21 04:54:39 PM PDT 24
Peak memory 206044 kb
Host smart-7ee0646a-00b6-4896-b380-4a9e27a2c1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25660
24344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2566024344
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2220124860
Short name T716
Test name
Test status
Simulation time 41708867 ps
CPU time 0.66 seconds
Started Jun 21 04:54:30 PM PDT 24
Finished Jun 21 04:54:35 PM PDT 24
Peak memory 205984 kb
Host smart-72f3c59d-7422-4a2a-a19a-c2f1f4c7e6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22201
24860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2220124860
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3911690376
Short name T167
Test name
Test status
Simulation time 20248264272 ps
CPU time 44.28 seconds
Started Jun 21 04:54:34 PM PDT 24
Finished Jun 21 04:55:22 PM PDT 24
Peak memory 206352 kb
Host smart-5de5c160-4d89-46ac-a1a2-4678e204a4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39116
90376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3911690376
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3519483548
Short name T1585
Test name
Test status
Simulation time 176654505 ps
CPU time 0.82 seconds
Started Jun 21 04:54:29 PM PDT 24
Finished Jun 21 04:54:34 PM PDT 24
Peak memory 205928 kb
Host smart-3f1b6819-27d1-43f7-9b80-273cd671a48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35194
83548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3519483548
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.193071051
Short name T2099
Test name
Test status
Simulation time 233942843 ps
CPU time 0.9 seconds
Started Jun 21 04:54:29 PM PDT 24
Finished Jun 21 04:54:34 PM PDT 24
Peak memory 205956 kb
Host smart-e4a1e759-fc36-4c1d-8cb9-8c8ebde21ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19307
1051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.193071051
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.396293824
Short name T168
Test name
Test status
Simulation time 23642416581 ps
CPU time 146.61 seconds
Started Jun 21 04:54:28 PM PDT 24
Finished Jun 21 04:56:57 PM PDT 24
Peak memory 206372 kb
Host smart-ebe9512c-ab88-4a8b-a35d-3d3b6dbbdf0f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=396293824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.396293824
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.3845335008
Short name T173
Test name
Test status
Simulation time 14322023352 ps
CPU time 283.59 seconds
Started Jun 21 04:54:31 PM PDT 24
Finished Jun 21 04:59:19 PM PDT 24
Peak memory 206320 kb
Host smart-7005eb62-c152-4d46-a7e0-b39e3bd478d6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3845335008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.3845335008
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.1541931316
Short name T1590
Test name
Test status
Simulation time 28936921327 ps
CPU time 220.45 seconds
Started Jun 21 04:54:26 PM PDT 24
Finished Jun 21 04:58:09 PM PDT 24
Peak memory 206272 kb
Host smart-3b299e6a-d05f-45fc-afb4-0f8b223ac856
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1541931316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.1541931316
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.3260832094
Short name T943
Test name
Test status
Simulation time 226153700 ps
CPU time 0.87 seconds
Started Jun 21 04:54:31 PM PDT 24
Finished Jun 21 04:54:37 PM PDT 24
Peak memory 205976 kb
Host smart-bf3a486d-4d49-4b39-a913-7959faffcd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32608
32094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.3260832094
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3779085134
Short name T75
Test name
Test status
Simulation time 180952619 ps
CPU time 0.86 seconds
Started Jun 21 04:54:29 PM PDT 24
Finished Jun 21 04:54:33 PM PDT 24
Peak memory 205988 kb
Host smart-04302f5c-aa31-4062-b5c5-68a8755c18e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37790
85134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3779085134
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.4213706269
Short name T2146
Test name
Test status
Simulation time 209211564 ps
CPU time 0.85 seconds
Started Jun 21 04:54:29 PM PDT 24
Finished Jun 21 04:54:34 PM PDT 24
Peak memory 205976 kb
Host smart-c6d4d81e-8408-41a2-afbd-afaebafbf2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42137
06269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.4213706269
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.539995847
Short name T211
Test name
Test status
Simulation time 862232820 ps
CPU time 1.72 seconds
Started Jun 21 04:54:30 PM PDT 24
Finished Jun 21 04:54:37 PM PDT 24
Peak memory 223884 kb
Host smart-81f0d1cb-82df-4c2d-9ba7-71431573c5eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=539995847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.539995847
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.1966472615
Short name T48
Test name
Test status
Simulation time 343209421 ps
CPU time 1.09 seconds
Started Jun 21 04:54:39 PM PDT 24
Finished Jun 21 04:54:41 PM PDT 24
Peak memory 206044 kb
Host smart-fd938699-bfc8-4f49-8e9b-964acccb5a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19664
72615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.1966472615
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.4162796578
Short name T1151
Test name
Test status
Simulation time 141712861 ps
CPU time 0.75 seconds
Started Jun 21 04:54:31 PM PDT 24
Finished Jun 21 04:54:36 PM PDT 24
Peak memory 206016 kb
Host smart-1386aac5-ce6e-45db-b4d2-d21d5bcbc52c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41627
96578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.4162796578
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3579246278
Short name T324
Test name
Test status
Simulation time 143029344 ps
CPU time 0.78 seconds
Started Jun 21 04:54:33 PM PDT 24
Finished Jun 21 04:54:38 PM PDT 24
Peak memory 206036 kb
Host smart-7b5db440-a818-4e6c-b270-b3b5c6514b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35792
46278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3579246278
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.283287333
Short name T492
Test name
Test status
Simulation time 187342634 ps
CPU time 0.89 seconds
Started Jun 21 04:54:22 PM PDT 24
Finished Jun 21 04:54:25 PM PDT 24
Peak memory 205964 kb
Host smart-46c70805-e659-49b1-a6d9-279d09540219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28328
7333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.283287333
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.3924928126
Short name T367
Test name
Test status
Simulation time 7631836679 ps
CPU time 217.79 seconds
Started Jun 21 04:54:29 PM PDT 24
Finished Jun 21 04:58:10 PM PDT 24
Peak memory 206212 kb
Host smart-39517cd4-8b63-460f-9cac-f88ccf6cd8f4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3924928126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.3924928126
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.636719264
Short name T1491
Test name
Test status
Simulation time 152972167 ps
CPU time 0.77 seconds
Started Jun 21 04:54:31 PM PDT 24
Finished Jun 21 04:54:36 PM PDT 24
Peak memory 206000 kb
Host smart-56a8ecf5-eb8e-446e-b0d3-70eb5aded30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63671
9264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.636719264
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.2772649367
Short name T2163
Test name
Test status
Simulation time 175709425 ps
CPU time 0.83 seconds
Started Jun 21 04:54:30 PM PDT 24
Finished Jun 21 04:54:35 PM PDT 24
Peak memory 206000 kb
Host smart-0b7157d2-8934-49f8-b740-28767e14d4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27726
49367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.2772649367
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.3127543148
Short name T1917
Test name
Test status
Simulation time 4941643993 ps
CPU time 36.68 seconds
Started Jun 21 04:54:30 PM PDT 24
Finished Jun 21 04:55:11 PM PDT 24
Peak memory 206312 kb
Host smart-cce19012-69e6-4367-b133-b7cdb066488e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31275
43148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.3127543148
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.3733802486
Short name T1466
Test name
Test status
Simulation time 30733509914 ps
CPU time 187.16 seconds
Started Jun 21 04:54:30 PM PDT 24
Finished Jun 21 04:57:41 PM PDT 24
Peak memory 206352 kb
Host smart-b5c4f1b8-f3f3-4f6f-ae1b-326910b63b50
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3733802486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.3733802486
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.3769567412
Short name T2217
Test name
Test status
Simulation time 4084126296 ps
CPU time 5.57 seconds
Started Jun 21 04:59:51 PM PDT 24
Finished Jun 21 04:59:59 PM PDT 24
Peak memory 206080 kb
Host smart-2b39f5e3-d7d2-4715-aec6-97058cf475c0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3769567412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.3769567412
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.398730801
Short name T2496
Test name
Test status
Simulation time 13381078464 ps
CPU time 15.85 seconds
Started Jun 21 04:59:53 PM PDT 24
Finished Jun 21 05:00:13 PM PDT 24
Peak memory 206196 kb
Host smart-6016732c-e8cd-49b5-93d1-5e4313cbd1c1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=398730801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.398730801
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3970433755
Short name T1506
Test name
Test status
Simulation time 23355668753 ps
CPU time 28.57 seconds
Started Jun 21 05:00:03 PM PDT 24
Finished Jun 21 05:00:36 PM PDT 24
Peak memory 206000 kb
Host smart-171c774a-2e28-40bd-af6d-7bb9d735afb1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3970433755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3970433755
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2012655369
Short name T2185
Test name
Test status
Simulation time 194551921 ps
CPU time 0.85 seconds
Started Jun 21 04:59:47 PM PDT 24
Finished Jun 21 04:59:50 PM PDT 24
Peak memory 206004 kb
Host smart-5b1c2306-34f8-491f-afdd-8f35cce82807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20126
55369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2012655369
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.3735537445
Short name T745
Test name
Test status
Simulation time 145173285 ps
CPU time 0.77 seconds
Started Jun 21 04:59:52 PM PDT 24
Finished Jun 21 04:59:56 PM PDT 24
Peak memory 205996 kb
Host smart-9662ec1b-f69b-4f5c-94ca-80738a41c313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37355
37445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.3735537445
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.3401835930
Short name T1190
Test name
Test status
Simulation time 353191138 ps
CPU time 1.28 seconds
Started Jun 21 04:59:47 PM PDT 24
Finished Jun 21 04:59:51 PM PDT 24
Peak memory 206024 kb
Host smart-ab86e3ae-e13d-47f6-bf6c-077180c3d6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34018
35930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.3401835930
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.1855282520
Short name T2015
Test name
Test status
Simulation time 1259541276 ps
CPU time 2.63 seconds
Started Jun 21 04:59:45 PM PDT 24
Finished Jun 21 04:59:50 PM PDT 24
Peak memory 206180 kb
Host smart-ceb36d9f-b6c8-4a1c-a56b-f0b0ee635f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18552
82520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.1855282520
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1181218448
Short name T756
Test name
Test status
Simulation time 9167682567 ps
CPU time 17.08 seconds
Started Jun 21 04:59:49 PM PDT 24
Finished Jun 21 05:00:08 PM PDT 24
Peak memory 206284 kb
Host smart-77900d7e-28aa-4749-a3a2-e96c16881a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11812
18448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1181218448
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.1893112275
Short name T397
Test name
Test status
Simulation time 526237396 ps
CPU time 1.32 seconds
Started Jun 21 04:59:45 PM PDT 24
Finished Jun 21 04:59:48 PM PDT 24
Peak memory 205968 kb
Host smart-6d288d1f-581d-4d6a-9335-848b31a1279c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18931
12275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.1893112275
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1173765230
Short name T2452
Test name
Test status
Simulation time 167296671 ps
CPU time 0.75 seconds
Started Jun 21 04:59:55 PM PDT 24
Finished Jun 21 04:59:59 PM PDT 24
Peak memory 205928 kb
Host smart-be9159af-7905-4304-b1c0-5b504ed0526c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11737
65230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1173765230
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.1837307766
Short name T1554
Test name
Test status
Simulation time 34784504 ps
CPU time 0.66 seconds
Started Jun 21 04:59:55 PM PDT 24
Finished Jun 21 04:59:59 PM PDT 24
Peak memory 206016 kb
Host smart-7dd74f9b-003d-4ceb-9b6c-ab87ec5d14dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18373
07766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1837307766
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.354494158
Short name T1334
Test name
Test status
Simulation time 988915412 ps
CPU time 2.13 seconds
Started Jun 21 04:59:52 PM PDT 24
Finished Jun 21 04:59:57 PM PDT 24
Peak memory 206264 kb
Host smart-a2fe581e-8d0f-4315-beea-0401e097d42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35449
4158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.354494158
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.231695112
Short name T323
Test name
Test status
Simulation time 304742817 ps
CPU time 2.07 seconds
Started Jun 21 05:00:00 PM PDT 24
Finished Jun 21 05:00:03 PM PDT 24
Peak memory 206168 kb
Host smart-fa1a7b10-4e7e-4ea6-baf6-812660fce210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23169
5112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.231695112
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1234516168
Short name T1503
Test name
Test status
Simulation time 179746414 ps
CPU time 0.9 seconds
Started Jun 21 04:59:55 PM PDT 24
Finished Jun 21 04:59:59 PM PDT 24
Peak memory 206000 kb
Host smart-5d1d685a-6760-44cb-a750-355d84a418f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12345
16168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1234516168
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3884381857
Short name T1202
Test name
Test status
Simulation time 139130361 ps
CPU time 0.78 seconds
Started Jun 21 04:59:56 PM PDT 24
Finished Jun 21 05:00:00 PM PDT 24
Peak memory 205960 kb
Host smart-e1adf32c-bb22-4519-bd58-94126a72145a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38843
81857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3884381857
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1331773092
Short name T1360
Test name
Test status
Simulation time 168710399 ps
CPU time 0.78 seconds
Started Jun 21 04:59:54 PM PDT 24
Finished Jun 21 04:59:58 PM PDT 24
Peak memory 205992 kb
Host smart-d9b46561-dd96-4a74-aff4-bde214087bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13317
73092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1331773092
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.1804868223
Short name T2279
Test name
Test status
Simulation time 8790087017 ps
CPU time 83.32 seconds
Started Jun 21 04:59:54 PM PDT 24
Finished Jun 21 05:01:21 PM PDT 24
Peak memory 206268 kb
Host smart-bb8c4d84-b4c9-43d2-825c-d477fe79f410
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1804868223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.1804868223
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.987563473
Short name T567
Test name
Test status
Simulation time 255301005 ps
CPU time 0.87 seconds
Started Jun 21 05:00:05 PM PDT 24
Finished Jun 21 05:00:11 PM PDT 24
Peak memory 206024 kb
Host smart-40096608-6ad9-40da-8410-9b6315af99d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98756
3473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.987563473
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.3608590339
Short name T1763
Test name
Test status
Simulation time 23331779687 ps
CPU time 27.56 seconds
Started Jun 21 04:59:54 PM PDT 24
Finished Jun 21 05:00:25 PM PDT 24
Peak memory 206020 kb
Host smart-602ff35f-6c29-4ea0-bcd2-8327bc6be914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36085
90339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3608590339
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.809308792
Short name T2292
Test name
Test status
Simulation time 3339084664 ps
CPU time 3.84 seconds
Started Jun 21 04:59:55 PM PDT 24
Finished Jun 21 05:00:02 PM PDT 24
Peak memory 206032 kb
Host smart-1f31a19d-2e9d-48e3-8d17-3a68376172f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80930
8792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.809308792
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.35056889
Short name T1027
Test name
Test status
Simulation time 12054622739 ps
CPU time 89.86 seconds
Started Jun 21 05:00:03 PM PDT 24
Finished Jun 21 05:01:36 PM PDT 24
Peak memory 206252 kb
Host smart-ef7c4d8c-aa1d-4866-ae7d-4360e4822b31
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=35056889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.35056889
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2703238283
Short name T849
Test name
Test status
Simulation time 237440534 ps
CPU time 0.88 seconds
Started Jun 21 05:00:07 PM PDT 24
Finished Jun 21 05:00:14 PM PDT 24
Peak memory 206052 kb
Host smart-4bc024f4-0696-450e-98a2-9cb640eb7c26
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2703238283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2703238283
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.4133238346
Short name T341
Test name
Test status
Simulation time 220535141 ps
CPU time 0.88 seconds
Started Jun 21 05:00:01 PM PDT 24
Finished Jun 21 05:00:05 PM PDT 24
Peak memory 206048 kb
Host smart-3993b863-2e7a-4881-8232-c474d854e524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41332
38346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.4133238346
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.3367994450
Short name T1315
Test name
Test status
Simulation time 8249524647 ps
CPU time 213.98 seconds
Started Jun 21 05:00:04 PM PDT 24
Finished Jun 21 05:03:42 PM PDT 24
Peak memory 206152 kb
Host smart-c395bede-91d5-4d23-855a-e15f2970bbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33679
94450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.3367994450
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.1172920397
Short name T1631
Test name
Test status
Simulation time 9229458351 ps
CPU time 63.97 seconds
Started Jun 21 05:00:00 PM PDT 24
Finished Jun 21 05:01:07 PM PDT 24
Peak memory 206252 kb
Host smart-7b5997f3-1c08-40bd-a18e-6c035722c8db
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1172920397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.1172920397
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.177580765
Short name T81
Test name
Test status
Simulation time 148761512 ps
CPU time 0.82 seconds
Started Jun 21 05:00:00 PM PDT 24
Finished Jun 21 05:00:04 PM PDT 24
Peak memory 206028 kb
Host smart-d710c43f-15cb-4ca4-b246-23122fb1e19d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=177580765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.177580765
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.4241925585
Short name T2088
Test name
Test status
Simulation time 143724705 ps
CPU time 0.8 seconds
Started Jun 21 04:59:55 PM PDT 24
Finished Jun 21 04:59:59 PM PDT 24
Peak memory 205972 kb
Host smart-586f486e-5040-400c-8e7f-d3628cb13ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42419
25585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.4241925585
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1018753918
Short name T2022
Test name
Test status
Simulation time 259291684 ps
CPU time 0.92 seconds
Started Jun 21 04:59:54 PM PDT 24
Finished Jun 21 04:59:58 PM PDT 24
Peak memory 206020 kb
Host smart-3a1f68b4-431b-4400-b9e8-e690d6e7dfc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10187
53918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1018753918
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.127231520
Short name T1344
Test name
Test status
Simulation time 193511943 ps
CPU time 0.93 seconds
Started Jun 21 04:59:52 PM PDT 24
Finished Jun 21 04:59:56 PM PDT 24
Peak memory 205992 kb
Host smart-2b56a76d-bbd4-4515-82a6-2dd1da1e9521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12723
1520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.127231520
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1763301369
Short name T1115
Test name
Test status
Simulation time 191414927 ps
CPU time 0.8 seconds
Started Jun 21 04:59:52 PM PDT 24
Finished Jun 21 04:59:56 PM PDT 24
Peak memory 205920 kb
Host smart-c399959e-613d-4613-a026-d4f95987c35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17633
01369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1763301369
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3139324888
Short name T1907
Test name
Test status
Simulation time 153091667 ps
CPU time 0.81 seconds
Started Jun 21 04:59:56 PM PDT 24
Finished Jun 21 05:00:00 PM PDT 24
Peak memory 205996 kb
Host smart-99a58562-b732-48ba-9f0c-d794e1391463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31393
24888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3139324888
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.4159702964
Short name T1636
Test name
Test status
Simulation time 161709409 ps
CPU time 0.79 seconds
Started Jun 21 04:59:55 PM PDT 24
Finished Jun 21 04:59:59 PM PDT 24
Peak memory 205868 kb
Host smart-5cc1fc73-878e-432a-9882-c4227ca822d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41597
02964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.4159702964
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.597102104
Short name T1224
Test name
Test status
Simulation time 232444676 ps
CPU time 0.99 seconds
Started Jun 21 04:59:55 PM PDT 24
Finished Jun 21 04:59:59 PM PDT 24
Peak memory 206048 kb
Host smart-a726c015-0551-4690-ac86-3d5f7e2e1d0d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=597102104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.597102104
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1005807477
Short name T733
Test name
Test status
Simulation time 162702416 ps
CPU time 0.79 seconds
Started Jun 21 04:59:52 PM PDT 24
Finished Jun 21 04:59:56 PM PDT 24
Peak memory 206032 kb
Host smart-4a330049-ce3f-472b-819c-c0dfebc05725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10058
07477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1005807477
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.485031197
Short name T1162
Test name
Test status
Simulation time 41195641 ps
CPU time 0.67 seconds
Started Jun 21 04:59:55 PM PDT 24
Finished Jun 21 04:59:59 PM PDT 24
Peak memory 205944 kb
Host smart-6515e138-c7d2-4b31-a423-39f5d7e09fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48503
1197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.485031197
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.1638799701
Short name T2406
Test name
Test status
Simulation time 12084308229 ps
CPU time 25.47 seconds
Started Jun 21 04:59:54 PM PDT 24
Finished Jun 21 05:00:23 PM PDT 24
Peak memory 206228 kb
Host smart-674c7c2c-f646-4608-b430-1c64a7ea0625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16387
99701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.1638799701
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.1837467066
Short name T854
Test name
Test status
Simulation time 162925269 ps
CPU time 0.84 seconds
Started Jun 21 04:59:53 PM PDT 24
Finished Jun 21 04:59:58 PM PDT 24
Peak memory 205972 kb
Host smart-486e009b-60d7-453b-b26f-84e08f2c31af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18374
67066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.1837467066
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1602249075
Short name T2485
Test name
Test status
Simulation time 257422432 ps
CPU time 1.04 seconds
Started Jun 21 04:59:53 PM PDT 24
Finished Jun 21 04:59:58 PM PDT 24
Peak memory 206024 kb
Host smart-d7da9389-88bd-40b4-badc-985b4f903216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16022
49075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1602249075
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.1004039628
Short name T591
Test name
Test status
Simulation time 196617436 ps
CPU time 0.84 seconds
Started Jun 21 04:59:56 PM PDT 24
Finished Jun 21 05:00:00 PM PDT 24
Peak memory 205968 kb
Host smart-72a1652a-238a-42c0-b2a2-100c6ae96f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10040
39628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.1004039628
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.18332887
Short name T212
Test name
Test status
Simulation time 173380417 ps
CPU time 0.85 seconds
Started Jun 21 05:00:01 PM PDT 24
Finished Jun 21 05:00:04 PM PDT 24
Peak memory 206024 kb
Host smart-5f20402a-19f6-469c-9db8-8af52ecc57f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18332
887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.18332887
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2384691217
Short name T529
Test name
Test status
Simulation time 201993279 ps
CPU time 0.82 seconds
Started Jun 21 05:00:05 PM PDT 24
Finished Jun 21 05:00:11 PM PDT 24
Peak memory 206024 kb
Host smart-dbd9faef-ae32-44a7-87be-c4eaee40bcad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23846
91217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2384691217
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1900907642
Short name T1405
Test name
Test status
Simulation time 150351941 ps
CPU time 0.76 seconds
Started Jun 21 05:00:05 PM PDT 24
Finished Jun 21 05:00:10 PM PDT 24
Peak memory 205956 kb
Host smart-11b1d5cf-61a2-45e8-862b-32f78d209611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19009
07642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1900907642
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2736005299
Short name T1395
Test name
Test status
Simulation time 169151375 ps
CPU time 0.8 seconds
Started Jun 21 05:00:03 PM PDT 24
Finished Jun 21 05:00:08 PM PDT 24
Peak memory 205924 kb
Host smart-27921563-25d6-4ea7-9e06-1abd10e1abd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27360
05299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2736005299
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.4216615410
Short name T2201
Test name
Test status
Simulation time 240152600 ps
CPU time 1.03 seconds
Started Jun 21 04:59:47 PM PDT 24
Finished Jun 21 04:59:50 PM PDT 24
Peak memory 206052 kb
Host smart-d137ae80-4081-4534-9d5a-1600fb13119e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42166
15410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.4216615410
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.3935448107
Short name T2283
Test name
Test status
Simulation time 7164748814 ps
CPU time 184.12 seconds
Started Jun 21 04:59:53 PM PDT 24
Finished Jun 21 05:03:01 PM PDT 24
Peak memory 206204 kb
Host smart-5ea5a359-be64-4661-8c05-6c4dc2cc9ad7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3935448107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.3935448107
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1247441638
Short name T741
Test name
Test status
Simulation time 199009740 ps
CPU time 0.86 seconds
Started Jun 21 04:59:56 PM PDT 24
Finished Jun 21 05:00:00 PM PDT 24
Peak memory 206012 kb
Host smart-49aa1d2c-df52-4305-81da-21f54f18132f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12474
41638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1247441638
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.305426724
Short name T407
Test name
Test status
Simulation time 174306311 ps
CPU time 0.81 seconds
Started Jun 21 04:59:58 PM PDT 24
Finished Jun 21 05:00:00 PM PDT 24
Peak memory 206020 kb
Host smart-683df798-af52-4dcf-ab07-d5a8e036eb24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30542
6724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.305426724
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.3383928330
Short name T1497
Test name
Test status
Simulation time 8546524365 ps
CPU time 62.34 seconds
Started Jun 21 04:59:55 PM PDT 24
Finished Jun 21 05:01:01 PM PDT 24
Peak memory 206184 kb
Host smart-778dfce1-bddc-4059-8f69-dde47e2ffb51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33839
28330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.3383928330
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.1430323480
Short name T601
Test name
Test status
Simulation time 3583322251 ps
CPU time 4.07 seconds
Started Jun 21 05:00:06 PM PDT 24
Finished Jun 21 05:00:16 PM PDT 24
Peak memory 206340 kb
Host smart-f95fa416-5c73-40db-b848-5f5e5d66d445
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1430323480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.1430323480
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.1720794417
Short name T1022
Test name
Test status
Simulation time 13357537825 ps
CPU time 12.1 seconds
Started Jun 21 05:00:05 PM PDT 24
Finished Jun 21 05:00:21 PM PDT 24
Peak memory 206092 kb
Host smart-aca72ad6-d64b-407f-a07d-7539902e4fb8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1720794417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1720794417
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3404374975
Short name T454
Test name
Test status
Simulation time 23471887864 ps
CPU time 28.3 seconds
Started Jun 21 05:00:01 PM PDT 24
Finished Jun 21 05:00:32 PM PDT 24
Peak memory 206208 kb
Host smart-ffe1ee80-ccc0-4e52-8fa2-c7f6749458eb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3404374975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.3404374975
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1945402288
Short name T2214
Test name
Test status
Simulation time 175118452 ps
CPU time 0.83 seconds
Started Jun 21 05:00:00 PM PDT 24
Finished Jun 21 05:00:03 PM PDT 24
Peak memory 206008 kb
Host smart-dad439de-2841-4d25-b802-3a23b3118b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19454
02288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1945402288
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1541987638
Short name T1655
Test name
Test status
Simulation time 157901055 ps
CPU time 0.82 seconds
Started Jun 21 05:00:08 PM PDT 24
Finished Jun 21 05:00:16 PM PDT 24
Peak memory 205972 kb
Host smart-42d54316-9e5f-4a51-b3f1-25d2bd2ea2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15419
87638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1541987638
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.117235987
Short name T110
Test name
Test status
Simulation time 546470198 ps
CPU time 1.71 seconds
Started Jun 21 05:00:00 PM PDT 24
Finished Jun 21 05:00:04 PM PDT 24
Peak memory 206176 kb
Host smart-06dfabc6-ee28-42f8-9f39-88ce1d29f8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11723
5987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.117235987
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.839554520
Short name T184
Test name
Test status
Simulation time 564511255 ps
CPU time 1.37 seconds
Started Jun 21 05:00:03 PM PDT 24
Finished Jun 21 05:00:09 PM PDT 24
Peak memory 205968 kb
Host smart-539263ab-2208-409f-9211-9612bff2f4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83955
4520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.839554520
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.2257191966
Short name T1764
Test name
Test status
Simulation time 17086385339 ps
CPU time 31.36 seconds
Started Jun 21 05:00:02 PM PDT 24
Finished Jun 21 05:00:37 PM PDT 24
Peak memory 206220 kb
Host smart-cb6b7bdd-a3e3-451c-bfe1-43e5d698ee00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22571
91966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.2257191966
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.4035302108
Short name T1089
Test name
Test status
Simulation time 426937320 ps
CPU time 1.32 seconds
Started Jun 21 05:00:04 PM PDT 24
Finished Jun 21 05:00:09 PM PDT 24
Peak memory 206028 kb
Host smart-a291743d-ab1d-4d86-9bf1-711957781d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40353
02108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.4035302108
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.3816791310
Short name T996
Test name
Test status
Simulation time 164281956 ps
CPU time 0.82 seconds
Started Jun 21 05:00:00 PM PDT 24
Finished Jun 21 05:00:03 PM PDT 24
Peak memory 205948 kb
Host smart-3f35d63a-522e-4223-bc01-bd39de0fe937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38167
91310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.3816791310
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.1789719266
Short name T1608
Test name
Test status
Simulation time 47070860 ps
CPU time 0.68 seconds
Started Jun 21 05:00:06 PM PDT 24
Finished Jun 21 05:00:12 PM PDT 24
Peak memory 205924 kb
Host smart-27a5cb0d-41d2-486a-a9ed-e89b07c73065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17897
19266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.1789719266
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.145202160
Short name T931
Test name
Test status
Simulation time 920155653 ps
CPU time 2.03 seconds
Started Jun 21 05:00:05 PM PDT 24
Finished Jun 21 05:00:11 PM PDT 24
Peak memory 206140 kb
Host smart-3ef4471c-129f-4ccc-88c7-af970b2ab2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14520
2160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.145202160
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3067519980
Short name T1837
Test name
Test status
Simulation time 394577066 ps
CPU time 2.46 seconds
Started Jun 21 05:00:01 PM PDT 24
Finished Jun 21 05:00:06 PM PDT 24
Peak memory 206180 kb
Host smart-7958bcde-d675-44a9-822c-e73c615b2c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30675
19980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3067519980
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2905653826
Short name T851
Test name
Test status
Simulation time 143694982 ps
CPU time 0.72 seconds
Started Jun 21 05:00:03 PM PDT 24
Finished Jun 21 05:00:08 PM PDT 24
Peak memory 206020 kb
Host smart-9937d813-4d10-45a3-a756-c2ef79e351a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29056
53826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2905653826
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2544526626
Short name T2477
Test name
Test status
Simulation time 213507942 ps
CPU time 0.9 seconds
Started Jun 21 05:00:06 PM PDT 24
Finished Jun 21 05:00:13 PM PDT 24
Peak memory 205964 kb
Host smart-483c49a1-72c7-4b6a-b7d0-c3b14e6ce117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25445
26626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2544526626
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2476969585
Short name T1549
Test name
Test status
Simulation time 223840679 ps
CPU time 0.87 seconds
Started Jun 21 05:00:01 PM PDT 24
Finished Jun 21 05:00:05 PM PDT 24
Peak memory 206020 kb
Host smart-be21b348-62b7-447c-8c89-5f7a121ad0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24769
69585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2476969585
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.3166456649
Short name T2027
Test name
Test status
Simulation time 23332836901 ps
CPU time 30.31 seconds
Started Jun 21 05:00:04 PM PDT 24
Finished Jun 21 05:00:39 PM PDT 24
Peak memory 206060 kb
Host smart-bd551d56-ff2d-4661-889f-d111250e1478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31664
56649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3166456649
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.234851053
Short name T868
Test name
Test status
Simulation time 3301599280 ps
CPU time 3.7 seconds
Started Jun 21 04:59:58 PM PDT 24
Finished Jun 21 05:00:04 PM PDT 24
Peak memory 206028 kb
Host smart-19be97f5-ba22-46f6-ad6d-b501815ef813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23485
1053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.234851053
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.2234483550
Short name T1053
Test name
Test status
Simulation time 14116975133 ps
CPU time 382 seconds
Started Jun 21 05:00:04 PM PDT 24
Finished Jun 21 05:06:30 PM PDT 24
Peak memory 206216 kb
Host smart-75b693df-b92f-4b60-912d-023905443de4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2234483550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.2234483550
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.3475928636
Short name T1594
Test name
Test status
Simulation time 254108707 ps
CPU time 0.9 seconds
Started Jun 21 05:00:00 PM PDT 24
Finished Jun 21 05:00:02 PM PDT 24
Peak memory 206048 kb
Host smart-085e75f8-fa4f-439b-a9c0-9960bc6783ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3475928636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.3475928636
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3385980865
Short name T2482
Test name
Test status
Simulation time 189456256 ps
CPU time 0.87 seconds
Started Jun 21 05:00:00 PM PDT 24
Finished Jun 21 05:00:02 PM PDT 24
Peak memory 205976 kb
Host smart-e1eb2a22-347f-4e22-bf09-74ebf85a895f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33859
80865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3385980865
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.2192383773
Short name T410
Test name
Test status
Simulation time 5435940253 ps
CPU time 50.88 seconds
Started Jun 21 05:00:07 PM PDT 24
Finished Jun 21 05:01:05 PM PDT 24
Peak memory 206248 kb
Host smart-12bcf698-29c3-4e17-8b3d-f71bb8e8cabe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21923
83773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.2192383773
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.1044618353
Short name T1618
Test name
Test status
Simulation time 4370120195 ps
CPU time 117.28 seconds
Started Jun 21 05:00:07 PM PDT 24
Finished Jun 21 05:02:10 PM PDT 24
Peak memory 206272 kb
Host smart-65e33ea8-7e9c-41c5-8bec-d6e118b56640
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1044618353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.1044618353
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.1214372642
Short name T1237
Test name
Test status
Simulation time 155845179 ps
CPU time 0.8 seconds
Started Jun 21 05:00:04 PM PDT 24
Finished Jun 21 05:00:10 PM PDT 24
Peak memory 206048 kb
Host smart-e8527863-e88e-4cbd-aa82-ed5cee6255dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1214372642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.1214372642
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.227407567
Short name T2012
Test name
Test status
Simulation time 139675830 ps
CPU time 0.79 seconds
Started Jun 21 05:00:07 PM PDT 24
Finished Jun 21 05:00:14 PM PDT 24
Peak memory 206048 kb
Host smart-bca5a924-985d-4525-be90-4d4e4da7a419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22740
7567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.227407567
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.874153207
Short name T1316
Test name
Test status
Simulation time 211319712 ps
CPU time 0.83 seconds
Started Jun 21 05:00:02 PM PDT 24
Finished Jun 21 05:00:06 PM PDT 24
Peak memory 205992 kb
Host smart-9669ac12-089c-4fce-b412-b16f86f21ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87415
3207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.874153207
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2491262478
Short name T100
Test name
Test status
Simulation time 190278031 ps
CPU time 0.89 seconds
Started Jun 21 05:00:01 PM PDT 24
Finished Jun 21 05:00:04 PM PDT 24
Peak memory 205960 kb
Host smart-a65041f3-bcc6-43aa-8d25-67a0b9bc3653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24912
62478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2491262478
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1409657977
Short name T865
Test name
Test status
Simulation time 235007501 ps
CPU time 0.84 seconds
Started Jun 21 05:00:00 PM PDT 24
Finished Jun 21 05:00:04 PM PDT 24
Peak memory 205964 kb
Host smart-44576328-99d7-4b8b-8d15-c9642d546bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14096
57977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1409657977
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1602459182
Short name T1014
Test name
Test status
Simulation time 219352582 ps
CPU time 0.83 seconds
Started Jun 21 05:00:01 PM PDT 24
Finished Jun 21 05:00:04 PM PDT 24
Peak memory 206036 kb
Host smart-397923de-2ce1-47e9-ad6a-7aa52e5446dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16024
59182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1602459182
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.172414281
Short name T799
Test name
Test status
Simulation time 170673097 ps
CPU time 0.8 seconds
Started Jun 21 05:00:03 PM PDT 24
Finished Jun 21 05:00:07 PM PDT 24
Peak memory 205972 kb
Host smart-cd6b9916-eb5d-4bfa-837a-da75fb57a90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17241
4281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.172414281
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.3090971913
Short name T908
Test name
Test status
Simulation time 207748729 ps
CPU time 0.9 seconds
Started Jun 21 05:00:02 PM PDT 24
Finished Jun 21 05:00:06 PM PDT 24
Peak memory 206068 kb
Host smart-011b5d24-24a9-40b3-9cf5-7ced075ebc3d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3090971913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.3090971913
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1206957545
Short name T1523
Test name
Test status
Simulation time 144131432 ps
CPU time 0.83 seconds
Started Jun 21 05:00:00 PM PDT 24
Finished Jun 21 05:00:02 PM PDT 24
Peak memory 205932 kb
Host smart-ceffa02f-0080-449e-bf74-b2573150a5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12069
57545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1206957545
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2798403561
Short name T1478
Test name
Test status
Simulation time 35224029 ps
CPU time 0.62 seconds
Started Jun 21 05:00:08 PM PDT 24
Finished Jun 21 05:00:16 PM PDT 24
Peak memory 205980 kb
Host smart-d4d698ea-1c5e-47b8-a7e6-75a70818dd1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27984
03561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2798403561
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3876746923
Short name T1308
Test name
Test status
Simulation time 10031233756 ps
CPU time 20.95 seconds
Started Jun 21 05:00:02 PM PDT 24
Finished Jun 21 05:00:27 PM PDT 24
Peak memory 206228 kb
Host smart-4f822d11-1d96-45b9-a483-941996949954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38767
46923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3876746923
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.3952378606
Short name T1351
Test name
Test status
Simulation time 211969378 ps
CPU time 0.84 seconds
Started Jun 21 05:00:02 PM PDT 24
Finished Jun 21 05:00:06 PM PDT 24
Peak memory 206080 kb
Host smart-2732c2af-1fce-4297-a548-99ef0553ded7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39523
78606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.3952378606
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2145080446
Short name T1239
Test name
Test status
Simulation time 186086708 ps
CPU time 0.89 seconds
Started Jun 21 05:00:03 PM PDT 24
Finished Jun 21 05:00:08 PM PDT 24
Peak memory 205968 kb
Host smart-5423e897-30de-457d-8af7-56e145e37c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21450
80446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2145080446
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.357517545
Short name T1877
Test name
Test status
Simulation time 264404934 ps
CPU time 0.95 seconds
Started Jun 21 05:00:01 PM PDT 24
Finished Jun 21 05:00:04 PM PDT 24
Peak memory 206024 kb
Host smart-895574fb-7280-4ce0-bb50-217582d3b305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35751
7545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.357517545
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.3442057262
Short name T1783
Test name
Test status
Simulation time 187098368 ps
CPU time 0.95 seconds
Started Jun 21 05:00:07 PM PDT 24
Finished Jun 21 05:00:15 PM PDT 24
Peak memory 206048 kb
Host smart-4e77edee-e618-4158-be83-374a95a09118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34420
57262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.3442057262
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.251884801
Short name T1035
Test name
Test status
Simulation time 139317248 ps
CPU time 0.77 seconds
Started Jun 21 05:00:04 PM PDT 24
Finished Jun 21 05:00:09 PM PDT 24
Peak memory 205960 kb
Host smart-6005fb9f-7e2e-45e2-a1c6-53b9d7426f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25188
4801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.251884801
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.307780984
Short name T424
Test name
Test status
Simulation time 156371242 ps
CPU time 0.78 seconds
Started Jun 21 05:00:05 PM PDT 24
Finished Jun 21 05:00:10 PM PDT 24
Peak memory 205920 kb
Host smart-733fc7f4-66af-4767-b04f-97b20577c429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30778
0984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.307780984
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.470988381
Short name T642
Test name
Test status
Simulation time 180226378 ps
CPU time 0.77 seconds
Started Jun 21 05:00:01 PM PDT 24
Finished Jun 21 05:00:04 PM PDT 24
Peak memory 206168 kb
Host smart-ab7c4919-74b4-4d5d-b4c5-13e8b448f9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47098
8381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.470988381
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3142114612
Short name T1404
Test name
Test status
Simulation time 247791073 ps
CPU time 1 seconds
Started Jun 21 05:00:05 PM PDT 24
Finished Jun 21 05:00:10 PM PDT 24
Peak memory 206028 kb
Host smart-0400194e-5540-44fc-b3e3-edc00de4017e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31421
14612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3142114612
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.4084082044
Short name T1472
Test name
Test status
Simulation time 11550044603 ps
CPU time 80.78 seconds
Started Jun 21 05:00:04 PM PDT 24
Finished Jun 21 05:01:29 PM PDT 24
Peak memory 206236 kb
Host smart-ca7e229c-b4ab-4615-a145-eb7d792490a4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4084082044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.4084082044
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.240285805
Short name T1945
Test name
Test status
Simulation time 175279220 ps
CPU time 0.81 seconds
Started Jun 21 05:00:01 PM PDT 24
Finished Jun 21 05:00:05 PM PDT 24
Peak memory 206160 kb
Host smart-826a4628-5baf-4b9e-9453-1679a3b8d47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24028
5805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.240285805
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.1487872939
Short name T314
Test name
Test status
Simulation time 176330497 ps
CPU time 0.93 seconds
Started Jun 21 05:00:01 PM PDT 24
Finished Jun 21 05:00:04 PM PDT 24
Peak memory 205968 kb
Host smart-57d02e80-bf5e-4e81-8d27-11393746fa30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14878
72939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1487872939
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.3547079819
Short name T1393
Test name
Test status
Simulation time 14763797284 ps
CPU time 105.44 seconds
Started Jun 21 05:00:09 PM PDT 24
Finished Jun 21 05:02:02 PM PDT 24
Peak memory 206284 kb
Host smart-f0810f17-f63a-4b84-95bb-651cb428069e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35470
79819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.3547079819
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.376661938
Short name T1539
Test name
Test status
Simulation time 4014108534 ps
CPU time 4.68 seconds
Started Jun 21 05:00:04 PM PDT 24
Finished Jun 21 05:00:13 PM PDT 24
Peak memory 206340 kb
Host smart-4d362f1f-2c8a-4734-a5b3-17c7b95775bd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=376661938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.376661938
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1553225668
Short name T1414
Test name
Test status
Simulation time 23294431109 ps
CPU time 23.25 seconds
Started Jun 21 05:00:05 PM PDT 24
Finished Jun 21 05:00:32 PM PDT 24
Peak memory 206316 kb
Host smart-26ec5e4a-6099-435f-9f99-68d16e084161
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1553225668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.1553225668
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2835933877
Short name T1114
Test name
Test status
Simulation time 157429006 ps
CPU time 0.81 seconds
Started Jun 21 05:00:01 PM PDT 24
Finished Jun 21 05:00:05 PM PDT 24
Peak memory 206020 kb
Host smart-dfc37a07-384f-4abb-83b0-c7789c7c267f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28359
33877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2835933877
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.172856103
Short name T2349
Test name
Test status
Simulation time 192213325 ps
CPU time 0.82 seconds
Started Jun 21 05:00:09 PM PDT 24
Finished Jun 21 05:00:17 PM PDT 24
Peak memory 205972 kb
Host smart-669cee1b-beb4-41a0-8932-de3512f1960c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17285
6103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.172856103
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.3033871929
Short name T1004
Test name
Test status
Simulation time 183995435 ps
CPU time 0.85 seconds
Started Jun 21 05:00:04 PM PDT 24
Finished Jun 21 05:00:09 PM PDT 24
Peak memory 205956 kb
Host smart-3a7a2779-0a07-4089-a8e3-8564bc670a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30338
71929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.3033871929
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.286061185
Short name T1841
Test name
Test status
Simulation time 756413314 ps
CPU time 1.71 seconds
Started Jun 21 05:00:09 PM PDT 24
Finished Jun 21 05:00:19 PM PDT 24
Peak memory 206152 kb
Host smart-9ea2947b-3275-40cd-b3ac-560c9feef81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28606
1185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.286061185
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.2379316370
Short name T1546
Test name
Test status
Simulation time 15391678140 ps
CPU time 30.73 seconds
Started Jun 21 05:00:13 PM PDT 24
Finished Jun 21 05:00:53 PM PDT 24
Peak memory 206252 kb
Host smart-5cd44337-6bcb-482a-a5a8-968d9ba962de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23793
16370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.2379316370
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.4126656010
Short name T1556
Test name
Test status
Simulation time 455088215 ps
CPU time 1.42 seconds
Started Jun 21 05:00:08 PM PDT 24
Finished Jun 21 05:00:16 PM PDT 24
Peak memory 206000 kb
Host smart-c79c792c-41ea-4f7f-83fa-bf1201543197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41266
56010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.4126656010
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3583233705
Short name T2374
Test name
Test status
Simulation time 169808006 ps
CPU time 0.79 seconds
Started Jun 21 05:00:11 PM PDT 24
Finished Jun 21 05:00:21 PM PDT 24
Peak memory 206000 kb
Host smart-7649d8df-4181-47b4-869a-a38aa23655ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35832
33705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3583233705
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1622599457
Short name T725
Test name
Test status
Simulation time 53855636 ps
CPU time 0.68 seconds
Started Jun 21 05:00:09 PM PDT 24
Finished Jun 21 05:00:18 PM PDT 24
Peak memory 205956 kb
Host smart-b5570e54-d05d-46f7-bf02-ea938528a722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16225
99457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1622599457
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.495161107
Short name T654
Test name
Test status
Simulation time 871741184 ps
CPU time 1.94 seconds
Started Jun 21 05:00:08 PM PDT 24
Finished Jun 21 05:00:17 PM PDT 24
Peak memory 206256 kb
Host smart-8539b3c3-5ef8-4da9-87c6-3474e500f140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49516
1107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.495161107
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3017390443
Short name T648
Test name
Test status
Simulation time 197753244 ps
CPU time 2.09 seconds
Started Jun 21 05:00:12 PM PDT 24
Finished Jun 21 05:00:23 PM PDT 24
Peak memory 206148 kb
Host smart-db430d30-428f-4059-95d8-26cf4249f14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30173
90443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3017390443
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3688136616
Short name T1719
Test name
Test status
Simulation time 152630934 ps
CPU time 0.8 seconds
Started Jun 21 05:00:11 PM PDT 24
Finished Jun 21 05:00:20 PM PDT 24
Peak memory 206024 kb
Host smart-ff397390-c3e3-4295-8956-82ff725f9c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36881
36616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3688136616
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3009885667
Short name T1911
Test name
Test status
Simulation time 191882233 ps
CPU time 0.77 seconds
Started Jun 21 05:00:08 PM PDT 24
Finished Jun 21 05:00:16 PM PDT 24
Peak memory 206016 kb
Host smart-e83c385b-4e31-4cce-a58a-903a22004729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30098
85667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3009885667
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1954810753
Short name T1258
Test name
Test status
Simulation time 176189594 ps
CPU time 0.78 seconds
Started Jun 21 05:00:11 PM PDT 24
Finished Jun 21 05:00:20 PM PDT 24
Peak memory 205860 kb
Host smart-7fe29db4-a957-42e9-a717-a162b4ed84f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19548
10753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1954810753
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.1691920963
Short name T225
Test name
Test status
Simulation time 11027741240 ps
CPU time 324.95 seconds
Started Jun 21 05:00:12 PM PDT 24
Finished Jun 21 05:05:46 PM PDT 24
Peak memory 206152 kb
Host smart-58756b39-23b2-456f-96f3-104919c035fb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1691920963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.1691920963
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3070560460
Short name T1109
Test name
Test status
Simulation time 153892636 ps
CPU time 0.78 seconds
Started Jun 21 05:00:11 PM PDT 24
Finished Jun 21 05:00:20 PM PDT 24
Peak memory 206000 kb
Host smart-06ae9461-f112-4262-aa3b-9be320a6df54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30705
60460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3070560460
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.3120703215
Short name T1794
Test name
Test status
Simulation time 23344387924 ps
CPU time 23.44 seconds
Started Jun 21 05:00:12 PM PDT 24
Finished Jun 21 05:00:44 PM PDT 24
Peak memory 206080 kb
Host smart-368bf2bb-f1e8-4e9e-8660-b14a26fe8f59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31207
03215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.3120703215
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1155841490
Short name T2106
Test name
Test status
Simulation time 3280796554 ps
CPU time 3.64 seconds
Started Jun 21 05:00:09 PM PDT 24
Finished Jun 21 05:00:20 PM PDT 24
Peak memory 206040 kb
Host smart-fa7660bf-f310-41b1-adba-6d969d019b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11558
41490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1155841490
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.181366138
Short name T547
Test name
Test status
Simulation time 4074274735 ps
CPU time 28.47 seconds
Started Jun 21 05:00:14 PM PDT 24
Finished Jun 21 05:00:51 PM PDT 24
Peak memory 206104 kb
Host smart-00b4710d-b402-442a-a0c7-1e9fc802811c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=181366138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.181366138
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.3108353858
Short name T2075
Test name
Test status
Simulation time 236447595 ps
CPU time 0.93 seconds
Started Jun 21 05:00:07 PM PDT 24
Finished Jun 21 05:00:15 PM PDT 24
Peak memory 206048 kb
Host smart-bfba7243-68a5-4f92-a1f5-e6cfe93eba64
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3108353858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.3108353858
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3760966298
Short name T1173
Test name
Test status
Simulation time 190623990 ps
CPU time 0.94 seconds
Started Jun 21 05:00:06 PM PDT 24
Finished Jun 21 05:00:13 PM PDT 24
Peak memory 206016 kb
Host smart-c238b203-d241-4bc8-bd10-e4f4c7991c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37609
66298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3760966298
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.332516202
Short name T2158
Test name
Test status
Simulation time 4903214441 ps
CPU time 140.13 seconds
Started Jun 21 05:00:09 PM PDT 24
Finished Jun 21 05:02:37 PM PDT 24
Peak memory 206204 kb
Host smart-e45ccf20-c8d7-4add-89b8-013aae8afe95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33251
6202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.332516202
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.604339310
Short name T2195
Test name
Test status
Simulation time 13395094110 ps
CPU time 376.04 seconds
Started Jun 21 05:00:09 PM PDT 24
Finished Jun 21 05:06:33 PM PDT 24
Peak memory 206212 kb
Host smart-41a3b13c-7fcb-40ef-9c63-d8b9cfda0903
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=604339310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.604339310
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3257130925
Short name T746
Test name
Test status
Simulation time 189876100 ps
CPU time 0.84 seconds
Started Jun 21 05:00:11 PM PDT 24
Finished Jun 21 05:00:20 PM PDT 24
Peak memory 205956 kb
Host smart-b65f2a95-1f29-438d-b6a6-a4a115c0b53d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3257130925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3257130925
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.4161748241
Short name T1596
Test name
Test status
Simulation time 143103827 ps
CPU time 0.77 seconds
Started Jun 21 05:00:18 PM PDT 24
Finished Jun 21 05:00:28 PM PDT 24
Peak memory 205980 kb
Host smart-de339302-8e05-4a50-b97b-4d8b656b2921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41617
48241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.4161748241
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3564950219
Short name T133
Test name
Test status
Simulation time 200568468 ps
CPU time 0.85 seconds
Started Jun 21 05:00:09 PM PDT 24
Finished Jun 21 05:00:17 PM PDT 24
Peak memory 206008 kb
Host smart-99a3ac22-9845-478f-b30a-77aceecde64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35649
50219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3564950219
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.1970031760
Short name T678
Test name
Test status
Simulation time 156489420 ps
CPU time 0.77 seconds
Started Jun 21 05:00:12 PM PDT 24
Finished Jun 21 05:00:22 PM PDT 24
Peak memory 205968 kb
Host smart-19bb6685-72f8-4550-a29a-4f19666188f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19700
31760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.1970031760
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2940194500
Short name T422
Test name
Test status
Simulation time 167093469 ps
CPU time 0.8 seconds
Started Jun 21 05:00:11 PM PDT 24
Finished Jun 21 05:00:20 PM PDT 24
Peak memory 206000 kb
Host smart-391d00d4-f756-4243-90b8-3c1da5fac60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29401
94500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2940194500
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.4230554238
Short name T748
Test name
Test status
Simulation time 149798637 ps
CPU time 0.78 seconds
Started Jun 21 05:00:07 PM PDT 24
Finished Jun 21 05:00:14 PM PDT 24
Peak memory 205976 kb
Host smart-f5511260-04d2-41d6-bd80-ce721c47f320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42305
54238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.4230554238
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.1608482932
Short name T878
Test name
Test status
Simulation time 165102413 ps
CPU time 0.77 seconds
Started Jun 21 05:00:06 PM PDT 24
Finished Jun 21 05:00:12 PM PDT 24
Peak memory 206024 kb
Host smart-b3964852-8130-4cfc-a5bb-e78134ea5179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16084
82932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.1608482932
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.1211246852
Short name T1947
Test name
Test status
Simulation time 212839644 ps
CPU time 0.89 seconds
Started Jun 21 05:00:11 PM PDT 24
Finished Jun 21 05:00:20 PM PDT 24
Peak memory 205992 kb
Host smart-628f9d6b-f166-4fcf-9639-927886d739e1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1211246852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.1211246852
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1342688064
Short name T1770
Test name
Test status
Simulation time 140701226 ps
CPU time 0.85 seconds
Started Jun 21 05:00:07 PM PDT 24
Finished Jun 21 05:00:14 PM PDT 24
Peak memory 206024 kb
Host smart-7ea755ca-9042-44e1-945b-1fd72fb67fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13426
88064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1342688064
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1538094282
Short name T26
Test name
Test status
Simulation time 46494682 ps
CPU time 0.68 seconds
Started Jun 21 05:00:19 PM PDT 24
Finished Jun 21 05:00:28 PM PDT 24
Peak memory 205112 kb
Host smart-c5f2a886-8cf1-485b-a61f-f9352b4d3b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15380
94282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1538094282
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.1040906641
Short name T1265
Test name
Test status
Simulation time 8980031819 ps
CPU time 18.62 seconds
Started Jun 21 05:00:18 PM PDT 24
Finished Jun 21 05:00:50 PM PDT 24
Peak memory 206292 kb
Host smart-48e66d36-0d71-426e-a36c-b0183cb4c049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10409
06641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.1040906641
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.4263526251
Short name T625
Test name
Test status
Simulation time 257166131 ps
CPU time 0.91 seconds
Started Jun 21 05:00:18 PM PDT 24
Finished Jun 21 05:00:28 PM PDT 24
Peak memory 205968 kb
Host smart-1ac7edf6-7501-4f4a-a783-414f693e428b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42635
26251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.4263526251
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.410934001
Short name T2446
Test name
Test status
Simulation time 214474311 ps
CPU time 0.88 seconds
Started Jun 21 05:00:08 PM PDT 24
Finished Jun 21 05:00:17 PM PDT 24
Peak memory 206024 kb
Host smart-6f0f88d0-4cdd-4dc3-8e86-4dc5a75c11d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41093
4001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.410934001
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3432531588
Short name T1954
Test name
Test status
Simulation time 149761190 ps
CPU time 0.81 seconds
Started Jun 21 05:00:10 PM PDT 24
Finished Jun 21 05:00:19 PM PDT 24
Peak memory 206044 kb
Host smart-acb6f8dc-047b-4ef5-b1c9-c85cb2b5480e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34325
31588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3432531588
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.821125880
Short name T2183
Test name
Test status
Simulation time 167551990 ps
CPU time 0.78 seconds
Started Jun 21 05:00:08 PM PDT 24
Finished Jun 21 05:00:16 PM PDT 24
Peak memory 206020 kb
Host smart-ec2c87df-0774-4fa4-8cb2-94d0b99d435b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82112
5880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.821125880
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.4002458242
Short name T1805
Test name
Test status
Simulation time 174387762 ps
CPU time 0.76 seconds
Started Jun 21 05:00:10 PM PDT 24
Finished Jun 21 05:00:19 PM PDT 24
Peak memory 206000 kb
Host smart-7215d032-0073-43c5-b78c-05f20535cff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40024
58242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.4002458242
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2502564856
Short name T722
Test name
Test status
Simulation time 167263917 ps
CPU time 0.82 seconds
Started Jun 21 05:00:14 PM PDT 24
Finished Jun 21 05:00:23 PM PDT 24
Peak memory 205932 kb
Host smart-691f4378-5380-4eab-b07c-fb8254068010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25025
64856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2502564856
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2419070376
Short name T2276
Test name
Test status
Simulation time 186998402 ps
CPU time 0.84 seconds
Started Jun 21 05:00:04 PM PDT 24
Finished Jun 21 05:00:09 PM PDT 24
Peak memory 206028 kb
Host smart-0b745399-22eb-433e-ad54-9115b8be0293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24190
70376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2419070376
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.4133836107
Short name T2049
Test name
Test status
Simulation time 9897006296 ps
CPU time 72.28 seconds
Started Jun 21 05:00:11 PM PDT 24
Finished Jun 21 05:01:32 PM PDT 24
Peak memory 206212 kb
Host smart-3a3616d9-33a1-47a2-9070-26b78d71efb4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4133836107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.4133836107
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2994968127
Short name T2306
Test name
Test status
Simulation time 196142890 ps
CPU time 0.83 seconds
Started Jun 21 05:00:11 PM PDT 24
Finished Jun 21 05:00:20 PM PDT 24
Peak memory 205772 kb
Host smart-863aefbc-6d2a-445f-a7f4-bb308a99cedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29949
68127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2994968127
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2860736361
Short name T2059
Test name
Test status
Simulation time 186469027 ps
CPU time 0.82 seconds
Started Jun 21 05:00:18 PM PDT 24
Finished Jun 21 05:00:32 PM PDT 24
Peak memory 205968 kb
Host smart-f695f046-17f7-4564-88d9-2c3e902c5a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28607
36361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2860736361
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.978142991
Short name T2479
Test name
Test status
Simulation time 8909145883 ps
CPU time 87.55 seconds
Started Jun 21 05:00:05 PM PDT 24
Finished Jun 21 05:01:37 PM PDT 24
Peak memory 206196 kb
Host smart-3e5c9d06-a882-4ba8-9f54-5547d56cff04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97814
2991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.978142991
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.3820247143
Short name T2189
Test name
Test status
Simulation time 3558681087 ps
CPU time 4.01 seconds
Started Jun 21 05:00:08 PM PDT 24
Finished Jun 21 05:00:20 PM PDT 24
Peak memory 206228 kb
Host smart-ad0604d6-aaa5-4e87-a158-60fbf88aae86
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3820247143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.3820247143
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.2141956919
Short name T671
Test name
Test status
Simulation time 13319951621 ps
CPU time 12.61 seconds
Started Jun 21 05:00:11 PM PDT 24
Finished Jun 21 05:00:33 PM PDT 24
Peak memory 206252 kb
Host smart-a0aaf621-98a1-491f-989b-b2ac49c47bfd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2141956919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.2141956919
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.1141351359
Short name T224
Test name
Test status
Simulation time 23452342242 ps
CPU time 21.89 seconds
Started Jun 21 05:00:10 PM PDT 24
Finished Jun 21 05:00:40 PM PDT 24
Peak memory 206248 kb
Host smart-6a55a982-610c-4c58-84a0-17c89751eaa6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1141351359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.1141351359
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2117779241
Short name T2255
Test name
Test status
Simulation time 162901162 ps
CPU time 0.83 seconds
Started Jun 21 05:00:10 PM PDT 24
Finished Jun 21 05:00:19 PM PDT 24
Peak memory 205932 kb
Host smart-ebbe9e3d-8481-450d-b5b5-ee984e85da1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21177
79241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2117779241
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.1516254255
Short name T2277
Test name
Test status
Simulation time 234449203 ps
CPU time 0.9 seconds
Started Jun 21 05:00:08 PM PDT 24
Finished Jun 21 05:00:16 PM PDT 24
Peak memory 206024 kb
Host smart-160bfdb4-542b-449d-9ed8-418ace1453f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15162
54255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.1516254255
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.3146019416
Short name T111
Test name
Test status
Simulation time 550307282 ps
CPU time 1.6 seconds
Started Jun 21 05:00:11 PM PDT 24
Finished Jun 21 05:00:21 PM PDT 24
Peak memory 206132 kb
Host smart-0974d3c2-b667-4011-a502-5c9efc21a660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31460
19416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.3146019416
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.2271217497
Short name T816
Test name
Test status
Simulation time 503861148 ps
CPU time 1.33 seconds
Started Jun 21 05:00:14 PM PDT 24
Finished Jun 21 05:00:24 PM PDT 24
Peak memory 205876 kb
Host smart-c0cbcfdd-93ba-4ec8-b296-c9fe9452fd0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22712
17497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.2271217497
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.2937335823
Short name T2224
Test name
Test status
Simulation time 14258831309 ps
CPU time 25.01 seconds
Started Jun 21 05:00:13 PM PDT 24
Finished Jun 21 05:00:47 PM PDT 24
Peak memory 206204 kb
Host smart-e5aedc1f-b2bc-4cad-a0bb-fcd3f7bdb21d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29373
35823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.2937335823
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.288382458
Short name T1807
Test name
Test status
Simulation time 367508466 ps
CPU time 1.3 seconds
Started Jun 21 05:00:10 PM PDT 24
Finished Jun 21 05:00:20 PM PDT 24
Peak memory 206008 kb
Host smart-36d85a2a-8888-46d1-b3fd-5ca1140b2511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28838
2458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.288382458
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3141114532
Short name T39
Test name
Test status
Simulation time 137702495 ps
CPU time 0.73 seconds
Started Jun 21 05:00:11 PM PDT 24
Finished Jun 21 05:00:21 PM PDT 24
Peak memory 205996 kb
Host smart-45d93ed5-fe00-4db7-abc8-50829ff0a3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31411
14532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3141114532
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.2714099463
Short name T1725
Test name
Test status
Simulation time 47393283 ps
CPU time 0.64 seconds
Started Jun 21 05:00:13 PM PDT 24
Finished Jun 21 05:00:22 PM PDT 24
Peak memory 206012 kb
Host smart-75b952ee-e4d3-4db7-9014-3138a2d31bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27140
99463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2714099463
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.3687570250
Short name T364
Test name
Test status
Simulation time 809137916 ps
CPU time 2 seconds
Started Jun 21 05:00:19 PM PDT 24
Finished Jun 21 05:00:29 PM PDT 24
Peak memory 205384 kb
Host smart-10285fd5-42f7-40b9-94d4-2e5da46c94f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36875
70250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.3687570250
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.4079593398
Short name T2197
Test name
Test status
Simulation time 182049397 ps
CPU time 1.83 seconds
Started Jun 21 05:00:10 PM PDT 24
Finished Jun 21 05:00:20 PM PDT 24
Peak memory 206088 kb
Host smart-2ce5c879-9200-40a4-b482-b239d24b6bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40795
93398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.4079593398
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2592527853
Short name T1902
Test name
Test status
Simulation time 171824257 ps
CPU time 0.82 seconds
Started Jun 21 05:00:19 PM PDT 24
Finished Jun 21 05:00:28 PM PDT 24
Peak memory 206032 kb
Host smart-b0b108a6-40c3-4c2b-99ea-80a95cc66b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25925
27853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2592527853
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2827215852
Short name T2267
Test name
Test status
Simulation time 169354172 ps
CPU time 0.85 seconds
Started Jun 21 05:00:18 PM PDT 24
Finished Jun 21 05:00:28 PM PDT 24
Peak memory 206016 kb
Host smart-30cc64f6-ce0c-4c19-bbca-773f31894cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28272
15852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2827215852
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.2681140233
Short name T841
Test name
Test status
Simulation time 167662521 ps
CPU time 0.8 seconds
Started Jun 21 05:00:08 PM PDT 24
Finished Jun 21 05:00:16 PM PDT 24
Peak memory 205956 kb
Host smart-20797589-a6ee-46fd-9d00-7138c2345701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26811
40233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.2681140233
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.164717711
Short name T106
Test name
Test status
Simulation time 10223641944 ps
CPU time 92.59 seconds
Started Jun 21 05:00:11 PM PDT 24
Finished Jun 21 05:01:53 PM PDT 24
Peak memory 206332 kb
Host smart-9f08fa5e-82b1-4eb5-b4a8-0dd71a441d60
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=164717711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.164717711
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.1038103194
Short name T895
Test name
Test status
Simulation time 271466102 ps
CPU time 0.93 seconds
Started Jun 21 05:00:08 PM PDT 24
Finished Jun 21 05:00:16 PM PDT 24
Peak memory 205956 kb
Host smart-913a26ee-1673-468f-8fa7-1a8018f86e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10381
03194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.1038103194
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.1370699323
Short name T479
Test name
Test status
Simulation time 23348932567 ps
CPU time 23.15 seconds
Started Jun 21 05:00:16 PM PDT 24
Finished Jun 21 05:00:48 PM PDT 24
Peak memory 206008 kb
Host smart-1d4afeb7-211a-49cd-bb9e-f59b9ff579c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13706
99323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1370699323
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.2443080283
Short name T563
Test name
Test status
Simulation time 3281878334 ps
CPU time 3.52 seconds
Started Jun 21 05:00:17 PM PDT 24
Finished Jun 21 05:00:29 PM PDT 24
Peak memory 206088 kb
Host smart-1df756a4-ce05-4921-98b6-0b3db3429201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24430
80283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.2443080283
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.703724717
Short name T1105
Test name
Test status
Simulation time 11846657655 ps
CPU time 107.98 seconds
Started Jun 21 05:00:16 PM PDT 24
Finished Jun 21 05:02:13 PM PDT 24
Peak memory 206272 kb
Host smart-dbd33c30-67f9-4fe1-ae29-ac8983c08a45
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=703724717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.703724717
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.886419273
Short name T1634
Test name
Test status
Simulation time 239940473 ps
CPU time 0.91 seconds
Started Jun 21 05:00:20 PM PDT 24
Finished Jun 21 05:00:29 PM PDT 24
Peak memory 206012 kb
Host smart-50c9dff3-c51b-4798-8f01-c8c077e089f7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=886419273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.886419273
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2538033756
Short name T1041
Test name
Test status
Simulation time 187406791 ps
CPU time 0.81 seconds
Started Jun 21 05:00:16 PM PDT 24
Finished Jun 21 05:00:25 PM PDT 24
Peak memory 205992 kb
Host smart-86520c4b-b753-4db1-b805-f95a957db324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25380
33756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2538033756
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.33345062
Short name T1136
Test name
Test status
Simulation time 3850148985 ps
CPU time 35.92 seconds
Started Jun 21 05:00:17 PM PDT 24
Finished Jun 21 05:01:01 PM PDT 24
Peak memory 206228 kb
Host smart-1e8295f5-a819-45d6-b507-a9f40bc38b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33345
062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.33345062
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3944496600
Short name T2194
Test name
Test status
Simulation time 10948134076 ps
CPU time 306.33 seconds
Started Jun 21 05:00:19 PM PDT 24
Finished Jun 21 05:05:34 PM PDT 24
Peak memory 206212 kb
Host smart-7e58f5ee-6d5f-431d-9344-4763c38ae454
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3944496600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3944496600
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.496658057
Short name T2166
Test name
Test status
Simulation time 205287677 ps
CPU time 0.78 seconds
Started Jun 21 05:00:22 PM PDT 24
Finished Jun 21 05:00:31 PM PDT 24
Peak memory 206044 kb
Host smart-0223ea4f-535a-47dd-a6e5-756dad59cef2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=496658057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.496658057
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.4180585927
Short name T16
Test name
Test status
Simulation time 150063570 ps
CPU time 0.76 seconds
Started Jun 21 05:00:17 PM PDT 24
Finished Jun 21 05:00:26 PM PDT 24
Peak memory 205980 kb
Host smart-562bc52a-64f5-47be-add3-f429103a5e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41805
85927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.4180585927
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.653909500
Short name T129
Test name
Test status
Simulation time 216909636 ps
CPU time 0.88 seconds
Started Jun 21 05:00:17 PM PDT 24
Finished Jun 21 05:00:26 PM PDT 24
Peak memory 206000 kb
Host smart-ddf3a38d-d947-471e-a89f-94a25a58a1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65390
9500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.653909500
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.759139022
Short name T456
Test name
Test status
Simulation time 182769523 ps
CPU time 0.81 seconds
Started Jun 21 05:00:17 PM PDT 24
Finished Jun 21 05:00:26 PM PDT 24
Peak memory 206032 kb
Host smart-21e1de38-a7e9-4b07-a466-cf56e572dcd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75913
9022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.759139022
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1980460853
Short name T1436
Test name
Test status
Simulation time 164381832 ps
CPU time 0.9 seconds
Started Jun 21 05:00:15 PM PDT 24
Finished Jun 21 05:00:24 PM PDT 24
Peak memory 206024 kb
Host smart-95a54e86-0d07-44c2-8026-95f1b68c9188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19804
60853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1980460853
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.581832576
Short name T617
Test name
Test status
Simulation time 171788361 ps
CPU time 0.77 seconds
Started Jun 21 05:00:17 PM PDT 24
Finished Jun 21 05:00:26 PM PDT 24
Peak memory 206076 kb
Host smart-70156482-d0c7-4adf-b750-452ea8cf07b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58183
2576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.581832576
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.209765876
Short name T769
Test name
Test status
Simulation time 156908153 ps
CPU time 0.87 seconds
Started Jun 21 05:00:25 PM PDT 24
Finished Jun 21 05:00:32 PM PDT 24
Peak memory 205960 kb
Host smart-64150167-7a16-4fe0-a588-4086fdfa54ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20976
5876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.209765876
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3778771051
Short name T1943
Test name
Test status
Simulation time 230725168 ps
CPU time 0.95 seconds
Started Jun 21 05:00:20 PM PDT 24
Finished Jun 21 05:00:29 PM PDT 24
Peak memory 205980 kb
Host smart-045728a7-f69a-4ea8-9cb9-f2f15432735a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3778771051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3778771051
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1256629786
Short name T598
Test name
Test status
Simulation time 146345495 ps
CPU time 0.77 seconds
Started Jun 21 05:00:20 PM PDT 24
Finished Jun 21 05:00:29 PM PDT 24
Peak memory 205968 kb
Host smart-90eae184-2a0d-46dd-b374-6da417f9d333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12566
29786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1256629786
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.607103329
Short name T31
Test name
Test status
Simulation time 66368412 ps
CPU time 0.71 seconds
Started Jun 21 05:00:20 PM PDT 24
Finished Jun 21 05:00:29 PM PDT 24
Peak memory 205976 kb
Host smart-ca9779c8-8c84-47aa-abc7-68363143b9b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60710
3329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.607103329
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1455455666
Short name T243
Test name
Test status
Simulation time 12941915429 ps
CPU time 27.12 seconds
Started Jun 21 05:00:22 PM PDT 24
Finished Jun 21 05:00:57 PM PDT 24
Peak memory 206288 kb
Host smart-18805a02-2269-4e8e-8a61-4f62e46d0c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14554
55666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1455455666
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.680669163
Short name T2373
Test name
Test status
Simulation time 164594187 ps
CPU time 0.79 seconds
Started Jun 21 05:00:17 PM PDT 24
Finished Jun 21 05:00:26 PM PDT 24
Peak memory 205972 kb
Host smart-3feb3a52-6746-4f59-a9ac-fc4b2d26dd0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68066
9163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.680669163
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.335201913
Short name T2390
Test name
Test status
Simulation time 236736972 ps
CPU time 0.93 seconds
Started Jun 21 05:00:18 PM PDT 24
Finished Jun 21 05:00:28 PM PDT 24
Peak memory 206024 kb
Host smart-fb8b5a15-351f-413f-a77a-c01001bc01b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33520
1913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.335201913
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.3012606702
Short name T512
Test name
Test status
Simulation time 237287682 ps
CPU time 0.9 seconds
Started Jun 21 05:00:21 PM PDT 24
Finished Jun 21 05:00:30 PM PDT 24
Peak memory 206028 kb
Host smart-8c86cc09-7874-4448-af64-35f0172102fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30126
06702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.3012606702
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.1248828029
Short name T2505
Test name
Test status
Simulation time 182496073 ps
CPU time 0.86 seconds
Started Jun 21 05:00:16 PM PDT 24
Finished Jun 21 05:00:26 PM PDT 24
Peak memory 205988 kb
Host smart-b5bcd043-369d-4a36-8938-5ec8987869cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12488
28029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.1248828029
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.382216650
Short name T935
Test name
Test status
Simulation time 134060468 ps
CPU time 0.75 seconds
Started Jun 21 05:00:21 PM PDT 24
Finished Jun 21 05:00:30 PM PDT 24
Peak memory 206020 kb
Host smart-9a4bfa0e-829e-4cfb-9c77-85a0d95753b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38221
6650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.382216650
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1297677495
Short name T819
Test name
Test status
Simulation time 168227892 ps
CPU time 0.76 seconds
Started Jun 21 05:00:18 PM PDT 24
Finished Jun 21 05:00:27 PM PDT 24
Peak memory 205996 kb
Host smart-5efc8c23-fb4e-4850-abd2-af6a2839f526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12976
77495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1297677495
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2570474891
Short name T972
Test name
Test status
Simulation time 170889820 ps
CPU time 0.78 seconds
Started Jun 21 05:00:15 PM PDT 24
Finished Jun 21 05:00:24 PM PDT 24
Peak memory 205968 kb
Host smart-c3c3eb39-114b-4e17-88ee-1429ddd4d9eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25704
74891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2570474891
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2483485968
Short name T155
Test name
Test status
Simulation time 180559162 ps
CPU time 0.79 seconds
Started Jun 21 05:00:10 PM PDT 24
Finished Jun 21 05:00:19 PM PDT 24
Peak memory 205976 kb
Host smart-8651eda1-8b0d-454d-98d8-00b9963071ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24834
85968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2483485968
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.481780673
Short name T905
Test name
Test status
Simulation time 6276548819 ps
CPU time 59.65 seconds
Started Jun 21 05:00:21 PM PDT 24
Finished Jun 21 05:01:29 PM PDT 24
Peak memory 206168 kb
Host smart-af51dfa2-5ac4-4f99-b225-4dfe26f99d5a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=481780673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.481780673
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2101379831
Short name T2372
Test name
Test status
Simulation time 216411799 ps
CPU time 0.83 seconds
Started Jun 21 05:00:23 PM PDT 24
Finished Jun 21 05:00:32 PM PDT 24
Peak memory 205928 kb
Host smart-e855e5aa-2e42-4249-bad5-ec4d23f0c423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21013
79831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2101379831
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.459221862
Short name T350
Test name
Test status
Simulation time 151232106 ps
CPU time 0.81 seconds
Started Jun 21 05:00:22 PM PDT 24
Finished Jun 21 05:00:31 PM PDT 24
Peak memory 205964 kb
Host smart-c8694007-62df-4404-9fd4-dd2cbd66df7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45922
1862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.459221862
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.2490734191
Short name T328
Test name
Test status
Simulation time 6369322232 ps
CPU time 60.96 seconds
Started Jun 21 05:00:19 PM PDT 24
Finished Jun 21 05:01:28 PM PDT 24
Peak memory 206248 kb
Host smart-20346786-2163-45c5-b370-372e0dbb9eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24907
34191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.2490734191
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3703316119
Short name T9
Test name
Test status
Simulation time 4303065202 ps
CPU time 5.02 seconds
Started Jun 21 05:00:20 PM PDT 24
Finished Jun 21 05:00:34 PM PDT 24
Peak memory 206048 kb
Host smart-696fb3fe-b37a-40b1-ab7c-8d4faff31036
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3703316119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.3703316119
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.43835726
Short name T1828
Test name
Test status
Simulation time 13399187009 ps
CPU time 12.78 seconds
Started Jun 21 05:00:26 PM PDT 24
Finished Jun 21 05:00:45 PM PDT 24
Peak memory 206088 kb
Host smart-99354bca-5608-46ab-9a8f-7f840e073806
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=43835726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.43835726
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2537299957
Short name T934
Test name
Test status
Simulation time 23372827578 ps
CPU time 25.2 seconds
Started Jun 21 05:00:27 PM PDT 24
Finished Jun 21 05:00:58 PM PDT 24
Peak memory 206228 kb
Host smart-248f7b3f-28c2-4a29-90d3-f6ec24adeb37
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2537299957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.2537299957
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3483549416
Short name T2384
Test name
Test status
Simulation time 178058911 ps
CPU time 0.79 seconds
Started Jun 21 05:00:40 PM PDT 24
Finished Jun 21 05:00:42 PM PDT 24
Peak memory 205936 kb
Host smart-6d415ca9-a3db-4cb6-8754-de8ed859e115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34835
49416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3483549416
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.3554940324
Short name T721
Test name
Test status
Simulation time 147283910 ps
CPU time 0.83 seconds
Started Jun 21 05:00:19 PM PDT 24
Finished Jun 21 05:00:28 PM PDT 24
Peak memory 205960 kb
Host smart-4ad5fea5-467d-4c6e-b9ac-af50e8328849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35549
40324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.3554940324
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.3469633793
Short name T2095
Test name
Test status
Simulation time 251979651 ps
CPU time 0.99 seconds
Started Jun 21 05:00:25 PM PDT 24
Finished Jun 21 05:00:32 PM PDT 24
Peak memory 206024 kb
Host smart-f66fa56b-94c0-4ec8-b86c-cc5915afd69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34696
33793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.3469633793
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1582127236
Short name T2480
Test name
Test status
Simulation time 334752345 ps
CPU time 1.05 seconds
Started Jun 21 05:00:19 PM PDT 24
Finished Jun 21 05:00:28 PM PDT 24
Peak memory 206040 kb
Host smart-1e3491ed-1f32-4941-9847-850269ff89f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15821
27236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1582127236
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.3932618158
Short name T1756
Test name
Test status
Simulation time 6077624703 ps
CPU time 12.38 seconds
Started Jun 21 05:00:21 PM PDT 24
Finished Jun 21 05:00:41 PM PDT 24
Peak memory 206216 kb
Host smart-582c325a-550c-4832-b02a-dae216a703bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39326
18158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.3932618158
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2899948086
Short name T2333
Test name
Test status
Simulation time 411448466 ps
CPU time 1.37 seconds
Started Jun 21 05:00:26 PM PDT 24
Finished Jun 21 05:00:33 PM PDT 24
Peak memory 206028 kb
Host smart-7899f2fb-d857-4788-92fa-9894a2c644fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28999
48086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2899948086
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3222588565
Short name T1928
Test name
Test status
Simulation time 148173543 ps
CPU time 0.77 seconds
Started Jun 21 05:00:39 PM PDT 24
Finished Jun 21 05:00:42 PM PDT 24
Peak memory 206000 kb
Host smart-e5ab6e93-5160-4a65-a4f2-71a5dbe690ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32225
88565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3222588565
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.2358911049
Short name T831
Test name
Test status
Simulation time 39203297 ps
CPU time 0.68 seconds
Started Jun 21 05:00:39 PM PDT 24
Finished Jun 21 05:00:41 PM PDT 24
Peak memory 205992 kb
Host smart-d234f0c1-81fe-481f-ab85-75bcebf8e7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23589
11049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2358911049
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.2112854715
Short name T2427
Test name
Test status
Simulation time 648955876 ps
CPU time 1.71 seconds
Started Jun 21 05:00:25 PM PDT 24
Finished Jun 21 05:00:33 PM PDT 24
Peak memory 206200 kb
Host smart-5701e3b6-10c7-4d74-8863-7fd469a36b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21128
54715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2112854715
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2824292504
Short name T480
Test name
Test status
Simulation time 337774246 ps
CPU time 2.02 seconds
Started Jun 21 05:00:36 PM PDT 24
Finished Jun 21 05:00:40 PM PDT 24
Peak memory 206092 kb
Host smart-c1017cb3-3469-4947-b8ec-a7475947212e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28242
92504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2824292504
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.1892550149
Short name T1311
Test name
Test status
Simulation time 232844227 ps
CPU time 0.93 seconds
Started Jun 21 05:00:42 PM PDT 24
Finished Jun 21 05:00:45 PM PDT 24
Peak memory 205928 kb
Host smart-bf22fc8e-3c5d-47d7-b388-2838cb298df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18925
50149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.1892550149
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2457667065
Short name T1475
Test name
Test status
Simulation time 146963901 ps
CPU time 0.81 seconds
Started Jun 21 05:00:23 PM PDT 24
Finished Jun 21 05:00:32 PM PDT 24
Peak memory 205980 kb
Host smart-097cabe7-d3d5-46e2-b244-26daf74a18d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24576
67065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2457667065
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.690928784
Short name T832
Test name
Test status
Simulation time 239342548 ps
CPU time 0.99 seconds
Started Jun 21 05:00:39 PM PDT 24
Finished Jun 21 05:00:41 PM PDT 24
Peak memory 206024 kb
Host smart-992977e5-8454-437d-884f-dc6bd6dffbf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69092
8784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.690928784
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.231140814
Short name T1642
Test name
Test status
Simulation time 212461005 ps
CPU time 0.84 seconds
Started Jun 21 05:00:42 PM PDT 24
Finished Jun 21 05:00:44 PM PDT 24
Peak memory 206024 kb
Host smart-382f1915-71c6-4fa5-9249-14ec7e4226d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23114
0814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.231140814
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.1774357671
Short name T1797
Test name
Test status
Simulation time 23300209272 ps
CPU time 22.33 seconds
Started Jun 21 05:00:24 PM PDT 24
Finished Jun 21 05:00:54 PM PDT 24
Peak memory 206028 kb
Host smart-79cd5df1-c1a4-47dc-a51e-950113d67db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17743
57671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.1774357671
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3140104254
Short name T293
Test name
Test status
Simulation time 3344829750 ps
CPU time 4.08 seconds
Started Jun 21 05:00:44 PM PDT 24
Finished Jun 21 05:00:49 PM PDT 24
Peak memory 206064 kb
Host smart-01bbcdbb-5721-4794-95b5-5dc3b421b9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31401
04254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3140104254
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.3734410633
Short name T2354
Test name
Test status
Simulation time 4159790967 ps
CPU time 114.2 seconds
Started Jun 21 05:00:44 PM PDT 24
Finished Jun 21 05:02:40 PM PDT 24
Peak memory 206272 kb
Host smart-fa165559-7f9d-43ad-aacd-49c8e5afd8f8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3734410633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.3734410633
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.464872652
Short name T2207
Test name
Test status
Simulation time 295642735 ps
CPU time 0.94 seconds
Started Jun 21 05:00:25 PM PDT 24
Finished Jun 21 05:00:32 PM PDT 24
Peak memory 206044 kb
Host smart-2e6f4ffe-087b-4c7b-9773-5dd02a303a0a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=464872652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.464872652
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2704377061
Short name T1068
Test name
Test status
Simulation time 203729092 ps
CPU time 0.91 seconds
Started Jun 21 05:00:37 PM PDT 24
Finished Jun 21 05:00:40 PM PDT 24
Peak memory 206032 kb
Host smart-2c3bb30e-077f-42bc-a7b8-058a08114412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27043
77061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2704377061
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3008473176
Short name T2413
Test name
Test status
Simulation time 3881899809 ps
CPU time 101.06 seconds
Started Jun 21 05:00:29 PM PDT 24
Finished Jun 21 05:02:15 PM PDT 24
Peak memory 206252 kb
Host smart-f50cd9ba-7095-4be1-b487-59cdee95d6cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30084
73176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3008473176
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.761609028
Short name T1531
Test name
Test status
Simulation time 9374083895 ps
CPU time 91.36 seconds
Started Jun 21 05:00:33 PM PDT 24
Finished Jun 21 05:02:07 PM PDT 24
Peak memory 206252 kb
Host smart-8d26dc6a-790e-4d9f-8bfc-8af5aa53d606
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=761609028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.761609028
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.1027353203
Short name T1880
Test name
Test status
Simulation time 162882087 ps
CPU time 0.79 seconds
Started Jun 21 05:00:25 PM PDT 24
Finished Jun 21 05:00:32 PM PDT 24
Peak memory 206028 kb
Host smart-99617efc-cab7-4ad4-8d08-aab77a6d8cd2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1027353203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.1027353203
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1126750836
Short name T2087
Test name
Test status
Simulation time 176625911 ps
CPU time 0.8 seconds
Started Jun 21 05:00:44 PM PDT 24
Finished Jun 21 05:00:46 PM PDT 24
Peak memory 205956 kb
Host smart-1ea035f8-73cb-402b-9a9b-e8442bbf5270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11267
50836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1126750836
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1775185024
Short name T2438
Test name
Test status
Simulation time 224349110 ps
CPU time 0.9 seconds
Started Jun 21 05:00:33 PM PDT 24
Finished Jun 21 05:00:37 PM PDT 24
Peak memory 206000 kb
Host smart-43cc2c85-85aa-4a2b-bea9-7a389af0d74e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17751
85024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1775185024
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2307116617
Short name T1152
Test name
Test status
Simulation time 245688710 ps
CPU time 0.9 seconds
Started Jun 21 05:00:28 PM PDT 24
Finished Jun 21 05:00:34 PM PDT 24
Peak memory 206000 kb
Host smart-5807a1ba-95df-4025-b4bd-dd0e28d6020e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23071
16617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2307116617
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3566530741
Short name T917
Test name
Test status
Simulation time 155570659 ps
CPU time 0.77 seconds
Started Jun 21 05:00:37 PM PDT 24
Finished Jun 21 05:00:40 PM PDT 24
Peak memory 206024 kb
Host smart-3bd58100-ac9e-4c69-b6c4-b0efe0c4f959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35665
30741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3566530741
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2704694515
Short name T2270
Test name
Test status
Simulation time 194623665 ps
CPU time 0.79 seconds
Started Jun 21 05:00:41 PM PDT 24
Finished Jun 21 05:00:43 PM PDT 24
Peak memory 206036 kb
Host smart-70ad1f8d-8281-4aac-98d8-70dc5d162090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27046
94515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2704694515
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.33729461
Short name T1082
Test name
Test status
Simulation time 171884051 ps
CPU time 0.81 seconds
Started Jun 21 05:00:43 PM PDT 24
Finished Jun 21 05:00:46 PM PDT 24
Peak memory 205964 kb
Host smart-55690765-6988-4a1e-b7b0-50e1f59f1c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33729
461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.33729461
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1525892276
Short name T370
Test name
Test status
Simulation time 275511633 ps
CPU time 0.97 seconds
Started Jun 21 05:00:27 PM PDT 24
Finished Jun 21 05:00:34 PM PDT 24
Peak memory 206044 kb
Host smart-c155962f-589b-478d-9e63-73c1ddd173f0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1525892276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1525892276
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3640557289
Short name T2478
Test name
Test status
Simulation time 145615569 ps
CPU time 0.77 seconds
Started Jun 21 05:00:41 PM PDT 24
Finished Jun 21 05:00:43 PM PDT 24
Peak memory 205936 kb
Host smart-483e7735-8f26-4032-8143-a2029ee854d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36405
57289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3640557289
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.1635211136
Short name T595
Test name
Test status
Simulation time 43783898 ps
CPU time 0.69 seconds
Started Jun 21 05:00:43 PM PDT 24
Finished Jun 21 05:00:45 PM PDT 24
Peak memory 205980 kb
Host smart-6afb1d7b-2e2b-435c-a67b-2308873a5df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16352
11136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.1635211136
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.4069352739
Short name T1802
Test name
Test status
Simulation time 14391726357 ps
CPU time 30.52 seconds
Started Jun 21 05:00:37 PM PDT 24
Finished Jun 21 05:01:10 PM PDT 24
Peak memory 206228 kb
Host smart-01916c83-4617-4495-a571-7dd01cfa74fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40693
52739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.4069352739
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2540489429
Short name T2388
Test name
Test status
Simulation time 177405311 ps
CPU time 0.81 seconds
Started Jun 21 05:00:40 PM PDT 24
Finished Jun 21 05:00:42 PM PDT 24
Peak memory 206004 kb
Host smart-9ed89bdb-06a0-4ea5-971f-d596dcf0ca78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25404
89429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2540489429
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2943548718
Short name T1407
Test name
Test status
Simulation time 218795023 ps
CPU time 0.89 seconds
Started Jun 21 05:00:30 PM PDT 24
Finished Jun 21 05:00:35 PM PDT 24
Peak memory 206024 kb
Host smart-76ca32e4-83a5-4aaf-b62b-fc42c9e59013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29435
48718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2943548718
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.1485383937
Short name T1077
Test name
Test status
Simulation time 210901906 ps
CPU time 0.85 seconds
Started Jun 21 05:00:34 PM PDT 24
Finished Jun 21 05:00:37 PM PDT 24
Peak memory 205932 kb
Host smart-c928d32b-6fd1-4637-b8ad-cd9970aed092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14853
83937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.1485383937
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.3167850603
Short name T426
Test name
Test status
Simulation time 175507859 ps
CPU time 0.89 seconds
Started Jun 21 05:00:27 PM PDT 24
Finished Jun 21 05:00:34 PM PDT 24
Peak memory 206024 kb
Host smart-d1884b51-b3fa-4941-bfd5-0f17c3153ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31678
50603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.3167850603
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.3102376909
Short name T434
Test name
Test status
Simulation time 146860635 ps
CPU time 0.76 seconds
Started Jun 21 05:00:28 PM PDT 24
Finished Jun 21 05:00:34 PM PDT 24
Peak memory 205996 kb
Host smart-d6efa72e-44d6-4e4a-b1eb-c440248f5ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31023
76909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.3102376909
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2636138035
Short name T784
Test name
Test status
Simulation time 154817233 ps
CPU time 0.76 seconds
Started Jun 21 05:00:24 PM PDT 24
Finished Jun 21 05:00:32 PM PDT 24
Peak memory 205996 kb
Host smart-cdfb3d22-fd51-4f69-8a0e-2d4b3ebdcd06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26361
38035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2636138035
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.64953650
Short name T342
Test name
Test status
Simulation time 158481739 ps
CPU time 0.78 seconds
Started Jun 21 05:00:23 PM PDT 24
Finished Jun 21 05:00:32 PM PDT 24
Peak memory 206040 kb
Host smart-1b40d7df-bed8-4027-88c8-1b0fc7263ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64953
650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.64953650
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2754633347
Short name T927
Test name
Test status
Simulation time 238147253 ps
CPU time 0.99 seconds
Started Jun 21 05:00:19 PM PDT 24
Finished Jun 21 05:00:29 PM PDT 24
Peak memory 206052 kb
Host smart-777eb253-55b5-414d-82db-c48517a1a99a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27546
33347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2754633347
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.1412949906
Short name T932
Test name
Test status
Simulation time 4958479438 ps
CPU time 46.31 seconds
Started Jun 21 05:00:23 PM PDT 24
Finished Jun 21 05:01:17 PM PDT 24
Peak memory 206268 kb
Host smart-f9bc71f4-e862-47ca-8f14-5beebec56f0f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1412949906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.1412949906
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2071145405
Short name T755
Test name
Test status
Simulation time 187900621 ps
CPU time 0.82 seconds
Started Jun 21 05:00:27 PM PDT 24
Finished Jun 21 05:00:34 PM PDT 24
Peak memory 206012 kb
Host smart-b8d5327a-a56b-4c49-beb8-0e3bd6a1cbcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20711
45405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2071145405
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.672143557
Short name T1801
Test name
Test status
Simulation time 174845112 ps
CPU time 0.84 seconds
Started Jun 21 05:00:34 PM PDT 24
Finished Jun 21 05:00:37 PM PDT 24
Peak memory 206024 kb
Host smart-c76afea3-16de-4b90-b741-ca638e3a0207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67214
3557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.672143557
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.568695870
Short name T1893
Test name
Test status
Simulation time 9424631846 ps
CPU time 256.24 seconds
Started Jun 21 05:00:24 PM PDT 24
Finished Jun 21 05:04:47 PM PDT 24
Peak memory 206248 kb
Host smart-c71f9acd-6adb-4e71-afb4-a2273c2f70fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56869
5870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.568695870
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.3803510451
Short name T498
Test name
Test status
Simulation time 3907829293 ps
CPU time 4.48 seconds
Started Jun 21 05:00:27 PM PDT 24
Finished Jun 21 05:00:37 PM PDT 24
Peak memory 206104 kb
Host smart-2cbb62a3-1971-4bc0-8afb-cfe483f03844
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3803510451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.3803510451
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.4125247048
Short name T706
Test name
Test status
Simulation time 13371474747 ps
CPU time 12.97 seconds
Started Jun 21 05:00:28 PM PDT 24
Finished Jun 21 05:00:46 PM PDT 24
Peak memory 206084 kb
Host smart-77532dec-6828-4c26-b928-96479585c569
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4125247048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.4125247048
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.605244888
Short name T1357
Test name
Test status
Simulation time 23384506843 ps
CPU time 22.3 seconds
Started Jun 21 05:00:27 PM PDT 24
Finished Jun 21 05:00:55 PM PDT 24
Peak memory 206068 kb
Host smart-804b012d-1e35-4efd-a971-d1e239e7c81a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=605244888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.605244888
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1672725961
Short name T1138
Test name
Test status
Simulation time 193467584 ps
CPU time 0.84 seconds
Started Jun 21 05:00:25 PM PDT 24
Finished Jun 21 05:00:32 PM PDT 24
Peak memory 205928 kb
Host smart-49f2519d-bf8a-4b80-a60f-35d0ff9a6d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16727
25961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1672725961
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.3585549662
Short name T1683
Test name
Test status
Simulation time 150628679 ps
CPU time 0.77 seconds
Started Jun 21 05:00:27 PM PDT 24
Finished Jun 21 05:00:34 PM PDT 24
Peak memory 205992 kb
Host smart-7370b02d-46f3-46f2-aed4-bd634fe0192d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35855
49662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.3585549662
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.898146384
Short name T806
Test name
Test status
Simulation time 337726766 ps
CPU time 1.19 seconds
Started Jun 21 05:00:28 PM PDT 24
Finished Jun 21 05:00:34 PM PDT 24
Peak memory 206052 kb
Host smart-d4fb2ded-f191-448c-8b75-a2ef68818f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89814
6384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.898146384
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3184115042
Short name T1903
Test name
Test status
Simulation time 1527017645 ps
CPU time 3.23 seconds
Started Jun 21 05:00:30 PM PDT 24
Finished Jun 21 05:00:37 PM PDT 24
Peak memory 206236 kb
Host smart-6dfeb803-f9c7-4736-b049-6c6906f1137e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31841
15042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3184115042
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.112721482
Short name T701
Test name
Test status
Simulation time 13255911834 ps
CPU time 23.85 seconds
Started Jun 21 05:00:38 PM PDT 24
Finished Jun 21 05:01:03 PM PDT 24
Peak memory 206164 kb
Host smart-3646303c-6d98-4a5a-995e-ac2dcf06a838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11272
1482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.112721482
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.3595348103
Short name T1419
Test name
Test status
Simulation time 383536303 ps
CPU time 1.23 seconds
Started Jun 21 05:00:26 PM PDT 24
Finished Jun 21 05:00:34 PM PDT 24
Peak memory 206028 kb
Host smart-8616f8bd-e447-43c2-ad88-7e1b678fa2a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35953
48103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.3595348103
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.603265361
Short name T588
Test name
Test status
Simulation time 134933745 ps
CPU time 0.73 seconds
Started Jun 21 05:00:37 PM PDT 24
Finished Jun 21 05:00:40 PM PDT 24
Peak memory 205960 kb
Host smart-2ef9feba-9bea-47f0-92b0-5b224f3e85c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60326
5361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.603265361
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.1192830728
Short name T808
Test name
Test status
Simulation time 60052331 ps
CPU time 0.68 seconds
Started Jun 21 05:00:52 PM PDT 24
Finished Jun 21 05:00:56 PM PDT 24
Peak memory 205960 kb
Host smart-ddfdcfa3-015b-4cfe-8c32-a744cbfe5b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11928
30728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.1192830728
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.331833550
Short name T150
Test name
Test status
Simulation time 849970486 ps
CPU time 1.97 seconds
Started Jun 21 05:00:35 PM PDT 24
Finished Jun 21 05:00:39 PM PDT 24
Peak memory 206248 kb
Host smart-99525b3e-42d6-47dc-b3b0-36b4e5aa271f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33183
3550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.331833550
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2665213079
Short name T2073
Test name
Test status
Simulation time 152331998 ps
CPU time 1.15 seconds
Started Jun 21 05:00:43 PM PDT 24
Finished Jun 21 05:00:45 PM PDT 24
Peak memory 206128 kb
Host smart-6026508b-0a29-4f33-b2c5-52c4d7164055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26652
13079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2665213079
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.1316801901
Short name T1270
Test name
Test status
Simulation time 222470399 ps
CPU time 0.98 seconds
Started Jun 21 05:00:37 PM PDT 24
Finished Jun 21 05:00:40 PM PDT 24
Peak memory 205928 kb
Host smart-9d4952bb-7ccd-42b9-8e7e-a4d27aeda5f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13168
01901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.1316801901
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3403933945
Short name T623
Test name
Test status
Simulation time 151174700 ps
CPU time 0.78 seconds
Started Jun 21 05:00:50 PM PDT 24
Finished Jun 21 05:00:54 PM PDT 24
Peak memory 206020 kb
Host smart-3867521b-6cdf-461e-a70f-dbdf1b4a582a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34039
33945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3403933945
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2989917436
Short name T1617
Test name
Test status
Simulation time 215667552 ps
CPU time 0.91 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:00:55 PM PDT 24
Peak memory 206020 kb
Host smart-8a13c359-4c5b-4a4f-9662-07adabc45930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29899
17436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2989917436
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.1663683400
Short name T526
Test name
Test status
Simulation time 200229126 ps
CPU time 0.86 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:00:55 PM PDT 24
Peak memory 205960 kb
Host smart-a0de3589-9626-4a10-9251-b09fd105500c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16636
83400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1663683400
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.3116243659
Short name T1382
Test name
Test status
Simulation time 23331658241 ps
CPU time 22.58 seconds
Started Jun 21 05:00:46 PM PDT 24
Finished Jun 21 05:01:11 PM PDT 24
Peak memory 206080 kb
Host smart-dd204a76-4bdb-4c6c-8a8b-7102e3dcada8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31162
43659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.3116243659
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.454099424
Short name T1254
Test name
Test status
Simulation time 3317325640 ps
CPU time 3.45 seconds
Started Jun 21 05:00:39 PM PDT 24
Finished Jun 21 05:00:44 PM PDT 24
Peak memory 206040 kb
Host smart-a79546bb-a974-413e-8496-aa10719b1de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45409
9424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.454099424
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.963734950
Short name T1318
Test name
Test status
Simulation time 10613473912 ps
CPU time 74.69 seconds
Started Jun 21 05:00:39 PM PDT 24
Finished Jun 21 05:01:56 PM PDT 24
Peak memory 206276 kb
Host smart-69b98efc-27bb-4d1b-8bc1-f01d7e32e2cc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=963734950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.963734950
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.502391128
Short name T1043
Test name
Test status
Simulation time 231245234 ps
CPU time 0.91 seconds
Started Jun 21 05:00:54 PM PDT 24
Finished Jun 21 05:00:58 PM PDT 24
Peak memory 206048 kb
Host smart-2f38a984-3051-4d60-872c-1caed67f5585
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=502391128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.502391128
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3735733159
Short name T1510
Test name
Test status
Simulation time 199227236 ps
CPU time 0.86 seconds
Started Jun 21 05:00:36 PM PDT 24
Finished Jun 21 05:00:39 PM PDT 24
Peak memory 205996 kb
Host smart-f40076b0-6cc8-498b-93c1-e7d181dd605d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37357
33159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3735733159
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.4258882364
Short name T1057
Test name
Test status
Simulation time 8621170438 ps
CPU time 233.91 seconds
Started Jun 21 05:00:37 PM PDT 24
Finished Jun 21 05:04:33 PM PDT 24
Peak memory 206188 kb
Host smart-9134828e-d392-49cf-9356-77acac92b511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42588
82364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.4258882364
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.2958718958
Short name T1271
Test name
Test status
Simulation time 7873843754 ps
CPU time 72.87 seconds
Started Jun 21 05:00:52 PM PDT 24
Finished Jun 21 05:02:08 PM PDT 24
Peak memory 206220 kb
Host smart-6c081f8d-7395-4570-9d18-9b84c9b5f308
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2958718958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.2958718958
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3734916557
Short name T2165
Test name
Test status
Simulation time 156805751 ps
CPU time 0.75 seconds
Started Jun 21 05:00:45 PM PDT 24
Finished Jun 21 05:00:47 PM PDT 24
Peak memory 205996 kb
Host smart-1993da50-dda6-4a20-a612-ed4b61b6e509
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3734916557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3734916557
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.4199577836
Short name T571
Test name
Test status
Simulation time 160452414 ps
CPU time 0.8 seconds
Started Jun 21 05:00:48 PM PDT 24
Finished Jun 21 05:00:51 PM PDT 24
Peak memory 205932 kb
Host smart-1548ea26-896f-4427-a77d-b4a28d7db90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41995
77836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.4199577836
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2682775777
Short name T2237
Test name
Test status
Simulation time 197911423 ps
CPU time 0.8 seconds
Started Jun 21 05:00:38 PM PDT 24
Finished Jun 21 05:00:41 PM PDT 24
Peak memory 206052 kb
Host smart-3ace376e-e294-4792-abac-81acca2447de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26827
75777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2682775777
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.2582813175
Short name T2396
Test name
Test status
Simulation time 191190276 ps
CPU time 0.86 seconds
Started Jun 21 05:00:34 PM PDT 24
Finished Jun 21 05:00:37 PM PDT 24
Peak memory 205960 kb
Host smart-07c89be1-bdca-4b5c-9520-a8fe2995da29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25828
13175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.2582813175
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.250235373
Short name T1037
Test name
Test status
Simulation time 164594559 ps
CPU time 0.78 seconds
Started Jun 21 05:00:57 PM PDT 24
Finished Jun 21 05:01:01 PM PDT 24
Peak memory 206016 kb
Host smart-c3e6e7a3-4917-4eb1-b499-9a74b3b50518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25023
5373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.250235373
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1160665301
Short name T1376
Test name
Test status
Simulation time 169056131 ps
CPU time 0.79 seconds
Started Jun 21 05:00:35 PM PDT 24
Finished Jun 21 05:00:38 PM PDT 24
Peak memory 206000 kb
Host smart-852ec8ba-603f-4dcc-a9cd-8f04fd7479cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11606
65301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1160665301
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.381087100
Short name T2382
Test name
Test status
Simulation time 165964819 ps
CPU time 0.81 seconds
Started Jun 21 05:00:45 PM PDT 24
Finished Jun 21 05:00:48 PM PDT 24
Peak memory 206020 kb
Host smart-d243d2ac-235f-43da-9b05-38708019ce07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38108
7100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.381087100
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.278527688
Short name T540
Test name
Test status
Simulation time 216151148 ps
CPU time 0.95 seconds
Started Jun 21 05:00:48 PM PDT 24
Finished Jun 21 05:00:52 PM PDT 24
Peak memory 205996 kb
Host smart-88d3c342-042b-4f64-99ae-53b960d18c0a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=278527688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.278527688
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3143968988
Short name T983
Test name
Test status
Simulation time 196396725 ps
CPU time 0.82 seconds
Started Jun 21 05:00:38 PM PDT 24
Finished Jun 21 05:00:41 PM PDT 24
Peak memory 205984 kb
Host smart-39996f87-af3b-4fae-86b9-fd1d8f26bbd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31439
68988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3143968988
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2088680942
Short name T1949
Test name
Test status
Simulation time 32515338 ps
CPU time 0.69 seconds
Started Jun 21 05:00:36 PM PDT 24
Finished Jun 21 05:00:39 PM PDT 24
Peak memory 206012 kb
Host smart-01ca5109-5253-4572-aaaa-c610edf12c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20886
80942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2088680942
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.717826164
Short name T1915
Test name
Test status
Simulation time 20774007931 ps
CPU time 46.07 seconds
Started Jun 21 05:00:36 PM PDT 24
Finished Jun 21 05:01:24 PM PDT 24
Peak memory 206332 kb
Host smart-1ec34cef-0ef0-4ec6-958d-e6c1dec77fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71782
6164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.717826164
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3201741121
Short name T1275
Test name
Test status
Simulation time 183096521 ps
CPU time 0.94 seconds
Started Jun 21 05:00:37 PM PDT 24
Finished Jun 21 05:00:40 PM PDT 24
Peak memory 206028 kb
Host smart-f89c5dac-d704-4e4e-8fbf-11ebcadc5199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32017
41121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3201741121
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3726833296
Short name T633
Test name
Test status
Simulation time 230758370 ps
CPU time 0.91 seconds
Started Jun 21 05:00:35 PM PDT 24
Finished Jun 21 05:00:38 PM PDT 24
Peak memory 206032 kb
Host smart-394027af-4455-4328-bbd5-ad8a035fd7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37268
33296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3726833296
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.3494631055
Short name T1553
Test name
Test status
Simulation time 193145434 ps
CPU time 0.83 seconds
Started Jun 21 05:00:54 PM PDT 24
Finished Jun 21 05:00:58 PM PDT 24
Peak memory 206028 kb
Host smart-e7adae8e-3c8d-49ae-a081-55492e564487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34946
31055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3494631055
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.1479186699
Short name T2030
Test name
Test status
Simulation time 182207580 ps
CPU time 0.89 seconds
Started Jun 21 05:00:46 PM PDT 24
Finished Jun 21 05:00:50 PM PDT 24
Peak memory 206080 kb
Host smart-3d080fcc-97de-467f-822d-6e07473e24c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14791
86699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.1479186699
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.852150291
Short name T1467
Test name
Test status
Simulation time 174870777 ps
CPU time 0.78 seconds
Started Jun 21 05:00:37 PM PDT 24
Finished Jun 21 05:00:40 PM PDT 24
Peak memory 205932 kb
Host smart-a12f872d-097d-4b8f-918a-806d6274c508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85215
0291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.852150291
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.4275586222
Short name T1094
Test name
Test status
Simulation time 163023036 ps
CPU time 0.76 seconds
Started Jun 21 05:00:37 PM PDT 24
Finished Jun 21 05:00:40 PM PDT 24
Peak memory 205996 kb
Host smart-b6e643bb-2e89-4706-b9c4-8a2acb4f55bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42755
86222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.4275586222
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2634088221
Short name T1340
Test name
Test status
Simulation time 151875945 ps
CPU time 0.77 seconds
Started Jun 21 05:00:46 PM PDT 24
Finished Jun 21 05:00:50 PM PDT 24
Peak memory 205972 kb
Host smart-be226120-64f9-4995-aab7-b04261fee48e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26340
88221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2634088221
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1438428017
Short name T2001
Test name
Test status
Simulation time 217720490 ps
CPU time 0.9 seconds
Started Jun 21 05:00:43 PM PDT 24
Finished Jun 21 05:00:46 PM PDT 24
Peak memory 205968 kb
Host smart-35210310-227c-4530-a5c6-6ec8ee9ae52c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14384
28017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1438428017
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.756148411
Short name T450
Test name
Test status
Simulation time 8885552853 ps
CPU time 252.4 seconds
Started Jun 21 05:00:45 PM PDT 24
Finished Jun 21 05:04:59 PM PDT 24
Peak memory 206280 kb
Host smart-b2408a3a-c008-4db5-8c32-5e9e6e69e01f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=756148411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.756148411
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1806809055
Short name T2148
Test name
Test status
Simulation time 149564963 ps
CPU time 0.77 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:00:55 PM PDT 24
Peak memory 205932 kb
Host smart-faf8e445-a67f-4c87-bf79-80038eba10ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18068
09055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1806809055
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.2666755078
Short name T1160
Test name
Test status
Simulation time 166704483 ps
CPU time 0.79 seconds
Started Jun 21 05:00:38 PM PDT 24
Finished Jun 21 05:00:40 PM PDT 24
Peak memory 206020 kb
Host smart-be430313-a6be-452d-8042-f47469f42f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26667
55078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.2666755078
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.445502424
Short name T1842
Test name
Test status
Simulation time 4682395403 ps
CPU time 129.46 seconds
Started Jun 21 05:00:37 PM PDT 24
Finished Jun 21 05:02:49 PM PDT 24
Peak memory 206248 kb
Host smart-a53c645d-5252-4534-9618-5ff1f05248c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44550
2424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.445502424
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3174535422
Short name T1430
Test name
Test status
Simulation time 3607718673 ps
CPU time 4.83 seconds
Started Jun 21 05:00:49 PM PDT 24
Finished Jun 21 05:00:57 PM PDT 24
Peak memory 206284 kb
Host smart-9e85f0fa-007e-4936-87d3-44685625e2fa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3174535422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.3174535422
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1089631122
Short name T1886
Test name
Test status
Simulation time 13386001159 ps
CPU time 15.9 seconds
Started Jun 21 05:00:49 PM PDT 24
Finished Jun 21 05:01:07 PM PDT 24
Peak memory 206092 kb
Host smart-7f924894-5657-4170-918f-133db2e76603
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1089631122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1089631122
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3405570357
Short name T988
Test name
Test status
Simulation time 23448625524 ps
CPU time 24.24 seconds
Started Jun 21 05:00:47 PM PDT 24
Finished Jun 21 05:01:14 PM PDT 24
Peak memory 206260 kb
Host smart-6c3c29c3-b475-4a1b-a6f7-1178a7c28d0a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3405570357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.3405570357
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3044744625
Short name T1789
Test name
Test status
Simulation time 217390951 ps
CPU time 0.83 seconds
Started Jun 21 05:00:49 PM PDT 24
Finished Jun 21 05:00:53 PM PDT 24
Peak memory 205928 kb
Host smart-cf847b1e-42bc-4b76-bbd7-731785a70a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30447
44625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3044744625
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.1680914306
Short name T1135
Test name
Test status
Simulation time 150843048 ps
CPU time 0.82 seconds
Started Jun 21 05:00:49 PM PDT 24
Finished Jun 21 05:00:52 PM PDT 24
Peak memory 206024 kb
Host smart-ebbdb5f3-f593-470b-9578-833c772286d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16809
14306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.1680914306
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.745841725
Short name T615
Test name
Test status
Simulation time 200409320 ps
CPU time 0.89 seconds
Started Jun 21 05:00:46 PM PDT 24
Finished Jun 21 05:00:49 PM PDT 24
Peak memory 205936 kb
Host smart-3cadba97-04c1-4e1d-91ed-5410dfa065d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74584
1725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.745841725
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1663987967
Short name T1287
Test name
Test status
Simulation time 1209641615 ps
CPU time 2.73 seconds
Started Jun 21 05:00:47 PM PDT 24
Finished Jun 21 05:00:52 PM PDT 24
Peak memory 206196 kb
Host smart-2038c5e0-14e4-42db-a3c1-934e83881bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16639
87967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1663987967
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.3088063360
Short name T1327
Test name
Test status
Simulation time 11421520802 ps
CPU time 21.81 seconds
Started Jun 21 05:00:50 PM PDT 24
Finished Jun 21 05:01:15 PM PDT 24
Peak memory 206312 kb
Host smart-99499669-69a2-4581-a08c-e38b03cc20d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30880
63360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.3088063360
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.4214420916
Short name T2346
Test name
Test status
Simulation time 461270740 ps
CPU time 1.44 seconds
Started Jun 21 05:00:38 PM PDT 24
Finished Jun 21 05:00:42 PM PDT 24
Peak memory 206052 kb
Host smart-55d682c4-10d6-453d-b217-5f519b94f330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42144
20916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.4214420916
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.1203881539
Short name T1234
Test name
Test status
Simulation time 154642780 ps
CPU time 0.94 seconds
Started Jun 21 05:00:36 PM PDT 24
Finished Jun 21 05:00:39 PM PDT 24
Peak memory 206020 kb
Host smart-6b34c82a-c408-4207-9fb4-973646affcf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12038
81539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.1203881539
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2118685529
Short name T1858
Test name
Test status
Simulation time 68991909 ps
CPU time 0.66 seconds
Started Jun 21 05:00:47 PM PDT 24
Finished Jun 21 05:00:51 PM PDT 24
Peak memory 206012 kb
Host smart-d7200a65-1690-498d-a709-9ab8ba8a542b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21186
85529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2118685529
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.380771485
Short name T752
Test name
Test status
Simulation time 851653651 ps
CPU time 1.95 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:00:56 PM PDT 24
Peak memory 206236 kb
Host smart-3c81a699-7b16-4a7f-bfe2-b461b5b3512f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38077
1485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.380771485
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1637045342
Short name T318
Test name
Test status
Simulation time 466732179 ps
CPU time 2.55 seconds
Started Jun 21 05:00:41 PM PDT 24
Finished Jun 21 05:00:45 PM PDT 24
Peak memory 206200 kb
Host smart-7ae933db-0c9e-4543-9b80-0a62578b0905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16370
45342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1637045342
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.401005896
Short name T1796
Test name
Test status
Simulation time 184754197 ps
CPU time 0.86 seconds
Started Jun 21 05:00:53 PM PDT 24
Finished Jun 21 05:00:57 PM PDT 24
Peak memory 205972 kb
Host smart-04fcc244-3886-45b3-84a3-4c592fb63469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40100
5896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.401005896
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3678363178
Short name T1561
Test name
Test status
Simulation time 181243007 ps
CPU time 0.83 seconds
Started Jun 21 05:00:54 PM PDT 24
Finished Jun 21 05:00:58 PM PDT 24
Peak memory 206076 kb
Host smart-6c974d50-b805-4e03-a5f6-5dd897b6d161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36783
63178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3678363178
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1820534364
Short name T1129
Test name
Test status
Simulation time 184753101 ps
CPU time 0.9 seconds
Started Jun 21 05:00:54 PM PDT 24
Finished Jun 21 05:00:58 PM PDT 24
Peak memory 206024 kb
Host smart-b675662d-0b80-4ea6-b758-c21da1ab2232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18205
34364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1820534364
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.3991658334
Short name T1718
Test name
Test status
Simulation time 165007679 ps
CPU time 0.79 seconds
Started Jun 21 05:00:49 PM PDT 24
Finished Jun 21 05:00:53 PM PDT 24
Peak memory 205972 kb
Host smart-da1fc71c-a971-4842-ac18-eb77a648e9d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39916
58334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.3991658334
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.1855373359
Short name T337
Test name
Test status
Simulation time 23344017470 ps
CPU time 22.37 seconds
Started Jun 21 05:00:42 PM PDT 24
Finished Jun 21 05:01:06 PM PDT 24
Peak memory 205980 kb
Host smart-81549f35-88da-4943-87bb-70da929d03b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18553
73359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.1855373359
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2143336738
Short name T1280
Test name
Test status
Simulation time 3311344897 ps
CPU time 3.45 seconds
Started Jun 21 05:00:46 PM PDT 24
Finished Jun 21 05:00:51 PM PDT 24
Peak memory 206036 kb
Host smart-d6d52453-ba6c-45f9-a27c-7c97a42699c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21433
36738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2143336738
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3593235523
Short name T842
Test name
Test status
Simulation time 10224779243 ps
CPU time 284.08 seconds
Started Jun 21 05:00:53 PM PDT 24
Finished Jun 21 05:05:40 PM PDT 24
Peak memory 206304 kb
Host smart-b1670185-eb28-4d4c-9bce-965ecf30ce3f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3593235523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3593235523
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.461217495
Short name T1670
Test name
Test status
Simulation time 245339863 ps
CPU time 0.91 seconds
Started Jun 21 05:00:49 PM PDT 24
Finished Jun 21 05:00:53 PM PDT 24
Peak memory 205956 kb
Host smart-0bdfe050-7a42-48bc-addb-71e498966b05
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=461217495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.461217495
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1920855195
Short name T1111
Test name
Test status
Simulation time 219569466 ps
CPU time 0.89 seconds
Started Jun 21 05:00:58 PM PDT 24
Finished Jun 21 05:01:02 PM PDT 24
Peak memory 206016 kb
Host smart-15f6392f-375b-4351-bb3f-0c83d2e733f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19208
55195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1920855195
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.4102271509
Short name T2181
Test name
Test status
Simulation time 8852435106 ps
CPU time 61.72 seconds
Started Jun 21 05:00:55 PM PDT 24
Finished Jun 21 05:02:00 PM PDT 24
Peak memory 206340 kb
Host smart-be64ec0b-847b-4c0e-bfe7-b7e249fa7536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41022
71509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.4102271509
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.2585569586
Short name T1253
Test name
Test status
Simulation time 6799402261 ps
CPU time 186.44 seconds
Started Jun 21 05:00:56 PM PDT 24
Finished Jun 21 05:04:06 PM PDT 24
Peak memory 206216 kb
Host smart-e5ecb6b0-f9ae-4a26-834c-8eefaef0e63c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2585569586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.2585569586
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.2611679269
Short name T516
Test name
Test status
Simulation time 217227316 ps
CPU time 0.87 seconds
Started Jun 21 05:00:48 PM PDT 24
Finished Jun 21 05:00:52 PM PDT 24
Peak memory 205992 kb
Host smart-53a91584-215c-4396-be65-abb65fc1ef19
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2611679269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.2611679269
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2540775293
Short name T2358
Test name
Test status
Simulation time 144844777 ps
CPU time 0.76 seconds
Started Jun 21 05:00:48 PM PDT 24
Finished Jun 21 05:00:51 PM PDT 24
Peak memory 205976 kb
Host smart-2ee9632b-1268-49ac-9d30-2798af658b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25407
75293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2540775293
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2363437680
Short name T65
Test name
Test status
Simulation time 211672478 ps
CPU time 0.9 seconds
Started Jun 21 05:00:45 PM PDT 24
Finished Jun 21 05:00:48 PM PDT 24
Peak memory 206024 kb
Host smart-779bde88-b8c3-4085-9ecc-c99fbc52c6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23634
37680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2363437680
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.2672773057
Short name T1874
Test name
Test status
Simulation time 198222232 ps
CPU time 0.85 seconds
Started Jun 21 05:00:52 PM PDT 24
Finished Jun 21 05:00:56 PM PDT 24
Peak memory 206024 kb
Host smart-273ef095-a4f9-4f0c-a0db-ab36d883dd70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26727
73057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2672773057
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.314364901
Short name T1337
Test name
Test status
Simulation time 176029933 ps
CPU time 0.77 seconds
Started Jun 21 05:00:48 PM PDT 24
Finished Jun 21 05:00:52 PM PDT 24
Peak memory 206020 kb
Host smart-e5cc687e-d5f7-4e7e-8d0d-f85005a3a1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31436
4901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.314364901
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2396952874
Short name T349
Test name
Test status
Simulation time 180146068 ps
CPU time 0.84 seconds
Started Jun 21 05:00:46 PM PDT 24
Finished Jun 21 05:00:49 PM PDT 24
Peak memory 206020 kb
Host smart-81f1f131-31f7-4bd7-a45e-c58ca80a5261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23969
52874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2396952874
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1701717194
Short name T179
Test name
Test status
Simulation time 153882546 ps
CPU time 0.87 seconds
Started Jun 21 05:00:46 PM PDT 24
Finished Jun 21 05:00:49 PM PDT 24
Peak memory 206004 kb
Host smart-32ca238e-df7e-4ef9-b252-89087b365aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17017
17194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1701717194
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.3463526133
Short name T673
Test name
Test status
Simulation time 213620639 ps
CPU time 0.9 seconds
Started Jun 21 05:00:49 PM PDT 24
Finished Jun 21 05:00:53 PM PDT 24
Peak memory 206008 kb
Host smart-db56b8c9-3588-4e38-ae1b-aa1b3b82e9a3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3463526133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3463526133
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3371398840
Short name T1674
Test name
Test status
Simulation time 190456512 ps
CPU time 0.78 seconds
Started Jun 21 05:00:56 PM PDT 24
Finished Jun 21 05:01:00 PM PDT 24
Peak memory 206008 kb
Host smart-3a78020d-77f6-4eb0-99a5-5164bd53dbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33713
98840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3371398840
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3201880523
Short name T1569
Test name
Test status
Simulation time 36723315 ps
CPU time 0.64 seconds
Started Jun 21 05:00:47 PM PDT 24
Finished Jun 21 05:00:50 PM PDT 24
Peak memory 205948 kb
Host smart-e712cf9a-5347-4942-bdd2-731bad06d97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32018
80523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3201880523
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3304660174
Short name T2272
Test name
Test status
Simulation time 6262613346 ps
CPU time 13.41 seconds
Started Jun 21 05:00:55 PM PDT 24
Finished Jun 21 05:01:12 PM PDT 24
Peak memory 206260 kb
Host smart-8e634c18-ac71-4aa2-924a-3fb0eb4e14ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33046
60174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3304660174
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.4005268488
Short name T887
Test name
Test status
Simulation time 189168450 ps
CPU time 0.85 seconds
Started Jun 21 05:00:50 PM PDT 24
Finished Jun 21 05:00:54 PM PDT 24
Peak memory 206028 kb
Host smart-9a9f2ace-52e3-4006-9abe-1b5140bb2f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40052
68488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.4005268488
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.528580451
Short name T552
Test name
Test status
Simulation time 223382934 ps
CPU time 0.89 seconds
Started Jun 21 05:00:45 PM PDT 24
Finished Jun 21 05:00:49 PM PDT 24
Peak memory 205992 kb
Host smart-907224e6-5c89-4432-a658-dc1b8cbdce09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52858
0451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.528580451
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.2755321964
Short name T1933
Test name
Test status
Simulation time 252809777 ps
CPU time 0.93 seconds
Started Jun 21 05:00:58 PM PDT 24
Finished Jun 21 05:01:02 PM PDT 24
Peak memory 206028 kb
Host smart-02653722-4e8c-423d-8f8a-aadd98c8565a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27553
21964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.2755321964
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.3289015451
Short name T727
Test name
Test status
Simulation time 174984614 ps
CPU time 0.83 seconds
Started Jun 21 05:00:42 PM PDT 24
Finished Jun 21 05:00:44 PM PDT 24
Peak memory 205980 kb
Host smart-0b354420-a996-4726-8b23-196097a2e5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32890
15451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.3289015451
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2985192019
Short name T946
Test name
Test status
Simulation time 145162589 ps
CPU time 0.8 seconds
Started Jun 21 05:00:52 PM PDT 24
Finished Jun 21 05:00:56 PM PDT 24
Peak memory 205964 kb
Host smart-54207323-e65b-45a4-8e6c-653419f4166b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29851
92019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2985192019
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.1823534166
Short name T1444
Test name
Test status
Simulation time 151824991 ps
CPU time 0.74 seconds
Started Jun 21 05:00:44 PM PDT 24
Finished Jun 21 05:00:46 PM PDT 24
Peak memory 205956 kb
Host smart-96889044-7e75-4e62-a9a6-577f16952bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18235
34166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1823534166
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3250500399
Short name T2138
Test name
Test status
Simulation time 148705955 ps
CPU time 0.8 seconds
Started Jun 21 05:00:50 PM PDT 24
Finished Jun 21 05:00:54 PM PDT 24
Peak memory 206004 kb
Host smart-f5de3f06-d873-4cb8-b5f6-1b84818b2746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32505
00399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3250500399
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.871677178
Short name T1638
Test name
Test status
Simulation time 232308059 ps
CPU time 0.91 seconds
Started Jun 21 05:00:36 PM PDT 24
Finished Jun 21 05:00:39 PM PDT 24
Peak memory 205928 kb
Host smart-e31386b7-ef67-4c5a-a5b0-65cca6440cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87167
7178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.871677178
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.416512368
Short name T1626
Test name
Test status
Simulation time 9670472296 ps
CPU time 70.58 seconds
Started Jun 21 05:00:45 PM PDT 24
Finished Jun 21 05:01:58 PM PDT 24
Peak memory 206288 kb
Host smart-de32f953-b960-44f6-97d7-ababbe8d9ce1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=416512368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.416512368
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.998799788
Short name T738
Test name
Test status
Simulation time 246700186 ps
CPU time 0.92 seconds
Started Jun 21 05:00:45 PM PDT 24
Finished Jun 21 05:00:48 PM PDT 24
Peak memory 206020 kb
Host smart-e8cb9926-265d-4b48-a1e4-d63e7c771b0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99879
9788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.998799788
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.3850777040
Short name T662
Test name
Test status
Simulation time 176909511 ps
CPU time 0.85 seconds
Started Jun 21 05:00:50 PM PDT 24
Finished Jun 21 05:00:54 PM PDT 24
Peak memory 206020 kb
Host smart-d90a776c-a498-4361-8c91-f9bba11cd11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38507
77040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.3850777040
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.87705572
Short name T1333
Test name
Test status
Simulation time 5282816565 ps
CPU time 142.64 seconds
Started Jun 21 05:00:57 PM PDT 24
Finished Jun 21 05:03:23 PM PDT 24
Peak memory 206288 kb
Host smart-7cd28fbc-8c97-404c-b62b-71ae24f28416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87705
572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.87705572
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.2216489195
Short name T652
Test name
Test status
Simulation time 3584326544 ps
CPU time 5.36 seconds
Started Jun 21 05:00:48 PM PDT 24
Finished Jun 21 05:00:56 PM PDT 24
Peak memory 206248 kb
Host smart-2c27b4ed-152f-4a4a-9df9-f804ae2aa82e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2216489195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.2216489195
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.2777052719
Short name T359
Test name
Test status
Simulation time 13391323162 ps
CPU time 13.34 seconds
Started Jun 21 05:00:44 PM PDT 24
Finished Jun 21 05:00:59 PM PDT 24
Peak memory 206264 kb
Host smart-40968761-239b-410d-bfde-220a158340bb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2777052719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.2777052719
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.1317398507
Short name T1090
Test name
Test status
Simulation time 23346271246 ps
CPU time 25.05 seconds
Started Jun 21 05:00:48 PM PDT 24
Finished Jun 21 05:01:16 PM PDT 24
Peak memory 206088 kb
Host smart-23d07461-47a4-4899-8bc4-778a65aebc5a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1317398507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.1317398507
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2133929760
Short name T1536
Test name
Test status
Simulation time 173150553 ps
CPU time 0.76 seconds
Started Jun 21 05:00:46 PM PDT 24
Finished Jun 21 05:00:48 PM PDT 24
Peak memory 205996 kb
Host smart-6ee2d349-7e94-4464-9aa9-b8b4b7f39a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21339
29760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2133929760
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2039876689
Short name T1835
Test name
Test status
Simulation time 149169120 ps
CPU time 0.81 seconds
Started Jun 21 05:00:47 PM PDT 24
Finished Jun 21 05:00:50 PM PDT 24
Peak memory 205996 kb
Host smart-d7440b17-6c08-4f88-a04e-72afba0d20c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20398
76689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2039876689
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.1531389504
Short name T1932
Test name
Test status
Simulation time 298883742 ps
CPU time 1.09 seconds
Started Jun 21 05:00:54 PM PDT 24
Finished Jun 21 05:00:59 PM PDT 24
Peak memory 206024 kb
Host smart-2fbf89fe-ff83-4f4d-b147-2df7b2d78de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15313
89504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.1531389504
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.2706081498
Short name T1709
Test name
Test status
Simulation time 564554699 ps
CPU time 1.47 seconds
Started Jun 21 05:00:44 PM PDT 24
Finished Jun 21 05:00:48 PM PDT 24
Peak memory 206028 kb
Host smart-688f6aa1-8ebc-4851-bbcf-24749c95c016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27060
81498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.2706081498
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.1295934847
Short name T871
Test name
Test status
Simulation time 16964325487 ps
CPU time 31.59 seconds
Started Jun 21 05:00:48 PM PDT 24
Finished Jun 21 05:01:22 PM PDT 24
Peak memory 206244 kb
Host smart-0e4e1a27-4349-4307-a0bf-54aed023d28a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12959
34847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.1295934847
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.4035605455
Short name T797
Test name
Test status
Simulation time 524806846 ps
CPU time 1.43 seconds
Started Jun 21 05:00:49 PM PDT 24
Finished Jun 21 05:00:54 PM PDT 24
Peak memory 206084 kb
Host smart-4e945d24-323d-49ff-a1ef-99e77a85254f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40356
05455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.4035605455
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.1975790579
Short name T1993
Test name
Test status
Simulation time 146110705 ps
CPU time 0.73 seconds
Started Jun 21 05:00:42 PM PDT 24
Finished Jun 21 05:00:44 PM PDT 24
Peak memory 206020 kb
Host smart-aa38ef49-f0df-45fe-9623-17be2ef28ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19757
90579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.1975790579
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3771889695
Short name T2311
Test name
Test status
Simulation time 36854131 ps
CPU time 0.67 seconds
Started Jun 21 05:00:54 PM PDT 24
Finished Jun 21 05:00:58 PM PDT 24
Peak memory 205996 kb
Host smart-684b3d16-8bce-42e7-adc4-ce8e2f413aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37718
89695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3771889695
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2752532200
Short name T412
Test name
Test status
Simulation time 973494899 ps
CPU time 2.38 seconds
Started Jun 21 05:00:45 PM PDT 24
Finished Jun 21 05:00:50 PM PDT 24
Peak memory 206144 kb
Host smart-361a1f5d-3f02-482e-aa49-19ed7e1601e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27525
32200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2752532200
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1021755942
Short name T333
Test name
Test status
Simulation time 262143704 ps
CPU time 1.92 seconds
Started Jun 21 05:00:58 PM PDT 24
Finished Jun 21 05:01:03 PM PDT 24
Peak memory 206088 kb
Host smart-b6c26eed-352e-456a-9fe8-d73f3c0529a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10217
55942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1021755942
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.781226099
Short name T542
Test name
Test status
Simulation time 225494451 ps
CPU time 0.88 seconds
Started Jun 21 05:00:57 PM PDT 24
Finished Jun 21 05:01:01 PM PDT 24
Peak memory 206024 kb
Host smart-2f7f0148-0972-439b-80a7-9b28742f8460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78122
6099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.781226099
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3955243893
Short name T1032
Test name
Test status
Simulation time 166051552 ps
CPU time 0.76 seconds
Started Jun 21 05:00:54 PM PDT 24
Finished Jun 21 05:00:58 PM PDT 24
Peak memory 205952 kb
Host smart-dde48a05-bc78-42c6-973b-1fe786324b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39552
43893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3955243893
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3335410316
Short name T2024
Test name
Test status
Simulation time 241861905 ps
CPU time 0.87 seconds
Started Jun 21 05:00:45 PM PDT 24
Finished Jun 21 05:00:48 PM PDT 24
Peak memory 205972 kb
Host smart-2ccc237b-6e19-4724-8834-f4040afb69a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33354
10316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3335410316
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.1198948423
Short name T1899
Test name
Test status
Simulation time 14074567023 ps
CPU time 132.68 seconds
Started Jun 21 05:00:48 PM PDT 24
Finished Jun 21 05:03:04 PM PDT 24
Peak memory 206192 kb
Host smart-29520a4a-9578-465a-9cc0-535f0dcd52bd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1198948423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.1198948423
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.1912517539
Short name T1890
Test name
Test status
Simulation time 218695885 ps
CPU time 0.86 seconds
Started Jun 21 05:00:48 PM PDT 24
Finished Jun 21 05:00:51 PM PDT 24
Peak memory 205968 kb
Host smart-3794e684-bfbd-4221-b83c-1d4c53e5e0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19125
17539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.1912517539
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.1313242388
Short name T1023
Test name
Test status
Simulation time 23305619398 ps
CPU time 22.58 seconds
Started Jun 21 05:00:57 PM PDT 24
Finished Jun 21 05:01:23 PM PDT 24
Peak memory 206028 kb
Host smart-14b94bbf-8d3a-4ff0-8044-18a1e823f96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13132
42388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.1313242388
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1237110866
Short name T1317
Test name
Test status
Simulation time 3405833113 ps
CPU time 3.74 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:00:58 PM PDT 24
Peak memory 206004 kb
Host smart-f33f714c-f0dc-44a6-a790-a757eac7e66c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12371
10866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1237110866
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.1641895065
Short name T576
Test name
Test status
Simulation time 10080880863 ps
CPU time 71.39 seconds
Started Jun 21 05:00:48 PM PDT 24
Finished Jun 21 05:02:02 PM PDT 24
Peak memory 206360 kb
Host smart-d60b4b8b-343c-48d8-b5a0-4ebaffbda31e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1641895065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.1641895065
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.1886783850
Short name T894
Test name
Test status
Simulation time 286689307 ps
CPU time 0.94 seconds
Started Jun 21 05:00:56 PM PDT 24
Finished Jun 21 05:01:00 PM PDT 24
Peak memory 206048 kb
Host smart-d0a9974c-6998-4bb7-a0a9-57842ab56034
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1886783850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.1886783850
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1770224020
Short name T1678
Test name
Test status
Simulation time 181324742 ps
CPU time 0.82 seconds
Started Jun 21 05:00:47 PM PDT 24
Finished Jun 21 05:00:50 PM PDT 24
Peak memory 205980 kb
Host smart-184f615f-c470-44da-aa34-dd44e18ee989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17702
24020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1770224020
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.4237850634
Short name T482
Test name
Test status
Simulation time 5958974737 ps
CPU time 59.18 seconds
Started Jun 21 05:00:44 PM PDT 24
Finished Jun 21 05:01:45 PM PDT 24
Peak memory 206200 kb
Host smart-25520f2f-aff1-4bf1-be17-b635f3884ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42378
50634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.4237850634
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.669461060
Short name T2450
Test name
Test status
Simulation time 10498932411 ps
CPU time 306.41 seconds
Started Jun 21 05:00:55 PM PDT 24
Finished Jun 21 05:06:05 PM PDT 24
Peak memory 206272 kb
Host smart-61e00469-e7b9-4ca3-96c8-b24ce9f5ea84
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=669461060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.669461060
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2668192386
Short name T2318
Test name
Test status
Simulation time 186075640 ps
CPU time 0.88 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:00:55 PM PDT 24
Peak memory 205984 kb
Host smart-6eb41cbf-8e36-4aee-8e5f-6588ddceeb97
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2668192386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2668192386
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2134836955
Short name T2290
Test name
Test status
Simulation time 142601165 ps
CPU time 0.78 seconds
Started Jun 21 05:00:48 PM PDT 24
Finished Jun 21 05:00:52 PM PDT 24
Peak memory 206032 kb
Host smart-ad2738d6-785d-40e5-b636-827b7f87f771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21348
36955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2134836955
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2568083902
Short name T1611
Test name
Test status
Simulation time 175814343 ps
CPU time 0.8 seconds
Started Jun 21 05:00:56 PM PDT 24
Finished Jun 21 05:01:00 PM PDT 24
Peak memory 206032 kb
Host smart-61e404a3-e8a3-4823-8a06-bee389d7606d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25680
83902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2568083902
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.2561339639
Short name T1540
Test name
Test status
Simulation time 139624714 ps
CPU time 0.78 seconds
Started Jun 21 05:00:48 PM PDT 24
Finished Jun 21 05:00:52 PM PDT 24
Peak memory 206020 kb
Host smart-760ff4c6-96dd-40fc-9551-2a80387a4eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25613
39639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.2561339639
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1673100215
Short name T604
Test name
Test status
Simulation time 184860756 ps
CPU time 0.83 seconds
Started Jun 21 05:00:48 PM PDT 24
Finished Jun 21 05:00:52 PM PDT 24
Peak memory 206024 kb
Host smart-682fcb6e-8846-49db-9e83-ed4f5fdab406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16731
00215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1673100215
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.807359514
Short name T1116
Test name
Test status
Simulation time 169573918 ps
CPU time 0.78 seconds
Started Jun 21 05:00:53 PM PDT 24
Finished Jun 21 05:00:56 PM PDT 24
Peak memory 206020 kb
Host smart-c78cd38a-4ba7-4e0d-832b-e5ba6519c15e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80735
9514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.807359514
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.1905561004
Short name T1371
Test name
Test status
Simulation time 155563412 ps
CPU time 0.82 seconds
Started Jun 21 05:00:44 PM PDT 24
Finished Jun 21 05:00:47 PM PDT 24
Peak memory 206020 kb
Host smart-97799213-626f-4193-9dbb-527800393549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19055
61004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.1905561004
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.1292858040
Short name T1940
Test name
Test status
Simulation time 189051587 ps
CPU time 0.89 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:00:55 PM PDT 24
Peak memory 205896 kb
Host smart-f9a94568-f2d0-4b89-ab8d-c6a2723a1b6e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1292858040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.1292858040
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.658143245
Short name T92
Test name
Test status
Simulation time 151099470 ps
CPU time 0.84 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:00:55 PM PDT 24
Peak memory 205844 kb
Host smart-d22ee42e-ae01-4973-a8fa-132f898a6fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65814
3245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.658143245
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.834667459
Short name T1694
Test name
Test status
Simulation time 89360595 ps
CPU time 0.77 seconds
Started Jun 21 05:00:56 PM PDT 24
Finished Jun 21 05:01:00 PM PDT 24
Peak memory 206032 kb
Host smart-c3363d6b-3b05-4cc3-9366-82160054850e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83466
7459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.834667459
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1484344629
Short name T2118
Test name
Test status
Simulation time 11575794125 ps
CPU time 25.63 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:01:20 PM PDT 24
Peak memory 206316 kb
Host smart-24abceb9-1684-4273-badd-aeb8c2245bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14843
44629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1484344629
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.3354636542
Short name T1972
Test name
Test status
Simulation time 208627626 ps
CPU time 0.85 seconds
Started Jun 21 05:00:45 PM PDT 24
Finished Jun 21 05:00:47 PM PDT 24
Peak memory 206052 kb
Host smart-51c87814-5ba1-4dfc-9b78-4f04f60eb9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33546
36542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3354636542
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.124159774
Short name T719
Test name
Test status
Simulation time 226310793 ps
CPU time 0.89 seconds
Started Jun 21 05:00:44 PM PDT 24
Finished Jun 21 05:00:47 PM PDT 24
Peak memory 206044 kb
Host smart-c39e0c8b-51b5-4f8d-90e1-b34330f18551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12415
9774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.124159774
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.805672243
Short name T1676
Test name
Test status
Simulation time 200296397 ps
CPU time 0.85 seconds
Started Jun 21 05:00:56 PM PDT 24
Finished Jun 21 05:01:01 PM PDT 24
Peak memory 205960 kb
Host smart-0c485a2f-ab50-4232-be2e-e183e2a95ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80567
2243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.805672243
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.3273472783
Short name T2504
Test name
Test status
Simulation time 169714424 ps
CPU time 0.78 seconds
Started Jun 21 05:00:57 PM PDT 24
Finished Jun 21 05:01:01 PM PDT 24
Peak memory 206036 kb
Host smart-c21a742b-d359-43a0-9f03-85050e7bc2a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32734
72783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.3273472783
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.180808380
Short name T1742
Test name
Test status
Simulation time 166548423 ps
CPU time 0.86 seconds
Started Jun 21 05:00:58 PM PDT 24
Finished Jun 21 05:01:02 PM PDT 24
Peak memory 206036 kb
Host smart-deb6b990-6e21-4c21-8aff-ee0a4ba4c081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18080
8380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.180808380
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.2075495521
Short name T1672
Test name
Test status
Simulation time 147448522 ps
CPU time 0.78 seconds
Started Jun 21 05:00:55 PM PDT 24
Finished Jun 21 05:00:59 PM PDT 24
Peak memory 206016 kb
Host smart-16bcba2a-4208-4d36-9746-1682fa1443cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20754
95521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2075495521
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1241744500
Short name T2423
Test name
Test status
Simulation time 159980754 ps
CPU time 0.81 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:00:55 PM PDT 24
Peak memory 205916 kb
Host smart-590aac66-8bff-4401-ae56-4df91b573ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12417
44500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1241744500
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2501574032
Short name T1110
Test name
Test status
Simulation time 233312373 ps
CPU time 0.92 seconds
Started Jun 21 05:00:47 PM PDT 24
Finished Jun 21 05:00:51 PM PDT 24
Peak memory 205972 kb
Host smart-3361b012-95cb-47fd-baf6-1e5937836841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25015
74032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2501574032
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.2043403368
Short name T319
Test name
Test status
Simulation time 5918479515 ps
CPU time 42.84 seconds
Started Jun 21 05:00:55 PM PDT 24
Finished Jun 21 05:01:41 PM PDT 24
Peak memory 206304 kb
Host smart-43377fd1-1fc3-438d-847b-6cad8517b888
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2043403368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.2043403368
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1724550734
Short name T901
Test name
Test status
Simulation time 183440499 ps
CPU time 0.89 seconds
Started Jun 21 05:00:50 PM PDT 24
Finished Jun 21 05:00:54 PM PDT 24
Peak memory 206032 kb
Host smart-efe99727-45fb-47d4-ac2f-a479616c3aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17245
50734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1724550734
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2786421209
Short name T22
Test name
Test status
Simulation time 177994169 ps
CPU time 0.85 seconds
Started Jun 21 05:00:55 PM PDT 24
Finished Jun 21 05:00:59 PM PDT 24
Peak memory 205996 kb
Host smart-00d42710-40f0-4887-a48e-8acc6c4987d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27864
21209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2786421209
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.445187583
Short name T1161
Test name
Test status
Simulation time 6575466612 ps
CPU time 45.54 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:01:40 PM PDT 24
Peak memory 206260 kb
Host smart-6347d3ff-acc5-4a4d-a3cd-02537b0a3744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44518
7583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.445187583
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.3805163158
Short name T667
Test name
Test status
Simulation time 3555080788 ps
CPU time 4.52 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:00:59 PM PDT 24
Peak memory 206108 kb
Host smart-1fdf276f-4577-4186-9e7e-0dadb8c65af2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3805163158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.3805163158
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.4037905065
Short name T669
Test name
Test status
Simulation time 13344085828 ps
CPU time 13.02 seconds
Started Jun 21 05:02:31 PM PDT 24
Finished Jun 21 05:02:46 PM PDT 24
Peak memory 205156 kb
Host smart-f47a56f8-816b-4733-aafe-4f4940848be9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4037905065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.4037905065
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.2753521166
Short name T503
Test name
Test status
Simulation time 23426297527 ps
CPU time 28.21 seconds
Started Jun 21 05:00:59 PM PDT 24
Finished Jun 21 05:01:30 PM PDT 24
Peak memory 206088 kb
Host smart-d33b66a0-4bea-40ba-b1dc-c29135587145
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2753521166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.2753521166
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.781510823
Short name T1438
Test name
Test status
Simulation time 154236111 ps
CPU time 0.77 seconds
Started Jun 21 05:00:50 PM PDT 24
Finished Jun 21 05:00:54 PM PDT 24
Peak memory 205960 kb
Host smart-d8ef5d53-5efb-402c-b7b7-43b6c8622d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78151
0823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.781510823
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.2683056428
Short name T1864
Test name
Test status
Simulation time 152682519 ps
CPU time 0.78 seconds
Started Jun 21 05:00:59 PM PDT 24
Finished Jun 21 05:01:02 PM PDT 24
Peak memory 206024 kb
Host smart-cf9b5316-95d2-4a2a-88b8-fc2b15f571d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26830
56428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.2683056428
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.3174921174
Short name T1244
Test name
Test status
Simulation time 645632677 ps
CPU time 1.78 seconds
Started Jun 21 05:00:59 PM PDT 24
Finished Jun 21 05:01:03 PM PDT 24
Peak memory 206096 kb
Host smart-11783645-a665-4d9d-b5cd-b2acdf8ab8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31749
21174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.3174921174
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1348554864
Short name T1225
Test name
Test status
Simulation time 978187717 ps
CPU time 2.36 seconds
Started Jun 21 05:00:55 PM PDT 24
Finished Jun 21 05:01:01 PM PDT 24
Peak memory 206240 kb
Host smart-08695611-7e5a-40d9-ba21-fc4ff0f4a56e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13485
54864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1348554864
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.3157001644
Short name T1323
Test name
Test status
Simulation time 13842435190 ps
CPU time 25.09 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:01:19 PM PDT 24
Peak memory 206280 kb
Host smart-95cc2579-fc8e-4be4-8d87-27a2e9a97fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31570
01644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.3157001644
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.1619582791
Short name T470
Test name
Test status
Simulation time 456013166 ps
CPU time 1.6 seconds
Started Jun 21 05:00:58 PM PDT 24
Finished Jun 21 05:01:03 PM PDT 24
Peak memory 206008 kb
Host smart-8b0c8e0b-363e-4650-bc34-3e7f182cb903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16195
82791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.1619582791
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.1087997121
Short name T2296
Test name
Test status
Simulation time 144266736 ps
CPU time 0.77 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:00:55 PM PDT 24
Peak memory 206024 kb
Host smart-d3979df4-a220-4e5d-9b8f-a525d852dbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10879
97121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1087997121
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.182124910
Short name T568
Test name
Test status
Simulation time 40072145 ps
CPU time 0.69 seconds
Started Jun 21 05:01:06 PM PDT 24
Finished Jun 21 05:01:09 PM PDT 24
Peak memory 205568 kb
Host smart-ce06c091-923d-42eb-abc5-c29857aee5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18212
4910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.182124910
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.3976474671
Short name T2342
Test name
Test status
Simulation time 986255146 ps
CPU time 2.09 seconds
Started Jun 21 05:00:56 PM PDT 24
Finished Jun 21 05:01:01 PM PDT 24
Peak memory 206172 kb
Host smart-8c2ea155-89ad-4587-9770-79c3a529f506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39764
74671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.3976474671
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1954715284
Short name T1273
Test name
Test status
Simulation time 250275957 ps
CPU time 1.48 seconds
Started Jun 21 05:00:56 PM PDT 24
Finished Jun 21 05:01:00 PM PDT 24
Peak memory 206172 kb
Host smart-2c48b183-d236-4779-a28a-50f240822ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19547
15284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1954715284
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.994853688
Short name T1680
Test name
Test status
Simulation time 197352345 ps
CPU time 0.89 seconds
Started Jun 21 05:01:08 PM PDT 24
Finished Jun 21 05:01:11 PM PDT 24
Peak memory 205948 kb
Host smart-f4fd837d-f008-4976-8d7a-b3c967a992f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99485
3688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.994853688
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1999662527
Short name T1573
Test name
Test status
Simulation time 146926150 ps
CPU time 0.74 seconds
Started Jun 21 05:01:06 PM PDT 24
Finished Jun 21 05:01:09 PM PDT 24
Peak memory 206016 kb
Host smart-590d1245-6cb6-4525-8435-28c9b14b9c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19996
62527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1999662527
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1084824110
Short name T1388
Test name
Test status
Simulation time 183615450 ps
CPU time 0.87 seconds
Started Jun 21 05:00:56 PM PDT 24
Finished Jun 21 05:01:00 PM PDT 24
Peak memory 206024 kb
Host smart-fc3fd456-f261-462f-8c89-a20f8183deb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10848
24110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1084824110
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3859975451
Short name T1295
Test name
Test status
Simulation time 222288457 ps
CPU time 0.93 seconds
Started Jun 21 05:01:02 PM PDT 24
Finished Jun 21 05:01:05 PM PDT 24
Peak memory 206000 kb
Host smart-b7d2fcaa-2264-49c0-a6e8-c91869a346b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38599
75451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3859975451
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.789395549
Short name T517
Test name
Test status
Simulation time 23266108777 ps
CPU time 27.96 seconds
Started Jun 21 05:00:51 PM PDT 24
Finished Jun 21 05:01:23 PM PDT 24
Peak memory 206088 kb
Host smart-35c67ddb-b3d0-47a1-8141-32afbfac6531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78939
5549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.789395549
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.3076376747
Short name T386
Test name
Test status
Simulation time 3351768867 ps
CPU time 3.52 seconds
Started Jun 21 05:00:53 PM PDT 24
Finished Jun 21 05:01:00 PM PDT 24
Peak memory 206024 kb
Host smart-7011ded6-71e4-4ed1-9252-985a63b07814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30763
76747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.3076376747
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2962464018
Short name T1887
Test name
Test status
Simulation time 8185813783 ps
CPU time 225.17 seconds
Started Jun 21 05:00:58 PM PDT 24
Finished Jun 21 05:04:46 PM PDT 24
Peak memory 206272 kb
Host smart-a3e63d51-a0b9-4df1-9e0c-53975a2566d0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2962464018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2962464018
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.1673136759
Short name T2101
Test name
Test status
Simulation time 238428886 ps
CPU time 0.92 seconds
Started Jun 21 05:01:04 PM PDT 24
Finished Jun 21 05:01:07 PM PDT 24
Peak memory 205948 kb
Host smart-b208a467-ec15-4eb8-a6a9-73fe811b97f8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1673136759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.1673136759
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3989842915
Short name T2458
Test name
Test status
Simulation time 197068459 ps
CPU time 0.83 seconds
Started Jun 21 05:01:06 PM PDT 24
Finished Jun 21 05:01:09 PM PDT 24
Peak memory 205984 kb
Host smart-b90f59e1-eadd-4c05-804b-d6fc46a8d89a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39898
42915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3989842915
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.2248707434
Short name T2186
Test name
Test status
Simulation time 11767236686 ps
CPU time 116.81 seconds
Started Jun 21 05:00:57 PM PDT 24
Finished Jun 21 05:02:57 PM PDT 24
Peak memory 206332 kb
Host smart-34fd338c-597b-4739-8fc1-2d8d69a1f2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22487
07434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.2248707434
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.34868760
Short name T1765
Test name
Test status
Simulation time 4714700923 ps
CPU time 31.45 seconds
Started Jun 21 05:00:53 PM PDT 24
Finished Jun 21 05:01:28 PM PDT 24
Peak memory 206220 kb
Host smart-d6d629fb-8917-4593-b279-6355457aa7be
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=34868760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.34868760
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.3589689487
Short name T2009
Test name
Test status
Simulation time 193020552 ps
CPU time 0.86 seconds
Started Jun 21 05:01:04 PM PDT 24
Finished Jun 21 05:01:07 PM PDT 24
Peak memory 205992 kb
Host smart-2391af0b-4af1-44b6-8a67-6c1748585bad
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3589689487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.3589689487
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1088473776
Short name T2020
Test name
Test status
Simulation time 145805691 ps
CPU time 0.75 seconds
Started Jun 21 05:01:06 PM PDT 24
Finished Jun 21 05:01:09 PM PDT 24
Peak memory 205980 kb
Host smart-77a34699-1ca2-4ef2-b797-201560fa0bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10884
73776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1088473776
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.992895367
Short name T1339
Test name
Test status
Simulation time 220561592 ps
CPU time 0.87 seconds
Started Jun 21 05:00:53 PM PDT 24
Finished Jun 21 05:00:57 PM PDT 24
Peak memory 206076 kb
Host smart-1572da73-fa74-4076-b911-73c91acca49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99289
5367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.992895367
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.3097877785
Short name T1440
Test name
Test status
Simulation time 183557630 ps
CPU time 0.83 seconds
Started Jun 21 05:00:58 PM PDT 24
Finished Jun 21 05:01:02 PM PDT 24
Peak memory 206024 kb
Host smart-5193844b-adaa-4b9e-baa1-77ba44dc5d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30978
77785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3097877785
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.823471940
Short name T2493
Test name
Test status
Simulation time 173175146 ps
CPU time 0.77 seconds
Started Jun 21 05:00:57 PM PDT 24
Finished Jun 21 05:01:01 PM PDT 24
Peak memory 205964 kb
Host smart-8e5e6eaf-6446-4329-8ebb-7f0a0496eabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82347
1940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.823471940
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2088016935
Short name T2471
Test name
Test status
Simulation time 208137653 ps
CPU time 0.76 seconds
Started Jun 21 05:02:45 PM PDT 24
Finished Jun 21 05:02:50 PM PDT 24
Peak memory 205708 kb
Host smart-f396c8a7-380e-41a6-8ab1-c90b69f4de95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20880
16935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2088016935
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.3519765292
Short name T1394
Test name
Test status
Simulation time 145881163 ps
CPU time 0.86 seconds
Started Jun 21 05:01:03 PM PDT 24
Finished Jun 21 05:01:05 PM PDT 24
Peak memory 206004 kb
Host smart-7c937b81-674c-45e9-ac1d-2d02ee79ab85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35197
65292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.3519765292
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1115883896
Short name T332
Test name
Test status
Simulation time 259324860 ps
CPU time 1.02 seconds
Started Jun 21 05:00:57 PM PDT 24
Finished Jun 21 05:01:02 PM PDT 24
Peak memory 206048 kb
Host smart-08963322-ef2b-4836-a310-4c9209fe1a26
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1115883896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1115883896
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1980322184
Short name T1957
Test name
Test status
Simulation time 154999401 ps
CPU time 0.83 seconds
Started Jun 21 05:01:01 PM PDT 24
Finished Jun 21 05:01:04 PM PDT 24
Peak memory 206004 kb
Host smart-fe6657f1-6abe-4df5-8959-889c10089db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19803
22184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1980322184
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1996163151
Short name T1644
Test name
Test status
Simulation time 66736237 ps
CPU time 0.68 seconds
Started Jun 21 05:01:05 PM PDT 24
Finished Jun 21 05:01:07 PM PDT 24
Peak memory 206036 kb
Host smart-7d67293e-18d3-4367-8f76-0e93eb57792b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19961
63151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1996163151
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2200437648
Short name T936
Test name
Test status
Simulation time 20499518620 ps
CPU time 44.84 seconds
Started Jun 21 05:00:54 PM PDT 24
Finished Jun 21 05:01:42 PM PDT 24
Peak memory 206324 kb
Host smart-caea1e7e-45fd-4fad-aa85-1c40d2b549f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22004
37648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2200437648
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.513579077
Short name T2142
Test name
Test status
Simulation time 225316134 ps
CPU time 0.82 seconds
Started Jun 21 05:02:45 PM PDT 24
Finished Jun 21 05:02:50 PM PDT 24
Peak memory 205720 kb
Host smart-4b01b965-2143-4130-864c-9939836e1069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51357
9077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.513579077
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.800092294
Short name T1550
Test name
Test status
Simulation time 176066294 ps
CPU time 0.9 seconds
Started Jun 21 05:00:53 PM PDT 24
Finished Jun 21 05:00:58 PM PDT 24
Peak memory 205960 kb
Host smart-f29470aa-5d71-4193-b1fb-d6b8598b5b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80009
2294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.800092294
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2685585713
Short name T301
Test name
Test status
Simulation time 210067921 ps
CPU time 0.87 seconds
Started Jun 21 05:01:03 PM PDT 24
Finished Jun 21 05:01:06 PM PDT 24
Peak memory 206028 kb
Host smart-451a24e0-603e-45e3-8a8e-e1b63534d3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26855
85713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2685585713
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.1111248793
Short name T758
Test name
Test status
Simulation time 150113878 ps
CPU time 0.76 seconds
Started Jun 21 05:00:57 PM PDT 24
Finished Jun 21 05:01:01 PM PDT 24
Peak memory 206048 kb
Host smart-15c1c6cb-9b73-4ca9-a706-5aa3b9b8169c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11112
48793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.1111248793
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1124823507
Short name T989
Test name
Test status
Simulation time 193862140 ps
CPU time 0.82 seconds
Started Jun 21 05:00:55 PM PDT 24
Finished Jun 21 05:00:58 PM PDT 24
Peak memory 205964 kb
Host smart-be1103e4-5a09-41b2-a29b-aa7f0431a34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11248
23507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1124823507
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.443526721
Short name T1469
Test name
Test status
Simulation time 150512595 ps
CPU time 0.77 seconds
Started Jun 21 05:01:03 PM PDT 24
Finished Jun 21 05:01:05 PM PDT 24
Peak memory 205956 kb
Host smart-ebdf2a11-4394-4093-9137-f4850fb8d5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44352
6721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.443526721
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1705495927
Short name T2326
Test name
Test status
Simulation time 159566965 ps
CPU time 0.8 seconds
Started Jun 21 05:01:06 PM PDT 24
Finished Jun 21 05:01:09 PM PDT 24
Peak memory 205644 kb
Host smart-7ede91c2-0481-48f5-8f8c-3b31a33e3d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17054
95927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1705495927
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2574439771
Short name T822
Test name
Test status
Simulation time 266207591 ps
CPU time 0.94 seconds
Started Jun 21 05:00:54 PM PDT 24
Finished Jun 21 05:00:58 PM PDT 24
Peak memory 206028 kb
Host smart-f02d9c17-a18b-4173-8e06-4abf2cd22fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25744
39771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2574439771
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.2455192589
Short name T1380
Test name
Test status
Simulation time 9478850571 ps
CPU time 87.18 seconds
Started Jun 21 05:01:07 PM PDT 24
Finished Jun 21 05:02:36 PM PDT 24
Peak memory 206228 kb
Host smart-1b4c2001-5d70-4f60-8370-7f915b259078
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2455192589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.2455192589
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1671615754
Short name T535
Test name
Test status
Simulation time 198536280 ps
CPU time 0.81 seconds
Started Jun 21 05:00:55 PM PDT 24
Finished Jun 21 05:00:59 PM PDT 24
Peak memory 206024 kb
Host smart-0998cbab-6776-4a6f-9667-048947300b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16716
15754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1671615754
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.2428849817
Short name T1848
Test name
Test status
Simulation time 183486473 ps
CPU time 0.85 seconds
Started Jun 21 05:00:53 PM PDT 24
Finished Jun 21 05:00:58 PM PDT 24
Peak memory 206020 kb
Host smart-501fb382-4f04-460f-b796-f09574fae3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24288
49817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.2428849817
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.2498102582
Short name T875
Test name
Test status
Simulation time 11940533452 ps
CPU time 88.02 seconds
Started Jun 21 05:00:56 PM PDT 24
Finished Jun 21 05:02:27 PM PDT 24
Peak memory 206336 kb
Host smart-6c441234-9f15-4378-921b-94fab7db4edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24981
02582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.2498102582
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.375626850
Short name T432
Test name
Test status
Simulation time 4403210172 ps
CPU time 4.88 seconds
Started Jun 21 05:01:01 PM PDT 24
Finished Jun 21 05:01:08 PM PDT 24
Peak memory 206320 kb
Host smart-eda92746-e6c6-450b-8a82-95f61a5699f0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=375626850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.375626850
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.2841281195
Short name T515
Test name
Test status
Simulation time 13362182963 ps
CPU time 12.4 seconds
Started Jun 21 05:01:00 PM PDT 24
Finished Jun 21 05:01:15 PM PDT 24
Peak memory 206092 kb
Host smart-5498f94b-402b-4547-bc04-9a177118ed2b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2841281195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2841281195
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1179704018
Short name T824
Test name
Test status
Simulation time 23326504902 ps
CPU time 22.96 seconds
Started Jun 21 05:01:09 PM PDT 24
Finished Jun 21 05:01:33 PM PDT 24
Peak memory 206044 kb
Host smart-bdc7a5f6-d0f0-455a-bc25-f1266088716f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1179704018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.1179704018
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3276158513
Short name T1982
Test name
Test status
Simulation time 197331900 ps
CPU time 0.91 seconds
Started Jun 21 05:01:04 PM PDT 24
Finished Jun 21 05:01:07 PM PDT 24
Peak memory 206004 kb
Host smart-ef7923e3-e67e-4113-b4e4-eecc9e97355c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32761
58513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3276158513
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2270431989
Short name T812
Test name
Test status
Simulation time 219546972 ps
CPU time 0.85 seconds
Started Jun 21 05:01:06 PM PDT 24
Finished Jun 21 05:01:09 PM PDT 24
Peak memory 206020 kb
Host smart-7d368d28-81a2-448e-ae3b-2ed01a62a10d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22704
31989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2270431989
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.2315289800
Short name T158
Test name
Test status
Simulation time 460469506 ps
CPU time 1.42 seconds
Started Jun 21 05:01:03 PM PDT 24
Finished Jun 21 05:01:07 PM PDT 24
Peak memory 206020 kb
Host smart-c1cccdf3-cfe1-4b17-8c68-3d65639de0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23152
89800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.2315289800
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.2185306936
Short name T109
Test name
Test status
Simulation time 484343824 ps
CPU time 1.37 seconds
Started Jun 21 05:01:07 PM PDT 24
Finished Jun 21 05:01:10 PM PDT 24
Peak memory 206028 kb
Host smart-a458ee88-98dd-4a45-8441-5dbc8080ead5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21853
06936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.2185306936
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.2948766405
Short name T933
Test name
Test status
Simulation time 11566687071 ps
CPU time 20.58 seconds
Started Jun 21 05:01:02 PM PDT 24
Finished Jun 21 05:01:24 PM PDT 24
Peak memory 206332 kb
Host smart-c04f2b07-618c-4b97-b80d-b25920ce3867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29487
66405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.2948766405
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.879868591
Short name T214
Test name
Test status
Simulation time 348852082 ps
CPU time 1.23 seconds
Started Jun 21 05:01:09 PM PDT 24
Finished Jun 21 05:01:13 PM PDT 24
Peak memory 205968 kb
Host smart-b68a39b0-34f0-46c8-8645-d662a8c9366c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87986
8591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.879868591
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1729199025
Short name T1134
Test name
Test status
Simulation time 204978884 ps
CPU time 0.85 seconds
Started Jun 21 05:01:06 PM PDT 24
Finished Jun 21 05:01:08 PM PDT 24
Peak memory 205916 kb
Host smart-9f7f3f48-a54d-4c14-9b5a-b0e1680d8944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17291
99025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1729199025
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.1372491767
Short name T1654
Test name
Test status
Simulation time 64425637 ps
CPU time 0.68 seconds
Started Jun 21 05:01:01 PM PDT 24
Finished Jun 21 05:01:04 PM PDT 24
Peak memory 206016 kb
Host smart-3f3cee6b-39c9-4bd6-8525-b81eddea0197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13724
91767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.1372491767
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.2868492129
Short name T372
Test name
Test status
Simulation time 956427996 ps
CPU time 2.33 seconds
Started Jun 21 05:01:03 PM PDT 24
Finished Jun 21 05:01:07 PM PDT 24
Peak memory 206096 kb
Host smart-83869cda-430e-4e51-8b2e-8e6b9b799e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28684
92129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.2868492129
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1157346852
Short name T1249
Test name
Test status
Simulation time 263700170 ps
CPU time 1.53 seconds
Started Jun 21 05:01:01 PM PDT 24
Finished Jun 21 05:01:04 PM PDT 24
Peak memory 206204 kb
Host smart-f2e284ab-716a-456d-ba0d-b30319b2d46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11573
46852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1157346852
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1008720884
Short name T530
Test name
Test status
Simulation time 164020684 ps
CPU time 0.84 seconds
Started Jun 21 05:01:13 PM PDT 24
Finished Jun 21 05:01:16 PM PDT 24
Peak memory 206024 kb
Host smart-cc759437-abb5-46bf-8252-1e21ad0c6a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087
20884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1008720884
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2422608474
Short name T2302
Test name
Test status
Simulation time 170766358 ps
CPU time 0.8 seconds
Started Jun 21 05:01:11 PM PDT 24
Finished Jun 21 05:01:13 PM PDT 24
Peak memory 205984 kb
Host smart-e4bae014-8492-4a34-b8a7-96ff43361b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24226
08474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2422608474
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.96618217
Short name T899
Test name
Test status
Simulation time 238571883 ps
CPU time 0.98 seconds
Started Jun 21 05:01:04 PM PDT 24
Finished Jun 21 05:01:07 PM PDT 24
Peak memory 206008 kb
Host smart-a81867ec-0b1c-4615-af70-1682506dba25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96618
217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.96618217
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1561511099
Short name T2135
Test name
Test status
Simulation time 268792829 ps
CPU time 1.04 seconds
Started Jun 21 05:01:04 PM PDT 24
Finished Jun 21 05:01:07 PM PDT 24
Peak memory 206020 kb
Host smart-350f1d21-3849-4e51-b2fa-3deaa5af6fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15615
11099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1561511099
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.2054695944
Short name T2265
Test name
Test status
Simulation time 23285101912 ps
CPU time 23.9 seconds
Started Jun 21 05:01:03 PM PDT 24
Finished Jun 21 05:01:29 PM PDT 24
Peak memory 206080 kb
Host smart-ebe866a3-dc9b-402b-99b2-cc820849c3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20546
95944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.2054695944
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.782153093
Short name T635
Test name
Test status
Simulation time 3327945110 ps
CPU time 3.68 seconds
Started Jun 21 05:00:59 PM PDT 24
Finished Jun 21 05:01:06 PM PDT 24
Peak memory 205996 kb
Host smart-46b9dbfb-7acd-4688-ab4f-e5ca52080749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78215
3093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.782153093
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.3923275249
Short name T2032
Test name
Test status
Simulation time 6152110304 ps
CPU time 165.83 seconds
Started Jun 21 05:01:05 PM PDT 24
Finished Jun 21 05:03:52 PM PDT 24
Peak memory 206272 kb
Host smart-01a6eb22-1d88-47a7-acd3-2905edab4415
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3923275249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.3923275249
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.3096387827
Short name T1512
Test name
Test status
Simulation time 235535734 ps
CPU time 0.87 seconds
Started Jun 21 05:01:13 PM PDT 24
Finished Jun 21 05:01:15 PM PDT 24
Peak memory 206048 kb
Host smart-c1da4b6b-29e3-4c45-8521-f03ea02edde9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3096387827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.3096387827
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1042747175
Short name T2246
Test name
Test status
Simulation time 191872905 ps
CPU time 0.85 seconds
Started Jun 21 05:01:01 PM PDT 24
Finished Jun 21 05:01:04 PM PDT 24
Peak memory 206016 kb
Host smart-510733bd-9da1-48e7-9143-6da5eb3b10f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10427
47175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1042747175
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1274701827
Short name T2038
Test name
Test status
Simulation time 10237182333 ps
CPU time 289.08 seconds
Started Jun 21 05:01:03 PM PDT 24
Finished Jun 21 05:05:54 PM PDT 24
Peak memory 206156 kb
Host smart-f9e7ddd7-0eca-471d-bad1-4fb2b5025dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12747
01827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1274701827
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.1920000059
Short name T2191
Test name
Test status
Simulation time 6060782626 ps
CPU time 57.58 seconds
Started Jun 21 05:01:04 PM PDT 24
Finished Jun 21 05:02:04 PM PDT 24
Peak memory 206252 kb
Host smart-222a1022-ff82-435c-8335-df25134436a0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1920000059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.1920000059
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.3278909245
Short name T1989
Test name
Test status
Simulation time 213752280 ps
CPU time 0.83 seconds
Started Jun 21 05:01:11 PM PDT 24
Finished Jun 21 05:01:13 PM PDT 24
Peak memory 206048 kb
Host smart-64a88fbd-0567-422d-8d34-9f1ddb758089
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3278909245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.3278909245
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3056614968
Short name T1714
Test name
Test status
Simulation time 153365727 ps
CPU time 0.76 seconds
Started Jun 21 05:01:07 PM PDT 24
Finished Jun 21 05:01:10 PM PDT 24
Peak memory 205952 kb
Host smart-9891c8b0-67f4-43ee-93c2-6b705d6011ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30566
14968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3056614968
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1820580512
Short name T118
Test name
Test status
Simulation time 188409041 ps
CPU time 0.83 seconds
Started Jun 21 05:01:03 PM PDT 24
Finished Jun 21 05:01:06 PM PDT 24
Peak memory 205964 kb
Host smart-ac03c248-1c74-445e-b2c0-8eaf38c48dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18205
80512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1820580512
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.3148491611
Short name T1689
Test name
Test status
Simulation time 151175373 ps
CPU time 0.81 seconds
Started Jun 21 05:01:02 PM PDT 24
Finished Jun 21 05:01:04 PM PDT 24
Peak memory 205928 kb
Host smart-1f9f54c1-9803-4d2f-95e5-de00209bdeb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31484
91611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.3148491611
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3056871816
Short name T1096
Test name
Test status
Simulation time 150481116 ps
CPU time 0.77 seconds
Started Jun 21 05:01:08 PM PDT 24
Finished Jun 21 05:01:11 PM PDT 24
Peak memory 205964 kb
Host smart-901322c8-3c0b-4157-bd0e-089682c01f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30568
71816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3056871816
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1617702143
Short name T1182
Test name
Test status
Simulation time 188608217 ps
CPU time 0.82 seconds
Started Jun 21 05:01:09 PM PDT 24
Finished Jun 21 05:01:11 PM PDT 24
Peak memory 205964 kb
Host smart-65b16b58-4af2-47f2-bd90-93ff2340152a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16177
02143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1617702143
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3143320689
Short name T1998
Test name
Test status
Simulation time 153502138 ps
CPU time 0.77 seconds
Started Jun 21 05:01:08 PM PDT 24
Finished Jun 21 05:01:11 PM PDT 24
Peak memory 205960 kb
Host smart-cb046413-b236-4b91-b208-23a07279bfb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31433
20689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3143320689
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.899412105
Short name T1454
Test name
Test status
Simulation time 243359260 ps
CPU time 0.92 seconds
Started Jun 21 05:01:06 PM PDT 24
Finished Jun 21 05:01:09 PM PDT 24
Peak memory 205992 kb
Host smart-f949203d-40f3-494c-b23b-5e9b0fc168a9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=899412105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.899412105
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.16018083
Short name T462
Test name
Test status
Simulation time 164632276 ps
CPU time 0.82 seconds
Started Jun 21 05:01:12 PM PDT 24
Finished Jun 21 05:01:14 PM PDT 24
Peak memory 205996 kb
Host smart-d5e844bd-9a68-4661-841b-78b2ea3573c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16018
083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.16018083
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3554717398
Short name T1905
Test name
Test status
Simulation time 35859706 ps
CPU time 0.64 seconds
Started Jun 21 05:01:09 PM PDT 24
Finished Jun 21 05:01:11 PM PDT 24
Peak memory 205988 kb
Host smart-8243b183-03f8-4553-ab74-8980be9d14f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35547
17398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3554717398
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2413929971
Short name T2204
Test name
Test status
Simulation time 18206262178 ps
CPU time 40.2 seconds
Started Jun 21 05:01:04 PM PDT 24
Finished Jun 21 05:01:46 PM PDT 24
Peak memory 206328 kb
Host smart-ee8b107a-e2ea-42e6-a891-bb0131124ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24139
29971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2413929971
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.71472270
Short name T987
Test name
Test status
Simulation time 157319024 ps
CPU time 0.76 seconds
Started Jun 21 05:01:08 PM PDT 24
Finished Jun 21 05:01:11 PM PDT 24
Peak memory 205972 kb
Host smart-9d56219d-ea36-429c-bcb4-d3fd1dd3daad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71472
270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.71472270
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2743089971
Short name T1661
Test name
Test status
Simulation time 173310271 ps
CPU time 0.79 seconds
Started Jun 21 05:01:03 PM PDT 24
Finished Jun 21 05:01:06 PM PDT 24
Peak memory 206028 kb
Host smart-fd5444eb-9f2e-4cd9-86e7-edfbd4b99e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27430
89971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2743089971
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3306776853
Short name T2419
Test name
Test status
Simulation time 217843399 ps
CPU time 0.9 seconds
Started Jun 21 05:01:11 PM PDT 24
Finished Jun 21 05:01:13 PM PDT 24
Peak memory 206036 kb
Host smart-d966dc5b-e518-49ce-ae99-8522eadbc49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33067
76853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3306776853
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.2124341250
Short name T1188
Test name
Test status
Simulation time 176741726 ps
CPU time 0.88 seconds
Started Jun 21 05:01:06 PM PDT 24
Finished Jun 21 05:01:08 PM PDT 24
Peak memory 205944 kb
Host smart-971f2aae-c1e3-445b-b926-6e1cbbf891f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21243
41250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.2124341250
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.1309386916
Short name T829
Test name
Test status
Simulation time 179852015 ps
CPU time 0.84 seconds
Started Jun 21 05:01:08 PM PDT 24
Finished Jun 21 05:01:11 PM PDT 24
Peak memory 205960 kb
Host smart-485d25dd-e0fd-489c-89bf-28917ad4ef5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13093
86916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.1309386916
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2422525929
Short name T840
Test name
Test status
Simulation time 153686277 ps
CPU time 0.79 seconds
Started Jun 21 05:01:03 PM PDT 24
Finished Jun 21 05:01:06 PM PDT 24
Peak memory 205956 kb
Host smart-5a95fde6-77d6-40ec-a938-9feb6442e86f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24225
25929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2422525929
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2249743438
Short name T1822
Test name
Test status
Simulation time 207214164 ps
CPU time 0.89 seconds
Started Jun 21 05:01:04 PM PDT 24
Finished Jun 21 05:01:07 PM PDT 24
Peak memory 205960 kb
Host smart-8148e584-7d60-4343-acab-0443b5085123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22497
43438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2249743438
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.2093642157
Short name T2284
Test name
Test status
Simulation time 200313429 ps
CPU time 0.9 seconds
Started Jun 21 05:01:06 PM PDT 24
Finished Jun 21 05:01:09 PM PDT 24
Peak memory 206008 kb
Host smart-5a7d1166-b815-4155-9529-20d9a6617457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20936
42157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2093642157
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.2718594454
Short name T1916
Test name
Test status
Simulation time 8709971448 ps
CPU time 253.04 seconds
Started Jun 21 05:01:05 PM PDT 24
Finished Jun 21 05:05:20 PM PDT 24
Peak memory 206260 kb
Host smart-0063b74c-12d3-45e3-829f-622402d89ba3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2718594454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.2718594454
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.3535975005
Short name T1264
Test name
Test status
Simulation time 173164146 ps
CPU time 0.79 seconds
Started Jun 21 05:01:08 PM PDT 24
Finished Jun 21 05:01:11 PM PDT 24
Peak memory 205972 kb
Host smart-20cf7ef9-843f-4a4e-bb5d-87372244df9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35359
75005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.3535975005
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.264234291
Short name T1421
Test name
Test status
Simulation time 148806567 ps
CPU time 0.78 seconds
Started Jun 21 05:01:08 PM PDT 24
Finished Jun 21 05:01:11 PM PDT 24
Peak memory 205944 kb
Host smart-14e7bc4b-d6f6-4848-9d8b-3f2ac5920b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26423
4291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.264234291
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.3300432434
Short name T1462
Test name
Test status
Simulation time 10193000910 ps
CPU time 75.54 seconds
Started Jun 21 05:01:03 PM PDT 24
Finished Jun 21 05:02:21 PM PDT 24
Peak memory 206340 kb
Host smart-6d73a5d0-bd05-4d52-8654-018e36c7f4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33004
32434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.3300432434
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.628798165
Short name T1991
Test name
Test status
Simulation time 13403430247 ps
CPU time 12.4 seconds
Started Jun 21 04:54:31 PM PDT 24
Finished Jun 21 04:54:48 PM PDT 24
Peak memory 206024 kb
Host smart-611fbe12-7dac-405e-800f-20414768abe8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=628798165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.628798165
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.1192830754
Short name T1640
Test name
Test status
Simulation time 23338822930 ps
CPU time 23.77 seconds
Started Jun 21 04:54:31 PM PDT 24
Finished Jun 21 04:54:59 PM PDT 24
Peak memory 205992 kb
Host smart-770e32f5-e44e-46b3-9644-902e0bf1b114
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1192830754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.1192830754
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1127722754
Short name T317
Test name
Test status
Simulation time 169124586 ps
CPU time 0.86 seconds
Started Jun 21 04:54:32 PM PDT 24
Finished Jun 21 04:54:37 PM PDT 24
Peak memory 206144 kb
Host smart-59cfe030-17b1-460d-9ad5-e8ee4a613a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11277
22754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1127722754
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3371914983
Short name T1875
Test name
Test status
Simulation time 141140650 ps
CPU time 0.75 seconds
Started Jun 21 04:54:31 PM PDT 24
Finished Jun 21 04:54:37 PM PDT 24
Peak memory 206028 kb
Host smart-14463afd-4237-45a1-9fb8-bdf7a38ba413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33719
14983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3371914983
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.4087604219
Short name T647
Test name
Test status
Simulation time 333848010 ps
CPU time 1.17 seconds
Started Jun 21 04:54:31 PM PDT 24
Finished Jun 21 04:54:37 PM PDT 24
Peak memory 206144 kb
Host smart-d2ca6d19-e655-4af2-838f-349da2defdaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40876
04219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.4087604219
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_device_address.3781194429
Short name T104
Test name
Test status
Simulation time 22299746054 ps
CPU time 40.5 seconds
Started Jun 21 04:54:30 PM PDT 24
Finished Jun 21 04:55:14 PM PDT 24
Peak memory 206312 kb
Host smart-68e9a345-3670-413a-ad33-5270086eb47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37811
94429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.3781194429
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.345262559
Short name T2251
Test name
Test status
Simulation time 389985622 ps
CPU time 1.39 seconds
Started Jun 21 04:54:30 PM PDT 24
Finished Jun 21 04:54:36 PM PDT 24
Peak memory 206028 kb
Host smart-9a39eb60-11d0-4997-ac98-5d7924f2a28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34526
2559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.345262559
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.2525557729
Short name T1934
Test name
Test status
Simulation time 160475856 ps
CPU time 0.8 seconds
Started Jun 21 04:54:34 PM PDT 24
Finished Jun 21 04:54:38 PM PDT 24
Peak memory 206020 kb
Host smart-3b7d6c09-2494-4fc4-bc07-f80ad24e492d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25255
57729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.2525557729
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.772647395
Short name T2209
Test name
Test status
Simulation time 38019165 ps
CPU time 0.64 seconds
Started Jun 21 04:54:32 PM PDT 24
Finished Jun 21 04:54:37 PM PDT 24
Peak memory 205964 kb
Host smart-993aaa7b-35f8-4445-8fbe-f49c152c36fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77264
7395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.772647395
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.1222231130
Short name T1408
Test name
Test status
Simulation time 907976907 ps
CPU time 2.05 seconds
Started Jun 21 04:54:34 PM PDT 24
Finished Jun 21 04:54:40 PM PDT 24
Peak memory 206280 kb
Host smart-bb596d22-8493-4673-ab17-43f55f6fb1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12222
31130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1222231130
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.4173241372
Short name T217
Test name
Test status
Simulation time 368299028 ps
CPU time 2.29 seconds
Started Jun 21 04:54:33 PM PDT 24
Finished Jun 21 04:54:39 PM PDT 24
Peak memory 206252 kb
Host smart-2791f01e-2b7d-40aa-ab89-54e6c61f54be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41732
41372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.4173241372
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2505254982
Short name T637
Test name
Test status
Simulation time 210147415 ps
CPU time 0.83 seconds
Started Jun 21 04:54:45 PM PDT 24
Finished Jun 21 04:54:48 PM PDT 24
Peak memory 205912 kb
Host smart-1cfb6a5a-06b2-4439-a3b1-fec68631721e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25052
54982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2505254982
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2421160843
Short name T2161
Test name
Test status
Simulation time 164099459 ps
CPU time 0.74 seconds
Started Jun 21 04:54:44 PM PDT 24
Finished Jun 21 04:54:46 PM PDT 24
Peak memory 205968 kb
Host smart-5ece9907-d746-4fb2-be81-c17f151cc13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24211
60843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2421160843
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2402706024
Short name T1658
Test name
Test status
Simulation time 212907129 ps
CPU time 0.91 seconds
Started Jun 21 04:54:43 PM PDT 24
Finished Jun 21 04:54:46 PM PDT 24
Peak memory 205956 kb
Host smart-a3089f3f-199c-4353-8935-80211dbb8c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24027
06024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2402706024
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.2901614825
Short name T54
Test name
Test status
Simulation time 283199361 ps
CPU time 0.93 seconds
Started Jun 21 04:54:44 PM PDT 24
Finished Jun 21 04:54:47 PM PDT 24
Peak memory 206020 kb
Host smart-e354c500-eaa4-4c75-8885-ce75ad5f9645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29016
14825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.2901614825
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.1423055091
Short name T360
Test name
Test status
Simulation time 23305295824 ps
CPU time 29.22 seconds
Started Jun 21 04:54:42 PM PDT 24
Finished Jun 21 04:55:12 PM PDT 24
Peak memory 206084 kb
Host smart-cab8dd59-910f-48ae-a227-682045ac9e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14230
55091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.1423055091
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.4046510890
Short name T1812
Test name
Test status
Simulation time 3293340593 ps
CPU time 3.89 seconds
Started Jun 21 04:54:40 PM PDT 24
Finished Jun 21 04:54:45 PM PDT 24
Peak memory 206032 kb
Host smart-1d01c2a5-9e1c-4398-ab06-b83af86e3c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40465
10890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.4046510890
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.1749322581
Short name T1213
Test name
Test status
Simulation time 5545853408 ps
CPU time 54.13 seconds
Started Jun 21 04:54:45 PM PDT 24
Finished Jun 21 04:55:41 PM PDT 24
Peak memory 206220 kb
Host smart-77624a72-f548-4833-8f64-76b2c3525555
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1749322581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.1749322581
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.374608231
Short name T1792
Test name
Test status
Simulation time 268504214 ps
CPU time 0.92 seconds
Started Jun 21 04:54:48 PM PDT 24
Finished Jun 21 04:54:50 PM PDT 24
Peak memory 206048 kb
Host smart-61c0ebb8-f080-43a4-8925-705d05070aac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=374608231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.374608231
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3255720084
Short name T1267
Test name
Test status
Simulation time 202972934 ps
CPU time 0.9 seconds
Started Jun 21 04:54:44 PM PDT 24
Finished Jun 21 04:54:47 PM PDT 24
Peak memory 205952 kb
Host smart-9ef81b63-a26c-4723-93e3-6fb0166beb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32557
20084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3255720084
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1244615642
Short name T775
Test name
Test status
Simulation time 7737955909 ps
CPU time 207.69 seconds
Started Jun 21 04:54:43 PM PDT 24
Finished Jun 21 04:58:13 PM PDT 24
Peak memory 206192 kb
Host smart-e8195c34-c568-4c4d-b911-70aef77d13db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12446
15642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1244615642
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.2308484488
Short name T433
Test name
Test status
Simulation time 10785449336 ps
CPU time 105.45 seconds
Started Jun 21 04:54:44 PM PDT 24
Finished Jun 21 04:56:32 PM PDT 24
Peak memory 206220 kb
Host smart-81bd444d-5553-4706-a2e1-b4b22bfe4ef4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2308484488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.2308484488
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.239560508
Short name T2011
Test name
Test status
Simulation time 164779239 ps
CPU time 0.8 seconds
Started Jun 21 04:54:45 PM PDT 24
Finished Jun 21 04:54:48 PM PDT 24
Peak memory 206028 kb
Host smart-37a4d70d-ab73-4a9f-a9ea-6feeb75fdc04
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=239560508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.239560508
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1046453509
Short name T916
Test name
Test status
Simulation time 154164194 ps
CPU time 0.75 seconds
Started Jun 21 04:54:43 PM PDT 24
Finished Jun 21 04:54:46 PM PDT 24
Peak memory 206052 kb
Host smart-a86c0ebe-c55a-4431-ad57-61001bef8809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10464
53509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1046453509
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1700896152
Short name T135
Test name
Test status
Simulation time 228017405 ps
CPU time 0.86 seconds
Started Jun 21 04:54:43 PM PDT 24
Finished Jun 21 04:54:44 PM PDT 24
Peak memory 206028 kb
Host smart-437c1e7d-dac2-4cdd-9d13-9cc0e3b88442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17008
96152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1700896152
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.1198317724
Short name T2278
Test name
Test status
Simulation time 229564815 ps
CPU time 0.91 seconds
Started Jun 21 04:54:45 PM PDT 24
Finished Jun 21 04:54:48 PM PDT 24
Peak memory 205916 kb
Host smart-35d39376-dce9-459c-b734-ac8ad18d73ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11983
17724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.1198317724
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.26368477
Short name T1859
Test name
Test status
Simulation time 185785754 ps
CPU time 0.84 seconds
Started Jun 21 04:54:44 PM PDT 24
Finished Jun 21 04:54:46 PM PDT 24
Peak memory 206000 kb
Host smart-0f648a2c-cffa-496e-bdd4-5e4cc7ec8fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26368
477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.26368477
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1802746356
Short name T1931
Test name
Test status
Simulation time 159944845 ps
CPU time 0.84 seconds
Started Jun 21 04:54:43 PM PDT 24
Finished Jun 21 04:54:44 PM PDT 24
Peak memory 205928 kb
Host smart-28a3bd2e-75b4-4e6f-b58d-4ec668c15928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18027
46356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1802746356
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3890033389
Short name T1075
Test name
Test status
Simulation time 148030719 ps
CPU time 0.74 seconds
Started Jun 21 04:54:44 PM PDT 24
Finished Jun 21 04:54:47 PM PDT 24
Peak memory 206028 kb
Host smart-c494416a-4f29-4263-bee4-d7027a066916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38900
33389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3890033389
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.1193265007
Short name T1021
Test name
Test status
Simulation time 223978077 ps
CPU time 0.9 seconds
Started Jun 21 04:54:45 PM PDT 24
Finished Jun 21 04:54:48 PM PDT 24
Peak memory 205944 kb
Host smart-74979bb9-82bb-4426-ac6b-720613638565
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1193265007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.1193265007
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.1286979035
Short name T1065
Test name
Test status
Simulation time 154490392 ps
CPU time 0.76 seconds
Started Jun 21 04:54:45 PM PDT 24
Finished Jun 21 04:54:48 PM PDT 24
Peak memory 205944 kb
Host smart-08a304ba-7cdd-4b44-956a-ef4fe6b0503e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12869
79035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1286979035
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.246240022
Short name T1056
Test name
Test status
Simulation time 45989035 ps
CPU time 0.66 seconds
Started Jun 21 04:54:45 PM PDT 24
Finished Jun 21 04:54:48 PM PDT 24
Peak memory 206036 kb
Host smart-aa6aa6cc-d60a-4955-a6dc-6d600272f827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24624
0022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.246240022
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.918731516
Short name T245
Test name
Test status
Simulation time 12758173070 ps
CPU time 29.46 seconds
Started Jun 21 04:54:45 PM PDT 24
Finished Jun 21 04:55:16 PM PDT 24
Peak memory 206324 kb
Host smart-94ec173a-fe07-46b9-9a2f-d5e055ea9f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91873
1516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.918731516
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.1513914304
Short name T320
Test name
Test status
Simulation time 153488731 ps
CPU time 0.82 seconds
Started Jun 21 04:54:45 PM PDT 24
Finished Jun 21 04:54:48 PM PDT 24
Peak memory 205944 kb
Host smart-5b061d1a-63bf-467f-ad31-215e7172efde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15139
14304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.1513914304
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.4059185813
Short name T1656
Test name
Test status
Simulation time 208171127 ps
CPU time 0.91 seconds
Started Jun 21 04:54:46 PM PDT 24
Finished Jun 21 04:54:49 PM PDT 24
Peak memory 206008 kb
Host smart-f0a34a60-9941-4fd2-8c17-34089f97da87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40591
85813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.4059185813
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.1449183877
Short name T2476
Test name
Test status
Simulation time 22794505216 ps
CPU time 153.9 seconds
Started Jun 21 04:54:47 PM PDT 24
Finished Jun 21 04:57:23 PM PDT 24
Peak memory 206340 kb
Host smart-69bcd013-00eb-43b4-b382-123f42d78a4d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1449183877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1449183877
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.371815507
Short name T1016
Test name
Test status
Simulation time 24067637978 ps
CPU time 205.28 seconds
Started Jun 21 04:54:43 PM PDT 24
Finished Jun 21 04:58:10 PM PDT 24
Peak memory 206320 kb
Host smart-f428eee8-bafe-4b30-9b2a-63fcd6f0cd6e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=371815507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.371815507
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.1426765326
Short name T157
Test name
Test status
Simulation time 18785821953 ps
CPU time 144.63 seconds
Started Jun 21 04:54:42 PM PDT 24
Finished Jun 21 04:57:08 PM PDT 24
Peak memory 206264 kb
Host smart-12e2e6d5-ac2f-44e7-83a5-6cd466f09af0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1426765326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.1426765326
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.1310033330
Short name T940
Test name
Test status
Simulation time 170601741 ps
CPU time 0.79 seconds
Started Jun 21 04:54:46 PM PDT 24
Finished Jun 21 04:54:49 PM PDT 24
Peak memory 206008 kb
Host smart-09677a9c-8def-4607-a238-948c348b2f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13100
33330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.1310033330
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.3315791964
Short name T1413
Test name
Test status
Simulation time 141160806 ps
CPU time 0.77 seconds
Started Jun 21 04:54:45 PM PDT 24
Finished Jun 21 04:54:48 PM PDT 24
Peak memory 205952 kb
Host smart-223ee65d-9d72-4f77-a59a-09484ce2d4e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33157
91964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.3315791964
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2518854990
Short name T584
Test name
Test status
Simulation time 144597447 ps
CPU time 0.76 seconds
Started Jun 21 04:54:42 PM PDT 24
Finished Jun 21 04:54:44 PM PDT 24
Peak memory 206024 kb
Host smart-2f0fc7bf-8988-4318-88c7-73ec1943cb72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25188
54990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2518854990
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1447105553
Short name T1575
Test name
Test status
Simulation time 175091820 ps
CPU time 0.77 seconds
Started Jun 21 04:54:42 PM PDT 24
Finished Jun 21 04:54:43 PM PDT 24
Peak memory 206016 kb
Host smart-9c0ed7b3-3024-491b-afa8-a9494e3d1a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14471
05553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1447105553
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1638148569
Short name T2339
Test name
Test status
Simulation time 169500811 ps
CPU time 0.81 seconds
Started Jun 21 04:54:45 PM PDT 24
Finished Jun 21 04:54:48 PM PDT 24
Peak memory 205968 kb
Host smart-f1907e70-a1a4-4c02-ba2d-6e95c924b7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16381
48569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1638148569
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3798459361
Short name T1341
Test name
Test status
Simulation time 248916761 ps
CPU time 0.96 seconds
Started Jun 21 04:54:29 PM PDT 24
Finished Jun 21 04:54:34 PM PDT 24
Peak memory 206032 kb
Host smart-b898c426-bfc9-4a15-9f73-0551f0137e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37984
59361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3798459361
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.1628252270
Short name T573
Test name
Test status
Simulation time 3807158958 ps
CPU time 27.23 seconds
Started Jun 21 04:54:44 PM PDT 24
Finished Jun 21 04:55:13 PM PDT 24
Peak memory 206336 kb
Host smart-dc76adee-c16c-4079-8995-5438c325f448
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1628252270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.1628252270
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3901202140
Short name T2294
Test name
Test status
Simulation time 163374467 ps
CPU time 0.8 seconds
Started Jun 21 04:54:44 PM PDT 24
Finished Jun 21 04:54:47 PM PDT 24
Peak memory 206164 kb
Host smart-a053708b-badb-4ec5-b731-bf8f533fd3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39012
02140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3901202140
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3874002764
Short name T2187
Test name
Test status
Simulation time 151994140 ps
CPU time 0.79 seconds
Started Jun 21 04:54:44 PM PDT 24
Finished Jun 21 04:54:47 PM PDT 24
Peak memory 205920 kb
Host smart-9cd3f291-4113-46aa-838b-2459084c9e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38740
02764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3874002764
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.1795481518
Short name T821
Test name
Test status
Simulation time 10790760515 ps
CPU time 103.83 seconds
Started Jun 21 04:54:44 PM PDT 24
Finished Jun 21 04:56:30 PM PDT 24
Peak memory 206208 kb
Host smart-4a9b2888-c9ea-444a-b104-129230177658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17954
81518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.1795481518
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.1623789851
Short name T223
Test name
Test status
Simulation time 4194058292 ps
CPU time 5.21 seconds
Started Jun 21 04:54:42 PM PDT 24
Finished Jun 21 04:54:48 PM PDT 24
Peak memory 206284 kb
Host smart-aefde710-80c9-4272-9528-1f07887a7e05
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1623789851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.1623789851
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.2812163349
Short name T918
Test name
Test status
Simulation time 13308280286 ps
CPU time 11.95 seconds
Started Jun 21 04:54:42 PM PDT 24
Finished Jun 21 04:54:54 PM PDT 24
Peak memory 206248 kb
Host smart-da8e5c65-35cb-489e-9fa0-1f609d644ed6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2812163349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.2812163349
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.896393187
Short name T1741
Test name
Test status
Simulation time 23344390465 ps
CPU time 22.96 seconds
Started Jun 21 04:54:44 PM PDT 24
Finished Jun 21 04:55:10 PM PDT 24
Peak memory 206100 kb
Host smart-acab0055-ba6c-4bd9-a532-ace6cc7a8241
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=896393187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.896393187
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.4214929005
Short name T2159
Test name
Test status
Simulation time 183360196 ps
CPU time 0.88 seconds
Started Jun 21 04:54:46 PM PDT 24
Finished Jun 21 04:54:49 PM PDT 24
Peak memory 206004 kb
Host smart-48746aef-8f62-4ecf-be2d-a21c15ad2729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42149
29005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.4214929005
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.2539484885
Short name T1969
Test name
Test status
Simulation time 155634766 ps
CPU time 0.78 seconds
Started Jun 21 04:54:44 PM PDT 24
Finished Jun 21 04:54:47 PM PDT 24
Peak memory 205952 kb
Host smart-b1ba8c7d-91d0-43c7-8c14-85b3b2e51a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25394
84885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.2539484885
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.400774564
Short name T636
Test name
Test status
Simulation time 192043086 ps
CPU time 0.85 seconds
Started Jun 21 04:54:43 PM PDT 24
Finished Jun 21 04:54:45 PM PDT 24
Peak memory 206004 kb
Host smart-40080532-ce8b-4762-ab72-0c47d5443bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40077
4564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.400774564
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.2354572535
Short name T827
Test name
Test status
Simulation time 557618617 ps
CPU time 1.56 seconds
Started Jun 21 04:54:43 PM PDT 24
Finished Jun 21 04:54:46 PM PDT 24
Peak memory 206040 kb
Host smart-550bb70d-af94-4fb4-a3e0-e093dbb99ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23545
72535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2354572535
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.2337126749
Short name T2376
Test name
Test status
Simulation time 18125383973 ps
CPU time 33.63 seconds
Started Jun 21 04:54:52 PM PDT 24
Finished Jun 21 04:55:27 PM PDT 24
Peak memory 206288 kb
Host smart-ef7f7b2b-8174-4c00-b00d-6a78a90e4563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23371
26749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.2337126749
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.3837023341
Short name T1078
Test name
Test status
Simulation time 487265732 ps
CPU time 1.43 seconds
Started Jun 21 04:55:03 PM PDT 24
Finished Jun 21 04:55:05 PM PDT 24
Peak memory 205936 kb
Host smart-d30a9cbf-4cc6-41b2-b604-6234e9de03cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38370
23341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.3837023341
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.3614428062
Short name T2392
Test name
Test status
Simulation time 184853241 ps
CPU time 0.79 seconds
Started Jun 21 04:54:51 PM PDT 24
Finished Jun 21 04:54:53 PM PDT 24
Peak memory 205960 kb
Host smart-718f1155-6e30-42dd-a44e-d1a79a3867fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36144
28062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3614428062
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.1122029787
Short name T511
Test name
Test status
Simulation time 34559877 ps
CPU time 0.67 seconds
Started Jun 21 04:54:57 PM PDT 24
Finished Jun 21 04:54:59 PM PDT 24
Peak memory 205960 kb
Host smart-a3584ca0-b83c-45d8-8f69-2e6dab496862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11220
29787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1122029787
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1130611092
Short name T792
Test name
Test status
Simulation time 1083511260 ps
CPU time 2.34 seconds
Started Jun 21 04:54:52 PM PDT 24
Finished Jun 21 04:54:56 PM PDT 24
Peak memory 206180 kb
Host smart-29e3bd37-4f6d-4c4a-a7d9-7b5e5def4096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11306
11092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1130611092
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1551269863
Short name T893
Test name
Test status
Simulation time 290980905 ps
CPU time 1.8 seconds
Started Jun 21 04:54:52 PM PDT 24
Finished Jun 21 04:54:56 PM PDT 24
Peak memory 206232 kb
Host smart-44395f70-96ed-429b-b020-6493a84ea4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15512
69863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1551269863
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.898451929
Short name T1003
Test name
Test status
Simulation time 232181534 ps
CPU time 0.89 seconds
Started Jun 21 04:54:52 PM PDT 24
Finished Jun 21 04:54:55 PM PDT 24
Peak memory 205964 kb
Host smart-ad748fd9-6420-446a-9297-b826563a31d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89845
1929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.898451929
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3600858320
Short name T859
Test name
Test status
Simulation time 139220099 ps
CPU time 0.75 seconds
Started Jun 21 04:54:53 PM PDT 24
Finished Jun 21 04:54:56 PM PDT 24
Peak memory 205964 kb
Host smart-1b83c82b-e50b-485c-ab1d-c8e1230b78b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36008
58320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3600858320
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3050794384
Short name T1203
Test name
Test status
Simulation time 186821716 ps
CPU time 0.86 seconds
Started Jun 21 04:55:03 PM PDT 24
Finished Jun 21 04:55:05 PM PDT 24
Peak memory 205900 kb
Host smart-9cb9f608-1a98-4cf9-ba19-10f93261a1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30507
94384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3050794384
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.3009021120
Short name T720
Test name
Test status
Simulation time 189946064 ps
CPU time 0.81 seconds
Started Jun 21 04:54:51 PM PDT 24
Finished Jun 21 04:54:53 PM PDT 24
Peak memory 206020 kb
Host smart-3190f83f-1dfa-46d2-8f9d-5ced4160f47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30090
21120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.3009021120
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.208106513
Short name T1450
Test name
Test status
Simulation time 23359815222 ps
CPU time 24.32 seconds
Started Jun 21 04:55:03 PM PDT 24
Finished Jun 21 04:55:28 PM PDT 24
Peak memory 205872 kb
Host smart-b4ed45d9-d3e2-400a-8ec1-8fab58cb44f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20810
6513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.208106513
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.238612808
Short name T1699
Test name
Test status
Simulation time 3321131201 ps
CPU time 4.48 seconds
Started Jun 21 04:54:51 PM PDT 24
Finished Jun 21 04:54:56 PM PDT 24
Peak memory 206068 kb
Host smart-f3abbe4c-9a57-4ba1-8e08-f4d24dc9ff9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23861
2808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.238612808
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.3096653461
Short name T1831
Test name
Test status
Simulation time 8957486325 ps
CPU time 63.32 seconds
Started Jun 21 04:54:52 PM PDT 24
Finished Jun 21 04:55:58 PM PDT 24
Peak memory 206232 kb
Host smart-dd80015d-93ec-4d1c-bd66-cafd691cbee0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3096653461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.3096653461
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2724956215
Short name T582
Test name
Test status
Simulation time 261625879 ps
CPU time 0.97 seconds
Started Jun 21 04:54:52 PM PDT 24
Finished Jun 21 04:54:56 PM PDT 24
Peak memory 205996 kb
Host smart-b605f1c9-9be6-4cb7-9e12-c1aea59c2565
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2724956215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2724956215
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2676896481
Short name T1011
Test name
Test status
Simulation time 198812460 ps
CPU time 0.88 seconds
Started Jun 21 04:54:52 PM PDT 24
Finished Jun 21 04:54:56 PM PDT 24
Peak memory 206076 kb
Host smart-f6c6998c-45ed-4dab-aaff-39f5d4bee3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26768
96481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2676896481
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.3458529840
Short name T549
Test name
Test status
Simulation time 4239456735 ps
CPU time 28.21 seconds
Started Jun 21 04:54:54 PM PDT 24
Finished Jun 21 04:55:24 PM PDT 24
Peak memory 206268 kb
Host smart-1a4498da-cfab-4089-8e92-516479c2a946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34585
29840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.3458529840
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.1261508853
Short name T2117
Test name
Test status
Simulation time 6088252265 ps
CPU time 58.87 seconds
Started Jun 21 04:54:52 PM PDT 24
Finished Jun 21 04:55:52 PM PDT 24
Peak memory 206272 kb
Host smart-368e8967-210d-4333-b26e-70b21cd8ccd5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1261508853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.1261508853
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.4047325559
Short name T1715
Test name
Test status
Simulation time 164966685 ps
CPU time 0.81 seconds
Started Jun 21 04:54:52 PM PDT 24
Finished Jun 21 04:54:55 PM PDT 24
Peak memory 205976 kb
Host smart-b8d08fef-39a4-45e0-8c9c-b4e4aaccfe55
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4047325559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.4047325559
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1487902583
Short name T2380
Test name
Test status
Simulation time 166831458 ps
CPU time 0.77 seconds
Started Jun 21 04:54:52 PM PDT 24
Finished Jun 21 04:54:55 PM PDT 24
Peak memory 205992 kb
Host smart-549d065c-653c-49e6-9f91-6029bef047a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14879
02583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1487902583
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2978676165
Short name T148
Test name
Test status
Simulation time 174714871 ps
CPU time 0.81 seconds
Started Jun 21 04:54:53 PM PDT 24
Finished Jun 21 04:54:56 PM PDT 24
Peak memory 205964 kb
Host smart-12229a9c-1cbb-4603-a135-92fb10866721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29786
76165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2978676165
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.3249189135
Short name T1894
Test name
Test status
Simulation time 203653350 ps
CPU time 0.83 seconds
Started Jun 21 04:55:02 PM PDT 24
Finished Jun 21 04:55:05 PM PDT 24
Peak memory 205956 kb
Host smart-de7d7366-e6b6-4eb5-90e7-5d2ffcfc5a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32491
89135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3249189135
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1662937539
Short name T804
Test name
Test status
Simulation time 142801894 ps
CPU time 0.79 seconds
Started Jun 21 04:54:51 PM PDT 24
Finished Jun 21 04:54:54 PM PDT 24
Peak memory 205976 kb
Host smart-4142df94-6dee-4165-b106-2a4d9119a0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16629
37539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1662937539
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3106707504
Short name T2403
Test name
Test status
Simulation time 196819736 ps
CPU time 0.79 seconds
Started Jun 21 04:54:58 PM PDT 24
Finished Jun 21 04:55:01 PM PDT 24
Peak memory 205956 kb
Host smart-071cb842-0909-423f-92a1-4b9cc9b1fc04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31067
07504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3106707504
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.4131484893
Short name T950
Test name
Test status
Simulation time 152475217 ps
CPU time 0.75 seconds
Started Jun 21 04:54:55 PM PDT 24
Finished Jun 21 04:54:57 PM PDT 24
Peak memory 205972 kb
Host smart-e563fa47-c7c3-4604-a544-fec4c5ca1898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41314
84893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.4131484893
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.3447531917
Short name T1924
Test name
Test status
Simulation time 250821803 ps
CPU time 0.93 seconds
Started Jun 21 04:54:58 PM PDT 24
Finished Jun 21 04:55:01 PM PDT 24
Peak memory 206048 kb
Host smart-2ce85a94-db28-4e50-abf3-33595da5d677
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3447531917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.3447531917
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2755272031
Short name T1389
Test name
Test status
Simulation time 140059954 ps
CPU time 0.75 seconds
Started Jun 21 04:54:53 PM PDT 24
Finished Jun 21 04:54:57 PM PDT 24
Peak memory 205944 kb
Host smart-f5ad913e-8b9c-46a1-8b31-3b8989bc07bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27552
72031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2755272031
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2988338142
Short name T1112
Test name
Test status
Simulation time 49998958 ps
CPU time 0.68 seconds
Started Jun 21 04:54:52 PM PDT 24
Finished Jun 21 04:54:55 PM PDT 24
Peak memory 206044 kb
Host smart-5e5ff041-1370-4c75-93a9-06d88fab43e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29883
38142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2988338142
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3725490564
Short name T735
Test name
Test status
Simulation time 11666739774 ps
CPU time 25.98 seconds
Started Jun 21 04:54:57 PM PDT 24
Finished Jun 21 04:55:25 PM PDT 24
Peak memory 206292 kb
Host smart-7ef8576a-8ec0-45a4-9972-0653bc2ade7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37254
90564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3725490564
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1936190405
Short name T991
Test name
Test status
Simulation time 173399972 ps
CPU time 0.83 seconds
Started Jun 21 04:54:51 PM PDT 24
Finished Jun 21 04:54:52 PM PDT 24
Peak memory 206028 kb
Host smart-8b6d8da2-df42-4588-bfdc-ca5488d87817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19361
90405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1936190405
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.193365026
Short name T1962
Test name
Test status
Simulation time 221735097 ps
CPU time 0.9 seconds
Started Jun 21 04:54:51 PM PDT 24
Finished Jun 21 04:54:54 PM PDT 24
Peak memory 206076 kb
Host smart-93f5c4d6-a537-44c7-9c70-84bff996deb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19336
5026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.193365026
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.1717964262
Short name T162
Test name
Test status
Simulation time 22104795672 ps
CPU time 127.23 seconds
Started Jun 21 04:54:50 PM PDT 24
Finished Jun 21 04:56:58 PM PDT 24
Peak memory 206360 kb
Host smart-d73365f7-febc-44f6-adec-3739d4d44aeb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1717964262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.1717964262
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.1805758574
Short name T2256
Test name
Test status
Simulation time 20634232096 ps
CPU time 489.16 seconds
Started Jun 21 04:54:53 PM PDT 24
Finished Jun 21 05:03:04 PM PDT 24
Peak memory 206324 kb
Host smart-6ca28954-0f09-4c6a-a979-34d43a82d4a1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1805758574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.1805758574
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2505600344
Short name T357
Test name
Test status
Simulation time 186975810 ps
CPU time 0.85 seconds
Started Jun 21 04:54:54 PM PDT 24
Finished Jun 21 04:54:57 PM PDT 24
Peak memory 205928 kb
Host smart-fbcbbd5d-54a7-4d35-a310-b59d425dc8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25056
00344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2505600344
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.3577214154
Short name T1762
Test name
Test status
Simulation time 196938476 ps
CPU time 0.83 seconds
Started Jun 21 04:54:54 PM PDT 24
Finished Jun 21 04:54:57 PM PDT 24
Peak memory 205992 kb
Host smart-3346b566-278e-4c66-8fcb-54232ade4780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35772
14154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.3577214154
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.244019091
Short name T1092
Test name
Test status
Simulation time 180206741 ps
CPU time 0.8 seconds
Started Jun 21 04:54:58 PM PDT 24
Finished Jun 21 04:55:01 PM PDT 24
Peak memory 205936 kb
Host smart-57d19087-94b9-4927-b81b-c9b8529b397f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24401
9091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.244019091
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.2641189803
Short name T801
Test name
Test status
Simulation time 157370833 ps
CPU time 0.74 seconds
Started Jun 21 04:55:03 PM PDT 24
Finished Jun 21 04:55:05 PM PDT 24
Peak memory 205964 kb
Host smart-66409e91-adc6-4f82-9cc5-d8937549a480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26411
89803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.2641189803
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1813250494
Short name T1083
Test name
Test status
Simulation time 198689883 ps
CPU time 0.83 seconds
Started Jun 21 04:54:57 PM PDT 24
Finished Jun 21 04:55:00 PM PDT 24
Peak memory 205816 kb
Host smart-2426f86e-1f85-43a1-ab59-89f04d4317e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18132
50494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1813250494
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.4235490649
Short name T795
Test name
Test status
Simulation time 245062883 ps
CPU time 0.97 seconds
Started Jun 21 04:54:43 PM PDT 24
Finished Jun 21 04:54:46 PM PDT 24
Peak memory 206028 kb
Host smart-56fe3968-771b-4232-9ed2-5c08514dac35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42354
90649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.4235490649
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.889378176
Short name T1074
Test name
Test status
Simulation time 6668329948 ps
CPU time 179.18 seconds
Started Jun 21 04:54:57 PM PDT 24
Finished Jun 21 04:57:59 PM PDT 24
Peak memory 206224 kb
Host smart-3f0edb6c-f071-4528-a92d-816a902f7974
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=889378176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.889378176
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.4214255403
Short name T2008
Test name
Test status
Simulation time 187840596 ps
CPU time 0.77 seconds
Started Jun 21 04:54:52 PM PDT 24
Finished Jun 21 04:54:55 PM PDT 24
Peak memory 205972 kb
Host smart-c7935bd5-34f0-47f3-8a03-0c182a8437e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42142
55403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.4214255403
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2558817813
Short name T2363
Test name
Test status
Simulation time 179141079 ps
CPU time 0.78 seconds
Started Jun 21 04:54:57 PM PDT 24
Finished Jun 21 04:54:59 PM PDT 24
Peak memory 206020 kb
Host smart-1b8f0a2b-4ed9-42f7-a8d1-e725aa055153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25588
17813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2558817813
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.2156085038
Short name T2053
Test name
Test status
Simulation time 9278327802 ps
CPU time 68.08 seconds
Started Jun 21 04:54:50 PM PDT 24
Finished Jun 21 04:55:59 PM PDT 24
Peak memory 206212 kb
Host smart-ce68b125-7899-449a-8cea-49f65ed568c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21560
85038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.2156085038
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1524151665
Short name T1964
Test name
Test status
Simulation time 4252775797 ps
CPU time 4.82 seconds
Started Jun 21 04:54:59 PM PDT 24
Finished Jun 21 04:55:06 PM PDT 24
Peak memory 206208 kb
Host smart-d2c71d22-2f05-4b2f-ac99-6c2c56bf090e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1524151665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.1524151665
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.2552802318
Short name T747
Test name
Test status
Simulation time 13411530448 ps
CPU time 13.04 seconds
Started Jun 21 04:55:00 PM PDT 24
Finished Jun 21 04:55:14 PM PDT 24
Peak memory 206116 kb
Host smart-376c6077-67e8-4890-886b-6de6f7befce2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2552802318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.2552802318
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.1642757894
Short name T222
Test name
Test status
Simulation time 23475119690 ps
CPU time 26.59 seconds
Started Jun 21 04:54:59 PM PDT 24
Finished Jun 21 04:55:27 PM PDT 24
Peak memory 206164 kb
Host smart-381df98c-2b21-407e-8bfe-d81cf0c7bab7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1642757894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.1642757894
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3628837962
Short name T2448
Test name
Test status
Simulation time 193967620 ps
CPU time 0.89 seconds
Started Jun 21 04:55:01 PM PDT 24
Finished Jun 21 04:55:03 PM PDT 24
Peak memory 206148 kb
Host smart-64b9ae5f-759e-4ec9-974a-612e7aa3ca71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36288
37962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3628837962
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.2761427134
Short name T1769
Test name
Test status
Simulation time 139108168 ps
CPU time 0.74 seconds
Started Jun 21 04:55:05 PM PDT 24
Finished Jun 21 04:55:08 PM PDT 24
Peak memory 205972 kb
Host smart-6f8ba2c5-81b1-4f3b-b7f3-ab413aa28aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27614
27134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.2761427134
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.530495138
Short name T379
Test name
Test status
Simulation time 217825888 ps
CPU time 0.89 seconds
Started Jun 21 04:55:03 PM PDT 24
Finished Jun 21 04:55:05 PM PDT 24
Peak memory 206000 kb
Host smart-16cd270e-7499-4002-b470-176b7bb7dcd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53049
5138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.530495138
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.1471364020
Short name T2120
Test name
Test status
Simulation time 1010601710 ps
CPU time 2.14 seconds
Started Jun 21 04:55:05 PM PDT 24
Finished Jun 21 04:55:09 PM PDT 24
Peak memory 206184 kb
Host smart-bedc7416-5391-42ba-a3ac-0a70b197be23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14713
64020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.1471364020
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.56202024
Short name T1760
Test name
Test status
Simulation time 19116212467 ps
CPU time 35.43 seconds
Started Jun 21 04:55:04 PM PDT 24
Finished Jun 21 04:55:41 PM PDT 24
Peak memory 206232 kb
Host smart-6d133fbd-b05c-4682-b1dd-366cd35e82a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56202
024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.56202024
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.3490959499
Short name T970
Test name
Test status
Simulation time 426244352 ps
CPU time 1.5 seconds
Started Jun 21 04:54:57 PM PDT 24
Finished Jun 21 04:55:00 PM PDT 24
Peak memory 205924 kb
Host smart-1bdafde3-a2a0-47c5-88d7-466949a71ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34909
59499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.3490959499
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3718098914
Short name T40
Test name
Test status
Simulation time 144782550 ps
CPU time 0.73 seconds
Started Jun 21 04:54:57 PM PDT 24
Finished Jun 21 04:54:59 PM PDT 24
Peak memory 206028 kb
Host smart-a04b1158-005c-40ff-9bd5-93217cd6663f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37180
98914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3718098914
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.772821671
Short name T1798
Test name
Test status
Simulation time 42285526 ps
CPU time 0.66 seconds
Started Jun 21 04:54:58 PM PDT 24
Finished Jun 21 04:55:01 PM PDT 24
Peak memory 205964 kb
Host smart-bd409eb2-de26-423b-a2db-de3cec0caad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77282
1671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.772821671
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1278617232
Short name T886
Test name
Test status
Simulation time 860432030 ps
CPU time 2.08 seconds
Started Jun 21 04:54:58 PM PDT 24
Finished Jun 21 04:55:02 PM PDT 24
Peak memory 206252 kb
Host smart-dc2df483-7af8-4383-8199-6e114e3d60a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12786
17232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1278617232
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.3176172200
Short name T1587
Test name
Test status
Simulation time 345564831 ps
CPU time 1.94 seconds
Started Jun 21 04:55:03 PM PDT 24
Finished Jun 21 04:55:06 PM PDT 24
Peak memory 206184 kb
Host smart-3b0f5609-b237-4f6c-bd10-534a505368bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31761
72200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.3176172200
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.509608774
Short name T1282
Test name
Test status
Simulation time 169768566 ps
CPU time 0.79 seconds
Started Jun 21 04:55:05 PM PDT 24
Finished Jun 21 04:55:08 PM PDT 24
Peak memory 205980 kb
Host smart-2b852be9-4138-40e0-b89b-b7a5dbd77d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50960
8774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.509608774
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3097788569
Short name T115
Test name
Test status
Simulation time 146761084 ps
CPU time 0.84 seconds
Started Jun 21 04:55:06 PM PDT 24
Finished Jun 21 04:55:09 PM PDT 24
Peak memory 206020 kb
Host smart-8d0f1f05-b215-424e-b92c-65ea28c35ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30977
88569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3097788569
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.1665060295
Short name T1637
Test name
Test status
Simulation time 170185041 ps
CPU time 0.85 seconds
Started Jun 21 04:55:03 PM PDT 24
Finished Jun 21 04:55:05 PM PDT 24
Peak memory 205928 kb
Host smart-e3590813-3a6d-438e-a342-d7e445b89151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16650
60295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.1665060295
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.98279741
Short name T1804
Test name
Test status
Simulation time 283192293 ps
CPU time 0.93 seconds
Started Jun 21 04:54:59 PM PDT 24
Finished Jun 21 04:55:02 PM PDT 24
Peak memory 206028 kb
Host smart-0e98b428-294b-4c00-aa0e-30a18779565f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98279
741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.98279741
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.3372648832
Short name T1458
Test name
Test status
Simulation time 23370505495 ps
CPU time 23.67 seconds
Started Jun 21 04:54:57 PM PDT 24
Finished Jun 21 04:55:23 PM PDT 24
Peak memory 206080 kb
Host smart-5cd757c4-3d9a-40bf-8daa-cf0100d83a75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33726
48832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.3372648832
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1796306362
Short name T1526
Test name
Test status
Simulation time 3307053265 ps
CPU time 3.75 seconds
Started Jun 21 04:54:58 PM PDT 24
Finished Jun 21 04:55:04 PM PDT 24
Peak memory 206092 kb
Host smart-8fc4fb0f-56cd-4d0c-97b0-61652486e198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17963
06362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1796306362
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.1525522710
Short name T2329
Test name
Test status
Simulation time 4865715426 ps
CPU time 46.95 seconds
Started Jun 21 04:54:58 PM PDT 24
Finished Jun 21 04:55:47 PM PDT 24
Peak memory 206176 kb
Host smart-2b204652-8bd6-4f70-bd0f-10da0f05d5a4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1525522710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.1525522710
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2683042500
Short name T103
Test name
Test status
Simulation time 289369970 ps
CPU time 0.99 seconds
Started Jun 21 04:55:13 PM PDT 24
Finished Jun 21 04:55:15 PM PDT 24
Peak memory 205988 kb
Host smart-040a662c-6c85-4a9e-ac26-05dda9805c36
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2683042500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2683042500
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2783207355
Short name T2397
Test name
Test status
Simulation time 202492755 ps
CPU time 0.93 seconds
Started Jun 21 04:55:02 PM PDT 24
Finished Jun 21 04:55:05 PM PDT 24
Peak memory 205960 kb
Host smart-c1f7e9d4-9b39-4735-ac4c-68f5cc3a7053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27832
07355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2783207355
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.764665200
Short name T805
Test name
Test status
Simulation time 7043765533 ps
CPU time 202.9 seconds
Started Jun 21 04:54:59 PM PDT 24
Finished Jun 21 04:58:24 PM PDT 24
Peak memory 206180 kb
Host smart-15847146-8a02-4817-b67d-6db09fc09da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76466
5200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.764665200
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.4248418205
Short name T838
Test name
Test status
Simulation time 7727431505 ps
CPU time 222.34 seconds
Started Jun 21 04:55:02 PM PDT 24
Finished Jun 21 04:58:46 PM PDT 24
Peak memory 206180 kb
Host smart-01d8738a-37bb-429f-bba8-dd383239edb0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4248418205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.4248418205
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.3421234506
Short name T523
Test name
Test status
Simulation time 155299363 ps
CPU time 0.84 seconds
Started Jun 21 04:55:05 PM PDT 24
Finished Jun 21 04:55:08 PM PDT 24
Peak memory 205960 kb
Host smart-9297c947-f3fa-4604-81a1-560a23f89b23
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3421234506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.3421234506
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.450576374
Short name T1054
Test name
Test status
Simulation time 146952260 ps
CPU time 0.78 seconds
Started Jun 21 04:55:02 PM PDT 24
Finished Jun 21 04:55:04 PM PDT 24
Peak memory 206020 kb
Host smart-3e1c7854-1a70-4e81-9e5a-0ef93e02d3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45057
6374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.450576374
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3775863779
Short name T1095
Test name
Test status
Simulation time 256753244 ps
CPU time 0.98 seconds
Started Jun 21 04:55:06 PM PDT 24
Finished Jun 21 04:55:08 PM PDT 24
Peak memory 206144 kb
Host smart-31136672-ef60-4b36-9f29-50833bccee06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37758
63779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3775863779
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.210239457
Short name T414
Test name
Test status
Simulation time 147579801 ps
CPU time 0.82 seconds
Started Jun 21 04:55:06 PM PDT 24
Finished Jun 21 04:55:09 PM PDT 24
Peak memory 206024 kb
Host smart-0eb7dbb5-f547-49c7-94ed-605e3d9b1cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21023
9457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.210239457
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3067202130
Short name T858
Test name
Test status
Simulation time 199126795 ps
CPU time 0.86 seconds
Started Jun 21 04:55:04 PM PDT 24
Finished Jun 21 04:55:07 PM PDT 24
Peak memory 205976 kb
Host smart-d7aacc49-3a08-4e2d-a1b3-f1ebcfd805df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30672
02130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3067202130
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.4097963457
Short name T847
Test name
Test status
Simulation time 175403704 ps
CPU time 0.83 seconds
Started Jun 21 04:55:05 PM PDT 24
Finished Jun 21 04:55:08 PM PDT 24
Peak memory 205924 kb
Host smart-bad28f57-6ede-400b-9832-0961829da3a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40979
63457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.4097963457
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2213435410
Short name T180
Test name
Test status
Simulation time 150046074 ps
CPU time 0.8 seconds
Started Jun 21 04:55:05 PM PDT 24
Finished Jun 21 04:55:08 PM PDT 24
Peak memory 206016 kb
Host smart-39e0aea2-72c1-45d2-85a9-c199d7534949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22134
35410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2213435410
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.2452523644
Short name T1684
Test name
Test status
Simulation time 222683570 ps
CPU time 0.97 seconds
Started Jun 21 04:55:05 PM PDT 24
Finished Jun 21 04:55:08 PM PDT 24
Peak memory 206028 kb
Host smart-be3b2235-4b2a-4dc9-b23d-7801d4e5d815
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2452523644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.2452523644
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.4050242808
Short name T1866
Test name
Test status
Simulation time 149058809 ps
CPU time 0.75 seconds
Started Jun 21 04:55:06 PM PDT 24
Finished Jun 21 04:55:09 PM PDT 24
Peak memory 206048 kb
Host smart-e3bf4c04-8269-42b9-b952-dcd9e52fbb5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40502
42808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.4050242808
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3366266980
Short name T717
Test name
Test status
Simulation time 40935082 ps
CPU time 0.68 seconds
Started Jun 21 04:55:05 PM PDT 24
Finished Jun 21 04:55:08 PM PDT 24
Peak memory 206068 kb
Host smart-a4f4cca4-5c1a-4830-8e42-f6fdae19d7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33662
66980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3366266980
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.144781704
Short name T161
Test name
Test status
Simulation time 7904930380 ps
CPU time 17.41 seconds
Started Jun 21 04:55:08 PM PDT 24
Finished Jun 21 04:55:27 PM PDT 24
Peak memory 206128 kb
Host smart-c66bcf05-ff81-441e-af71-15acd2826b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14478
1704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.144781704
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1418564624
Short name T1620
Test name
Test status
Simulation time 165790392 ps
CPU time 0.82 seconds
Started Jun 21 04:55:08 PM PDT 24
Finished Jun 21 04:55:10 PM PDT 24
Peak memory 205912 kb
Host smart-8daaecda-6ad8-473e-ab07-aea39d2f9050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14185
64624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1418564624
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2583588503
Short name T1309
Test name
Test status
Simulation time 176130188 ps
CPU time 0.86 seconds
Started Jun 21 04:55:07 PM PDT 24
Finished Jun 21 04:55:10 PM PDT 24
Peak memory 206028 kb
Host smart-7f5e1425-6463-48f9-8dd6-e24d143aeabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25835
88503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2583588503
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.1060185269
Short name T2287
Test name
Test status
Simulation time 18877812692 ps
CPU time 112.3 seconds
Started Jun 21 04:55:05 PM PDT 24
Finished Jun 21 04:56:59 PM PDT 24
Peak memory 206356 kb
Host smart-edf8a4f2-188e-49b5-abfd-bde93764a3de
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1060185269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.1060185269
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.801770771
Short name T178
Test name
Test status
Simulation time 5401283312 ps
CPU time 33.68 seconds
Started Jun 21 04:55:06 PM PDT 24
Finished Jun 21 04:55:42 PM PDT 24
Peak memory 206240 kb
Host smart-769ce1a6-1501-44f0-ad13-55f2f0ec1a94
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=801770771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.801770771
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.3864305390
Short name T583
Test name
Test status
Simulation time 26560038830 ps
CPU time 625.11 seconds
Started Jun 21 04:55:06 PM PDT 24
Finished Jun 21 05:05:33 PM PDT 24
Peak memory 206360 kb
Host smart-61a5919d-dc3d-40a7-8ed8-8275264f873d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3864305390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.3864305390
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.1495635328
Short name T1667
Test name
Test status
Simulation time 239112275 ps
CPU time 0.96 seconds
Started Jun 21 04:55:06 PM PDT 24
Finished Jun 21 04:55:08 PM PDT 24
Peak memory 205964 kb
Host smart-70f67b3c-aa28-418c-a247-ae1c25a0b90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14956
35328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.1495635328
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.1378439125
Short name T644
Test name
Test status
Simulation time 170253945 ps
CPU time 0.86 seconds
Started Jun 21 04:55:06 PM PDT 24
Finished Jun 21 04:55:09 PM PDT 24
Peak memory 206024 kb
Host smart-83d4fb9e-2ee8-498a-9372-d8492950f7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13784
39125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1378439125
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1772332865
Short name T1483
Test name
Test status
Simulation time 153531876 ps
CPU time 0.81 seconds
Started Jun 21 04:55:05 PM PDT 24
Finished Jun 21 04:55:08 PM PDT 24
Peak memory 205956 kb
Host smart-82735095-4c9b-4d8d-88a0-dd2b60dd16ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17723
32865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1772332865
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.2779003974
Short name T1200
Test name
Test status
Simulation time 143407801 ps
CPU time 0.78 seconds
Started Jun 21 04:55:06 PM PDT 24
Finished Jun 21 04:55:09 PM PDT 24
Peak memory 206040 kb
Host smart-aa4ec194-f557-4cd6-a312-5ac709195268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27790
03974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2779003974
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2899749534
Short name T1285
Test name
Test status
Simulation time 143133876 ps
CPU time 0.76 seconds
Started Jun 21 04:55:05 PM PDT 24
Finished Jun 21 04:55:07 PM PDT 24
Peak memory 206036 kb
Host smart-9eb943db-7a3a-41f1-9ee2-5203e0275409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28997
49534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2899749534
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.3209290111
Short name T1058
Test name
Test status
Simulation time 207364706 ps
CPU time 0.9 seconds
Started Jun 21 04:54:58 PM PDT 24
Finished Jun 21 04:55:01 PM PDT 24
Peak memory 206024 kb
Host smart-a68e8023-ff9e-4524-96b7-29e886b7da23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32092
90111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.3209290111
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.4154818786
Short name T1439
Test name
Test status
Simulation time 4409619465 ps
CPU time 31.95 seconds
Started Jun 21 04:55:06 PM PDT 24
Finished Jun 21 04:55:39 PM PDT 24
Peak memory 206296 kb
Host smart-8970d452-9546-4c40-8b38-00516f903a13
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4154818786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.4154818786
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.297802007
Short name T681
Test name
Test status
Simulation time 141008280 ps
CPU time 0.78 seconds
Started Jun 21 04:55:06 PM PDT 24
Finished Jun 21 04:55:09 PM PDT 24
Peak memory 206004 kb
Host smart-becd9b8a-afca-4905-b7d9-7dd6a6cfee4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29780
2007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.297802007
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.722226346
Short name T1584
Test name
Test status
Simulation time 150537529 ps
CPU time 0.81 seconds
Started Jun 21 04:55:06 PM PDT 24
Finished Jun 21 04:55:09 PM PDT 24
Peak memory 206028 kb
Host smart-e2ea1f9b-90bb-4b7c-bd6b-0dad280f50c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72222
6346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.722226346
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.4144143990
Short name T1194
Test name
Test status
Simulation time 5559752733 ps
CPU time 38.92 seconds
Started Jun 21 04:55:05 PM PDT 24
Finished Jun 21 04:55:46 PM PDT 24
Peak memory 206332 kb
Host smart-27ace808-dd6b-4052-a8e2-7228b37e7b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41441
43990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.4144143990
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.4116140874
Short name T1101
Test name
Test status
Simulation time 3468150661 ps
CPU time 3.88 seconds
Started Jun 21 04:55:13 PM PDT 24
Finished Jun 21 04:55:18 PM PDT 24
Peak memory 206208 kb
Host smart-834163f0-87c3-4614-b5bb-6d2840c112fb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4116140874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.4116140874
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.2863842775
Short name T606
Test name
Test status
Simulation time 13311793499 ps
CPU time 12.97 seconds
Started Jun 21 04:55:18 PM PDT 24
Finished Jun 21 04:55:32 PM PDT 24
Peak memory 206092 kb
Host smart-49c4a317-40ee-4f0a-8887-6663a00a437f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2863842775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.2863842775
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.880740994
Short name T1979
Test name
Test status
Simulation time 23441523699 ps
CPU time 23.68 seconds
Started Jun 21 04:55:20 PM PDT 24
Finished Jun 21 04:55:45 PM PDT 24
Peak memory 206292 kb
Host smart-f7fd9485-9cde-47c5-bf24-7c04c2e7211f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=880740994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.880740994
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2024196813
Short name T419
Test name
Test status
Simulation time 187433535 ps
CPU time 0.82 seconds
Started Jun 21 04:55:18 PM PDT 24
Finished Jun 21 04:55:20 PM PDT 24
Peak memory 205968 kb
Host smart-6b1bb7c5-eb77-45de-9daf-e2428127541d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20241
96813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2024196813
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3849623815
Short name T2133
Test name
Test status
Simulation time 173204855 ps
CPU time 0.77 seconds
Started Jun 21 04:55:16 PM PDT 24
Finished Jun 21 04:55:18 PM PDT 24
Peak memory 205936 kb
Host smart-f7a82dc8-f2cb-4a60-b1cb-7598afd11688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38496
23815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3849623815
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.1215798966
Short name T2123
Test name
Test status
Simulation time 258125155 ps
CPU time 1.05 seconds
Started Jun 21 04:55:15 PM PDT 24
Finished Jun 21 04:55:17 PM PDT 24
Peak memory 205960 kb
Host smart-c0508009-4b87-4928-904d-50646682b280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12157
98966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.1215798966
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.1551696313
Short name T1923
Test name
Test status
Simulation time 1267860906 ps
CPU time 2.96 seconds
Started Jun 21 04:55:16 PM PDT 24
Finished Jun 21 04:55:20 PM PDT 24
Peak memory 206248 kb
Host smart-c03dce50-f0ed-445d-957a-560e5a675dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15516
96313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.1551696313
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.2960345284
Short name T2173
Test name
Test status
Simulation time 10309471350 ps
CPU time 18.91 seconds
Started Jun 21 04:55:13 PM PDT 24
Finished Jun 21 04:55:34 PM PDT 24
Peak memory 206224 kb
Host smart-fd1968e7-a285-4d37-958a-b7cb2d62106e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29603
45284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2960345284
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.3552827313
Short name T2081
Test name
Test status
Simulation time 468911629 ps
CPU time 1.32 seconds
Started Jun 21 04:55:14 PM PDT 24
Finished Jun 21 04:55:17 PM PDT 24
Peak memory 206000 kb
Host smart-799c21a8-63c5-43de-84fe-d3079b308577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35528
27313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.3552827313
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.1983372901
Short name T1946
Test name
Test status
Simulation time 181613454 ps
CPU time 0.83 seconds
Started Jun 21 04:55:17 PM PDT 24
Finished Jun 21 04:55:19 PM PDT 24
Peak memory 206024 kb
Host smart-e2b40349-0085-4793-8cbb-66f70e8efa35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19833
72901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.1983372901
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.4086795269
Short name T1228
Test name
Test status
Simulation time 38296685 ps
CPU time 0.65 seconds
Started Jun 21 04:55:14 PM PDT 24
Finished Jun 21 04:55:16 PM PDT 24
Peak memory 206016 kb
Host smart-749ce332-68c2-4994-b0ed-f68876228b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40867
95269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.4086795269
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.292385245
Short name T2436
Test name
Test status
Simulation time 717993672 ps
CPU time 1.88 seconds
Started Jun 21 04:55:11 PM PDT 24
Finished Jun 21 04:55:14 PM PDT 24
Peak memory 206268 kb
Host smart-3565808d-97ce-4673-9044-35f17d8639b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29238
5245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.292385245
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.912502911
Short name T1159
Test name
Test status
Simulation time 168245295 ps
CPU time 1.66 seconds
Started Jun 21 04:55:13 PM PDT 24
Finished Jun 21 04:55:17 PM PDT 24
Peak memory 206188 kb
Host smart-5c85dda3-6529-4454-8852-c926be9d2de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91250
2911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.912502911
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.801560717
Short name T392
Test name
Test status
Simulation time 213521631 ps
CPU time 0.91 seconds
Started Jun 21 04:55:23 PM PDT 24
Finished Jun 21 04:55:26 PM PDT 24
Peak memory 205936 kb
Host smart-ca789a13-d8f0-4894-a8a1-c96989d254d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80156
0717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.801560717
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1749534489
Short name T729
Test name
Test status
Simulation time 180604162 ps
CPU time 0.79 seconds
Started Jun 21 04:55:20 PM PDT 24
Finished Jun 21 04:55:22 PM PDT 24
Peak memory 205960 kb
Host smart-241a7057-e262-420a-b7e9-be8509653988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17495
34489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1749534489
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.914201607
Short name T1697
Test name
Test status
Simulation time 237120473 ps
CPU time 0.92 seconds
Started Jun 21 04:55:13 PM PDT 24
Finished Jun 21 04:55:16 PM PDT 24
Peak memory 206048 kb
Host smart-aabbaf8c-8ad0-460f-ba29-5b748386701d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91420
1607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.914201607
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.1042400827
Short name T1707
Test name
Test status
Simulation time 178143078 ps
CPU time 0.85 seconds
Started Jun 21 04:55:24 PM PDT 24
Finished Jun 21 04:55:26 PM PDT 24
Peak memory 205968 kb
Host smart-0057997d-0667-4297-bbf1-ca98733090d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10424
00827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.1042400827
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.4287483056
Short name T1061
Test name
Test status
Simulation time 23325202726 ps
CPU time 23.35 seconds
Started Jun 21 04:55:20 PM PDT 24
Finished Jun 21 04:55:44 PM PDT 24
Peak memory 206028 kb
Host smart-f9c675f6-9a29-440d-8dfe-d41dbdff61e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42874
83056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.4287483056
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.356680617
Short name T1821
Test name
Test status
Simulation time 3301445656 ps
CPU time 4.1 seconds
Started Jun 21 04:55:13 PM PDT 24
Finished Jun 21 04:55:19 PM PDT 24
Peak memory 205984 kb
Host smart-07bb3463-d0c0-49be-a1fd-339832f9117e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35668
0617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.356680617
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.673901438
Short name T437
Test name
Test status
Simulation time 12725896365 ps
CPU time 348.45 seconds
Started Jun 21 04:55:19 PM PDT 24
Finished Jun 21 05:01:08 PM PDT 24
Peak memory 206220 kb
Host smart-4182d551-3e38-4f64-bd73-f77894bcdb18
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=673901438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.673901438
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.4126058680
Short name T952
Test name
Test status
Simulation time 244155160 ps
CPU time 0.95 seconds
Started Jun 21 04:55:25 PM PDT 24
Finished Jun 21 04:55:27 PM PDT 24
Peak memory 205948 kb
Host smart-f2b940ec-adce-449e-9090-499e2dfeb9a1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4126058680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.4126058680
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.11536967
Short name T1321
Test name
Test status
Simulation time 197916070 ps
CPU time 0.88 seconds
Started Jun 21 04:55:20 PM PDT 24
Finished Jun 21 04:55:22 PM PDT 24
Peak memory 206016 kb
Host smart-85fc7608-face-4217-ac9d-4138d0816331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11536
967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.11536967
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2725415549
Short name T1780
Test name
Test status
Simulation time 12459023424 ps
CPU time 360.65 seconds
Started Jun 21 04:55:19 PM PDT 24
Finished Jun 21 05:01:21 PM PDT 24
Peak memory 206252 kb
Host smart-91df8c04-a0f2-44e2-968b-f25eeb4d0d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27254
15549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2725415549
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2347448258
Short name T2258
Test name
Test status
Simulation time 5398180384 ps
CPU time 154.83 seconds
Started Jun 21 04:55:18 PM PDT 24
Finished Jun 21 04:57:54 PM PDT 24
Peak memory 206200 kb
Host smart-054e6065-9f39-4522-b7a8-396136707106
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2347448258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2347448258
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3412921455
Short name T2145
Test name
Test status
Simulation time 187290752 ps
CPU time 0.85 seconds
Started Jun 21 04:55:23 PM PDT 24
Finished Jun 21 04:55:26 PM PDT 24
Peak memory 206048 kb
Host smart-835ede21-2b40-4b9c-9178-871d79f666de
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3412921455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3412921455
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.710449561
Short name T768
Test name
Test status
Simulation time 146026362 ps
CPU time 0.77 seconds
Started Jun 21 04:55:19 PM PDT 24
Finished Jun 21 04:55:21 PM PDT 24
Peak memory 206048 kb
Host smart-69b8c4ce-c7e8-48ec-95a5-2dde397dcba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71044
9561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.710449561
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.1381119281
Short name T130
Test name
Test status
Simulation time 176879107 ps
CPU time 0.75 seconds
Started Jun 21 04:55:18 PM PDT 24
Finished Jun 21 04:55:19 PM PDT 24
Peak memory 206028 kb
Host smart-31917af6-3740-4ae4-baf6-69fbe921ff9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13811
19281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1381119281
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.4109713134
Short name T1409
Test name
Test status
Simulation time 245219453 ps
CPU time 0.92 seconds
Started Jun 21 04:55:19 PM PDT 24
Finished Jun 21 04:55:21 PM PDT 24
Peak memory 205972 kb
Host smart-f98551f0-a5aa-45d3-b0f3-861c5a3e1dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41097
13134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.4109713134
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.643088527
Short name T1681
Test name
Test status
Simulation time 163448311 ps
CPU time 0.74 seconds
Started Jun 21 04:55:20 PM PDT 24
Finished Jun 21 04:55:22 PM PDT 24
Peak memory 205964 kb
Host smart-72a89b7d-fbf2-49ef-b86f-ec899754c378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64308
8527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.643088527
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3747507044
Short name T674
Test name
Test status
Simulation time 181661565 ps
CPU time 0.85 seconds
Started Jun 21 04:55:13 PM PDT 24
Finished Jun 21 04:55:15 PM PDT 24
Peak memory 206000 kb
Host smart-c584d387-6a70-4c29-9625-4a2ddd2f49d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37475
07044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3747507044
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.4281233949
Short name T1122
Test name
Test status
Simulation time 192036584 ps
CPU time 0.81 seconds
Started Jun 21 04:55:21 PM PDT 24
Finished Jun 21 04:55:24 PM PDT 24
Peak memory 206020 kb
Host smart-7601451a-fa10-4b4c-9f02-16a794dd8223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42812
33949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.4281233949
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.3358321024
Short name T1288
Test name
Test status
Simulation time 219491706 ps
CPU time 0.87 seconds
Started Jun 21 04:55:21 PM PDT 24
Finished Jun 21 04:55:23 PM PDT 24
Peak memory 206048 kb
Host smart-57023b74-4aff-4452-a243-37f8304c42c6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3358321024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.3358321024
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.756179550
Short name T2475
Test name
Test status
Simulation time 139040654 ps
CPU time 0.75 seconds
Started Jun 21 04:55:23 PM PDT 24
Finished Jun 21 04:55:26 PM PDT 24
Peak memory 205952 kb
Host smart-23f76f92-6a51-4e37-9849-58b312d2dcf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75617
9550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.756179550
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1593571717
Short name T213
Test name
Test status
Simulation time 83869729 ps
CPU time 0.76 seconds
Started Jun 21 04:55:23 PM PDT 24
Finished Jun 21 04:55:26 PM PDT 24
Peak memory 205976 kb
Host smart-931ccda6-1633-4654-8d25-2deafda45a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15935
71717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1593571717
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.1204296799
Short name T2491
Test name
Test status
Simulation time 21143675439 ps
CPU time 48.23 seconds
Started Jun 21 04:55:19 PM PDT 24
Finished Jun 21 04:56:08 PM PDT 24
Peak memory 206244 kb
Host smart-b658f6ed-c417-428f-90ec-c39688f34d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12042
96799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1204296799
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2797709905
Short name T78
Test name
Test status
Simulation time 168323473 ps
CPU time 0.78 seconds
Started Jun 21 04:55:24 PM PDT 24
Finished Jun 21 04:55:26 PM PDT 24
Peak memory 205980 kb
Host smart-40f2a1fc-a02f-4edc-806a-28dc3408665e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27977
09905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2797709905
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2612170570
Short name T1320
Test name
Test status
Simulation time 282636016 ps
CPU time 0.98 seconds
Started Jun 21 04:55:19 PM PDT 24
Finished Jun 21 04:55:22 PM PDT 24
Peak memory 205972 kb
Host smart-4d64e4b7-b939-4b40-827b-86b427473424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26121
70570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2612170570
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.441739936
Short name T1695
Test name
Test status
Simulation time 11255593747 ps
CPU time 55.95 seconds
Started Jun 21 04:55:18 PM PDT 24
Finished Jun 21 04:56:16 PM PDT 24
Peak memory 206324 kb
Host smart-c0bb393c-3894-4547-8761-f54892c07543
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=441739936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.441739936
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.956291686
Short name T1749
Test name
Test status
Simulation time 17953972033 ps
CPU time 157.45 seconds
Started Jun 21 04:55:17 PM PDT 24
Finished Jun 21 04:57:56 PM PDT 24
Peak memory 206300 kb
Host smart-e1b0c098-30c5-44ed-88ad-9d8e91e1c31c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=956291686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.956291686
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.3102323989
Short name T84
Test name
Test status
Simulation time 21871116918 ps
CPU time 504.15 seconds
Started Jun 21 04:55:20 PM PDT 24
Finished Jun 21 05:03:45 PM PDT 24
Peak memory 206332 kb
Host smart-6fbfd6be-1846-479e-8564-fd2f8a3ca1d2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3102323989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.3102323989
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.982171757
Short name T1303
Test name
Test status
Simulation time 237902461 ps
CPU time 0.98 seconds
Started Jun 21 04:55:27 PM PDT 24
Finished Jun 21 04:55:28 PM PDT 24
Peak memory 205976 kb
Host smart-2f44e044-5327-418a-83bb-2ca01bf5efba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98217
1757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.982171757
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.305531899
Short name T713
Test name
Test status
Simulation time 187977942 ps
CPU time 0.91 seconds
Started Jun 21 04:55:17 PM PDT 24
Finished Jun 21 04:55:18 PM PDT 24
Peak memory 206148 kb
Host smart-3d661b96-9bbf-41a4-b46f-9029c469bb4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30553
1899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.305531899
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1292776894
Short name T2004
Test name
Test status
Simulation time 175434752 ps
CPU time 0.81 seconds
Started Jun 21 04:55:23 PM PDT 24
Finished Jun 21 04:55:26 PM PDT 24
Peak memory 206008 kb
Host smart-b4125097-de71-49c9-a14d-155f46b831a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12927
76894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1292776894
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3624712400
Short name T85
Test name
Test status
Simulation time 148450556 ps
CPU time 0.82 seconds
Started Jun 21 04:55:21 PM PDT 24
Finished Jun 21 04:55:24 PM PDT 24
Peak memory 206016 kb
Host smart-a34027a2-2355-49d2-860e-fdcdc06d869c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36247
12400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3624712400
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1927099210
Short name T1500
Test name
Test status
Simulation time 147423774 ps
CPU time 0.81 seconds
Started Jun 21 04:55:22 PM PDT 24
Finished Jun 21 04:55:24 PM PDT 24
Peak memory 205940 kb
Host smart-a6d21574-2a19-4274-a902-7fa8e13cf211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19270
99210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1927099210
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.337471973
Short name T1605
Test name
Test status
Simulation time 233532550 ps
CPU time 0.91 seconds
Started Jun 21 04:55:13 PM PDT 24
Finished Jun 21 04:55:15 PM PDT 24
Peak memory 206024 kb
Host smart-db22a2be-5b61-412a-9e28-93a618729e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33747
1973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.337471973
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.1942098398
Short name T1791
Test name
Test status
Simulation time 6260014469 ps
CPU time 48 seconds
Started Jun 21 04:55:14 PM PDT 24
Finished Jun 21 04:56:03 PM PDT 24
Peak memory 206292 kb
Host smart-dc1242aa-86cc-42c8-94f8-8fc8dc66d996
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1942098398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.1942098398
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1418544309
Short name T2091
Test name
Test status
Simulation time 186214183 ps
CPU time 0.82 seconds
Started Jun 21 04:55:20 PM PDT 24
Finished Jun 21 04:55:22 PM PDT 24
Peak memory 206028 kb
Host smart-6c94c597-f074-4f7a-b408-63c966dcd66c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14185
44309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1418544309
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.3061241007
Short name T2077
Test name
Test status
Simulation time 182307137 ps
CPU time 0.8 seconds
Started Jun 21 04:55:23 PM PDT 24
Finished Jun 21 04:55:26 PM PDT 24
Peak memory 206020 kb
Host smart-3e1eb157-3699-4844-8f36-51aa77878672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30612
41007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3061241007
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.893270846
Short name T1198
Test name
Test status
Simulation time 13542889389 ps
CPU time 394.25 seconds
Started Jun 21 04:55:22 PM PDT 24
Finished Jun 21 05:01:57 PM PDT 24
Peak memory 206188 kb
Host smart-06ade3fe-826b-4c99-b3d8-93b6eb662756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89327
0846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.893270846
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.2884658076
Short name T1827
Test name
Test status
Simulation time 4141734031 ps
CPU time 4.46 seconds
Started Jun 21 04:55:20 PM PDT 24
Finished Jun 21 04:55:26 PM PDT 24
Peak memory 206276 kb
Host smart-97c0f357-d7ca-42ae-96c8-e48148f0b764
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2884658076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.2884658076
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3587550819
Short name T813
Test name
Test status
Simulation time 13371840439 ps
CPU time 12.4 seconds
Started Jun 21 04:55:26 PM PDT 24
Finished Jun 21 04:55:39 PM PDT 24
Peak memory 206040 kb
Host smart-45a92b1f-a37c-46a3-99bc-7844ad997df7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3587550819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3587550819
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.789674244
Short name T192
Test name
Test status
Simulation time 23397614868 ps
CPU time 27.52 seconds
Started Jun 21 04:55:23 PM PDT 24
Finished Jun 21 04:55:52 PM PDT 24
Peak memory 206264 kb
Host smart-be859971-de9f-4571-a7ea-271d765c05a9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=789674244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.789674244
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.558081490
Short name T1530
Test name
Test status
Simulation time 154940279 ps
CPU time 0.81 seconds
Started Jun 21 04:55:22 PM PDT 24
Finished Jun 21 04:55:24 PM PDT 24
Peak memory 206004 kb
Host smart-e193aee6-8839-4670-9f1b-fc7f3bc4cee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55808
1490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.558081490
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1600438104
Short name T2464
Test name
Test status
Simulation time 183830562 ps
CPU time 0.81 seconds
Started Jun 21 04:55:22 PM PDT 24
Finished Jun 21 04:55:24 PM PDT 24
Peak memory 206004 kb
Host smart-d0a61d8c-d0dc-49ac-aebe-92b6593f2129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16004
38104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1600438104
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.3064026785
Short name T1988
Test name
Test status
Simulation time 522719116 ps
CPU time 1.78 seconds
Started Jun 21 04:55:22 PM PDT 24
Finished Jun 21 04:55:26 PM PDT 24
Peak memory 206104 kb
Host smart-677533a9-13d0-4f57-b6d1-844238a8aa98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30640
26785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.3064026785
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.659477435
Short name T1269
Test name
Test status
Simulation time 1116143283 ps
CPU time 2.54 seconds
Started Jun 21 04:55:22 PM PDT 24
Finished Jun 21 04:55:27 PM PDT 24
Peak memory 206148 kb
Host smart-291812f1-1461-4ba3-8dc4-5557527c6821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65947
7435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.659477435
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.3200784759
Short name T164
Test name
Test status
Simulation time 15928599362 ps
CPU time 32.05 seconds
Started Jun 21 04:55:26 PM PDT 24
Finished Jun 21 04:55:58 PM PDT 24
Peak memory 206212 kb
Host smart-7ad5709c-d49e-4723-b90d-d5fd41f5ebb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32007
84759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.3200784759
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3960931851
Short name T967
Test name
Test status
Simulation time 357691342 ps
CPU time 1.31 seconds
Started Jun 21 04:55:28 PM PDT 24
Finished Jun 21 04:55:30 PM PDT 24
Peak memory 205940 kb
Host smart-9edeb493-2b94-420c-901a-91264bba5c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39609
31851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3960931851
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1887471949
Short name T1233
Test name
Test status
Simulation time 168676005 ps
CPU time 0.76 seconds
Started Jun 21 04:55:30 PM PDT 24
Finished Jun 21 04:55:32 PM PDT 24
Peak memory 205924 kb
Host smart-8f60ad39-a855-4bf3-9962-d7dc2a5bf0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18874
71949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1887471949
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1773467762
Short name T944
Test name
Test status
Simulation time 32370331 ps
CPU time 0.65 seconds
Started Jun 21 04:55:34 PM PDT 24
Finished Jun 21 04:55:36 PM PDT 24
Peak memory 206016 kb
Host smart-2dff5c55-82db-4d68-83e2-b6dd76a8d7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17734
67762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1773467762
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3757484469
Short name T560
Test name
Test status
Simulation time 1009466115 ps
CPU time 2.32 seconds
Started Jun 21 04:55:30 PM PDT 24
Finished Jun 21 04:55:33 PM PDT 24
Peak memory 206140 kb
Host smart-ba2c0ea8-3e39-436a-b742-4d10444c8b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37574
84469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3757484469
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.2627112493
Short name T2268
Test name
Test status
Simulation time 287871795 ps
CPU time 1.78 seconds
Started Jun 21 04:55:29 PM PDT 24
Finished Jun 21 04:55:32 PM PDT 24
Peak memory 206176 kb
Host smart-94fee342-0569-49da-9d5b-9cb7dba832ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26271
12493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2627112493
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.87835058
Short name T2013
Test name
Test status
Simulation time 159395622 ps
CPU time 0.82 seconds
Started Jun 21 04:55:35 PM PDT 24
Finished Jun 21 04:55:36 PM PDT 24
Peak memory 206008 kb
Host smart-fe6599f2-aa3c-430b-9ea4-04cfd2e28ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87835
058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.87835058
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2165893385
Short name T373
Test name
Test status
Simulation time 144919735 ps
CPU time 0.81 seconds
Started Jun 21 04:55:30 PM PDT 24
Finished Jun 21 04:55:32 PM PDT 24
Peak memory 205928 kb
Host smart-001f1c79-469d-4d0f-b4c5-3ed1bce64042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21658
93385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2165893385
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.909554243
Short name T29
Test name
Test status
Simulation time 236890742 ps
CPU time 0.89 seconds
Started Jun 21 04:55:33 PM PDT 24
Finished Jun 21 04:55:35 PM PDT 24
Peak memory 206024 kb
Host smart-a9120169-a07a-48cd-80a7-dc62a4d786b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90955
4243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.909554243
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3085269546
Short name T1504
Test name
Test status
Simulation time 216589793 ps
CPU time 0.92 seconds
Started Jun 21 04:55:31 PM PDT 24
Finished Jun 21 04:55:33 PM PDT 24
Peak memory 205952 kb
Host smart-7c05a1e6-4028-41aa-9001-fb7f74e0ee61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30852
69546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3085269546
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.1236057196
Short name T2495
Test name
Test status
Simulation time 23312791237 ps
CPU time 21.96 seconds
Started Jun 21 04:55:29 PM PDT 24
Finished Jun 21 04:55:52 PM PDT 24
Peak memory 206084 kb
Host smart-db71037c-460d-49f4-b57c-01f7aaf63e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12360
57196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.1236057196
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.1453998301
Short name T959
Test name
Test status
Simulation time 3358082863 ps
CPU time 4.32 seconds
Started Jun 21 04:55:30 PM PDT 24
Finished Jun 21 04:55:36 PM PDT 24
Peak memory 205984 kb
Host smart-f5d43000-83df-49fc-bd22-85f97a2cd99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14539
98301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.1453998301
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.3568124235
Short name T1953
Test name
Test status
Simulation time 8387734915 ps
CPU time 59.52 seconds
Started Jun 21 04:55:28 PM PDT 24
Finished Jun 21 04:56:28 PM PDT 24
Peak memory 206352 kb
Host smart-8bf93529-da98-450d-9514-4db66d8ab3df
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3568124235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.3568124235
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.1250089349
Short name T620
Test name
Test status
Simulation time 239099571 ps
CPU time 0.96 seconds
Started Jun 21 04:55:43 PM PDT 24
Finished Jun 21 04:55:46 PM PDT 24
Peak memory 206048 kb
Host smart-cd4bf77d-7eb3-4aa6-b99a-f583fb9a95bd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1250089349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.1250089349
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1375953372
Short name T308
Test name
Test status
Simulation time 185117604 ps
CPU time 0.84 seconds
Started Jun 21 04:55:33 PM PDT 24
Finished Jun 21 04:55:35 PM PDT 24
Peak memory 206052 kb
Host smart-5f710d82-916c-4476-a40b-041b88136c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13759
53372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1375953372
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.2617913775
Short name T1231
Test name
Test status
Simulation time 11050350597 ps
CPU time 81.83 seconds
Started Jun 21 04:55:29 PM PDT 24
Finished Jun 21 04:56:51 PM PDT 24
Peak memory 206272 kb
Host smart-42865477-5731-4721-9b12-8e35bd811537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26179
13775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.2617913775
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.255113118
Short name T1431
Test name
Test status
Simulation time 3727456951 ps
CPU time 108.24 seconds
Started Jun 21 04:55:31 PM PDT 24
Finished Jun 21 04:57:21 PM PDT 24
Peak memory 206212 kb
Host smart-f8ef2395-eddc-4f11-bbbe-a64897fa280a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=255113118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.255113118
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.183453508
Short name T2400
Test name
Test status
Simulation time 171998364 ps
CPU time 0.9 seconds
Started Jun 21 04:55:36 PM PDT 24
Finished Jun 21 04:55:38 PM PDT 24
Peak memory 206000 kb
Host smart-cf0449bb-959c-4ccd-b80d-bfa51f42451c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=183453508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.183453508
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3446088597
Short name T1521
Test name
Test status
Simulation time 173082063 ps
CPU time 0.84 seconds
Started Jun 21 04:55:31 PM PDT 24
Finished Jun 21 04:55:33 PM PDT 24
Peak memory 206148 kb
Host smart-16b0e995-3624-4330-8f87-e31d2817867a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34460
88597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3446088597
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.718546873
Short name T20
Test name
Test status
Simulation time 266867972 ps
CPU time 0.95 seconds
Started Jun 21 04:55:35 PM PDT 24
Finished Jun 21 04:55:36 PM PDT 24
Peak memory 206000 kb
Host smart-ffdb55f4-3503-404a-b383-0239a69a1ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71854
6873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.718546873
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.3264702829
Short name T2371
Test name
Test status
Simulation time 149199170 ps
CPU time 0.77 seconds
Started Jun 21 04:55:31 PM PDT 24
Finished Jun 21 04:55:33 PM PDT 24
Peak memory 205920 kb
Host smart-dd627a1d-6c00-4ef7-8df6-0454f569fbfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32647
02829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.3264702829
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2104384874
Short name T2211
Test name
Test status
Simulation time 176916482 ps
CPU time 0.84 seconds
Started Jun 21 04:55:30 PM PDT 24
Finished Jun 21 04:55:33 PM PDT 24
Peak memory 205928 kb
Host smart-d059bfb7-db19-474b-88ad-8d1a78776377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21043
84874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2104384874
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1201086681
Short name T1343
Test name
Test status
Simulation time 190839627 ps
CPU time 0.83 seconds
Started Jun 21 04:55:31 PM PDT 24
Finished Jun 21 04:55:33 PM PDT 24
Peak memory 206024 kb
Host smart-2b135f54-14c5-4f96-9bfb-d001307a39b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12010
86681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1201086681
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1037748053
Short name T1251
Test name
Test status
Simulation time 150492570 ps
CPU time 0.83 seconds
Started Jun 21 04:55:29 PM PDT 24
Finished Jun 21 04:55:31 PM PDT 24
Peak memory 206020 kb
Host smart-b04643dc-f6e2-4e99-8d37-888db7ee2cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10377
48053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1037748053
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.2730787986
Short name T1461
Test name
Test status
Simulation time 181130898 ps
CPU time 0.87 seconds
Started Jun 21 04:55:31 PM PDT 24
Finished Jun 21 04:55:33 PM PDT 24
Peak memory 205944 kb
Host smart-0dabf89f-6f35-4099-813e-e58868074991
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2730787986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.2730787986
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.126580692
Short name T994
Test name
Test status
Simulation time 157160122 ps
CPU time 0.78 seconds
Started Jun 21 04:55:34 PM PDT 24
Finished Jun 21 04:55:36 PM PDT 24
Peak memory 206048 kb
Host smart-bb12a442-e32f-4f51-ae7a-0c2702df1e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12658
0692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.126580692
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1522778062
Short name T33
Test name
Test status
Simulation time 68725648 ps
CPU time 0.71 seconds
Started Jun 21 04:55:34 PM PDT 24
Finished Jun 21 04:55:36 PM PDT 24
Peak memory 206012 kb
Host smart-32af4bab-97e2-476f-aa8d-d8e517acf0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15227
78062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1522778062
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2288183693
Short name T244
Test name
Test status
Simulation time 7313236883 ps
CPU time 15.1 seconds
Started Jun 21 04:55:29 PM PDT 24
Finished Jun 21 04:55:45 PM PDT 24
Peak memory 206280 kb
Host smart-09e727e5-309c-479f-b5dc-7e43afdecd2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22881
83693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2288183693
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.2797829664
Short name T442
Test name
Test status
Simulation time 196400532 ps
CPU time 0.85 seconds
Started Jun 21 04:55:29 PM PDT 24
Finished Jun 21 04:55:31 PM PDT 24
Peak memory 205972 kb
Host smart-993c7d81-10a4-41d2-b36d-656d3b12b9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27978
29664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.2797829664
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1166980067
Short name T765
Test name
Test status
Simulation time 174884203 ps
CPU time 0.85 seconds
Started Jun 21 04:55:32 PM PDT 24
Finished Jun 21 04:55:34 PM PDT 24
Peak memory 206080 kb
Host smart-3ab18c62-c988-4919-86d0-776cec3c062b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11669
80067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1166980067
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.4131082193
Short name T6
Test name
Test status
Simulation time 15371954069 ps
CPU time 328.79 seconds
Started Jun 21 04:55:30 PM PDT 24
Finished Jun 21 05:01:01 PM PDT 24
Peak memory 206244 kb
Host smart-994b11c6-3c9e-40b4-9f76-4faa1dda1854
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4131082193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.4131082193
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1076364070
Short name T1446
Test name
Test status
Simulation time 19446609615 ps
CPU time 156.82 seconds
Started Jun 21 04:55:29 PM PDT 24
Finished Jun 21 04:58:06 PM PDT 24
Peak memory 206296 kb
Host smart-cf51ba07-fb3b-4f70-8244-1cc393363381
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1076364070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1076364070
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.2156532128
Short name T2054
Test name
Test status
Simulation time 19721757979 ps
CPU time 123.81 seconds
Started Jun 21 04:55:28 PM PDT 24
Finished Jun 21 04:57:33 PM PDT 24
Peak memory 206244 kb
Host smart-8fefcfcf-2d7f-415f-8680-e14f2569d034
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2156532128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.2156532128
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.795446496
Short name T618
Test name
Test status
Simulation time 234522998 ps
CPU time 0.9 seconds
Started Jun 21 04:55:30 PM PDT 24
Finished Jun 21 04:55:32 PM PDT 24
Peak memory 206036 kb
Host smart-69d96c53-4fe1-4440-9907-2ef435985878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79544
6496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.795446496
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.1464030411
Short name T2362
Test name
Test status
Simulation time 211235103 ps
CPU time 0.86 seconds
Started Jun 21 04:55:31 PM PDT 24
Finished Jun 21 04:55:33 PM PDT 24
Peak memory 205940 kb
Host smart-15283c3d-2f51-43f9-bb1e-116cc04a391d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14640
30411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.1464030411
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.3794010374
Short name T1518
Test name
Test status
Simulation time 199139996 ps
CPU time 0.81 seconds
Started Jun 21 04:55:34 PM PDT 24
Finished Jun 21 04:55:36 PM PDT 24
Peak memory 206028 kb
Host smart-21ba2243-8d63-4fa0-b649-0ee5307e8cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37940
10374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.3794010374
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1100747805
Short name T1102
Test name
Test status
Simulation time 149237233 ps
CPU time 0.77 seconds
Started Jun 21 04:55:30 PM PDT 24
Finished Jun 21 04:55:32 PM PDT 24
Peak memory 205964 kb
Host smart-8549838a-b6db-42ae-80a3-bfa41f9dc23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11007
47805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1100747805
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2598499192
Short name T836
Test name
Test status
Simulation time 161857935 ps
CPU time 0.8 seconds
Started Jun 21 04:55:33 PM PDT 24
Finished Jun 21 04:55:34 PM PDT 24
Peak memory 206072 kb
Host smart-b809e914-8022-46e7-a36f-1f7d0a2649ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25984
99192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2598499192
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2710308856
Short name T594
Test name
Test status
Simulation time 253853279 ps
CPU time 0.98 seconds
Started Jun 21 04:55:22 PM PDT 24
Finished Jun 21 04:55:24 PM PDT 24
Peak memory 206028 kb
Host smart-126909f1-22da-45d1-a3d5-5f746a8a42eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27103
08856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2710308856
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.1244286800
Short name T2122
Test name
Test status
Simulation time 7059527812 ps
CPU time 53.14 seconds
Started Jun 21 04:55:31 PM PDT 24
Finished Jun 21 04:56:26 PM PDT 24
Peak memory 206204 kb
Host smart-6a23acab-1e56-4464-abd6-e384ea5fbec4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1244286800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.1244286800
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.80088499
Short name T810
Test name
Test status
Simulation time 183275576 ps
CPU time 0.82 seconds
Started Jun 21 04:55:31 PM PDT 24
Finished Jun 21 04:55:33 PM PDT 24
Peak memory 206024 kb
Host smart-2e363d46-cd71-43c4-8718-cb27003123de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80088
499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.80088499
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2029053325
Short name T1768
Test name
Test status
Simulation time 151094605 ps
CPU time 0.81 seconds
Started Jun 21 04:55:30 PM PDT 24
Finished Jun 21 04:55:33 PM PDT 24
Peak memory 205928 kb
Host smart-fdc3e552-7b8b-4768-a83f-61595bcfdf6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20290
53325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2029053325
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.2514836118
Short name T603
Test name
Test status
Simulation time 10725743031 ps
CPU time 76.98 seconds
Started Jun 21 04:55:29 PM PDT 24
Finished Jun 21 04:56:46 PM PDT 24
Peak memory 206208 kb
Host smart-3d2cf322-2bc0-4e1a-93f6-2a80876a151a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25148
36118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.2514836118
Directory /workspace/9.usbdev_streaming_out/latest
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