Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	121305	1		T1	2		T2	2		T3	2
all_values[1]	121305	1		T1	2		T2	2		T3	2
all_values[2]	121305	1		T1	2		T2	2		T3	2
all_values[3]	121305	1		T1	2		T2	2		T3	2
all_values[4]	121305	1		T1	2		T2	2		T3	2
all_values[5]	121305	1		T1	2		T2	2		T3	2
all_values[6]	121305	1		T1	2		T2	2		T3	2
all_values[7]	121305	1		T1	2		T2	2		T3	2
all_values[8]	121305	1		T1	2		T2	2		T3	2
all_values[9]	121305	1		T1	2		T2	2		T3	2
all_values[10]	121305	1		T1	2		T2	2		T3	2
all_values[11]	121305	1		T1	2		T2	2		T3	2
all_values[12]	121305	1		T1	2		T2	2		T3	2
all_values[13]	121305	1		T1	2		T2	2		T3	2
all_values[14]	121305	1		T1	2		T2	2		T3	2
all_values[15]	121305	1		T1	2		T2	2		T3	2
all_values[16]	121305	1		T1	2		T2	2		T3	2
all_values[17]	121305	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2175943	1		T1	34		T2	34		T3	36
auto[1]	7547	1		T1	2		T2	2		T7	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2178674	1		T1	36		T2	36		T3	36
auto[1]	4816	1		T198	70		T195	84		T196	125

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	120370	1		T1	2		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	117	1		T198	4		T195	3		T196	5
all_values[0]	auto[1]	auto[0]	669	1		T18	4		T49	3		T50	3
all_values[0]	auto[1]	auto[1]	149	1		T198	1		T195	2		T196	3
all_values[1]	auto[0]	auto[0]	118837	1		T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	136	1		T198	1		T195	3		T196	6
all_values[1]	auto[1]	auto[0]	2214	1		T7	2		T17	16		T20	3
all_values[1]	auto[1]	auto[1]	118	1		T198	4		T195	2		T196	1
all_values[2]	auto[0]	auto[0]	120902	1		T1	2		T3	2		T4	2
all_values[2]	auto[0]	auto[1]	161	1		T198	4		T195	5		T196	3
all_values[2]	auto[1]	auto[0]	126	1		T2	2		T40	2		T45	2
all_values[2]	auto[1]	auto[1]	116	1		T198	1		T196	5		T253	3
all_values[3]	auto[0]	auto[0]	119526	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	134	1		T195	1		T196	5		T197	3
all_values[3]	auto[1]	auto[0]	1520	1		T71	1485		T198	5		T197	1
all_values[3]	auto[1]	auto[1]	125	1		T195	4		T196	3		T253	4
all_values[4]	auto[0]	auto[0]	121006	1		T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	113	1		T195	1		T196	5		T197	3
all_values[4]	auto[1]	auto[0]	29	1		T72	2		T254	1		T255	1
all_values[4]	auto[1]	auto[1]	157	1		T198	5		T195	4		T196	3
all_values[5]	auto[0]	auto[0]	121008	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	141	1		T198	2		T195	1		T196	5
all_values[5]	auto[1]	auto[0]	40	1		T256	1		T253	5		T257	1
all_values[5]	auto[1]	auto[1]	116	1		T198	3		T195	4		T196	3
all_values[6]	auto[0]	auto[0]	121008	1		T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	139	1		T198	1		T195	2		T196	5
all_values[6]	auto[1]	auto[0]	26	1		T196	1		T256	1		T258	3
all_values[6]	auto[1]	auto[1]	132	1		T198	4		T195	3		T196	2
all_values[7]	auto[0]	auto[0]	120999	1		T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	151	1		T198	4		T195	3		T196	1
all_values[7]	auto[1]	auto[0]	24	1		T52	2		T53	2		T54	2
all_values[7]	auto[1]	auto[1]	131	1		T198	1		T195	1		T196	6
all_values[8]	auto[0]	auto[0]	120996	1		T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	135	1		T198	3		T195	1		T196	3
all_values[8]	auto[1]	auto[0]	42	1		T58	11		T195	1		T196	3
all_values[8]	auto[1]	auto[1]	132	1		T198	2		T195	3		T197	3
all_values[9]	auto[0]	auto[0]	120971	1		T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	141	1		T195	3		T196	5		T253	6
all_values[9]	auto[1]	auto[0]	52	1		T68	5		T69	5		T70	5
all_values[9]	auto[1]	auto[1]	141	1		T198	3		T195	1		T196	2
all_values[10]	auto[0]	auto[0]	121020	1		T1	2		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	131	1		T198	3		T195	1		T196	3
all_values[10]	auto[1]	auto[0]	28	1		T198	2		T196	2		T256	3
all_values[10]	auto[1]	auto[1]	126	1		T195	4		T196	2		T197	2
all_values[11]	auto[0]	auto[0]	120917	1		T2	2		T3	2		T4	2
all_values[11]	auto[0]	auto[1]	113	1		T198	3		T195	1		T196	2
all_values[11]	auto[1]	auto[0]	129	1		T1	2		T76	2		T77	2
all_values[11]	auto[1]	auto[1]	146	1		T198	2		T195	3		T196	4
all_values[12]	auto[0]	auto[0]	120997	1		T1	2		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	136	1		T198	2		T195	2		T196	6
all_values[12]	auto[1]	auto[0]	26	1		T254	1		T257	1		T259	5
all_values[12]	auto[1]	auto[1]	146	1		T198	3		T195	3		T196	1
all_values[13]	auto[0]	auto[0]	121014	1		T1	2		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	118	1		T195	2		T196	5		T197	3
all_values[13]	auto[1]	auto[0]	33	1		T196	1		T197	1		T254	1
all_values[13]	auto[1]	auto[1]	140	1		T195	3		T196	1		T197	1
all_values[14]	auto[0]	auto[0]	121014	1		T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	124	1		T198	4		T195	1		T196	6
all_values[14]	auto[1]	auto[0]	20	1		T256	3		T260	5		T261	1
all_values[14]	auto[1]	auto[1]	147	1		T195	3		T196	2		T197	4
all_values[15]	auto[0]	auto[0]	121010	1		T1	2		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	128	1		T196	5		T197	3		T256	1
all_values[15]	auto[1]	auto[0]	23	1		T197	1		T253	1		T260	5
all_values[15]	auto[1]	auto[1]	144	1		T195	4		T196	3		T197	1
all_values[16]	auto[0]	auto[0]	120987	1		T1	2		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	117	1		T198	2		T196	3		T197	3
all_values[16]	auto[1]	auto[0]	52	1		T73	8		T74	8		T75	8
all_values[16]	auto[1]	auto[1]	149	1		T198	3		T195	5		T196	4
all_values[17]	auto[0]	auto[0]	121005	1		T1	2		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	121	1		T198	5		T195	2		T196	5
all_values[17]	auto[1]	auto[0]	34	1		T59	2		T60	2		T196	1
all_values[17]	auto[1]	auto[1]	145	1		T195	3		T196	2		T197	3