Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	121305	1		T1	2		T2	2		T3	2
all_pins[1]	121305	1		T1	2		T2	2		T3	2
all_pins[2]	121305	1		T1	2		T2	2		T3	2
all_pins[3]	121305	1		T1	2		T2	2		T3	2
all_pins[4]	121305	1		T1	2		T2	2		T3	2
all_pins[5]	121305	1		T1	2		T2	2		T3	2
all_pins[6]	121305	1		T1	2		T2	2		T3	2
all_pins[7]	121305	1		T1	2		T2	2		T3	2
all_pins[8]	121305	1		T1	2		T2	2		T3	2
all_pins[9]	121305	1		T1	2		T2	2		T3	2
all_pins[10]	121305	1		T1	2		T2	2		T3	2
all_pins[11]	121305	1		T1	2		T2	2		T3	2
all_pins[12]	121305	1		T1	2		T2	2		T3	2
all_pins[13]	121305	1		T1	2		T2	2		T3	2
all_pins[14]	121305	1		T1	2		T2	2		T3	2
all_pins[15]	121305	1		T1	2		T2	2		T3	2
all_pins[16]	121305	1		T1	2		T2	2		T3	2
all_pins[17]	121305	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2180856	1		T1	35		T2	35		T3	36
values[0x1]	2634	1		T1	1		T2	1		T7	1
transitions[0x0=>0x1]	2294	1		T1	1		T2	1		T7	1
transitions[0x1=>0x0]	2309	1		T1	1		T2	1		T7	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	121196	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	109	1		T18	1		T262	1		T263	1
all_pins[0]	transitions[0x0=>0x1]	88	1		T18	1		T262	1		T263	1
all_pins[0]	transitions[0x1=>0x0]	1344	1		T7	1		T17	13		T20	1
all_pins[1]	values[0x0]	119940	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	1365	1		T7	1		T17	13		T20	1
all_pins[1]	transitions[0x0=>0x1]	1352	1		T7	1		T17	13		T20	1
all_pins[1]	transitions[0x1=>0x0]	97	1		T2	1		T40	1		T45	1
all_pins[2]	values[0x0]	121195	1		T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	110	1		T2	1		T40	1		T45	1
all_pins[2]	transitions[0x0=>0x1]	92	1		T2	1		T40	1		T45	1
all_pins[2]	transitions[0x1=>0x0]	44	1		T71	1		T195	3		T196	1
all_pins[3]	values[0x0]	121243	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	62	1		T71	1		T195	3		T196	3
all_pins[3]	transitions[0x0=>0x1]	37	1		T71	1		T195	1		T196	1
all_pins[3]	transitions[0x1=>0x0]	58	1		T72	1		T198	3		T195	1
all_pins[4]	values[0x0]	121222	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	83	1		T72	1		T198	3		T195	3
all_pins[4]	transitions[0x0=>0x1]	65	1		T72	1		T198	1		T195	3
all_pins[4]	transitions[0x1=>0x0]	45	1		T195	1		T254	1		T257	2
all_pins[5]	values[0x0]	121242	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	63	1		T198	2		T195	1		T196	1
all_pins[5]	transitions[0x0=>0x1]	40	1		T195	1		T196	1		T264	1
all_pins[5]	transitions[0x1=>0x0]	31	1		T198	1		T195	2		T196	1
all_pins[6]	values[0x0]	121251	1		T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	54	1		T198	3		T195	2		T196	1
all_pins[6]	transitions[0x0=>0x1]	44	1		T198	3		T195	2		T196	1
all_pins[6]	transitions[0x1=>0x0]	49	1		T52	1		T53	1		T54	1
all_pins[7]	values[0x0]	121246	1		T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	59	1		T52	1		T53	1		T54	1
all_pins[7]	transitions[0x0=>0x1]	46	1		T52	1		T53	1		T54	1
all_pins[7]	transitions[0x1=>0x0]	38	1		T58	1		T195	1		T256	1
all_pins[8]	values[0x0]	121254	1		T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	51	1		T58	1		T198	1		T195	1
all_pins[8]	transitions[0x0=>0x1]	41	1		T58	1		T198	1		T195	1
all_pins[8]	transitions[0x1=>0x0]	67	1		T68	2		T69	2		T70	2
all_pins[9]	values[0x0]	121228	1		T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	77	1		T68	2		T69	2		T70	2
all_pins[9]	transitions[0x0=>0x1]	55	1		T68	2		T69	2		T70	2
all_pins[9]	transitions[0x1=>0x0]	39	1		T197	1		T261	1		T255	2
all_pins[10]	values[0x0]	121244	1		T1	2		T2	2		T3	2
all_pins[10]	values[0x1]	61	1		T195	1		T196	1		T197	1
all_pins[10]	transitions[0x0=>0x1]	41	1		T195	1		T261	1		T255	2
all_pins[10]	transitions[0x1=>0x0]	103	1		T1	1		T76	1		T77	1
all_pins[11]	values[0x0]	121182	1		T1	1		T2	2		T3	2
all_pins[11]	values[0x1]	123	1		T1	1		T76	1		T77	1
all_pins[11]	transitions[0x0=>0x1]	101	1		T1	1		T76	1		T77	1
all_pins[11]	transitions[0x1=>0x0]	48	1		T195	2		T197	2		T256	1
all_pins[12]	values[0x0]	121235	1		T1	2		T2	2		T3	2
all_pins[12]	values[0x1]	70	1		T195	2		T197	2		T256	1
all_pins[12]	transitions[0x0=>0x1]	52	1		T197	2		T253	1		T257	5
all_pins[12]	transitions[0x1=>0x0]	47	1		T196	1		T253	1		T260	3
all_pins[13]	values[0x0]	121240	1		T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	65	1		T195	2		T196	1		T256	1
all_pins[13]	transitions[0x0=>0x1]	43	1		T256	1		T253	1		T260	3
all_pins[13]	transitions[0x1=>0x0]	53	1		T197	1		T254	2		T257	1
all_pins[14]	values[0x0]	121230	1		T1	2		T2	2		T3	2
all_pins[14]	values[0x1]	75	1		T195	2		T196	1		T197	1
all_pins[14]	transitions[0x0=>0x1]	54	1		T196	1		T197	1		T254	1
all_pins[14]	transitions[0x1=>0x0]	38	1		T195	1		T196	3		T256	1
all_pins[15]	values[0x0]	121246	1		T1	2		T2	2		T3	2
all_pins[15]	values[0x1]	59	1		T195	3		T196	3		T256	1
all_pins[15]	transitions[0x0=>0x1]	41	1		T196	2		T256	1		T261	1
all_pins[15]	transitions[0x1=>0x0]	62	1		T73	4		T74	4		T75	4
all_pins[16]	values[0x0]	121225	1		T1	2		T2	2		T3	2
all_pins[16]	values[0x1]	80	1		T73	4		T74	4		T75	4
all_pins[16]	transitions[0x0=>0x1]	62	1		T73	4		T74	4		T75	4
all_pins[16]	transitions[0x1=>0x0]	50	1		T59	1		T60	1		T196	1
all_pins[17]	values[0x0]	121237	1		T1	2		T2	2		T3	2
all_pins[17]	values[0x1]	68	1		T59	1		T60	1		T195	1
all_pins[17]	transitions[0x0=>0x1]	40	1		T59	1		T60	1		T196	2
all_pins[17]	transitions[0x1=>0x0]	96	1		T18	1		T262	1		T263	1