Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1		T198	4		T195	4		T196	7
all_values[1]	272	1		T198	4		T195	4		T196	7
all_values[2]	272	1		T198	4		T195	4		T196	7
all_values[3]	272	1		T198	4		T195	4		T196	7
all_values[4]	272	1		T198	4		T195	4		T196	7
all_values[5]	272	1		T198	4		T195	4		T196	7
all_values[6]	272	1		T198	4		T195	4		T196	7
all_values[7]	272	1		T198	4		T195	4		T196	7
all_values[8]	272	1		T198	4		T195	4		T196	7
all_values[9]	272	1		T198	4		T195	4		T196	7
all_values[10]	272	1		T198	4		T195	4		T196	7
all_values[11]	272	1		T198	4		T195	4		T196	7
all_values[12]	272	1		T198	4		T195	4		T196	7
all_values[13]	272	1		T198	4		T195	4		T196	7
all_values[14]	272	1		T198	4		T195	4		T196	7
all_values[15]	272	1		T198	4		T195	4		T196	7
all_values[16]	272	1		T198	4		T195	4		T196	7
all_values[17]	272	1		T198	4		T195	4		T196	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2635	1		T198	47		T195	41		T196	62
auto[1]	2261	1		T198	25		T195	31		T196	64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	904	1		T198	17		T195	6		T196	19
auto[1]	3992	1		T198	55		T195	66		T196	107

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2873	1		T198	44		T195	33		T196	71
auto[1]	2023	1		T198	28		T195	39		T196	55

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	35	1		T256	4		T254	1		T255	2
all_values[0]	auto[0]	auto[0]	auto[1]	56	1		T198	3		T195	1		T196	4
all_values[0]	auto[0]	auto[1]	auto[0]	15	1		T253	2		T254	1		T261	4
all_values[0]	auto[0]	auto[1]	auto[1]	60	1		T196	1		T253	2		T254	3
all_values[0]	auto[1]	auto[0]	auto[1]	57	1		T198	1		T195	1		T196	2
all_values[0]	auto[1]	auto[1]	auto[1]	49	1		T195	2		T197	1		T254	2
all_values[1]	auto[0]	auto[0]	auto[0]	45	1		T196	1		T197	1		T253	2
all_values[1]	auto[0]	auto[0]	auto[1]	54	1		T195	1		T196	2		T256	2
all_values[1]	auto[0]	auto[1]	auto[0]	20	1		T197	1		T260	2		T257	1
all_values[1]	auto[0]	auto[1]	auto[1]	47	1		T198	2		T195	1		T196	1
all_values[1]	auto[1]	auto[0]	auto[1]	57	1		T198	1		T195	1		T196	3
all_values[1]	auto[1]	auto[1]	auto[1]	49	1		T198	1		T195	1		T197	1
all_values[2]	auto[0]	auto[0]	auto[0]	19	1		T197	1		T256	1		T253	2
all_values[2]	auto[0]	auto[0]	auto[1]	67	1		T198	2		T195	1		T197	1
all_values[2]	auto[0]	auto[1]	auto[0]	22	1		T256	1		T261	3		T265	3
all_values[2]	auto[0]	auto[1]	auto[1]	44	1		T196	2		T260	2		T254	1
all_values[2]	auto[1]	auto[0]	auto[1]	67	1		T198	1		T195	3		T196	3
all_values[2]	auto[1]	auto[1]	auto[1]	53	1		T198	1		T196	2		T197	1
all_values[3]	auto[0]	auto[0]	auto[0]	36	1		T198	1		T197	2		T256	1
all_values[3]	auto[0]	auto[0]	auto[1]	60	1		T196	1		T197	1		T256	1
all_values[3]	auto[0]	auto[1]	auto[0]	24	1		T198	3		T256	1		T254	2
all_values[3]	auto[0]	auto[1]	auto[1]	46	1		T195	1		T196	3		T253	2
all_values[3]	auto[1]	auto[0]	auto[1]	57	1		T195	1		T196	1		T256	1
all_values[3]	auto[1]	auto[1]	auto[1]	49	1		T195	2		T196	2		T197	1
all_values[4]	auto[0]	auto[0]	auto[0]	30	1		T256	1		T253	1		T260	2
all_values[4]	auto[0]	auto[0]	auto[1]	51	1		T195	1		T196	3		T197	1
all_values[4]	auto[0]	auto[1]	auto[0]	17	1		T254	1		T258	2		T266	1
all_values[4]	auto[0]	auto[1]	auto[1]	62	1		T198	2		T195	1		T196	1
all_values[4]	auto[1]	auto[0]	auto[1]	55	1		T198	1		T195	2		T197	1
all_values[4]	auto[1]	auto[1]	auto[1]	57	1		T198	1		T196	3		T197	1
all_values[5]	auto[0]	auto[0]	auto[0]	33	1		T256	1		T253	4		T260	1
all_values[5]	auto[0]	auto[0]	auto[1]	49	1		T196	2		T197	2		T256	2
all_values[5]	auto[0]	auto[1]	auto[0]	28	1		T253	3		T257	1		T258	1
all_values[5]	auto[0]	auto[1]	auto[1]	52	1		T198	1		T195	2		T196	2
all_values[5]	auto[1]	auto[0]	auto[1]	61	1		T198	2		T195	1		T196	1
all_values[5]	auto[1]	auto[1]	auto[1]	49	1		T198	1		T195	1		T196	2
all_values[6]	auto[0]	auto[0]	auto[0]	30	1		T256	1		T253	1		T260	1
all_values[6]	auto[0]	auto[0]	auto[1]	50	1		T196	3		T197	1		T256	1
all_values[6]	auto[0]	auto[1]	auto[0]	18	1		T196	1		T256	1		T258	3
all_values[6]	auto[0]	auto[1]	auto[1]	59	1		T198	1		T195	1		T197	2
all_values[6]	auto[1]	auto[0]	auto[1]	70	1		T198	1		T195	3		T196	1
all_values[6]	auto[1]	auto[1]	auto[1]	45	1		T198	2		T196	2		T253	2
all_values[7]	auto[0]	auto[0]	auto[0]	27	1		T195	1		T256	4		T257	2
all_values[7]	auto[0]	auto[0]	auto[1]	70	1		T198	2		T195	1		T196	1
all_values[7]	auto[0]	auto[1]	auto[0]	10	1		T196	1		T260	1		T267	1
all_values[7]	auto[0]	auto[1]	auto[1]	48	1		T196	3		T253	1		T261	4
all_values[7]	auto[1]	auto[0]	auto[1]	67	1		T198	2		T197	1		T253	3
all_values[7]	auto[1]	auto[1]	auto[1]	50	1		T195	2		T196	2		T197	1
all_values[8]	auto[0]	auto[0]	auto[0]	31	1		T195	1		T196	3		T254	2
all_values[8]	auto[0]	auto[0]	auto[1]	60	1		T198	1		T196	1		T197	2
all_values[8]	auto[0]	auto[1]	auto[0]	19	1		T196	2		T254	3		T258	1
all_values[8]	auto[0]	auto[1]	auto[1]	55	1		T198	1		T195	1		T197	1
all_values[8]	auto[1]	auto[0]	auto[1]	67	1		T198	2		T195	2		T197	1
all_values[8]	auto[1]	auto[1]	auto[1]	40	1		T196	1		T253	2		T257	1
all_values[9]	auto[0]	auto[0]	auto[0]	23	1		T198	1		T195	1		T197	1
all_values[9]	auto[0]	auto[0]	auto[1]	56	1		T195	1		T196	2		T253	3
all_values[9]	auto[0]	auto[1]	auto[0]	14	1		T198	1		T196	1		T256	3
all_values[9]	auto[0]	auto[1]	auto[1]	56	1		T198	1		T196	1		T197	1
all_values[9]	auto[1]	auto[0]	auto[1]	74	1		T196	1		T253	3		T260	2
all_values[9]	auto[1]	auto[1]	auto[1]	49	1		T198	1		T195	2		T196	2
all_values[10]	auto[0]	auto[0]	auto[0]	38	1		T198	1		T256	2		T255	2
all_values[10]	auto[0]	auto[0]	auto[1]	53	1		T198	1		T196	1		T197	1
all_values[10]	auto[0]	auto[1]	auto[0]	22	1		T198	1		T196	3		T256	2
all_values[10]	auto[0]	auto[1]	auto[1]	61	1		T195	2		T196	1		T260	2
all_values[10]	auto[1]	auto[0]	auto[1]	49	1		T198	1		T195	1		T197	1
all_values[10]	auto[1]	auto[1]	auto[1]	49	1		T195	1		T196	2		T197	2
all_values[11]	auto[0]	auto[0]	auto[0]	36	1		T195	1		T256	1		T254	2
all_values[11]	auto[0]	auto[0]	auto[1]	46	1		T198	1		T195	1		T197	1
all_values[11]	auto[0]	auto[1]	auto[0]	21	1		T196	2		T256	1		T260	4
all_values[11]	auto[0]	auto[1]	auto[1]	57	1		T198	1		T195	1		T196	1
all_values[11]	auto[1]	auto[0]	auto[1]	59	1		T198	2		T195	1		T196	2
all_values[11]	auto[1]	auto[1]	auto[1]	53	1		T196	2		T197	1		T256	1
all_values[12]	auto[0]	auto[0]	auto[0]	19	1		T196	1		T197	1		T260	1
all_values[12]	auto[0]	auto[0]	auto[1]	53	1		T198	1		T195	1		T196	3
all_values[12]	auto[0]	auto[1]	auto[0]	18	1		T254	1		T257	1		T259	3
all_values[12]	auto[0]	auto[1]	auto[1]	61	1		T198	2		T195	1		T197	1
all_values[12]	auto[1]	auto[0]	auto[1]	68	1		T198	1		T195	2		T196	2
all_values[12]	auto[1]	auto[1]	auto[1]	53	1		T196	1		T197	1		T253	2
all_values[13]	auto[0]	auto[0]	auto[0]	37	1		T198	4		T197	1		T255	1
all_values[13]	auto[0]	auto[0]	auto[1]	51	1		T195	1		T196	1		T197	1
all_values[13]	auto[0]	auto[1]	auto[0]	22	1		T196	2		T254	1		T266	1
all_values[13]	auto[0]	auto[1]	auto[1]	59	1		T195	1		T197	1		T253	4
all_values[13]	auto[1]	auto[0]	auto[1]	56	1		T195	2		T196	2		T256	1
all_values[13]	auto[1]	auto[1]	auto[1]	47	1		T196	2		T197	1		T256	1
all_values[14]	auto[0]	auto[0]	auto[0]	31	1		T198	1		T195	1		T197	1
all_values[14]	auto[0]	auto[0]	auto[1]	57	1		T198	1		T196	4		T253	3
all_values[14]	auto[0]	auto[1]	auto[0]	15	1		T256	2		T260	4		T261	1
all_values[14]	auto[0]	auto[1]	auto[1]	56	1		T195	1		T197	2		T254	3
all_values[14]	auto[1]	auto[0]	auto[1]	63	1		T198	2		T195	2		T196	1
all_values[14]	auto[1]	auto[1]	auto[1]	50	1		T196	2		T254	1		T266	3
all_values[15]	auto[0]	auto[0]	auto[0]	32	1		T198	4		T195	1		T197	1
all_values[15]	auto[0]	auto[0]	auto[1]	50	1		T196	2		T197	1		T253	1
all_values[15]	auto[0]	auto[1]	auto[0]	14	1		T253	1		T260	4		T254	2
all_values[15]	auto[0]	auto[1]	auto[1]	53	1		T195	1		T196	1		T256	1
all_values[15]	auto[1]	auto[0]	auto[1]	54	1		T196	1		T256	1		T253	2
all_values[15]	auto[1]	auto[1]	auto[1]	69	1		T195	2		T196	3		T197	2
all_values[16]	auto[0]	auto[0]	auto[0]	29	1		T196	1		T197	2		T256	2
all_values[16]	auto[0]	auto[0]	auto[1]	45	1		T196	1		T197	1		T253	1
all_values[16]	auto[0]	auto[1]	auto[0]	23	1		T253	1		T255	1		T266	2
all_values[16]	auto[0]	auto[1]	auto[1]	60	1		T198	1		T195	2		T196	2
all_values[16]	auto[1]	auto[0]	auto[1]	54	1		T198	2		T195	1		T196	1
all_values[16]	auto[1]	auto[1]	auto[1]	61	1		T198	1		T195	1		T196	2
all_values[17]	auto[0]	auto[0]	auto[0]	32	1		T197	1		T253	2		T260	1
all_values[17]	auto[0]	auto[0]	auto[1]	48	1		T198	3		T195	1		T196	2
all_values[17]	auto[0]	auto[1]	auto[0]	19	1		T196	1		T197	1		T261	1
all_values[17]	auto[0]	auto[1]	auto[1]	57	1		T195	1		T197	1		T256	1
all_values[17]	auto[1]	auto[0]	auto[1]	61	1		T198	1		T195	2		T196	2
all_values[17]	auto[1]	auto[1]	auto[1]	55	1		T196	2		T253	2		T260	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal