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LINE 9294
EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T6,T82 |
1 | 1 | 0 | Covered | T191,T215,T217 |
1 | 1 | 1 | Covered | T26,T27,T28 |
LINE 9313
EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T215,T217,T218 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 9326
EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T6,T7 |
1 | 1 | 0 | Covered | T191,T215,T217 |
1 | 1 | 1 | Covered | T7,T8,T9 |
LINE 9329
EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T31,T6 |
1 | 1 | 0 | Covered | T191,T210,T214 |
1 | 1 | 1 | Covered | T31,T82,T89 |
LINE 9336
EXPRESSION (addr_hit[39] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T6,T82 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T189,T193,T194 |
LINE 9337
EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T6,T82 |
1 | 1 | 0 | Covered | T210,T215,T217 |
1 | 1 | 1 | Covered | T189,T193,T194 |
LINE 9350
EXPRESSION (addr_hit[40] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T6,T82 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T189,T193,T194 |
LINE 9351
EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T6,T82 |
1 | 1 | 0 | Covered | T191,T210,T215 |
1 | 1 | 1 | Covered | T189,T193,T194 |
LINE 9362
EXPRESSION (addr_hit[41] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T6,T82 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T189,T193,T194 |
LINE 9363
EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T6,T82 |
1 | 1 | 0 | Covered | T191,T215,T217 |
1 | 1 | 1 | Covered | T189,T193,T194 |
LINE 9368
EXPRESSION (addr_hit[42] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T6,T82 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T189,T193,T194 |
LINE 9369
EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T4,T6,T82 |
1 | 1 | 0 | Covered | T215,T216,T219 |
1 | 1 | 1 | Covered | T189,T193,T194 |
LINE 9881
EXPRESSION (reg_busy_sel | shadow_busy)
------1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T7,T8,T9 |