Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.57 97.84 93.72 97.44 75.00 96.25 98.17 96.58


Total test records in report: 2609
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T259 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1612308720 Jun 23 04:47:13 PM PDT 24 Jun 23 04:47:15 PM PDT 24 40146909 ps
T275 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1496874233 Jun 23 04:46:58 PM PDT 24 Jun 23 04:47:03 PM PDT 24 679140788 ps
T265 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1586626733 Jun 23 04:46:59 PM PDT 24 Jun 23 04:47:06 PM PDT 24 88508040 ps
T2512 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2178310482 Jun 23 04:47:05 PM PDT 24 Jun 23 04:47:08 PM PDT 24 252391599 ps
T2513 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.511118784 Jun 23 04:47:19 PM PDT 24 Jun 23 04:47:20 PM PDT 24 52683851 ps
T2514 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3722689842 Jun 23 04:48:44 PM PDT 24 Jun 23 04:48:47 PM PDT 24 505383556 ps
T2515 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.435179253 Jun 23 04:47:07 PM PDT 24 Jun 23 04:47:13 PM PDT 24 746315803 ps
T239 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3786578862 Jun 23 04:47:52 PM PDT 24 Jun 23 04:47:54 PM PDT 24 72258981 ps
T2516 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1060517909 Jun 23 04:46:56 PM PDT 24 Jun 23 04:47:06 PM PDT 24 858079289 ps
T2517 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.886476466 Jun 23 04:47:13 PM PDT 24 Jun 23 04:47:20 PM PDT 24 42831340 ps
T2518 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1585329869 Jun 23 04:47:23 PM PDT 24 Jun 23 04:47:25 PM PDT 24 78839627 ps
T2519 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3349372845 Jun 23 04:47:09 PM PDT 24 Jun 23 04:47:14 PM PDT 24 123142975 ps
T2520 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1380228339 Jun 23 04:47:24 PM PDT 24 Jun 23 04:47:25 PM PDT 24 53640147 ps
T2521 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2940722456 Jun 23 04:47:12 PM PDT 24 Jun 23 04:47:15 PM PDT 24 175703261 ps
T2522 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.4170546785 Jun 23 04:47:08 PM PDT 24 Jun 23 04:47:10 PM PDT 24 57098616 ps
T2523 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1426243669 Jun 23 04:47:16 PM PDT 24 Jun 23 04:47:18 PM PDT 24 38300603 ps
T2524 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2219986374 Jun 23 04:47:10 PM PDT 24 Jun 23 04:47:13 PM PDT 24 194928224 ps
T2525 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2029904398 Jun 23 04:46:57 PM PDT 24 Jun 23 04:47:01 PM PDT 24 323994952 ps
T2526 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.4014870638 Jun 23 04:47:01 PM PDT 24 Jun 23 04:47:03 PM PDT 24 133406487 ps
T2527 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.4055766365 Jun 23 04:46:47 PM PDT 24 Jun 23 04:46:48 PM PDT 24 93690970 ps
T267 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4096388634 Jun 23 04:47:11 PM PDT 24 Jun 23 04:47:13 PM PDT 24 50003479 ps
T2528 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1457262761 Jun 23 04:47:21 PM PDT 24 Jun 23 04:47:22 PM PDT 24 42536045 ps
T2529 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.482768491 Jun 23 04:46:48 PM PDT 24 Jun 23 04:46:51 PM PDT 24 167682438 ps
T272 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.390962004 Jun 23 04:46:58 PM PDT 24 Jun 23 04:47:03 PM PDT 24 553295804 ps
T2530 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3116732828 Jun 23 04:47:00 PM PDT 24 Jun 23 04:47:09 PM PDT 24 1290567726 ps
T2531 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.690799912 Jun 23 04:47:09 PM PDT 24 Jun 23 04:47:10 PM PDT 24 48988512 ps
T2532 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.700402746 Jun 23 04:47:26 PM PDT 24 Jun 23 04:47:29 PM PDT 24 555344802 ps
T2533 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3893501626 Jun 23 04:47:10 PM PDT 24 Jun 23 04:47:13 PM PDT 24 59671300 ps
T2534 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1125839911 Jun 23 04:47:29 PM PDT 24 Jun 23 04:47:30 PM PDT 24 112292914 ps
T2535 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.505678862 Jun 23 04:47:19 PM PDT 24 Jun 23 04:47:21 PM PDT 24 81403677 ps
T2536 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.872518867 Jun 23 04:47:06 PM PDT 24 Jun 23 04:47:08 PM PDT 24 127184694 ps
T2537 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1712299078 Jun 23 04:46:58 PM PDT 24 Jun 23 04:47:02 PM PDT 24 261795738 ps
T2538 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3260837406 Jun 23 04:46:54 PM PDT 24 Jun 23 04:46:57 PM PDT 24 369414399 ps
T2539 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1421253197 Jun 23 04:47:08 PM PDT 24 Jun 23 04:47:10 PM PDT 24 82572709 ps
T2540 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2306865963 Jun 23 04:47:05 PM PDT 24 Jun 23 04:47:06 PM PDT 24 55871806 ps
T2541 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2294757472 Jun 23 04:46:43 PM PDT 24 Jun 23 04:46:45 PM PDT 24 189583431 ps
T2542 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1942678642 Jun 23 04:47:04 PM PDT 24 Jun 23 04:47:07 PM PDT 24 171567501 ps
T2543 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.4189844429 Jun 23 04:47:10 PM PDT 24 Jun 23 04:47:12 PM PDT 24 111763375 ps
T2544 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.7393549 Jun 23 04:47:11 PM PDT 24 Jun 23 04:47:13 PM PDT 24 87956924 ps
T2545 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2363785812 Jun 23 04:47:09 PM PDT 24 Jun 23 04:47:11 PM PDT 24 64396677 ps
T2546 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1575551455 Jun 23 04:47:02 PM PDT 24 Jun 23 04:47:07 PM PDT 24 489789832 ps
T2547 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3559874668 Jun 23 04:47:31 PM PDT 24 Jun 23 04:47:32 PM PDT 24 33543894 ps
T2548 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2530381278 Jun 23 04:47:01 PM PDT 24 Jun 23 04:47:02 PM PDT 24 77771227 ps
T2549 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3179577333 Jun 23 04:47:08 PM PDT 24 Jun 23 04:47:10 PM PDT 24 62993295 ps
T2550 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.4199221912 Jun 23 04:47:28 PM PDT 24 Jun 23 04:47:29 PM PDT 24 49317613 ps
T2551 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2123545978 Jun 23 04:47:15 PM PDT 24 Jun 23 04:47:17 PM PDT 24 123701675 ps
T2552 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2064332670 Jun 23 04:47:09 PM PDT 24 Jun 23 04:47:13 PM PDT 24 274292626 ps
T2553 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.632954650 Jun 23 04:47:02 PM PDT 24 Jun 23 04:47:04 PM PDT 24 69638093 ps
T2554 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2270425209 Jun 23 04:47:20 PM PDT 24 Jun 23 04:47:24 PM PDT 24 265285602 ps
T2555 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2498948653 Jun 23 04:47:07 PM PDT 24 Jun 23 04:47:09 PM PDT 24 106808074 ps
T2556 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.798217162 Jun 23 04:47:20 PM PDT 24 Jun 23 04:47:21 PM PDT 24 55591812 ps
T2557 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.4282790726 Jun 23 04:47:09 PM PDT 24 Jun 23 04:47:11 PM PDT 24 172221885 ps
T2558 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2175297827 Jun 23 04:47:01 PM PDT 24 Jun 23 04:47:03 PM PDT 24 135161440 ps
T2559 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2249487158 Jun 23 04:47:13 PM PDT 24 Jun 23 04:47:15 PM PDT 24 65735825 ps
T2560 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3546582920 Jun 23 04:47:00 PM PDT 24 Jun 23 04:47:02 PM PDT 24 253691782 ps
T2561 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2168903504 Jun 23 04:47:11 PM PDT 24 Jun 23 04:47:13 PM PDT 24 37705277 ps
T2562 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3069588551 Jun 23 04:47:09 PM PDT 24 Jun 23 04:47:11 PM PDT 24 91708157 ps
T2563 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3193590681 Jun 23 04:47:14 PM PDT 24 Jun 23 04:47:16 PM PDT 24 53972963 ps
T2564 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1721621037 Jun 23 04:47:14 PM PDT 24 Jun 23 04:47:16 PM PDT 24 109196170 ps
T2565 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2495670621 Jun 23 04:47:11 PM PDT 24 Jun 23 04:47:13 PM PDT 24 33793315 ps
T2566 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1936420431 Jun 23 04:46:57 PM PDT 24 Jun 23 04:46:59 PM PDT 24 61091959 ps
T2567 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3913689520 Jun 23 04:47:06 PM PDT 24 Jun 23 04:47:08 PM PDT 24 74454611 ps
T2568 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3232657130 Jun 23 04:47:03 PM PDT 24 Jun 23 04:47:08 PM PDT 24 1144104609 ps
T2569 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1640601053 Jun 23 04:47:12 PM PDT 24 Jun 23 04:47:14 PM PDT 24 106464815 ps
T2570 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3232209671 Jun 23 04:47:08 PM PDT 24 Jun 23 04:47:10 PM PDT 24 71709345 ps
T2571 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2648121077 Jun 23 04:47:11 PM PDT 24 Jun 23 04:47:13 PM PDT 24 80797649 ps
T2572 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3045965065 Jun 23 04:47:07 PM PDT 24 Jun 23 04:47:09 PM PDT 24 79506650 ps
T2573 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1709324779 Jun 23 04:47:11 PM PDT 24 Jun 23 04:47:13 PM PDT 24 62462896 ps
T2574 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3118747924 Jun 23 04:47:25 PM PDT 24 Jun 23 04:47:26 PM PDT 24 30429999 ps
T2575 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1798715222 Jun 23 04:47:00 PM PDT 24 Jun 23 04:47:05 PM PDT 24 716115529 ps
T2576 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1891370337 Jun 23 04:46:45 PM PDT 24 Jun 23 04:46:47 PM PDT 24 229494193 ps
T2577 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1862709842 Jun 23 04:47:10 PM PDT 24 Jun 23 04:47:11 PM PDT 24 44050397 ps
T278 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3146357193 Jun 23 04:47:08 PM PDT 24 Jun 23 04:47:13 PM PDT 24 859361878 ps
T2578 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1752339260 Jun 23 04:46:56 PM PDT 24 Jun 23 04:46:58 PM PDT 24 42494301 ps
T2579 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.165300245 Jun 23 04:47:11 PM PDT 24 Jun 23 04:47:14 PM PDT 24 96907341 ps
T2580 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3950716740 Jun 23 04:47:01 PM PDT 24 Jun 23 04:47:05 PM PDT 24 726902425 ps
T2581 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3266634771 Jun 23 04:47:39 PM PDT 24 Jun 23 04:47:40 PM PDT 24 38253418 ps
T2582 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.583350574 Jun 23 04:47:10 PM PDT 24 Jun 23 04:47:12 PM PDT 24 82769992 ps
T268 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.339297627 Jun 23 04:47:10 PM PDT 24 Jun 23 04:47:16 PM PDT 24 868346912 ps
T2583 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1095672075 Jun 23 04:47:10 PM PDT 24 Jun 23 04:47:12 PM PDT 24 50794278 ps
T2584 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2673276064 Jun 23 04:46:59 PM PDT 24 Jun 23 04:47:01 PM PDT 24 116638379 ps
T2585 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.4032963716 Jun 23 04:47:03 PM PDT 24 Jun 23 04:47:05 PM PDT 24 42235744 ps
T2586 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1819756729 Jun 23 04:47:18 PM PDT 24 Jun 23 04:47:20 PM PDT 24 177092992 ps
T2587 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1748971632 Jun 23 04:47:03 PM PDT 24 Jun 23 04:47:07 PM PDT 24 296965276 ps
T2588 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1106889285 Jun 23 04:46:49 PM PDT 24 Jun 23 04:46:54 PM PDT 24 694282495 ps
T2589 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3434358833 Jun 23 04:47:13 PM PDT 24 Jun 23 04:47:15 PM PDT 24 71240504 ps
T2590 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3754441246 Jun 23 04:47:05 PM PDT 24 Jun 23 04:47:08 PM PDT 24 100693053 ps
T2591 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1413035457 Jun 23 04:47:06 PM PDT 24 Jun 23 04:47:08 PM PDT 24 158762745 ps
T2592 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2895862246 Jun 23 04:47:10 PM PDT 24 Jun 23 04:47:13 PM PDT 24 129244497 ps
T269 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1489449515 Jun 23 04:47:10 PM PDT 24 Jun 23 04:47:25 PM PDT 24 1187765321 ps
T2593 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.404846083 Jun 23 04:46:49 PM PDT 24 Jun 23 04:46:51 PM PDT 24 126161552 ps
T2594 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3464920514 Jun 23 04:47:11 PM PDT 24 Jun 23 04:47:14 PM PDT 24 76330299 ps
T2595 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3494215078 Jun 23 04:46:54 PM PDT 24 Jun 23 04:46:56 PM PDT 24 192806102 ps
T2596 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2840728148 Jun 23 04:47:52 PM PDT 24 Jun 23 04:47:54 PM PDT 24 107016125 ps
T2597 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2386616461 Jun 23 04:46:53 PM PDT 24 Jun 23 04:46:57 PM PDT 24 96042050 ps
T2598 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.361459530 Jun 23 04:47:30 PM PDT 24 Jun 23 04:47:31 PM PDT 24 45031186 ps
T2599 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.597953871 Jun 23 04:47:06 PM PDT 24 Jun 23 04:47:09 PM PDT 24 119169523 ps
T276 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3777827702 Jun 23 04:47:20 PM PDT 24 Jun 23 04:47:25 PM PDT 24 588140013 ps
T2600 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2122819271 Jun 23 04:47:19 PM PDT 24 Jun 23 04:47:21 PM PDT 24 90954842 ps
T2601 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2635436152 Jun 23 04:47:07 PM PDT 24 Jun 23 04:47:10 PM PDT 24 70863364 ps
T2602 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3236992716 Jun 23 04:47:04 PM PDT 24 Jun 23 04:47:07 PM PDT 24 129983040 ps
T2603 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.566953930 Jun 23 04:47:14 PM PDT 24 Jun 23 04:47:16 PM PDT 24 30980263 ps
T270 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.462247814 Jun 23 04:46:59 PM PDT 24 Jun 23 04:47:05 PM PDT 24 741416382 ps
T2604 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2842746767 Jun 23 04:47:15 PM PDT 24 Jun 23 04:47:18 PM PDT 24 164859152 ps
T2605 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1490355596 Jun 23 04:46:56 PM PDT 24 Jun 23 04:47:00 PM PDT 24 69653341 ps
T2606 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2984914060 Jun 23 04:47:15 PM PDT 24 Jun 23 04:47:17 PM PDT 24 87135393 ps
T2607 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2584139155 Jun 23 04:46:56 PM PDT 24 Jun 23 04:46:59 PM PDT 24 52007892 ps
T2608 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2120909710 Jun 23 04:46:56 PM PDT 24 Jun 23 04:47:00 PM PDT 24 99891356 ps
T2609 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2161632112 Jun 23 04:47:11 PM PDT 24 Jun 23 04:47:14 PM PDT 24 157681456 ps

Test location /workspace/coverage/default/26.usbdev_device_address.3500081048
Short name T31
Test name
Test status
Simulation time 17464434845 ps
CPU time 32.67 seconds
Started Jun 23 05:19:57 PM PDT 24
Finished Jun 23 05:20:31 PM PDT 24
Peak memory 206348 kb
Host smart-6408f4bb-cc41-470a-a84b-f24c7e157443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35000
81048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.3500081048
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.4175972385
Short name T6
Test name
Test status
Simulation time 10064397387 ps
CPU time 61.63 seconds
Started Jun 23 05:15:08 PM PDT 24
Finished Jun 23 05:16:10 PM PDT 24
Peak memory 206424 kb
Host smart-d526b844-31c1-4d3e-8c11-bf4fb8dc93d2
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4175972385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.4175972385
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1973041515
Short name T196
Test name
Test status
Simulation time 39904623 ps
CPU time 0.66 seconds
Started Jun 23 04:47:39 PM PDT 24
Finished Jun 23 04:47:40 PM PDT 24
Peak memory 205876 kb
Host smart-d5e83942-783a-44d9-9b6f-3934b3b71d8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1973041515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1973041515
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.3926773522
Short name T7
Test name
Test status
Simulation time 4254197225 ps
CPU time 5.07 seconds
Started Jun 23 05:20:54 PM PDT 24
Finished Jun 23 05:21:00 PM PDT 24
Peak memory 206188 kb
Host smart-f66dc318-98ab-4394-a530-79ffd74c56bf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3926773522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.3926773522
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3515230645
Short name T190
Test name
Test status
Simulation time 2232906960 ps
CPU time 6.69 seconds
Started Jun 23 04:47:11 PM PDT 24
Finished Jun 23 04:47:19 PM PDT 24
Peak memory 206368 kb
Host smart-8bd27315-b039-4b30-a01c-0cc722fc4fa7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3515230645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3515230645
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3027335999
Short name T535
Test name
Test status
Simulation time 267860070 ps
CPU time 0.91 seconds
Started Jun 23 05:14:47 PM PDT 24
Finished Jun 23 05:14:48 PM PDT 24
Peak memory 206000 kb
Host smart-f1341023-d1ad-4cd7-ac49-eb1c92edee13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30273
35999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3027335999
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3816905521
Short name T253
Test name
Test status
Simulation time 66755467 ps
CPU time 0.72 seconds
Started Jun 23 04:47:09 PM PDT 24
Finished Jun 23 04:47:11 PM PDT 24
Peak memory 205888 kb
Host smart-9cfefeeb-f46e-4dd8-acea-5288ac0c65fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3816905521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3816905521
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3406246721
Short name T103
Test name
Test status
Simulation time 220667993 ps
CPU time 0.88 seconds
Started Jun 23 05:20:56 PM PDT 24
Finished Jun 23 05:20:58 PM PDT 24
Peak memory 206108 kb
Host smart-c0593061-23e3-455b-b286-5bdafa772ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34062
46721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3406246721
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2032495541
Short name T348
Test name
Test status
Simulation time 142676262 ps
CPU time 0.73 seconds
Started Jun 23 05:17:24 PM PDT 24
Finished Jun 23 05:17:25 PM PDT 24
Peak memory 206072 kb
Host smart-53f769bb-53c2-4d40-bacd-4775e0316f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20324
95541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2032495541
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.98030419
Short name T215
Test name
Test status
Simulation time 100537035 ps
CPU time 2.32 seconds
Started Jun 23 04:47:33 PM PDT 24
Finished Jun 23 04:47:36 PM PDT 24
Peak memory 206260 kb
Host smart-6f2afb2d-c09d-4ca2-a68a-6feebbc42496
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=98030419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.98030419
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.302864777
Short name T106
Test name
Test status
Simulation time 185017353 ps
CPU time 0.85 seconds
Started Jun 23 05:17:10 PM PDT 24
Finished Jun 23 05:17:12 PM PDT 24
Peak memory 205996 kb
Host smart-73ee487c-0f2a-4b85-85f9-1d0db2b2d6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30286
4777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.302864777
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.1569906623
Short name T101
Test name
Test status
Simulation time 338435215 ps
CPU time 1.17 seconds
Started Jun 23 05:20:06 PM PDT 24
Finished Jun 23 05:20:08 PM PDT 24
Peak memory 206104 kb
Host smart-93683bb6-6276-4704-89a1-0b6f8dc1ebfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15699
06623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.1569906623
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3941315111
Short name T26
Test name
Test status
Simulation time 40579524 ps
CPU time 0.65 seconds
Started Jun 23 05:19:05 PM PDT 24
Finished Jun 23 05:19:06 PM PDT 24
Peak memory 206112 kb
Host smart-a0aa6569-1de7-4e47-82c6-69cdaaacfc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39413
15111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3941315111
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.1065031297
Short name T9
Test name
Test status
Simulation time 13348101214 ps
CPU time 12.26 seconds
Started Jun 23 05:18:51 PM PDT 24
Finished Jun 23 05:19:04 PM PDT 24
Peak memory 206124 kb
Host smart-f2b704d7-c576-431a-9a86-0ad6742c8d89
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1065031297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.1065031297
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2106335548
Short name T199
Test name
Test status
Simulation time 321998819 ps
CPU time 1.42 seconds
Started Jun 23 05:15:07 PM PDT 24
Finished Jun 23 05:15:09 PM PDT 24
Peak memory 223016 kb
Host smart-4bd4ce4d-49b2-4db7-9515-88aeb1029d8a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2106335548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2106335548
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.647372568
Short name T261
Test name
Test status
Simulation time 38767159 ps
CPU time 0.67 seconds
Started Jun 23 04:47:35 PM PDT 24
Finished Jun 23 04:47:36 PM PDT 24
Peak memory 205820 kb
Host smart-2598f16e-9310-4376-b433-a232e72f95dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=647372568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.647372568
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.511871447
Short name T78
Test name
Test status
Simulation time 316406539 ps
CPU time 1.04 seconds
Started Jun 23 05:14:53 PM PDT 24
Finished Jun 23 05:14:55 PM PDT 24
Peak memory 206076 kb
Host smart-8d74612d-1416-47ac-ac9c-1dba432450db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51187
1447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.511871447
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.3188753536
Short name T47
Test name
Test status
Simulation time 22278603671 ps
CPU time 619.17 seconds
Started Jun 23 05:15:21 PM PDT 24
Finished Jun 23 05:25:40 PM PDT 24
Peak memory 206300 kb
Host smart-1a90cc30-bd43-4fcb-a0a6-51cbfc3334cc
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3188753536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.3188753536
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.1314414773
Short name T48
Test name
Test status
Simulation time 20171750732 ps
CPU time 18.53 seconds
Started Jun 23 05:14:51 PM PDT 24
Finished Jun 23 05:15:10 PM PDT 24
Peak memory 206088 kb
Host smart-4c4cd1d1-05ed-4754-a447-13cb94190629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13144
14773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.1314414773
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3422116518
Short name T94
Test name
Test status
Simulation time 1479356486 ps
CPU time 3.28 seconds
Started Jun 23 05:22:58 PM PDT 24
Finished Jun 23 05:23:02 PM PDT 24
Peak memory 206316 kb
Host smart-cee4b79f-7b66-4f09-a296-b66974314223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34221
16518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3422116518
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3440732951
Short name T230
Test name
Test status
Simulation time 64162099 ps
CPU time 0.85 seconds
Started Jun 23 04:47:19 PM PDT 24
Finished Jun 23 04:47:21 PM PDT 24
Peak memory 205948 kb
Host smart-f5989d67-80a5-4dd9-b791-ee9a5dcc18bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3440732951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3440732951
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1131190868
Short name T254
Test name
Test status
Simulation time 43908699 ps
CPU time 0.68 seconds
Started Jun 23 04:47:07 PM PDT 24
Finished Jun 23 04:47:08 PM PDT 24
Peak memory 205956 kb
Host smart-98d55d80-b9cd-4a62-b356-7fe380850c2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1131190868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1131190868
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3410679463
Short name T18
Test name
Test status
Simulation time 179572715 ps
CPU time 0.81 seconds
Started Jun 23 05:17:40 PM PDT 24
Finished Jun 23 05:17:42 PM PDT 24
Peak memory 206028 kb
Host smart-8fd1428a-45e2-4053-8e92-87cf46d887a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34106
79463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3410679463
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.2688783301
Short name T76
Test name
Test status
Simulation time 137362248 ps
CPU time 0.74 seconds
Started Jun 23 05:17:48 PM PDT 24
Finished Jun 23 05:17:49 PM PDT 24
Peak memory 206096 kb
Host smart-e1559b8e-fccc-49d0-9374-d0a090080d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26887
83301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.2688783301
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.462247814
Short name T270
Test name
Test status
Simulation time 741416382 ps
CPU time 4.27 seconds
Started Jun 23 04:46:59 PM PDT 24
Finished Jun 23 04:47:05 PM PDT 24
Peak memory 206236 kb
Host smart-dc638084-1023-4bae-af06-5f52e8913673
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=462247814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.462247814
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.2270852932
Short name T11
Test name
Test status
Simulation time 13359780241 ps
CPU time 13.48 seconds
Started Jun 23 05:19:48 PM PDT 24
Finished Jun 23 05:20:02 PM PDT 24
Peak memory 205964 kb
Host smart-239e2a42-39e3-4ad1-b62d-e767f5904d22
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2270852932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.2270852932
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1887437283
Short name T255
Test name
Test status
Simulation time 54880343 ps
CPU time 0.68 seconds
Started Jun 23 04:46:59 PM PDT 24
Finished Jun 23 04:47:01 PM PDT 24
Peak memory 205880 kb
Host smart-51dbb04f-b8b6-434a-af15-6bd7f722e4f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1887437283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1887437283
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.1580877110
Short name T73
Test name
Test status
Simulation time 560378773 ps
CPU time 1.42 seconds
Started Jun 23 05:14:42 PM PDT 24
Finished Jun 23 05:14:44 PM PDT 24
Peak memory 206040 kb
Host smart-d1d18ffc-53de-42ee-b7bd-ea7d697b65c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15808
77110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.1580877110
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.1098646193
Short name T140
Test name
Test status
Simulation time 3357343163 ps
CPU time 91.05 seconds
Started Jun 23 05:18:28 PM PDT 24
Finished Jun 23 05:19:59 PM PDT 24
Peak memory 206264 kb
Host smart-82540dcf-1903-466e-be9e-48829a88b888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10986
46193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.1098646193
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3777827702
Short name T276
Test name
Test status
Simulation time 588140013 ps
CPU time 4.62 seconds
Started Jun 23 04:47:20 PM PDT 24
Finished Jun 23 04:47:25 PM PDT 24
Peak memory 206320 kb
Host smart-d94e2766-17d1-4a51-92d7-bac6d86d3acc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3777827702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3777827702
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.3753569300
Short name T58
Test name
Test status
Simulation time 272788633 ps
CPU time 1 seconds
Started Jun 23 05:14:51 PM PDT 24
Finished Jun 23 05:14:52 PM PDT 24
Peak memory 206076 kb
Host smart-bb769db8-3426-4116-96b0-b4d6b1381443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37535
69300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.3753569300
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.2756624178
Short name T69
Test name
Test status
Simulation time 134777033 ps
CPU time 0.77 seconds
Started Jun 23 05:14:41 PM PDT 24
Finished Jun 23 05:14:43 PM PDT 24
Peak memory 206040 kb
Host smart-3d42d227-bd3c-4118-808e-2104f5060fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27566
24178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.2756624178
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.390962004
Short name T272
Test name
Test status
Simulation time 553295804 ps
CPU time 4.13 seconds
Started Jun 23 04:46:58 PM PDT 24
Finished Jun 23 04:47:03 PM PDT 24
Peak memory 206196 kb
Host smart-9e599cb7-4e89-4080-abaf-697ceb801778
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=390962004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.390962004
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2064332670
Short name T2552
Test name
Test status
Simulation time 274292626 ps
CPU time 3.16 seconds
Started Jun 23 04:47:09 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 214456 kb
Host smart-1d828e14-b499-4a03-b8a8-5445b8d55935
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2064332670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2064332670
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1112663872
Short name T82
Test name
Test status
Simulation time 15015801293 ps
CPU time 25.19 seconds
Started Jun 23 05:17:23 PM PDT 24
Finished Jun 23 05:17:48 PM PDT 24
Peak memory 206424 kb
Host smart-ffd4ae6a-269d-444d-ae63-16b5eafb2dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11126
63872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1112663872
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3437575335
Short name T161
Test name
Test status
Simulation time 21414535176 ps
CPU time 44.58 seconds
Started Jun 23 05:15:03 PM PDT 24
Finished Jun 23 05:15:48 PM PDT 24
Peak memory 206304 kb
Host smart-065f5b92-c61a-485c-b58e-ed0c2b021219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34375
75335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3437575335
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.3827758298
Short name T64
Test name
Test status
Simulation time 14235893151 ps
CPU time 132.92 seconds
Started Jun 23 05:22:14 PM PDT 24
Finished Jun 23 05:24:27 PM PDT 24
Peak memory 206352 kb
Host smart-73741d36-6557-43e9-afec-2ae46865f06c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3827758298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.3827758298
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.396966316
Short name T440
Test name
Test status
Simulation time 138503090 ps
CPU time 0.76 seconds
Started Jun 23 05:17:21 PM PDT 24
Finished Jun 23 05:17:22 PM PDT 24
Peak memory 206124 kb
Host smart-98b90796-5b87-4bf9-9d96-4ffc3bf6b857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39696
6316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.396966316
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.631031268
Short name T787
Test name
Test status
Simulation time 23429685179 ps
CPU time 25.92 seconds
Started Jun 23 05:19:12 PM PDT 24
Finished Jun 23 05:19:38 PM PDT 24
Peak memory 206168 kb
Host smart-b46949f1-3552-484c-8b77-8586fbb45d85
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=631031268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.631031268
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1360938033
Short name T573
Test name
Test status
Simulation time 162730768 ps
CPU time 1.48 seconds
Started Jun 23 05:14:55 PM PDT 24
Finished Jun 23 05:14:57 PM PDT 24
Peak memory 206344 kb
Host smart-2a8a63ad-6655-4b31-ae91-620fe4b576d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13609
38033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1360938033
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.2378075366
Short name T68
Test name
Test status
Simulation time 140723163 ps
CPU time 0.77 seconds
Started Jun 23 05:15:06 PM PDT 24
Finished Jun 23 05:15:08 PM PDT 24
Peak memory 206064 kb
Host smart-0198c50f-75c0-4d97-8bcb-2a1626c0bde4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23780
75366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2378075366
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.1070593463
Short name T2140
Test name
Test status
Simulation time 17599504915 ps
CPU time 440.73 seconds
Started Jun 23 05:15:17 PM PDT 24
Finished Jun 23 05:22:38 PM PDT 24
Peak memory 206356 kb
Host smart-c45eb063-9457-4235-8bd1-435397f62e55
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1070593463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.1070593463
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/28.usbdev_device_address.2838064846
Short name T89
Test name
Test status
Simulation time 13998329220 ps
CPU time 24.9 seconds
Started Jun 23 05:20:12 PM PDT 24
Finished Jun 23 05:20:37 PM PDT 24
Peak memory 206392 kb
Host smart-f1b527a7-281d-4727-a822-1a177490f45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28380
64846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.2838064846
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.331734978
Short name T52
Test name
Test status
Simulation time 152135702 ps
CPU time 0.85 seconds
Started Jun 23 05:14:39 PM PDT 24
Finished Jun 23 05:14:40 PM PDT 24
Peak memory 206092 kb
Host smart-c60b906e-fb65-4f63-8285-462d9227e5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33173
4978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.331734978
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.1180935087
Short name T71
Test name
Test status
Simulation time 4161462689 ps
CPU time 9.2 seconds
Started Jun 23 05:14:49 PM PDT 24
Finished Jun 23 05:14:59 PM PDT 24
Peak memory 206336 kb
Host smart-8d141dcc-1f96-485e-81d8-62805321732c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11809
35087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1180935087
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.3678393473
Short name T72
Test name
Test status
Simulation time 214017534 ps
CPU time 0.86 seconds
Started Jun 23 05:14:41 PM PDT 24
Finished Jun 23 05:14:42 PM PDT 24
Peak memory 206004 kb
Host smart-ea4f64f4-a6c4-4b4e-aa4d-6fe30fd351fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36783
93473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.3678393473
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1379833303
Short name T894
Test name
Test status
Simulation time 36897899 ps
CPU time 0.67 seconds
Started Jun 23 05:14:52 PM PDT 24
Finished Jun 23 05:14:53 PM PDT 24
Peak memory 206072 kb
Host smart-875ef239-d059-4ba3-973a-60ecf212eafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13798
33303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1379833303
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3597457900
Short name T1057
Test name
Test status
Simulation time 1310210204 ps
CPU time 2.83 seconds
Started Jun 23 05:15:12 PM PDT 24
Finished Jun 23 05:15:16 PM PDT 24
Peak memory 206360 kb
Host smart-bd41dd9c-86da-4a38-91e3-2e5e38142186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35974
57900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3597457900
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.3291682993
Short name T60
Test name
Test status
Simulation time 154025184 ps
CPU time 0.87 seconds
Started Jun 23 05:15:25 PM PDT 24
Finished Jun 23 05:15:26 PM PDT 24
Peak memory 206024 kb
Host smart-b0613dd6-894a-4d3c-9892-96fca54c971d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32916
82993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.3291682993
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/47.usbdev_device_address.810643110
Short name T563
Test name
Test status
Simulation time 12008868873 ps
CPU time 24.9 seconds
Started Jun 23 05:22:46 PM PDT 24
Finished Jun 23 05:23:12 PM PDT 24
Peak memory 206368 kb
Host smart-ca533ff5-e7b3-47f3-a794-74023444c43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81064
3110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.810643110
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3260211854
Short name T251
Test name
Test status
Simulation time 486319643 ps
CPU time 2.37 seconds
Started Jun 23 04:47:16 PM PDT 24
Finished Jun 23 04:47:19 PM PDT 24
Peak memory 206256 kb
Host smart-21626a5b-c79b-4144-99b1-ade619321851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3260211854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3260211854
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1986716257
Short name T2034
Test name
Test status
Simulation time 229016969 ps
CPU time 0.89 seconds
Started Jun 23 05:14:44 PM PDT 24
Finished Jun 23 05:14:46 PM PDT 24
Peak memory 206100 kb
Host smart-13174114-ca1e-4f7b-bd36-42ab4f998879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19867
16257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1986716257
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.1076083078
Short name T43
Test name
Test status
Simulation time 17417233159 ps
CPU time 38.55 seconds
Started Jun 23 05:14:48 PM PDT 24
Finished Jun 23 05:15:27 PM PDT 24
Peak memory 206432 kb
Host smart-5dc196f3-1ee9-45b8-ba20-95600eb8f461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10760
83078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.1076083078
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.148266230
Short name T56
Test name
Test status
Simulation time 388424875 ps
CPU time 1.25 seconds
Started Jun 23 05:14:49 PM PDT 24
Finished Jun 23 05:14:51 PM PDT 24
Peak memory 206052 kb
Host smart-6b1b5cb5-2629-4816-ae9c-aacb77c9e6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14826
6230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.148266230
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.887537999
Short name T109
Test name
Test status
Simulation time 203497418 ps
CPU time 0.98 seconds
Started Jun 23 05:15:02 PM PDT 24
Finished Jun 23 05:15:03 PM PDT 24
Peak memory 206284 kb
Host smart-d57e97eb-f551-4f87-bb76-a419353d5d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88753
7999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.887537999
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.819200688
Short name T130
Test name
Test status
Simulation time 263611200 ps
CPU time 0.89 seconds
Started Jun 23 05:17:13 PM PDT 24
Finished Jun 23 05:17:14 PM PDT 24
Peak memory 206100 kb
Host smart-1ae249b7-1c63-49e1-a656-c2059bdc248a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81920
0688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.819200688
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2388352253
Short name T108
Test name
Test status
Simulation time 175950479 ps
CPU time 0.8 seconds
Started Jun 23 05:17:30 PM PDT 24
Finished Jun 23 05:17:31 PM PDT 24
Peak memory 206120 kb
Host smart-6c480510-0402-43ff-974c-0398fb874a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23883
52253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2388352253
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.39550592
Short name T122
Test name
Test status
Simulation time 243847150 ps
CPU time 0.94 seconds
Started Jun 23 05:17:43 PM PDT 24
Finished Jun 23 05:17:44 PM PDT 24
Peak memory 206056 kb
Host smart-52e3092f-aff6-4dd3-a0c8-2b415e5be133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39550
592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.39550592
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3569139870
Short name T115
Test name
Test status
Simulation time 202038121 ps
CPU time 0.84 seconds
Started Jun 23 05:17:52 PM PDT 24
Finished Jun 23 05:17:53 PM PDT 24
Peak memory 206100 kb
Host smart-eedcee25-5efc-4206-8d22-55fce81d7c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35691
39870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3569139870
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.781305961
Short name T138
Test name
Test status
Simulation time 177091601 ps
CPU time 0.78 seconds
Started Jun 23 05:18:31 PM PDT 24
Finished Jun 23 05:18:33 PM PDT 24
Peak memory 206100 kb
Host smart-facddab2-5432-4828-a3b8-ecd268e2dc6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78130
5961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.781305961
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3437878311
Short name T2091
Test name
Test status
Simulation time 228106729 ps
CPU time 0.9 seconds
Started Jun 23 05:18:47 PM PDT 24
Finished Jun 23 05:18:49 PM PDT 24
Peak memory 206104 kb
Host smart-1ad45916-d4ee-4fe3-87c8-4e663c1b2358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34378
78311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3437878311
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.4018961103
Short name T2495
Test name
Test status
Simulation time 206282780 ps
CPU time 0.86 seconds
Started Jun 23 05:15:12 PM PDT 24
Finished Jun 23 05:15:13 PM PDT 24
Peak memory 206116 kb
Host smart-5971a6a7-f62c-41c1-bffc-dcf12ef2996d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40189
61103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.4018961103
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.885574495
Short name T131
Test name
Test status
Simulation time 181817423 ps
CPU time 0.86 seconds
Started Jun 23 05:19:40 PM PDT 24
Finished Jun 23 05:19:41 PM PDT 24
Peak memory 206092 kb
Host smart-4b7d2105-291c-4add-8ec8-39daac5dbc8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88557
4495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.885574495
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2231145421
Short name T134
Test name
Test status
Simulation time 223791468 ps
CPU time 0.9 seconds
Started Jun 23 05:15:36 PM PDT 24
Finished Jun 23 05:15:37 PM PDT 24
Peak memory 205880 kb
Host smart-c712125a-a9d5-48cf-86f1-32470ff64222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22311
45421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2231145421
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.3711224292
Short name T102
Test name
Test status
Simulation time 13522525759 ps
CPU time 371.5 seconds
Started Jun 23 05:21:45 PM PDT 24
Finished Jun 23 05:27:57 PM PDT 24
Peak memory 206308 kb
Host smart-472982a5-ec56-4847-be98-84da1c225e87
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3711224292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.3711224292
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.482768491
Short name T2529
Test name
Test status
Simulation time 167682438 ps
CPU time 2.09 seconds
Started Jun 23 04:46:48 PM PDT 24
Finished Jun 23 04:46:51 PM PDT 24
Peak memory 206176 kb
Host smart-be6a7ae5-5d61-4a7a-a315-3c843b77e317
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=482768491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.482768491
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4026465099
Short name T194
Test name
Test status
Simulation time 707830900 ps
CPU time 4.21 seconds
Started Jun 23 04:47:03 PM PDT 24
Finished Jun 23 04:47:08 PM PDT 24
Peak memory 206340 kb
Host smart-92099653-c342-459c-9211-42ef9f3e1af5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4026465099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.4026465099
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2381199853
Short name T234
Test name
Test status
Simulation time 164345588 ps
CPU time 0.87 seconds
Started Jun 23 04:47:04 PM PDT 24
Finished Jun 23 04:47:06 PM PDT 24
Peak memory 206004 kb
Host smart-546586ef-1dbf-4ba7-9db7-8be4b8ee36f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2381199853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2381199853
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3189458608
Short name T224
Test name
Test status
Simulation time 133894313 ps
CPU time 1.32 seconds
Started Jun 23 04:46:59 PM PDT 24
Finished Jun 23 04:47:01 PM PDT 24
Peak memory 214404 kb
Host smart-bcb9263a-1205-4199-85eb-7204ef80b07b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189458608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3189458608
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.4173204815
Short name T240
Test name
Test status
Simulation time 53549072 ps
CPU time 0.81 seconds
Started Jun 23 04:47:12 PM PDT 24
Finished Jun 23 04:47:15 PM PDT 24
Peak memory 205972 kb
Host smart-cae4adb4-1b53-4827-adab-5e81fec9db99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4173204815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.4173204815
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1862709842
Short name T2577
Test name
Test status
Simulation time 44050397 ps
CPU time 0.67 seconds
Started Jun 23 04:47:10 PM PDT 24
Finished Jun 23 04:47:11 PM PDT 24
Peak memory 205884 kb
Host smart-cb0e82c0-4770-4d8c-8604-b792ad2b8a18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1862709842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1862709842
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3754441246
Short name T2590
Test name
Test status
Simulation time 100693053 ps
CPU time 1.41 seconds
Started Jun 23 04:47:05 PM PDT 24
Finished Jun 23 04:47:08 PM PDT 24
Peak memory 214448 kb
Host smart-0a4d2c70-319b-42f2-a7a1-b2bfd8ad7f4c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3754441246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3754441246
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1575551455
Short name T2546
Test name
Test status
Simulation time 489789832 ps
CPU time 4.54 seconds
Started Jun 23 04:47:02 PM PDT 24
Finished Jun 23 04:47:07 PM PDT 24
Peak memory 206240 kb
Host smart-2f75160b-1130-4649-8487-9afed4224aab
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1575551455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1575551455
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1675428762
Short name T243
Test name
Test status
Simulation time 135969782 ps
CPU time 1.44 seconds
Started Jun 23 04:46:50 PM PDT 24
Finished Jun 23 04:46:53 PM PDT 24
Peak memory 206252 kb
Host smart-cba2ead0-f449-4886-8afd-ccd6ee64edeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1675428762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1675428762
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.404846083
Short name T2593
Test name
Test status
Simulation time 126161552 ps
CPU time 1.59 seconds
Started Jun 23 04:46:49 PM PDT 24
Finished Jun 23 04:46:51 PM PDT 24
Peak memory 206148 kb
Host smart-107c1d11-db2d-4133-9354-68a3d5e4873f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=404846083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.404846083
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.435179253
Short name T2515
Test name
Test status
Simulation time 746315803 ps
CPU time 4.81 seconds
Started Jun 23 04:47:07 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 206256 kb
Host smart-4b6ba9ce-ec59-4cd7-9a92-439a2c3fdf37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=435179253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.435179253
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3349372845
Short name T2519
Test name
Test status
Simulation time 123142975 ps
CPU time 3.2 seconds
Started Jun 23 04:47:09 PM PDT 24
Finished Jun 23 04:47:14 PM PDT 24
Peak memory 206164 kb
Host smart-d17ec011-1bf1-4864-a500-0db0bb70c7ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3349372845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3349372845
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3116732828
Short name T2530
Test name
Test status
Simulation time 1290567726 ps
CPU time 7.95 seconds
Started Jun 23 04:47:00 PM PDT 24
Finished Jun 23 04:47:09 PM PDT 24
Peak memory 206200 kb
Host smart-cce0286d-3dc3-4954-9511-9c038c23f9b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3116732828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3116732828
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.690799912
Short name T2531
Test name
Test status
Simulation time 48988512 ps
CPU time 0.77 seconds
Started Jun 23 04:47:09 PM PDT 24
Finished Jun 23 04:47:10 PM PDT 24
Peak memory 205924 kb
Host smart-b6c63ba8-e4c2-4cf2-b4ac-e4e4811d4d5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=690799912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.690799912
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2294757472
Short name T2541
Test name
Test status
Simulation time 189583431 ps
CPU time 1.69 seconds
Started Jun 23 04:46:43 PM PDT 24
Finished Jun 23 04:46:45 PM PDT 24
Peak memory 217988 kb
Host smart-60dc804a-217c-4cca-aba8-ecee69784f12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294757472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2294757472
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1936420431
Short name T2566
Test name
Test status
Simulation time 61091959 ps
CPU time 0.83 seconds
Started Jun 23 04:46:57 PM PDT 24
Finished Jun 23 04:46:59 PM PDT 24
Peak memory 205928 kb
Host smart-922173dd-1e05-4bdf-b4f5-c3f4f0c67c9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1936420431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1936420431
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.7393549
Short name T2544
Test name
Test status
Simulation time 87956924 ps
CPU time 0.72 seconds
Started Jun 23 04:47:11 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 205832 kb
Host smart-e703317c-a067-44ba-928c-cc3844b197ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=7393549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.7393549
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2584344130
Short name T238
Test name
Test status
Simulation time 99785795 ps
CPU time 1.44 seconds
Started Jun 23 04:46:52 PM PDT 24
Finished Jun 23 04:46:54 PM PDT 24
Peak memory 214452 kb
Host smart-1d572b6f-598d-4f51-940f-bf949cd3b120
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2584344130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2584344130
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.612558456
Short name T2502
Test name
Test status
Simulation time 109435935 ps
CPU time 2.38 seconds
Started Jun 23 04:47:01 PM PDT 24
Finished Jun 23 04:47:04 PM PDT 24
Peak memory 206284 kb
Host smart-f16eac8f-bb17-491e-8f16-e50f793e5c0b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=612558456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.612558456
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1428960953
Short name T252
Test name
Test status
Simulation time 139157553 ps
CPU time 1.18 seconds
Started Jun 23 04:46:57 PM PDT 24
Finished Jun 23 04:47:00 PM PDT 24
Peak memory 206184 kb
Host smart-02fde5e0-a3a1-4b41-9c98-b3fe29882e8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1428960953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1428960953
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1712299078
Short name T2537
Test name
Test status
Simulation time 261795738 ps
CPU time 3.31 seconds
Started Jun 23 04:46:58 PM PDT 24
Finished Jun 23 04:47:02 PM PDT 24
Peak memory 221840 kb
Host smart-dfa0efd0-65d9-40e8-b1b6-b0468a84ec34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1712299078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1712299078
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3232657130
Short name T2568
Test name
Test status
Simulation time 1144104609 ps
CPU time 3.93 seconds
Started Jun 23 04:47:03 PM PDT 24
Finished Jun 23 04:47:08 PM PDT 24
Peak memory 206292 kb
Host smart-9d555e85-b6fa-43ab-ba12-1025f162caed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3232657130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3232657130
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4221235289
Short name T223
Test name
Test status
Simulation time 119106712 ps
CPU time 1.2 seconds
Started Jun 23 04:47:05 PM PDT 24
Finished Jun 23 04:47:07 PM PDT 24
Peak memory 214452 kb
Host smart-50767ebe-8d13-4c50-8ea9-5afd7ad83818
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221235289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.4221235289
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.583350574
Short name T2582
Test name
Test status
Simulation time 82769992 ps
CPU time 0.84 seconds
Started Jun 23 04:47:10 PM PDT 24
Finished Jun 23 04:47:12 PM PDT 24
Peak memory 205936 kb
Host smart-e505ac5b-7d2c-45d3-b161-3a6931f594a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=583350574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.583350574
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3684389584
Short name T264
Test name
Test status
Simulation time 38761269 ps
CPU time 0.66 seconds
Started Jun 23 04:47:23 PM PDT 24
Finished Jun 23 04:47:24 PM PDT 24
Peak memory 205868 kb
Host smart-b40e3cfc-81c7-4316-95ba-53d0283b91cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3684389584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3684389584
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1413035457
Short name T2591
Test name
Test status
Simulation time 158762745 ps
CPU time 1.23 seconds
Started Jun 23 04:47:06 PM PDT 24
Finished Jun 23 04:47:08 PM PDT 24
Peak memory 206172 kb
Host smart-330c3595-04fe-457e-894b-b4fd3bf66e7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1413035457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1413035457
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3457774231
Short name T218
Test name
Test status
Simulation time 146424623 ps
CPU time 2.91 seconds
Started Jun 23 04:47:15 PM PDT 24
Finished Jun 23 04:47:19 PM PDT 24
Peak memory 222188 kb
Host smart-1fe48417-0618-4568-a4f4-f3e39fa8ef7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3457774231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3457774231
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3858512917
Short name T2507
Test name
Test status
Simulation time 94252162 ps
CPU time 1.15 seconds
Started Jun 23 04:47:10 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 214324 kb
Host smart-0b8370c5-4ce4-4cb6-91c4-8ef86e4b8c80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858512917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3858512917
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.4597300
Short name T2508
Test name
Test status
Simulation time 66877055 ps
CPU time 0.98 seconds
Started Jun 23 04:47:11 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 206188 kb
Host smart-625e2571-3cee-457e-b4a2-9f6e27cf5606
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4597300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.4597300
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1421253197
Short name T2539
Test name
Test status
Simulation time 82572709 ps
CPU time 0.73 seconds
Started Jun 23 04:47:08 PM PDT 24
Finished Jun 23 04:47:10 PM PDT 24
Peak memory 205892 kb
Host smart-ee2bc695-d421-4de3-b09d-01ccfd55e3b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1421253197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1421253197
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2219986374
Short name T2524
Test name
Test status
Simulation time 194928224 ps
CPU time 2.51 seconds
Started Jun 23 04:47:10 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 222164 kb
Host smart-4755891a-24e7-479f-89eb-44365ca6086b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2219986374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2219986374
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1951204117
Short name T213
Test name
Test status
Simulation time 431294412 ps
CPU time 2.77 seconds
Started Jun 23 04:47:06 PM PDT 24
Finished Jun 23 04:47:10 PM PDT 24
Peak memory 206176 kb
Host smart-2b496f5c-8fd9-4808-a6cd-465b0f80ab21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1951204117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1951204117
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2940722456
Short name T2521
Test name
Test status
Simulation time 175703261 ps
CPU time 1.85 seconds
Started Jun 23 04:47:12 PM PDT 24
Finished Jun 23 04:47:15 PM PDT 24
Peak memory 217988 kb
Host smart-99c39890-22b2-41cb-97a6-2a6f93dc74aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940722456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.2940722456
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2306865963
Short name T2540
Test name
Test status
Simulation time 55871806 ps
CPU time 0.66 seconds
Started Jun 23 04:47:05 PM PDT 24
Finished Jun 23 04:47:06 PM PDT 24
Peak memory 205912 kb
Host smart-8e825c37-8dab-425c-9a59-93c399337a75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2306865963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2306865963
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.4282790726
Short name T2557
Test name
Test status
Simulation time 172221885 ps
CPU time 1.46 seconds
Started Jun 23 04:47:09 PM PDT 24
Finished Jun 23 04:47:11 PM PDT 24
Peak memory 206196 kb
Host smart-41beae27-cbdd-4d37-8e9e-a4d76789f2d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4282790726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.4282790726
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1748971632
Short name T2587
Test name
Test status
Simulation time 296965276 ps
CPU time 3.28 seconds
Started Jun 23 04:47:03 PM PDT 24
Finished Jun 23 04:47:07 PM PDT 24
Peak memory 206268 kb
Host smart-a10f6b24-43cf-4a85-b830-df5c245cb3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1748971632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1748971632
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.339297627
Short name T268
Test name
Test status
Simulation time 868346912 ps
CPU time 4.97 seconds
Started Jun 23 04:47:10 PM PDT 24
Finished Jun 23 04:47:16 PM PDT 24
Peak memory 206172 kb
Host smart-834919e5-1f83-40af-9e58-53b1c8f1da48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=339297627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.339297627
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.81193015
Short name T2503
Test name
Test status
Simulation time 167320979 ps
CPU time 1.85 seconds
Started Jun 23 04:46:58 PM PDT 24
Finished Jun 23 04:47:01 PM PDT 24
Peak memory 214344 kb
Host smart-1448cdfa-f033-423d-b42c-3a666d574475
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81193015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev
_csr_mem_rw_with_rand_reset.81193015
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2249487158
Short name T2559
Test name
Test status
Simulation time 65735825 ps
CPU time 0.83 seconds
Started Jun 23 04:47:13 PM PDT 24
Finished Jun 23 04:47:15 PM PDT 24
Peak memory 206048 kb
Host smart-f69cf909-2fcd-4c68-95f8-9adb87a28e33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2249487158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2249487158
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3744394212
Short name T258
Test name
Test status
Simulation time 52152261 ps
CPU time 0.67 seconds
Started Jun 23 04:47:12 PM PDT 24
Finished Jun 23 04:47:14 PM PDT 24
Peak memory 205876 kb
Host smart-de738782-0e9d-4715-a15b-1a1f27dfdc7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3744394212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3744394212
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2123545978
Short name T2551
Test name
Test status
Simulation time 123701675 ps
CPU time 1.15 seconds
Started Jun 23 04:47:15 PM PDT 24
Finished Jun 23 04:47:17 PM PDT 24
Peak memory 206216 kb
Host smart-0bc6cf1b-956a-4fec-a962-92c91025627d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2123545978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2123545978
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1489449515
Short name T269
Test name
Test status
Simulation time 1187765321 ps
CPU time 4.51 seconds
Started Jun 23 04:47:10 PM PDT 24
Finished Jun 23 04:47:25 PM PDT 24
Peak memory 206216 kb
Host smart-6297613a-10ee-42da-bfdc-6ac6ffb9d516
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1489449515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1489449515
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3236992716
Short name T2602
Test name
Test status
Simulation time 129983040 ps
CPU time 1.81 seconds
Started Jun 23 04:47:04 PM PDT 24
Finished Jun 23 04:47:07 PM PDT 24
Peak memory 214340 kb
Host smart-ec3310cd-d6e8-4b5e-a483-54be0a7822c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236992716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3236992716
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2840728148
Short name T2596
Test name
Test status
Simulation time 107016125 ps
CPU time 1.04 seconds
Started Jun 23 04:47:52 PM PDT 24
Finished Jun 23 04:47:54 PM PDT 24
Peak memory 206148 kb
Host smart-afae5e95-db81-49d7-9fa9-118422edd267
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2840728148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2840728148
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3893501626
Short name T2533
Test name
Test status
Simulation time 59671300 ps
CPU time 0.68 seconds
Started Jun 23 04:47:10 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 205876 kb
Host smart-9f233621-1f41-483c-aff7-9c7a08c2a6dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3893501626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3893501626
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.700402746
Short name T2532
Test name
Test status
Simulation time 555344802 ps
CPU time 2.92 seconds
Started Jun 23 04:47:26 PM PDT 24
Finished Jun 23 04:47:29 PM PDT 24
Peak memory 206256 kb
Host smart-efb2f880-4562-4bfd-937f-6315ac33d5a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=700402746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.700402746
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4233647434
Short name T216
Test name
Test status
Simulation time 287011970 ps
CPU time 3.13 seconds
Started Jun 23 04:47:14 PM PDT 24
Finished Jun 23 04:47:22 PM PDT 24
Peak memory 214404 kb
Host smart-9fcd895a-9e7e-456e-a5b1-27e689b5b058
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4233647434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.4233647434
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3950716740
Short name T2580
Test name
Test status
Simulation time 726902425 ps
CPU time 2.81 seconds
Started Jun 23 04:47:01 PM PDT 24
Finished Jun 23 04:47:05 PM PDT 24
Peak memory 206256 kb
Host smart-2ecee6bb-483f-43a1-9f95-708aa7fc0cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3950716740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3950716740
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2673276064
Short name T2584
Test name
Test status
Simulation time 116638379 ps
CPU time 1.19 seconds
Started Jun 23 04:46:59 PM PDT 24
Finished Jun 23 04:47:01 PM PDT 24
Peak memory 216336 kb
Host smart-81ba42f1-7d1a-4e0a-afff-4b83e21cee36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673276064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2673276064
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2635436152
Short name T2601
Test name
Test status
Simulation time 70863364 ps
CPU time 0.99 seconds
Started Jun 23 04:47:07 PM PDT 24
Finished Jun 23 04:47:10 PM PDT 24
Peak memory 206368 kb
Host smart-aa6d8c67-442a-40d6-8cb7-c7a235aa39ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2635436152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2635436152
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1729233533
Short name T2505
Test name
Test status
Simulation time 200138111 ps
CPU time 1.61 seconds
Started Jun 23 04:47:04 PM PDT 24
Finished Jun 23 04:47:06 PM PDT 24
Peak memory 206232 kb
Host smart-76e01b27-cb1d-437f-b4a0-527c29457c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1729233533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1729233533
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.597953871
Short name T2599
Test name
Test status
Simulation time 119169523 ps
CPU time 1.72 seconds
Started Jun 23 04:47:06 PM PDT 24
Finished Jun 23 04:47:09 PM PDT 24
Peak memory 214460 kb
Host smart-bd2695c4-b90c-47d3-b4fc-e579e17c1db1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=597953871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.597953871
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3045965065
Short name T2572
Test name
Test status
Simulation time 79506650 ps
CPU time 1.82 seconds
Started Jun 23 04:47:07 PM PDT 24
Finished Jun 23 04:47:09 PM PDT 24
Peak memory 214408 kb
Host smart-c07da32f-6f43-4842-ba03-3abbc02efcdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045965065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3045965065
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.42076173
Short name T235
Test name
Test status
Simulation time 87619790 ps
CPU time 0.87 seconds
Started Jun 23 04:47:20 PM PDT 24
Finished Jun 23 04:47:22 PM PDT 24
Peak memory 205964 kb
Host smart-c485d83d-57e2-4a54-a363-7aa5580a621f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=42076173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.42076173
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.4032963716
Short name T2585
Test name
Test status
Simulation time 42235744 ps
CPU time 0.69 seconds
Started Jun 23 04:47:03 PM PDT 24
Finished Jun 23 04:47:05 PM PDT 24
Peak memory 205876 kb
Host smart-b4bfc8a0-c5b0-4f24-a947-afa9d582dca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4032963716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.4032963716
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2648121077
Short name T2571
Test name
Test status
Simulation time 80797649 ps
CPU time 1 seconds
Started Jun 23 04:47:11 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 206140 kb
Host smart-97e84778-33c7-4df6-87ed-ff5058690371
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2648121077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2648121077
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2178310482
Short name T2512
Test name
Test status
Simulation time 252391599 ps
CPU time 3.06 seconds
Started Jun 23 04:47:05 PM PDT 24
Finished Jun 23 04:47:08 PM PDT 24
Peak memory 214452 kb
Host smart-80c4b384-729c-4443-9acc-a70b55b560ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2178310482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2178310482
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.4014870638
Short name T2526
Test name
Test status
Simulation time 133406487 ps
CPU time 1.39 seconds
Started Jun 23 04:47:01 PM PDT 24
Finished Jun 23 04:47:03 PM PDT 24
Peak memory 214356 kb
Host smart-e4839bf8-a39a-4c0d-9fb0-786f457d2afc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014870638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.4014870638
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2363785812
Short name T2545
Test name
Test status
Simulation time 64396677 ps
CPU time 0.76 seconds
Started Jun 23 04:47:09 PM PDT 24
Finished Jun 23 04:47:11 PM PDT 24
Peak memory 206000 kb
Host smart-fa843388-44b2-4cd2-a892-ca251ed7cbf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2363785812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2363785812
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.705104115
Short name T2510
Test name
Test status
Simulation time 52802733 ps
CPU time 0.73 seconds
Started Jun 23 04:47:11 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 206184 kb
Host smart-1b62d994-d497-4107-a1f8-82480793287a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=705104115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.705104115
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1708090609
Short name T193
Test name
Test status
Simulation time 89537096 ps
CPU time 1.13 seconds
Started Jun 23 04:47:12 PM PDT 24
Finished Jun 23 04:47:14 PM PDT 24
Peak memory 206188 kb
Host smart-6719cb96-0bf8-4833-b5a6-a61e9a3d0e8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1708090609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1708090609
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.998545269
Short name T225
Test name
Test status
Simulation time 1208664604 ps
CPU time 4.82 seconds
Started Jun 23 04:47:10 PM PDT 24
Finished Jun 23 04:47:16 PM PDT 24
Peak memory 206252 kb
Host smart-2214f156-24aa-456b-bc75-4830a99c03c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=998545269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.998545269
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2895862246
Short name T2592
Test name
Test status
Simulation time 129244497 ps
CPU time 2.35 seconds
Started Jun 23 04:47:10 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 214332 kb
Host smart-f03d74fd-8a3a-4ae4-b15d-874428093841
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895862246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2895862246
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2868411329
Short name T245
Test name
Test status
Simulation time 65608214 ps
CPU time 0.87 seconds
Started Jun 23 04:47:09 PM PDT 24
Finished Jun 23 04:47:11 PM PDT 24
Peak memory 205952 kb
Host smart-c860817b-7bf2-4033-a223-48ad278b33b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2868411329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2868411329
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.664880156
Short name T2509
Test name
Test status
Simulation time 33296179 ps
CPU time 0.66 seconds
Started Jun 23 04:47:06 PM PDT 24
Finished Jun 23 04:47:08 PM PDT 24
Peak memory 205908 kb
Host smart-0e01c097-8202-4c30-b62b-9371b3ec1ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=664880156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.664880156
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.505678862
Short name T2535
Test name
Test status
Simulation time 81403677 ps
CPU time 1.16 seconds
Started Jun 23 04:47:19 PM PDT 24
Finished Jun 23 04:47:21 PM PDT 24
Peak memory 206136 kb
Host smart-8f5f0247-25b7-4638-b7d0-e310b482ec03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=505678862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.505678862
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2161632112
Short name T2609
Test name
Test status
Simulation time 157681456 ps
CPU time 1.86 seconds
Started Jun 23 04:47:11 PM PDT 24
Finished Jun 23 04:47:14 PM PDT 24
Peak memory 214460 kb
Host smart-22f62982-1a10-4d88-b2a6-01f7eda1cb8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2161632112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2161632112
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3722689842
Short name T2514
Test name
Test status
Simulation time 505383556 ps
CPU time 2.65 seconds
Started Jun 23 04:48:44 PM PDT 24
Finished Jun 23 04:48:47 PM PDT 24
Peak memory 206240 kb
Host smart-7c794011-113f-4d1b-b5e3-cb6a708c2040
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3722689842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3722689842
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2842746767
Short name T2604
Test name
Test status
Simulation time 164859152 ps
CPU time 1.85 seconds
Started Jun 23 04:47:15 PM PDT 24
Finished Jun 23 04:47:18 PM PDT 24
Peak memory 214324 kb
Host smart-57f56642-63b3-4186-8472-51fd46002a34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842746767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2842746767
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1640601053
Short name T2569
Test name
Test status
Simulation time 106464815 ps
CPU time 0.91 seconds
Started Jun 23 04:47:12 PM PDT 24
Finished Jun 23 04:47:14 PM PDT 24
Peak memory 206264 kb
Host smart-f5481c1a-ee37-450e-ad71-4ae49dbba16f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1640601053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1640601053
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1526367442
Short name T2511
Test name
Test status
Simulation time 74860149 ps
CPU time 0.72 seconds
Started Jun 23 04:47:18 PM PDT 24
Finished Jun 23 04:47:19 PM PDT 24
Peak memory 205872 kb
Host smart-202c2195-724f-420a-b2c9-9c8fb4593066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1526367442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1526367442
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.282397004
Short name T244
Test name
Test status
Simulation time 256508015 ps
CPU time 1.59 seconds
Started Jun 23 04:47:18 PM PDT 24
Finished Jun 23 04:47:20 PM PDT 24
Peak memory 206176 kb
Host smart-9f7b6d6e-50fb-4abf-af70-6c7055eac17d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=282397004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.282397004
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1819756729
Short name T2586
Test name
Test status
Simulation time 177092992 ps
CPU time 1.65 seconds
Started Jun 23 04:47:18 PM PDT 24
Finished Jun 23 04:47:20 PM PDT 24
Peak memory 206312 kb
Host smart-b6ff4937-9dd5-485e-9b82-12373a90be75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1819756729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1819756729
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1778152676
Short name T273
Test name
Test status
Simulation time 769857213 ps
CPU time 4.56 seconds
Started Jun 23 04:47:11 PM PDT 24
Finished Jun 23 04:47:17 PM PDT 24
Peak memory 206224 kb
Host smart-af93e077-47c3-4660-b341-0db961120e18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1778152676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1778152676
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.761063215
Short name T237
Test name
Test status
Simulation time 363270532 ps
CPU time 3.35 seconds
Started Jun 23 04:47:25 PM PDT 24
Finished Jun 23 04:47:28 PM PDT 24
Peak memory 206304 kb
Host smart-eff56687-7916-4cac-8e29-96708c2dceac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=761063215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.761063215
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.774301354
Short name T231
Test name
Test status
Simulation time 928191144 ps
CPU time 7.91 seconds
Started Jun 23 04:47:13 PM PDT 24
Finished Jun 23 04:47:22 PM PDT 24
Peak memory 206336 kb
Host smart-c5eeb83c-06ac-4646-97c0-555fa88d1ee4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=774301354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.774301354
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3786578862
Short name T239
Test name
Test status
Simulation time 72258981 ps
CPU time 0.9 seconds
Started Jun 23 04:47:52 PM PDT 24
Finished Jun 23 04:47:54 PM PDT 24
Peak memory 206084 kb
Host smart-6e83d3de-98dc-4c22-abeb-2a06170382d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3786578862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3786578862
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3179577333
Short name T2549
Test name
Test status
Simulation time 62993295 ps
CPU time 1.33 seconds
Started Jun 23 04:47:08 PM PDT 24
Finished Jun 23 04:47:10 PM PDT 24
Peak memory 214460 kb
Host smart-e08af727-d269-47a1-8276-7d9c32901457
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179577333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3179577333
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3464920514
Short name T2594
Test name
Test status
Simulation time 76330299 ps
CPU time 0.84 seconds
Started Jun 23 04:47:11 PM PDT 24
Finished Jun 23 04:47:14 PM PDT 24
Peak memory 205920 kb
Host smart-449073ae-744b-4a84-a343-6efa10fd9c5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3464920514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3464920514
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.4055766365
Short name T2527
Test name
Test status
Simulation time 93690970 ps
CPU time 0.68 seconds
Started Jun 23 04:46:47 PM PDT 24
Finished Jun 23 04:46:48 PM PDT 24
Peak memory 205896 kb
Host smart-0be14320-2377-4192-b981-f67234f9c88b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4055766365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.4055766365
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.872518867
Short name T2536
Test name
Test status
Simulation time 127184694 ps
CPU time 1.41 seconds
Started Jun 23 04:47:06 PM PDT 24
Finished Jun 23 04:47:08 PM PDT 24
Peak memory 214452 kb
Host smart-94580d2f-7963-4620-abac-e177d6efbf77
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=872518867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.872518867
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2120909710
Short name T2608
Test name
Test status
Simulation time 99891356 ps
CPU time 2.24 seconds
Started Jun 23 04:46:56 PM PDT 24
Finished Jun 23 04:47:00 PM PDT 24
Peak memory 206284 kb
Host smart-7a5f64b7-635f-4158-8cf8-2b568dfdce24
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2120909710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2120909710
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2819632127
Short name T242
Test name
Test status
Simulation time 147840912 ps
CPU time 1.06 seconds
Started Jun 23 04:46:58 PM PDT 24
Finished Jun 23 04:47:00 PM PDT 24
Peak memory 206212 kb
Host smart-0d2e586c-2479-4109-872b-5bb95d3b6240
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2819632127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2819632127
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.553091954
Short name T217
Test name
Test status
Simulation time 87150980 ps
CPU time 1.83 seconds
Started Jun 23 04:46:52 PM PDT 24
Finished Jun 23 04:46:54 PM PDT 24
Peak memory 214424 kb
Host smart-ed37f387-5427-4a4d-8c25-3a1a4330adb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=553091954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.553091954
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.886476466
Short name T2517
Test name
Test status
Simulation time 42831340 ps
CPU time 0.65 seconds
Started Jun 23 04:47:13 PM PDT 24
Finished Jun 23 04:47:20 PM PDT 24
Peak memory 205944 kb
Host smart-f20b4a32-9007-4dbc-93cb-5bb3b852a856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=886476466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.886476466
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2495670621
Short name T2565
Test name
Test status
Simulation time 33793315 ps
CPU time 0.66 seconds
Started Jun 23 04:47:11 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 205868 kb
Host smart-25bb5f03-82a1-4757-94d1-939864e438c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2495670621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2495670621
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1586626733
Short name T265
Test name
Test status
Simulation time 88508040 ps
CPU time 0.7 seconds
Started Jun 23 04:46:59 PM PDT 24
Finished Jun 23 04:47:06 PM PDT 24
Peak memory 205956 kb
Host smart-4360bb2c-3611-445a-8b80-9a2208c3f36d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1586626733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1586626733
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.4170546785
Short name T2522
Test name
Test status
Simulation time 57098616 ps
CPU time 0.72 seconds
Started Jun 23 04:47:08 PM PDT 24
Finished Jun 23 04:47:10 PM PDT 24
Peak memory 205872 kb
Host smart-d2114ca3-fb67-48f2-a31b-71a66cfab6d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4170546785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.4170546785
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1612308720
Short name T259
Test name
Test status
Simulation time 40146909 ps
CPU time 0.69 seconds
Started Jun 23 04:47:13 PM PDT 24
Finished Jun 23 04:47:15 PM PDT 24
Peak memory 205872 kb
Host smart-14320d9f-8bc1-4d61-9632-61f7224a6c4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1612308720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1612308720
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2168903504
Short name T2561
Test name
Test status
Simulation time 37705277 ps
CPU time 0.67 seconds
Started Jun 23 04:47:11 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 205952 kb
Host smart-d50be138-2b5c-455e-839f-5169b9589f09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2168903504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2168903504
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.4199221912
Short name T2550
Test name
Test status
Simulation time 49317613 ps
CPU time 0.67 seconds
Started Jun 23 04:47:28 PM PDT 24
Finished Jun 23 04:47:29 PM PDT 24
Peak memory 205864 kb
Host smart-831f6cc9-7e2f-4544-86ce-6a6a1f06fd8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4199221912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.4199221912
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3118747924
Short name T2574
Test name
Test status
Simulation time 30429999 ps
CPU time 0.65 seconds
Started Jun 23 04:47:25 PM PDT 24
Finished Jun 23 04:47:26 PM PDT 24
Peak memory 205960 kb
Host smart-91bf7790-4f1a-4bf1-97e9-5c5d8dc08a4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3118747924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3118747924
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3559874668
Short name T2547
Test name
Test status
Simulation time 33543894 ps
CPU time 0.67 seconds
Started Jun 23 04:47:31 PM PDT 24
Finished Jun 23 04:47:32 PM PDT 24
Peak memory 205924 kb
Host smart-a80f753f-ee9d-4a2b-b84d-f36d92c2364e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3559874668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3559874668
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1709324779
Short name T2573
Test name
Test status
Simulation time 62462896 ps
CPU time 0.66 seconds
Started Jun 23 04:47:11 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 205956 kb
Host smart-c67eb5a7-e11f-4bdd-b5d5-5066983f16fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1709324779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1709324779
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4121049637
Short name T248
Test name
Test status
Simulation time 376284946 ps
CPU time 3.28 seconds
Started Jun 23 04:46:56 PM PDT 24
Finished Jun 23 04:47:01 PM PDT 24
Peak memory 206220 kb
Host smart-023d4682-c3f6-47c0-a363-2d8cf7e770e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4121049637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.4121049637
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1060517909
Short name T2516
Test name
Test status
Simulation time 858079289 ps
CPU time 9.08 seconds
Started Jun 23 04:46:56 PM PDT 24
Finished Jun 23 04:47:06 PM PDT 24
Peak memory 206256 kb
Host smart-4a348f62-24ef-4453-af2f-cec999789272
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1060517909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1060517909
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3913689520
Short name T2567
Test name
Test status
Simulation time 74454611 ps
CPU time 0.88 seconds
Started Jun 23 04:47:06 PM PDT 24
Finished Jun 23 04:47:08 PM PDT 24
Peak memory 205908 kb
Host smart-ac246276-4970-4ec4-bd28-4f9162399bbe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3913689520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3913689520
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.692634231
Short name T249
Test name
Test status
Simulation time 100192463 ps
CPU time 1.24 seconds
Started Jun 23 04:47:07 PM PDT 24
Finished Jun 23 04:47:09 PM PDT 24
Peak memory 214232 kb
Host smart-f9ad68a6-1104-4269-aca7-b48b5b6edfd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692634231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.692634231
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3232209671
Short name T2570
Test name
Test status
Simulation time 71709345 ps
CPU time 1.01 seconds
Started Jun 23 04:47:08 PM PDT 24
Finished Jun 23 04:47:10 PM PDT 24
Peak memory 206216 kb
Host smart-76676a83-00b3-412d-8e48-959747e01551
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3232209671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3232209671
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1095672075
Short name T2583
Test name
Test status
Simulation time 50794278 ps
CPU time 0.68 seconds
Started Jun 23 04:47:10 PM PDT 24
Finished Jun 23 04:47:12 PM PDT 24
Peak memory 205884 kb
Host smart-52041c82-8072-47cc-90e4-6517a2f53dc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1095672075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1095672075
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1453879543
Short name T232
Test name
Test status
Simulation time 115525676 ps
CPU time 1.46 seconds
Started Jun 23 04:47:09 PM PDT 24
Finished Jun 23 04:47:22 PM PDT 24
Peak memory 214436 kb
Host smart-24295ae0-6aa1-4056-9a49-ce4aa27ab8d0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1453879543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1453879543
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1798715222
Short name T2575
Test name
Test status
Simulation time 716115529 ps
CPU time 4.55 seconds
Started Jun 23 04:47:00 PM PDT 24
Finished Jun 23 04:47:05 PM PDT 24
Peak memory 206140 kb
Host smart-68df915a-871a-43de-be0f-136646ccaeea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1798715222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1798715222
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3104453350
Short name T241
Test name
Test status
Simulation time 72751910 ps
CPU time 1.11 seconds
Started Jun 23 04:47:03 PM PDT 24
Finished Jun 23 04:47:06 PM PDT 24
Peak memory 206340 kb
Host smart-693e06dd-5cd3-41b7-898b-b26186310ca1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3104453350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3104453350
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1284634446
Short name T219
Test name
Test status
Simulation time 105298196 ps
CPU time 2.49 seconds
Started Jun 23 04:46:59 PM PDT 24
Finished Jun 23 04:47:02 PM PDT 24
Peak memory 214532 kb
Host smart-79fc829a-5fb5-40da-8238-b0f7e2b43f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1284634446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1284634446
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3913539951
Short name T277
Test name
Test status
Simulation time 1056500327 ps
CPU time 4.44 seconds
Started Jun 23 04:47:13 PM PDT 24
Finished Jun 23 04:47:19 PM PDT 24
Peak memory 206076 kb
Host smart-2711c798-b61e-4fc9-89df-09e19c19b4cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3913539951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3913539951
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1380228339
Short name T2520
Test name
Test status
Simulation time 53640147 ps
CPU time 0.67 seconds
Started Jun 23 04:47:24 PM PDT 24
Finished Jun 23 04:47:25 PM PDT 24
Peak memory 205884 kb
Host smart-88dce6e8-bbb1-4cb5-816c-6b43c5363af7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1380228339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1380228339
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3069588551
Short name T2562
Test name
Test status
Simulation time 91708157 ps
CPU time 0.7 seconds
Started Jun 23 04:47:09 PM PDT 24
Finished Jun 23 04:47:11 PM PDT 24
Peak memory 205876 kb
Host smart-a03cc90f-a555-4823-b225-15b29e18f5f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3069588551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3069588551
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1310673625
Short name T198
Test name
Test status
Simulation time 48273427 ps
CPU time 0.67 seconds
Started Jun 23 04:47:17 PM PDT 24
Finished Jun 23 04:47:18 PM PDT 24
Peak memory 205904 kb
Host smart-b374e196-b41d-48e4-8ea3-163ed92c2856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1310673625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1310673625
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.361459530
Short name T2598
Test name
Test status
Simulation time 45031186 ps
CPU time 0.7 seconds
Started Jun 23 04:47:30 PM PDT 24
Finished Jun 23 04:47:31 PM PDT 24
Peak memory 205952 kb
Host smart-08e23239-486f-4a1d-9a77-6114f6f44430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=361459530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.361459530
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.798217162
Short name T2556
Test name
Test status
Simulation time 55591812 ps
CPU time 0.66 seconds
Started Jun 23 04:47:20 PM PDT 24
Finished Jun 23 04:47:21 PM PDT 24
Peak memory 205880 kb
Host smart-c57dfe72-490e-4a20-9e9a-421dcc76e714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=798217162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.798217162
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1426243669
Short name T2523
Test name
Test status
Simulation time 38300603 ps
CPU time 0.62 seconds
Started Jun 23 04:47:16 PM PDT 24
Finished Jun 23 04:47:18 PM PDT 24
Peak memory 205888 kb
Host smart-564f25cf-d562-432e-b41c-bb6400b32321
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1426243669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1426243669
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1457262761
Short name T2528
Test name
Test status
Simulation time 42536045 ps
CPU time 0.64 seconds
Started Jun 23 04:47:21 PM PDT 24
Finished Jun 23 04:47:22 PM PDT 24
Peak memory 205956 kb
Host smart-0a896b46-c537-4402-be9a-c39ca8f55ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1457262761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1457262761
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3266634771
Short name T2581
Test name
Test status
Simulation time 38253418 ps
CPU time 0.65 seconds
Started Jun 23 04:47:39 PM PDT 24
Finished Jun 23 04:47:40 PM PDT 24
Peak memory 205908 kb
Host smart-cca6a6a0-9652-44e6-986d-69fda64a4f1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3266634771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3266634771
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1490355596
Short name T2605
Test name
Test status
Simulation time 69653341 ps
CPU time 1.9 seconds
Started Jun 23 04:46:56 PM PDT 24
Finished Jun 23 04:47:00 PM PDT 24
Peak memory 206160 kb
Host smart-a716c0ab-c295-4f22-a287-befecbce986e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1490355596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1490355596
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2060392114
Short name T2501
Test name
Test status
Simulation time 370078638 ps
CPU time 4.59 seconds
Started Jun 23 04:47:09 PM PDT 24
Finished Jun 23 04:47:19 PM PDT 24
Peak memory 206280 kb
Host smart-81d90237-0218-4b40-9553-55d23578e39e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2060392114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2060392114
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3494215078
Short name T2595
Test name
Test status
Simulation time 192806102 ps
CPU time 1.03 seconds
Started Jun 23 04:46:54 PM PDT 24
Finished Jun 23 04:46:56 PM PDT 24
Peak memory 206084 kb
Host smart-6b86a766-c84d-4c09-a16a-f56cf0059565
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3494215078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3494215078
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1585329869
Short name T2518
Test name
Test status
Simulation time 78839627 ps
CPU time 1.96 seconds
Started Jun 23 04:47:23 PM PDT 24
Finished Jun 23 04:47:25 PM PDT 24
Peak memory 214408 kb
Host smart-d55ceb56-84fb-4a7a-ac28-652218a33255
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585329869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1585329869
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.4189844429
Short name T2543
Test name
Test status
Simulation time 111763375 ps
CPU time 0.95 seconds
Started Jun 23 04:47:10 PM PDT 24
Finished Jun 23 04:47:12 PM PDT 24
Peak memory 206184 kb
Host smart-09b99366-777e-44a7-be9f-5690163d949a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4189844429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.4189844429
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2530381278
Short name T2548
Test name
Test status
Simulation time 77771227 ps
CPU time 0.69 seconds
Started Jun 23 04:47:01 PM PDT 24
Finished Jun 23 04:47:02 PM PDT 24
Peak memory 205876 kb
Host smart-773f40af-6304-4f1f-a5a9-29ed04659976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2530381278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2530381278
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1059396917
Short name T233
Test name
Test status
Simulation time 74459410 ps
CPU time 2.26 seconds
Started Jun 23 04:46:44 PM PDT 24
Finished Jun 23 04:46:46 PM PDT 24
Peak memory 222532 kb
Host smart-b6289a8a-b9b7-412d-91ef-2cb2b6025794
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1059396917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1059396917
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1106889285
Short name T2588
Test name
Test status
Simulation time 694282495 ps
CPU time 4.47 seconds
Started Jun 23 04:46:49 PM PDT 24
Finished Jun 23 04:46:54 PM PDT 24
Peak memory 206200 kb
Host smart-4b798871-1787-47bc-bf16-fb70c4a3e973
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1106889285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1106889285
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2584139155
Short name T2607
Test name
Test status
Simulation time 52007892 ps
CPU time 1.09 seconds
Started Jun 23 04:46:56 PM PDT 24
Finished Jun 23 04:46:59 PM PDT 24
Peak memory 206208 kb
Host smart-3cc3b3dc-3639-4d82-9b59-f725b29fb8cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2584139155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2584139155
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2029904398
Short name T2525
Test name
Test status
Simulation time 323994952 ps
CPU time 3.02 seconds
Started Jun 23 04:46:57 PM PDT 24
Finished Jun 23 04:47:01 PM PDT 24
Peak memory 222068 kb
Host smart-6879d194-fa77-4660-9772-ae9e62685f9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2029904398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2029904398
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1496874233
Short name T275
Test name
Test status
Simulation time 679140788 ps
CPU time 4.18 seconds
Started Jun 23 04:46:58 PM PDT 24
Finished Jun 23 04:47:03 PM PDT 24
Peak memory 206280 kb
Host smart-460b47ac-3e1d-46f7-801b-4c174e3135db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1496874233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1496874233
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2985485422
Short name T197
Test name
Test status
Simulation time 71774714 ps
CPU time 0.67 seconds
Started Jun 23 04:47:16 PM PDT 24
Finished Jun 23 04:47:17 PM PDT 24
Peak memory 205956 kb
Host smart-557adaee-09cf-45c2-8500-968e8243a4c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2985485422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2985485422
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.473604816
Short name T266
Test name
Test status
Simulation time 85053188 ps
CPU time 0.75 seconds
Started Jun 23 04:47:21 PM PDT 24
Finished Jun 23 04:47:23 PM PDT 24
Peak memory 205876 kb
Host smart-eaed686f-d525-4dc6-9a02-356b15c919f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=473604816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.473604816
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4096388634
Short name T267
Test name
Test status
Simulation time 50003479 ps
CPU time 0.71 seconds
Started Jun 23 04:47:11 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 205824 kb
Host smart-4ac7f426-bfda-4d9e-944d-65360aa01c7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4096388634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.4096388634
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.511118784
Short name T2513
Test name
Test status
Simulation time 52683851 ps
CPU time 0.64 seconds
Started Jun 23 04:47:19 PM PDT 24
Finished Jun 23 04:47:20 PM PDT 24
Peak memory 205924 kb
Host smart-caffb7e1-1c07-4e57-991f-f0e36484d5c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=511118784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.511118784
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3048676091
Short name T2506
Test name
Test status
Simulation time 40759012 ps
CPU time 0.63 seconds
Started Jun 23 04:47:40 PM PDT 24
Finished Jun 23 04:47:42 PM PDT 24
Peak memory 205952 kb
Host smart-fb42e890-ecc5-4fde-aa2f-1be7c9a9e7eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3048676091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.3048676091
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1125839911
Short name T2534
Test name
Test status
Simulation time 112292914 ps
CPU time 0.7 seconds
Started Jun 23 04:47:29 PM PDT 24
Finished Jun 23 04:47:30 PM PDT 24
Peak memory 205956 kb
Host smart-30932c7a-8125-4e18-98dd-ecd79f278e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1125839911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1125839911
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3193590681
Short name T2563
Test name
Test status
Simulation time 53972963 ps
CPU time 0.68 seconds
Started Jun 23 04:47:14 PM PDT 24
Finished Jun 23 04:47:16 PM PDT 24
Peak memory 205876 kb
Host smart-024facff-fb33-4ee4-98a3-6d8de22d1376
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3193590681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3193590681
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.566953930
Short name T2603
Test name
Test status
Simulation time 30980263 ps
CPU time 0.67 seconds
Started Jun 23 04:47:14 PM PDT 24
Finished Jun 23 04:47:16 PM PDT 24
Peak memory 205880 kb
Host smart-163cebf3-e910-49f1-b106-099129510477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=566953930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.566953930
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3519400722
Short name T209
Test name
Test status
Simulation time 169317711 ps
CPU time 1.96 seconds
Started Jun 23 04:46:56 PM PDT 24
Finished Jun 23 04:46:59 PM PDT 24
Peak memory 214364 kb
Host smart-6517fd75-6e36-412d-ab7d-d414b0044aa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519400722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.3519400722
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3434358833
Short name T2589
Test name
Test status
Simulation time 71240504 ps
CPU time 0.82 seconds
Started Jun 23 04:47:13 PM PDT 24
Finished Jun 23 04:47:15 PM PDT 24
Peak memory 205944 kb
Host smart-fc0bb09b-4e93-4ca9-b17f-a73c0e5c7635
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3434358833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3434358833
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3709509158
Short name T257
Test name
Test status
Simulation time 33974051 ps
CPU time 0.69 seconds
Started Jun 23 04:46:45 PM PDT 24
Finished Jun 23 04:46:46 PM PDT 24
Peak memory 205868 kb
Host smart-a6f4a476-d443-4df0-8eee-ab9a0b3ec1b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3709509158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3709509158
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3260837406
Short name T2538
Test name
Test status
Simulation time 369414399 ps
CPU time 1.75 seconds
Started Jun 23 04:46:54 PM PDT 24
Finished Jun 23 04:46:57 PM PDT 24
Peak memory 206256 kb
Host smart-69710316-6ceb-4d48-acd2-356a17a67fb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3260837406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3260837406
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2485439492
Short name T210
Test name
Test status
Simulation time 93259915 ps
CPU time 1.35 seconds
Started Jun 23 04:47:14 PM PDT 24
Finished Jun 23 04:47:16 PM PDT 24
Peak memory 206276 kb
Host smart-1304d5ae-b284-47af-a248-d58fdaba9aca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2485439492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2485439492
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1651367217
Short name T189
Test name
Test status
Simulation time 248455151 ps
CPU time 2.4 seconds
Started Jun 23 04:47:05 PM PDT 24
Finished Jun 23 04:47:08 PM PDT 24
Peak memory 206280 kb
Host smart-0106acf6-a6bb-4986-97ee-a5a6ecbfff96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1651367217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1651367217
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1891370337
Short name T2576
Test name
Test status
Simulation time 229494193 ps
CPU time 1.25 seconds
Started Jun 23 04:46:45 PM PDT 24
Finished Jun 23 04:46:47 PM PDT 24
Peak memory 214276 kb
Host smart-3f486739-a629-4187-8f0e-28afd032304e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891370337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.1891370337
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1633757415
Short name T236
Test name
Test status
Simulation time 108264998 ps
CPU time 0.88 seconds
Started Jun 23 04:47:03 PM PDT 24
Finished Jun 23 04:47:05 PM PDT 24
Peak memory 206080 kb
Host smart-aca7d514-49d9-4532-99fa-b0e2c72d3460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1633757415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1633757415
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1752339260
Short name T2578
Test name
Test status
Simulation time 42494301 ps
CPU time 0.67 seconds
Started Jun 23 04:46:56 PM PDT 24
Finished Jun 23 04:46:58 PM PDT 24
Peak memory 205872 kb
Host smart-ce6e86aa-e585-46e8-97b9-97f8a121829f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1752339260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1752339260
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2175297827
Short name T2558
Test name
Test status
Simulation time 135161440 ps
CPU time 1.15 seconds
Started Jun 23 04:47:01 PM PDT 24
Finished Jun 23 04:47:03 PM PDT 24
Peak memory 206128 kb
Host smart-8300cc20-f659-4be1-a707-ef5dbeced843
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2175297827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.2175297827
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2386616461
Short name T2597
Test name
Test status
Simulation time 96042050 ps
CPU time 2.69 seconds
Started Jun 23 04:46:53 PM PDT 24
Finished Jun 23 04:46:57 PM PDT 24
Peak memory 222164 kb
Host smart-7a27ee78-821f-42b9-978a-632778357072
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2386616461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2386616461
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.14476432
Short name T250
Test name
Test status
Simulation time 550045778 ps
CPU time 2.96 seconds
Started Jun 23 04:47:12 PM PDT 24
Finished Jun 23 04:47:17 PM PDT 24
Peak memory 206188 kb
Host smart-33ddc4cc-737b-4f86-8eab-f7316d3a9eea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=14476432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.14476432
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1942678642
Short name T2542
Test name
Test status
Simulation time 171567501 ps
CPU time 1.78 seconds
Started Jun 23 04:47:04 PM PDT 24
Finished Jun 23 04:47:07 PM PDT 24
Peak memory 214400 kb
Host smart-a3c3b6b4-c98b-42fb-b678-984b8448f0bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942678642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1942678642
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.632954650
Short name T2553
Test name
Test status
Simulation time 69638093 ps
CPU time 0.83 seconds
Started Jun 23 04:47:02 PM PDT 24
Finished Jun 23 04:47:04 PM PDT 24
Peak memory 205924 kb
Host smart-af131d6b-01ba-46b4-a6aa-2813696a4b8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=632954650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.632954650
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2533536712
Short name T256
Test name
Test status
Simulation time 40304151 ps
CPU time 0.64 seconds
Started Jun 23 04:47:31 PM PDT 24
Finished Jun 23 04:47:32 PM PDT 24
Peak memory 205908 kb
Host smart-4ea4a641-d4e7-4d7c-9961-43ebb783eb00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2533536712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2533536712
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2498948653
Short name T2555
Test name
Test status
Simulation time 106808074 ps
CPU time 1.11 seconds
Started Jun 23 04:47:07 PM PDT 24
Finished Jun 23 04:47:09 PM PDT 24
Peak memory 206220 kb
Host smart-6ee1eb0b-4f05-4fa3-9f36-295b8aaed1f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2498948653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2498948653
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2270425209
Short name T2554
Test name
Test status
Simulation time 265285602 ps
CPU time 2.95 seconds
Started Jun 23 04:47:20 PM PDT 24
Finished Jun 23 04:47:24 PM PDT 24
Peak memory 222544 kb
Host smart-441bfca4-fec3-4d79-a140-8ee2f05cb3a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2270425209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2270425209
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2994646397
Short name T271
Test name
Test status
Simulation time 367011743 ps
CPU time 2.43 seconds
Started Jun 23 04:47:03 PM PDT 24
Finished Jun 23 04:47:06 PM PDT 24
Peak memory 206284 kb
Host smart-accf5246-da24-4dea-a636-048f0bc07afc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2994646397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2994646397
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2984914060
Short name T2606
Test name
Test status
Simulation time 87135393 ps
CPU time 1.75 seconds
Started Jun 23 04:47:15 PM PDT 24
Finished Jun 23 04:47:17 PM PDT 24
Peak memory 214456 kb
Host smart-10ab6c70-87be-4fba-b4a3-13f072af08ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984914060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2984914060
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.165300245
Short name T2579
Test name
Test status
Simulation time 96907341 ps
CPU time 0.83 seconds
Started Jun 23 04:47:11 PM PDT 24
Finished Jun 23 04:47:14 PM PDT 24
Peak memory 206080 kb
Host smart-8bc614a0-424f-4993-9793-a853335915b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=165300245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.165300245
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3138240978
Short name T260
Test name
Test status
Simulation time 59232968 ps
CPU time 0.69 seconds
Started Jun 23 04:47:05 PM PDT 24
Finished Jun 23 04:47:07 PM PDT 24
Peak memory 205800 kb
Host smart-01b273df-73bd-40c1-83a6-3b15949538e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3138240978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3138240978
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3546582920
Short name T2560
Test name
Test status
Simulation time 253691782 ps
CPU time 1.58 seconds
Started Jun 23 04:47:00 PM PDT 24
Finished Jun 23 04:47:02 PM PDT 24
Peak memory 206272 kb
Host smart-c18237b5-159f-4b65-afe2-22dcdde0b3dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3546582920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3546582920
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.329531279
Short name T191
Test name
Test status
Simulation time 78669907 ps
CPU time 1.85 seconds
Started Jun 23 04:47:06 PM PDT 24
Finished Jun 23 04:47:09 PM PDT 24
Peak memory 206324 kb
Host smart-5760f53a-de52-42c2-9bc1-5087e818af3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=329531279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.329531279
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4066865975
Short name T274
Test name
Test status
Simulation time 515760455 ps
CPU time 4.14 seconds
Started Jun 23 04:46:48 PM PDT 24
Finished Jun 23 04:46:53 PM PDT 24
Peak memory 206148 kb
Host smart-02496b06-7db0-4102-a9d8-b1ec81b81d56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4066865975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.4066865975
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1721621037
Short name T2564
Test name
Test status
Simulation time 109196170 ps
CPU time 1.24 seconds
Started Jun 23 04:47:14 PM PDT 24
Finished Jun 23 04:47:16 PM PDT 24
Peak memory 214296 kb
Host smart-a77f5d6e-3858-42a4-992b-37b42cc621e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721621037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1721621037
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2122819271
Short name T2600
Test name
Test status
Simulation time 90954842 ps
CPU time 1.05 seconds
Started Jun 23 04:47:19 PM PDT 24
Finished Jun 23 04:47:21 PM PDT 24
Peak memory 206172 kb
Host smart-0aa644b6-f27f-4ec8-8b4a-5d914b635b7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2122819271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2122819271
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.505059029
Short name T195
Test name
Test status
Simulation time 47166401 ps
CPU time 0.65 seconds
Started Jun 23 04:47:02 PM PDT 24
Finished Jun 23 04:47:04 PM PDT 24
Peak memory 205868 kb
Host smart-20fe9345-d5ea-4eda-b07e-40a0708cdabf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=505059029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.505059029
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1369505866
Short name T2504
Test name
Test status
Simulation time 220276300 ps
CPU time 1.47 seconds
Started Jun 23 04:46:52 PM PDT 24
Finished Jun 23 04:46:55 PM PDT 24
Peak memory 206212 kb
Host smart-45a757cb-1caa-4186-a965-dfab9e40cb2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1369505866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1369505866
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.101171025
Short name T214
Test name
Test status
Simulation time 115405324 ps
CPU time 1.38 seconds
Started Jun 23 04:47:05 PM PDT 24
Finished Jun 23 04:47:08 PM PDT 24
Peak memory 221740 kb
Host smart-23c64787-9fec-4522-88d6-a9b59c8e0467
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=101171025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.101171025
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3146357193
Short name T278
Test name
Test status
Simulation time 859361878 ps
CPU time 3.12 seconds
Started Jun 23 04:47:08 PM PDT 24
Finished Jun 23 04:47:13 PM PDT 24
Peak memory 206544 kb
Host smart-84ceb12c-e7bb-450a-9cd4-e9dede45e348
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3146357193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3146357193
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.153097928
Short name T475
Test name
Test status
Simulation time 3553781932 ps
CPU time 4.41 seconds
Started Jun 23 05:14:48 PM PDT 24
Finished Jun 23 05:14:53 PM PDT 24
Peak memory 206416 kb
Host smart-a61ca741-dca9-49e4-be9e-f2cb5d8af9c0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=153097928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.153097928
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.3193283255
Short name T1739
Test name
Test status
Simulation time 13354297519 ps
CPU time 13.45 seconds
Started Jun 23 05:14:45 PM PDT 24
Finished Jun 23 05:14:59 PM PDT 24
Peak memory 206172 kb
Host smart-584505e2-e10e-4374-b2d1-ee3cc1262c45
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3193283255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.3193283255
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.2618839546
Short name T1308
Test name
Test status
Simulation time 23368976939 ps
CPU time 23.06 seconds
Started Jun 23 05:14:41 PM PDT 24
Finished Jun 23 05:15:05 PM PDT 24
Peak memory 206172 kb
Host smart-d814cb63-4ca7-4b06-9f72-dc35ca4ca3ba
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2618839546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.2618839546
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.383117703
Short name T2499
Test name
Test status
Simulation time 157125030 ps
CPU time 0.81 seconds
Started Jun 23 05:14:40 PM PDT 24
Finished Jun 23 05:14:41 PM PDT 24
Peak memory 206092 kb
Host smart-398fe305-4932-4963-801d-eaba6a4bc151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38311
7703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.383117703
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1800911264
Short name T67
Test name
Test status
Simulation time 165037942 ps
CPU time 0.82 seconds
Started Jun 23 05:14:39 PM PDT 24
Finished Jun 23 05:14:40 PM PDT 24
Peak memory 206108 kb
Host smart-321123e9-5502-4c78-9d70-d6d134d1d9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18009
11264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1800911264
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.3752316453
Short name T173
Test name
Test status
Simulation time 483154586 ps
CPU time 1.41 seconds
Started Jun 23 05:14:40 PM PDT 24
Finished Jun 23 05:14:42 PM PDT 24
Peak memory 206268 kb
Host smart-db8cd139-e259-4e62-8ebc-c227950dd479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37523
16453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.3752316453
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.519872988
Short name T1966
Test name
Test status
Simulation time 423200994 ps
CPU time 1.16 seconds
Started Jun 23 05:14:42 PM PDT 24
Finished Jun 23 05:14:43 PM PDT 24
Peak memory 206040 kb
Host smart-da878b93-1c24-4a63-b80b-cb0cc108151e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51987
2988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.519872988
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.3223485007
Short name T833
Test name
Test status
Simulation time 19252001615 ps
CPU time 39.54 seconds
Started Jun 23 05:14:41 PM PDT 24
Finished Jun 23 05:15:21 PM PDT 24
Peak memory 206376 kb
Host smart-85281655-0f03-4921-9132-73f6b9af7130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32234
85007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.3223485007
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.2802603596
Short name T1461
Test name
Test status
Simulation time 436816602 ps
CPU time 1.54 seconds
Started Jun 23 05:14:41 PM PDT 24
Finished Jun 23 05:14:43 PM PDT 24
Peak memory 206104 kb
Host smart-e422677c-225d-493c-ba23-e2a47783f107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28026
03596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.2802603596
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.171901955
Short name T1334
Test name
Test status
Simulation time 165942924 ps
CPU time 0.79 seconds
Started Jun 23 05:14:46 PM PDT 24
Finished Jun 23 05:14:47 PM PDT 24
Peak memory 206020 kb
Host smart-863c395a-9961-4a3f-a0fd-0227e2376b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17190
1955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.171901955
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3277450414
Short name T2097
Test name
Test status
Simulation time 5113579920 ps
CPU time 130.38 seconds
Started Jun 23 05:14:43 PM PDT 24
Finished Jun 23 05:16:54 PM PDT 24
Peak memory 206312 kb
Host smart-925d3626-48ba-4a3e-9f82-3c9124518c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32774
50414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3277450414
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.1200542797
Short name T882
Test name
Test status
Simulation time 44371664 ps
CPU time 0.64 seconds
Started Jun 23 05:14:43 PM PDT 24
Finished Jun 23 05:14:44 PM PDT 24
Peak memory 206096 kb
Host smart-a4626047-0919-4f2c-a523-fd4651983c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12005
42797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1200542797
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.1796104811
Short name T1008
Test name
Test status
Simulation time 976297751 ps
CPU time 2.36 seconds
Started Jun 23 05:14:43 PM PDT 24
Finished Jun 23 05:14:46 PM PDT 24
Peak memory 206360 kb
Host smart-35f6c512-3589-4718-985a-9559e4a1fd95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17961
04811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.1796104811
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3105858331
Short name T2448
Test name
Test status
Simulation time 303859424 ps
CPU time 1.94 seconds
Started Jun 23 05:14:42 PM PDT 24
Finished Jun 23 05:14:45 PM PDT 24
Peak memory 206288 kb
Host smart-926fa338-2d45-4fee-b880-38eb1373ee31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31058
58331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3105858331
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1899581189
Short name T945
Test name
Test status
Simulation time 245125267 ps
CPU time 0.89 seconds
Started Jun 23 05:14:48 PM PDT 24
Finished Jun 23 05:14:49 PM PDT 24
Peak memory 206076 kb
Host smart-211282c1-b549-40f0-bfdb-c9b76d2d1354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18995
81189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1899581189
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2698415843
Short name T1832
Test name
Test status
Simulation time 153284345 ps
CPU time 0.85 seconds
Started Jun 23 05:14:51 PM PDT 24
Finished Jun 23 05:14:52 PM PDT 24
Peak memory 206016 kb
Host smart-ff111f79-de03-4a8c-8112-5d8a0970f4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26984
15843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2698415843
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.4223055721
Short name T600
Test name
Test status
Simulation time 228984770 ps
CPU time 0.96 seconds
Started Jun 23 05:14:43 PM PDT 24
Finished Jun 23 05:14:45 PM PDT 24
Peak memory 205972 kb
Host smart-edbfc883-1438-42bd-b09c-9a7a19ffadc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42230
55721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.4223055721
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1470961702
Short name T633
Test name
Test status
Simulation time 9819560595 ps
CPU time 90.59 seconds
Started Jun 23 05:14:43 PM PDT 24
Finished Jun 23 05:16:14 PM PDT 24
Peak memory 206240 kb
Host smart-c0eaf497-e0a9-4985-9a75-197816806744
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1470961702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1470961702
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1174194883
Short name T1525
Test name
Test status
Simulation time 170323243 ps
CPU time 0.82 seconds
Started Jun 23 05:14:48 PM PDT 24
Finished Jun 23 05:14:49 PM PDT 24
Peak memory 206100 kb
Host smart-f89a0c3f-2744-4304-8f53-1e04f2526b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11741
94883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1174194883
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.3918458496
Short name T75
Test name
Test status
Simulation time 423589445 ps
CPU time 1.34 seconds
Started Jun 23 05:14:48 PM PDT 24
Finished Jun 23 05:14:50 PM PDT 24
Peak memory 206000 kb
Host smart-ec752367-677f-4f2b-9a13-844b2c3dbfc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39184
58496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.3918458496
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.1712582438
Short name T2240
Test name
Test status
Simulation time 23285935220 ps
CPU time 22.46 seconds
Started Jun 23 05:14:44 PM PDT 24
Finished Jun 23 05:15:06 PM PDT 24
Peak memory 206084 kb
Host smart-c5b194fb-3112-44d8-9341-5f6918f8c248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17125
82438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.1712582438
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.2935135155
Short name T1607
Test name
Test status
Simulation time 3311926823 ps
CPU time 4.35 seconds
Started Jun 23 05:14:44 PM PDT 24
Finished Jun 23 05:14:48 PM PDT 24
Peak memory 206124 kb
Host smart-16dda3af-0561-4311-8387-c61fe35a7293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29351
35155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.2935135155
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2025436769
Short name T1375
Test name
Test status
Simulation time 5512692379 ps
CPU time 53.01 seconds
Started Jun 23 05:14:48 PM PDT 24
Finished Jun 23 05:15:41 PM PDT 24
Peak memory 206352 kb
Host smart-df8b631d-114d-4635-a6bb-f726d0e0e5ec
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2025436769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2025436769
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.1354457942
Short name T1148
Test name
Test status
Simulation time 232003192 ps
CPU time 0.91 seconds
Started Jun 23 05:14:59 PM PDT 24
Finished Jun 23 05:15:00 PM PDT 24
Peak memory 206128 kb
Host smart-afcd047e-7681-434b-ad7a-ae35e2cac3e7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1354457942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.1354457942
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3112846422
Short name T2063
Test name
Test status
Simulation time 196444742 ps
CPU time 0.88 seconds
Started Jun 23 05:14:44 PM PDT 24
Finished Jun 23 05:14:45 PM PDT 24
Peak memory 206144 kb
Host smart-68846561-688a-4e1e-b82e-0a7104143de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31128
46422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3112846422
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2064846657
Short name T2476
Test name
Test status
Simulation time 7371375622 ps
CPU time 69.05 seconds
Started Jun 23 05:14:44 PM PDT 24
Finished Jun 23 05:15:54 PM PDT 24
Peak memory 206572 kb
Host smart-7518bba2-a928-45ac-bf35-c8708c19cd5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20648
46657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2064846657
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.3059149654
Short name T587
Test name
Test status
Simulation time 4959845469 ps
CPU time 35.56 seconds
Started Jun 23 05:14:44 PM PDT 24
Finished Jun 23 05:15:20 PM PDT 24
Peak memory 206388 kb
Host smart-77d4b6a6-fa30-4cfd-8619-521f37e602e0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3059149654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.3059149654
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.3821194003
Short name T421
Test name
Test status
Simulation time 183772037 ps
CPU time 0.82 seconds
Started Jun 23 05:14:56 PM PDT 24
Finished Jun 23 05:14:57 PM PDT 24
Peak memory 206128 kb
Host smart-577995c2-2959-4e6e-93a9-bc53719d1acc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3821194003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.3821194003
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2347983751
Short name T944
Test name
Test status
Simulation time 139994957 ps
CPU time 0.73 seconds
Started Jun 23 05:14:44 PM PDT 24
Finished Jun 23 05:14:45 PM PDT 24
Peak memory 206128 kb
Host smart-37d74e41-a865-43b6-b6c0-1131401b2121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23479
83751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2347983751
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3066506322
Short name T74
Test name
Test status
Simulation time 486571805 ps
CPU time 1.46 seconds
Started Jun 23 05:14:44 PM PDT 24
Finished Jun 23 05:14:46 PM PDT 24
Peak memory 206048 kb
Host smart-5dd953ce-ac3f-4fcf-aa1b-1ec48029898a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30665
06322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3066506322
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.1232103872
Short name T2489
Test name
Test status
Simulation time 202125089 ps
CPU time 0.86 seconds
Started Jun 23 05:14:47 PM PDT 24
Finished Jun 23 05:14:48 PM PDT 24
Peak memory 206004 kb
Host smart-5e07c47d-c782-4da6-af65-0d5a7674f099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12321
03872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.1232103872
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1013513644
Short name T2317
Test name
Test status
Simulation time 169326305 ps
CPU time 0.8 seconds
Started Jun 23 05:14:47 PM PDT 24
Finished Jun 23 05:14:48 PM PDT 24
Peak memory 206100 kb
Host smart-b215b718-2e6b-4a50-a03a-01ec6ae33d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10135
13644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1013513644
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.684118459
Short name T1181
Test name
Test status
Simulation time 190329621 ps
CPU time 0.81 seconds
Started Jun 23 05:14:50 PM PDT 24
Finished Jun 23 05:14:51 PM PDT 24
Peak memory 206096 kb
Host smart-4697f66e-4e95-4ceb-a6a7-a8c0822db200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68411
8459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.684118459
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1809594936
Short name T1920
Test name
Test status
Simulation time 188568380 ps
CPU time 0.85 seconds
Started Jun 23 05:14:52 PM PDT 24
Finished Jun 23 05:14:53 PM PDT 24
Peak memory 206100 kb
Host smart-51d99eed-1a50-4c39-abc7-4ea85ffe6e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18095
94936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1809594936
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.3924290955
Short name T752
Test name
Test status
Simulation time 226922943 ps
CPU time 0.92 seconds
Started Jun 23 05:14:51 PM PDT 24
Finished Jun 23 05:14:52 PM PDT 24
Peak memory 206128 kb
Host smart-2616bea1-624e-4526-a121-d6b59d10fcc8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3924290955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.3924290955
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3413240784
Short name T1234
Test name
Test status
Simulation time 152720184 ps
CPU time 0.77 seconds
Started Jun 23 05:14:50 PM PDT 24
Finished Jun 23 05:14:51 PM PDT 24
Peak memory 206124 kb
Host smart-ffbf0710-3ce4-45e6-bead-51a07f7f2074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34132
40784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3413240784
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1058650618
Short name T395
Test name
Test status
Simulation time 189538675 ps
CPU time 0.86 seconds
Started Jun 23 05:14:45 PM PDT 24
Finished Jun 23 05:14:47 PM PDT 24
Peak memory 206052 kb
Host smart-c10c58a3-1e1f-4ced-89b1-bf3b15364bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10586
50618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1058650618
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1027114181
Short name T467
Test name
Test status
Simulation time 216785165 ps
CPU time 0.83 seconds
Started Jun 23 05:14:47 PM PDT 24
Finished Jun 23 05:14:48 PM PDT 24
Peak memory 206060 kb
Host smart-60c73b74-81a3-46a7-afe1-0aa8e3f1477f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10271
14181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1027114181
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.22865124
Short name T171
Test name
Test status
Simulation time 13850297189 ps
CPU time 70.09 seconds
Started Jun 23 05:14:47 PM PDT 24
Finished Jun 23 05:15:57 PM PDT 24
Peak memory 206472 kb
Host smart-fe2ac37a-e854-45ad-9c7d-aaea2e73aa4b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=22865124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.22865124
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.2064543618
Short name T155
Test name
Test status
Simulation time 22604461586 ps
CPU time 153.85 seconds
Started Jun 23 05:14:45 PM PDT 24
Finished Jun 23 05:17:19 PM PDT 24
Peak memory 206316 kb
Host smart-4079e2d5-ae7c-4689-b03e-7abf7bb74b42
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2064543618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2064543618
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.355262373
Short name T597
Test name
Test status
Simulation time 13414148996 ps
CPU time 294.74 seconds
Started Jun 23 05:14:45 PM PDT 24
Finished Jun 23 05:19:40 PM PDT 24
Peak memory 206396 kb
Host smart-d81569d6-f8be-4e81-a759-a8a71c299fb7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=355262373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.355262373
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3926071343
Short name T687
Test name
Test status
Simulation time 207715994 ps
CPU time 0.84 seconds
Started Jun 23 05:14:56 PM PDT 24
Finished Jun 23 05:14:57 PM PDT 24
Peak memory 206108 kb
Host smart-37633478-4d8b-4b28-8260-72101017b921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39260
71343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3926071343
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.4236821847
Short name T2250
Test name
Test status
Simulation time 157008521 ps
CPU time 0.79 seconds
Started Jun 23 05:14:48 PM PDT 24
Finished Jun 23 05:14:49 PM PDT 24
Peak memory 206120 kb
Host smart-22efb9b3-1d0e-4191-8bac-22b21c84cd04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42368
21847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.4236821847
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.276527181
Short name T1058
Test name
Test status
Simulation time 145104312 ps
CPU time 0.75 seconds
Started Jun 23 05:14:50 PM PDT 24
Finished Jun 23 05:14:52 PM PDT 24
Peak memory 206028 kb
Host smart-1ea8e917-d81e-480b-8245-e04e8716b547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27652
7181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.276527181
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.18935317
Short name T186
Test name
Test status
Simulation time 253823763 ps
CPU time 1.06 seconds
Started Jun 23 05:14:55 PM PDT 24
Finished Jun 23 05:14:56 PM PDT 24
Peak memory 223940 kb
Host smart-1371e6b8-42ca-400e-b5df-cdcb0080b2d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=18935317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.18935317
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.919782857
Short name T1684
Test name
Test status
Simulation time 163608634 ps
CPU time 0.83 seconds
Started Jun 23 05:14:51 PM PDT 24
Finished Jun 23 05:14:53 PM PDT 24
Peak memory 206120 kb
Host smart-42f3fe53-31a7-4772-9ce4-a44b25238332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91978
2857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.919782857
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.2629010452
Short name T911
Test name
Test status
Simulation time 163158181 ps
CPU time 0.78 seconds
Started Jun 23 05:14:52 PM PDT 24
Finished Jun 23 05:14:53 PM PDT 24
Peak memory 206020 kb
Host smart-784e4bce-9d4f-4a89-8fb6-493a3afd7e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26290
10452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.2629010452
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.656223597
Short name T441
Test name
Test status
Simulation time 253117466 ps
CPU time 0.98 seconds
Started Jun 23 05:14:39 PM PDT 24
Finished Jun 23 05:14:40 PM PDT 24
Peak memory 206024 kb
Host smart-4857e03c-d2e4-4523-8c64-4a1deff1ea8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65622
3597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.656223597
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.2182803332
Short name T2249
Test name
Test status
Simulation time 13408855583 ps
CPU time 103.22 seconds
Started Jun 23 05:14:49 PM PDT 24
Finished Jun 23 05:16:33 PM PDT 24
Peak memory 206516 kb
Host smart-c02e72cc-10cb-4904-804b-35edfa422d21
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2182803332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.2182803332
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1077598013
Short name T1604
Test name
Test status
Simulation time 172804296 ps
CPU time 0.85 seconds
Started Jun 23 05:14:53 PM PDT 24
Finished Jun 23 05:14:54 PM PDT 24
Peak memory 206104 kb
Host smart-23b6c135-d266-420e-a670-1d29a0df61a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10775
98013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1077598013
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.1110998965
Short name T280
Test name
Test status
Simulation time 196282769 ps
CPU time 0.86 seconds
Started Jun 23 05:14:51 PM PDT 24
Finished Jun 23 05:14:52 PM PDT 24
Peak memory 206076 kb
Host smart-6a192b59-4c1b-4028-9182-dc6ec607aa9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11109
98965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.1110998965
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.681487707
Short name T322
Test name
Test status
Simulation time 10182103140 ps
CPU time 275.54 seconds
Started Jun 23 05:14:51 PM PDT 24
Finished Jun 23 05:19:27 PM PDT 24
Peak memory 206248 kb
Host smart-97218db0-cc81-445b-b641-f3b420c102ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68148
7707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.681487707
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.3211150000
Short name T46
Test name
Test status
Simulation time 26058696680 ps
CPU time 648.5 seconds
Started Jun 23 05:14:51 PM PDT 24
Finished Jun 23 05:25:40 PM PDT 24
Peak memory 206300 kb
Host smart-ce9fdaa2-cff0-4efb-bc3b-9715e28c4b7e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3211150000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.3211150000
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1017559471
Short name T1717
Test name
Test status
Simulation time 4169939362 ps
CPU time 4.46 seconds
Started Jun 23 05:14:56 PM PDT 24
Finished Jun 23 05:15:00 PM PDT 24
Peak memory 206156 kb
Host smart-9a379263-0f02-4daf-b7af-9d21e4eca9f7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1017559471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.1017559471
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.2436777644
Short name T864
Test name
Test status
Simulation time 13424232017 ps
CPU time 12.6 seconds
Started Jun 23 05:14:58 PM PDT 24
Finished Jun 23 05:15:11 PM PDT 24
Peak memory 206172 kb
Host smart-29c2e556-c6b2-4b5f-9f80-f158355256c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2436777644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.2436777644
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.1265626926
Short name T589
Test name
Test status
Simulation time 23424975184 ps
CPU time 24.04 seconds
Started Jun 23 05:14:56 PM PDT 24
Finished Jun 23 05:15:21 PM PDT 24
Peak memory 206276 kb
Host smart-21b63e3a-3b4a-4fdc-8ed6-6808abf31557
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1265626926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.1265626926
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1907330583
Short name T2171
Test name
Test status
Simulation time 164709142 ps
CPU time 0.79 seconds
Started Jun 23 05:14:57 PM PDT 24
Finished Jun 23 05:14:58 PM PDT 24
Peak memory 206028 kb
Host smart-18144c23-e9f4-4ac2-a259-123951615719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19073
30583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1907330583
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.4185324072
Short name T54
Test name
Test status
Simulation time 197570751 ps
CPU time 0.83 seconds
Started Jun 23 05:15:01 PM PDT 24
Finished Jun 23 05:15:02 PM PDT 24
Peak memory 206104 kb
Host smart-62eee5c9-9d2b-441a-996b-f5fb577920d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41853
24072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.4185324072
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.2012025148
Short name T85
Test name
Test status
Simulation time 137069381 ps
CPU time 0.76 seconds
Started Jun 23 05:15:01 PM PDT 24
Finished Jun 23 05:15:02 PM PDT 24
Peak memory 206096 kb
Host smart-d617e31b-3bcc-48d5-b07f-360897286426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20120
25148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.2012025148
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1206915218
Short name T2047
Test name
Test status
Simulation time 159817155 ps
CPU time 0.79 seconds
Started Jun 23 05:14:57 PM PDT 24
Finished Jun 23 05:14:58 PM PDT 24
Peak memory 206108 kb
Host smart-606eaae5-10cd-48d0-b0c8-ea8a9ddbc9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12069
15218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1206915218
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.1509832214
Short name T1174
Test name
Test status
Simulation time 268240662 ps
CPU time 1.04 seconds
Started Jun 23 05:15:06 PM PDT 24
Finished Jun 23 05:15:08 PM PDT 24
Peak memory 206096 kb
Host smart-6815b85d-ab45-468c-980d-2087ee14b850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15098
32214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.1509832214
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1350692324
Short name T1338
Test name
Test status
Simulation time 404775926 ps
CPU time 1.2 seconds
Started Jun 23 05:15:06 PM PDT 24
Finished Jun 23 05:15:08 PM PDT 24
Peak memory 206112 kb
Host smart-e7d2bee0-2340-49df-97c2-732f81348ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13506
92324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1350692324
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.4063364399
Short name T918
Test name
Test status
Simulation time 6488449202 ps
CPU time 13.14 seconds
Started Jun 23 05:14:59 PM PDT 24
Finished Jun 23 05:15:12 PM PDT 24
Peak memory 206392 kb
Host smart-6a3da7b7-ab79-401d-aa04-8ab6ed1f26c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40633
64399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.4063364399
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.3380598092
Short name T1696
Test name
Test status
Simulation time 420756112 ps
CPU time 1.23 seconds
Started Jun 23 05:15:02 PM PDT 24
Finished Jun 23 05:15:03 PM PDT 24
Peak memory 206104 kb
Host smart-a359e46f-7aa3-4631-96e3-056363145c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33805
98092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.3380598092
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.1408842293
Short name T2199
Test name
Test status
Simulation time 175971400 ps
CPU time 0.76 seconds
Started Jun 23 05:14:55 PM PDT 24
Finished Jun 23 05:14:56 PM PDT 24
Peak memory 206024 kb
Host smart-35594021-271b-440e-8015-3904d30ae31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14088
42293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.1408842293
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.2262052334
Short name T750
Test name
Test status
Simulation time 35469700 ps
CPU time 0.66 seconds
Started Jun 23 05:15:01 PM PDT 24
Finished Jun 23 05:15:02 PM PDT 24
Peak memory 206096 kb
Host smart-692a6b85-f53c-4e86-b1c3-f3dfd9025794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22620
52334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2262052334
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.87945035
Short name T1436
Test name
Test status
Simulation time 966014895 ps
CPU time 2.15 seconds
Started Jun 23 05:15:02 PM PDT 24
Finished Jun 23 05:15:04 PM PDT 24
Peak memory 206288 kb
Host smart-a586beef-07e1-4c44-9e0b-9780e7bd7e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87945
035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.87945035
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.297796206
Short name T1984
Test name
Test status
Simulation time 194174601 ps
CPU time 0.84 seconds
Started Jun 23 05:15:06 PM PDT 24
Finished Jun 23 05:15:08 PM PDT 24
Peak memory 206120 kb
Host smart-dd86f8c1-84ea-4d9c-8a9b-e63968d4e64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29779
6206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.297796206
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3644599701
Short name T370
Test name
Test status
Simulation time 219424322 ps
CPU time 0.85 seconds
Started Jun 23 05:15:22 PM PDT 24
Finished Jun 23 05:15:23 PM PDT 24
Peak memory 205876 kb
Host smart-ef3b7b13-f3f6-4450-9bd7-942e2ef30ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36445
99701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3644599701
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3044005766
Short name T1639
Test name
Test status
Simulation time 180117152 ps
CPU time 0.82 seconds
Started Jun 23 05:15:05 PM PDT 24
Finished Jun 23 05:15:06 PM PDT 24
Peak memory 206096 kb
Host smart-57b1d472-349b-437b-a1b1-185acd81a788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30440
05766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3044005766
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.858864352
Short name T1219
Test name
Test status
Simulation time 245847995 ps
CPU time 0.91 seconds
Started Jun 23 05:15:05 PM PDT 24
Finished Jun 23 05:15:06 PM PDT 24
Peak memory 206096 kb
Host smart-881067b5-bd8e-4058-bd82-95ae095ad1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85886
4352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.858864352
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.139642673
Short name T1462
Test name
Test status
Simulation time 23329924941 ps
CPU time 22.65 seconds
Started Jun 23 05:15:00 PM PDT 24
Finished Jun 23 05:15:23 PM PDT 24
Peak memory 206140 kb
Host smart-64853dd5-6890-4ab3-bbde-f2761c4c3d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13964
2673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.139642673
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.3865779476
Short name T927
Test name
Test status
Simulation time 3264817295 ps
CPU time 3.93 seconds
Started Jun 23 05:15:00 PM PDT 24
Finished Jun 23 05:15:05 PM PDT 24
Peak memory 206172 kb
Host smart-7e246404-9971-4bee-897e-3a234c1516c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38657
79476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.3865779476
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.3012720631
Short name T1800
Test name
Test status
Simulation time 15102908459 ps
CPU time 146.66 seconds
Started Jun 23 05:15:02 PM PDT 24
Finished Jun 23 05:17:29 PM PDT 24
Peak memory 206400 kb
Host smart-a4d6fbe7-4cd2-49ef-89ea-527fd5afe778
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3012720631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.3012720631
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.4123381561
Short name T1221
Test name
Test status
Simulation time 239474354 ps
CPU time 0.87 seconds
Started Jun 23 05:15:12 PM PDT 24
Finished Jun 23 05:15:13 PM PDT 24
Peak memory 206120 kb
Host smart-31677f70-5a26-4099-9aa7-d5c43be19503
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4123381561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.4123381561
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.460315410
Short name T682
Test name
Test status
Simulation time 220059821 ps
CPU time 0.9 seconds
Started Jun 23 05:15:00 PM PDT 24
Finished Jun 23 05:15:01 PM PDT 24
Peak memory 206132 kb
Host smart-9b633f17-7d7c-4235-998a-987331d6b7d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46031
5410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.460315410
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.4075027294
Short name T1843
Test name
Test status
Simulation time 5632980249 ps
CPU time 55.01 seconds
Started Jun 23 05:15:00 PM PDT 24
Finished Jun 23 05:15:55 PM PDT 24
Peak memory 206268 kb
Host smart-7ea7c21d-84bc-4d8e-af83-0fae41df5ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40750
27294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.4075027294
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.3491880139
Short name T1166
Test name
Test status
Simulation time 10273795471 ps
CPU time 257.68 seconds
Started Jun 23 05:15:05 PM PDT 24
Finished Jun 23 05:19:23 PM PDT 24
Peak memory 206340 kb
Host smart-2592f910-d391-4fb7-9f1f-5748097d8912
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3491880139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3491880139
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.1473335768
Short name T1899
Test name
Test status
Simulation time 184741781 ps
CPU time 0.81 seconds
Started Jun 23 05:15:07 PM PDT 24
Finished Jun 23 05:15:09 PM PDT 24
Peak memory 206120 kb
Host smart-c72d224a-8a43-4cae-a2f0-2d2a2f1384d2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1473335768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1473335768
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2609823787
Short name T1144
Test name
Test status
Simulation time 152857461 ps
CPU time 0.75 seconds
Started Jun 23 05:15:00 PM PDT 24
Finished Jun 23 05:15:01 PM PDT 24
Peak memory 206012 kb
Host smart-29061480-da39-4b13-b267-5323fe05f2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26098
23787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2609823787
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.611725708
Short name T1755
Test name
Test status
Simulation time 180649481 ps
CPU time 0.86 seconds
Started Jun 23 05:14:59 PM PDT 24
Finished Jun 23 05:15:01 PM PDT 24
Peak memory 206044 kb
Host smart-43cb34e5-a984-406d-a3df-74ce4b2e2e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61172
5708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.611725708
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2770860460
Short name T637
Test name
Test status
Simulation time 167031756 ps
CPU time 0.83 seconds
Started Jun 23 05:15:02 PM PDT 24
Finished Jun 23 05:15:03 PM PDT 24
Peak memory 206108 kb
Host smart-a9371f5a-3f9f-4564-a777-3b8f05060bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27708
60460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2770860460
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1011582139
Short name T1831
Test name
Test status
Simulation time 162853195 ps
CPU time 0.83 seconds
Started Jun 23 05:15:02 PM PDT 24
Finished Jun 23 05:15:03 PM PDT 24
Peak memory 206056 kb
Host smart-1f0ad209-9895-4907-8fba-b5a82c1c49ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10115
82139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1011582139
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1831125792
Short name T2254
Test name
Test status
Simulation time 195986793 ps
CPU time 0.81 seconds
Started Jun 23 05:15:07 PM PDT 24
Finished Jun 23 05:15:09 PM PDT 24
Peak memory 206080 kb
Host smart-f8efcfef-5226-4fa0-80b3-83a5d0d2723a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18311
25792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1831125792
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.4088289667
Short name T1104
Test name
Test status
Simulation time 244419538 ps
CPU time 1.01 seconds
Started Jun 23 05:15:04 PM PDT 24
Finished Jun 23 05:15:06 PM PDT 24
Peak memory 205900 kb
Host smart-29dd7fca-7b0a-48a5-9091-304ae0b15cc8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4088289667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.4088289667
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1581274736
Short name T2376
Test name
Test status
Simulation time 143381128 ps
CPU time 0.74 seconds
Started Jun 23 05:15:07 PM PDT 24
Finished Jun 23 05:15:08 PM PDT 24
Peak memory 206060 kb
Host smart-cb5a949a-9c4d-4369-95a7-7719caaabaf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15812
74736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1581274736
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1530800142
Short name T1357
Test name
Test status
Simulation time 93074457 ps
CPU time 0.7 seconds
Started Jun 23 05:15:08 PM PDT 24
Finished Jun 23 05:15:09 PM PDT 24
Peak memory 206040 kb
Host smart-770c0881-6326-437c-9443-d1defe7e99d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15308
00142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1530800142
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.864810192
Short name T2446
Test name
Test status
Simulation time 216045837 ps
CPU time 0.91 seconds
Started Jun 23 05:15:02 PM PDT 24
Finished Jun 23 05:15:04 PM PDT 24
Peak memory 206084 kb
Host smart-93c4a4e9-9d43-47a4-a7a1-0d8529e3836c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86481
0192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.864810192
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.805359433
Short name T2064
Test name
Test status
Simulation time 182334132 ps
CPU time 0.83 seconds
Started Jun 23 05:15:01 PM PDT 24
Finished Jun 23 05:15:02 PM PDT 24
Peak memory 206068 kb
Host smart-8d8f406b-5849-4979-a10f-8ac34d936f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80535
9433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.805359433
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.6752606
Short name T702
Test name
Test status
Simulation time 7666369248 ps
CPU time 34.55 seconds
Started Jun 23 05:15:03 PM PDT 24
Finished Jun 23 05:15:37 PM PDT 24
Peak memory 206392 kb
Host smart-4996f037-2edb-49ef-86b5-178fddb5e35c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=6752606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.6752606
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2725921644
Short name T1950
Test name
Test status
Simulation time 21230378042 ps
CPU time 123.33 seconds
Started Jun 23 05:15:02 PM PDT 24
Finished Jun 23 05:17:06 PM PDT 24
Peak memory 206348 kb
Host smart-c5666e67-c869-4fb5-8c68-3bdaabe410d5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2725921644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2725921644
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.261961004
Short name T762
Test name
Test status
Simulation time 33228499520 ps
CPU time 830.95 seconds
Started Jun 23 05:15:01 PM PDT 24
Finished Jun 23 05:28:52 PM PDT 24
Peak memory 206324 kb
Host smart-8eedfda1-1c07-4524-ac38-4707f952ee1b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=261961004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.261961004
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.2040907274
Short name T1167
Test name
Test status
Simulation time 230381709 ps
CPU time 0.87 seconds
Started Jun 23 05:15:06 PM PDT 24
Finished Jun 23 05:15:08 PM PDT 24
Peak memory 206072 kb
Host smart-b64976e3-c70d-4156-8d94-db831af2aeb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20409
07274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.2040907274
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.30626628
Short name T1052
Test name
Test status
Simulation time 216964524 ps
CPU time 0.9 seconds
Started Jun 23 05:15:06 PM PDT 24
Finished Jun 23 05:15:07 PM PDT 24
Peak memory 206108 kb
Host smart-bc04e574-d16c-4d90-a5fe-e71630ae3c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30626
628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.30626628
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.982719635
Short name T899
Test name
Test status
Simulation time 146094862 ps
CPU time 0.8 seconds
Started Jun 23 05:15:07 PM PDT 24
Finished Jun 23 05:15:09 PM PDT 24
Peak memory 206004 kb
Host smart-b242ce8a-e96e-433a-926b-cdab1ad06966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98271
9635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.982719635
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.950008300
Short name T2462
Test name
Test status
Simulation time 372530130 ps
CPU time 1.32 seconds
Started Jun 23 05:15:00 PM PDT 24
Finished Jun 23 05:15:01 PM PDT 24
Peak memory 206268 kb
Host smart-d549a797-c8d2-4d4d-a934-15c8a0d832a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95000
8300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.950008300
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.3456512195
Short name T373
Test name
Test status
Simulation time 147715211 ps
CPU time 0.78 seconds
Started Jun 23 05:15:08 PM PDT 24
Finished Jun 23 05:15:09 PM PDT 24
Peak memory 206096 kb
Host smart-90491fd4-9de1-4d82-8331-cbe7ea400b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34565
12195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.3456512195
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2952532101
Short name T49
Test name
Test status
Simulation time 153334569 ps
CPU time 0.83 seconds
Started Jun 23 05:15:05 PM PDT 24
Finished Jun 23 05:15:06 PM PDT 24
Peak memory 206052 kb
Host smart-a4dd288b-80fc-48c5-bcb3-89887f5156bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29525
32101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2952532101
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2356055971
Short name T497
Test name
Test status
Simulation time 226781445 ps
CPU time 0.97 seconds
Started Jun 23 05:15:06 PM PDT 24
Finished Jun 23 05:15:08 PM PDT 24
Peak memory 206100 kb
Host smart-75703e3a-dc2e-4d3e-a7f3-b476908d32e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23560
55971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2356055971
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.1522215762
Short name T1213
Test name
Test status
Simulation time 10364196539 ps
CPU time 298.13 seconds
Started Jun 23 05:15:00 PM PDT 24
Finished Jun 23 05:19:59 PM PDT 24
Peak memory 206288 kb
Host smart-2cb73e19-c6d6-4895-8c1b-6b589eb72f46
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1522215762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.1522215762
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2013587066
Short name T650
Test name
Test status
Simulation time 173734607 ps
CPU time 0.78 seconds
Started Jun 23 05:15:06 PM PDT 24
Finished Jun 23 05:15:08 PM PDT 24
Peak memory 206096 kb
Host smart-a037826b-531b-4da4-a178-1631c069fc64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20135
87066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2013587066
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.955138869
Short name T331
Test name
Test status
Simulation time 254666019 ps
CPU time 0.86 seconds
Started Jun 23 05:15:05 PM PDT 24
Finished Jun 23 05:15:06 PM PDT 24
Peak memory 206040 kb
Host smart-9788ea28-f964-4fb7-a72a-f616d36c4e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95513
8869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.955138869
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.4170439607
Short name T447
Test name
Test status
Simulation time 8739351622 ps
CPU time 85.08 seconds
Started Jun 23 05:15:06 PM PDT 24
Finished Jun 23 05:16:32 PM PDT 24
Peak memory 206376 kb
Host smart-39409817-58b0-4d46-8b67-867f2b762090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41704
39607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.4170439607
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.2911951643
Short name T719
Test name
Test status
Simulation time 3699209982 ps
CPU time 4.95 seconds
Started Jun 23 05:17:01 PM PDT 24
Finished Jun 23 05:17:06 PM PDT 24
Peak memory 206360 kb
Host smart-d6c8d1ef-936c-4678-a11a-0f9acf61c4d5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2911951643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.2911951643
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.3891339685
Short name T1680
Test name
Test status
Simulation time 13350995488 ps
CPU time 13.86 seconds
Started Jun 23 05:17:00 PM PDT 24
Finished Jun 23 05:17:14 PM PDT 24
Peak memory 206376 kb
Host smart-8d0c59c4-b9c0-417b-aec8-43085af2c613
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3891339685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.3891339685
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.2856633131
Short name T1505
Test name
Test status
Simulation time 23463210828 ps
CPU time 27.54 seconds
Started Jun 23 05:17:01 PM PDT 24
Finished Jun 23 05:17:29 PM PDT 24
Peak memory 206184 kb
Host smart-07ad8a37-c251-4056-933f-be3e5a67ec09
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2856633131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.2856633131
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.7724695
Short name T380
Test name
Test status
Simulation time 194730301 ps
CPU time 0.86 seconds
Started Jun 23 05:17:00 PM PDT 24
Finished Jun 23 05:17:02 PM PDT 24
Peak memory 206108 kb
Host smart-c4d4e1fd-fff1-458f-a0bc-4cb45673bdef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77246
95 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.7724695
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.1435330517
Short name T301
Test name
Test status
Simulation time 149531521 ps
CPU time 0.75 seconds
Started Jun 23 05:17:01 PM PDT 24
Finished Jun 23 05:17:02 PM PDT 24
Peak memory 206024 kb
Host smart-36f5f462-c4fb-4b8a-bfb8-7156ba66e857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14353
30517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.1435330517
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.879389664
Short name T1214
Test name
Test status
Simulation time 182040816 ps
CPU time 0.87 seconds
Started Jun 23 05:17:01 PM PDT 24
Finished Jun 23 05:17:02 PM PDT 24
Peak memory 206028 kb
Host smart-04267663-36fd-4555-90e7-963a79ab26f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87938
9664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.879389664
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.536839610
Short name T2116
Test name
Test status
Simulation time 1207050054 ps
CPU time 2.64 seconds
Started Jun 23 05:17:01 PM PDT 24
Finished Jun 23 05:17:04 PM PDT 24
Peak memory 206288 kb
Host smart-78b89407-e71b-42ac-9f92-f890bc333965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53683
9610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.536839610
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.4068527629
Short name T177
Test name
Test status
Simulation time 22066909009 ps
CPU time 41.4 seconds
Started Jun 23 05:17:03 PM PDT 24
Finished Jun 23 05:17:45 PM PDT 24
Peak memory 206424 kb
Host smart-c7338fa4-2cfd-417b-ade4-e797a1ef3e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40685
27629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.4068527629
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.211668040
Short name T721
Test name
Test status
Simulation time 405121515 ps
CPU time 1.32 seconds
Started Jun 23 05:17:03 PM PDT 24
Finished Jun 23 05:17:05 PM PDT 24
Peak memory 206108 kb
Host smart-b156bae9-cef7-4b13-8da9-d34dd2925a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21166
8040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.211668040
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.1939171893
Short name T817
Test name
Test status
Simulation time 136183417 ps
CPU time 0.75 seconds
Started Jun 23 05:17:02 PM PDT 24
Finished Jun 23 05:17:03 PM PDT 24
Peak memory 206260 kb
Host smart-ffc8cf37-0754-4df9-b61e-44f9fff8ac30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19391
71893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.1939171893
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1919217129
Short name T430
Test name
Test status
Simulation time 51886008 ps
CPU time 0.74 seconds
Started Jun 23 05:17:03 PM PDT 24
Finished Jun 23 05:17:04 PM PDT 24
Peak memory 206088 kb
Host smart-4a6921cd-9f09-48f0-89b4-3e68604fe44f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19192
17129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1919217129
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.3243804439
Short name T393
Test name
Test status
Simulation time 994942629 ps
CPU time 2.43 seconds
Started Jun 23 05:17:01 PM PDT 24
Finished Jun 23 05:17:03 PM PDT 24
Peak memory 206264 kb
Host smart-a22d3460-d080-4484-8b99-cf828fff2bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32438
04439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.3243804439
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.417648517
Short name T1793
Test name
Test status
Simulation time 361836878 ps
CPU time 2.18 seconds
Started Jun 23 05:17:02 PM PDT 24
Finished Jun 23 05:17:04 PM PDT 24
Peak memory 206288 kb
Host smart-d1872402-29b1-413c-9011-50253e31c94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41764
8517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.417648517
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3896303253
Short name T436
Test name
Test status
Simulation time 193661073 ps
CPU time 0.84 seconds
Started Jun 23 05:17:11 PM PDT 24
Finished Jun 23 05:17:12 PM PDT 24
Peak memory 205996 kb
Host smart-2d03ae58-bde8-4640-9be9-d38c65114bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38963
03253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3896303253
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3020044214
Short name T727
Test name
Test status
Simulation time 144563165 ps
CPU time 0.77 seconds
Started Jun 23 05:17:08 PM PDT 24
Finished Jun 23 05:17:09 PM PDT 24
Peak memory 206096 kb
Host smart-776ff82a-6892-4405-a060-ad6c85235f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30200
44214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3020044214
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.726079007
Short name T1551
Test name
Test status
Simulation time 280422053 ps
CPU time 0.9 seconds
Started Jun 23 05:17:01 PM PDT 24
Finished Jun 23 05:17:03 PM PDT 24
Peak memory 206104 kb
Host smart-549e5739-83b2-43f0-90c0-ba4d2e0cf35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72607
9007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.726079007
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.3949174502
Short name T1603
Test name
Test status
Simulation time 6703045858 ps
CPU time 192.69 seconds
Started Jun 23 05:17:02 PM PDT 24
Finished Jun 23 05:20:15 PM PDT 24
Peak memory 206284 kb
Host smart-7621c485-4806-4329-bc8a-ec2c0dec623d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3949174502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.3949174502
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.1182472701
Short name T2124
Test name
Test status
Simulation time 194596854 ps
CPU time 0.88 seconds
Started Jun 23 05:17:03 PM PDT 24
Finished Jun 23 05:17:04 PM PDT 24
Peak memory 205984 kb
Host smart-744606f1-9f02-43c8-9789-9b1ef8cdaca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11824
72701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.1182472701
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.2255509122
Short name T1276
Test name
Test status
Simulation time 23276458662 ps
CPU time 22.25 seconds
Started Jun 23 05:17:01 PM PDT 24
Finished Jun 23 05:17:24 PM PDT 24
Peak memory 206096 kb
Host smart-1ef4006e-69fb-4127-abc5-d5e8cc52ed54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22555
09122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.2255509122
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1800049914
Short name T826
Test name
Test status
Simulation time 3326091150 ps
CPU time 3.9 seconds
Started Jun 23 05:17:07 PM PDT 24
Finished Jun 23 05:17:12 PM PDT 24
Peak memory 206176 kb
Host smart-b05510fc-a8cd-49df-855f-f3afa612af48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18000
49914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1800049914
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.320470175
Short name T1017
Test name
Test status
Simulation time 14106248923 ps
CPU time 132.02 seconds
Started Jun 23 05:17:07 PM PDT 24
Finished Jun 23 05:19:19 PM PDT 24
Peak memory 206300 kb
Host smart-132a40fd-a068-44fd-b7ae-24f7545b56fd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=320470175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.320470175
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.75639525
Short name T1258
Test name
Test status
Simulation time 237824157 ps
CPU time 0.94 seconds
Started Jun 23 05:17:08 PM PDT 24
Finished Jun 23 05:17:09 PM PDT 24
Peak memory 206056 kb
Host smart-3a89b766-3ed6-4ae3-863b-3c4029a331b0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=75639525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.75639525
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3804271068
Short name T1868
Test name
Test status
Simulation time 183717734 ps
CPU time 0.81 seconds
Started Jun 23 05:17:08 PM PDT 24
Finished Jun 23 05:17:09 PM PDT 24
Peak memory 206044 kb
Host smart-0d5d19fd-a937-4406-9214-62727007ad39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38042
71068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3804271068
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.3814568022
Short name T472
Test name
Test status
Simulation time 10230584776 ps
CPU time 73.24 seconds
Started Jun 23 05:17:07 PM PDT 24
Finished Jun 23 05:18:21 PM PDT 24
Peak memory 206360 kb
Host smart-989f69cd-f160-4bc0-9c98-89930a173cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38145
68022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.3814568022
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.3204262428
Short name T2353
Test name
Test status
Simulation time 9821285898 ps
CPU time 82.04 seconds
Started Jun 23 05:17:10 PM PDT 24
Finished Jun 23 05:18:33 PM PDT 24
Peak memory 205956 kb
Host smart-f1a5e1a1-ba28-4cd1-b39e-21b26c465eb3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3204262428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.3204262428
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1373422269
Short name T1331
Test name
Test status
Simulation time 177109140 ps
CPU time 0.79 seconds
Started Jun 23 05:17:09 PM PDT 24
Finished Jun 23 05:17:10 PM PDT 24
Peak memory 206128 kb
Host smart-4962ad3b-aa1e-43eb-aa72-dc1b2ccca4be
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1373422269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1373422269
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3053769087
Short name T796
Test name
Test status
Simulation time 185335274 ps
CPU time 0.8 seconds
Started Jun 23 05:17:05 PM PDT 24
Finished Jun 23 05:17:06 PM PDT 24
Peak memory 206112 kb
Host smart-8e8f8711-43b4-4f1c-b721-98e191668fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30537
69087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3053769087
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2274847246
Short name T1056
Test name
Test status
Simulation time 171701097 ps
CPU time 0.83 seconds
Started Jun 23 05:17:10 PM PDT 24
Finished Jun 23 05:17:11 PM PDT 24
Peak memory 205196 kb
Host smart-84258335-3053-4167-af3c-9491cd89f146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22748
47246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2274847246
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.3326231114
Short name T1784
Test name
Test status
Simulation time 263872135 ps
CPU time 0.9 seconds
Started Jun 23 05:17:07 PM PDT 24
Finished Jun 23 05:17:08 PM PDT 24
Peak memory 206096 kb
Host smart-298e2be9-a502-4671-ad6b-f346de3096ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33262
31114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3326231114
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2391091463
Short name T632
Test name
Test status
Simulation time 149326691 ps
CPU time 0.78 seconds
Started Jun 23 05:17:07 PM PDT 24
Finished Jun 23 05:17:08 PM PDT 24
Peak memory 206108 kb
Host smart-cd02b88b-b9d5-45e6-8bc7-1d2defc2c304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23910
91463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2391091463
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.271219582
Short name T2275
Test name
Test status
Simulation time 222319329 ps
CPU time 0.93 seconds
Started Jun 23 05:17:09 PM PDT 24
Finished Jun 23 05:17:11 PM PDT 24
Peak memory 206100 kb
Host smart-edb76fd8-00af-47ea-b301-b0b52f880cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27121
9582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.271219582
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.133411337
Short name T1928
Test name
Test status
Simulation time 303564432 ps
CPU time 1.02 seconds
Started Jun 23 05:17:06 PM PDT 24
Finished Jun 23 05:17:08 PM PDT 24
Peak memory 206136 kb
Host smart-b4333d6a-a9a6-457f-967f-52c2455083f9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=133411337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.133411337
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1621743828
Short name T694
Test name
Test status
Simulation time 182546669 ps
CPU time 0.8 seconds
Started Jun 23 05:17:07 PM PDT 24
Finished Jun 23 05:17:08 PM PDT 24
Peak memory 206056 kb
Host smart-feb88061-0a6a-4690-a381-108a8028938f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16217
43828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1621743828
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1771189074
Short name T1038
Test name
Test status
Simulation time 39687386 ps
CPU time 0.62 seconds
Started Jun 23 05:17:06 PM PDT 24
Finished Jun 23 05:17:07 PM PDT 24
Peak memory 206104 kb
Host smart-ab06d9fe-4d68-4ba7-a564-ca634970472e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17711
89074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1771189074
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1627465385
Short name T2019
Test name
Test status
Simulation time 13802238828 ps
CPU time 35.83 seconds
Started Jun 23 05:17:08 PM PDT 24
Finished Jun 23 05:17:44 PM PDT 24
Peak memory 206400 kb
Host smart-c64545a4-5de5-4c0a-b803-4be58e15f01e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16274
65385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1627465385
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.4286394153
Short name T366
Test name
Test status
Simulation time 186418094 ps
CPU time 0.83 seconds
Started Jun 23 05:17:05 PM PDT 24
Finished Jun 23 05:17:07 PM PDT 24
Peak memory 206104 kb
Host smart-f7a0590e-949d-4a3e-9142-53490432be66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42863
94153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.4286394153
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2710694676
Short name T2388
Test name
Test status
Simulation time 208120930 ps
CPU time 0.85 seconds
Started Jun 23 05:17:08 PM PDT 24
Finished Jun 23 05:17:09 PM PDT 24
Peak memory 205996 kb
Host smart-f29f5631-6815-4817-8ad7-02c83d799e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27106
94676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2710694676
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.2139420387
Short name T859
Test name
Test status
Simulation time 179713993 ps
CPU time 0.8 seconds
Started Jun 23 05:17:10 PM PDT 24
Finished Jun 23 05:17:11 PM PDT 24
Peak memory 206004 kb
Host smart-e678b9fa-cf24-460d-b548-3f8567242caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21394
20387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.2139420387
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.3970048694
Short name T1566
Test name
Test status
Simulation time 215258313 ps
CPU time 0.86 seconds
Started Jun 23 05:17:07 PM PDT 24
Finished Jun 23 05:17:08 PM PDT 24
Peak memory 206112 kb
Host smart-932a08bb-ccb1-45da-b9d9-dbe5710a7ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39700
48694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.3970048694
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1306388804
Short name T932
Test name
Test status
Simulation time 139117541 ps
CPU time 0.71 seconds
Started Jun 23 05:17:07 PM PDT 24
Finished Jun 23 05:17:09 PM PDT 24
Peak memory 205988 kb
Host smart-e0d9fb76-54bc-4324-a014-f4d74bd496d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13063
88804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1306388804
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.235361109
Short name T1063
Test name
Test status
Simulation time 158273846 ps
CPU time 0.72 seconds
Started Jun 23 05:17:10 PM PDT 24
Finished Jun 23 05:17:11 PM PDT 24
Peak memory 205916 kb
Host smart-4a94352a-bc94-4053-80bf-f102de07f505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23536
1109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.235361109
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.4046052499
Short name T1313
Test name
Test status
Simulation time 199148135 ps
CPU time 0.81 seconds
Started Jun 23 05:17:08 PM PDT 24
Finished Jun 23 05:17:09 PM PDT 24
Peak memory 206032 kb
Host smart-d73d725e-f369-414a-a21c-7fd0cdb06bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40460
52499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.4046052499
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2536958655
Short name T540
Test name
Test status
Simulation time 199690875 ps
CPU time 0.96 seconds
Started Jun 23 05:17:00 PM PDT 24
Finished Jun 23 05:17:02 PM PDT 24
Peak memory 206036 kb
Host smart-d4047c85-e49d-492f-9b8a-5da7b2da7dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25369
58655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2536958655
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2917172249
Short name T531
Test name
Test status
Simulation time 5842509550 ps
CPU time 40.91 seconds
Started Jun 23 05:17:04 PM PDT 24
Finished Jun 23 05:17:46 PM PDT 24
Peak memory 206340 kb
Host smart-e3effff7-94a2-40aa-8037-501dfa58263c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2917172249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2917172249
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.4007691470
Short name T643
Test name
Test status
Simulation time 147761512 ps
CPU time 0.72 seconds
Started Jun 23 05:17:10 PM PDT 24
Finished Jun 23 05:17:11 PM PDT 24
Peak memory 205924 kb
Host smart-4ff89838-891f-44e2-8dab-9b9ce1a10381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40076
91470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.4007691470
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1902833702
Short name T423
Test name
Test status
Simulation time 163327348 ps
CPU time 0.78 seconds
Started Jun 23 05:17:10 PM PDT 24
Finished Jun 23 05:17:11 PM PDT 24
Peak memory 205996 kb
Host smart-c35d571d-f47a-4d97-bba5-0dcbb4a2ed8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19028
33702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1902833702
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.125751079
Short name T1233
Test name
Test status
Simulation time 9354096049 ps
CPU time 83.41 seconds
Started Jun 23 05:17:09 PM PDT 24
Finished Jun 23 05:18:33 PM PDT 24
Peak memory 206132 kb
Host smart-16e0ca38-fe49-4b2e-9a27-79c4e7722edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12575
1079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.125751079
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1312152880
Short name T1627
Test name
Test status
Simulation time 3827962695 ps
CPU time 4.93 seconds
Started Jun 23 05:17:10 PM PDT 24
Finished Jun 23 05:17:15 PM PDT 24
Peak memory 205264 kb
Host smart-d00e3176-bd69-4d49-bfd7-335d248eb5d0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1312152880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.1312152880
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.2827639733
Short name T1115
Test name
Test status
Simulation time 13329726539 ps
CPU time 13.53 seconds
Started Jun 23 05:17:12 PM PDT 24
Finished Jun 23 05:17:26 PM PDT 24
Peak memory 206356 kb
Host smart-7745ef26-a7df-48d3-acab-e7881e8fd909
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2827639733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.2827639733
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.3889792113
Short name T788
Test name
Test status
Simulation time 23451503679 ps
CPU time 24.13 seconds
Started Jun 23 05:17:11 PM PDT 24
Finished Jun 23 05:17:36 PM PDT 24
Peak memory 206352 kb
Host smart-f4de2aa1-0588-4301-b48f-c684086374d3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3889792113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.3889792113
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.100777954
Short name T1447
Test name
Test status
Simulation time 151812236 ps
CPU time 0.8 seconds
Started Jun 23 05:17:12 PM PDT 24
Finished Jun 23 05:17:14 PM PDT 24
Peak memory 206016 kb
Host smart-95180dac-8607-4909-80b0-5c8f79dc499c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10077
7954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.100777954
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.853765809
Short name T906
Test name
Test status
Simulation time 143401100 ps
CPU time 0.77 seconds
Started Jun 23 05:17:12 PM PDT 24
Finished Jun 23 05:17:13 PM PDT 24
Peak memory 206048 kb
Host smart-d86de7cf-06d9-48ba-bd28-4fadd9aa795e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85376
5809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.853765809
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.1994498569
Short name T1499
Test name
Test status
Simulation time 360445871 ps
CPU time 1.28 seconds
Started Jun 23 05:17:12 PM PDT 24
Finished Jun 23 05:17:14 PM PDT 24
Peak memory 206020 kb
Host smart-fc99f55f-d561-4909-a414-ca534c9c9ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19944
98569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.1994498569
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.1962954381
Short name T98
Test name
Test status
Simulation time 1233696408 ps
CPU time 2.63 seconds
Started Jun 23 05:17:12 PM PDT 24
Finished Jun 23 05:17:16 PM PDT 24
Peak memory 206248 kb
Host smart-55636429-9969-4d22-a3b5-b89d3f9283da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19629
54381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.1962954381
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.954399373
Short name T2300
Test name
Test status
Simulation time 8912586087 ps
CPU time 17.54 seconds
Started Jun 23 05:17:13 PM PDT 24
Finished Jun 23 05:17:31 PM PDT 24
Peak memory 206348 kb
Host smart-29b6b0fd-cb13-4eb8-96fd-e03c84b42749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95439
9373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.954399373
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.2321351477
Short name T2236
Test name
Test status
Simulation time 413633459 ps
CPU time 1.24 seconds
Started Jun 23 05:17:13 PM PDT 24
Finished Jun 23 05:17:15 PM PDT 24
Peak memory 206108 kb
Host smart-9d97a534-3722-4d92-853d-040455f9162d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23213
51477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.2321351477
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.4143055649
Short name T2368
Test name
Test status
Simulation time 141635368 ps
CPU time 0.72 seconds
Started Jun 23 05:17:12 PM PDT 24
Finished Jun 23 05:17:13 PM PDT 24
Peak memory 206036 kb
Host smart-1dae1104-afad-4a02-bf65-b6b630c7006e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41430
55649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.4143055649
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2251241555
Short name T1087
Test name
Test status
Simulation time 38978958 ps
CPU time 0.68 seconds
Started Jun 23 05:17:13 PM PDT 24
Finished Jun 23 05:17:14 PM PDT 24
Peak memory 206284 kb
Host smart-5cd8f262-1632-4daa-a551-9277ad88a903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22512
41555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2251241555
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.352449933
Short name T1416
Test name
Test status
Simulation time 969531926 ps
CPU time 2.25 seconds
Started Jun 23 05:17:13 PM PDT 24
Finished Jun 23 05:17:16 PM PDT 24
Peak memory 206268 kb
Host smart-a01e4ef9-e4b8-4d8a-a5a7-902f76e91a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35244
9933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.352449933
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.2188640366
Short name T1940
Test name
Test status
Simulation time 238497739 ps
CPU time 1.37 seconds
Started Jun 23 05:17:12 PM PDT 24
Finished Jun 23 05:17:14 PM PDT 24
Peak memory 206308 kb
Host smart-4e1b0715-3c26-441d-b0ba-7e0d7bd040df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21886
40366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.2188640366
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2024130971
Short name T1468
Test name
Test status
Simulation time 250698584 ps
CPU time 0.94 seconds
Started Jun 23 05:17:19 PM PDT 24
Finished Jun 23 05:17:20 PM PDT 24
Peak memory 206100 kb
Host smart-b71960f8-3d3c-4212-9a47-66b3df087eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20241
30971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2024130971
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.2637708376
Short name T2451
Test name
Test status
Simulation time 152560875 ps
CPU time 0.79 seconds
Started Jun 23 05:17:19 PM PDT 24
Finished Jun 23 05:17:20 PM PDT 24
Peak memory 206096 kb
Host smart-dd009a7d-476f-4b17-95fb-97aaf3c5f667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26377
08376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.2637708376
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.4199761793
Short name T813
Test name
Test status
Simulation time 177820768 ps
CPU time 0.8 seconds
Started Jun 23 05:17:12 PM PDT 24
Finished Jun 23 05:17:14 PM PDT 24
Peak memory 206068 kb
Host smart-b6f8ae2c-2fea-42a0-b08e-e87fd3336396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41997
61793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.4199761793
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1009325863
Short name T700
Test name
Test status
Simulation time 232592734 ps
CPU time 0.94 seconds
Started Jun 23 05:17:11 PM PDT 24
Finished Jun 23 05:17:13 PM PDT 24
Peak memory 206092 kb
Host smart-fd0fd326-efa6-4a2c-9571-af88ead05cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10093
25863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1009325863
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.507639631
Short name T2256
Test name
Test status
Simulation time 23316506329 ps
CPU time 22.92 seconds
Started Jun 23 05:17:11 PM PDT 24
Finished Jun 23 05:17:35 PM PDT 24
Peak memory 206096 kb
Host smart-8efca6c4-7080-4b90-ab05-56927e0dbfbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50763
9631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.507639631
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.1355617727
Short name T1926
Test name
Test status
Simulation time 3373002773 ps
CPU time 3.98 seconds
Started Jun 23 05:17:12 PM PDT 24
Finished Jun 23 05:17:17 PM PDT 24
Peak memory 206128 kb
Host smart-d06f6b6d-e16f-4d62-a4a4-952b99f0df78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13556
17727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1355617727
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.4194819639
Short name T949
Test name
Test status
Simulation time 7852239103 ps
CPU time 56.1 seconds
Started Jun 23 05:17:16 PM PDT 24
Finished Jun 23 05:18:12 PM PDT 24
Peak memory 206420 kb
Host smart-30e46f98-d231-46c0-a8d0-2771f29680c9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4194819639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.4194819639
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.3738709006
Short name T353
Test name
Test status
Simulation time 243237230 ps
CPU time 0.88 seconds
Started Jun 23 05:17:21 PM PDT 24
Finished Jun 23 05:17:22 PM PDT 24
Peak memory 206128 kb
Host smart-54393982-c5ef-4b3f-a892-4310ffb260be
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3738709006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.3738709006
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.567708339
Short name T360
Test name
Test status
Simulation time 186081725 ps
CPU time 0.86 seconds
Started Jun 23 05:17:13 PM PDT 24
Finished Jun 23 05:17:14 PM PDT 24
Peak memory 206132 kb
Host smart-2552049a-a238-41a4-a6af-952346e67935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56770
8339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.567708339
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.3590662076
Short name T1486
Test name
Test status
Simulation time 9799678572 ps
CPU time 71.39 seconds
Started Jun 23 05:17:13 PM PDT 24
Finished Jun 23 05:18:25 PM PDT 24
Peak memory 206356 kb
Host smart-63612a94-41da-45ab-a25f-931c4a32763b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35906
62076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.3590662076
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.2948431346
Short name T671
Test name
Test status
Simulation time 6912091283 ps
CPU time 185.55 seconds
Started Jun 23 05:17:14 PM PDT 24
Finished Jun 23 05:20:20 PM PDT 24
Peak memory 206356 kb
Host smart-debbb250-1d14-426e-9239-9225df2379a9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2948431346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.2948431346
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.2962410289
Short name T1359
Test name
Test status
Simulation time 186010700 ps
CPU time 0.79 seconds
Started Jun 23 05:17:18 PM PDT 24
Finished Jun 23 05:17:19 PM PDT 24
Peak memory 206048 kb
Host smart-0acb6dd7-9b79-4b37-80f8-68671e1411a6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2962410289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.2962410289
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.963514571
Short name T1989
Test name
Test status
Simulation time 157657803 ps
CPU time 0.82 seconds
Started Jun 23 05:17:13 PM PDT 24
Finished Jun 23 05:17:14 PM PDT 24
Peak memory 206124 kb
Host smart-b9594a6a-6462-4388-bd6a-52b790d418db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96351
4571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.963514571
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.1626449125
Short name T483
Test name
Test status
Simulation time 182526834 ps
CPU time 0.83 seconds
Started Jun 23 05:17:17 PM PDT 24
Finished Jun 23 05:17:18 PM PDT 24
Peak memory 206104 kb
Host smart-86bfcab3-8555-4b95-b32e-c15cdc1ed9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16264
49125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.1626449125
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1741440481
Short name T2302
Test name
Test status
Simulation time 166942674 ps
CPU time 0.81 seconds
Started Jun 23 05:17:13 PM PDT 24
Finished Jun 23 05:17:14 PM PDT 24
Peak memory 206100 kb
Host smart-44046e93-c6f3-463a-992e-35b9ef126c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17414
40481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1741440481
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1607846570
Short name T2472
Test name
Test status
Simulation time 178996557 ps
CPU time 0.85 seconds
Started Jun 23 05:17:14 PM PDT 24
Finished Jun 23 05:17:15 PM PDT 24
Peak memory 206124 kb
Host smart-c5f912d2-6cb2-4450-81f1-7395960c8764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16078
46570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1607846570
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1302073831
Short name T601
Test name
Test status
Simulation time 155264787 ps
CPU time 0.83 seconds
Started Jun 23 05:17:21 PM PDT 24
Finished Jun 23 05:17:22 PM PDT 24
Peak memory 206256 kb
Host smart-e9e85c28-322a-4894-b990-8257e544935b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13020
73831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1302073831
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.971024449
Short name T1298
Test name
Test status
Simulation time 243563831 ps
CPU time 1.02 seconds
Started Jun 23 05:17:20 PM PDT 24
Finished Jun 23 05:17:21 PM PDT 24
Peak memory 206276 kb
Host smart-c3e1be4b-654d-42f5-be84-c3eedb8ce605
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=971024449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.971024449
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3112486714
Short name T1312
Test name
Test status
Simulation time 35100535 ps
CPU time 0.71 seconds
Started Jun 23 05:17:18 PM PDT 24
Finished Jun 23 05:17:19 PM PDT 24
Peak memory 206148 kb
Host smart-402fa324-814d-4c52-8783-887aa79b69a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31124
86714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3112486714
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1367633967
Short name T779
Test name
Test status
Simulation time 17275863765 ps
CPU time 45.6 seconds
Started Jun 23 05:17:14 PM PDT 24
Finished Jun 23 05:18:00 PM PDT 24
Peak memory 206388 kb
Host smart-0b74e9e2-52da-432f-af4f-4331d1b67f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13676
33967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1367633967
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3543302723
Short name T688
Test name
Test status
Simulation time 162983755 ps
CPU time 0.82 seconds
Started Jun 23 05:17:22 PM PDT 24
Finished Jun 23 05:17:23 PM PDT 24
Peak memory 206104 kb
Host smart-8817302d-c86c-4bb3-9722-f1005ffd0b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35433
02723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3543302723
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2970601211
Short name T749
Test name
Test status
Simulation time 195398549 ps
CPU time 0.86 seconds
Started Jun 23 05:17:20 PM PDT 24
Finished Jun 23 05:17:21 PM PDT 24
Peak memory 206100 kb
Host smart-248f8843-aee8-442a-94b9-38723de707cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29706
01211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2970601211
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.3104871663
Short name T2217
Test name
Test status
Simulation time 197257023 ps
CPU time 0.85 seconds
Started Jun 23 05:17:20 PM PDT 24
Finished Jun 23 05:17:21 PM PDT 24
Peak memory 206100 kb
Host smart-d8801219-6a37-4d90-a92e-ba827428993b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31048
71663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.3104871663
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.4079115598
Short name T1533
Test name
Test status
Simulation time 167978047 ps
CPU time 0.79 seconds
Started Jun 23 05:17:21 PM PDT 24
Finished Jun 23 05:17:23 PM PDT 24
Peak memory 206124 kb
Host smart-7ea79af7-079a-4681-9b07-83cfac7a29bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40791
15598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.4079115598
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.458930360
Short name T1361
Test name
Test status
Simulation time 208892321 ps
CPU time 0.92 seconds
Started Jun 23 05:17:22 PM PDT 24
Finished Jun 23 05:17:23 PM PDT 24
Peak memory 206108 kb
Host smart-a63e9381-b967-4ab6-b653-45b94a57ca9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45893
0360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.458930360
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1551075830
Short name T1050
Test name
Test status
Simulation time 188776946 ps
CPU time 0.89 seconds
Started Jun 23 05:17:19 PM PDT 24
Finished Jun 23 05:17:20 PM PDT 24
Peak memory 206156 kb
Host smart-183f6cb9-eabd-4bd9-b785-407ca687d75b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15510
75830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1551075830
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3645976856
Short name T2494
Test name
Test status
Simulation time 143223369 ps
CPU time 0.77 seconds
Started Jun 23 05:17:21 PM PDT 24
Finished Jun 23 05:17:22 PM PDT 24
Peak memory 206104 kb
Host smart-920c42b5-f1a0-4a1c-9821-43a84147534b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36459
76856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3645976856
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1486512874
Short name T782
Test name
Test status
Simulation time 212815121 ps
CPU time 0.92 seconds
Started Jun 23 05:17:09 PM PDT 24
Finished Jun 23 05:17:10 PM PDT 24
Peak memory 206104 kb
Host smart-ae3bf133-2bce-4225-9455-21aeb1f08b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14865
12874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1486512874
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.1011737348
Short name T1767
Test name
Test status
Simulation time 9759784033 ps
CPU time 268.78 seconds
Started Jun 23 05:17:22 PM PDT 24
Finished Jun 23 05:21:51 PM PDT 24
Peak memory 206316 kb
Host smart-8155270e-e600-4243-85f4-44d6701f71fb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1011737348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.1011737348
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3583616862
Short name T1431
Test name
Test status
Simulation time 147829018 ps
CPU time 0.77 seconds
Started Jun 23 05:17:19 PM PDT 24
Finished Jun 23 05:17:20 PM PDT 24
Peak memory 206104 kb
Host smart-e0345da7-cf81-4976-960d-c22f8930871f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35836
16862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3583616862
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.886408383
Short name T1513
Test name
Test status
Simulation time 183136606 ps
CPU time 0.83 seconds
Started Jun 23 05:17:21 PM PDT 24
Finished Jun 23 05:17:22 PM PDT 24
Peak memory 206104 kb
Host smart-74ccf6e6-cf8c-42f1-9641-89400ad91aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88640
8383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.886408383
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.3542563456
Short name T707
Test name
Test status
Simulation time 10959148498 ps
CPU time 331.97 seconds
Started Jun 23 05:17:21 PM PDT 24
Finished Jun 23 05:22:53 PM PDT 24
Peak memory 206304 kb
Host smart-074edd04-ad03-4433-9f04-5db5691078cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35425
63456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.3542563456
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.4144249379
Short name T740
Test name
Test status
Simulation time 3957567139 ps
CPU time 4.57 seconds
Started Jun 23 05:17:21 PM PDT 24
Finished Jun 23 05:17:26 PM PDT 24
Peak memory 206180 kb
Host smart-0e002f7a-2c06-457a-9002-a5b35537f657
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4144249379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.4144249379
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.1536446847
Short name T2242
Test name
Test status
Simulation time 13430799693 ps
CPU time 13.59 seconds
Started Jun 23 05:17:18 PM PDT 24
Finished Jun 23 05:17:32 PM PDT 24
Peak memory 206368 kb
Host smart-fb7a8198-2ed8-4125-b3f8-6acb3a06f387
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1536446847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.1536446847
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.1182208545
Short name T207
Test name
Test status
Simulation time 23319879942 ps
CPU time 24.13 seconds
Started Jun 23 05:17:22 PM PDT 24
Finished Jun 23 05:17:47 PM PDT 24
Peak memory 206168 kb
Host smart-9bc32877-5621-4bd7-819d-4b6ee0e0efd1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1182208545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.1182208545
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2983993318
Short name T1016
Test name
Test status
Simulation time 150421748 ps
CPU time 0.84 seconds
Started Jun 23 05:17:18 PM PDT 24
Finished Jun 23 05:17:20 PM PDT 24
Peak memory 206096 kb
Host smart-6f2cc8a6-da80-48b4-ad31-9750352f42cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29839
93318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2983993318
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.3847509686
Short name T2336
Test name
Test status
Simulation time 143707175 ps
CPU time 0.79 seconds
Started Jun 23 05:17:19 PM PDT 24
Finished Jun 23 05:17:21 PM PDT 24
Peak memory 206104 kb
Host smart-0602cd2c-4a54-4003-9641-b47d9b47c546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38475
09686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.3847509686
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.1535850713
Short name T848
Test name
Test status
Simulation time 289836047 ps
CPU time 1.14 seconds
Started Jun 23 05:17:24 PM PDT 24
Finished Jun 23 05:17:26 PM PDT 24
Peak memory 206048 kb
Host smart-86f1be2a-a761-43fe-926c-95af1d62e7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15358
50713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.1535850713
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.1528731100
Short name T1553
Test name
Test status
Simulation time 520987164 ps
CPU time 1.32 seconds
Started Jun 23 05:17:22 PM PDT 24
Finished Jun 23 05:17:24 PM PDT 24
Peak memory 206100 kb
Host smart-11834ab5-83d1-4da2-8557-ad606beff03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15287
31100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.1528731100
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.2965377947
Short name T672
Test name
Test status
Simulation time 446503155 ps
CPU time 1.34 seconds
Started Jun 23 05:17:23 PM PDT 24
Finished Jun 23 05:17:25 PM PDT 24
Peak memory 206048 kb
Host smart-39dc7e60-43ee-4a3c-b7e5-ea9de9499ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29653
77947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.2965377947
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_enable.1653503234
Short name T1954
Test name
Test status
Simulation time 52394368 ps
CPU time 0.69 seconds
Started Jun 23 05:17:23 PM PDT 24
Finished Jun 23 05:17:24 PM PDT 24
Peak memory 206092 kb
Host smart-5c700a7c-115f-437e-a0ea-2e87a22c24d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16535
03234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1653503234
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.4048487982
Short name T416
Test name
Test status
Simulation time 929999423 ps
CPU time 2.05 seconds
Started Jun 23 05:17:23 PM PDT 24
Finished Jun 23 05:17:25 PM PDT 24
Peak memory 206304 kb
Host smart-a031337e-68e8-461e-b38f-0150f566c37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40484
87982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.4048487982
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2303430234
Short name T1256
Test name
Test status
Simulation time 176663621 ps
CPU time 1.68 seconds
Started Jun 23 05:17:26 PM PDT 24
Finished Jun 23 05:17:28 PM PDT 24
Peak memory 206336 kb
Host smart-07c1fe1d-5ae3-4d63-9fd9-2444062b11ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23034
30234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2303430234
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.1163852362
Short name T1830
Test name
Test status
Simulation time 261816364 ps
CPU time 0.91 seconds
Started Jun 23 05:17:34 PM PDT 24
Finished Jun 23 05:17:36 PM PDT 24
Peak memory 206028 kb
Host smart-fa639b25-5efa-43ed-9402-d56005b86c66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11638
52362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.1163852362
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.4034712970
Short name T1736
Test name
Test status
Simulation time 191496655 ps
CPU time 0.83 seconds
Started Jun 23 05:17:36 PM PDT 24
Finished Jun 23 05:17:38 PM PDT 24
Peak memory 206100 kb
Host smart-6551e6bb-b4f2-4ceb-ba0c-a86d5a6b9591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40347
12970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.4034712970
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.877589105
Short name T981
Test name
Test status
Simulation time 200535110 ps
CPU time 0.94 seconds
Started Jun 23 05:17:24 PM PDT 24
Finished Jun 23 05:17:25 PM PDT 24
Peak memory 206060 kb
Host smart-36597e19-bfa9-4323-bbd9-04988d87fe57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87758
9105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.877589105
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.2513307039
Short name T1478
Test name
Test status
Simulation time 6533060396 ps
CPU time 61.39 seconds
Started Jun 23 05:17:25 PM PDT 24
Finished Jun 23 05:18:27 PM PDT 24
Peak memory 206312 kb
Host smart-b476ecf7-3ed7-4aa8-bc31-020dc4ba132e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2513307039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.2513307039
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.1263206517
Short name T1390
Test name
Test status
Simulation time 174876527 ps
CPU time 0.84 seconds
Started Jun 23 05:17:24 PM PDT 24
Finished Jun 23 05:17:25 PM PDT 24
Peak memory 206044 kb
Host smart-47282316-6b8e-4b07-9ccd-8d48c6ffe937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12632
06517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.1263206517
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2439114600
Short name T310
Test name
Test status
Simulation time 23332443997 ps
CPU time 20.99 seconds
Started Jun 23 05:17:23 PM PDT 24
Finished Jun 23 05:17:45 PM PDT 24
Peak memory 206124 kb
Host smart-ed725c4d-a47c-4950-a1ba-519e2ce736ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24391
14600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2439114600
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.1342320131
Short name T1821
Test name
Test status
Simulation time 3341787244 ps
CPU time 3.84 seconds
Started Jun 23 05:17:24 PM PDT 24
Finished Jun 23 05:17:28 PM PDT 24
Peak memory 206168 kb
Host smart-130bcfdd-3435-4954-a60c-01908dc61e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13423
20131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.1342320131
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.4032640548
Short name T1856
Test name
Test status
Simulation time 6613467650 ps
CPU time 180.24 seconds
Started Jun 23 05:17:32 PM PDT 24
Finished Jun 23 05:20:33 PM PDT 24
Peak memory 206344 kb
Host smart-ccac1a0f-3ec9-4fa4-8ac9-4f7a11ac22c6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4032640548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.4032640548
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.4036019624
Short name T1651
Test name
Test status
Simulation time 251099875 ps
CPU time 0.93 seconds
Started Jun 23 05:17:36 PM PDT 24
Finished Jun 23 05:17:37 PM PDT 24
Peak memory 206132 kb
Host smart-aaabaaa0-efd1-4779-abd1-384ec5ce6e60
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4036019624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.4036019624
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1899419261
Short name T1480
Test name
Test status
Simulation time 185636253 ps
CPU time 0.84 seconds
Started Jun 23 05:17:25 PM PDT 24
Finished Jun 23 05:17:26 PM PDT 24
Peak memory 206088 kb
Host smart-2707245c-9ab3-410b-9b61-61c9c1304d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18994
19261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1899419261
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.340890371
Short name T642
Test name
Test status
Simulation time 13107294978 ps
CPU time 137.41 seconds
Started Jun 23 05:17:32 PM PDT 24
Finished Jun 23 05:19:50 PM PDT 24
Peak memory 206516 kb
Host smart-eae2b02d-672e-40c1-8cc3-330cbd46d373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34089
0371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.340890371
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1454008060
Short name T920
Test name
Test status
Simulation time 15034515353 ps
CPU time 142.42 seconds
Started Jun 23 05:17:30 PM PDT 24
Finished Jun 23 05:19:53 PM PDT 24
Peak memory 206344 kb
Host smart-8cdc07e2-e944-4b59-8cf5-f2e871c07bf2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1454008060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1454008060
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.3816201852
Short name T2496
Test name
Test status
Simulation time 150378706 ps
CPU time 0.82 seconds
Started Jun 23 05:17:37 PM PDT 24
Finished Jun 23 05:17:38 PM PDT 24
Peak memory 206128 kb
Host smart-7c08c15c-d8ba-4861-8777-34ad10aaa983
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3816201852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.3816201852
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1110118779
Short name T2123
Test name
Test status
Simulation time 185876465 ps
CPU time 0.79 seconds
Started Jun 23 05:17:23 PM PDT 24
Finished Jun 23 05:17:24 PM PDT 24
Peak memory 206032 kb
Host smart-3480351d-7e7a-40ae-bff6-42cb12ec01b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11101
18779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1110118779
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.49459794
Short name T2397
Test name
Test status
Simulation time 171781576 ps
CPU time 0.82 seconds
Started Jun 23 05:17:32 PM PDT 24
Finished Jun 23 05:17:34 PM PDT 24
Peak memory 206096 kb
Host smart-0f205be5-5243-4a3c-9eda-f5557e713743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49459
794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.49459794
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.4117684867
Short name T2152
Test name
Test status
Simulation time 193865959 ps
CPU time 0.85 seconds
Started Jun 23 05:17:30 PM PDT 24
Finished Jun 23 05:17:31 PM PDT 24
Peak memory 206076 kb
Host smart-f49db33d-6552-4832-9d3c-d13dbbc41db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41176
84867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.4117684867
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.483588726
Short name T1990
Test name
Test status
Simulation time 194459808 ps
CPU time 0.82 seconds
Started Jun 23 05:17:28 PM PDT 24
Finished Jun 23 05:17:29 PM PDT 24
Peak memory 206044 kb
Host smart-97b814b0-cb71-41f0-8fc8-5f487103d7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48358
8726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.483588726
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1275056164
Short name T1095
Test name
Test status
Simulation time 150369425 ps
CPU time 0.76 seconds
Started Jun 23 05:17:35 PM PDT 24
Finished Jun 23 05:17:36 PM PDT 24
Peak memory 206100 kb
Host smart-c8d15781-6366-4553-a5bd-026090ae4145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12750
56164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1275056164
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.1544794778
Short name T512
Test name
Test status
Simulation time 236753244 ps
CPU time 0.93 seconds
Started Jun 23 05:17:36 PM PDT 24
Finished Jun 23 05:17:37 PM PDT 24
Peak memory 206124 kb
Host smart-fa014e30-1ffb-4fb3-b7f5-c457dc62553c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1544794778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.1544794778
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2858967404
Short name T748
Test name
Test status
Simulation time 137746760 ps
CPU time 0.82 seconds
Started Jun 23 05:17:34 PM PDT 24
Finished Jun 23 05:17:35 PM PDT 24
Peak memory 206064 kb
Host smart-31d4ac39-901e-4399-a829-606131a8bc39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28589
67404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2858967404
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.1482569900
Short name T38
Test name
Test status
Simulation time 53988560 ps
CPU time 0.72 seconds
Started Jun 23 05:17:34 PM PDT 24
Finished Jun 23 05:17:35 PM PDT 24
Peak memory 206104 kb
Host smart-52d5f714-7add-4f77-86c9-cbe0df0a73e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14825
69900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.1482569900
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.538812178
Short name T247
Test name
Test status
Simulation time 9817544920 ps
CPU time 23.66 seconds
Started Jun 23 05:17:29 PM PDT 24
Finished Jun 23 05:17:53 PM PDT 24
Peak memory 206388 kb
Host smart-f22f4a88-ab29-4d2a-98ae-6bb230cecfc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53881
2178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.538812178
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3571549316
Short name T1010
Test name
Test status
Simulation time 177424753 ps
CPU time 0.85 seconds
Started Jun 23 05:17:30 PM PDT 24
Finished Jun 23 05:17:31 PM PDT 24
Peak memory 206028 kb
Host smart-669e01ef-4494-4935-8657-52545f4decf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35715
49316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3571549316
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2867011747
Short name T2371
Test name
Test status
Simulation time 247167032 ps
CPU time 0.92 seconds
Started Jun 23 05:17:30 PM PDT 24
Finished Jun 23 05:17:31 PM PDT 24
Peak memory 206116 kb
Host smart-6a264cf4-1745-4f7f-b004-0badea17a16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28670
11747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2867011747
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1391571677
Short name T387
Test name
Test status
Simulation time 199728165 ps
CPU time 0.82 seconds
Started Jun 23 05:17:34 PM PDT 24
Finished Jun 23 05:17:35 PM PDT 24
Peak memory 206124 kb
Host smart-e60866d8-eb3b-4ee1-b76a-2dbcb153212d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13915
71677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1391571677
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.133346720
Short name T506
Test name
Test status
Simulation time 197219930 ps
CPU time 0.82 seconds
Started Jun 23 05:17:31 PM PDT 24
Finished Jun 23 05:17:32 PM PDT 24
Peak memory 206120 kb
Host smart-44d7a571-a27b-45a4-bd0c-746fd278962d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13334
6720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.133346720
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.613541779
Short name T1059
Test name
Test status
Simulation time 144941164 ps
CPU time 0.81 seconds
Started Jun 23 05:17:31 PM PDT 24
Finished Jun 23 05:17:32 PM PDT 24
Peak memory 206096 kb
Host smart-f9769b26-a8a2-4a69-b7c5-60985994335c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61354
1779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.613541779
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.4222913712
Short name T811
Test name
Test status
Simulation time 150311221 ps
CPU time 0.78 seconds
Started Jun 23 05:17:35 PM PDT 24
Finished Jun 23 05:17:36 PM PDT 24
Peak memory 206096 kb
Host smart-00fcf6f3-f14c-4dfd-a17c-405ee022bbd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42229
13712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.4222913712
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.848637090
Short name T415
Test name
Test status
Simulation time 153723051 ps
CPU time 0.81 seconds
Started Jun 23 05:17:29 PM PDT 24
Finished Jun 23 05:17:30 PM PDT 24
Peak memory 206076 kb
Host smart-487f3d20-c0ed-46b9-8bf2-d6940fb52c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84863
7090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.848637090
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1168456173
Short name T50
Test name
Test status
Simulation time 292257340 ps
CPU time 0.97 seconds
Started Jun 23 05:17:18 PM PDT 24
Finished Jun 23 05:17:19 PM PDT 24
Peak memory 206040 kb
Host smart-be35fd2b-8e41-4f9f-a852-7d08ecf5a48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11684
56173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1168456173
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.1943393452
Short name T1752
Test name
Test status
Simulation time 8695260369 ps
CPU time 249.89 seconds
Started Jun 23 05:17:33 PM PDT 24
Finished Jun 23 05:21:43 PM PDT 24
Peak memory 206356 kb
Host smart-070554d4-980e-4611-9bd8-043622c8b745
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1943393452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.1943393452
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.156822745
Short name T507
Test name
Test status
Simulation time 149013793 ps
CPU time 0.96 seconds
Started Jun 23 05:17:32 PM PDT 24
Finished Jun 23 05:17:33 PM PDT 24
Peak memory 206096 kb
Host smart-2d631f77-8641-4a63-8be4-b8eccfadd5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15682
2745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.156822745
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.3932260208
Short name T2131
Test name
Test status
Simulation time 171520404 ps
CPU time 0.83 seconds
Started Jun 23 05:17:31 PM PDT 24
Finished Jun 23 05:17:32 PM PDT 24
Peak memory 206036 kb
Host smart-604acee9-7765-4ee2-ac0e-2369e3f63ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39322
60208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.3932260208
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.3134510574
Short name T83
Test name
Test status
Simulation time 8499774736 ps
CPU time 242.93 seconds
Started Jun 23 05:17:30 PM PDT 24
Finished Jun 23 05:21:33 PM PDT 24
Peak memory 206328 kb
Host smart-e3152b8f-de55-43c7-96cd-ce7801e91756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31345
10574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3134510574
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.2985661897
Short name T2442
Test name
Test status
Simulation time 3538750677 ps
CPU time 3.8 seconds
Started Jun 23 05:17:35 PM PDT 24
Finished Jun 23 05:17:39 PM PDT 24
Peak memory 206428 kb
Host smart-ff64141d-7556-4dee-aff4-012fa489f38b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2985661897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.2985661897
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.239244388
Short name T504
Test name
Test status
Simulation time 13300086238 ps
CPU time 13.6 seconds
Started Jun 23 05:17:37 PM PDT 24
Finished Jun 23 05:17:51 PM PDT 24
Peak memory 206164 kb
Host smart-d369ce5a-3291-4e27-ba4b-cffb6110afdc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=239244388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.239244388
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.2356877973
Short name T809
Test name
Test status
Simulation time 23548564741 ps
CPU time 23.71 seconds
Started Jun 23 05:17:35 PM PDT 24
Finished Jun 23 05:17:59 PM PDT 24
Peak memory 206396 kb
Host smart-aee40971-1171-4f60-ad76-0232fa41015d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2356877973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.2356877973
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2403859272
Short name T1601
Test name
Test status
Simulation time 175290417 ps
CPU time 0.83 seconds
Started Jun 23 05:17:37 PM PDT 24
Finished Jun 23 05:17:38 PM PDT 24
Peak memory 206108 kb
Host smart-ba8a4deb-1a87-4719-8740-a28a4f64b113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24038
59272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2403859272
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.1189396599
Short name T2153
Test name
Test status
Simulation time 194943048 ps
CPU time 0.85 seconds
Started Jun 23 05:17:32 PM PDT 24
Finished Jun 23 05:17:34 PM PDT 24
Peak memory 206040 kb
Host smart-beae8c68-e263-463a-8388-f172afc1fb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11893
96599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.1189396599
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3657271906
Short name T1772
Test name
Test status
Simulation time 475713632 ps
CPU time 1.52 seconds
Started Jun 23 05:17:38 PM PDT 24
Finished Jun 23 05:17:40 PM PDT 24
Peak memory 206312 kb
Host smart-414cc19f-77d2-44e6-a31d-b7178b530e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36572
71906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3657271906
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.1852108314
Short name T2379
Test name
Test status
Simulation time 1284823173 ps
CPU time 3.19 seconds
Started Jun 23 05:17:33 PM PDT 24
Finished Jun 23 05:17:37 PM PDT 24
Peak memory 206308 kb
Host smart-c7dc7db8-edf7-42ae-a9d7-dee4e1088fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18521
08314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.1852108314
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.4054003612
Short name T711
Test name
Test status
Simulation time 14211310082 ps
CPU time 29.27 seconds
Started Jun 23 05:17:34 PM PDT 24
Finished Jun 23 05:18:03 PM PDT 24
Peak memory 206360 kb
Host smart-55519dcf-b376-419a-b44a-fdd2514eb1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40540
03612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.4054003612
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.666497905
Short name T297
Test name
Test status
Simulation time 443509555 ps
CPU time 1.39 seconds
Started Jun 23 05:17:37 PM PDT 24
Finished Jun 23 05:17:39 PM PDT 24
Peak memory 206100 kb
Host smart-e193fc40-5771-473f-9241-8c1f4887949a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66649
7905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.666497905
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.3970550911
Short name T429
Test name
Test status
Simulation time 150478756 ps
CPU time 0.72 seconds
Started Jun 23 05:17:41 PM PDT 24
Finished Jun 23 05:17:42 PM PDT 24
Peak memory 206260 kb
Host smart-eede7eb6-4e8a-4e4d-92d0-986567ac398a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39705
50911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.3970550911
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.2841484955
Short name T439
Test name
Test status
Simulation time 64352285 ps
CPU time 0.7 seconds
Started Jun 23 05:17:44 PM PDT 24
Finished Jun 23 05:17:45 PM PDT 24
Peak memory 206088 kb
Host smart-317ccad8-685a-4e02-9cdc-d0d377942302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28414
84955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2841484955
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.154502085
Short name T1358
Test name
Test status
Simulation time 1023911495 ps
CPU time 2.3 seconds
Started Jun 23 05:17:40 PM PDT 24
Finished Jun 23 05:17:43 PM PDT 24
Peak memory 206364 kb
Host smart-889eed53-00c6-4067-a381-77f44e1409b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15450
2085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.154502085
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2203642654
Short name T1188
Test name
Test status
Simulation time 173264960 ps
CPU time 1.91 seconds
Started Jun 23 05:17:40 PM PDT 24
Finished Jun 23 05:17:42 PM PDT 24
Peak memory 206256 kb
Host smart-c7ef33f1-1567-4d86-aefc-a1d23ebfe706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22036
42654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2203642654
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.24747886
Short name T656
Test name
Test status
Simulation time 264811602 ps
CPU time 0.94 seconds
Started Jun 23 05:17:46 PM PDT 24
Finished Jun 23 05:17:47 PM PDT 24
Peak memory 205992 kb
Host smart-754f914a-ddf7-444a-a1a4-02899dae475f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24747
886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.24747886
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.120121635
Short name T105
Test name
Test status
Simulation time 147900323 ps
CPU time 0.72 seconds
Started Jun 23 05:17:44 PM PDT 24
Finished Jun 23 05:17:45 PM PDT 24
Peak memory 205908 kb
Host smart-2f0a8d1e-4698-4e87-aeb6-f2118b774e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12012
1635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.120121635
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1529626754
Short name T1093
Test name
Test status
Simulation time 236297941 ps
CPU time 0.88 seconds
Started Jun 23 05:17:40 PM PDT 24
Finished Jun 23 05:17:42 PM PDT 24
Peak memory 206104 kb
Host smart-ea745c47-ea4a-47b8-bf2d-cda92fcf84da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15296
26754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1529626754
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.1782553616
Short name T1850
Test name
Test status
Simulation time 8015797473 ps
CPU time 79.47 seconds
Started Jun 23 05:17:44 PM PDT 24
Finished Jun 23 05:19:04 PM PDT 24
Peak memory 206392 kb
Host smart-926b918f-4a14-4984-aa90-d1fb6fc2a9b4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1782553616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.1782553616
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.593200247
Short name T1666
Test name
Test status
Simulation time 228861813 ps
CPU time 0.88 seconds
Started Jun 23 05:17:43 PM PDT 24
Finished Jun 23 05:17:44 PM PDT 24
Peak memory 206032 kb
Host smart-5daeb488-3c0d-415a-a10b-58e6cd195314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59320
0247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.593200247
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.553628701
Short name T1801
Test name
Test status
Simulation time 23252503090 ps
CPU time 21.45 seconds
Started Jun 23 05:17:42 PM PDT 24
Finished Jun 23 05:18:04 PM PDT 24
Peak memory 206152 kb
Host smart-c689b7ab-e2ab-48a6-8fda-3271ac4f2e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55362
8701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.553628701
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3422092597
Short name T494
Test name
Test status
Simulation time 3261266679 ps
CPU time 3.67 seconds
Started Jun 23 05:17:41 PM PDT 24
Finished Jun 23 05:17:45 PM PDT 24
Peak memory 206124 kb
Host smart-1293eb14-3fe0-42d2-bd75-af7ba9a0ab10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34220
92597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3422092597
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.187966081
Short name T1650
Test name
Test status
Simulation time 8778274002 ps
CPU time 253.58 seconds
Started Jun 23 05:17:42 PM PDT 24
Finished Jun 23 05:21:56 PM PDT 24
Peak memory 206236 kb
Host smart-82ca4fb7-9701-41d2-b40e-968e31d8da62
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=187966081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.187966081
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.3331208241
Short name T530
Test name
Test status
Simulation time 262240468 ps
CPU time 0.97 seconds
Started Jun 23 05:17:45 PM PDT 24
Finished Jun 23 05:17:47 PM PDT 24
Peak memory 206136 kb
Host smart-96427a00-158b-4169-b607-1a585204d4cc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3331208241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.3331208241
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3624443123
Short name T2320
Test name
Test status
Simulation time 212773913 ps
CPU time 0.9 seconds
Started Jun 23 05:17:39 PM PDT 24
Finished Jun 23 05:17:41 PM PDT 24
Peak memory 206148 kb
Host smart-eae77677-4eaa-47e4-b3f7-54eb4c7ccf42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36244
43123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3624443123
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.4125799840
Short name T1075
Test name
Test status
Simulation time 7050552843 ps
CPU time 207.51 seconds
Started Jun 23 05:17:39 PM PDT 24
Finished Jun 23 05:21:07 PM PDT 24
Peak memory 206260 kb
Host smart-d8266af2-1664-41d6-a166-303d71c7da67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41257
99840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.4125799840
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.199920757
Short name T1317
Test name
Test status
Simulation time 13140854597 ps
CPU time 127.15 seconds
Started Jun 23 05:17:40 PM PDT 24
Finished Jun 23 05:19:47 PM PDT 24
Peak memory 206268 kb
Host smart-cda5f4fc-4cd7-415f-9d4c-a746b3803bcb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=199920757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.199920757
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2135484967
Short name T969
Test name
Test status
Simulation time 248327174 ps
CPU time 0.86 seconds
Started Jun 23 05:17:57 PM PDT 24
Finished Jun 23 05:17:59 PM PDT 24
Peak memory 206056 kb
Host smart-5d9910b2-8019-41e9-b4a8-67a8739ce759
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2135484967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2135484967
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.795970302
Short name T665
Test name
Test status
Simulation time 152163627 ps
CPU time 0.78 seconds
Started Jun 23 05:17:43 PM PDT 24
Finished Jun 23 05:17:44 PM PDT 24
Peak memory 206032 kb
Host smart-b039c2bb-9f61-4109-8a97-88d10fb1c647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79597
0302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.795970302
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.401586294
Short name T900
Test name
Test status
Simulation time 149764131 ps
CPU time 0.79 seconds
Started Jun 23 05:17:41 PM PDT 24
Finished Jun 23 05:17:43 PM PDT 24
Peak memory 206052 kb
Host smart-cf7bdf58-3213-4bb6-ab10-721ce0279e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40158
6294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.401586294
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2012658737
Short name T1124
Test name
Test status
Simulation time 215454975 ps
CPU time 0.83 seconds
Started Jun 23 05:17:42 PM PDT 24
Finished Jun 23 05:17:43 PM PDT 24
Peak memory 206060 kb
Host smart-fce4870d-042f-4fe0-86f3-6027089b0517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20126
58737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2012658737
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2579218399
Short name T1649
Test name
Test status
Simulation time 177893518 ps
CPU time 0.8 seconds
Started Jun 23 05:17:40 PM PDT 24
Finished Jun 23 05:17:42 PM PDT 24
Peak memory 206112 kb
Host smart-2ac0c298-2a77-4e05-acbb-5f26b7170396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25792
18399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2579218399
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1695358833
Short name T1384
Test name
Test status
Simulation time 142785611 ps
CPU time 0.77 seconds
Started Jun 23 05:17:45 PM PDT 24
Finished Jun 23 05:17:46 PM PDT 24
Peak memory 206096 kb
Host smart-ccbcbb84-c8f2-407e-afc7-f62bc1e57517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16953
58833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1695358833
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.4024666069
Short name T2307
Test name
Test status
Simulation time 261043271 ps
CPU time 0.98 seconds
Started Jun 23 05:17:44 PM PDT 24
Finished Jun 23 05:17:45 PM PDT 24
Peak memory 206116 kb
Host smart-46fae676-23af-42bc-93dd-b604039e79b6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4024666069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.4024666069
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.2303271742
Short name T431
Test name
Test status
Simulation time 167933506 ps
CPU time 0.85 seconds
Started Jun 23 05:17:57 PM PDT 24
Finished Jun 23 05:17:59 PM PDT 24
Peak memory 206032 kb
Host smart-43956691-d146-4a7b-aa38-c46e9e56d974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23032
71742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.2303271742
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2290378495
Short name T1107
Test name
Test status
Simulation time 71090120 ps
CPU time 0.68 seconds
Started Jun 23 05:17:46 PM PDT 24
Finished Jun 23 05:17:48 PM PDT 24
Peak memory 206108 kb
Host smart-a4446028-6a63-4a44-b0aa-aa48b18bb4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22903
78495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2290378495
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.4137370532
Short name T1775
Test name
Test status
Simulation time 14048877400 ps
CPU time 31.91 seconds
Started Jun 23 05:17:39 PM PDT 24
Finished Jun 23 05:18:12 PM PDT 24
Peak memory 206400 kb
Host smart-63514cbc-d21a-4d76-9dff-ee032ca9b5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41373
70532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.4137370532
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3343362773
Short name T989
Test name
Test status
Simulation time 160834928 ps
CPU time 0.79 seconds
Started Jun 23 05:17:42 PM PDT 24
Finished Jun 23 05:17:43 PM PDT 24
Peak memory 206100 kb
Host smart-7a54c754-e8f6-49b5-b105-76033cd5514c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33433
62773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3343362773
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.4227816701
Short name T703
Test name
Test status
Simulation time 197710038 ps
CPU time 0.86 seconds
Started Jun 23 05:17:46 PM PDT 24
Finished Jun 23 05:17:47 PM PDT 24
Peak memory 206044 kb
Host smart-e442663d-dafb-4e97-9998-49e4d4f142f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42278
16701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.4227816701
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.280571424
Short name T726
Test name
Test status
Simulation time 176432437 ps
CPU time 0.8 seconds
Started Jun 23 05:17:42 PM PDT 24
Finished Jun 23 05:17:43 PM PDT 24
Peak memory 206116 kb
Host smart-7e4dd043-7dd6-4c27-86d9-da6ffd5d6fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28057
1424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.280571424
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.844694639
Short name T2150
Test name
Test status
Simulation time 152302974 ps
CPU time 0.82 seconds
Started Jun 23 05:17:57 PM PDT 24
Finished Jun 23 05:17:58 PM PDT 24
Peak memory 206100 kb
Host smart-a1abee2b-7952-41cb-952c-c8f9b85cb049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84469
4639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.844694639
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.15955961
Short name T1006
Test name
Test status
Simulation time 158168290 ps
CPU time 0.77 seconds
Started Jun 23 05:17:48 PM PDT 24
Finished Jun 23 05:17:49 PM PDT 24
Peak memory 206024 kb
Host smart-3c40b385-01c9-48e0-9dcf-65f1ebf7d7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15955
961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.15955961
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1546922502
Short name T1337
Test name
Test status
Simulation time 205103994 ps
CPU time 0.87 seconds
Started Jun 23 05:17:36 PM PDT 24
Finished Jun 23 05:17:37 PM PDT 24
Peak memory 206104 kb
Host smart-0b4a31f7-e1c2-4ab2-9cc2-d65800ecbad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15469
22502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1546922502
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.3355056785
Short name T2021
Test name
Test status
Simulation time 6681202972 ps
CPU time 60.75 seconds
Started Jun 23 05:17:40 PM PDT 24
Finished Jun 23 05:18:41 PM PDT 24
Peak memory 206368 kb
Host smart-9b4c2fa5-fc86-4338-b56b-fbfd122de708
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3355056785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.3355056785
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1801817574
Short name T2050
Test name
Test status
Simulation time 259792006 ps
CPU time 0.87 seconds
Started Jun 23 05:17:57 PM PDT 24
Finished Jun 23 05:17:59 PM PDT 24
Peak memory 206052 kb
Host smart-eef26abb-1960-4e83-a3ac-680d5d2f9937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18018
17574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1801817574
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.4099239611
Short name T329
Test name
Test status
Simulation time 184105796 ps
CPU time 0.88 seconds
Started Jun 23 05:17:41 PM PDT 24
Finished Jun 23 05:17:43 PM PDT 24
Peak memory 206020 kb
Host smart-0c52e23f-c0eb-4366-a750-a8d35f27a375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40992
39611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.4099239611
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.3689393255
Short name T2193
Test name
Test status
Simulation time 7191941831 ps
CPU time 51.2 seconds
Started Jun 23 05:17:43 PM PDT 24
Finished Jun 23 05:18:35 PM PDT 24
Peak memory 206408 kb
Host smart-24f6d992-b105-4eba-b23a-4147c6da3dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36893
93255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.3689393255
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3533227691
Short name T875
Test name
Test status
Simulation time 3888781262 ps
CPU time 4.64 seconds
Started Jun 23 05:17:46 PM PDT 24
Finished Jun 23 05:17:52 PM PDT 24
Peak memory 206416 kb
Host smart-886dec7b-c4ae-44e2-9ebe-12e9fa8f201e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3533227691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.3533227691
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2425451409
Short name T2459
Test name
Test status
Simulation time 13414300097 ps
CPU time 11.65 seconds
Started Jun 23 05:17:44 PM PDT 24
Finished Jun 23 05:17:56 PM PDT 24
Peak memory 206400 kb
Host smart-e04ae761-86e9-474a-8d1c-27518330a306
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2425451409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2425451409
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.2042110093
Short name T1824
Test name
Test status
Simulation time 23372956124 ps
CPU time 24.28 seconds
Started Jun 23 05:17:45 PM PDT 24
Finished Jun 23 05:18:10 PM PDT 24
Peak memory 206144 kb
Host smart-0d8c3129-88a2-4114-ab25-7a90995d6f02
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2042110093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.2042110093
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.420700476
Short name T2251
Test name
Test status
Simulation time 177746083 ps
CPU time 0.8 seconds
Started Jun 23 05:17:47 PM PDT 24
Finished Jun 23 05:17:48 PM PDT 24
Peak memory 206100 kb
Host smart-bdd76be8-a6e6-49ed-b1e5-e30e2e92eb2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42070
0476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.420700476
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.2346981202
Short name T1902
Test name
Test status
Simulation time 139734232 ps
CPU time 0.79 seconds
Started Jun 23 05:17:46 PM PDT 24
Finished Jun 23 05:17:48 PM PDT 24
Peak memory 206032 kb
Host smart-1491433c-47c0-4d2f-8c9e-114c0f6168bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23469
81202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.2346981202
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.3238778220
Short name T2354
Test name
Test status
Simulation time 233798418 ps
CPU time 1.02 seconds
Started Jun 23 05:17:57 PM PDT 24
Finished Jun 23 05:17:59 PM PDT 24
Peak memory 206104 kb
Host smart-fadaf3bd-9d5b-4ed7-b4b8-76fb528f65ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32387
78220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.3238778220
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.716833244
Short name T2360
Test name
Test status
Simulation time 1011437551 ps
CPU time 2.52 seconds
Started Jun 23 05:17:48 PM PDT 24
Finished Jun 23 05:17:51 PM PDT 24
Peak memory 206256 kb
Host smart-b3a32700-8855-4ab8-9d14-6f5c8554541f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71683
3244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.716833244
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.907259051
Short name T1955
Test name
Test status
Simulation time 22248779577 ps
CPU time 47.31 seconds
Started Jun 23 05:17:47 PM PDT 24
Finished Jun 23 05:18:35 PM PDT 24
Peak memory 206324 kb
Host smart-8ac66172-ec82-497c-997a-683e774e2a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90725
9051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.907259051
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.1750929378
Short name T1969
Test name
Test status
Simulation time 444288080 ps
CPU time 1.27 seconds
Started Jun 23 05:17:47 PM PDT 24
Finished Jun 23 05:17:49 PM PDT 24
Peak memory 206108 kb
Host smart-3bb9b577-9108-46d8-a209-d6eb755bd74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17509
29378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.1750929378
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2887822361
Short name T1024
Test name
Test status
Simulation time 159807956 ps
CPU time 0.75 seconds
Started Jun 23 05:17:56 PM PDT 24
Finished Jun 23 05:17:58 PM PDT 24
Peak memory 206100 kb
Host smart-880702c5-c1bb-4d30-adc1-aa75979060ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28878
22361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2887822361
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.2044060119
Short name T2283
Test name
Test status
Simulation time 53376968 ps
CPU time 0.67 seconds
Started Jun 23 05:17:45 PM PDT 24
Finished Jun 23 05:17:46 PM PDT 24
Peak memory 206044 kb
Host smart-7521afeb-ecd0-42d7-aa80-2ff7b564685a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20440
60119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2044060119
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.583136878
Short name T1239
Test name
Test status
Simulation time 1002995583 ps
CPU time 2.13 seconds
Started Jun 23 05:17:47 PM PDT 24
Finished Jun 23 05:17:50 PM PDT 24
Peak memory 206336 kb
Host smart-ffcc5dcf-3158-4a66-920a-32f48cd1e9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58313
6878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.583136878
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.56749877
Short name T1776
Test name
Test status
Simulation time 303300200 ps
CPU time 2.21 seconds
Started Jun 23 05:17:46 PM PDT 24
Finished Jun 23 05:17:49 PM PDT 24
Peak memory 206344 kb
Host smart-2c0160a2-5f91-4782-a700-c0e00f341f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56749
877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.56749877
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1867902880
Short name T831
Test name
Test status
Simulation time 176206636 ps
CPU time 0.79 seconds
Started Jun 23 05:17:57 PM PDT 24
Finished Jun 23 05:17:59 PM PDT 24
Peak memory 206104 kb
Host smart-ce7de7b2-4786-4ea3-a0ae-8bdabba8639a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18679
02880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1867902880
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1729251684
Short name T913
Test name
Test status
Simulation time 152710943 ps
CPU time 0.77 seconds
Started Jun 23 05:17:59 PM PDT 24
Finished Jun 23 05:18:00 PM PDT 24
Peak memory 206096 kb
Host smart-1d26ef5a-afc7-40c7-8718-2ef066508dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17292
51684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1729251684
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.4028035897
Short name T299
Test name
Test status
Simulation time 200123131 ps
CPU time 0.9 seconds
Started Jun 23 05:17:46 PM PDT 24
Finished Jun 23 05:17:47 PM PDT 24
Peak memory 206120 kb
Host smart-802ea0e1-1830-4bbb-951d-8ff1260d2430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40280
35897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.4028035897
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.1087411945
Short name T1372
Test name
Test status
Simulation time 6099230557 ps
CPU time 165.6 seconds
Started Jun 23 05:17:54 PM PDT 24
Finished Jun 23 05:20:40 PM PDT 24
Peak memory 206340 kb
Host smart-6e7436e7-b726-4ce6-b497-a8fd9b5f2bbd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1087411945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.1087411945
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.1431306981
Short name T999
Test name
Test status
Simulation time 282295536 ps
CPU time 0.94 seconds
Started Jun 23 05:17:51 PM PDT 24
Finished Jun 23 05:17:52 PM PDT 24
Peak memory 206068 kb
Host smart-4a28e254-644a-404f-bcec-7bf81d6e377a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14313
06981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.1431306981
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.2648247466
Short name T2344
Test name
Test status
Simulation time 23368745494 ps
CPU time 22.06 seconds
Started Jun 23 05:17:55 PM PDT 24
Finished Jun 23 05:18:17 PM PDT 24
Peak memory 206160 kb
Host smart-735db12d-99fe-4e13-ba35-25c71cb3e09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26482
47466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.2648247466
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.2224224224
Short name T1962
Test name
Test status
Simulation time 3343431876 ps
CPU time 4.13 seconds
Started Jun 23 05:17:56 PM PDT 24
Finished Jun 23 05:18:01 PM PDT 24
Peak memory 206064 kb
Host smart-d372b674-03b9-471e-97f2-3aa9658a03f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22242
24224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.2224224224
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.3473562360
Short name T1599
Test name
Test status
Simulation time 7230102437 ps
CPU time 212.37 seconds
Started Jun 23 05:17:52 PM PDT 24
Finished Jun 23 05:21:25 PM PDT 24
Peak memory 206272 kb
Host smart-c78c881f-ad7f-4eb0-8824-23c8c7161898
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3473562360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.3473562360
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2580250675
Short name T2328
Test name
Test status
Simulation time 251073317 ps
CPU time 0.91 seconds
Started Jun 23 05:17:57 PM PDT 24
Finished Jun 23 05:17:58 PM PDT 24
Peak memory 206120 kb
Host smart-5f874151-539c-4404-8a04-21453f345e18
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2580250675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2580250675
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.4131125690
Short name T1028
Test name
Test status
Simulation time 201547851 ps
CPU time 0.85 seconds
Started Jun 23 05:17:51 PM PDT 24
Finished Jun 23 05:17:52 PM PDT 24
Peak memory 206068 kb
Host smart-4b7a864d-702e-46a5-b4e3-eae151b21fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41311
25690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.4131125690
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3518424156
Short name T667
Test name
Test status
Simulation time 10697881914 ps
CPU time 78.65 seconds
Started Jun 23 05:17:55 PM PDT 24
Finished Jun 23 05:19:14 PM PDT 24
Peak memory 206224 kb
Host smart-e4b8bfd6-3536-4eb3-8cb7-08be3d721332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35184
24156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3518424156
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.3711116248
Short name T1009
Test name
Test status
Simulation time 9772021738 ps
CPU time 69.55 seconds
Started Jun 23 05:17:52 PM PDT 24
Finished Jun 23 05:19:02 PM PDT 24
Peak memory 206432 kb
Host smart-c955d2a9-d375-4b6d-977b-79d3e4d9e3c8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3711116248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.3711116248
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.416980218
Short name T141
Test name
Test status
Simulation time 146482924 ps
CPU time 0.81 seconds
Started Jun 23 05:18:00 PM PDT 24
Finished Jun 23 05:18:01 PM PDT 24
Peak memory 206084 kb
Host smart-b8a4b944-5d3e-4363-83c5-6ff2e769c4af
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=416980218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.416980218
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3343803926
Short name T321
Test name
Test status
Simulation time 144900532 ps
CPU time 0.77 seconds
Started Jun 23 05:17:54 PM PDT 24
Finished Jun 23 05:17:55 PM PDT 24
Peak memory 206104 kb
Host smart-9819c10a-9e01-413d-99d7-ded9e9f2bd50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33438
03926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3343803926
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.339858433
Short name T1339
Test name
Test status
Simulation time 172491306 ps
CPU time 0.82 seconds
Started Jun 23 05:17:50 PM PDT 24
Finished Jun 23 05:17:52 PM PDT 24
Peak memory 206112 kb
Host smart-f98df04f-ecca-45b8-9af1-36835c66b58f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33985
8433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.339858433
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.4068419078
Short name T313
Test name
Test status
Simulation time 151829003 ps
CPU time 0.85 seconds
Started Jun 23 05:17:50 PM PDT 24
Finished Jun 23 05:17:52 PM PDT 24
Peak memory 206040 kb
Host smart-a15ef5e1-3c5a-44b1-bc18-77a1353f3449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40684
19078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.4068419078
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1511839471
Short name T425
Test name
Test status
Simulation time 183449044 ps
CPU time 0.82 seconds
Started Jun 23 05:17:51 PM PDT 24
Finished Jun 23 05:17:52 PM PDT 24
Peak memory 206044 kb
Host smart-01938402-ad0a-4556-b4e9-7a45ed3fdb6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15118
39471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1511839471
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.1304352292
Short name T1365
Test name
Test status
Simulation time 164685755 ps
CPU time 0.79 seconds
Started Jun 23 05:17:57 PM PDT 24
Finished Jun 23 05:17:58 PM PDT 24
Peak memory 206024 kb
Host smart-cf81ab64-7de2-4190-bcd4-413fda6ee206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13043
52292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.1304352292
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.3864367228
Short name T1242
Test name
Test status
Simulation time 218559002 ps
CPU time 0.91 seconds
Started Jun 23 05:17:53 PM PDT 24
Finished Jun 23 05:17:54 PM PDT 24
Peak memory 206128 kb
Host smart-96dec0fd-e374-447d-b1a7-2e15c2062b2c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3864367228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.3864367228
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.4184252054
Short name T621
Test name
Test status
Simulation time 156041338 ps
CPU time 0.76 seconds
Started Jun 23 05:17:52 PM PDT 24
Finished Jun 23 05:17:53 PM PDT 24
Peak memory 206112 kb
Host smart-a25eebce-c6ff-490b-b17d-cbdfbebb827f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41842
52054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.4184252054
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.573946903
Short name T1629
Test name
Test status
Simulation time 67421975 ps
CPU time 0.69 seconds
Started Jun 23 05:17:59 PM PDT 24
Finished Jun 23 05:18:00 PM PDT 24
Peak memory 206016 kb
Host smart-4c8607d2-8e2e-43e6-9849-67abfc4d5539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57394
6903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.573946903
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.2273419131
Short name T229
Test name
Test status
Simulation time 10350921618 ps
CPU time 23.11 seconds
Started Jun 23 05:18:00 PM PDT 24
Finished Jun 23 05:18:24 PM PDT 24
Peak memory 206344 kb
Host smart-441e3638-60de-4b36-8789-12496c5abb80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22734
19131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.2273419131
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.4111003183
Short name T2438
Test name
Test status
Simulation time 162113760 ps
CPU time 0.78 seconds
Started Jun 23 05:17:49 PM PDT 24
Finished Jun 23 05:17:50 PM PDT 24
Peak memory 206048 kb
Host smart-6b473c2e-afdd-47f1-b175-aada0ef815b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41110
03183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.4111003183
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1188852198
Short name T2311
Test name
Test status
Simulation time 199448581 ps
CPU time 0.85 seconds
Started Jun 23 05:17:52 PM PDT 24
Finished Jun 23 05:17:53 PM PDT 24
Peak memory 206032 kb
Host smart-ec2c7c37-ad54-473c-950b-3dde4a3139ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11888
52198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1188852198
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.4214417416
Short name T283
Test name
Test status
Simulation time 212017048 ps
CPU time 0.91 seconds
Started Jun 23 05:17:58 PM PDT 24
Finished Jun 23 05:18:00 PM PDT 24
Peak memory 206100 kb
Host smart-6c24d4cb-6ef1-4804-be77-8a5f3200c975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42144
17416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.4214417416
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.577212197
Short name T569
Test name
Test status
Simulation time 164467496 ps
CPU time 0.81 seconds
Started Jun 23 05:17:55 PM PDT 24
Finished Jun 23 05:17:56 PM PDT 24
Peak memory 206016 kb
Host smart-dc8f4862-5e08-46c3-b226-0d6236ea6bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57721
2197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.577212197
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.567587073
Short name T1910
Test name
Test status
Simulation time 197337298 ps
CPU time 0.82 seconds
Started Jun 23 05:17:54 PM PDT 24
Finished Jun 23 05:17:56 PM PDT 24
Peak memory 206108 kb
Host smart-560e7b67-8c64-4e8f-a454-c6ea2f02dc1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56758
7073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.567587073
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2261470271
Short name T2084
Test name
Test status
Simulation time 146604303 ps
CPU time 0.81 seconds
Started Jun 23 05:17:51 PM PDT 24
Finished Jun 23 05:17:52 PM PDT 24
Peak memory 206012 kb
Host smart-dda3c05d-54f4-481c-aea3-36be7bac869c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22614
70271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2261470271
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.134893011
Short name T677
Test name
Test status
Simulation time 149583217 ps
CPU time 0.79 seconds
Started Jun 23 05:17:51 PM PDT 24
Finished Jun 23 05:17:52 PM PDT 24
Peak memory 206120 kb
Host smart-02f7dce9-c08a-4798-b9ce-96dd464ddc9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13489
3011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.134893011
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.4181927879
Short name T2458
Test name
Test status
Simulation time 225895718 ps
CPU time 1 seconds
Started Jun 23 05:17:48 PM PDT 24
Finished Jun 23 05:17:49 PM PDT 24
Peak memory 206108 kb
Host smart-31d9b828-777d-4bba-b611-cad419767701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41819
27879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.4181927879
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.1037358825
Short name T2399
Test name
Test status
Simulation time 11236162593 ps
CPU time 303.56 seconds
Started Jun 23 05:17:53 PM PDT 24
Finished Jun 23 05:22:57 PM PDT 24
Peak memory 206340 kb
Host smart-14541c27-302e-463f-a9ba-b3e77ba182c2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1037358825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.1037358825
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2164547072
Short name T1484
Test name
Test status
Simulation time 163604515 ps
CPU time 0.81 seconds
Started Jun 23 05:17:55 PM PDT 24
Finished Jun 23 05:17:56 PM PDT 24
Peak memory 206008 kb
Host smart-42cbe450-4be3-4320-8f1f-d909ccc968ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21645
47072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2164547072
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.4159944067
Short name T1976
Test name
Test status
Simulation time 238824903 ps
CPU time 0.88 seconds
Started Jun 23 05:17:54 PM PDT 24
Finished Jun 23 05:17:55 PM PDT 24
Peak memory 206004 kb
Host smart-6cee2b4d-9d9f-4fb0-a6de-4cb1e6a94cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41599
44067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.4159944067
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.4274038221
Short name T1587
Test name
Test status
Simulation time 9824779297 ps
CPU time 297.86 seconds
Started Jun 23 05:17:53 PM PDT 24
Finished Jun 23 05:22:51 PM PDT 24
Peak memory 206360 kb
Host smart-17524f8b-02c4-4a4c-b57c-1ae62c81778e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42740
38221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.4274038221
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2002334817
Short name T1305
Test name
Test status
Simulation time 4002459960 ps
CPU time 4.53 seconds
Started Jun 23 05:17:58 PM PDT 24
Finished Jun 23 05:18:03 PM PDT 24
Peak memory 206324 kb
Host smart-d1ff83a3-2873-4671-a307-8acc255d4de6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2002334817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.2002334817
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.2968382306
Short name T2049
Test name
Test status
Simulation time 13302369580 ps
CPU time 12.62 seconds
Started Jun 23 05:18:03 PM PDT 24
Finished Jun 23 05:18:16 PM PDT 24
Peak memory 206092 kb
Host smart-9addbe33-347a-4cb5-910f-05054082508b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2968382306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.2968382306
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.1403813846
Short name T1022
Test name
Test status
Simulation time 23350995416 ps
CPU time 26.88 seconds
Started Jun 23 05:18:04 PM PDT 24
Finished Jun 23 05:18:32 PM PDT 24
Peak memory 206088 kb
Host smart-b353adb8-8a53-4d1c-af8d-36440c638089
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1403813846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.1403813846
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3132662553
Short name T1790
Test name
Test status
Simulation time 169915585 ps
CPU time 0.85 seconds
Started Jun 23 05:17:58 PM PDT 24
Finished Jun 23 05:17:59 PM PDT 24
Peak memory 205988 kb
Host smart-75eeec60-86ac-45d4-950a-a0799555ab5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31326
62553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3132662553
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.4258268495
Short name T66
Test name
Test status
Simulation time 201009372 ps
CPU time 0.8 seconds
Started Jun 23 05:17:58 PM PDT 24
Finished Jun 23 05:17:59 PM PDT 24
Peak memory 206092 kb
Host smart-f302c2cb-f6c1-45a1-ac94-b484def0a50b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42582
68495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.4258268495
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.1435033213
Short name T691
Test name
Test status
Simulation time 173955010 ps
CPU time 0.93 seconds
Started Jun 23 05:17:58 PM PDT 24
Finished Jun 23 05:18:00 PM PDT 24
Peak memory 206068 kb
Host smart-fc60585e-d81a-4b6b-a010-e0a4a46bba90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14350
33213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.1435033213
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.1103856451
Short name T1860
Test name
Test status
Simulation time 858007694 ps
CPU time 1.96 seconds
Started Jun 23 05:18:04 PM PDT 24
Finished Jun 23 05:18:07 PM PDT 24
Peak memory 206180 kb
Host smart-921ae401-1332-424e-910a-0bdee191594e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11038
56451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.1103856451
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.2795542065
Short name T88
Test name
Test status
Simulation time 15654376395 ps
CPU time 26.97 seconds
Started Jun 23 05:18:04 PM PDT 24
Finished Jun 23 05:18:32 PM PDT 24
Peak memory 206312 kb
Host smart-b07d58b5-f9a5-4062-b24f-56c26bd4b599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27955
42065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.2795542065
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.676357358
Short name T1688
Test name
Test status
Simulation time 414338666 ps
CPU time 1.32 seconds
Started Jun 23 05:17:58 PM PDT 24
Finished Jun 23 05:18:00 PM PDT 24
Peak memory 206108 kb
Host smart-813890b0-10bc-44f7-b363-983fdcadc910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67635
7358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.676357358
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.1317538756
Short name T326
Test name
Test status
Simulation time 144302629 ps
CPU time 0.74 seconds
Started Jun 23 05:17:57 PM PDT 24
Finished Jun 23 05:17:58 PM PDT 24
Peak memory 206092 kb
Host smart-84ff640b-20ef-4c69-9b0c-736d4e73929a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13175
38756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1317538756
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.3811953817
Short name T2170
Test name
Test status
Simulation time 48172301 ps
CPU time 0.67 seconds
Started Jun 23 05:17:58 PM PDT 24
Finished Jun 23 05:17:59 PM PDT 24
Peak memory 206156 kb
Host smart-93b90b54-0fa2-4b69-b7c2-d0d0caa37ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38119
53817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3811953817
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.1215765533
Short name T1751
Test name
Test status
Simulation time 1141400967 ps
CPU time 2.53 seconds
Started Jun 23 05:17:58 PM PDT 24
Finished Jun 23 05:18:02 PM PDT 24
Peak memory 206244 kb
Host smart-7c79ba04-1340-4908-a03a-3039d2db2085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12157
65533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.1215765533
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2668938586
Short name T1291
Test name
Test status
Simulation time 216949646 ps
CPU time 1.39 seconds
Started Jun 23 05:18:04 PM PDT 24
Finished Jun 23 05:18:07 PM PDT 24
Peak memory 206228 kb
Host smart-03a72eb7-7fdf-4832-9610-9fa8b4196571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26689
38586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2668938586
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.755589478
Short name T1698
Test name
Test status
Simulation time 213292663 ps
CPU time 0.84 seconds
Started Jun 23 05:18:10 PM PDT 24
Finished Jun 23 05:18:11 PM PDT 24
Peak memory 206072 kb
Host smart-919a46bd-a37e-4426-9a4c-220bcb18d34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75558
9478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.755589478
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2059354461
Short name T509
Test name
Test status
Simulation time 177000167 ps
CPU time 0.79 seconds
Started Jun 23 05:18:09 PM PDT 24
Finished Jun 23 05:18:10 PM PDT 24
Peak memory 206068 kb
Host smart-2aff6692-f0a1-45c2-b2d1-76f030afdb50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20593
54461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2059354461
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.3953539531
Short name T1694
Test name
Test status
Simulation time 181118746 ps
CPU time 0.93 seconds
Started Jun 23 05:17:58 PM PDT 24
Finished Jun 23 05:18:00 PM PDT 24
Peak memory 206104 kb
Host smart-2f2b95a8-2f1c-4bc8-a429-d29454c2aaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39535
39531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3953539531
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.4045477625
Short name T1401
Test name
Test status
Simulation time 18096074165 ps
CPU time 136.36 seconds
Started Jun 23 05:17:56 PM PDT 24
Finished Jun 23 05:20:13 PM PDT 24
Peak memory 206324 kb
Host smart-398e3ba5-2fbb-4f1c-9cc4-9a3867ebb4c3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4045477625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.4045477625
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.4227971257
Short name T1433
Test name
Test status
Simulation time 191061300 ps
CPU time 0.86 seconds
Started Jun 23 05:18:04 PM PDT 24
Finished Jun 23 05:18:05 PM PDT 24
Peak memory 206016 kb
Host smart-0b431856-40d3-4a33-9101-6a9f8511e6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42279
71257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.4227971257
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.2532272585
Short name T2087
Test name
Test status
Simulation time 23322115510 ps
CPU time 22.54 seconds
Started Jun 23 05:18:06 PM PDT 24
Finished Jun 23 05:18:29 PM PDT 24
Peak memory 206164 kb
Host smart-ee99da43-3cd8-4eb7-ac61-ebcf65bca399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25322
72585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.2532272585
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2123096124
Short name T789
Test name
Test status
Simulation time 3365397154 ps
CPU time 4.55 seconds
Started Jun 23 05:18:07 PM PDT 24
Finished Jun 23 05:18:12 PM PDT 24
Peak memory 206168 kb
Host smart-96bdc3b6-5b56-434d-b639-3f92374d47ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21230
96124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2123096124
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.3308123345
Short name T314
Test name
Test status
Simulation time 12098826854 ps
CPU time 338.53 seconds
Started Jun 23 05:18:04 PM PDT 24
Finished Jun 23 05:23:43 PM PDT 24
Peak memory 206340 kb
Host smart-7827b8b8-4f65-40b8-9c13-ebc38ee5c155
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3308123345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.3308123345
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.3347465722
Short name T2439
Test name
Test status
Simulation time 243166498 ps
CPU time 0.97 seconds
Started Jun 23 05:18:17 PM PDT 24
Finished Jun 23 05:18:18 PM PDT 24
Peak memory 206064 kb
Host smart-bcbde9e3-eafe-4ebb-8fca-d8b67ad36438
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3347465722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.3347465722
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1045514186
Short name T2044
Test name
Test status
Simulation time 199352463 ps
CPU time 0.83 seconds
Started Jun 23 05:18:07 PM PDT 24
Finished Jun 23 05:18:09 PM PDT 24
Peak memory 206116 kb
Host smart-876fdc01-0578-4c15-bec3-9465573590ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10455
14186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1045514186
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.1730940728
Short name T1740
Test name
Test status
Simulation time 4789530808 ps
CPU time 44.07 seconds
Started Jun 23 05:18:02 PM PDT 24
Finished Jun 23 05:18:46 PM PDT 24
Peak memory 206284 kb
Host smart-d2d4f82f-782b-4444-8449-e1863d06d883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17309
40728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.1730940728
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.3104506353
Short name T673
Test name
Test status
Simulation time 14059372032 ps
CPU time 132.63 seconds
Started Jun 23 05:18:03 PM PDT 24
Finished Jun 23 05:20:16 PM PDT 24
Peak memory 206432 kb
Host smart-465d2ad0-e0f7-4284-8049-c1591d06dbc2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3104506353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.3104506353
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.621349627
Short name T1311
Test name
Test status
Simulation time 154062290 ps
CPU time 0.75 seconds
Started Jun 23 05:18:13 PM PDT 24
Finished Jun 23 05:18:14 PM PDT 24
Peak memory 206132 kb
Host smart-4ae9ac2e-8878-4c2b-9872-adee049907ec
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=621349627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.621349627
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.954211763
Short name T1949
Test name
Test status
Simulation time 148493194 ps
CPU time 0.81 seconds
Started Jun 23 05:18:02 PM PDT 24
Finished Jun 23 05:18:04 PM PDT 24
Peak memory 206128 kb
Host smart-9bbdf2da-650d-4795-90c2-448722f94bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95421
1763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.954211763
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2734112456
Short name T117
Test name
Test status
Simulation time 179562386 ps
CPU time 0.84 seconds
Started Jun 23 05:18:04 PM PDT 24
Finished Jun 23 05:18:05 PM PDT 24
Peak memory 206156 kb
Host smart-23314abe-bceb-40f1-b62c-7717ef846ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27341
12456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2734112456
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.1317558201
Short name T428
Test name
Test status
Simulation time 175603533 ps
CPU time 0.8 seconds
Started Jun 23 05:18:03 PM PDT 24
Finished Jun 23 05:18:04 PM PDT 24
Peak memory 206024 kb
Host smart-cdf69b49-37ca-4a07-97f2-6129372ef0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13175
58201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.1317558201
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1168676896
Short name T807
Test name
Test status
Simulation time 179156783 ps
CPU time 0.84 seconds
Started Jun 23 05:18:04 PM PDT 24
Finished Jun 23 05:18:05 PM PDT 24
Peak memory 206104 kb
Host smart-ba7fde59-a2f9-4c99-8a4d-adad1c62e763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11686
76896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1168676896
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.600320868
Short name T2260
Test name
Test status
Simulation time 151518274 ps
CPU time 0.8 seconds
Started Jun 23 05:18:07 PM PDT 24
Finished Jun 23 05:18:09 PM PDT 24
Peak memory 206100 kb
Host smart-ee7bcb44-352a-43e2-adf3-0ae8bfa0368f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60032
0868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.600320868
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3111647803
Short name T1731
Test name
Test status
Simulation time 152395167 ps
CPU time 0.75 seconds
Started Jun 23 05:18:12 PM PDT 24
Finished Jun 23 05:18:13 PM PDT 24
Peak memory 206024 kb
Host smart-80645283-8474-4f1e-a4a3-9c9534914075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31116
47803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3111647803
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.897411869
Short name T1517
Test name
Test status
Simulation time 234875026 ps
CPU time 1.02 seconds
Started Jun 23 05:18:10 PM PDT 24
Finished Jun 23 05:18:11 PM PDT 24
Peak memory 206128 kb
Host smart-d3d15cec-27e2-4384-93d8-f849c8559379
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=897411869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.897411869
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.1867466471
Short name T444
Test name
Test status
Simulation time 180216707 ps
CPU time 0.8 seconds
Started Jun 23 05:18:12 PM PDT 24
Finished Jun 23 05:18:13 PM PDT 24
Peak memory 206108 kb
Host smart-09c52dbf-6c79-422d-b1b3-9946d4fdba07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18674
66471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1867466471
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.4227987161
Short name T2463
Test name
Test status
Simulation time 57376444 ps
CPU time 0.68 seconds
Started Jun 23 05:18:08 PM PDT 24
Finished Jun 23 05:18:10 PM PDT 24
Peak memory 206112 kb
Host smart-6e73504d-87df-4fea-9400-f5976efb299d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42279
87161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.4227987161
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1678193250
Short name T2246
Test name
Test status
Simulation time 11974483143 ps
CPU time 29.07 seconds
Started Jun 23 05:18:04 PM PDT 24
Finished Jun 23 05:18:34 PM PDT 24
Peak memory 206316 kb
Host smart-2e298dfa-b4cb-4ea0-9a1e-35aa244de8bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16781
93250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1678193250
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2955048634
Short name T461
Test name
Test status
Simulation time 163180094 ps
CPU time 0.79 seconds
Started Jun 23 05:18:03 PM PDT 24
Finished Jun 23 05:18:04 PM PDT 24
Peak memory 206096 kb
Host smart-9f22d930-717e-432f-be72-28f3222da2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29550
48634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2955048634
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2454146314
Short name T605
Test name
Test status
Simulation time 198671230 ps
CPU time 0.91 seconds
Started Jun 23 05:18:02 PM PDT 24
Finished Jun 23 05:18:03 PM PDT 24
Peak memory 206040 kb
Host smart-25b31d9e-6415-44ff-a748-d144ebb98044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24541
46314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2454146314
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.2519693717
Short name T204
Test name
Test status
Simulation time 154642125 ps
CPU time 0.8 seconds
Started Jun 23 05:18:09 PM PDT 24
Finished Jun 23 05:18:10 PM PDT 24
Peak memory 206056 kb
Host smart-9289178f-d368-4838-ae18-5b3812552b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25196
93717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.2519693717
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2463326231
Short name T934
Test name
Test status
Simulation time 179803580 ps
CPU time 0.84 seconds
Started Jun 23 05:18:02 PM PDT 24
Finished Jun 23 05:18:04 PM PDT 24
Peak memory 206132 kb
Host smart-d2c1eb79-5663-4b50-8c1d-2cde00a2719f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24633
26231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2463326231
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.761761844
Short name T1827
Test name
Test status
Simulation time 151232652 ps
CPU time 0.82 seconds
Started Jun 23 05:18:05 PM PDT 24
Finished Jun 23 05:18:06 PM PDT 24
Peak memory 206036 kb
Host smart-129b52ce-0180-48b3-8546-02f17c5cde44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76176
1844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.761761844
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.229731766
Short name T2450
Test name
Test status
Simulation time 155951465 ps
CPU time 0.75 seconds
Started Jun 23 05:18:12 PM PDT 24
Finished Jun 23 05:18:13 PM PDT 24
Peak memory 206100 kb
Host smart-7058e54a-d076-43c9-bd76-8e6e81b53a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22973
1766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.229731766
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.3709443545
Short name T417
Test name
Test status
Simulation time 195278938 ps
CPU time 0.83 seconds
Started Jun 23 05:18:07 PM PDT 24
Finished Jun 23 05:18:09 PM PDT 24
Peak memory 206104 kb
Host smart-beb0a20e-fa51-46f9-ab01-96fbfaa5bf80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37094
43545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.3709443545
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2243661310
Short name T409
Test name
Test status
Simulation time 257936691 ps
CPU time 0.97 seconds
Started Jun 23 05:17:57 PM PDT 24
Finished Jun 23 05:17:59 PM PDT 24
Peak memory 206040 kb
Host smart-0465f5ec-c992-4b7e-90c6-8f8473954831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22436
61310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2243661310
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.280448013
Short name T1323
Test name
Test status
Simulation time 7998140427 ps
CPU time 218.28 seconds
Started Jun 23 05:18:03 PM PDT 24
Finished Jun 23 05:21:42 PM PDT 24
Peak memory 206272 kb
Host smart-15a0d063-a3fa-4749-b67a-aa10989c4f65
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=280448013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.280448013
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3324381908
Short name T1656
Test name
Test status
Simulation time 185702675 ps
CPU time 0.81 seconds
Started Jun 23 05:18:03 PM PDT 24
Finished Jun 23 05:18:05 PM PDT 24
Peak memory 206084 kb
Host smart-c05f207f-fcb4-4942-82a8-b77374a29393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33243
81908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3324381908
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.408438168
Short name T1644
Test name
Test status
Simulation time 173276238 ps
CPU time 0.81 seconds
Started Jun 23 05:18:15 PM PDT 24
Finished Jun 23 05:18:16 PM PDT 24
Peak memory 206028 kb
Host smart-8f87b17b-30d8-4be7-87ef-4dba95766ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40843
8168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.408438168
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.4864116
Short name T1972
Test name
Test status
Simulation time 5313729167 ps
CPU time 49.1 seconds
Started Jun 23 05:18:05 PM PDT 24
Finished Jun 23 05:18:55 PM PDT 24
Peak memory 206416 kb
Host smart-937300b5-8cba-4693-8cb6-80e3f3c61499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48641
16 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.4864116
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.1408277046
Short name T1268
Test name
Test status
Simulation time 4317033800 ps
CPU time 5.19 seconds
Started Jun 23 05:18:11 PM PDT 24
Finished Jun 23 05:18:16 PM PDT 24
Peak memory 206180 kb
Host smart-d529c03d-00ae-4856-8bd5-48fa25013108
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1408277046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.1408277046
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.278187631
Short name T1567
Test name
Test status
Simulation time 13369556129 ps
CPU time 12.54 seconds
Started Jun 23 05:18:08 PM PDT 24
Finished Jun 23 05:18:22 PM PDT 24
Peak memory 206172 kb
Host smart-92834133-ed5a-47db-acb3-d6fa5f0fc557
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=278187631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.278187631
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2623147379
Short name T2149
Test name
Test status
Simulation time 23359399882 ps
CPU time 28.23 seconds
Started Jun 23 05:18:12 PM PDT 24
Finished Jun 23 05:18:41 PM PDT 24
Peak memory 206168 kb
Host smart-36a3bb26-d88a-49a4-8668-81981f54f3c7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2623147379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.2623147379
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2604874944
Short name T1251
Test name
Test status
Simulation time 176622217 ps
CPU time 0.86 seconds
Started Jun 23 05:18:10 PM PDT 24
Finished Jun 23 05:18:12 PM PDT 24
Peak memory 206080 kb
Host smart-9e5de49a-3d9f-4162-85e0-08f268fb7780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26048
74944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2604874944
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.757889722
Short name T87
Test name
Test status
Simulation time 146466603 ps
CPU time 0.77 seconds
Started Jun 23 05:18:09 PM PDT 24
Finished Jun 23 05:18:10 PM PDT 24
Peak memory 206104 kb
Host smart-6f0c0fa9-b36d-4c45-bd37-5d2d09cab8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75788
9722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.757889722
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.3067076191
Short name T1539
Test name
Test status
Simulation time 272782410 ps
CPU time 1.07 seconds
Started Jun 23 05:18:07 PM PDT 24
Finished Jun 23 05:18:09 PM PDT 24
Peak memory 206096 kb
Host smart-85b2c73d-9ac0-41ab-ab2d-20a04328e8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30670
76191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.3067076191
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3167662003
Short name T220
Test name
Test status
Simulation time 297229703 ps
CPU time 0.99 seconds
Started Jun 23 05:18:10 PM PDT 24
Finished Jun 23 05:18:12 PM PDT 24
Peak memory 206028 kb
Host smart-33148677-0bef-46d0-bc90-fe888e0f192e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31676
62003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3167662003
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.693316221
Short name T1596
Test name
Test status
Simulation time 9255116095 ps
CPU time 16.65 seconds
Started Jun 23 05:18:10 PM PDT 24
Finished Jun 23 05:18:27 PM PDT 24
Peak memory 206380 kb
Host smart-7bcca250-efb0-456b-aaea-a001cf90b566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69331
6221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.693316221
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.2613797812
Short name T351
Test name
Test status
Simulation time 412132329 ps
CPU time 1.27 seconds
Started Jun 23 05:18:10 PM PDT 24
Finished Jun 23 05:18:12 PM PDT 24
Peak memory 206064 kb
Host smart-34e0b3c6-d72b-43e1-a624-10b11002a825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26137
97812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.2613797812
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.2541450567
Short name T1778
Test name
Test status
Simulation time 144330409 ps
CPU time 0.83 seconds
Started Jun 23 05:18:10 PM PDT 24
Finished Jun 23 05:18:11 PM PDT 24
Peak memory 206100 kb
Host smart-d90ab32a-6a06-43f0-81cf-7f0a7d43e784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25414
50567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.2541450567
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.2310521666
Short name T2498
Test name
Test status
Simulation time 63909586 ps
CPU time 0.66 seconds
Started Jun 23 05:18:13 PM PDT 24
Finished Jun 23 05:18:13 PM PDT 24
Peak memory 206092 kb
Host smart-d860907b-1ec5-473f-abad-526fafe911f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23105
21666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2310521666
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1291576213
Short name T775
Test name
Test status
Simulation time 984256092 ps
CPU time 2.18 seconds
Started Jun 23 05:18:09 PM PDT 24
Finished Jun 23 05:18:12 PM PDT 24
Peak memory 206340 kb
Host smart-66e78eb8-446d-4244-b1b3-3f17614a6f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12915
76213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1291576213
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3591288896
Short name T1524
Test name
Test status
Simulation time 202393433 ps
CPU time 1.33 seconds
Started Jun 23 05:18:09 PM PDT 24
Finished Jun 23 05:18:11 PM PDT 24
Peak memory 206328 kb
Host smart-44167968-04d2-4d86-b111-3f65f7b9e9f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35912
88896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3591288896
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.608836560
Short name T957
Test name
Test status
Simulation time 252731493 ps
CPU time 0.87 seconds
Started Jun 23 05:18:27 PM PDT 24
Finished Jun 23 05:18:28 PM PDT 24
Peak memory 206108 kb
Host smart-d732edc0-e5de-4248-bc05-04e28ffa4785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60883
6560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.608836560
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2579686330
Short name T1625
Test name
Test status
Simulation time 220293780 ps
CPU time 0.81 seconds
Started Jun 23 05:18:21 PM PDT 24
Finished Jun 23 05:18:23 PM PDT 24
Peak memory 206096 kb
Host smart-5ba0ca9c-e93e-4889-9ab4-bbce93727dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25796
86330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2579686330
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1686483129
Short name T332
Test name
Test status
Simulation time 229825023 ps
CPU time 1 seconds
Started Jun 23 05:18:08 PM PDT 24
Finished Jun 23 05:18:09 PM PDT 24
Peak memory 206068 kb
Host smart-0fccd83d-92e5-4a20-b15c-1db6c15f2d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16864
83129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1686483129
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.1550700286
Short name T2276
Test name
Test status
Simulation time 223391891 ps
CPU time 0.9 seconds
Started Jun 23 05:18:17 PM PDT 24
Finished Jun 23 05:18:18 PM PDT 24
Peak memory 206220 kb
Host smart-b3e88f8b-a2e0-4b02-b8d6-1b3b9abcb5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15507
00286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.1550700286
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.4005764065
Short name T1247
Test name
Test status
Simulation time 23282765925 ps
CPU time 20.78 seconds
Started Jun 23 05:18:17 PM PDT 24
Finished Jun 23 05:18:38 PM PDT 24
Peak memory 206180 kb
Host smart-f3563a16-4ae0-4555-a544-7ae0796475a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40057
64065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.4005764065
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1430276306
Short name T1908
Test name
Test status
Simulation time 3308428052 ps
CPU time 3.68 seconds
Started Jun 23 05:18:16 PM PDT 24
Finished Jun 23 05:18:20 PM PDT 24
Peak memory 206160 kb
Host smart-86533cb0-0940-4ec0-aa7c-71825abebef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14302
76306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1430276306
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.3524962435
Short name T2377
Test name
Test status
Simulation time 10918016557 ps
CPU time 108.98 seconds
Started Jun 23 05:18:15 PM PDT 24
Finished Jun 23 05:20:05 PM PDT 24
Peak memory 206376 kb
Host smart-4483f4d3-7798-40a9-8c6a-dc0d38f2b759
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3524962435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.3524962435
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.4164590334
Short name T1622
Test name
Test status
Simulation time 255484973 ps
CPU time 0.97 seconds
Started Jun 23 05:18:22 PM PDT 24
Finished Jun 23 05:18:24 PM PDT 24
Peak memory 206128 kb
Host smart-8ae00073-41db-47fb-b1fd-c89813dec94f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4164590334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.4164590334
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3864854003
Short name T1180
Test name
Test status
Simulation time 204852966 ps
CPU time 0.85 seconds
Started Jun 23 05:18:18 PM PDT 24
Finished Jun 23 05:18:19 PM PDT 24
Peak memory 206116 kb
Host smart-9d6db378-454e-4c1c-ad77-c32e8f83f424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38648
54003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3864854003
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.2408632289
Short name T1479
Test name
Test status
Simulation time 12043908182 ps
CPU time 87.47 seconds
Started Jun 23 05:18:17 PM PDT 24
Finished Jun 23 05:19:45 PM PDT 24
Peak memory 206352 kb
Host smart-ea26b40a-a718-4710-84e8-220fcb2ffb7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24086
32289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.2408632289
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.3195100116
Short name T84
Test name
Test status
Simulation time 9021357969 ps
CPU time 91.22 seconds
Started Jun 23 05:18:17 PM PDT 24
Finished Jun 23 05:19:49 PM PDT 24
Peak memory 206552 kb
Host smart-19bbc2a3-6963-430e-8bd7-8018581ffce7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3195100116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.3195100116
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.2528470678
Short name T1974
Test name
Test status
Simulation time 166354023 ps
CPU time 0.81 seconds
Started Jun 23 05:18:21 PM PDT 24
Finished Jun 23 05:18:22 PM PDT 24
Peak memory 206012 kb
Host smart-bb0a27a4-6057-45b3-926e-59bb946e79ac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2528470678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.2528470678
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1440114211
Short name T282
Test name
Test status
Simulation time 155843386 ps
CPU time 0.82 seconds
Started Jun 23 05:18:13 PM PDT 24
Finished Jun 23 05:18:14 PM PDT 24
Peak memory 206048 kb
Host smart-e9dcf6d0-5eaf-4410-990f-67fe8e2db169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14401
14211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1440114211
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.416305441
Short name T2375
Test name
Test status
Simulation time 197605408 ps
CPU time 0.82 seconds
Started Jun 23 05:18:19 PM PDT 24
Finished Jun 23 05:18:20 PM PDT 24
Peak memory 206100 kb
Host smart-7eaf369b-f9ce-43c4-a19a-273517ef6e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41630
5441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.416305441
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.3087467042
Short name T668
Test name
Test status
Simulation time 148747680 ps
CPU time 0.8 seconds
Started Jun 23 05:18:19 PM PDT 24
Finished Jun 23 05:18:20 PM PDT 24
Peak memory 206100 kb
Host smart-e836ae59-acdf-49b3-87f2-91f71a164488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30874
67042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.3087467042
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.4144034163
Short name T1380
Test name
Test status
Simulation time 235613212 ps
CPU time 0.93 seconds
Started Jun 23 05:18:15 PM PDT 24
Finished Jun 23 05:18:17 PM PDT 24
Peak memory 206104 kb
Host smart-1562283a-1062-4a19-868f-b76e21b4896a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41440
34163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.4144034163
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.4172373564
Short name T288
Test name
Test status
Simulation time 175264627 ps
CPU time 0.81 seconds
Started Jun 23 05:18:15 PM PDT 24
Finished Jun 23 05:18:16 PM PDT 24
Peak memory 206052 kb
Host smart-c1aba274-0c65-4dbc-ba91-4b50da720de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41723
73564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.4172373564
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.2917482202
Short name T179
Test name
Test status
Simulation time 164590442 ps
CPU time 0.8 seconds
Started Jun 23 05:18:24 PM PDT 24
Finished Jun 23 05:18:25 PM PDT 24
Peak memory 206008 kb
Host smart-b32262bc-6f1b-48aa-967a-03b0f485031a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29174
82202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.2917482202
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.1631255019
Short name T1060
Test name
Test status
Simulation time 228677981 ps
CPU time 0.96 seconds
Started Jun 23 05:18:20 PM PDT 24
Finished Jun 23 05:18:22 PM PDT 24
Peak memory 206072 kb
Host smart-8d0c855f-fb38-46e4-89fe-27e3f277c951
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1631255019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.1631255019
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2262409493
Short name T1067
Test name
Test status
Simulation time 177309567 ps
CPU time 0.84 seconds
Started Jun 23 05:18:26 PM PDT 24
Finished Jun 23 05:18:28 PM PDT 24
Peak memory 206112 kb
Host smart-48644465-1510-4c5a-af1a-ab3e78587c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22624
09493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2262409493
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.3336125690
Short name T2110
Test name
Test status
Simulation time 46337550 ps
CPU time 0.74 seconds
Started Jun 23 05:18:26 PM PDT 24
Finished Jun 23 05:18:27 PM PDT 24
Peak memory 206112 kb
Host smart-f856a6dc-0040-46e3-98e3-77879e2af462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33361
25690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3336125690
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.764108663
Short name T44
Test name
Test status
Simulation time 12733322796 ps
CPU time 28.41 seconds
Started Jun 23 05:18:15 PM PDT 24
Finished Jun 23 05:18:44 PM PDT 24
Peak memory 206376 kb
Host smart-9867bdff-7806-4142-af89-e173e0c98314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76410
8663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.764108663
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.4078949384
Short name T1353
Test name
Test status
Simulation time 177405955 ps
CPU time 0.82 seconds
Started Jun 23 05:18:14 PM PDT 24
Finished Jun 23 05:18:15 PM PDT 24
Peak memory 206124 kb
Host smart-89ebc232-bf79-477a-9aeb-09fbd4bebce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40789
49384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.4078949384
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.107952981
Short name T1866
Test name
Test status
Simulation time 250814086 ps
CPU time 0.94 seconds
Started Jun 23 05:18:14 PM PDT 24
Finished Jun 23 05:18:15 PM PDT 24
Peak memory 206092 kb
Host smart-96e184d7-ac64-4f97-a9e6-e78d6caa9c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10795
2981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.107952981
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.110461102
Short name T901
Test name
Test status
Simulation time 232455350 ps
CPU time 0.88 seconds
Started Jun 23 05:18:23 PM PDT 24
Finished Jun 23 05:18:25 PM PDT 24
Peak memory 206104 kb
Host smart-cbc0a76c-e852-41cd-9a7b-c5f7327ed011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11046
1102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.110461102
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1687347022
Short name T2218
Test name
Test status
Simulation time 183209248 ps
CPU time 0.78 seconds
Started Jun 23 05:18:15 PM PDT 24
Finished Jun 23 05:18:17 PM PDT 24
Peak memory 206068 kb
Host smart-cb39e4e2-2c68-4f01-9f4e-0c5cde5a9a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16873
47022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1687347022
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.3150902666
Short name T2351
Test name
Test status
Simulation time 172043176 ps
CPU time 0.85 seconds
Started Jun 23 05:18:16 PM PDT 24
Finished Jun 23 05:18:18 PM PDT 24
Peak memory 206040 kb
Host smart-68e12a06-446f-49e2-ae2d-06b12db7949f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31509
02666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.3150902666
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1065202186
Short name T2308
Test name
Test status
Simulation time 155163647 ps
CPU time 0.8 seconds
Started Jun 23 05:18:23 PM PDT 24
Finished Jun 23 05:18:24 PM PDT 24
Peak memory 206068 kb
Host smart-e504a1e0-9630-41c4-a703-f67b36822323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10652
02186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1065202186
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2120895892
Short name T745
Test name
Test status
Simulation time 157407484 ps
CPU time 0.79 seconds
Started Jun 23 05:18:20 PM PDT 24
Finished Jun 23 05:18:21 PM PDT 24
Peak memory 206108 kb
Host smart-7219ba56-8bbd-4c4c-be09-40a52adf1f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21208
95892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2120895892
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3201841728
Short name T1193
Test name
Test status
Simulation time 276413344 ps
CPU time 0.92 seconds
Started Jun 23 05:18:10 PM PDT 24
Finished Jun 23 05:18:12 PM PDT 24
Peak memory 206108 kb
Host smart-ecaa0809-6128-4546-b728-19c810d11749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32018
41728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3201841728
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.4210262712
Short name T1092
Test name
Test status
Simulation time 9314696964 ps
CPU time 267.87 seconds
Started Jun 23 05:18:17 PM PDT 24
Finished Jun 23 05:22:45 PM PDT 24
Peak memory 206340 kb
Host smart-398d3ca0-2692-46af-8754-0cda65d3c3a7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4210262712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.4210262712
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1803170134
Short name T791
Test name
Test status
Simulation time 185690995 ps
CPU time 0.81 seconds
Started Jun 23 05:18:20 PM PDT 24
Finished Jun 23 05:18:21 PM PDT 24
Peak memory 206128 kb
Host smart-7d961c1d-3e62-4352-8f6f-9d5122f6d16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18031
70134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1803170134
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.870039112
Short name T753
Test name
Test status
Simulation time 184658675 ps
CPU time 0.8 seconds
Started Jun 23 05:18:18 PM PDT 24
Finished Jun 23 05:18:19 PM PDT 24
Peak memory 206100 kb
Host smart-bf52b986-7e72-414f-ba4a-e857e8b38ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87003
9112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.870039112
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.780420387
Short name T2079
Test name
Test status
Simulation time 8077624459 ps
CPU time 57.37 seconds
Started Jun 23 05:18:15 PM PDT 24
Finished Jun 23 05:19:12 PM PDT 24
Peak memory 206324 kb
Host smart-48bce941-c9be-4e11-ad67-0e3075e6d554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78042
0387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.780420387
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.3704647162
Short name T1979
Test name
Test status
Simulation time 3776113133 ps
CPU time 4.46 seconds
Started Jun 23 05:18:25 PM PDT 24
Finished Jun 23 05:18:30 PM PDT 24
Peak memory 206272 kb
Host smart-e4e5d127-4a37-47b5-9ca5-db30d636691c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3704647162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.3704647162
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.886781828
Short name T1419
Test name
Test status
Simulation time 13382550318 ps
CPU time 12.51 seconds
Started Jun 23 05:18:20 PM PDT 24
Finished Jun 23 05:18:33 PM PDT 24
Peak memory 206172 kb
Host smart-a24475ed-3979-4afd-861e-e70467529860
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=886781828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.886781828
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.63615130
Short name T517
Test name
Test status
Simulation time 23530036108 ps
CPU time 21.85 seconds
Started Jun 23 05:18:21 PM PDT 24
Finished Jun 23 05:18:43 PM PDT 24
Peak memory 206356 kb
Host smart-78a856da-7b1b-40e2-89e3-6f91c8cc2128
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=63615130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.63615130
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2768473559
Short name T2321
Test name
Test status
Simulation time 211994280 ps
CPU time 0.89 seconds
Started Jun 23 05:18:27 PM PDT 24
Finished Jun 23 05:18:28 PM PDT 24
Peak memory 206104 kb
Host smart-802f9210-3801-40a4-9877-564f9b16a0f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27684
73559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2768473559
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.4099528596
Short name T2225
Test name
Test status
Simulation time 165418885 ps
CPU time 0.81 seconds
Started Jun 23 05:18:20 PM PDT 24
Finished Jun 23 05:18:22 PM PDT 24
Peak memory 206020 kb
Host smart-c9f261d1-ecc5-499e-b8be-52545c4f101e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40995
28596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.4099528596
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.117063856
Short name T1658
Test name
Test status
Simulation time 283467810 ps
CPU time 1.09 seconds
Started Jun 23 05:18:23 PM PDT 24
Finished Jun 23 05:18:25 PM PDT 24
Peak memory 206108 kb
Host smart-4a4776bc-a02c-40ab-b14f-d498df2d0761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11706
3856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.117063856
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.3150634507
Short name T1158
Test name
Test status
Simulation time 805268582 ps
CPU time 2.24 seconds
Started Jun 23 05:18:27 PM PDT 24
Finished Jun 23 05:18:30 PM PDT 24
Peak memory 206356 kb
Host smart-00c2f746-d45e-4c48-80b4-38248c2f9e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31506
34507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.3150634507
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.105155654
Short name T2384
Test name
Test status
Simulation time 19929520713 ps
CPU time 38.89 seconds
Started Jun 23 05:18:25 PM PDT 24
Finished Jun 23 05:19:05 PM PDT 24
Peak memory 206360 kb
Host smart-d8a05a96-1253-46ea-8021-27d5e771f1a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10515
5654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.105155654
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.811426620
Short name T1642
Test name
Test status
Simulation time 463849452 ps
CPU time 1.47 seconds
Started Jun 23 05:18:23 PM PDT 24
Finished Jun 23 05:18:25 PM PDT 24
Peak memory 206260 kb
Host smart-342d6df3-766a-4c36-9436-6162bec07c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81142
6620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.811426620
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3439756671
Short name T614
Test name
Test status
Simulation time 158348786 ps
CPU time 0.77 seconds
Started Jun 23 05:18:20 PM PDT 24
Finished Jun 23 05:18:22 PM PDT 24
Peak memory 206024 kb
Host smart-e711b08f-ef75-466b-b3bb-ca33d6cdcb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34397
56671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3439756671
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.128821584
Short name T1722
Test name
Test status
Simulation time 52920660 ps
CPU time 0.68 seconds
Started Jun 23 05:18:22 PM PDT 24
Finished Jun 23 05:18:23 PM PDT 24
Peak memory 206096 kb
Host smart-7fc326a3-4177-4717-9b17-b1f70a6b9d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12882
1584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.128821584
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.703032206
Short name T880
Test name
Test status
Simulation time 877838156 ps
CPU time 2.11 seconds
Started Jun 23 05:18:26 PM PDT 24
Finished Jun 23 05:18:28 PM PDT 24
Peak memory 206260 kb
Host smart-5954f4ca-ac0f-471a-9bbd-ce516a5a39e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70303
2206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.703032206
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1743979982
Short name T2380
Test name
Test status
Simulation time 448222437 ps
CPU time 2.51 seconds
Started Jun 23 05:18:22 PM PDT 24
Finished Jun 23 05:18:25 PM PDT 24
Peak memory 206344 kb
Host smart-ca57c7fe-83e8-48c0-8a34-7d48ef29e2f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17439
79982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1743979982
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.3033132078
Short name T570
Test name
Test status
Simulation time 213597516 ps
CPU time 0.87 seconds
Started Jun 23 05:18:31 PM PDT 24
Finished Jun 23 05:18:32 PM PDT 24
Peak memory 206112 kb
Host smart-c8f43019-49de-4498-8f0e-28c177d14b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30331
32078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.3033132078
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.383519478
Short name T1191
Test name
Test status
Simulation time 138166530 ps
CPU time 0.78 seconds
Started Jun 23 05:18:31 PM PDT 24
Finished Jun 23 05:18:33 PM PDT 24
Peak memory 206088 kb
Host smart-c3d99d7f-bfb9-40bf-8ef7-c6ebe4ed8a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38351
9478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.383519478
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1113048969
Short name T822
Test name
Test status
Simulation time 255082458 ps
CPU time 0.99 seconds
Started Jun 23 05:18:22 PM PDT 24
Finished Jun 23 05:18:23 PM PDT 24
Peak memory 206060 kb
Host smart-03542e3c-5c90-456b-9a5f-57666d87882b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11130
48969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1113048969
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3412861074
Short name T685
Test name
Test status
Simulation time 178505499 ps
CPU time 0.83 seconds
Started Jun 23 05:18:28 PM PDT 24
Finished Jun 23 05:18:29 PM PDT 24
Peak memory 206092 kb
Host smart-104f5f76-f15b-4aae-ba61-f3c08fd3e640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34128
61074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3412861074
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.2479842377
Short name T718
Test name
Test status
Simulation time 23275763638 ps
CPU time 21.94 seconds
Started Jun 23 05:18:29 PM PDT 24
Finished Jun 23 05:18:51 PM PDT 24
Peak memory 206136 kb
Host smart-a92c44bd-c5d7-47ae-aaab-cd451028322a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24798
42377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.2479842377
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.521483525
Short name T1127
Test name
Test status
Simulation time 3352032247 ps
CPU time 3.59 seconds
Started Jun 23 05:18:29 PM PDT 24
Finished Jun 23 05:18:33 PM PDT 24
Peak memory 206160 kb
Host smart-d27c6c62-0c15-4370-9c34-78aad61b0aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52148
3525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.521483525
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.2039910970
Short name T1716
Test name
Test status
Simulation time 3709520767 ps
CPU time 40.01 seconds
Started Jun 23 05:18:28 PM PDT 24
Finished Jun 23 05:19:09 PM PDT 24
Peak memory 206352 kb
Host smart-48b19f3a-8495-4fdc-ab5f-8ba54e116234
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2039910970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.2039910970
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.3564216169
Short name T1971
Test name
Test status
Simulation time 237763121 ps
CPU time 1.04 seconds
Started Jun 23 05:18:30 PM PDT 24
Finished Jun 23 05:18:31 PM PDT 24
Peak memory 206032 kb
Host smart-be6e6d87-90c8-4df7-8f69-faf082e3e4f3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3564216169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.3564216169
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1763556867
Short name T2405
Test name
Test status
Simulation time 194062145 ps
CPU time 0.85 seconds
Started Jun 23 05:18:29 PM PDT 24
Finished Jun 23 05:18:30 PM PDT 24
Peak memory 206072 kb
Host smart-9677f7be-949a-4a5f-af97-199a61768ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17635
56867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1763556867
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.2955907841
Short name T837
Test name
Test status
Simulation time 5426422222 ps
CPU time 40.36 seconds
Started Jun 23 05:18:29 PM PDT 24
Finished Jun 23 05:19:10 PM PDT 24
Peak memory 206376 kb
Host smart-0d509e69-bf43-41ec-a2c6-dba87b888139
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2955907841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.2955907841
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.4147727389
Short name T1944
Test name
Test status
Simulation time 154917407 ps
CPU time 0.83 seconds
Started Jun 23 05:18:31 PM PDT 24
Finished Jun 23 05:18:32 PM PDT 24
Peak memory 206128 kb
Host smart-509b7a4d-3a38-4aea-92c5-86ddc715b7c7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4147727389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.4147727389
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.107311213
Short name T1890
Test name
Test status
Simulation time 169046054 ps
CPU time 0.83 seconds
Started Jun 23 05:18:29 PM PDT 24
Finished Jun 23 05:18:30 PM PDT 24
Peak memory 206084 kb
Host smart-d8d3a5c8-b230-436a-8c88-41b3548c93d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10731
1213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.107311213
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.801787717
Short name T1619
Test name
Test status
Simulation time 211147319 ps
CPU time 0.83 seconds
Started Jun 23 05:18:30 PM PDT 24
Finished Jun 23 05:18:32 PM PDT 24
Peak memory 206100 kb
Host smart-1c7c399c-f501-470c-b840-fce7ad9700e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80178
7717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.801787717
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.550499608
Short name T1402
Test name
Test status
Simulation time 185466418 ps
CPU time 0.75 seconds
Started Jun 23 05:18:27 PM PDT 24
Finished Jun 23 05:18:28 PM PDT 24
Peak memory 206096 kb
Host smart-04e72580-8491-42ed-814f-3f9473bdc906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55049
9608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.550499608
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3141451315
Short name T636
Test name
Test status
Simulation time 180774782 ps
CPU time 0.9 seconds
Started Jun 23 05:18:30 PM PDT 24
Finished Jun 23 05:18:31 PM PDT 24
Peak memory 206004 kb
Host smart-01043504-5d19-43c0-9219-29ea29fdc31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31414
51315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3141451315
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.710293176
Short name T364
Test name
Test status
Simulation time 179086917 ps
CPU time 0.84 seconds
Started Jun 23 05:18:30 PM PDT 24
Finished Jun 23 05:18:32 PM PDT 24
Peak memory 206028 kb
Host smart-7cd22781-1440-43f5-9402-ba348bca0285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71029
3176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.710293176
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.3341027798
Short name T871
Test name
Test status
Simulation time 211122491 ps
CPU time 0.88 seconds
Started Jun 23 05:18:31 PM PDT 24
Finished Jun 23 05:18:33 PM PDT 24
Peak memory 206120 kb
Host smart-133c6407-da50-47c8-875d-e42c6e1d4dbe
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3341027798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.3341027798
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1895726829
Short name T1272
Test name
Test status
Simulation time 153437691 ps
CPU time 0.75 seconds
Started Jun 23 05:18:31 PM PDT 24
Finished Jun 23 05:18:33 PM PDT 24
Peak memory 206108 kb
Host smart-30616aa0-05d8-4269-9b7b-b864c8a2f268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18957
26829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1895726829
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1502865638
Short name T1640
Test name
Test status
Simulation time 52668504 ps
CPU time 0.68 seconds
Started Jun 23 05:18:29 PM PDT 24
Finished Jun 23 05:18:30 PM PDT 24
Peak memory 206076 kb
Host smart-51412525-5560-4f95-aef5-67c99e0f9d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15028
65638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1502865638
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3718502229
Short name T2210
Test name
Test status
Simulation time 7224057915 ps
CPU time 15.8 seconds
Started Jun 23 05:18:29 PM PDT 24
Finished Jun 23 05:18:45 PM PDT 24
Peak memory 206396 kb
Host smart-586d357f-968c-4ee5-810f-b7d63cdd48cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37185
02229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3718502229
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1052872291
Short name T1895
Test name
Test status
Simulation time 191737418 ps
CPU time 0.85 seconds
Started Jun 23 05:18:29 PM PDT 24
Finished Jun 23 05:18:30 PM PDT 24
Peak memory 206064 kb
Host smart-95ed77a0-a60d-45a5-ba87-10658ea85faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10528
72291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1052872291
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1932249262
Short name T346
Test name
Test status
Simulation time 185073101 ps
CPU time 0.82 seconds
Started Jun 23 05:18:30 PM PDT 24
Finished Jun 23 05:18:32 PM PDT 24
Peak memory 206100 kb
Host smart-72481d23-5ddf-4ef3-a69d-c7eb3ccd2783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19322
49262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1932249262
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.987736058
Short name T1325
Test name
Test status
Simulation time 247238174 ps
CPU time 0.9 seconds
Started Jun 23 05:18:30 PM PDT 24
Finished Jun 23 05:18:31 PM PDT 24
Peak memory 206060 kb
Host smart-b64de9e2-fdf2-4a89-b701-03bd8b80cacf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98773
6058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.987736058
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.2975399657
Short name T2103
Test name
Test status
Simulation time 162977499 ps
CPU time 0.87 seconds
Started Jun 23 05:18:27 PM PDT 24
Finished Jun 23 05:18:29 PM PDT 24
Peak memory 206060 kb
Host smart-6cd2494e-37b9-4db5-8496-748ccfbb2830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29753
99657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.2975399657
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.4152498948
Short name T1796
Test name
Test status
Simulation time 158035811 ps
CPU time 0.79 seconds
Started Jun 23 05:18:28 PM PDT 24
Finished Jun 23 05:18:29 PM PDT 24
Peak memory 206088 kb
Host smart-7df522b9-878e-4ab9-9c03-c4700943f5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41524
98948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.4152498948
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1009383543
Short name T2207
Test name
Test status
Simulation time 211945597 ps
CPU time 0.85 seconds
Started Jun 23 05:18:28 PM PDT 24
Finished Jun 23 05:18:29 PM PDT 24
Peak memory 206044 kb
Host smart-eb1275a2-4d8a-4610-b055-b6555a4aadc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10093
83543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1009383543
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.405467758
Short name T2125
Test name
Test status
Simulation time 167441889 ps
CPU time 0.82 seconds
Started Jun 23 05:18:31 PM PDT 24
Finished Jun 23 05:18:33 PM PDT 24
Peak memory 206120 kb
Host smart-1d360558-d93b-428a-a96f-40c2f25e6e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40546
7758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.405467758
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3697447247
Short name T2121
Test name
Test status
Simulation time 245414788 ps
CPU time 0.98 seconds
Started Jun 23 05:18:25 PM PDT 24
Finished Jun 23 05:18:27 PM PDT 24
Peak memory 205940 kb
Host smart-38df3174-01c1-4fe7-9f4e-73ac27198039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36974
47247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3697447247
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.3639409416
Short name T1403
Test name
Test status
Simulation time 12111750826 ps
CPU time 114.37 seconds
Started Jun 23 05:18:29 PM PDT 24
Finished Jun 23 05:20:24 PM PDT 24
Peak memory 206204 kb
Host smart-c2e2878f-9f46-4af3-adf5-45620a2641b1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3639409416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.3639409416
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1604048666
Short name T2102
Test name
Test status
Simulation time 164061420 ps
CPU time 0.85 seconds
Started Jun 23 05:18:30 PM PDT 24
Finished Jun 23 05:18:31 PM PDT 24
Peak memory 206120 kb
Host smart-b90e5dd4-3263-4d0c-bb5d-13608a778ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16040
48666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1604048666
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.548781497
Short name T457
Test name
Test status
Simulation time 185204931 ps
CPU time 0.85 seconds
Started Jun 23 05:18:31 PM PDT 24
Finished Jun 23 05:18:32 PM PDT 24
Peak memory 206104 kb
Host smart-29007109-fe70-485f-97ae-222705aa1f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54878
1497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.548781497
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.476885308
Short name T1597
Test name
Test status
Simulation time 14560262881 ps
CPU time 101.21 seconds
Started Jun 23 05:18:30 PM PDT 24
Finished Jun 23 05:20:12 PM PDT 24
Peak memory 206384 kb
Host smart-0e77d938-b907-4fc0-b730-71db308e2081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47688
5308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.476885308
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3622716548
Short name T212
Test name
Test status
Simulation time 3724914422 ps
CPU time 4.45 seconds
Started Jun 23 05:18:30 PM PDT 24
Finished Jun 23 05:18:36 PM PDT 24
Peak memory 206104 kb
Host smart-3f0f3ac2-873e-4e73-b6d1-aa6fb30309ed
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3622716548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.3622716548
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.762818702
Short name T1133
Test name
Test status
Simulation time 13367740758 ps
CPU time 11.81 seconds
Started Jun 23 05:18:31 PM PDT 24
Finished Jun 23 05:18:44 PM PDT 24
Peak memory 206164 kb
Host smart-84701921-8d05-46f6-b067-8cd5aefac93f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=762818702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.762818702
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3957708974
Short name T446
Test name
Test status
Simulation time 23378235810 ps
CPU time 21.29 seconds
Started Jun 23 05:18:31 PM PDT 24
Finished Jun 23 05:18:53 PM PDT 24
Peak memory 206396 kb
Host smart-3c654c77-212c-4bf3-8abc-26f62a7c55d8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3957708974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.3957708974
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3862997468
Short name T795
Test name
Test status
Simulation time 190108808 ps
CPU time 0.89 seconds
Started Jun 23 05:18:31 PM PDT 24
Finished Jun 23 05:18:33 PM PDT 24
Peak memory 206108 kb
Host smart-0ce220c7-543e-4a2e-8366-69af670b9324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38629
97468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3862997468
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1860946804
Short name T414
Test name
Test status
Simulation time 163012044 ps
CPU time 0.74 seconds
Started Jun 23 05:18:29 PM PDT 24
Finished Jun 23 05:18:31 PM PDT 24
Peak memory 206036 kb
Host smart-1e69f6c9-c499-4c14-a6dd-4e1c5f32292b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18609
46804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1860946804
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.4102165054
Short name T62
Test name
Test status
Simulation time 400703973 ps
CPU time 1.33 seconds
Started Jun 23 05:18:39 PM PDT 24
Finished Jun 23 05:18:41 PM PDT 24
Peak memory 206104 kb
Host smart-a45e1478-2f5a-4e56-97bb-fa13e15f44d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41021
65054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.4102165054
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.3523719908
Short name T1351
Test name
Test status
Simulation time 576858705 ps
CPU time 1.53 seconds
Started Jun 23 05:18:38 PM PDT 24
Finished Jun 23 05:18:40 PM PDT 24
Peak memory 206012 kb
Host smart-6a961a95-5d6f-4223-b978-b9fe956f6635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35237
19908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3523719908
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.562222133
Short name T1068
Test name
Test status
Simulation time 13648038589 ps
CPU time 28.33 seconds
Started Jun 23 05:18:37 PM PDT 24
Finished Jun 23 05:19:06 PM PDT 24
Peak memory 206448 kb
Host smart-55a188f4-587d-43ae-8108-5145725ea7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56222
2133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.562222133
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.456267447
Short name T2465
Test name
Test status
Simulation time 454935170 ps
CPU time 1.39 seconds
Started Jun 23 05:18:39 PM PDT 24
Finished Jun 23 05:18:41 PM PDT 24
Peak memory 206104 kb
Host smart-bbf223de-f101-4d49-b32b-1d95c2a8a1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45626
7447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.456267447
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.2723369666
Short name T734
Test name
Test status
Simulation time 136439718 ps
CPU time 0.76 seconds
Started Jun 23 05:18:38 PM PDT 24
Finished Jun 23 05:18:40 PM PDT 24
Peak memory 206024 kb
Host smart-37f1a57a-9c04-40ad-92d8-dc4b11269591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27233
69666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.2723369666
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1892662149
Short name T1704
Test name
Test status
Simulation time 67516775 ps
CPU time 0.7 seconds
Started Jun 23 05:18:40 PM PDT 24
Finished Jun 23 05:18:41 PM PDT 24
Peak memory 206096 kb
Host smart-2dee2b6c-03f7-41df-958c-da2a5b5a2289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18926
62149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1892662149
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.103902401
Short name T1454
Test name
Test status
Simulation time 1016524505 ps
CPU time 2.36 seconds
Started Jun 23 05:18:43 PM PDT 24
Finished Jun 23 05:18:47 PM PDT 24
Peak memory 206284 kb
Host smart-24256525-1893-429b-8d2d-1596c29a8549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10390
2401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.103902401
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2355930375
Short name T616
Test name
Test status
Simulation time 184281659 ps
CPU time 2.09 seconds
Started Jun 23 05:18:38 PM PDT 24
Finished Jun 23 05:18:41 PM PDT 24
Peak memory 206252 kb
Host smart-482c0f02-7743-4ab5-be04-48973f13fae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23559
30375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2355930375
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.893578519
Short name T2301
Test name
Test status
Simulation time 166919937 ps
CPU time 0.79 seconds
Started Jun 23 05:18:42 PM PDT 24
Finished Jun 23 05:18:44 PM PDT 24
Peak memory 206108 kb
Host smart-ca645d8b-ff90-4b8c-94b3-d0aa58e5391b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89357
8519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.893578519
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.80176956
Short name T557
Test name
Test status
Simulation time 135900215 ps
CPU time 0.75 seconds
Started Jun 23 05:18:44 PM PDT 24
Finished Jun 23 05:18:46 PM PDT 24
Peak memory 206064 kb
Host smart-13be01dd-9e80-4b2d-acdd-f168b53bdaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80176
956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.80176956
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1405128646
Short name T1469
Test name
Test status
Simulation time 191496453 ps
CPU time 0.87 seconds
Started Jun 23 05:18:41 PM PDT 24
Finished Jun 23 05:18:43 PM PDT 24
Peak memory 205868 kb
Host smart-2360a50e-ee3e-41f6-a133-602aba4ffc0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14051
28646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1405128646
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2337183105
Short name T2238
Test name
Test status
Simulation time 191043807 ps
CPU time 0.85 seconds
Started Jun 23 05:18:38 PM PDT 24
Finished Jun 23 05:18:39 PM PDT 24
Peak memory 206032 kb
Host smart-3037a6eb-8be8-4cec-8931-50a3c74aee87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23371
83105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2337183105
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.2568071887
Short name T342
Test name
Test status
Simulation time 23271755335 ps
CPU time 25.46 seconds
Started Jun 23 05:18:37 PM PDT 24
Finished Jun 23 05:19:03 PM PDT 24
Peak memory 206156 kb
Host smart-a38da7a3-50dc-4702-961e-5d9f06490764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25680
71887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.2568071887
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.1475725221
Short name T2460
Test name
Test status
Simulation time 3345765609 ps
CPU time 3.94 seconds
Started Jun 23 05:18:43 PM PDT 24
Finished Jun 23 05:18:48 PM PDT 24
Peak memory 206168 kb
Host smart-8459225b-ea29-444c-843d-94c1f85ddb99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14757
25221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1475725221
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.3688960228
Short name T543
Test name
Test status
Simulation time 7304300108 ps
CPU time 54.82 seconds
Started Jun 23 05:18:38 PM PDT 24
Finished Jun 23 05:19:34 PM PDT 24
Peak memory 206276 kb
Host smart-d1d82f7d-ff6b-4571-9501-fe6dfb858aac
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3688960228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.3688960228
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.4222270156
Short name T1149
Test name
Test status
Simulation time 239056746 ps
CPU time 0.96 seconds
Started Jun 23 05:18:44 PM PDT 24
Finished Jun 23 05:18:46 PM PDT 24
Peak memory 206100 kb
Host smart-cc3a0322-b5ec-445b-ad68-c9114ea41cad
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4222270156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.4222270156
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1061400930
Short name T757
Test name
Test status
Simulation time 192959368 ps
CPU time 0.84 seconds
Started Jun 23 05:18:38 PM PDT 24
Finished Jun 23 05:18:39 PM PDT 24
Peak memory 206104 kb
Host smart-e86641b3-bc6c-4b51-beac-d4ef0579a0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10614
00930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1061400930
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.3309631626
Short name T2072
Test name
Test status
Simulation time 5048940767 ps
CPU time 38.23 seconds
Started Jun 23 05:18:39 PM PDT 24
Finished Jun 23 05:19:18 PM PDT 24
Peak memory 206340 kb
Host smart-d34670f9-e021-4296-927a-3d197158ec76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33096
31626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.3309631626
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.2107073739
Short name T1489
Test name
Test status
Simulation time 12262192654 ps
CPU time 333.65 seconds
Started Jun 23 05:18:41 PM PDT 24
Finished Jun 23 05:24:16 PM PDT 24
Peak memory 206112 kb
Host smart-0d5078f6-00c9-433b-a462-e8bfdd5453fc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2107073739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.2107073739
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.2493685161
Short name T1054
Test name
Test status
Simulation time 170736219 ps
CPU time 0.83 seconds
Started Jun 23 05:18:42 PM PDT 24
Finished Jun 23 05:18:44 PM PDT 24
Peak memory 206052 kb
Host smart-d261f920-4f88-45fe-a065-af6ef0f03378
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2493685161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.2493685161
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.381922067
Short name T2284
Test name
Test status
Simulation time 151887404 ps
CPU time 0.75 seconds
Started Jun 23 05:18:41 PM PDT 24
Finished Jun 23 05:18:43 PM PDT 24
Peak memory 205884 kb
Host smart-bb6bba2e-5fc4-4f27-9006-d8e8d6ef5f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38192
2067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.381922067
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.4243348806
Short name T110
Test name
Test status
Simulation time 167316627 ps
CPU time 0.84 seconds
Started Jun 23 05:18:44 PM PDT 24
Finished Jun 23 05:18:45 PM PDT 24
Peak memory 206104 kb
Host smart-951897f6-2a4b-4543-9579-0633afd0eaac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42433
48806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.4243348806
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.1288604501
Short name T1078
Test name
Test status
Simulation time 176287244 ps
CPU time 0.81 seconds
Started Jun 23 05:18:40 PM PDT 24
Finished Jun 23 05:18:41 PM PDT 24
Peak memory 206104 kb
Host smart-335d91d1-927c-4f77-b956-6d39cf756bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12886
04501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.1288604501
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.2106619051
Short name T1600
Test name
Test status
Simulation time 185230334 ps
CPU time 0.83 seconds
Started Jun 23 05:18:40 PM PDT 24
Finished Jun 23 05:18:41 PM PDT 24
Peak memory 206104 kb
Host smart-fe3736ca-c493-4146-bdc9-b65fb4d706f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21066
19051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2106619051
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1008592636
Short name T1319
Test name
Test status
Simulation time 186383621 ps
CPU time 0.83 seconds
Started Jun 23 05:18:43 PM PDT 24
Finished Jun 23 05:18:45 PM PDT 24
Peak memory 206088 kb
Host smart-0cb5783d-113c-4ae3-b515-478d9c4e8345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10085
92636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1008592636
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1966910832
Short name T1086
Test name
Test status
Simulation time 153738577 ps
CPU time 0.79 seconds
Started Jun 23 05:18:43 PM PDT 24
Finished Jun 23 05:18:44 PM PDT 24
Peak memory 206104 kb
Host smart-16905f86-40cd-4d32-b21f-aefe10b2b77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19669
10832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1966910832
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.3431449009
Short name T953
Test name
Test status
Simulation time 221505671 ps
CPU time 0.93 seconds
Started Jun 23 05:18:43 PM PDT 24
Finished Jun 23 05:18:44 PM PDT 24
Peak memory 206108 kb
Host smart-f384a15e-d6e8-4879-9828-0d4db55a1e74
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3431449009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.3431449009
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3734629665
Short name T2106
Test name
Test status
Simulation time 139180269 ps
CPU time 0.81 seconds
Started Jun 23 05:18:44 PM PDT 24
Finished Jun 23 05:18:45 PM PDT 24
Peak memory 206012 kb
Host smart-70cc8380-07d8-438c-9a37-49e7aee53901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37346
29665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3734629665
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2175153863
Short name T816
Test name
Test status
Simulation time 59000972 ps
CPU time 0.66 seconds
Started Jun 23 05:18:44 PM PDT 24
Finished Jun 23 05:18:45 PM PDT 24
Peak memory 206112 kb
Host smart-6a98eee8-8715-4dc7-aab4-e22057953abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21751
53863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2175153863
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2255266597
Short name T2288
Test name
Test status
Simulation time 21703811885 ps
CPU time 51.4 seconds
Started Jun 23 05:18:39 PM PDT 24
Finished Jun 23 05:19:31 PM PDT 24
Peak memory 206408 kb
Host smart-f4fd5fa1-d64f-4692-b058-b8c32e991022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22552
66597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2255266597
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2776889682
Short name T1161
Test name
Test status
Simulation time 202780705 ps
CPU time 0.82 seconds
Started Jun 23 05:18:37 PM PDT 24
Finished Jun 23 05:18:38 PM PDT 24
Peak memory 206028 kb
Host smart-9164a7cd-8263-4db4-a68d-9c4eaec42154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27768
89682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2776889682
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.393577405
Short name T499
Test name
Test status
Simulation time 250737621 ps
CPU time 0.9 seconds
Started Jun 23 05:18:38 PM PDT 24
Finished Jun 23 05:18:40 PM PDT 24
Peak memory 206104 kb
Host smart-b6855df9-7c46-4f16-88cb-77e9d636c113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39357
7405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.393577405
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.2248752739
Short name T1383
Test name
Test status
Simulation time 222357813 ps
CPU time 0.9 seconds
Started Jun 23 05:18:45 PM PDT 24
Finished Jun 23 05:18:46 PM PDT 24
Peak memory 206116 kb
Host smart-8224affc-29aa-49e0-b953-eae8be865c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22487
52739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.2248752739
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.1146938688
Short name T1593
Test name
Test status
Simulation time 188715151 ps
CPU time 0.82 seconds
Started Jun 23 05:18:39 PM PDT 24
Finished Jun 23 05:18:40 PM PDT 24
Peak memory 206128 kb
Host smart-e1430ce7-6646-4378-a372-439a6ee1c7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11469
38688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.1146938688
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2335882800
Short name T1518
Test name
Test status
Simulation time 143074309 ps
CPU time 0.8 seconds
Started Jun 23 05:18:45 PM PDT 24
Finished Jun 23 05:18:46 PM PDT 24
Peak memory 206112 kb
Host smart-dbc7dd93-452b-4f19-95d8-7e704890a964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23358
82800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2335882800
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.1732254525
Short name T1023
Test name
Test status
Simulation time 151555076 ps
CPU time 0.83 seconds
Started Jun 23 05:18:43 PM PDT 24
Finished Jun 23 05:18:45 PM PDT 24
Peak memory 206016 kb
Host smart-754ea4f7-7310-4de1-bf2a-5f901ed99803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17322
54525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1732254525
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3922019762
Short name T1754
Test name
Test status
Simulation time 148075489 ps
CPU time 0.77 seconds
Started Jun 23 05:18:42 PM PDT 24
Finished Jun 23 05:18:43 PM PDT 24
Peak memory 206296 kb
Host smart-eaf5fa7b-3579-4503-a039-e4065cc8951b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39220
19762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3922019762
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1196208782
Short name T1858
Test name
Test status
Simulation time 278388531 ps
CPU time 0.95 seconds
Started Jun 23 05:18:31 PM PDT 24
Finished Jun 23 05:18:32 PM PDT 24
Peak memory 206100 kb
Host smart-d1afc6d0-b7a9-4145-b5c4-2a22ceef48f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11962
08782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1196208782
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.1273409704
Short name T1220
Test name
Test status
Simulation time 9192030917 ps
CPU time 263.73 seconds
Started Jun 23 05:18:37 PM PDT 24
Finished Jun 23 05:23:01 PM PDT 24
Peak memory 206268 kb
Host smart-9076ab3c-7ea5-4366-91f8-c7d39439748f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1273409704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.1273409704
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1648696411
Short name T2426
Test name
Test status
Simulation time 224135187 ps
CPU time 0.87 seconds
Started Jun 23 05:18:41 PM PDT 24
Finished Jun 23 05:18:43 PM PDT 24
Peak memory 206068 kb
Host smart-a09caa62-c922-4779-8c5a-6007f3081cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16486
96411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1648696411
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2208796951
Short name T1399
Test name
Test status
Simulation time 235404783 ps
CPU time 0.85 seconds
Started Jun 23 05:18:39 PM PDT 24
Finished Jun 23 05:18:41 PM PDT 24
Peak memory 206100 kb
Host smart-853e5d75-e791-4d0b-af32-0381f14fc96e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22087
96951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2208796951
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.2450275102
Short name T1400
Test name
Test status
Simulation time 5203992557 ps
CPU time 139.43 seconds
Started Jun 23 05:18:40 PM PDT 24
Finished Jun 23 05:21:00 PM PDT 24
Peak memory 206328 kb
Host smart-573ad46c-5d12-41c2-b9d1-6b49ef6cd5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24502
75102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2450275102
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.2064885841
Short name T793
Test name
Test status
Simulation time 4266343736 ps
CPU time 4.49 seconds
Started Jun 23 05:18:43 PM PDT 24
Finished Jun 23 05:18:48 PM PDT 24
Peak memory 206344 kb
Host smart-9341103d-7789-42e2-9530-a27e99a4138a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2064885841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.2064885841
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.1207265927
Short name T1341
Test name
Test status
Simulation time 13313425832 ps
CPU time 12.05 seconds
Started Jun 23 05:18:44 PM PDT 24
Finished Jun 23 05:18:57 PM PDT 24
Peak memory 206164 kb
Host smart-ff273e58-363c-437e-8ccc-f9249981369a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1207265927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.1207265927
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.2450830617
Short name T1039
Test name
Test status
Simulation time 23411189896 ps
CPU time 22.57 seconds
Started Jun 23 05:18:45 PM PDT 24
Finished Jun 23 05:19:08 PM PDT 24
Peak memory 206168 kb
Host smart-bacd7da5-7f1e-454b-bb21-0f7b01a2d4bd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2450830617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.2450830617
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.4283161289
Short name T1295
Test name
Test status
Simulation time 148582543 ps
CPU time 0.83 seconds
Started Jun 23 05:18:42 PM PDT 24
Finished Jun 23 05:18:43 PM PDT 24
Peak memory 206040 kb
Host smart-5798f193-8919-465e-9ccf-277df8a8dd60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42831
61289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.4283161289
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.2160463145
Short name T950
Test name
Test status
Simulation time 148978497 ps
CPU time 0.75 seconds
Started Jun 23 05:18:43 PM PDT 24
Finished Jun 23 05:18:44 PM PDT 24
Peak memory 206096 kb
Host smart-3c0ceb20-b9c4-4f9b-93f6-01fcb4f7bb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21604
63145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.2160463145
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.82934298
Short name T2117
Test name
Test status
Simulation time 440890284 ps
CPU time 1.4 seconds
Started Jun 23 05:18:43 PM PDT 24
Finished Jun 23 05:18:45 PM PDT 24
Peak memory 206028 kb
Host smart-4b224c7e-d464-429a-8503-36867e3b2396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82934
298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.82934298
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2833722246
Short name T175
Test name
Test status
Simulation time 1273585331 ps
CPU time 2.98 seconds
Started Jun 23 05:18:44 PM PDT 24
Finished Jun 23 05:18:48 PM PDT 24
Peak memory 206232 kb
Host smart-fcb10d51-5066-4288-981d-bc5e55a82457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28337
22246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2833722246
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.2804689544
Short name T2096
Test name
Test status
Simulation time 9309754044 ps
CPU time 19.36 seconds
Started Jun 23 05:18:43 PM PDT 24
Finished Jun 23 05:19:04 PM PDT 24
Peak memory 206412 kb
Host smart-31290fa2-6afc-4843-8e03-23f550d77337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28046
89544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2804689544
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.4058398254
Short name T1671
Test name
Test status
Simulation time 438436486 ps
CPU time 1.27 seconds
Started Jun 23 05:18:44 PM PDT 24
Finished Jun 23 05:18:46 PM PDT 24
Peak memory 205880 kb
Host smart-9dacca2e-1ea6-45fc-8e16-a63c6481fb33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40583
98254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.4058398254
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.3422108064
Short name T338
Test name
Test status
Simulation time 145330382 ps
CPU time 0.74 seconds
Started Jun 23 05:18:49 PM PDT 24
Finished Jun 23 05:18:50 PM PDT 24
Peak memory 205996 kb
Host smart-4b2d7cb0-5f47-4733-a4fe-d0aa723ca314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34221
08064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.3422108064
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.1953838332
Short name T1033
Test name
Test status
Simulation time 69692362 ps
CPU time 0.7 seconds
Started Jun 23 05:18:47 PM PDT 24
Finished Jun 23 05:18:49 PM PDT 24
Peak memory 206156 kb
Host smart-54a3f49b-2902-472a-bc0f-247ae2dd9566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19538
38332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.1953838332
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.873215925
Short name T1632
Test name
Test status
Simulation time 852988079 ps
CPU time 2.41 seconds
Started Jun 23 05:18:53 PM PDT 24
Finished Jun 23 05:18:56 PM PDT 24
Peak memory 206276 kb
Host smart-48efb793-1c2e-48c8-93f8-6ba98f3cc6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87321
5925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.873215925
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2724353326
Short name T1527
Test name
Test status
Simulation time 283899658 ps
CPU time 1.35 seconds
Started Jun 23 05:18:50 PM PDT 24
Finished Jun 23 05:18:52 PM PDT 24
Peak memory 206260 kb
Host smart-d83638ca-e8cb-448b-806c-ea15df3c581c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27243
53326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2724353326
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2987856987
Short name T1140
Test name
Test status
Simulation time 263776141 ps
CPU time 0.92 seconds
Started Jun 23 05:18:53 PM PDT 24
Finished Jun 23 05:18:54 PM PDT 24
Peak memory 206108 kb
Host smart-d01d0a20-b93d-44da-af7f-bd7695501104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29878
56987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2987856987
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.3389473082
Short name T1932
Test name
Test status
Simulation time 132178322 ps
CPU time 0.79 seconds
Started Jun 23 05:18:52 PM PDT 24
Finished Jun 23 05:18:54 PM PDT 24
Peak memory 206036 kb
Host smart-379bab96-d8b9-4d3e-b1e2-1ff88cfb7c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33894
73082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.3389473082
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2541661791
Short name T1385
Test name
Test status
Simulation time 237030598 ps
CPU time 0.94 seconds
Started Jun 23 05:18:47 PM PDT 24
Finished Jun 23 05:18:48 PM PDT 24
Peak memory 206068 kb
Host smart-c4f0d4f4-aab2-415f-9559-5d19365d303f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25416
61791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2541661791
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.291301098
Short name T1411
Test name
Test status
Simulation time 248367723 ps
CPU time 0.89 seconds
Started Jun 23 05:18:49 PM PDT 24
Finished Jun 23 05:18:50 PM PDT 24
Peak memory 206104 kb
Host smart-a72bf202-83b5-41a5-9b18-81c5d600d2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29130
1098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.291301098
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.1666767378
Short name T1439
Test name
Test status
Simulation time 23284512972 ps
CPU time 30.33 seconds
Started Jun 23 05:18:48 PM PDT 24
Finished Jun 23 05:19:19 PM PDT 24
Peak memory 206172 kb
Host smart-4d968169-ff54-46e7-89bc-631db43b587f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16667
67378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.1666767378
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2604493309
Short name T1985
Test name
Test status
Simulation time 3275037667 ps
CPU time 4.1 seconds
Started Jun 23 05:18:53 PM PDT 24
Finished Jun 23 05:18:57 PM PDT 24
Peak memory 206112 kb
Host smart-5d3f59ce-83b8-4045-90ad-7250d2e2d18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26044
93309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2604493309
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.3522711215
Short name T2491
Test name
Test status
Simulation time 12644630910 ps
CPU time 118.65 seconds
Started Jun 23 05:18:50 PM PDT 24
Finished Jun 23 05:20:49 PM PDT 24
Peak memory 206136 kb
Host smart-5f8753d9-469b-44c0-9819-d94fde5dbf96
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3522711215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.3522711215
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3114545790
Short name T1192
Test name
Test status
Simulation time 291641618 ps
CPU time 0.96 seconds
Started Jun 23 05:18:57 PM PDT 24
Finished Jun 23 05:18:59 PM PDT 24
Peak memory 206120 kb
Host smart-a9535959-a546-4c52-bd1d-67878532bd44
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3114545790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3114545790
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.806129145
Short name T1749
Test name
Test status
Simulation time 213188436 ps
CPU time 0.91 seconds
Started Jun 23 05:18:50 PM PDT 24
Finished Jun 23 05:18:52 PM PDT 24
Peak memory 206128 kb
Host smart-7c8c6653-5a96-4494-be2d-21e5fa21379b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80612
9145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.806129145
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.3524197036
Short name T1208
Test name
Test status
Simulation time 11723054652 ps
CPU time 118.2 seconds
Started Jun 23 05:18:47 PM PDT 24
Finished Jun 23 05:20:46 PM PDT 24
Peak memory 206260 kb
Host smart-68828522-7e73-45a2-847b-90ba74360155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35241
97036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.3524197036
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.2785954065
Short name T2212
Test name
Test status
Simulation time 6976563201 ps
CPU time 188.54 seconds
Started Jun 23 05:18:47 PM PDT 24
Finished Jun 23 05:21:57 PM PDT 24
Peak memory 206300 kb
Host smart-5c1a6ac9-6198-43df-a159-bf02fa0c7aee
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2785954065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.2785954065
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.4104172945
Short name T2144
Test name
Test status
Simulation time 149147074 ps
CPU time 0.82 seconds
Started Jun 23 05:18:52 PM PDT 24
Finished Jun 23 05:18:53 PM PDT 24
Peak memory 206064 kb
Host smart-5653cc83-7af0-4869-aff6-6aa941668604
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4104172945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.4104172945
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2412710761
Short name T1096
Test name
Test status
Simulation time 159875995 ps
CPU time 0.82 seconds
Started Jun 23 05:18:50 PM PDT 24
Finished Jun 23 05:18:51 PM PDT 24
Peak memory 206100 kb
Host smart-cea2910d-c282-4c9b-8ab6-6f111dc9700a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24127
10761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2412710761
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.3859739267
Short name T1803
Test name
Test status
Simulation time 169805917 ps
CPU time 0.8 seconds
Started Jun 23 05:18:47 PM PDT 24
Finished Jun 23 05:18:48 PM PDT 24
Peak memory 206080 kb
Host smart-0c25340c-6c64-4755-a3fd-62b362d68d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38597
39267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.3859739267
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3492405622
Short name T1437
Test name
Test status
Simulation time 176652528 ps
CPU time 0.85 seconds
Started Jun 23 05:18:47 PM PDT 24
Finished Jun 23 05:18:48 PM PDT 24
Peak memory 206020 kb
Host smart-bc184588-500a-4c6b-a9d0-67b6891c37a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34924
05622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3492405622
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1341559591
Short name T1114
Test name
Test status
Simulation time 161804159 ps
CPU time 0.79 seconds
Started Jun 23 05:18:50 PM PDT 24
Finished Jun 23 05:18:51 PM PDT 24
Peak memory 206092 kb
Host smart-d466c9bf-2181-4644-8378-889cc5380e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13415
59591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1341559591
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3921757797
Short name T623
Test name
Test status
Simulation time 155192223 ps
CPU time 0.79 seconds
Started Jun 23 05:18:51 PM PDT 24
Finished Jun 23 05:18:53 PM PDT 24
Peak memory 206068 kb
Host smart-cb58d5fd-4f7e-4e88-a83f-d1fa1516c551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39217
57797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3921757797
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.667999786
Short name T747
Test name
Test status
Simulation time 179601404 ps
CPU time 0.89 seconds
Started Jun 23 05:18:54 PM PDT 24
Finished Jun 23 05:18:56 PM PDT 24
Peak memory 206144 kb
Host smart-749f6738-2e35-4ea6-9b10-d8e56e2c7c71
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=667999786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.667999786
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1150862797
Short name T2030
Test name
Test status
Simulation time 156680642 ps
CPU time 0.77 seconds
Started Jun 23 05:18:52 PM PDT 24
Finished Jun 23 05:18:54 PM PDT 24
Peak memory 206104 kb
Host smart-597e0d86-3645-4ba9-9dc3-534cb54aab7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11508
62797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1150862797
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.128312627
Short name T683
Test name
Test status
Simulation time 37974169 ps
CPU time 0.65 seconds
Started Jun 23 05:18:57 PM PDT 24
Finished Jun 23 05:18:59 PM PDT 24
Peak memory 206104 kb
Host smart-2a36d2a6-a1f8-4a84-8a02-4ea16e6298b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12831
2627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.128312627
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.106163964
Short name T2178
Test name
Test status
Simulation time 21547972583 ps
CPU time 47.54 seconds
Started Jun 23 05:18:49 PM PDT 24
Finished Jun 23 05:19:37 PM PDT 24
Peak memory 206260 kb
Host smart-e25056e4-e3b1-41a5-a796-f8ad6eddc89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10616
3964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.106163964
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.1640322303
Short name T1190
Test name
Test status
Simulation time 177551785 ps
CPU time 0.81 seconds
Started Jun 23 05:18:52 PM PDT 24
Finished Jun 23 05:18:54 PM PDT 24
Peak memory 206048 kb
Host smart-358b06f5-ef39-4e61-bf5e-6f32fcc7372c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16403
22303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1640322303
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3248615904
Short name T1557
Test name
Test status
Simulation time 206953587 ps
CPU time 0.88 seconds
Started Jun 23 05:18:51 PM PDT 24
Finished Jun 23 05:18:53 PM PDT 24
Peak memory 206048 kb
Host smart-c41b4dcc-2586-4950-903e-c84e992aafa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32486
15904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3248615904
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3674851127
Short name T1153
Test name
Test status
Simulation time 154959913 ps
CPU time 0.78 seconds
Started Jun 23 05:18:58 PM PDT 24
Finished Jun 23 05:19:00 PM PDT 24
Peak memory 206100 kb
Host smart-572af4f4-8020-4b8c-bd51-bdc201e816d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36748
51127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3674851127
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.1865232182
Short name T355
Test name
Test status
Simulation time 179085043 ps
CPU time 0.82 seconds
Started Jun 23 05:18:48 PM PDT 24
Finished Jun 23 05:18:49 PM PDT 24
Peak memory 206124 kb
Host smart-985a5862-1b55-4ad4-925f-8d73c7e4dff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18652
32182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.1865232182
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.963459904
Short name T606
Test name
Test status
Simulation time 149304159 ps
CPU time 0.76 seconds
Started Jun 23 05:18:49 PM PDT 24
Finished Jun 23 05:18:50 PM PDT 24
Peak memory 206104 kb
Host smart-0e08cc53-74a4-4550-9a63-5ca63de7e9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96345
9904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.963459904
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2274966453
Short name T1491
Test name
Test status
Simulation time 148094800 ps
CPU time 0.77 seconds
Started Jun 23 05:18:56 PM PDT 24
Finished Jun 23 05:18:58 PM PDT 24
Peak memory 206088 kb
Host smart-333c8b85-96ed-477d-b074-10139e80cb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22749
66453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2274966453
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1084799082
Short name T1724
Test name
Test status
Simulation time 145367397 ps
CPU time 0.85 seconds
Started Jun 23 05:18:50 PM PDT 24
Finished Jun 23 05:18:52 PM PDT 24
Peak memory 206000 kb
Host smart-b3ff1b62-7953-4e7d-850f-d7d73d575a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10847
99082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1084799082
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1093379603
Short name T1546
Test name
Test status
Simulation time 215313894 ps
CPU time 0.93 seconds
Started Jun 23 05:18:42 PM PDT 24
Finished Jun 23 05:18:43 PM PDT 24
Peak memory 206108 kb
Host smart-7167db3e-b0e5-4543-b66d-0a464f78dfc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10933
79603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1093379603
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.3885533971
Short name T424
Test name
Test status
Simulation time 5213587079 ps
CPU time 45.4 seconds
Started Jun 23 05:18:47 PM PDT 24
Finished Jun 23 05:19:33 PM PDT 24
Peak memory 206396 kb
Host smart-eb10fb4a-fac8-4230-84de-272a521ad71f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3885533971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.3885533971
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1299101405
Short name T1781
Test name
Test status
Simulation time 159736231 ps
CPU time 0.84 seconds
Started Jun 23 05:18:49 PM PDT 24
Finished Jun 23 05:18:50 PM PDT 24
Peak memory 206112 kb
Host smart-4bb067e2-d703-4f39-ac8d-e24e3e181fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12991
01405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1299101405
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.4077266222
Short name T1147
Test name
Test status
Simulation time 151471895 ps
CPU time 0.76 seconds
Started Jun 23 05:18:52 PM PDT 24
Finished Jun 23 05:18:53 PM PDT 24
Peak memory 206044 kb
Host smart-eb9a41c6-b33d-4da4-9c94-3ec3433ec8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40772
66222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.4077266222
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1514525328
Short name T1946
Test name
Test status
Simulation time 11211096555 ps
CPU time 110.5 seconds
Started Jun 23 05:18:51 PM PDT 24
Finished Jun 23 05:20:41 PM PDT 24
Peak memory 206328 kb
Host smart-c2fb2659-a222-4ef0-9422-d30bd6d006d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15145
25328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1514525328
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.4126482593
Short name T1829
Test name
Test status
Simulation time 4071336014 ps
CPU time 5.53 seconds
Started Jun 23 05:15:06 PM PDT 24
Finished Jun 23 05:15:12 PM PDT 24
Peak memory 206128 kb
Host smart-7b58b13e-b3cc-4e8d-9b72-cd7e5cdefc36
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4126482593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.4126482593
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.3267428283
Short name T1947
Test name
Test status
Simulation time 13409118807 ps
CPU time 15.45 seconds
Started Jun 23 05:15:07 PM PDT 24
Finished Jun 23 05:15:23 PM PDT 24
Peak memory 206136 kb
Host smart-0b2ead24-3a5a-4105-8217-a25e3a517f84
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3267428283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.3267428283
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.812141395
Short name T510
Test name
Test status
Simulation time 23351424038 ps
CPU time 22.88 seconds
Started Jun 23 05:15:08 PM PDT 24
Finished Jun 23 05:15:31 PM PDT 24
Peak memory 206372 kb
Host smart-66387bc0-4ac9-40fb-a6d3-a40bcc820c86
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=812141395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.812141395
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.305701846
Short name T1727
Test name
Test status
Simulation time 160880710 ps
CPU time 0.79 seconds
Started Jun 23 05:15:05 PM PDT 24
Finished Jun 23 05:15:06 PM PDT 24
Peak memory 205996 kb
Host smart-55ac5938-1aa0-4719-9654-b1df1a47d177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30570
1846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.305701846
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.1402866342
Short name T53
Test name
Test status
Simulation time 188582936 ps
CPU time 0.84 seconds
Started Jun 23 05:15:06 PM PDT 24
Finished Jun 23 05:15:07 PM PDT 24
Peak memory 206024 kb
Host smart-0bcdfecc-2cf5-4570-8fb4-e429ca635f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14028
66342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.1402866342
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.6745881
Short name T1734
Test name
Test status
Simulation time 138357388 ps
CPU time 0.81 seconds
Started Jun 23 05:15:08 PM PDT 24
Finished Jun 23 05:15:09 PM PDT 24
Peak memory 206096 kb
Host smart-e391c0e5-e4aa-4678-ab0c-e4ecd3c584f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67458
81 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.6745881
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.1157798979
Short name T1886
Test name
Test status
Simulation time 373721097 ps
CPU time 1.37 seconds
Started Jun 23 05:15:11 PM PDT 24
Finished Jun 23 05:15:13 PM PDT 24
Peak memory 206104 kb
Host smart-12b3fd5b-f86f-4695-97e7-9c6759a87be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11577
98979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.1157798979
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_device_address.1326863271
Short name T172
Test name
Test status
Simulation time 15535443706 ps
CPU time 28.34 seconds
Started Jun 23 05:15:10 PM PDT 24
Finished Jun 23 05:15:39 PM PDT 24
Peak memory 206392 kb
Host smart-00b08d73-0921-489a-bd72-192b59322841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13268
63271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.1326863271
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.3407875232
Short name T2298
Test name
Test status
Simulation time 476133753 ps
CPU time 1.45 seconds
Started Jun 23 05:15:11 PM PDT 24
Finished Jun 23 05:15:13 PM PDT 24
Peak memory 206104 kb
Host smart-dacb29a4-049f-494d-a724-9f67635b43a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34078
75232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.3407875232
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.4123561778
Short name T960
Test name
Test status
Simulation time 203665747 ps
CPU time 0.81 seconds
Started Jun 23 05:15:10 PM PDT 24
Finished Jun 23 05:15:11 PM PDT 24
Peak memory 206096 kb
Host smart-ed487840-67b5-4ab4-aa46-16fca6698f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41235
61778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.4123561778
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.229314210
Short name T1571
Test name
Test status
Simulation time 40620087 ps
CPU time 0.68 seconds
Started Jun 23 05:15:11 PM PDT 24
Finished Jun 23 05:15:13 PM PDT 24
Peak memory 206020 kb
Host smart-f8987ed1-51cf-448e-8cec-cb0176239ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22931
4210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.229314210
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.272828426
Short name T478
Test name
Test status
Simulation time 953597708 ps
CPU time 2.06 seconds
Started Jun 23 05:15:12 PM PDT 24
Finished Jun 23 05:15:15 PM PDT 24
Peak memory 206276 kb
Host smart-4d354f4c-efd5-43c7-98f5-a4ca80e9d406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27282
8426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.272828426
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.433185540
Short name T2133
Test name
Test status
Simulation time 272900247 ps
CPU time 1.7 seconds
Started Jun 23 05:15:13 PM PDT 24
Finished Jun 23 05:15:15 PM PDT 24
Peak memory 206340 kb
Host smart-3d86abb2-51b5-4020-a929-16213c5d06e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43318
5540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.433185540
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.2853375109
Short name T2332
Test name
Test status
Simulation time 245497695 ps
CPU time 0.9 seconds
Started Jun 23 05:15:21 PM PDT 24
Finished Jun 23 05:15:22 PM PDT 24
Peak memory 206100 kb
Host smart-18348761-07d4-48e5-8cc2-9fc225d2d945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28533
75109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2853375109
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2832860714
Short name T847
Test name
Test status
Simulation time 136251256 ps
CPU time 0.79 seconds
Started Jun 23 05:15:20 PM PDT 24
Finished Jun 23 05:15:21 PM PDT 24
Peak memory 206100 kb
Host smart-c4ddf930-1e5d-4b82-97c1-6f558929e6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28328
60714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2832860714
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.960870519
Short name T1779
Test name
Test status
Simulation time 295241858 ps
CPU time 1.02 seconds
Started Jun 23 05:15:11 PM PDT 24
Finished Jun 23 05:15:13 PM PDT 24
Peak memory 206096 kb
Host smart-c193f06d-fd5c-4a60-92c5-39d89229aea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96087
0519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.960870519
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.257087495
Short name T1861
Test name
Test status
Simulation time 14718107661 ps
CPU time 107.32 seconds
Started Jun 23 05:15:12 PM PDT 24
Finished Jun 23 05:17:00 PM PDT 24
Peak memory 206436 kb
Host smart-419600bc-282b-4cdb-9306-fe18d60e84ba
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=257087495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.257087495
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.3023387892
Short name T391
Test name
Test status
Simulation time 172177286 ps
CPU time 0.83 seconds
Started Jun 23 05:15:11 PM PDT 24
Finished Jun 23 05:15:12 PM PDT 24
Peak memory 206120 kb
Host smart-771a64d4-c15a-4f97-91e5-af66d107f508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30233
87892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.3023387892
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.4294934894
Short name T1066
Test name
Test status
Simulation time 23319555830 ps
CPU time 27.91 seconds
Started Jun 23 05:15:12 PM PDT 24
Finished Jun 23 05:15:41 PM PDT 24
Peak memory 206156 kb
Host smart-30e381d0-9306-4fb2-b4d3-488c1bd1d257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42949
34894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.4294934894
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.123341807
Short name T1332
Test name
Test status
Simulation time 3319967567 ps
CPU time 4.93 seconds
Started Jun 23 05:15:12 PM PDT 24
Finished Jun 23 05:15:17 PM PDT 24
Peak memory 206160 kb
Host smart-aa05c6da-d27a-4199-b6f4-6d67ad34489d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12334
1807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.123341807
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.367951601
Short name T2357
Test name
Test status
Simulation time 7663406007 ps
CPU time 75.73 seconds
Started Jun 23 05:15:12 PM PDT 24
Finished Jun 23 05:16:28 PM PDT 24
Peak memory 206360 kb
Host smart-34bd066d-36f0-48fc-9d17-2446ff1dbe50
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=367951601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.367951601
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.1561064778
Short name T1113
Test name
Test status
Simulation time 260557906 ps
CPU time 0.89 seconds
Started Jun 23 05:15:21 PM PDT 24
Finished Jun 23 05:15:22 PM PDT 24
Peak memory 206120 kb
Host smart-1acd858a-9688-4316-9f7b-147dac9bf8d3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1561064778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.1561064778
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.747492512
Short name T2151
Test name
Test status
Simulation time 192595656 ps
CPU time 0.88 seconds
Started Jun 23 05:15:12 PM PDT 24
Finished Jun 23 05:15:13 PM PDT 24
Peak memory 206132 kb
Host smart-b312786c-ae0a-46ba-acfe-8633f7d52923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74749
2512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.747492512
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.2070872051
Short name T2185
Test name
Test status
Simulation time 8346015931 ps
CPU time 79.34 seconds
Started Jun 23 05:15:10 PM PDT 24
Finished Jun 23 05:16:30 PM PDT 24
Peak memory 206356 kb
Host smart-c009fcf9-9788-4c08-87fd-d6d29d209d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20708
72051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.2070872051
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3689321536
Short name T1289
Test name
Test status
Simulation time 5581484467 ps
CPU time 54.88 seconds
Started Jun 23 05:15:11 PM PDT 24
Finished Jun 23 05:16:06 PM PDT 24
Peak memory 206344 kb
Host smart-abbfadf4-63b3-4b88-bd72-a155f4d18810
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3689321536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3689321536
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.816973331
Short name T1916
Test name
Test status
Simulation time 193306149 ps
CPU time 0.83 seconds
Started Jun 23 05:15:20 PM PDT 24
Finished Jun 23 05:15:22 PM PDT 24
Peak memory 206052 kb
Host smart-4c6162f4-464d-41e2-801e-d458f3931f45
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=816973331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.816973331
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3461939882
Short name T2247
Test name
Test status
Simulation time 142055645 ps
CPU time 0.82 seconds
Started Jun 23 05:15:12 PM PDT 24
Finished Jun 23 05:15:14 PM PDT 24
Peak memory 206168 kb
Host smart-eeb60713-7217-4b06-8cfc-bd16a24608be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34619
39882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3461939882
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.4294940901
Short name T1099
Test name
Test status
Simulation time 145515899 ps
CPU time 0.77 seconds
Started Jun 23 05:15:12 PM PDT 24
Finished Jun 23 05:15:14 PM PDT 24
Peak memory 206104 kb
Host smart-91b64478-7fbf-4613-b40c-e73cc975b8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42949
40901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.4294940901
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2930274728
Short name T1864
Test name
Test status
Simulation time 161697630 ps
CPU time 0.79 seconds
Started Jun 23 05:15:13 PM PDT 24
Finished Jun 23 05:15:15 PM PDT 24
Peak memory 206108 kb
Host smart-945b1ed0-fc6e-4cde-bece-8055f2eca2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29302
74728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2930274728
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1581453705
Short name T458
Test name
Test status
Simulation time 196372637 ps
CPU time 0.86 seconds
Started Jun 23 05:15:12 PM PDT 24
Finished Jun 23 05:15:14 PM PDT 24
Peak memory 206020 kb
Host smart-61cabc19-9ea9-4be1-8b61-e37d84196312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15814
53705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1581453705
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.4017501866
Short name T2243
Test name
Test status
Simulation time 179036063 ps
CPU time 0.81 seconds
Started Jun 23 05:15:24 PM PDT 24
Finished Jun 23 05:15:25 PM PDT 24
Peak memory 206004 kb
Host smart-34eb58c2-1b63-44ea-813a-1b5fd92e77d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40175
01866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.4017501866
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.678599402
Short name T1121
Test name
Test status
Simulation time 281872113 ps
CPU time 0.98 seconds
Started Jun 23 05:15:15 PM PDT 24
Finished Jun 23 05:15:17 PM PDT 24
Peak memory 206120 kb
Host smart-e1f2998e-124f-46a9-833a-448375fc6984
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=678599402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.678599402
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2070645472
Short name T1672
Test name
Test status
Simulation time 146960403 ps
CPU time 0.76 seconds
Started Jun 23 05:15:22 PM PDT 24
Finished Jun 23 05:15:23 PM PDT 24
Peak memory 206044 kb
Host smart-4d8fe736-2aba-40f2-9b81-cd17fb43f1e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20706
45472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2070645472
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.1796876025
Short name T1134
Test name
Test status
Simulation time 66560064 ps
CPU time 0.7 seconds
Started Jun 23 05:15:20 PM PDT 24
Finished Jun 23 05:15:21 PM PDT 24
Peak memory 206112 kb
Host smart-d81c16af-d602-474c-a7a3-f2d609b47c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17968
76025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.1796876025
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3486396824
Short name T2165
Test name
Test status
Simulation time 16625268405 ps
CPU time 37.23 seconds
Started Jun 23 05:15:13 PM PDT 24
Finished Jun 23 05:15:50 PM PDT 24
Peak memory 206412 kb
Host smart-6edaa11e-75bf-42d2-8412-9a87a0acb836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34863
96824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3486396824
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.778456883
Short name T849
Test name
Test status
Simulation time 182538231 ps
CPU time 0.83 seconds
Started Jun 23 05:15:11 PM PDT 24
Finished Jun 23 05:15:12 PM PDT 24
Peak memory 206080 kb
Host smart-ff672446-7a59-4441-a3ef-a3d1ede9cdac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77845
6883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.778456883
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2316234896
Short name T500
Test name
Test status
Simulation time 165244416 ps
CPU time 0.82 seconds
Started Jun 23 05:15:15 PM PDT 24
Finished Jun 23 05:15:16 PM PDT 24
Peak memory 206124 kb
Host smart-3154cb8f-43ce-40f5-ab81-2550886be6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23162
34896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2316234896
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3701648764
Short name T2367
Test name
Test status
Simulation time 15388415974 ps
CPU time 331.13 seconds
Started Jun 23 05:15:17 PM PDT 24
Finished Jun 23 05:20:49 PM PDT 24
Peak memory 206368 kb
Host smart-4922cc8c-1a2d-471e-87c9-8dcf70d8b05e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3701648764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3701648764
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.3127066842
Short name T903
Test name
Test status
Simulation time 26089173101 ps
CPU time 656.8 seconds
Started Jun 23 05:15:16 PM PDT 24
Finished Jun 23 05:26:13 PM PDT 24
Peak memory 206432 kb
Host smart-23b8ad8c-ae3c-44a6-9dc5-839299458629
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3127066842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3127066842
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.2871613074
Short name T1915
Test name
Test status
Simulation time 254119677 ps
CPU time 0.9 seconds
Started Jun 23 05:15:22 PM PDT 24
Finished Jun 23 05:15:24 PM PDT 24
Peak memory 206028 kb
Host smart-e1f97c03-a820-493b-ae5b-e0bdb644e9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28716
13074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.2871613074
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.3126833863
Short name T916
Test name
Test status
Simulation time 152365385 ps
CPU time 0.84 seconds
Started Jun 23 05:15:22 PM PDT 24
Finished Jun 23 05:15:23 PM PDT 24
Peak memory 206040 kb
Host smart-6b203613-62bc-41a2-852d-52bc353bda3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31268
33863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.3126833863
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1594414476
Short name T77
Test name
Test status
Simulation time 197732532 ps
CPU time 0.83 seconds
Started Jun 23 05:15:21 PM PDT 24
Finished Jun 23 05:15:22 PM PDT 24
Peak memory 206060 kb
Host smart-6efe4644-72d3-438f-a831-53f4d7b0750a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15944
14476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1594414476
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.896938949
Short name T200
Test name
Test status
Simulation time 1174485984 ps
CPU time 1.88 seconds
Started Jun 23 05:15:21 PM PDT 24
Finished Jun 23 05:15:24 PM PDT 24
Peak memory 223928 kb
Host smart-c41b767f-3dc1-4aa2-8b7a-6cc178d6c0e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=896938949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.896938949
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.3457496261
Short name T57
Test name
Test status
Simulation time 378492168 ps
CPU time 1.32 seconds
Started Jun 23 05:15:17 PM PDT 24
Finished Jun 23 05:15:18 PM PDT 24
Peak memory 206140 kb
Host smart-c43c7e31-6190-49de-a577-7b6501f1faa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34574
96261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.3457496261
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.277984289
Short name T640
Test name
Test status
Simulation time 156593384 ps
CPU time 0.81 seconds
Started Jun 23 05:15:22 PM PDT 24
Finished Jun 23 05:15:23 PM PDT 24
Peak memory 206020 kb
Host smart-b7458493-8002-467b-ac2b-a78e17516839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27798
4289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.277984289
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.219368440
Short name T1973
Test name
Test status
Simulation time 150767838 ps
CPU time 0.79 seconds
Started Jun 23 05:15:18 PM PDT 24
Finished Jun 23 05:15:19 PM PDT 24
Peak memory 206116 kb
Host smart-3c80e286-9dc1-4957-ab21-45c907bdce25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21936
8440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.219368440
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.324387497
Short name T634
Test name
Test status
Simulation time 269874658 ps
CPU time 0.97 seconds
Started Jun 23 05:15:06 PM PDT 24
Finished Jun 23 05:15:08 PM PDT 24
Peak memory 206104 kb
Host smart-d4cc9e18-d0f2-425b-beca-7a2521800722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32438
7497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.324387497
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.3252530052
Short name T561
Test name
Test status
Simulation time 11636151707 ps
CPU time 77.76 seconds
Started Jun 23 05:15:17 PM PDT 24
Finished Jun 23 05:16:35 PM PDT 24
Peak memory 206436 kb
Host smart-3324ae5a-c0d0-48f0-92f0-209d36781753
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3252530052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.3252530052
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.697766094
Short name T139
Test name
Test status
Simulation time 212404371 ps
CPU time 0.85 seconds
Started Jun 23 05:15:17 PM PDT 24
Finished Jun 23 05:15:18 PM PDT 24
Peak memory 206096 kb
Host smart-84212a74-9e9e-450a-bda3-e9b825506aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69776
6094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.697766094
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3523762030
Short name T868
Test name
Test status
Simulation time 190917341 ps
CPU time 0.82 seconds
Started Jun 23 05:15:19 PM PDT 24
Finished Jun 23 05:15:20 PM PDT 24
Peak memory 206056 kb
Host smart-3a4a4645-c029-41cd-8f3f-0700d1f44ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35237
62030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3523762030
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.182567719
Short name T1458
Test name
Test status
Simulation time 5917770941 ps
CPU time 56.84 seconds
Started Jun 23 05:15:19 PM PDT 24
Finished Jun 23 05:16:16 PM PDT 24
Peak memory 206372 kb
Host smart-ab83d80e-b630-4ff0-b947-6f9b2b33ec24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18256
7719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.182567719
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.444682724
Short name T1573
Test name
Test status
Simulation time 3915556083 ps
CPU time 4.31 seconds
Started Jun 23 05:18:54 PM PDT 24
Finished Jun 23 05:18:58 PM PDT 24
Peak memory 206088 kb
Host smart-8171b112-21ee-4b86-8104-1514bde1dc89
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=444682724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.444682724
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.3294236289
Short name T1452
Test name
Test status
Simulation time 23472146124 ps
CPU time 24.43 seconds
Started Jun 23 05:18:52 PM PDT 24
Finished Jun 23 05:19:17 PM PDT 24
Peak memory 206356 kb
Host smart-d7d7f09a-db0c-4864-93ad-b9eafdfd3356
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3294236289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.3294236289
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1090219248
Short name T1286
Test name
Test status
Simulation time 155742854 ps
CPU time 0.89 seconds
Started Jun 23 05:18:55 PM PDT 24
Finished Jun 23 05:18:56 PM PDT 24
Peak memory 206024 kb
Host smart-53d2000e-cadb-4c71-bc65-42537539ad20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10902
19248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1090219248
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.1717062964
Short name T604
Test name
Test status
Simulation time 236515061 ps
CPU time 0.9 seconds
Started Jun 23 05:18:53 PM PDT 24
Finished Jun 23 05:18:54 PM PDT 24
Peak memory 206060 kb
Host smart-a0274a9b-938b-44c2-9a37-cf17b471b793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17170
62964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1717062964
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2130156403
Short name T1206
Test name
Test status
Simulation time 162692078 ps
CPU time 0.81 seconds
Started Jun 23 05:18:59 PM PDT 24
Finished Jun 23 05:19:01 PM PDT 24
Peak memory 206112 kb
Host smart-8ee29c28-cdac-4c76-9bc2-7824f5ac3647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21301
56403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2130156403
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.4046913756
Short name T2085
Test name
Test status
Simulation time 1458119182 ps
CPU time 3.18 seconds
Started Jun 23 05:19:00 PM PDT 24
Finished Jun 23 05:19:03 PM PDT 24
Peak memory 206336 kb
Host smart-67c23ce0-d2fc-4fc5-b295-d60782755b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40469
13756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.4046913756
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.1926108219
Short name T1344
Test name
Test status
Simulation time 15783539612 ps
CPU time 28.38 seconds
Started Jun 23 05:19:04 PM PDT 24
Finished Jun 23 05:19:33 PM PDT 24
Peak memory 206336 kb
Host smart-a5f8dec8-134e-471b-85fc-0782e154b639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19261
08219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.1926108219
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.3836349556
Short name T2203
Test name
Test status
Simulation time 410107904 ps
CPU time 1.26 seconds
Started Jun 23 05:19:04 PM PDT 24
Finished Jun 23 05:19:06 PM PDT 24
Peak memory 206100 kb
Host smart-30cf8420-92ce-468f-9c20-8e9faf1a6e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38363
49556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3836349556
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.91310490
Short name T2
Test name
Test status
Simulation time 141253516 ps
CPU time 0.78 seconds
Started Jun 23 05:18:57 PM PDT 24
Finished Jun 23 05:18:58 PM PDT 24
Peak memory 206032 kb
Host smart-756af881-0dce-4a15-85f3-53015cfd9551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91310
490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.91310490
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.4217130150
Short name T844
Test name
Test status
Simulation time 39913236 ps
CPU time 0.68 seconds
Started Jun 23 05:18:59 PM PDT 24
Finished Jun 23 05:19:00 PM PDT 24
Peak memory 205868 kb
Host smart-7302af5d-9fcd-4b71-94b9-f0aaccb47892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42171
30150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.4217130150
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.91941392
Short name T558
Test name
Test status
Simulation time 834044378 ps
CPU time 2.14 seconds
Started Jun 23 05:18:56 PM PDT 24
Finished Jun 23 05:18:59 PM PDT 24
Peak memory 206236 kb
Host smart-d106885d-8111-446f-a478-6156bc685190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91941
392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.91941392
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1302949219
Short name T2020
Test name
Test status
Simulation time 191180851 ps
CPU time 1.87 seconds
Started Jun 23 05:19:00 PM PDT 24
Finished Jun 23 05:19:03 PM PDT 24
Peak memory 206260 kb
Host smart-4bcf3bc0-ff5c-42ce-a11e-1937603494e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13029
49219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1302949219
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.4202030948
Short name T1412
Test name
Test status
Simulation time 181201201 ps
CPU time 0.8 seconds
Started Jun 23 05:19:04 PM PDT 24
Finished Jun 23 05:19:05 PM PDT 24
Peak memory 206056 kb
Host smart-c70284b4-308c-4b33-bba9-1edd1a90a6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42020
30948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.4202030948
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3656790413
Short name T1409
Test name
Test status
Simulation time 143933381 ps
CPU time 0.77 seconds
Started Jun 23 05:19:10 PM PDT 24
Finished Jun 23 05:19:11 PM PDT 24
Peak memory 206088 kb
Host smart-43e3ce1a-4d22-4d3b-8a3c-5a4d25347033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36567
90413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3656790413
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1953498186
Short name T307
Test name
Test status
Simulation time 200733687 ps
CPU time 0.86 seconds
Started Jun 23 05:19:03 PM PDT 24
Finished Jun 23 05:19:05 PM PDT 24
Peak memory 206096 kb
Host smart-20a2e8c0-ac40-44bb-b18a-987babd370c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19534
98186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1953498186
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3527725186
Short name T1660
Test name
Test status
Simulation time 293953194 ps
CPU time 1.02 seconds
Started Jun 23 05:18:57 PM PDT 24
Finished Jun 23 05:18:59 PM PDT 24
Peak memory 206100 kb
Host smart-72c1130d-3ed0-410a-aa20-8458eeb97440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35277
25186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3527725186
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.821997952
Short name T976
Test name
Test status
Simulation time 23350300831 ps
CPU time 21.1 seconds
Started Jun 23 05:19:03 PM PDT 24
Finished Jun 23 05:19:25 PM PDT 24
Peak memory 206164 kb
Host smart-f9684f60-d4ef-4751-9f98-fd7970fbb74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82199
7952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.821997952
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.3839887998
Short name T839
Test name
Test status
Simulation time 3296386776 ps
CPU time 3.88 seconds
Started Jun 23 05:18:57 PM PDT 24
Finished Jun 23 05:19:02 PM PDT 24
Peak memory 206160 kb
Host smart-f2758ee9-cdb5-48c9-b0a0-d12f1172c3a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38398
87998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.3839887998
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.1581165763
Short name T1841
Test name
Test status
Simulation time 9905786829 ps
CPU time 71.8 seconds
Started Jun 23 05:18:56 PM PDT 24
Finished Jun 23 05:20:08 PM PDT 24
Peak memory 206356 kb
Host smart-ed194fc6-f3ec-4fbf-83f2-37fe3bd80b5f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1581165763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.1581165763
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.1423578907
Short name T25
Test name
Test status
Simulation time 342057038 ps
CPU time 1.03 seconds
Started Jun 23 05:19:05 PM PDT 24
Finished Jun 23 05:19:06 PM PDT 24
Peak memory 206096 kb
Host smart-b554ec0f-2666-47cd-897e-b011bdec01f6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1423578907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.1423578907
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2260220778
Short name T1614
Test name
Test status
Simulation time 191017945 ps
CPU time 0.87 seconds
Started Jun 23 05:18:59 PM PDT 24
Finished Jun 23 05:19:00 PM PDT 24
Peak memory 206116 kb
Host smart-f9bf8388-8460-4a4e-a2eb-9edcc8c9c827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22602
20778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2260220778
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.1995303741
Short name T2041
Test name
Test status
Simulation time 10479585013 ps
CPU time 72.94 seconds
Started Jun 23 05:19:03 PM PDT 24
Finished Jun 23 05:20:17 PM PDT 24
Peak memory 206416 kb
Host smart-d35257d5-7b3d-476c-9550-f3c7f5bc67d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19953
03741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.1995303741
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.1299927549
Short name T923
Test name
Test status
Simulation time 5634260913 ps
CPU time 52.35 seconds
Started Jun 23 05:18:58 PM PDT 24
Finished Jun 23 05:19:51 PM PDT 24
Peak memory 206344 kb
Host smart-391b7daf-5bad-4753-a13f-cf1e706f6553
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1299927549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.1299927549
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1713677451
Short name T294
Test name
Test status
Simulation time 190464747 ps
CPU time 0.86 seconds
Started Jun 23 05:19:04 PM PDT 24
Finished Jun 23 05:19:05 PM PDT 24
Peak memory 206096 kb
Host smart-bdc807b8-27db-4690-abba-b0c6b237bf86
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1713677451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1713677451
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1775614867
Short name T1488
Test name
Test status
Simulation time 228416059 ps
CPU time 0.86 seconds
Started Jun 23 05:18:57 PM PDT 24
Finished Jun 23 05:18:58 PM PDT 24
Peak memory 206060 kb
Host smart-25d66a95-2634-4915-9662-4dcf7d1c79b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17756
14867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1775614867
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1189864121
Short name T107
Test name
Test status
Simulation time 197636165 ps
CPU time 0.86 seconds
Started Jun 23 05:18:57 PM PDT 24
Finished Jun 23 05:18:59 PM PDT 24
Peak memory 206108 kb
Host smart-0c1da6ef-b962-4c00-bc59-6c008e1852d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11898
64121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1189864121
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.532792873
Short name T645
Test name
Test status
Simulation time 184058902 ps
CPU time 0.89 seconds
Started Jun 23 05:19:03 PM PDT 24
Finished Jun 23 05:19:05 PM PDT 24
Peak memory 206108 kb
Host smart-87a4240f-e232-440f-bed9-3746857b9b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53279
2873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.532792873
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3574855652
Short name T2416
Test name
Test status
Simulation time 174354504 ps
CPU time 0.75 seconds
Started Jun 23 05:18:59 PM PDT 24
Finished Jun 23 05:19:00 PM PDT 24
Peak memory 205872 kb
Host smart-2154d5f5-97bc-455f-8404-42d1e1451c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35748
55652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3574855652
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3218611161
Short name T628
Test name
Test status
Simulation time 177519946 ps
CPU time 0.81 seconds
Started Jun 23 05:18:58 PM PDT 24
Finished Jun 23 05:18:59 PM PDT 24
Peak memory 206216 kb
Host smart-e9cf0d1e-7c65-480c-a935-962426e7cbde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32186
11161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3218611161
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.1569692101
Short name T1002
Test name
Test status
Simulation time 174661277 ps
CPU time 0.86 seconds
Started Jun 23 05:19:10 PM PDT 24
Finished Jun 23 05:19:11 PM PDT 24
Peak memory 206096 kb
Host smart-1059a48e-94d8-4844-90be-cee85ea19081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15696
92101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1569692101
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.2007831789
Short name T319
Test name
Test status
Simulation time 237104288 ps
CPU time 0.91 seconds
Started Jun 23 05:19:10 PM PDT 24
Finished Jun 23 05:19:11 PM PDT 24
Peak memory 206120 kb
Host smart-faf6ef7f-666b-450f-ba25-8034068cb688
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2007831789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.2007831789
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.934493074
Short name T961
Test name
Test status
Simulation time 146412411 ps
CPU time 0.81 seconds
Started Jun 23 05:19:04 PM PDT 24
Finished Jun 23 05:19:06 PM PDT 24
Peak memory 206032 kb
Host smart-765f6aba-1410-4c92-a0a6-e88446043125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93449
3074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.934493074
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.322715707
Short name T2061
Test name
Test status
Simulation time 11788016507 ps
CPU time 28.06 seconds
Started Jun 23 05:19:06 PM PDT 24
Finished Jun 23 05:19:34 PM PDT 24
Peak memory 206380 kb
Host smart-fe6d3940-d5e0-4937-9a63-e88a989b69d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32271
5707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.322715707
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.3622493443
Short name T581
Test name
Test status
Simulation time 153432268 ps
CPU time 0.78 seconds
Started Jun 23 05:19:06 PM PDT 24
Finished Jun 23 05:19:07 PM PDT 24
Peak memory 206108 kb
Host smart-99be2533-10fa-4851-ac1f-d87594f112d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36224
93443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3622493443
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.945714212
Short name T2147
Test name
Test status
Simulation time 169506623 ps
CPU time 0.85 seconds
Started Jun 23 05:19:04 PM PDT 24
Finished Jun 23 05:19:05 PM PDT 24
Peak memory 206116 kb
Host smart-48819d75-c79f-4965-83f6-d6945ad87fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94571
4212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.945714212
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.1887896279
Short name T2253
Test name
Test status
Simulation time 198517649 ps
CPU time 0.85 seconds
Started Jun 23 05:19:03 PM PDT 24
Finished Jun 23 05:19:04 PM PDT 24
Peak memory 206100 kb
Host smart-b9fdd1de-6405-4e5f-a38e-47770f665923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18878
96279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.1887896279
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.1323496101
Short name T578
Test name
Test status
Simulation time 196121921 ps
CPU time 0.88 seconds
Started Jun 23 05:19:03 PM PDT 24
Finished Jun 23 05:19:04 PM PDT 24
Peak memory 206048 kb
Host smart-e1643da1-f8d3-4b67-af2f-988d1a0b4d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13234
96101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.1323496101
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.2467731564
Short name T1503
Test name
Test status
Simulation time 137743497 ps
CPU time 0.79 seconds
Started Jun 23 05:19:04 PM PDT 24
Finished Jun 23 05:19:05 PM PDT 24
Peak memory 206100 kb
Host smart-bf56b6d9-8943-4441-b039-6609af5a2b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24677
31564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.2467731564
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3401075367
Short name T1960
Test name
Test status
Simulation time 149063219 ps
CPU time 0.82 seconds
Started Jun 23 05:19:05 PM PDT 24
Finished Jun 23 05:19:06 PM PDT 24
Peak memory 206096 kb
Host smart-592b7871-9c87-4aa9-9060-35cb274086eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34010
75367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3401075367
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1569297238
Short name T2409
Test name
Test status
Simulation time 204122010 ps
CPU time 0.82 seconds
Started Jun 23 05:19:01 PM PDT 24
Finished Jun 23 05:19:02 PM PDT 24
Peak memory 206104 kb
Host smart-7c140711-307c-42e3-817f-8640c290eed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15692
97238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1569297238
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3958107494
Short name T541
Test name
Test status
Simulation time 240832861 ps
CPU time 1.03 seconds
Started Jun 23 05:18:58 PM PDT 24
Finished Jun 23 05:18:59 PM PDT 24
Peak memory 206100 kb
Host smart-135546c3-a0e2-418c-94ac-5a61787e2265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39581
07494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3958107494
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.2288888297
Short name T1572
Test name
Test status
Simulation time 4711068196 ps
CPU time 31.98 seconds
Started Jun 23 05:19:06 PM PDT 24
Finished Jun 23 05:19:39 PM PDT 24
Peak memory 206408 kb
Host smart-fae614de-3d5e-4182-bb31-be37d763b5e0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2288888297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.2288888297
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.844239083
Short name T1315
Test name
Test status
Simulation time 191427718 ps
CPU time 0.86 seconds
Started Jun 23 05:19:02 PM PDT 24
Finished Jun 23 05:19:04 PM PDT 24
Peak memory 206276 kb
Host smart-f09b34c2-0e1e-4a13-8107-d1ff56b32897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84423
9083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.844239083
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.2730800475
Short name T2471
Test name
Test status
Simulation time 139696262 ps
CPU time 0.79 seconds
Started Jun 23 05:19:02 PM PDT 24
Finished Jun 23 05:19:04 PM PDT 24
Peak memory 206020 kb
Host smart-c60bbc7a-e1b8-4da9-a5db-3132225a999e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27308
00475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.2730800475
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.1604527866
Short name T1368
Test name
Test status
Simulation time 3963197429 ps
CPU time 34.97 seconds
Started Jun 23 05:19:10 PM PDT 24
Finished Jun 23 05:19:46 PM PDT 24
Peak memory 206328 kb
Host smart-fbfec083-db6a-48d6-8ca4-19ba18b666a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16045
27866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.1604527866
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.1242962822
Short name T1091
Test name
Test status
Simulation time 4294395153 ps
CPU time 6.05 seconds
Started Jun 23 05:19:06 PM PDT 24
Finished Jun 23 05:19:13 PM PDT 24
Peak memory 206348 kb
Host smart-93cb2992-6bc2-47af-98ab-871abb85a3e0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1242962822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.1242962822
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.410586273
Short name T1102
Test name
Test status
Simulation time 13337570059 ps
CPU time 14.72 seconds
Started Jun 23 05:19:02 PM PDT 24
Finished Jun 23 05:19:17 PM PDT 24
Peak memory 206344 kb
Host smart-5e7b915f-4272-4406-9256-75c9e1911b4b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=410586273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.410586273
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.706541905
Short name T1037
Test name
Test status
Simulation time 175572131 ps
CPU time 0.83 seconds
Started Jun 23 05:19:14 PM PDT 24
Finished Jun 23 05:19:16 PM PDT 24
Peak memory 206092 kb
Host smart-5d0cc648-1e56-4171-bec0-64eed2b4f3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70654
1905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.706541905
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.1301738533
Short name T1364
Test name
Test status
Simulation time 223789103 ps
CPU time 0.86 seconds
Started Jun 23 05:19:09 PM PDT 24
Finished Jun 23 05:19:10 PM PDT 24
Peak memory 206112 kb
Host smart-a0297a58-fa06-441a-9333-6ea0d67b11f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13017
38533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.1301738533
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.4226909736
Short name T100
Test name
Test status
Simulation time 425010289 ps
CPU time 1.34 seconds
Started Jun 23 05:19:06 PM PDT 24
Finished Jun 23 05:19:08 PM PDT 24
Peak memory 206120 kb
Host smart-2bf4cd9c-6d17-48e3-acd9-2f2debd4b5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42269
09736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.4226909736
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.454563315
Short name T1819
Test name
Test status
Simulation time 817426622 ps
CPU time 2.09 seconds
Started Jun 23 05:19:13 PM PDT 24
Finished Jun 23 05:19:15 PM PDT 24
Peak memory 206324 kb
Host smart-3cc39336-de6f-47a5-bed2-c67d18cb7f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45456
3315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.454563315
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.1430054693
Short name T554
Test name
Test status
Simulation time 21728016951 ps
CPU time 41.48 seconds
Started Jun 23 05:19:13 PM PDT 24
Finished Jun 23 05:19:55 PM PDT 24
Peak memory 206332 kb
Host smart-8470aee6-5b35-4bdb-b1b3-4fcc002357ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14300
54693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.1430054693
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.182864546
Short name T2392
Test name
Test status
Simulation time 322975348 ps
CPU time 1.12 seconds
Started Jun 23 05:19:08 PM PDT 24
Finished Jun 23 05:19:10 PM PDT 24
Peak memory 206028 kb
Host smart-870db908-d661-4e8b-9ddf-da0d311c5e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18286
4546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.182864546
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.767914419
Short name T2493
Test name
Test status
Simulation time 143891284 ps
CPU time 0.77 seconds
Started Jun 23 05:19:08 PM PDT 24
Finished Jun 23 05:19:10 PM PDT 24
Peak memory 206048 kb
Host smart-cb64a231-3ce8-44eb-aaae-9b9107d68749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76791
4419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.767914419
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1825518845
Short name T515
Test name
Test status
Simulation time 29463344 ps
CPU time 0.66 seconds
Started Jun 23 05:19:08 PM PDT 24
Finished Jun 23 05:19:09 PM PDT 24
Peak memory 206112 kb
Host smart-6f31e9ad-301e-4261-bdd9-e580423aacbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18255
18845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1825518845
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.890201877
Short name T812
Test name
Test status
Simulation time 749213724 ps
CPU time 1.93 seconds
Started Jun 23 05:19:08 PM PDT 24
Finished Jun 23 05:19:10 PM PDT 24
Peak memory 206296 kb
Host smart-3ac8966d-5ce0-4139-966e-ff10e154f010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89020
1877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.890201877
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.582489345
Short name T1122
Test name
Test status
Simulation time 262217902 ps
CPU time 1.42 seconds
Started Jun 23 05:19:09 PM PDT 24
Finished Jun 23 05:19:11 PM PDT 24
Peak memory 206256 kb
Host smart-a1f93b22-f4ce-449e-84c0-d28f48e5ac44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58248
9345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.582489345
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.2880666860
Short name T1271
Test name
Test status
Simulation time 156837640 ps
CPU time 0.8 seconds
Started Jun 23 05:19:14 PM PDT 24
Finished Jun 23 05:19:15 PM PDT 24
Peak memory 206100 kb
Host smart-58390f69-1d05-4a11-9d69-6ee879e51231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28806
66860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2880666860
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2367216497
Short name T2037
Test name
Test status
Simulation time 152560421 ps
CPU time 0.76 seconds
Started Jun 23 05:19:13 PM PDT 24
Finished Jun 23 05:19:14 PM PDT 24
Peak memory 206088 kb
Host smart-b40157ff-58ec-4283-90d0-163a06eade31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23672
16497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2367216497
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3432311574
Short name T1293
Test name
Test status
Simulation time 256045794 ps
CPU time 0.92 seconds
Started Jun 23 05:19:08 PM PDT 24
Finished Jun 23 05:19:10 PM PDT 24
Peak memory 206096 kb
Host smart-6afc4690-5777-452f-84b5-5dbec7c41eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34323
11574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3432311574
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.4153285521
Short name T2100
Test name
Test status
Simulation time 205022936 ps
CPU time 0.86 seconds
Started Jun 23 05:19:09 PM PDT 24
Finished Jun 23 05:19:10 PM PDT 24
Peak memory 206092 kb
Host smart-6674fa40-0881-437e-9046-5254d3d97d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41532
85521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.4153285521
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.3326339747
Short name T893
Test name
Test status
Simulation time 23318495219 ps
CPU time 23.48 seconds
Started Jun 23 05:19:08 PM PDT 24
Finished Jun 23 05:19:32 PM PDT 24
Peak memory 206092 kb
Host smart-26236f95-66fa-4daa-9cb8-eb096c660644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33263
39747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.3326339747
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.73898759
Short name T1397
Test name
Test status
Simulation time 3261536974 ps
CPU time 3.6 seconds
Started Jun 23 05:19:08 PM PDT 24
Finished Jun 23 05:19:12 PM PDT 24
Peak memory 206128 kb
Host smart-1f8df948-b3d6-43ab-b9f5-e78bf655d061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73898
759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.73898759
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.770566779
Short name T1535
Test name
Test status
Simulation time 10066781880 ps
CPU time 92.36 seconds
Started Jun 23 05:19:08 PM PDT 24
Finished Jun 23 05:20:41 PM PDT 24
Peak memory 206336 kb
Host smart-9a1dea54-fd22-4b90-bce8-3205d87ef593
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=770566779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.770566779
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.586308065
Short name T2466
Test name
Test status
Simulation time 270532190 ps
CPU time 0.97 seconds
Started Jun 23 05:19:16 PM PDT 24
Finished Jun 23 05:19:17 PM PDT 24
Peak memory 206128 kb
Host smart-d431695b-4b4d-42af-ba8d-d8b6917353a7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=586308065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.586308065
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.308575529
Short name T867
Test name
Test status
Simulation time 252643884 ps
CPU time 0.98 seconds
Started Jun 23 05:19:11 PM PDT 24
Finished Jun 23 05:19:12 PM PDT 24
Peak memory 205992 kb
Host smart-794c32b2-c02b-433f-9ebd-6a02cc89e7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30857
5529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.308575529
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.1377209925
Short name T343
Test name
Test status
Simulation time 5530620687 ps
CPU time 37.82 seconds
Started Jun 23 05:19:11 PM PDT 24
Finished Jun 23 05:19:49 PM PDT 24
Peak memory 206256 kb
Host smart-1996f801-4623-4d2c-981c-d373fcb2c66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13772
09925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.1377209925
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.2238794733
Short name T1762
Test name
Test status
Simulation time 15193271565 ps
CPU time 151.16 seconds
Started Jun 23 05:19:08 PM PDT 24
Finished Jun 23 05:21:40 PM PDT 24
Peak memory 206320 kb
Host smart-018e381e-98ab-4cc7-9afc-96a50c41a8ba
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2238794733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.2238794733
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.3024147510
Short name T2386
Test name
Test status
Simulation time 163679891 ps
CPU time 0.81 seconds
Started Jun 23 05:19:12 PM PDT 24
Finished Jun 23 05:19:13 PM PDT 24
Peak memory 206048 kb
Host smart-ade95e8e-dee9-44a2-a5f8-b4935cd62ec8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3024147510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.3024147510
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3915809884
Short name T1598
Test name
Test status
Simulation time 160204566 ps
CPU time 0.76 seconds
Started Jun 23 05:19:10 PM PDT 24
Finished Jun 23 05:19:11 PM PDT 24
Peak memory 206016 kb
Host smart-748d7a0b-ce28-4383-a0af-fc37c84ac5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39158
09884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3915809884
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.781158463
Short name T1825
Test name
Test status
Simulation time 194735702 ps
CPU time 0.87 seconds
Started Jun 23 05:19:13 PM PDT 24
Finished Jun 23 05:19:14 PM PDT 24
Peak memory 206020 kb
Host smart-c8c7d231-1204-436c-997b-6c9936f62c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78115
8463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.781158463
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.3916590678
Short name T1870
Test name
Test status
Simulation time 181635951 ps
CPU time 0.86 seconds
Started Jun 23 05:19:11 PM PDT 24
Finished Jun 23 05:19:12 PM PDT 24
Peak memory 206104 kb
Host smart-87050df9-a8da-4df2-a04d-7c0bccd8ff8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39165
90678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.3916590678
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3206992739
Short name T1891
Test name
Test status
Simulation time 220972805 ps
CPU time 0.8 seconds
Started Jun 23 05:19:06 PM PDT 24
Finished Jun 23 05:19:08 PM PDT 24
Peak memory 206104 kb
Host smart-37000fbf-03c6-4d64-af1e-72e4d87c82e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32069
92739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3206992739
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3842861127
Short name T1432
Test name
Test status
Simulation time 174681384 ps
CPU time 0.82 seconds
Started Jun 23 05:19:14 PM PDT 24
Finished Jun 23 05:19:16 PM PDT 24
Peak memory 206108 kb
Host smart-6f40a5e7-212e-4ca3-88b3-d9b01681c992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38428
61127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3842861127
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.3438248145
Short name T1446
Test name
Test status
Simulation time 158663887 ps
CPU time 0.85 seconds
Started Jun 23 05:19:14 PM PDT 24
Finished Jun 23 05:19:15 PM PDT 24
Peak memory 206020 kb
Host smart-78ce50a5-20cc-4a6b-b571-c9f60aa24ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34382
48145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.3438248145
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.3266342999
Short name T767
Test name
Test status
Simulation time 176799886 ps
CPU time 0.85 seconds
Started Jun 23 05:19:15 PM PDT 24
Finished Jun 23 05:19:16 PM PDT 24
Peak memory 206124 kb
Host smart-35d769b5-9806-4970-b7ea-c629e0884c09
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3266342999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3266342999
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.4115178891
Short name T1807
Test name
Test status
Simulation time 172038760 ps
CPU time 0.81 seconds
Started Jun 23 05:19:13 PM PDT 24
Finished Jun 23 05:19:14 PM PDT 24
Peak memory 206104 kb
Host smart-c660117d-adc7-41eb-a006-75dc6fc8ac74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41151
78891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.4115178891
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2298413075
Short name T2477
Test name
Test status
Simulation time 37572695 ps
CPU time 0.69 seconds
Started Jun 23 05:19:13 PM PDT 24
Finished Jun 23 05:19:15 PM PDT 24
Peak memory 206104 kb
Host smart-5e48cf9d-123c-4f19-acb1-1ab60dbd09e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22984
13075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2298413075
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2600580537
Short name T246
Test name
Test status
Simulation time 8356514802 ps
CPU time 19.14 seconds
Started Jun 23 05:19:10 PM PDT 24
Finished Jun 23 05:19:30 PM PDT 24
Peak memory 206292 kb
Host smart-7abdad47-8925-4715-99d9-1e47d6f82f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26005
80537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2600580537
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.627681384
Short name T1429
Test name
Test status
Simulation time 167408504 ps
CPU time 0.85 seconds
Started Jun 23 05:19:09 PM PDT 24
Finished Jun 23 05:19:10 PM PDT 24
Peak memory 206060 kb
Host smart-8e6952ec-1c16-418b-82dd-6792ceb9aaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62768
1384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.627681384
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3785054671
Short name T1981
Test name
Test status
Simulation time 241371103 ps
CPU time 0.86 seconds
Started Jun 23 05:19:14 PM PDT 24
Finished Jun 23 05:19:15 PM PDT 24
Peak memory 206100 kb
Host smart-14b002e3-3bf8-41b9-83c8-ca14dcc9b603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37850
54671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3785054671
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.1872888624
Short name T1366
Test name
Test status
Simulation time 230211092 ps
CPU time 0.91 seconds
Started Jun 23 05:19:12 PM PDT 24
Finished Jun 23 05:19:13 PM PDT 24
Peak memory 206076 kb
Host smart-71b8bc02-9f70-4b26-bdc8-1e2fc5fc229f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18728
88624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.1872888624
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.3387546839
Short name T565
Test name
Test status
Simulation time 170716093 ps
CPU time 0.84 seconds
Started Jun 23 05:19:06 PM PDT 24
Finished Jun 23 05:19:07 PM PDT 24
Peak memory 206120 kb
Host smart-0f3600d0-b923-4d00-9dd8-4eeb3903bbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33875
46839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.3387546839
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3642200059
Short name T2349
Test name
Test status
Simulation time 179441741 ps
CPU time 0.85 seconds
Started Jun 23 05:19:13 PM PDT 24
Finished Jun 23 05:19:15 PM PDT 24
Peak memory 206100 kb
Host smart-8fa93cda-93dc-4b30-ab01-68ecfe5b07b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36422
00059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3642200059
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2762977995
Short name T991
Test name
Test status
Simulation time 173956176 ps
CPU time 0.8 seconds
Started Jun 23 05:19:14 PM PDT 24
Finished Jun 23 05:19:15 PM PDT 24
Peak memory 206104 kb
Host smart-f4d2d30b-fffa-4e04-8669-9c4d5ecb4788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27629
77995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2762977995
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.224310209
Short name T2172
Test name
Test status
Simulation time 176510976 ps
CPU time 0.8 seconds
Started Jun 23 05:19:08 PM PDT 24
Finished Jun 23 05:19:09 PM PDT 24
Peak memory 206040 kb
Host smart-83795ab6-b299-4996-8f74-32b223a91e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22431
0209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.224310209
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1565038584
Short name T1279
Test name
Test status
Simulation time 258898214 ps
CPU time 1.02 seconds
Started Jun 23 05:19:04 PM PDT 24
Finished Jun 23 05:19:05 PM PDT 24
Peak memory 206064 kb
Host smart-3253cae9-49c6-4b61-aab4-49f808fc4579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15650
38584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1565038584
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.3410292785
Short name T1585
Test name
Test status
Simulation time 11361437077 ps
CPU time 311.58 seconds
Started Jun 23 05:19:08 PM PDT 24
Finished Jun 23 05:24:20 PM PDT 24
Peak memory 206276 kb
Host smart-9c021f08-4dbe-449a-a03b-5ea34b907298
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3410292785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.3410292785
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.661734712
Short name T971
Test name
Test status
Simulation time 202096261 ps
CPU time 0.88 seconds
Started Jun 23 05:19:08 PM PDT 24
Finished Jun 23 05:19:09 PM PDT 24
Peak memory 205988 kb
Host smart-c1e1de07-643c-4fc8-91ac-775296221e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66173
4712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.661734712
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.4257029108
Short name T2098
Test name
Test status
Simulation time 195685053 ps
CPU time 0.82 seconds
Started Jun 23 05:19:14 PM PDT 24
Finished Jun 23 05:19:15 PM PDT 24
Peak memory 206092 kb
Host smart-cde36429-6cbc-45a1-9813-25333ba91e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42570
29108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.4257029108
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.800476267
Short name T873
Test name
Test status
Simulation time 4620157844 ps
CPU time 130.27 seconds
Started Jun 23 05:19:12 PM PDT 24
Finished Jun 23 05:21:23 PM PDT 24
Peak memory 206328 kb
Host smart-0226491a-bc10-46f8-86d2-e104be34596e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80047
6267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.800476267
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.3787148752
Short name T2108
Test name
Test status
Simulation time 3991859428 ps
CPU time 5.54 seconds
Started Jun 23 05:19:12 PM PDT 24
Finished Jun 23 05:19:18 PM PDT 24
Peak memory 206436 kb
Host smart-daec48ea-3f2c-4991-8d12-205396f272a1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3787148752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.3787148752
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3011289978
Short name T892
Test name
Test status
Simulation time 13357952583 ps
CPU time 13.5 seconds
Started Jun 23 05:19:15 PM PDT 24
Finished Jun 23 05:19:29 PM PDT 24
Peak memory 206124 kb
Host smart-4c328ac1-85ac-4f9e-b1f0-71b7c0d4dc3f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3011289978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3011289978
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1207426845
Short name T2233
Test name
Test status
Simulation time 23372898834 ps
CPU time 22.24 seconds
Started Jun 23 05:19:14 PM PDT 24
Finished Jun 23 05:19:37 PM PDT 24
Peak memory 206096 kb
Host smart-fa1479c8-e133-43dd-bf08-0d6c37e3ac1b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1207426845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.1207426845
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.2407190664
Short name T1710
Test name
Test status
Simulation time 202290953 ps
CPU time 0.85 seconds
Started Jun 23 05:19:17 PM PDT 24
Finished Jun 23 05:19:18 PM PDT 24
Peak memory 206036 kb
Host smart-f8376063-d9de-4a5d-a43e-dbe038a7f7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24071
90664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2407190664
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.1865190271
Short name T766
Test name
Test status
Simulation time 140495928 ps
CPU time 0.74 seconds
Started Jun 23 05:19:20 PM PDT 24
Finished Jun 23 05:19:21 PM PDT 24
Peak memory 206104 kb
Host smart-aed57e07-0286-4bd2-88ca-a43145da935a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18651
90271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.1865190271
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.376199966
Short name T1588
Test name
Test status
Simulation time 162494571 ps
CPU time 0.76 seconds
Started Jun 23 05:19:19 PM PDT 24
Finished Jun 23 05:19:20 PM PDT 24
Peak memory 206092 kb
Host smart-cad5e51e-b1e3-41ed-a8f1-2c8e4b47d18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37619
9966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.376199966
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.416685003
Short name T1297
Test name
Test status
Simulation time 1136252434 ps
CPU time 2.29 seconds
Started Jun 23 05:19:21 PM PDT 24
Finished Jun 23 05:19:24 PM PDT 24
Peak memory 206344 kb
Host smart-f844a917-2e17-415b-8042-ad14c6ccf8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41668
5003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.416685003
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.2340535017
Short name T2396
Test name
Test status
Simulation time 21808570966 ps
CPU time 40.28 seconds
Started Jun 23 05:19:24 PM PDT 24
Finished Jun 23 05:20:04 PM PDT 24
Peak memory 206336 kb
Host smart-4239b1b8-07d4-4f88-8db8-e99330f79e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23405
35017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.2340535017
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2598762266
Short name T291
Test name
Test status
Simulation time 401445909 ps
CPU time 1.37 seconds
Started Jun 23 05:19:21 PM PDT 24
Finished Jun 23 05:19:23 PM PDT 24
Peak memory 206104 kb
Host smart-1def5b66-a027-4be7-b5bb-60ad1f438f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25987
62266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2598762266
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.380537033
Short name T1260
Test name
Test status
Simulation time 133417110 ps
CPU time 0.79 seconds
Started Jun 23 05:19:19 PM PDT 24
Finished Jun 23 05:19:20 PM PDT 24
Peak memory 206024 kb
Host smart-1d20ee2a-5d57-4a3d-95e2-2cf16ee42537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38053
7033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.380537033
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1040183155
Short name T1712
Test name
Test status
Simulation time 56685282 ps
CPU time 0.67 seconds
Started Jun 23 05:19:20 PM PDT 24
Finished Jun 23 05:19:21 PM PDT 24
Peak memory 206088 kb
Host smart-39374df2-ebc4-4c50-a0e7-493bc3b6f1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10401
83155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1040183155
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.4094071932
Short name T2184
Test name
Test status
Simulation time 923877886 ps
CPU time 2.18 seconds
Started Jun 23 05:19:19 PM PDT 24
Finished Jun 23 05:19:21 PM PDT 24
Peak memory 206508 kb
Host smart-20725f81-7c2a-46f9-8fa8-880c8987b985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40940
71932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.4094071932
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1641806794
Short name T647
Test name
Test status
Simulation time 291254203 ps
CPU time 1.8 seconds
Started Jun 23 05:19:22 PM PDT 24
Finished Jun 23 05:19:25 PM PDT 24
Peak memory 206276 kb
Host smart-b685d72b-4e40-4be1-ac1e-2c6d06d34339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16418
06794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1641806794
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.2036433918
Short name T670
Test name
Test status
Simulation time 180420481 ps
CPU time 0.82 seconds
Started Jun 23 05:19:23 PM PDT 24
Finished Jun 23 05:19:24 PM PDT 24
Peak memory 206160 kb
Host smart-ee8e94a1-172e-419b-93c0-064cdcdd0f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20364
33918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.2036433918
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2231313749
Short name T2296
Test name
Test status
Simulation time 155896725 ps
CPU time 0.77 seconds
Started Jun 23 05:19:23 PM PDT 24
Finished Jun 23 05:19:25 PM PDT 24
Peak memory 206100 kb
Host smart-485124e0-9f3b-406d-9478-bc51e25ceff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22313
13749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2231313749
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1724003938
Short name T1071
Test name
Test status
Simulation time 162299844 ps
CPU time 0.86 seconds
Started Jun 23 05:19:22 PM PDT 24
Finished Jun 23 05:19:23 PM PDT 24
Peak memory 206100 kb
Host smart-f0f57e17-75e8-4918-a338-0e65b3a4340e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17240
03938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1724003938
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.1165545036
Short name T1073
Test name
Test status
Simulation time 7180838471 ps
CPU time 68.6 seconds
Started Jun 23 05:19:19 PM PDT 24
Finished Jun 23 05:20:28 PM PDT 24
Peak memory 206264 kb
Host smart-9c231c7e-4421-48a1-87e8-5b2b44cd0a87
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1165545036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.1165545036
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3592072598
Short name T1020
Test name
Test status
Simulation time 229157502 ps
CPU time 0.88 seconds
Started Jun 23 05:19:21 PM PDT 24
Finished Jun 23 05:19:22 PM PDT 24
Peak memory 206100 kb
Host smart-6d829c17-0655-49f3-85da-61368d49d1ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35920
72598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3592072598
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.788566705
Short name T1753
Test name
Test status
Simulation time 23420559608 ps
CPU time 20.79 seconds
Started Jun 23 05:19:18 PM PDT 24
Finished Jun 23 05:19:39 PM PDT 24
Peak memory 206160 kb
Host smart-a4266222-9e2b-4cb7-8085-7860ef5babe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78856
6705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.788566705
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.1502278790
Short name T1745
Test name
Test status
Simulation time 3338893244 ps
CPU time 3.73 seconds
Started Jun 23 05:19:23 PM PDT 24
Finished Jun 23 05:19:28 PM PDT 24
Peak memory 206084 kb
Host smart-9e3e5ad6-343b-4969-a279-4df3e07184b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15022
78790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1502278790
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.855700208
Short name T1210
Test name
Test status
Simulation time 8448722356 ps
CPU time 76.01 seconds
Started Jun 23 05:19:25 PM PDT 24
Finished Jun 23 05:20:42 PM PDT 24
Peak memory 206340 kb
Host smart-4ceee613-9e4f-4310-9364-81ef2128cf28
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=855700208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.855700208
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.3248981403
Short name T1690
Test name
Test status
Simulation time 255771007 ps
CPU time 0.91 seconds
Started Jun 23 05:19:25 PM PDT 24
Finished Jun 23 05:19:26 PM PDT 24
Peak memory 206060 kb
Host smart-e12d46c2-fc2f-43ab-b90b-327651ab63b1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3248981403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.3248981403
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1856655201
Short name T723
Test name
Test status
Simulation time 201730375 ps
CPU time 0.87 seconds
Started Jun 23 05:19:21 PM PDT 24
Finished Jun 23 05:19:23 PM PDT 24
Peak memory 206040 kb
Host smart-0f767650-7b02-4497-882c-6057fa65d7c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18566
55201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1856655201
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.2445435800
Short name T1363
Test name
Test status
Simulation time 11215980915 ps
CPU time 308.67 seconds
Started Jun 23 05:19:17 PM PDT 24
Finished Jun 23 05:24:26 PM PDT 24
Peak memory 206328 kb
Host smart-0f216ca1-3d6e-4db9-ac45-bfeeff759da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24454
35800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.2445435800
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1536763254
Short name T909
Test name
Test status
Simulation time 8891865127 ps
CPU time 64.85 seconds
Started Jun 23 05:19:21 PM PDT 24
Finished Jun 23 05:20:26 PM PDT 24
Peak memory 206408 kb
Host smart-fe0b2b4c-2814-44fe-98b7-292a128ba8b6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1536763254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1536763254
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.2791631047
Short name T783
Test name
Test status
Simulation time 146918289 ps
CPU time 0.81 seconds
Started Jun 23 05:19:26 PM PDT 24
Finished Jun 23 05:19:27 PM PDT 24
Peak memory 206128 kb
Host smart-6fccd25a-a72d-45a9-9b1b-18db72f9bd21
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2791631047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.2791631047
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.2836290472
Short name T2146
Test name
Test status
Simulation time 171422413 ps
CPU time 0.81 seconds
Started Jun 23 05:19:22 PM PDT 24
Finished Jun 23 05:19:23 PM PDT 24
Peak memory 206112 kb
Host smart-5a00ccbd-90f8-457c-9f96-8cafdf93d327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28362
90472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2836290472
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.4213826522
Short name T1575
Test name
Test status
Simulation time 203871508 ps
CPU time 0.99 seconds
Started Jun 23 05:19:17 PM PDT 24
Finished Jun 23 05:19:18 PM PDT 24
Peak memory 206108 kb
Host smart-17ecda54-f7f2-4e6a-a37f-6ecf87c74dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42138
26522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.4213826522
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.3466725811
Short name T2420
Test name
Test status
Simulation time 168254096 ps
CPU time 0.84 seconds
Started Jun 23 05:19:19 PM PDT 24
Finished Jun 23 05:19:20 PM PDT 24
Peak memory 206104 kb
Host smart-d07b3415-482a-4795-9022-1f91744c407f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34667
25811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3466725811
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2764777308
Short name T1126
Test name
Test status
Simulation time 196888021 ps
CPU time 0.82 seconds
Started Jun 23 05:19:22 PM PDT 24
Finished Jun 23 05:19:23 PM PDT 24
Peak memory 206104 kb
Host smart-f8eb9f1a-0098-4934-b7dc-cb25b4df613a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27647
77308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2764777308
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1722708346
Short name T22
Test name
Test status
Simulation time 170628677 ps
CPU time 0.86 seconds
Started Jun 23 05:19:25 PM PDT 24
Finished Jun 23 05:19:27 PM PDT 24
Peak memory 206120 kb
Host smart-764dcabc-77ae-4b10-9676-a5579a264275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17227
08346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1722708346
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1824963659
Short name T1391
Test name
Test status
Simulation time 165478191 ps
CPU time 0.81 seconds
Started Jun 23 05:19:24 PM PDT 24
Finished Jun 23 05:19:26 PM PDT 24
Peak memory 206104 kb
Host smart-d1314ee8-bc0c-4e4f-94fa-2a6c5335577b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18249
63659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1824963659
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.3878240155
Short name T1785
Test name
Test status
Simulation time 239304330 ps
CPU time 0.99 seconds
Started Jun 23 05:19:25 PM PDT 24
Finished Jun 23 05:19:27 PM PDT 24
Peak memory 206056 kb
Host smart-b17484ca-8d2f-485b-aad3-9420ebd05dfc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3878240155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.3878240155
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.829550393
Short name T846
Test name
Test status
Simulation time 143416276 ps
CPU time 0.71 seconds
Started Jun 23 05:19:25 PM PDT 24
Finished Jun 23 05:19:26 PM PDT 24
Peak memory 206100 kb
Host smart-032319e4-9d8e-4e4a-ac6e-2dbd95efbf9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82955
0393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.829550393
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1716424771
Short name T27
Test name
Test status
Simulation time 41190348 ps
CPU time 0.68 seconds
Started Jun 23 05:19:24 PM PDT 24
Finished Jun 23 05:19:26 PM PDT 24
Peak memory 206112 kb
Host smart-6013e6eb-8cd8-462b-bad1-64853c1b4b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17164
24771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1716424771
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.4189696412
Short name T2111
Test name
Test status
Simulation time 21704821816 ps
CPU time 52.65 seconds
Started Jun 23 05:19:21 PM PDT 24
Finished Jun 23 05:20:14 PM PDT 24
Peak memory 206300 kb
Host smart-abbce6f7-8efa-479f-bc1d-abdb64764cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41896
96412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.4189696412
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2771568603
Short name T1893
Test name
Test status
Simulation time 183406731 ps
CPU time 0.85 seconds
Started Jun 23 05:19:23 PM PDT 24
Finished Jun 23 05:19:24 PM PDT 24
Peak memory 206036 kb
Host smart-9194ec0f-0b9f-42d7-9491-7771469bdb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27715
68603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2771568603
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1376012522
Short name T948
Test name
Test status
Simulation time 189507647 ps
CPU time 0.81 seconds
Started Jun 23 05:19:19 PM PDT 24
Finished Jun 23 05:19:20 PM PDT 24
Peak memory 206108 kb
Host smart-a515441b-fcad-4cd5-b7c7-cb8b0003e99d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13760
12522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1376012522
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.2898642677
Short name T1001
Test name
Test status
Simulation time 185084891 ps
CPU time 0.83 seconds
Started Jun 23 05:19:23 PM PDT 24
Finished Jun 23 05:19:24 PM PDT 24
Peak memory 206108 kb
Host smart-aa935e72-e1a5-4d88-9c93-32cb7f64bb4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28986
42677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2898642677
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.4202347278
Short name T2464
Test name
Test status
Simulation time 211789567 ps
CPU time 0.94 seconds
Started Jun 23 05:19:38 PM PDT 24
Finished Jun 23 05:19:40 PM PDT 24
Peak memory 206124 kb
Host smart-7423a693-777c-4e1f-b4d1-edda973c0d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42023
47278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.4202347278
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1716542805
Short name T1867
Test name
Test status
Simulation time 159541660 ps
CPU time 0.77 seconds
Started Jun 23 05:19:18 PM PDT 24
Finished Jun 23 05:19:20 PM PDT 24
Peak memory 206096 kb
Host smart-79704ab6-38f7-422a-a593-aaf0d96cd727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17165
42805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1716542805
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2708357037
Short name T460
Test name
Test status
Simulation time 160149017 ps
CPU time 0.79 seconds
Started Jun 23 05:19:26 PM PDT 24
Finished Jun 23 05:19:27 PM PDT 24
Peak memory 206112 kb
Host smart-42ada850-07ab-4fa4-8e5b-93d8aff3cd2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27083
57037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2708357037
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1540018672
Short name T2370
Test name
Test status
Simulation time 189953157 ps
CPU time 0.79 seconds
Started Jun 23 05:19:20 PM PDT 24
Finished Jun 23 05:19:22 PM PDT 24
Peak memory 206096 kb
Host smart-f47373ce-71e2-49a4-98e4-ff62916b41dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15400
18672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1540018672
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2566659318
Short name T381
Test name
Test status
Simulation time 202460233 ps
CPU time 0.89 seconds
Started Jun 23 05:19:15 PM PDT 24
Finished Jun 23 05:19:16 PM PDT 24
Peak memory 206108 kb
Host smart-96c1c0cb-3f15-4081-a303-b60d385e1b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25666
59318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2566659318
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.2214291308
Short name T1676
Test name
Test status
Simulation time 8865000445 ps
CPU time 82.34 seconds
Started Jun 23 05:19:25 PM PDT 24
Finished Jun 23 05:20:49 PM PDT 24
Peak memory 206356 kb
Host smart-e62ae990-edeb-4b68-9dc7-6cc25a64459c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2214291308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.2214291308
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.4274625965
Short name T368
Test name
Test status
Simulation time 152594519 ps
CPU time 0.77 seconds
Started Jun 23 05:19:20 PM PDT 24
Finished Jun 23 05:19:21 PM PDT 24
Peak memory 206112 kb
Host smart-b918c1d7-21a9-48e0-85f4-b9e64360fd13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42746
25965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.4274625965
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.829046577
Short name T358
Test name
Test status
Simulation time 168169666 ps
CPU time 0.79 seconds
Started Jun 23 05:19:22 PM PDT 24
Finished Jun 23 05:19:24 PM PDT 24
Peak memory 206024 kb
Host smart-c3df97a3-605d-483f-a815-3fee8c7baea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82904
6577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.829046577
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3442419014
Short name T866
Test name
Test status
Simulation time 7294852199 ps
CPU time 196.61 seconds
Started Jun 23 05:19:25 PM PDT 24
Finished Jun 23 05:22:43 PM PDT 24
Peak memory 206360 kb
Host smart-79e8afc6-f157-415a-8d59-f929a3381834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34424
19014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3442419014
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2697310227
Short name T1543
Test name
Test status
Simulation time 3466031877 ps
CPU time 4.47 seconds
Started Jun 23 05:19:25 PM PDT 24
Finished Jun 23 05:19:30 PM PDT 24
Peak memory 206196 kb
Host smart-d9eb26e5-771a-4f25-874a-cd7e394c8bc5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2697310227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.2697310227
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.636561981
Short name T1934
Test name
Test status
Simulation time 13431999478 ps
CPU time 12.37 seconds
Started Jun 23 05:19:29 PM PDT 24
Finished Jun 23 05:19:42 PM PDT 24
Peak memory 206388 kb
Host smart-410c9388-e9e3-4aac-b3fa-6b8c77edbd7e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=636561981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.636561981
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.2808083376
Short name T2258
Test name
Test status
Simulation time 23511643315 ps
CPU time 23.61 seconds
Started Jun 23 05:19:24 PM PDT 24
Finished Jun 23 05:19:48 PM PDT 24
Peak memory 206276 kb
Host smart-3668cc9d-1353-420f-ba23-50ef0c21ea52
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2808083376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.2808083376
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.4062978461
Short name T1542
Test name
Test status
Simulation time 170241230 ps
CPU time 0.8 seconds
Started Jun 23 05:19:26 PM PDT 24
Finished Jun 23 05:19:27 PM PDT 24
Peak memory 206048 kb
Host smart-f9f8f971-4312-4f58-a0f9-8cde4018c032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40629
78461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.4062978461
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.3417118844
Short name T1562
Test name
Test status
Simulation time 179570354 ps
CPU time 0.85 seconds
Started Jun 23 05:19:25 PM PDT 24
Finished Jun 23 05:19:26 PM PDT 24
Peak memory 206060 kb
Host smart-6c2775b6-ae02-4bcd-83a4-fdec1abfb3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34171
18844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3417118844
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.372054577
Short name T708
Test name
Test status
Simulation time 386975378 ps
CPU time 1.39 seconds
Started Jun 23 05:19:22 PM PDT 24
Finished Jun 23 05:19:24 PM PDT 24
Peak memory 206100 kb
Host smart-3be25099-aa0b-4ab2-9a8c-df0ad65521ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37205
4577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.372054577
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.4113756430
Short name T1265
Test name
Test status
Simulation time 571089935 ps
CPU time 1.63 seconds
Started Jun 23 05:19:24 PM PDT 24
Finished Jun 23 05:19:26 PM PDT 24
Peak memory 206108 kb
Host smart-bd8c2d60-c2b6-49f9-9b90-f233bb2c3837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41137
56430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.4113756430
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.4020349608
Short name T856
Test name
Test status
Simulation time 11588951801 ps
CPU time 21.28 seconds
Started Jun 23 05:19:26 PM PDT 24
Finished Jun 23 05:19:48 PM PDT 24
Peak memory 206320 kb
Host smart-833a7e60-6578-419f-b9c0-46e6da2719c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40203
49608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.4020349608
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.4027036551
Short name T954
Test name
Test status
Simulation time 412802730 ps
CPU time 1.25 seconds
Started Jun 23 05:19:26 PM PDT 24
Finished Jun 23 05:19:28 PM PDT 24
Peak memory 206056 kb
Host smart-453b8ce4-93d4-411f-b466-4208ef6f2543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40270
36551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.4027036551
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.1153532208
Short name T45
Test name
Test status
Simulation time 146168013 ps
CPU time 0.75 seconds
Started Jun 23 05:19:25 PM PDT 24
Finished Jun 23 05:19:27 PM PDT 24
Peak memory 206020 kb
Host smart-73464cb3-e5db-454e-bef9-ae5f08bdd7f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11535
32208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.1153532208
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3330750004
Short name T716
Test name
Test status
Simulation time 35863039 ps
CPU time 0.63 seconds
Started Jun 23 05:19:25 PM PDT 24
Finished Jun 23 05:19:27 PM PDT 24
Peak memory 206088 kb
Host smart-4343518a-c0df-4cbc-8ae9-8768a1df4218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33307
50004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3330750004
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.1447021248
Short name T549
Test name
Test status
Simulation time 914525235 ps
CPU time 2.23 seconds
Started Jun 23 05:19:29 PM PDT 24
Finished Jun 23 05:19:32 PM PDT 24
Peak memory 206252 kb
Host smart-d8f6eead-f890-41d1-ab6e-70745caf4d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14470
21248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.1447021248
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.460296984
Short name T917
Test name
Test status
Simulation time 173014158 ps
CPU time 1.97 seconds
Started Jun 23 05:19:23 PM PDT 24
Finished Jun 23 05:19:26 PM PDT 24
Peak memory 206292 kb
Host smart-3e1d089d-7352-4cdb-a0a5-1d534aa4f911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46029
6984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.460296984
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1817896946
Short name T1589
Test name
Test status
Simulation time 242100442 ps
CPU time 0.9 seconds
Started Jun 23 05:19:33 PM PDT 24
Finished Jun 23 05:19:35 PM PDT 24
Peak memory 206024 kb
Host smart-64a04bd7-5416-4f12-818b-3a492c173fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18178
96946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1817896946
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.492604124
Short name T952
Test name
Test status
Simulation time 143397674 ps
CPU time 0.73 seconds
Started Jun 23 05:19:30 PM PDT 24
Finished Jun 23 05:19:31 PM PDT 24
Peak memory 206096 kb
Host smart-29335ae1-63f9-4547-9729-5a9a91fc7cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49260
4124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.492604124
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.1399178762
Short name T1345
Test name
Test status
Simulation time 248126154 ps
CPU time 0.92 seconds
Started Jun 23 05:19:26 PM PDT 24
Finished Jun 23 05:19:28 PM PDT 24
Peak memory 206104 kb
Host smart-038d1453-770d-478a-82ad-f42afd18d668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13991
78762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1399178762
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.3795603017
Short name T2229
Test name
Test status
Simulation time 15802218241 ps
CPU time 156.08 seconds
Started Jun 23 05:19:23 PM PDT 24
Finished Jun 23 05:22:00 PM PDT 24
Peak memory 206336 kb
Host smart-ca366534-3185-459a-985b-ef10359c3526
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3795603017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3795603017
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.3364936550
Short name T2031
Test name
Test status
Simulation time 275085288 ps
CPU time 0.92 seconds
Started Jun 23 05:19:25 PM PDT 24
Finished Jun 23 05:19:26 PM PDT 24
Peak memory 206072 kb
Host smart-41fda092-87f0-4006-949c-16709e4a80ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33649
36550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.3364936550
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2010423326
Short name T1169
Test name
Test status
Simulation time 23336640800 ps
CPU time 25.04 seconds
Started Jun 23 05:19:25 PM PDT 24
Finished Jun 23 05:19:50 PM PDT 24
Peak memory 206068 kb
Host smart-c71a7fb1-f771-407e-93b1-1c230a7c1e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20104
23326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2010423326
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.1939428222
Short name T778
Test name
Test status
Simulation time 3347967048 ps
CPU time 4.52 seconds
Started Jun 23 05:19:28 PM PDT 24
Finished Jun 23 05:19:33 PM PDT 24
Peak memory 206352 kb
Host smart-5eaaf22e-b44b-402b-bbc2-c288c6a42431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19394
28222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.1939428222
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.2191289813
Short name T1748
Test name
Test status
Simulation time 9157431064 ps
CPU time 70.38 seconds
Started Jun 23 05:19:29 PM PDT 24
Finished Jun 23 05:20:40 PM PDT 24
Peak memory 206336 kb
Host smart-9d35dcb7-105a-4a45-b4a1-fa8fc71545d2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2191289813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.2191289813
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.2248544770
Short name T1675
Test name
Test status
Simulation time 254468877 ps
CPU time 0.99 seconds
Started Jun 23 05:19:36 PM PDT 24
Finished Jun 23 05:19:37 PM PDT 24
Peak memory 206128 kb
Host smart-859047ac-8bc4-4053-9f9e-3d63dc69b4fa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2248544770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.2248544770
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2550962362
Short name T2002
Test name
Test status
Simulation time 189298242 ps
CPU time 0.9 seconds
Started Jun 23 05:19:30 PM PDT 24
Finished Jun 23 05:19:31 PM PDT 24
Peak memory 206052 kb
Host smart-7de87d7a-d1fb-4a01-8648-9b0300461aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25509
62362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2550962362
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.2032590763
Short name T1283
Test name
Test status
Simulation time 3471406230 ps
CPU time 25.48 seconds
Started Jun 23 05:19:31 PM PDT 24
Finished Jun 23 05:19:57 PM PDT 24
Peak memory 206328 kb
Host smart-454f217c-fa04-436f-96db-192cd827c677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20325
90763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.2032590763
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.338645666
Short name T1438
Test name
Test status
Simulation time 7561094210 ps
CPU time 76.92 seconds
Started Jun 23 05:19:29 PM PDT 24
Finished Jun 23 05:20:47 PM PDT 24
Peak memory 206320 kb
Host smart-e51f855a-7bba-400d-935c-e0f1eb7b7d77
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=338645666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.338645666
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.3611584959
Short name T1493
Test name
Test status
Simulation time 157999965 ps
CPU time 0.8 seconds
Started Jun 23 05:19:33 PM PDT 24
Finished Jun 23 05:19:35 PM PDT 24
Peak memory 206068 kb
Host smart-70a5779b-4944-4ffe-9a16-ac7faf4d45f0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3611584959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.3611584959
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.4272342295
Short name T2169
Test name
Test status
Simulation time 164668739 ps
CPU time 0.84 seconds
Started Jun 23 05:19:29 PM PDT 24
Finished Jun 23 05:19:30 PM PDT 24
Peak memory 206112 kb
Host smart-2a9509fc-cee6-492c-926b-4d2519c24c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42723
42295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.4272342295
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2285162717
Short name T111
Test name
Test status
Simulation time 254212230 ps
CPU time 0.88 seconds
Started Jun 23 05:19:28 PM PDT 24
Finished Jun 23 05:19:30 PM PDT 24
Peak memory 206104 kb
Host smart-4d973850-8c25-42d1-be88-8c1a0144f09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22851
62717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2285162717
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.961688090
Short name T931
Test name
Test status
Simulation time 206927348 ps
CPU time 0.9 seconds
Started Jun 23 05:19:34 PM PDT 24
Finished Jun 23 05:19:35 PM PDT 24
Peak memory 206096 kb
Host smart-ec037ce1-a4cf-459c-9003-715b6c52aa83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96168
8090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.961688090
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2589279753
Short name T2142
Test name
Test status
Simulation time 184633142 ps
CPU time 0.81 seconds
Started Jun 23 05:19:33 PM PDT 24
Finished Jun 23 05:19:35 PM PDT 24
Peak memory 206024 kb
Host smart-ad7ae52b-6372-4950-bf28-7656d89c6248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25892
79753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2589279753
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1828621489
Short name T382
Test name
Test status
Simulation time 149842665 ps
CPU time 0.78 seconds
Started Jun 23 05:19:34 PM PDT 24
Finished Jun 23 05:19:35 PM PDT 24
Peak memory 206112 kb
Host smart-97922792-eb07-4666-a09b-5195f554b842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18286
21489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1828621489
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.501106487
Short name T1838
Test name
Test status
Simulation time 154881090 ps
CPU time 0.85 seconds
Started Jun 23 05:19:29 PM PDT 24
Finished Jun 23 05:19:31 PM PDT 24
Peak memory 206288 kb
Host smart-76604c1f-f3ec-422f-9eb6-1c4e1789e015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50110
6487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.501106487
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.3849739496
Short name T776
Test name
Test status
Simulation time 281938501 ps
CPU time 0.99 seconds
Started Jun 23 05:19:30 PM PDT 24
Finished Jun 23 05:19:32 PM PDT 24
Peak memory 206124 kb
Host smart-5d8ece5b-e99b-493b-b4da-6e04e04b35ee
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3849739496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.3849739496
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.495748456
Short name T41
Test name
Test status
Simulation time 212183295 ps
CPU time 0.82 seconds
Started Jun 23 05:19:31 PM PDT 24
Finished Jun 23 05:19:33 PM PDT 24
Peak memory 206096 kb
Host smart-39cbb36c-8fdd-4100-b0fc-cd345cc5237c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49574
8456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.495748456
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.4066908829
Short name T994
Test name
Test status
Simulation time 52096109 ps
CPU time 0.66 seconds
Started Jun 23 05:19:30 PM PDT 24
Finished Jun 23 05:19:31 PM PDT 24
Peak memory 206112 kb
Host smart-2f847f73-5369-4fa9-bd6f-bfce8327ef65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40669
08829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.4066908829
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3870099254
Short name T2389
Test name
Test status
Simulation time 20462178708 ps
CPU time 52.33 seconds
Started Jun 23 05:19:31 PM PDT 24
Finished Jun 23 05:20:24 PM PDT 24
Peak memory 206340 kb
Host smart-fabd8883-3fbe-4e88-82d5-7c5d9e5bcd86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38700
99254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3870099254
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.4192983046
Short name T1616
Test name
Test status
Simulation time 189092877 ps
CPU time 0.82 seconds
Started Jun 23 05:19:28 PM PDT 24
Finished Jun 23 05:19:29 PM PDT 24
Peak memory 206036 kb
Host smart-d3616b7e-8019-40a5-9456-5e48caf02a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41929
83046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.4192983046
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2364219216
Short name T1798
Test name
Test status
Simulation time 182763637 ps
CPU time 0.84 seconds
Started Jun 23 05:19:33 PM PDT 24
Finished Jun 23 05:19:34 PM PDT 24
Peak memory 206104 kb
Host smart-6ccd5e6f-f8aa-454c-8bc1-b9d91c534bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23642
19216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2364219216
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.454201492
Short name T1621
Test name
Test status
Simulation time 157016690 ps
CPU time 0.82 seconds
Started Jun 23 05:19:35 PM PDT 24
Finished Jun 23 05:19:37 PM PDT 24
Peak memory 206104 kb
Host smart-1be5cf14-d45f-4364-8d27-17a0e1d7020d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45420
1492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.454201492
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.4272871049
Short name T397
Test name
Test status
Simulation time 169896867 ps
CPU time 0.81 seconds
Started Jun 23 05:19:33 PM PDT 24
Finished Jun 23 05:19:34 PM PDT 24
Peak memory 206044 kb
Host smart-c5fb7a44-ba4c-4321-8d97-b635a1cc0b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42728
71049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.4272871049
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2214727588
Short name T1802
Test name
Test status
Simulation time 178379594 ps
CPU time 0.81 seconds
Started Jun 23 05:19:30 PM PDT 24
Finished Jun 23 05:19:32 PM PDT 24
Peak memory 206092 kb
Host smart-94e54bc9-020c-4501-b4f2-4b7c1eb1b741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22147
27588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2214727588
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.932092103
Short name T1602
Test name
Test status
Simulation time 147910699 ps
CPU time 0.77 seconds
Started Jun 23 05:19:28 PM PDT 24
Finished Jun 23 05:19:29 PM PDT 24
Peak memory 206100 kb
Host smart-0e8c0815-095a-4bb2-900c-c843172af119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93209
2103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.932092103
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3490970822
Short name T1958
Test name
Test status
Simulation time 158626902 ps
CPU time 0.8 seconds
Started Jun 23 05:19:29 PM PDT 24
Finished Jun 23 05:19:30 PM PDT 24
Peak memory 206036 kb
Host smart-ad3ea475-8610-47eb-a18e-264e6e1e7403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34909
70822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3490970822
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.2062846484
Short name T2479
Test name
Test status
Simulation time 282114096 ps
CPU time 1.03 seconds
Started Jun 23 05:19:24 PM PDT 24
Finished Jun 23 05:19:26 PM PDT 24
Peak memory 206108 kb
Host smart-2b7b827b-0d6d-4af5-adcc-b9499c576523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20628
46484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2062846484
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.1810475129
Short name T1159
Test name
Test status
Simulation time 13020937406 ps
CPU time 368.58 seconds
Started Jun 23 05:19:32 PM PDT 24
Finished Jun 23 05:25:41 PM PDT 24
Peak memory 206340 kb
Host smart-64639a32-27ef-4890-84b5-3454ca00b6ea
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1810475129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.1810475129
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3574833384
Short name T648
Test name
Test status
Simulation time 202515826 ps
CPU time 0.85 seconds
Started Jun 23 05:19:29 PM PDT 24
Finished Jun 23 05:19:30 PM PDT 24
Peak memory 206028 kb
Host smart-9a9cfad3-096a-442a-87b0-302e90d41ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35748
33384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3574833384
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1704255130
Short name T1746
Test name
Test status
Simulation time 174676222 ps
CPU time 0.81 seconds
Started Jun 23 05:19:28 PM PDT 24
Finished Jun 23 05:19:29 PM PDT 24
Peak memory 206076 kb
Host smart-5994e6b1-a3ec-4005-a4bd-6ae30ca3ee48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17042
55130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1704255130
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2522395891
Short name T1715
Test name
Test status
Simulation time 3741276375 ps
CPU time 26.91 seconds
Started Jun 23 05:19:29 PM PDT 24
Finished Jun 23 05:19:57 PM PDT 24
Peak memory 206224 kb
Host smart-a368481d-10cf-4df7-a090-62c0b90e1c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25223
95891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2522395891
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.1157131069
Short name T1472
Test name
Test status
Simulation time 3632280859 ps
CPU time 4.1 seconds
Started Jun 23 05:19:38 PM PDT 24
Finished Jun 23 05:19:43 PM PDT 24
Peak memory 206128 kb
Host smart-b4c8e316-d6b8-4630-938c-70a9baeb0ee4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1157131069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.1157131069
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.334099381
Short name T1561
Test name
Test status
Simulation time 13328196002 ps
CPU time 11.23 seconds
Started Jun 23 05:19:33 PM PDT 24
Finished Jun 23 05:19:45 PM PDT 24
Peak memory 206380 kb
Host smart-5c3c9ad6-f445-47db-86aa-0ec4c9e449c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=334099381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.334099381
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.2732434549
Short name T211
Test name
Test status
Simulation time 23326793521 ps
CPU time 22.54 seconds
Started Jun 23 05:19:39 PM PDT 24
Finished Jun 23 05:20:02 PM PDT 24
Peak memory 206340 kb
Host smart-ddfc47ce-60c3-4f39-a83c-e0fb7a686a9b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2732434549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.2732434549
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.4199510224
Short name T352
Test name
Test status
Simulation time 191749530 ps
CPU time 0.83 seconds
Started Jun 23 05:19:34 PM PDT 24
Finished Jun 23 05:19:35 PM PDT 24
Peak memory 206096 kb
Host smart-4094c85f-acf1-4423-a49f-4deeb051b18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41995
10224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.4199510224
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.1569510542
Short name T522
Test name
Test status
Simulation time 179962312 ps
CPU time 0.81 seconds
Started Jun 23 05:19:35 PM PDT 24
Finished Jun 23 05:19:36 PM PDT 24
Peak memory 206096 kb
Host smart-8ef713e4-baa0-47d4-890b-c4922c9eb692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15695
10542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.1569510542
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1406834146
Short name T2362
Test name
Test status
Simulation time 424604598 ps
CPU time 1.29 seconds
Started Jun 23 05:19:33 PM PDT 24
Finished Jun 23 05:19:35 PM PDT 24
Peak memory 206040 kb
Host smart-00b14ffa-a632-4d88-9b66-84c0153a71d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14068
34146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1406834146
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.2593258950
Short name T492
Test name
Test status
Simulation time 573412460 ps
CPU time 1.42 seconds
Started Jun 23 05:19:41 PM PDT 24
Finished Jun 23 05:19:44 PM PDT 24
Peak memory 206052 kb
Host smart-feb77d3f-8658-4d8f-a7bb-aad5eb085c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25932
58950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.2593258950
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.2907987516
Short name T2385
Test name
Test status
Simulation time 23142649596 ps
CPU time 40.56 seconds
Started Jun 23 05:19:33 PM PDT 24
Finished Jun 23 05:20:15 PM PDT 24
Peak memory 206380 kb
Host smart-7307b64a-1f63-4be2-b89d-112038456789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29079
87516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.2907987516
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.2529243078
Short name T418
Test name
Test status
Simulation time 386905884 ps
CPU time 1.43 seconds
Started Jun 23 05:19:35 PM PDT 24
Finished Jun 23 05:19:37 PM PDT 24
Peak memory 206108 kb
Host smart-042e2082-ed14-4ba4-bbce-91ff7af927c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25292
43078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.2529243078
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3655707337
Short name T2358
Test name
Test status
Simulation time 167506513 ps
CPU time 0.82 seconds
Started Jun 23 05:19:33 PM PDT 24
Finished Jun 23 05:19:35 PM PDT 24
Peak memory 206036 kb
Host smart-2c870d03-a1c0-459e-8e0d-c428f67acdd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36557
07337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3655707337
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.39419595
Short name T1507
Test name
Test status
Simulation time 35303599 ps
CPU time 0.66 seconds
Started Jun 23 05:19:34 PM PDT 24
Finished Jun 23 05:19:35 PM PDT 24
Peak memory 205996 kb
Host smart-5d5034a8-91ee-4a42-b17b-096c8b7cbee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39419
595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.39419595
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.3383813063
Short name T1222
Test name
Test status
Simulation time 844502024 ps
CPU time 2.02 seconds
Started Jun 23 05:19:33 PM PDT 24
Finished Jun 23 05:19:35 PM PDT 24
Peak memory 206360 kb
Host smart-b5b5899f-c5e4-46f0-aee6-96f15927e6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33838
13063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.3383813063
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3940624778
Short name T520
Test name
Test status
Simulation time 247489936 ps
CPU time 1.27 seconds
Started Jun 23 05:19:35 PM PDT 24
Finished Jun 23 05:19:37 PM PDT 24
Peak memory 206344 kb
Host smart-5201d9b2-58a2-463c-bb15-40f6e955ad08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39406
24778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3940624778
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1222076297
Short name T1797
Test name
Test status
Simulation time 175155837 ps
CPU time 0.86 seconds
Started Jun 23 05:19:43 PM PDT 24
Finished Jun 23 05:19:45 PM PDT 24
Peak memory 206248 kb
Host smart-e529697e-ce1e-4d2e-b348-e237bac72621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12220
76297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1222076297
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3505342592
Short name T996
Test name
Test status
Simulation time 151028697 ps
CPU time 0.84 seconds
Started Jun 23 05:19:44 PM PDT 24
Finished Jun 23 05:19:46 PM PDT 24
Peak memory 206100 kb
Host smart-b556fcbf-4f0f-45c7-9834-2befeaa6a640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35053
42592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3505342592
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.4002051186
Short name T760
Test name
Test status
Simulation time 210718022 ps
CPU time 0.84 seconds
Started Jun 23 05:19:42 PM PDT 24
Finished Jun 23 05:19:43 PM PDT 24
Peak memory 206048 kb
Host smart-fdc35d6a-e426-423d-8eb5-f62ade1dbc40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40020
51186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.4002051186
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3711859641
Short name T644
Test name
Test status
Simulation time 250360902 ps
CPU time 0.94 seconds
Started Jun 23 05:19:35 PM PDT 24
Finished Jun 23 05:19:37 PM PDT 24
Peak memory 206092 kb
Host smart-ab7af8c6-75de-404e-a09a-072ac95245e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37118
59641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3711859641
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.3849386455
Short name T1404
Test name
Test status
Simulation time 23288897286 ps
CPU time 21.25 seconds
Started Jun 23 05:19:36 PM PDT 24
Finished Jun 23 05:19:57 PM PDT 24
Peak memory 206160 kb
Host smart-6148272e-b755-4cb6-b547-3f98efe0fb8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38493
86455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.3849386455
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2260039355
Short name T946
Test name
Test status
Simulation time 3270373117 ps
CPU time 3.56 seconds
Started Jun 23 05:19:40 PM PDT 24
Finished Jun 23 05:19:44 PM PDT 24
Peak memory 205940 kb
Host smart-7b43ae5c-3e3c-4492-b63c-8806f6c8321c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22600
39355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2260039355
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.2021650225
Short name T613
Test name
Test status
Simulation time 12278346063 ps
CPU time 342.41 seconds
Started Jun 23 05:19:39 PM PDT 24
Finished Jun 23 05:25:22 PM PDT 24
Peak memory 206352 kb
Host smart-5b282632-4470-4486-a529-05b80d25cfa9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2021650225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.2021650225
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.4073368919
Short name T843
Test name
Test status
Simulation time 243961392 ps
CPU time 1 seconds
Started Jun 23 05:19:45 PM PDT 24
Finished Jun 23 05:19:47 PM PDT 24
Peak memory 206056 kb
Host smart-e2f9df13-37ee-4182-b666-3548eb96b506
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4073368919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.4073368919
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3166293022
Short name T394
Test name
Test status
Simulation time 198081289 ps
CPU time 0.9 seconds
Started Jun 23 05:19:39 PM PDT 24
Finished Jun 23 05:19:41 PM PDT 24
Peak memory 206116 kb
Host smart-7319a521-18b1-40aa-a384-3ace16a60d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31662
93022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3166293022
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.2089933766
Short name T1304
Test name
Test status
Simulation time 6192978396 ps
CPU time 46.53 seconds
Started Jun 23 05:19:37 PM PDT 24
Finished Jun 23 05:20:24 PM PDT 24
Peak memory 206324 kb
Host smart-54ac72b1-da4e-4617-afdb-7778e6376108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20899
33766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.2089933766
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.676749869
Short name T1826
Test name
Test status
Simulation time 6626246970 ps
CPU time 50.27 seconds
Started Jun 23 05:19:41 PM PDT 24
Finished Jun 23 05:20:32 PM PDT 24
Peak memory 206404 kb
Host smart-8b5ea1d5-2b78-44e7-a90b-df698a5e458c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=676749869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.676749869
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3260723052
Short name T937
Test name
Test status
Simulation time 158714045 ps
CPU time 0.88 seconds
Started Jun 23 05:19:49 PM PDT 24
Finished Jun 23 05:19:50 PM PDT 24
Peak memory 206120 kb
Host smart-bac98bd5-1faf-400b-a787-3eb006622f22
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3260723052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3260723052
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.659433285
Short name T576
Test name
Test status
Simulation time 205789655 ps
CPU time 0.88 seconds
Started Jun 23 05:19:38 PM PDT 24
Finished Jun 23 05:19:39 PM PDT 24
Peak memory 206292 kb
Host smart-110c8199-13ae-40f8-9a20-5853f9d1653d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65943
3285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.659433285
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.393347037
Short name T974
Test name
Test status
Simulation time 214425804 ps
CPU time 0.85 seconds
Started Jun 23 05:19:37 PM PDT 24
Finished Jun 23 05:19:38 PM PDT 24
Peak memory 206120 kb
Host smart-0a7a6b24-74a4-43b5-a2bf-c0c4945e2c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39334
7037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.393347037
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.744808723
Short name T1889
Test name
Test status
Simulation time 161896782 ps
CPU time 0.86 seconds
Started Jun 23 05:19:42 PM PDT 24
Finished Jun 23 05:19:44 PM PDT 24
Peak memory 206064 kb
Host smart-42a56f6f-0b80-4ac5-9b83-96d030d2a39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74480
8723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.744808723
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2077155873
Short name T1879
Test name
Test status
Simulation time 163133345 ps
CPU time 0.74 seconds
Started Jun 23 05:19:41 PM PDT 24
Finished Jun 23 05:19:43 PM PDT 24
Peak memory 205872 kb
Host smart-f03852a1-6b54-42db-a354-bd0df5af517f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20771
55873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2077155873
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.431757583
Short name T761
Test name
Test status
Simulation time 147139896 ps
CPU time 0.78 seconds
Started Jun 23 05:19:44 PM PDT 24
Finished Jun 23 05:19:46 PM PDT 24
Peak memory 206092 kb
Host smart-8b684ed4-3b8f-41a0-87a9-7d06c7ac0ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43175
7583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.431757583
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.1846908457
Short name T1373
Test name
Test status
Simulation time 254327051 ps
CPU time 0.97 seconds
Started Jun 23 05:19:39 PM PDT 24
Finished Jun 23 05:19:40 PM PDT 24
Peak memory 206044 kb
Host smart-f7489338-d847-478f-bc94-a2a092015d2d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1846908457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.1846908457
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3086003168
Short name T2158
Test name
Test status
Simulation time 152871656 ps
CPU time 0.8 seconds
Started Jun 23 05:19:38 PM PDT 24
Finished Jun 23 05:19:39 PM PDT 24
Peak memory 206008 kb
Host smart-f7960aaf-e3ca-448a-84af-d87c8a66c1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30860
03168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3086003168
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1340887739
Short name T1211
Test name
Test status
Simulation time 40221138 ps
CPU time 0.66 seconds
Started Jun 23 05:19:48 PM PDT 24
Finished Jun 23 05:19:49 PM PDT 24
Peak memory 206084 kb
Host smart-360b6415-f482-4320-b7f5-e0a2394dedda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13408
87739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1340887739
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2291189087
Short name T1623
Test name
Test status
Simulation time 11043782366 ps
CPU time 26.08 seconds
Started Jun 23 05:19:37 PM PDT 24
Finished Jun 23 05:20:04 PM PDT 24
Peak memory 206336 kb
Host smart-7d9f2d4d-e45c-4613-a6d1-639af6a7ff2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22911
89087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2291189087
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.924561913
Short name T870
Test name
Test status
Simulation time 157421995 ps
CPU time 0.8 seconds
Started Jun 23 05:19:39 PM PDT 24
Finished Jun 23 05:19:40 PM PDT 24
Peak memory 206108 kb
Host smart-30287145-91ad-442e-b248-859986927e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92456
1913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.924561913
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.876173433
Short name T1100
Test name
Test status
Simulation time 161552914 ps
CPU time 0.76 seconds
Started Jun 23 05:19:37 PM PDT 24
Finished Jun 23 05:19:38 PM PDT 24
Peak memory 206100 kb
Host smart-43d91814-0646-4885-b598-3baf3a6d3b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87617
3433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.876173433
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.432410412
Short name T1231
Test name
Test status
Simulation time 212973623 ps
CPU time 0.86 seconds
Started Jun 23 05:19:48 PM PDT 24
Finished Jun 23 05:19:49 PM PDT 24
Peak memory 206096 kb
Host smart-ad9098d7-dc79-4346-b6e7-64e8131eef3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43241
0412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.432410412
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3975601281
Short name T2482
Test name
Test status
Simulation time 192235496 ps
CPU time 0.89 seconds
Started Jun 23 05:19:40 PM PDT 24
Finished Jun 23 05:19:42 PM PDT 24
Peak memory 206144 kb
Host smart-4383ef29-0d4d-4594-86a8-52a83e3f356a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39756
01281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3975601281
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.2798967288
Short name T660
Test name
Test status
Simulation time 195531329 ps
CPU time 0.85 seconds
Started Jun 23 05:19:42 PM PDT 24
Finished Jun 23 05:19:43 PM PDT 24
Peak memory 205872 kb
Host smart-53bb8fd2-1e37-4d60-ae60-c4f944cbd08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27989
67288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.2798967288
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1032833504
Short name T1250
Test name
Test status
Simulation time 173651784 ps
CPU time 0.78 seconds
Started Jun 23 05:19:47 PM PDT 24
Finished Jun 23 05:19:48 PM PDT 24
Peak memory 206096 kb
Host smart-581c86c0-9f2f-4d36-94ee-d53e7a657eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10328
33504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1032833504
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1190242061
Short name T2052
Test name
Test status
Simulation time 145866857 ps
CPU time 0.8 seconds
Started Jun 23 05:19:41 PM PDT 24
Finished Jun 23 05:19:43 PM PDT 24
Peak memory 206120 kb
Host smart-9dafe948-0958-4ffa-b6b3-4947bf1d402b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11902
42061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1190242061
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3596132540
Short name T769
Test name
Test status
Simulation time 236038217 ps
CPU time 0.99 seconds
Started Jun 23 05:19:33 PM PDT 24
Finished Jun 23 05:19:35 PM PDT 24
Peak memory 206064 kb
Host smart-a20c4095-9243-4011-82cd-5767ef27583b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35961
32540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3596132540
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.1442837879
Short name T1047
Test name
Test status
Simulation time 8184179511 ps
CPU time 227.86 seconds
Started Jun 23 05:19:42 PM PDT 24
Finished Jun 23 05:23:31 PM PDT 24
Peak memory 206304 kb
Host smart-72e13efd-f65a-4d7d-a27f-03d1aea33700
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1442837879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.1442837879
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2471149982
Short name T1481
Test name
Test status
Simulation time 147605316 ps
CPU time 0.75 seconds
Started Jun 23 05:19:42 PM PDT 24
Finished Jun 23 05:19:43 PM PDT 24
Peak memory 205884 kb
Host smart-ca7867eb-f7c3-4048-8890-02bde5b9ae32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24711
49982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2471149982
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1536093174
Short name T2306
Test name
Test status
Simulation time 170701719 ps
CPU time 0.76 seconds
Started Jun 23 05:19:36 PM PDT 24
Finished Jun 23 05:19:37 PM PDT 24
Peak memory 206100 kb
Host smart-1d3d780c-dbe9-468d-8793-9974847f18ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15360
93174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1536093174
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.1637140589
Short name T1352
Test name
Test status
Simulation time 6744388615 ps
CPU time 64.69 seconds
Started Jun 23 05:19:37 PM PDT 24
Finished Jun 23 05:20:42 PM PDT 24
Peak memory 206268 kb
Host smart-3eac7b76-abcb-4e1a-bb17-eb51fd627093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16371
40589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.1637140589
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.869202943
Short name T514
Test name
Test status
Simulation time 4229907488 ps
CPU time 5.14 seconds
Started Jun 23 05:19:47 PM PDT 24
Finished Jun 23 05:19:53 PM PDT 24
Peak memory 206192 kb
Host smart-d6ae654a-66f6-475f-b98b-ecf033836476
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=869202943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.869202943
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.839251541
Short name T1244
Test name
Test status
Simulation time 23388681441 ps
CPU time 24.27 seconds
Started Jun 23 05:19:44 PM PDT 24
Finished Jun 23 05:20:10 PM PDT 24
Peak memory 206164 kb
Host smart-ae92bdc0-0099-41c0-b3da-3cf28ffdd298
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=839251541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.839251541
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.767472195
Short name T764
Test name
Test status
Simulation time 160558374 ps
CPU time 0.83 seconds
Started Jun 23 05:19:44 PM PDT 24
Finished Jun 23 05:19:46 PM PDT 24
Peak memory 206056 kb
Host smart-b6cbdb24-4518-4a8e-b6ad-d40d44663c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76747
2195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.767472195
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.1662701371
Short name T997
Test name
Test status
Simulation time 139413899 ps
CPU time 0.76 seconds
Started Jun 23 05:19:44 PM PDT 24
Finished Jun 23 05:19:46 PM PDT 24
Peak memory 206104 kb
Host smart-978e9225-9046-450e-be41-73e8d9466486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16627
01371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.1662701371
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.327877754
Short name T1909
Test name
Test status
Simulation time 188982220 ps
CPU time 0.87 seconds
Started Jun 23 05:19:43 PM PDT 24
Finished Jun 23 05:19:44 PM PDT 24
Peak memory 206028 kb
Host smart-3401ae6b-67d2-4b7c-8d22-9d566b2b45f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32787
7754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.327877754
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.768678754
Short name T159
Test name
Test status
Simulation time 1287730236 ps
CPU time 2.68 seconds
Started Jun 23 05:19:48 PM PDT 24
Finished Jun 23 05:19:51 PM PDT 24
Peak memory 206252 kb
Host smart-7c902778-1649-4932-9bc9-38e71ed83395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76867
8754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.768678754
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.198930434
Short name T1328
Test name
Test status
Simulation time 7200122746 ps
CPU time 14.48 seconds
Started Jun 23 05:19:44 PM PDT 24
Finished Jun 23 05:20:00 PM PDT 24
Peak memory 206300 kb
Host smart-f5dd7bd4-6004-4a07-b65c-f35393c79b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19893
0434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.198930434
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.3737992868
Short name T2435
Test name
Test status
Simulation time 346633245 ps
CPU time 1.11 seconds
Started Jun 23 05:19:44 PM PDT 24
Finished Jun 23 05:19:46 PM PDT 24
Peak memory 206012 kb
Host smart-245982cf-6508-4439-8a97-231ac0f2eafc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37379
92868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.3737992868
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.4108733850
Short name T639
Test name
Test status
Simulation time 144378974 ps
CPU time 0.77 seconds
Started Jun 23 05:19:46 PM PDT 24
Finished Jun 23 05:19:47 PM PDT 24
Peak memory 206100 kb
Host smart-e890f730-361d-4f86-a9fc-48366a6593ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41087
33850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.4108733850
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.2807236065
Short name T574
Test name
Test status
Simulation time 41338158 ps
CPU time 0.67 seconds
Started Jun 23 05:19:43 PM PDT 24
Finished Jun 23 05:19:45 PM PDT 24
Peak memory 205980 kb
Host smart-1488af23-5482-4081-a602-4bbac3b8198a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28072
36065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2807236065
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1753861780
Short name T2187
Test name
Test status
Simulation time 1019195205 ps
CPU time 2.62 seconds
Started Jun 23 05:19:46 PM PDT 24
Finished Jun 23 05:19:50 PM PDT 24
Peak memory 206260 kb
Host smart-ca38fc87-9adc-4b55-96b0-22f9b34ad671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17538
61780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1753861780
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2736471446
Short name T2295
Test name
Test status
Simulation time 202982949 ps
CPU time 2.23 seconds
Started Jun 23 05:19:47 PM PDT 24
Finished Jun 23 05:19:50 PM PDT 24
Peak memory 206228 kb
Host smart-ea4af378-0187-4903-9f7f-2abcf93fb20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27364
71446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2736471446
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1567225400
Short name T1273
Test name
Test status
Simulation time 253406480 ps
CPU time 0.92 seconds
Started Jun 23 05:19:48 PM PDT 24
Finished Jun 23 05:19:50 PM PDT 24
Peak memory 206104 kb
Host smart-336be8c5-4832-4c49-aaa6-ebd758aa3acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15672
25400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1567225400
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1210181238
Short name T1062
Test name
Test status
Simulation time 167107712 ps
CPU time 0.78 seconds
Started Jun 23 05:19:51 PM PDT 24
Finished Jun 23 05:19:52 PM PDT 24
Peak memory 206096 kb
Host smart-00c857d5-3edf-4057-9945-4837aa28a7c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12101
81238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1210181238
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2835264034
Short name T874
Test name
Test status
Simulation time 232073011 ps
CPU time 0.9 seconds
Started Jun 23 05:19:43 PM PDT 24
Finished Jun 23 05:19:45 PM PDT 24
Peak memory 206104 kb
Host smart-ac62c41a-04af-45a6-a214-7ff46ce8165c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28352
64034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2835264034
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.579735394
Short name T2266
Test name
Test status
Simulation time 173280872 ps
CPU time 0.84 seconds
Started Jun 23 05:19:44 PM PDT 24
Finished Jun 23 05:19:47 PM PDT 24
Peak memory 206096 kb
Host smart-78bb97df-4a2b-4b15-a003-1ca4348b7b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57973
5394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.579735394
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.4276039232
Short name T42
Test name
Test status
Simulation time 23286267877 ps
CPU time 25.48 seconds
Started Jun 23 05:19:42 PM PDT 24
Finished Jun 23 05:20:08 PM PDT 24
Peak memory 206080 kb
Host smart-515b91e9-e76d-4e33-9439-3d1de2bd630c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42760
39232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.4276039232
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1668263385
Short name T528
Test name
Test status
Simulation time 3285922764 ps
CPU time 3.84 seconds
Started Jun 23 05:19:44 PM PDT 24
Finished Jun 23 05:19:49 PM PDT 24
Peak memory 206160 kb
Host smart-2565e027-d1d3-484b-be23-a04771764fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16682
63385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1668263385
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.2676305063
Short name T1721
Test name
Test status
Simulation time 6516241316 ps
CPU time 168.73 seconds
Started Jun 23 05:19:44 PM PDT 24
Finished Jun 23 05:22:34 PM PDT 24
Peak memory 206244 kb
Host smart-89ea0067-6be0-48fc-87cc-6c275db7e229
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2676305063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.2676305063
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.2956845162
Short name T2035
Test name
Test status
Simulation time 279031765 ps
CPU time 0.93 seconds
Started Jun 23 05:19:54 PM PDT 24
Finished Jun 23 05:19:55 PM PDT 24
Peak memory 206144 kb
Host smart-6c40e800-a57d-4be0-badd-6740c255c86a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2956845162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.2956845162
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1253768235
Short name T1733
Test name
Test status
Simulation time 187882722 ps
CPU time 0.91 seconds
Started Jun 23 05:19:45 PM PDT 24
Finished Jun 23 05:19:47 PM PDT 24
Peak memory 206132 kb
Host smart-6b46089b-b3e9-4554-88c8-a97f880462e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12537
68235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1253768235
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2054212601
Short name T618
Test name
Test status
Simulation time 4892043069 ps
CPU time 142.41 seconds
Started Jun 23 05:19:45 PM PDT 24
Finished Jun 23 05:22:09 PM PDT 24
Peak memory 206380 kb
Host smart-3c466d44-b742-47db-845c-41cc99163e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20542
12601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2054212601
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.2628938202
Short name T706
Test name
Test status
Simulation time 11217787459 ps
CPU time 318.04 seconds
Started Jun 23 05:19:45 PM PDT 24
Finished Jun 23 05:25:05 PM PDT 24
Peak memory 206352 kb
Host smart-c1b14bb1-0fa5-4e4d-8aaa-ef0c72f5b303
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2628938202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.2628938202
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.1001341338
Short name T396
Test name
Test status
Simulation time 168884327 ps
CPU time 0.77 seconds
Started Jun 23 05:19:53 PM PDT 24
Finished Jun 23 05:19:55 PM PDT 24
Peak memory 206120 kb
Host smart-25c1f28b-dad8-4491-83c2-1e1e715c5734
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1001341338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.1001341338
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1789683036
Short name T1441
Test name
Test status
Simulation time 171549413 ps
CPU time 0.8 seconds
Started Jun 23 05:19:46 PM PDT 24
Finished Jun 23 05:19:48 PM PDT 24
Peak memory 206100 kb
Host smart-6d943471-15ed-422d-aacd-f71a98be414d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17896
83036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1789683036
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1164391532
Short name T118
Test name
Test status
Simulation time 234807359 ps
CPU time 0.99 seconds
Started Jun 23 05:19:50 PM PDT 24
Finished Jun 23 05:19:52 PM PDT 24
Peak memory 206096 kb
Host smart-49cd541a-bfca-4a57-a6b8-4bba69ef52d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11643
91532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1164391532
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.3560139698
Short name T550
Test name
Test status
Simulation time 228454813 ps
CPU time 0.87 seconds
Started Jun 23 05:19:51 PM PDT 24
Finished Jun 23 05:19:52 PM PDT 24
Peak memory 206020 kb
Host smart-1b15df95-e51f-4c4d-b305-62fe5993f233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35601
39698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.3560139698
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2788933903
Short name T1738
Test name
Test status
Simulation time 194659590 ps
CPU time 0.83 seconds
Started Jun 23 05:19:49 PM PDT 24
Finished Jun 23 05:19:51 PM PDT 24
Peak memory 206096 kb
Host smart-be8f208a-3046-472d-96e9-f4e355962e33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27889
33903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2788933903
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3582643540
Short name T2431
Test name
Test status
Simulation time 185362983 ps
CPU time 0.83 seconds
Started Jun 23 05:19:54 PM PDT 24
Finished Jun 23 05:19:55 PM PDT 24
Peak memory 206112 kb
Host smart-38187a0a-56ee-48b7-ae56-69771bffabc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35826
43540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3582643540
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2091238741
Short name T1281
Test name
Test status
Simulation time 147857003 ps
CPU time 0.77 seconds
Started Jun 23 05:19:49 PM PDT 24
Finished Jun 23 05:19:51 PM PDT 24
Peak memory 206100 kb
Host smart-9f720e54-73c0-489f-878e-07643a7121d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20912
38741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2091238741
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2993065619
Short name T491
Test name
Test status
Simulation time 242630587 ps
CPU time 0.89 seconds
Started Jun 23 05:19:48 PM PDT 24
Finished Jun 23 05:19:50 PM PDT 24
Peak memory 206116 kb
Host smart-1f2b4640-b673-4580-898d-e57e6e42b23b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2993065619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2993065619
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3996022180
Short name T2390
Test name
Test status
Simulation time 149124385 ps
CPU time 0.77 seconds
Started Jun 23 05:19:49 PM PDT 24
Finished Jun 23 05:19:51 PM PDT 24
Peak memory 206108 kb
Host smart-331f10ec-b4da-4c1a-80b0-92dee1d13dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39960
22180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3996022180
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.3163259950
Short name T34
Test name
Test status
Simulation time 36578796 ps
CPU time 0.69 seconds
Started Jun 23 05:19:47 PM PDT 24
Finished Jun 23 05:19:49 PM PDT 24
Peak memory 206068 kb
Host smart-817dc556-461e-4bcd-884d-97e26c085616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31632
59950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.3163259950
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.467523409
Short name T1592
Test name
Test status
Simulation time 5815652464 ps
CPU time 13 seconds
Started Jun 23 05:19:53 PM PDT 24
Finished Jun 23 05:20:07 PM PDT 24
Peak memory 206424 kb
Host smart-0423ef0d-d8b8-4749-9145-8046adeffb31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46752
3409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.467523409
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.4214639901
Short name T333
Test name
Test status
Simulation time 180331773 ps
CPU time 0.82 seconds
Started Jun 23 05:19:48 PM PDT 24
Finished Jun 23 05:19:50 PM PDT 24
Peak memory 206028 kb
Host smart-6f344f00-ccb9-4706-a727-088c03fb38ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42146
39901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.4214639901
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3621974492
Short name T1664
Test name
Test status
Simulation time 206004171 ps
CPU time 0.92 seconds
Started Jun 23 05:19:48 PM PDT 24
Finished Jun 23 05:19:50 PM PDT 24
Peak memory 206100 kb
Host smart-59c1319c-304e-45a4-bcb0-d1fb74ff4d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36219
74492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3621974492
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3386140983
Short name T1703
Test name
Test status
Simulation time 235900430 ps
CPU time 0.9 seconds
Started Jun 23 05:19:47 PM PDT 24
Finished Jun 23 05:19:48 PM PDT 24
Peak memory 205992 kb
Host smart-d55e88e7-ed43-4a64-9241-b7219247d6fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33861
40983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3386140983
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.4168756264
Short name T790
Test name
Test status
Simulation time 173652744 ps
CPU time 0.81 seconds
Started Jun 23 05:19:50 PM PDT 24
Finished Jun 23 05:19:52 PM PDT 24
Peak memory 206140 kb
Host smart-1a4b874a-f5ea-4f0d-85ea-a01a750a2090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41687
56264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.4168756264
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1813934261
Short name T785
Test name
Test status
Simulation time 181460179 ps
CPU time 0.79 seconds
Started Jun 23 05:19:50 PM PDT 24
Finished Jun 23 05:19:51 PM PDT 24
Peak memory 206096 kb
Host smart-72a82324-4a70-4a51-a352-6c04b4eb5d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18139
34261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1813934261
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1817852912
Short name T1791
Test name
Test status
Simulation time 187562044 ps
CPU time 0.8 seconds
Started Jun 23 05:19:51 PM PDT 24
Finished Jun 23 05:19:52 PM PDT 24
Peak memory 206104 kb
Host smart-39d9b5a9-00a8-4c71-aafd-85df6ec3bbef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18178
52912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1817852912
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1232736842
Short name T878
Test name
Test status
Simulation time 155460582 ps
CPU time 0.78 seconds
Started Jun 23 05:19:47 PM PDT 24
Finished Jun 23 05:19:48 PM PDT 24
Peak memory 206056 kb
Host smart-9c39df2b-917e-4fce-bc89-767904542a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12327
36842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1232736842
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.876662261
Short name T1995
Test name
Test status
Simulation time 234852189 ps
CPU time 0.85 seconds
Started Jun 23 05:19:42 PM PDT 24
Finished Jun 23 05:19:43 PM PDT 24
Peak memory 206108 kb
Host smart-27fd4a84-191f-45f7-9e1a-0537ec28ddcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87666
2261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.876662261
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.3681713845
Short name T2155
Test name
Test status
Simulation time 8069742784 ps
CPU time 61.01 seconds
Started Jun 23 05:19:49 PM PDT 24
Finished Jun 23 05:20:51 PM PDT 24
Peak memory 206356 kb
Host smart-9331c713-05f5-483f-b65e-701a0b2e64a1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3681713845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.3681713845
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.2310376333
Short name T2182
Test name
Test status
Simulation time 198115969 ps
CPU time 0.85 seconds
Started Jun 23 05:19:49 PM PDT 24
Finished Jun 23 05:19:50 PM PDT 24
Peak memory 206068 kb
Host smart-867f8c3f-2eb5-46ab-a351-03bef08d47d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23103
76333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.2310376333
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3379931388
Short name T1369
Test name
Test status
Simulation time 161284246 ps
CPU time 0.77 seconds
Started Jun 23 05:19:51 PM PDT 24
Finished Jun 23 05:19:52 PM PDT 24
Peak memory 206088 kb
Host smart-659d5c5d-afb7-4eea-9900-18bb790d0c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33799
31388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3379931388
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.3037900333
Short name T420
Test name
Test status
Simulation time 5684963290 ps
CPU time 41.4 seconds
Started Jun 23 05:19:49 PM PDT 24
Finished Jun 23 05:20:31 PM PDT 24
Peak memory 206288 kb
Host smart-80a74371-4d61-404a-9318-504a9f5ae166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30379
00333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.3037900333
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.229451302
Short name T1417
Test name
Test status
Simulation time 3382527861 ps
CPU time 3.99 seconds
Started Jun 23 05:19:54 PM PDT 24
Finished Jun 23 05:19:58 PM PDT 24
Peak memory 206184 kb
Host smart-2c8cdd59-2ea6-413f-bad8-7e270e0a1b44
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=229451302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.229451302
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.1293726302
Short name T2004
Test name
Test status
Simulation time 13389226637 ps
CPU time 12.52 seconds
Started Jun 23 05:19:57 PM PDT 24
Finished Jun 23 05:20:10 PM PDT 24
Peak memory 206136 kb
Host smart-95f5a4da-09f6-4cf8-b5a7-2e670653b5bd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1293726302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.1293726302
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.95844636
Short name T2395
Test name
Test status
Simulation time 23493415330 ps
CPU time 28.23 seconds
Started Jun 23 05:19:57 PM PDT 24
Finished Jun 23 05:20:26 PM PDT 24
Peak memory 206412 kb
Host smart-495c25ba-ac82-4f82-bf2f-adf4e076bbd6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=95844636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.95844636
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1367917745
Short name T1792
Test name
Test status
Simulation time 165761393 ps
CPU time 0.84 seconds
Started Jun 23 05:19:53 PM PDT 24
Finished Jun 23 05:19:55 PM PDT 24
Peak memory 206024 kb
Host smart-78c07dfc-70a3-4fca-870c-85ff7c712514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13679
17745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1367917745
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1513068777
Short name T1663
Test name
Test status
Simulation time 162453928 ps
CPU time 0.78 seconds
Started Jun 23 05:19:53 PM PDT 24
Finished Jun 23 05:19:54 PM PDT 24
Peak memory 206096 kb
Host smart-f39cca56-332a-4955-a9cb-5b149a419e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15130
68777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1513068777
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.731829790
Short name T99
Test name
Test status
Simulation time 269849587 ps
CPU time 1.03 seconds
Started Jun 23 05:19:55 PM PDT 24
Finished Jun 23 05:19:56 PM PDT 24
Peak memory 206124 kb
Host smart-3a135553-6ead-4158-8016-099b155f116f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73182
9790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.731829790
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.317460792
Short name T804
Test name
Test status
Simulation time 456973362 ps
CPU time 1.3 seconds
Started Jun 23 05:19:55 PM PDT 24
Finished Jun 23 05:19:56 PM PDT 24
Peak memory 206028 kb
Host smart-a6f362a1-00eb-4d22-8f36-7766e670a83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31746
0792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.317460792
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.3568248419
Short name T1836
Test name
Test status
Simulation time 464132420 ps
CPU time 1.39 seconds
Started Jun 23 05:19:54 PM PDT 24
Finished Jun 23 05:19:56 PM PDT 24
Peak memory 206108 kb
Host smart-8fcdcad9-d26e-4d12-8d39-717c90703536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35682
48419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.3568248419
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.3208663812
Short name T2237
Test name
Test status
Simulation time 135130984 ps
CPU time 0.7 seconds
Started Jun 23 05:19:54 PM PDT 24
Finished Jun 23 05:19:55 PM PDT 24
Peak memory 206100 kb
Host smart-00d4961b-1119-4bec-b7e9-c02fd29383f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32086
63812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.3208663812
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.814034194
Short name T221
Test name
Test status
Simulation time 51931726 ps
CPU time 0.68 seconds
Started Jun 23 05:19:54 PM PDT 24
Finished Jun 23 05:19:55 PM PDT 24
Peak memory 206092 kb
Host smart-196df519-5894-4a56-bb71-b6a680d9a33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81403
4194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.814034194
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2292720296
Short name T357
Test name
Test status
Simulation time 994568497 ps
CPU time 2.45 seconds
Started Jun 23 05:19:57 PM PDT 24
Finished Jun 23 05:20:00 PM PDT 24
Peak memory 206212 kb
Host smart-406822b8-752c-43fd-908a-cdfc473793c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22927
20296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2292720296
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.538008335
Short name T2319
Test name
Test status
Simulation time 287051587 ps
CPU time 1.76 seconds
Started Jun 23 05:19:57 PM PDT 24
Finished Jun 23 05:20:00 PM PDT 24
Peak memory 206180 kb
Host smart-96694841-3abc-4f7c-b4f9-28cc18f684c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53800
8335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.538008335
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.492995610
Short name T324
Test name
Test status
Simulation time 218968555 ps
CPU time 0.85 seconds
Started Jun 23 05:20:00 PM PDT 24
Finished Jun 23 05:20:01 PM PDT 24
Peak memory 206048 kb
Host smart-a0e94c2b-cc89-4847-b9b0-733207a8ba5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49299
5610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.492995610
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3265619997
Short name T1907
Test name
Test status
Simulation time 146208362 ps
CPU time 0.77 seconds
Started Jun 23 05:19:59 PM PDT 24
Finished Jun 23 05:20:01 PM PDT 24
Peak memory 206100 kb
Host smart-4df84e89-11e4-4e0d-8a8d-4537950d5265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32656
19997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3265619997
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.529009478
Short name T1924
Test name
Test status
Simulation time 266248579 ps
CPU time 0.95 seconds
Started Jun 23 05:19:54 PM PDT 24
Finished Jun 23 05:19:56 PM PDT 24
Peak memory 206000 kb
Host smart-392382ad-ad2d-440c-9d6e-9dfd3fc7ad79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52900
9478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.529009478
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.2316080097
Short name T676
Test name
Test status
Simulation time 204866657 ps
CPU time 0.92 seconds
Started Jun 23 05:19:54 PM PDT 24
Finished Jun 23 05:19:56 PM PDT 24
Peak memory 206032 kb
Host smart-618c11b5-86e8-420e-a9d6-dc6d0a026566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23160
80097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.2316080097
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3973746106
Short name T2480
Test name
Test status
Simulation time 23313014077 ps
CPU time 22.52 seconds
Started Jun 23 05:19:54 PM PDT 24
Finished Jun 23 05:20:17 PM PDT 24
Peak memory 206152 kb
Host smart-e8e0f8e8-3a3c-4575-a962-5185c35843ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39737
46106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3973746106
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2082757606
Short name T1081
Test name
Test status
Simulation time 3292095233 ps
CPU time 4.07 seconds
Started Jun 23 05:19:59 PM PDT 24
Finished Jun 23 05:20:03 PM PDT 24
Peak memory 206164 kb
Host smart-627067b3-50ba-413b-a4a3-adbab533bb9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20827
57606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2082757606
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.2898347195
Short name T862
Test name
Test status
Simulation time 9602133808 ps
CPU time 88.02 seconds
Started Jun 23 05:20:03 PM PDT 24
Finished Jun 23 05:21:31 PM PDT 24
Peak memory 206344 kb
Host smart-51ae7825-8b70-482c-b2dd-03f07b134927
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2898347195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.2898347195
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.890862131
Short name T2467
Test name
Test status
Simulation time 237035577 ps
CPU time 1.03 seconds
Started Jun 23 05:20:04 PM PDT 24
Finished Jun 23 05:20:06 PM PDT 24
Peak memory 206120 kb
Host smart-e04d6150-409e-445b-883a-16c94b4ab259
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=890862131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.890862131
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.4257830126
Short name T1556
Test name
Test status
Simulation time 222876534 ps
CPU time 0.89 seconds
Started Jun 23 05:19:55 PM PDT 24
Finished Jun 23 05:19:57 PM PDT 24
Peak memory 206124 kb
Host smart-f7fbd5de-c3ee-4426-9088-f5cbc3a9b549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42578
30126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.4257830126
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.826592753
Short name T966
Test name
Test status
Simulation time 6253320357 ps
CPU time 41.62 seconds
Started Jun 23 05:19:57 PM PDT 24
Finished Jun 23 05:20:40 PM PDT 24
Peak memory 206368 kb
Host smart-684e605f-b3c2-4a1a-bccd-4aaec8838ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82659
2753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.826592753
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.663591023
Short name T1648
Test name
Test status
Simulation time 5764476918 ps
CPU time 52.3 seconds
Started Jun 23 05:20:00 PM PDT 24
Finished Jun 23 05:20:52 PM PDT 24
Peak memory 206352 kb
Host smart-d5d972ad-12df-492f-a2e3-cbde824cf6c4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=663591023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.663591023
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.1189907588
Short name T861
Test name
Test status
Simulation time 154843477 ps
CPU time 0.83 seconds
Started Jun 23 05:20:04 PM PDT 24
Finished Jun 23 05:20:06 PM PDT 24
Peak memory 206120 kb
Host smart-e2e3a8b7-9f79-4080-83dc-7b48ce1b8a0e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1189907588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.1189907588
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3537586360
Short name T626
Test name
Test status
Simulation time 155910879 ps
CPU time 0.81 seconds
Started Jun 23 05:20:01 PM PDT 24
Finished Jun 23 05:20:03 PM PDT 24
Peak memory 206104 kb
Host smart-6c5976e9-89f7-4adc-9bd9-d329deb6dd98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35375
86360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3537586360
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2116409508
Short name T136
Test name
Test status
Simulation time 229836318 ps
CPU time 0.83 seconds
Started Jun 23 05:19:58 PM PDT 24
Finished Jun 23 05:20:00 PM PDT 24
Peak memory 206044 kb
Host smart-11940358-ff33-4d4e-b90d-3be638847c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21164
09508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2116409508
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.1454343346
Short name T746
Test name
Test status
Simulation time 164184193 ps
CPU time 0.83 seconds
Started Jun 23 05:20:05 PM PDT 24
Finished Jun 23 05:20:06 PM PDT 24
Peak memory 206092 kb
Host smart-b78c1505-5e50-4fc6-bca9-d7ef71cedd92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14543
43346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.1454343346
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1237819126
Short name T1670
Test name
Test status
Simulation time 149000225 ps
CPU time 0.79 seconds
Started Jun 23 05:19:59 PM PDT 24
Finished Jun 23 05:20:00 PM PDT 24
Peak memory 206032 kb
Host smart-0ab8c724-5aa7-4b0c-a4e8-341cfab486ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12378
19126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1237819126
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3025074769
Short name T889
Test name
Test status
Simulation time 174774417 ps
CPU time 0.77 seconds
Started Jun 23 05:20:02 PM PDT 24
Finished Jun 23 05:20:03 PM PDT 24
Peak memory 206048 kb
Host smart-a5a18db8-8ab6-40c6-a229-e10b9a164f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30250
74769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3025074769
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3248567858
Short name T777
Test name
Test status
Simulation time 212977181 ps
CPU time 0.85 seconds
Started Jun 23 05:19:59 PM PDT 24
Finished Jun 23 05:20:01 PM PDT 24
Peak memory 206104 kb
Host smart-17a004c3-473e-4a55-bded-2ed6877a5c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32485
67858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3248567858
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1534594536
Short name T371
Test name
Test status
Simulation time 197272186 ps
CPU time 0.89 seconds
Started Jun 23 05:19:59 PM PDT 24
Finished Jun 23 05:20:01 PM PDT 24
Peak memory 206132 kb
Host smart-2788125a-9e43-4bac-9764-7175b0ff966d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1534594536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1534594536
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.4077666597
Short name T184
Test name
Test status
Simulation time 189976859 ps
CPU time 0.84 seconds
Started Jun 23 05:20:02 PM PDT 24
Finished Jun 23 05:20:04 PM PDT 24
Peak memory 206112 kb
Host smart-c612c1c4-27eb-4edd-af70-15eb066bf45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40776
66597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.4077666597
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3109456506
Short name T1968
Test name
Test status
Simulation time 42691151 ps
CPU time 0.68 seconds
Started Jun 23 05:20:00 PM PDT 24
Finished Jun 23 05:20:02 PM PDT 24
Peak memory 206112 kb
Host smart-d4052881-57df-4f1a-bab0-f0e020eb4816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31094
56506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3109456506
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3246355082
Short name T1303
Test name
Test status
Simulation time 14446312099 ps
CPU time 32.33 seconds
Started Jun 23 05:20:01 PM PDT 24
Finished Jun 23 05:20:33 PM PDT 24
Peak memory 206404 kb
Host smart-da7baaa0-4c6e-453b-a7c3-53acc2513ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32463
55082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3246355082
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2656634879
Short name T208
Test name
Test status
Simulation time 180659387 ps
CPU time 0.81 seconds
Started Jun 23 05:19:59 PM PDT 24
Finished Jun 23 05:20:00 PM PDT 24
Peak memory 206104 kb
Host smart-6ff76ca3-5e00-4e19-b4e7-92fdf5bd9814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26566
34879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2656634879
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2102609057
Short name T2089
Test name
Test status
Simulation time 234259961 ps
CPU time 0.93 seconds
Started Jun 23 05:20:04 PM PDT 24
Finished Jun 23 05:20:06 PM PDT 24
Peak memory 206092 kb
Host smart-5f1400a4-5106-459c-97f0-fdc61fd1b52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21026
09057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2102609057
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.3507145178
Short name T1898
Test name
Test status
Simulation time 157914111 ps
CPU time 0.78 seconds
Started Jun 23 05:20:02 PM PDT 24
Finished Jun 23 05:20:03 PM PDT 24
Peak memory 206112 kb
Host smart-9d525e94-2c19-4799-853e-fbdd82dd6017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35071
45178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.3507145178
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.147519721
Short name T1839
Test name
Test status
Simulation time 170649950 ps
CPU time 0.87 seconds
Started Jun 23 05:19:59 PM PDT 24
Finished Jun 23 05:20:00 PM PDT 24
Peak memory 206120 kb
Host smart-5a775478-0c60-4cdd-b2dc-7d2f2cc889f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14751
9721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.147519721
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.547639222
Short name T1423
Test name
Test status
Simulation time 175462474 ps
CPU time 0.81 seconds
Started Jun 23 05:20:02 PM PDT 24
Finished Jun 23 05:20:03 PM PDT 24
Peak memory 206112 kb
Host smart-043a4643-6ee4-486c-ad7f-ba989c077815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54763
9222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.547639222
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1757780453
Short name T1487
Test name
Test status
Simulation time 184145915 ps
CPU time 0.79 seconds
Started Jun 23 05:20:00 PM PDT 24
Finished Jun 23 05:20:02 PM PDT 24
Peak memory 206288 kb
Host smart-40ff2764-2fe6-4885-885d-38299c10090c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17577
80453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1757780453
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.4162485724
Short name T389
Test name
Test status
Simulation time 170816470 ps
CPU time 0.82 seconds
Started Jun 23 05:20:01 PM PDT 24
Finished Jun 23 05:20:02 PM PDT 24
Peak memory 206096 kb
Host smart-638a34e1-ce08-4b13-a425-357e01310894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41624
85724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.4162485724
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.3212730044
Short name T1655
Test name
Test status
Simulation time 234330873 ps
CPU time 0.92 seconds
Started Jun 23 05:19:53 PM PDT 24
Finished Jun 23 05:19:54 PM PDT 24
Peak memory 206024 kb
Host smart-5c0e6113-fc9d-4344-b666-07f4036085fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32127
30044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.3212730044
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.1308477715
Short name T2211
Test name
Test status
Simulation time 5114291086 ps
CPU time 37.19 seconds
Started Jun 23 05:20:00 PM PDT 24
Finished Jun 23 05:20:38 PM PDT 24
Peak memory 206352 kb
Host smart-6ee24f14-4ae0-4832-a753-a44133de17a7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1308477715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.1308477715
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2224857801
Short name T1534
Test name
Test status
Simulation time 209625445 ps
CPU time 0.85 seconds
Started Jun 23 05:20:00 PM PDT 24
Finished Jun 23 05:20:01 PM PDT 24
Peak memory 206112 kb
Host smart-fc6cb426-898c-4560-be4a-8bd97495b4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22248
57801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2224857801
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.269205962
Short name T1713
Test name
Test status
Simulation time 183526902 ps
CPU time 0.87 seconds
Started Jun 23 05:20:01 PM PDT 24
Finished Jun 23 05:20:03 PM PDT 24
Peak memory 206096 kb
Host smart-ef02c272-b8b2-4649-ac62-f073210ef413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26920
5962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.269205962
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.4041370113
Short name T2231
Test name
Test status
Simulation time 10382408732 ps
CPU time 301.84 seconds
Started Jun 23 05:19:58 PM PDT 24
Finished Jun 23 05:25:00 PM PDT 24
Peak memory 206248 kb
Host smart-376c405a-5dda-4a41-ac40-857df28ba2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40413
70113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.4041370113
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.743166123
Short name T963
Test name
Test status
Simulation time 3887829298 ps
CPU time 4.86 seconds
Started Jun 23 05:20:03 PM PDT 24
Finished Jun 23 05:20:08 PM PDT 24
Peak memory 206192 kb
Host smart-16af0211-8c2a-4260-a9a0-723de3d3ad54
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=743166123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.743166123
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.1099741185
Short name T402
Test name
Test status
Simulation time 13373182922 ps
CPU time 11.44 seconds
Started Jun 23 05:20:03 PM PDT 24
Finished Jun 23 05:20:15 PM PDT 24
Peak memory 206328 kb
Host smart-2cae68d2-1e1b-4bf5-849f-8ffc59c11411
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1099741185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.1099741185
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.2646829069
Short name T1327
Test name
Test status
Simulation time 23325792674 ps
CPU time 22.97 seconds
Started Jun 23 05:20:05 PM PDT 24
Finished Jun 23 05:20:28 PM PDT 24
Peak memory 206160 kb
Host smart-a806a418-c9e3-4913-94e8-2fe128d4ceea
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2646829069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.2646829069
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1804453105
Short name T455
Test name
Test status
Simulation time 201108196 ps
CPU time 0.89 seconds
Started Jun 23 05:20:04 PM PDT 24
Finished Jun 23 05:20:05 PM PDT 24
Peak memory 206108 kb
Host smart-2615a1fd-7f4c-4deb-ace0-785760fe26ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18044
53105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1804453105
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.1781489235
Short name T347
Test name
Test status
Simulation time 179394606 ps
CPU time 0.8 seconds
Started Jun 23 05:20:06 PM PDT 24
Finished Jun 23 05:20:07 PM PDT 24
Peak memory 206032 kb
Host smart-e11994db-c062-4c3c-93fa-9252bf28d4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17814
89235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.1781489235
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.274449347
Short name T151
Test name
Test status
Simulation time 1250790354 ps
CPU time 2.89 seconds
Started Jun 23 05:20:04 PM PDT 24
Finished Jun 23 05:20:07 PM PDT 24
Peak memory 206356 kb
Host smart-f1187913-e181-40b4-8a17-35ab4fd891df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27444
9347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.274449347
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.903820624
Short name T157
Test name
Test status
Simulation time 13474440387 ps
CPU time 25.29 seconds
Started Jun 23 05:20:07 PM PDT 24
Finished Jun 23 05:20:32 PM PDT 24
Peak memory 206376 kb
Host smart-cda43ebf-9ba9-40d2-b295-83d6b4b75166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90382
0624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.903820624
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.899957062
Short name T1106
Test name
Test status
Simulation time 366471639 ps
CPU time 1.22 seconds
Started Jun 23 05:20:06 PM PDT 24
Finished Jun 23 05:20:08 PM PDT 24
Peak memory 206028 kb
Host smart-998bf27a-a795-4abc-acd6-3c7fe2cc96f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89995
7062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.899957062
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1186474867
Short name T40
Test name
Test status
Simulation time 146183775 ps
CPU time 0.78 seconds
Started Jun 23 05:20:03 PM PDT 24
Finished Jun 23 05:20:05 PM PDT 24
Peak memory 206092 kb
Host smart-fe394a58-648d-4657-a9b2-5a245c254418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11864
74867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1186474867
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.869835945
Short name T1072
Test name
Test status
Simulation time 40557848 ps
CPU time 0.63 seconds
Started Jun 23 05:20:05 PM PDT 24
Finished Jun 23 05:20:06 PM PDT 24
Peak memory 206096 kb
Host smart-12e315c4-be79-49f2-958d-5f804e3f2dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86983
5945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.869835945
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3626440546
Short name T737
Test name
Test status
Simulation time 967424067 ps
CPU time 2.25 seconds
Started Jun 23 05:20:06 PM PDT 24
Finished Jun 23 05:20:08 PM PDT 24
Peak memory 206308 kb
Host smart-3fd71f8a-4833-42ef-a2bc-f646eda2c6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36264
40546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3626440546
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1767051416
Short name T995
Test name
Test status
Simulation time 231843094 ps
CPU time 1.43 seconds
Started Jun 23 05:20:06 PM PDT 24
Finished Jun 23 05:20:08 PM PDT 24
Peak memory 206348 kb
Host smart-3ad5f844-9145-4877-b809-de1f80d57f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17670
51416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1767051416
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.3577407912
Short name T1080
Test name
Test status
Simulation time 189188200 ps
CPU time 0.85 seconds
Started Jun 23 05:20:10 PM PDT 24
Finished Jun 23 05:20:12 PM PDT 24
Peak memory 206108 kb
Host smart-a31f1f49-3eaf-45cb-bf8a-dda63eb964de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35774
07912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3577407912
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1516355735
Short name T386
Test name
Test status
Simulation time 143667339 ps
CPU time 0.75 seconds
Started Jun 23 05:20:10 PM PDT 24
Finished Jun 23 05:20:11 PM PDT 24
Peak memory 206036 kb
Host smart-6bc560ca-0f52-4604-8fb9-3233f4c005f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15163
55735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1516355735
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1051055749
Short name T284
Test name
Test status
Simulation time 164861631 ps
CPU time 0.83 seconds
Started Jun 23 05:20:06 PM PDT 24
Finished Jun 23 05:20:07 PM PDT 24
Peak memory 206100 kb
Host smart-4181d2ef-f08c-403b-9a8e-6a29e20647d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10510
55749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1051055749
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.3644874269
Short name T1249
Test name
Test status
Simulation time 223122619 ps
CPU time 0.89 seconds
Started Jun 23 05:20:05 PM PDT 24
Finished Jun 23 05:20:06 PM PDT 24
Peak memory 206100 kb
Host smart-41c8bc05-d971-4608-bd1f-42c4f5192fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36448
74269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3644874269
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.1950815724
Short name T363
Test name
Test status
Simulation time 23282854630 ps
CPU time 30.56 seconds
Started Jun 23 05:20:06 PM PDT 24
Finished Jun 23 05:20:38 PM PDT 24
Peak memory 206164 kb
Host smart-16f2f0c4-c909-4aa6-aac4-b9ddf80b30f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19508
15724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.1950815724
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.4186704475
Short name T304
Test name
Test status
Simulation time 3340535024 ps
CPU time 3.48 seconds
Started Jun 23 05:20:07 PM PDT 24
Finished Jun 23 05:20:11 PM PDT 24
Peak memory 206160 kb
Host smart-0a7d880f-afa1-4151-b265-35a121f47337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41867
04475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.4186704475
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.1605297326
Short name T651
Test name
Test status
Simulation time 8161870403 ps
CPU time 62.03 seconds
Started Jun 23 05:20:05 PM PDT 24
Finished Jun 23 05:21:07 PM PDT 24
Peak memory 206336 kb
Host smart-0829344a-d239-42a3-ad2f-c2738e53dcff
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1605297326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.1605297326
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.3317218550
Short name T564
Test name
Test status
Simulation time 240287700 ps
CPU time 0.91 seconds
Started Jun 23 05:20:13 PM PDT 24
Finished Jun 23 05:20:14 PM PDT 24
Peak memory 206048 kb
Host smart-25d3aeb3-1c5d-4bd3-b8a1-e708a438622b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3317218550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.3317218550
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.972046814
Short name T2432
Test name
Test status
Simulation time 187524194 ps
CPU time 0.85 seconds
Started Jun 23 05:20:08 PM PDT 24
Finished Jun 23 05:20:09 PM PDT 24
Peak memory 206124 kb
Host smart-087d151a-3ac5-4d5a-833e-e35ec79126ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97204
6814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.972046814
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.1512972812
Short name T1742
Test name
Test status
Simulation time 12390121161 ps
CPU time 116.56 seconds
Started Jun 23 05:20:06 PM PDT 24
Finished Jun 23 05:22:03 PM PDT 24
Peak memory 206416 kb
Host smart-d7d465cb-122c-424f-a0bd-ab8baeb94b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15129
72812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.1512972812
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1155283769
Short name T2186
Test name
Test status
Simulation time 5059226020 ps
CPU time 34.06 seconds
Started Jun 23 05:20:10 PM PDT 24
Finished Jun 23 05:20:45 PM PDT 24
Peak memory 206332 kb
Host smart-37aab9ff-67f5-4ff2-a81d-0cdb17e38d7c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1155283769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1155283769
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3182218011
Short name T1482
Test name
Test status
Simulation time 161830143 ps
CPU time 0.79 seconds
Started Jun 23 05:20:11 PM PDT 24
Finished Jun 23 05:20:13 PM PDT 24
Peak memory 206296 kb
Host smart-60fceaf1-8dec-40a1-8577-0ac774f58448
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3182218011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3182218011
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.230181300
Short name T1628
Test name
Test status
Simulation time 155770651 ps
CPU time 0.76 seconds
Started Jun 23 05:20:06 PM PDT 24
Finished Jun 23 05:20:08 PM PDT 24
Peak memory 206048 kb
Host smart-785c9d6c-cf95-45a0-bd50-f10193cecadd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23018
1300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.230181300
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3657484473
Short name T2012
Test name
Test status
Simulation time 210322677 ps
CPU time 0.89 seconds
Started Jun 23 05:20:05 PM PDT 24
Finished Jun 23 05:20:07 PM PDT 24
Peak memory 206020 kb
Host smart-c75290f5-b18f-4fd3-8f74-5417efbd4971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36574
84473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3657484473
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.3175785522
Short name T1051
Test name
Test status
Simulation time 175234975 ps
CPU time 0.81 seconds
Started Jun 23 05:20:04 PM PDT 24
Finished Jun 23 05:20:06 PM PDT 24
Peak memory 206072 kb
Host smart-d2f51cb0-d8b3-40e0-b9cc-5bde70b4cede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31757
85522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3175785522
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2893104984
Short name T317
Test name
Test status
Simulation time 144513929 ps
CPU time 0.78 seconds
Started Jun 23 05:20:05 PM PDT 24
Finished Jun 23 05:20:06 PM PDT 24
Peak memory 206028 kb
Host smart-ffa16bf4-f099-4235-9f51-e792ccbe0c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28931
04984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2893104984
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.447154450
Short name T705
Test name
Test status
Simulation time 178379995 ps
CPU time 0.78 seconds
Started Jun 23 05:20:05 PM PDT 24
Finished Jun 23 05:20:07 PM PDT 24
Peak memory 206032 kb
Host smart-2f3c2721-23bf-482d-8041-4cb82fef5f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44715
4450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.447154450
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.890121058
Short name T1970
Test name
Test status
Simulation time 154019746 ps
CPU time 0.77 seconds
Started Jun 23 05:20:10 PM PDT 24
Finished Jun 23 05:20:12 PM PDT 24
Peak memory 206036 kb
Host smart-31bfd578-b262-400d-a96a-e457dd073fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89012
1058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.890121058
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.3511589093
Short name T1465
Test name
Test status
Simulation time 207145418 ps
CPU time 0.92 seconds
Started Jun 23 05:20:09 PM PDT 24
Finished Jun 23 05:20:11 PM PDT 24
Peak memory 206056 kb
Host smart-359770ab-3e56-40b0-a955-2ebefb1d10e4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3511589093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3511589093
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.459896741
Short name T580
Test name
Test status
Simulation time 154108216 ps
CPU time 0.81 seconds
Started Jun 23 05:20:09 PM PDT 24
Finished Jun 23 05:20:10 PM PDT 24
Peak memory 206104 kb
Host smart-a59994e5-63bc-4b05-9ce4-1e8a42cb099e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45989
6741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.459896741
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3538876187
Short name T36
Test name
Test status
Simulation time 35492312 ps
CPU time 0.67 seconds
Started Jun 23 05:20:10 PM PDT 24
Finished Jun 23 05:20:12 PM PDT 24
Peak memory 206112 kb
Host smart-e3a32aca-96f3-41b0-ba04-6f0e7ae1f1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35388
76187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3538876187
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3851983870
Short name T2322
Test name
Test status
Simulation time 9138629489 ps
CPU time 19.78 seconds
Started Jun 23 05:20:05 PM PDT 24
Finished Jun 23 05:20:25 PM PDT 24
Peak memory 206396 kb
Host smart-0883a591-5a33-4333-aa0e-d79cee4f2512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38519
83870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3851983870
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.594786146
Short name T350
Test name
Test status
Simulation time 256009701 ps
CPU time 0.91 seconds
Started Jun 23 05:20:08 PM PDT 24
Finished Jun 23 05:20:09 PM PDT 24
Peak memory 206100 kb
Host smart-f9782c7e-8964-4375-8e7a-4a3cf02dc20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59478
6146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.594786146
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2682347538
Short name T741
Test name
Test status
Simulation time 239221474 ps
CPU time 0.89 seconds
Started Jun 23 05:20:07 PM PDT 24
Finished Jun 23 05:20:09 PM PDT 24
Peak memory 206096 kb
Host smart-cad41aaf-b098-455c-9747-fcc0612a85ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26823
47538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2682347538
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.555218304
Short name T479
Test name
Test status
Simulation time 181050249 ps
CPU time 0.82 seconds
Started Jun 23 05:20:12 PM PDT 24
Finished Jun 23 05:20:14 PM PDT 24
Peak memory 206104 kb
Host smart-3e5ac1ec-eeca-4b63-b9b5-5c57b131a4c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55521
8304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.555218304
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.196888693
Short name T323
Test name
Test status
Simulation time 155616314 ps
CPU time 0.83 seconds
Started Jun 23 05:20:10 PM PDT 24
Finished Jun 23 05:20:12 PM PDT 24
Peak memory 206120 kb
Host smart-71f32f22-02e2-4893-b0a8-a20725c574ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19688
8693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.196888693
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1183258738
Short name T2014
Test name
Test status
Simulation time 153392352 ps
CPU time 0.77 seconds
Started Jun 23 05:20:08 PM PDT 24
Finished Jun 23 05:20:09 PM PDT 24
Peak memory 206100 kb
Host smart-93875b47-52eb-4e5c-b559-cd0b16bf3b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11832
58738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1183258738
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.505054127
Short name T438
Test name
Test status
Simulation time 149082033 ps
CPU time 0.76 seconds
Started Jun 23 05:20:11 PM PDT 24
Finished Jun 23 05:20:12 PM PDT 24
Peak memory 205992 kb
Host smart-73831fb8-5485-476c-ae93-33d7bd3aa03d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50505
4127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.505054127
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2507496992
Short name T2227
Test name
Test status
Simulation time 150994088 ps
CPU time 0.8 seconds
Started Jun 23 05:20:09 PM PDT 24
Finished Jun 23 05:20:11 PM PDT 24
Peak memory 206008 kb
Host smart-debf682b-bd00-4b89-88f8-a8c37a86b13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25074
96992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2507496992
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2439397231
Short name T1387
Test name
Test status
Simulation time 233705118 ps
CPU time 0.89 seconds
Started Jun 23 05:20:04 PM PDT 24
Finished Jun 23 05:20:05 PM PDT 24
Peak memory 206064 kb
Host smart-2d387146-f13d-42dd-9f1d-330a092d7d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24393
97231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2439397231
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.2691272108
Short name T1822
Test name
Test status
Simulation time 2823964905 ps
CPU time 20.8 seconds
Started Jun 23 05:20:12 PM PDT 24
Finished Jun 23 05:20:33 PM PDT 24
Peak memory 206328 kb
Host smart-8348c049-a200-4fbc-8f98-b02ec45e435c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2691272108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2691272108
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3118055431
Short name T1197
Test name
Test status
Simulation time 206146753 ps
CPU time 0.89 seconds
Started Jun 23 05:20:10 PM PDT 24
Finished Jun 23 05:20:12 PM PDT 24
Peak memory 206124 kb
Host smart-521b38b8-691d-4afc-8f79-d0232c5c583b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31180
55431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3118055431
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1965821427
Short name T1942
Test name
Test status
Simulation time 195839433 ps
CPU time 0.86 seconds
Started Jun 23 05:20:11 PM PDT 24
Finished Jun 23 05:20:13 PM PDT 24
Peak memory 206160 kb
Host smart-850a076e-0516-4044-b76b-923571f808a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19658
21427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1965821427
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.449902046
Short name T2129
Test name
Test status
Simulation time 3220070047 ps
CPU time 22.27 seconds
Started Jun 23 05:20:09 PM PDT 24
Finished Jun 23 05:20:32 PM PDT 24
Peak memory 206328 kb
Host smart-4ab838f9-31c2-4064-8e68-790e12f50843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44990
2046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.449902046
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.3713654341
Short name T2434
Test name
Test status
Simulation time 3516422938 ps
CPU time 4.87 seconds
Started Jun 23 05:20:13 PM PDT 24
Finished Jun 23 05:20:18 PM PDT 24
Peak memory 206188 kb
Host smart-a54ed2c6-9127-4785-9567-9700fefffcc8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3713654341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.3713654341
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.917640830
Short name T2449
Test name
Test status
Simulation time 13388864426 ps
CPU time 12.96 seconds
Started Jun 23 05:20:09 PM PDT 24
Finished Jun 23 05:20:23 PM PDT 24
Peak memory 206332 kb
Host smart-7b475769-2981-4a8b-bb6a-b16f97ba79a8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=917640830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.917640830
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3528656951
Short name T836
Test name
Test status
Simulation time 23355772120 ps
CPU time 21.58 seconds
Started Jun 23 05:20:09 PM PDT 24
Finished Jun 23 05:20:31 PM PDT 24
Peak memory 206300 kb
Host smart-98189e67-e412-46f1-92ee-f7bf25e12d92
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3528656951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.3528656951
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3600691793
Short name T1999
Test name
Test status
Simulation time 190726971 ps
CPU time 0.8 seconds
Started Jun 23 05:20:11 PM PDT 24
Finished Jun 23 05:20:13 PM PDT 24
Peak memory 206104 kb
Host smart-ed2a2e27-b48f-4837-b682-f49ffea618e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36006
91793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3600691793
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.2026715005
Short name T1288
Test name
Test status
Simulation time 139402202 ps
CPU time 0.77 seconds
Started Jun 23 05:20:09 PM PDT 24
Finished Jun 23 05:20:10 PM PDT 24
Peak memory 206048 kb
Host smart-0cea3edf-1013-4db6-925b-ec43813942a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20267
15005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.2026715005
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.4220586704
Short name T556
Test name
Test status
Simulation time 365116309 ps
CPU time 1.17 seconds
Started Jun 23 05:20:10 PM PDT 24
Finished Jun 23 05:20:12 PM PDT 24
Peak memory 206060 kb
Host smart-5b01dab7-41a9-4e60-9174-76955cb80445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42205
86704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.4220586704
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.1433178669
Short name T1330
Test name
Test status
Simulation time 1430786908 ps
CPU time 2.94 seconds
Started Jun 23 05:20:09 PM PDT 24
Finished Jun 23 05:20:13 PM PDT 24
Peak memory 206232 kb
Host smart-ebb2ee24-fe26-4718-8cba-a6ccf7d32003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14331
78669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.1433178669
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.1271493341
Short name T1590
Test name
Test status
Simulation time 377595355 ps
CPU time 1.15 seconds
Started Jun 23 05:20:09 PM PDT 24
Finished Jun 23 05:20:11 PM PDT 24
Peak memory 206044 kb
Host smart-16a0f0c6-b8c1-499c-884b-de229fa6fa7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12714
93341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.1271493341
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.675580247
Short name T2497
Test name
Test status
Simulation time 135676793 ps
CPU time 0.76 seconds
Started Jun 23 05:20:11 PM PDT 24
Finished Jun 23 05:20:13 PM PDT 24
Peak memory 206100 kb
Host smart-a9aa0b16-8574-4033-87e8-d835510278a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67558
0247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.675580247
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3098588966
Short name T1615
Test name
Test status
Simulation time 59510250 ps
CPU time 0.68 seconds
Started Jun 23 05:20:10 PM PDT 24
Finished Jun 23 05:20:12 PM PDT 24
Peak memory 206152 kb
Host smart-6c3a2a3f-3a0e-48d6-8d4c-da133a9ab2cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30985
88966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3098588966
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.2510954054
Short name T1183
Test name
Test status
Simulation time 851099461 ps
CPU time 1.95 seconds
Started Jun 23 05:20:11 PM PDT 24
Finished Jun 23 05:20:14 PM PDT 24
Peak memory 206524 kb
Host smart-37b11613-f2b0-4c0d-9ae5-01b2346f2b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25109
54054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.2510954054
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1873605229
Short name T902
Test name
Test status
Simulation time 294006068 ps
CPU time 1.84 seconds
Started Jun 23 05:20:16 PM PDT 24
Finished Jun 23 05:20:18 PM PDT 24
Peak memory 206316 kb
Host smart-471348f2-09c5-4d82-ba32-5a7268360d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18736
05229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1873605229
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1114015118
Short name T1647
Test name
Test status
Simulation time 185392214 ps
CPU time 0.86 seconds
Started Jun 23 05:20:19 PM PDT 24
Finished Jun 23 05:20:20 PM PDT 24
Peak memory 206104 kb
Host smart-695ee46c-fcef-446e-8754-cec30ef5ed6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11140
15118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1114015118
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.2116920515
Short name T841
Test name
Test status
Simulation time 169022444 ps
CPU time 0.78 seconds
Started Jun 23 05:20:20 PM PDT 24
Finished Jun 23 05:20:21 PM PDT 24
Peak memory 206096 kb
Host smart-a9a86518-aba2-4eda-8045-5c3a8ee0bf72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21169
20515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2116920515
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3212030373
Short name T2473
Test name
Test status
Simulation time 211232944 ps
CPU time 0.88 seconds
Started Jun 23 05:20:21 PM PDT 24
Finished Jun 23 05:20:23 PM PDT 24
Peak memory 206096 kb
Host smart-d9c99fb3-56e1-4061-a9f0-5cbe3886310f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32120
30373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3212030373
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.3699540318
Short name T2223
Test name
Test status
Simulation time 13468319010 ps
CPU time 123.6 seconds
Started Jun 23 05:20:14 PM PDT 24
Finished Jun 23 05:22:19 PM PDT 24
Peak memory 206312 kb
Host smart-63e364e9-a12a-4770-a2e3-515f872aaac8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3699540318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.3699540318
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2574101881
Short name T2369
Test name
Test status
Simulation time 170822052 ps
CPU time 0.8 seconds
Started Jun 23 05:20:12 PM PDT 24
Finished Jun 23 05:20:14 PM PDT 24
Peak memory 206100 kb
Host smart-bc2da12f-08bd-4815-9f33-4c7715094711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25741
01881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2574101881
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.3620734475
Short name T2252
Test name
Test status
Simulation time 23339281584 ps
CPU time 23.59 seconds
Started Jun 23 05:20:17 PM PDT 24
Finished Jun 23 05:20:41 PM PDT 24
Peak memory 205808 kb
Host smart-4f990697-816a-4751-a0c5-bda7e64f647b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36207
34475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.3620734475
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.29444525
Short name T808
Test name
Test status
Simulation time 3328964765 ps
CPU time 4.75 seconds
Started Jun 23 05:20:17 PM PDT 24
Finished Jun 23 05:20:22 PM PDT 24
Peak memory 205816 kb
Host smart-9d6207a9-f751-4916-9108-ab434d9920ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29444
525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.29444525
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.1266215592
Short name T2166
Test name
Test status
Simulation time 11989331693 ps
CPU time 326.47 seconds
Started Jun 23 05:20:13 PM PDT 24
Finished Jun 23 05:25:40 PM PDT 24
Peak memory 206268 kb
Host smart-e9be1a27-7e49-495b-8e67-5da804f8865c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1266215592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.1266215592
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.2580832959
Short name T1089
Test name
Test status
Simulation time 256123460 ps
CPU time 0.92 seconds
Started Jun 23 05:20:21 PM PDT 24
Finished Jun 23 05:20:23 PM PDT 24
Peak memory 206128 kb
Host smart-d76ebe79-7d16-4838-8d6b-952fbee14656
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2580832959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.2580832959
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.4219507221
Short name T404
Test name
Test status
Simulation time 183172398 ps
CPU time 0.91 seconds
Started Jun 23 05:20:17 PM PDT 24
Finished Jun 23 05:20:18 PM PDT 24
Peak memory 206036 kb
Host smart-527bbce5-9f0c-4c96-ac83-c99104f82987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42195
07221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.4219507221
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.4026381432
Short name T369
Test name
Test status
Simulation time 6283410828 ps
CPU time 178.69 seconds
Started Jun 23 05:20:14 PM PDT 24
Finished Jun 23 05:23:13 PM PDT 24
Peak memory 206256 kb
Host smart-3c881a6b-4bce-446d-a6f3-c8c279d4f1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40263
81432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.4026381432
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.3830348034
Short name T888
Test name
Test status
Simulation time 9919381728 ps
CPU time 71.04 seconds
Started Jun 23 05:20:14 PM PDT 24
Finished Jun 23 05:21:25 PM PDT 24
Peak memory 206376 kb
Host smart-3ea08968-567f-475b-95ce-94f746c6b354
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3830348034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.3830348034
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.1198713396
Short name T2361
Test name
Test status
Simulation time 184339674 ps
CPU time 0.92 seconds
Started Jun 23 05:20:19 PM PDT 24
Finished Jun 23 05:20:21 PM PDT 24
Peak memory 206128 kb
Host smart-ef33d4a8-7687-4f32-b260-a43cd3fe58d6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1198713396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.1198713396
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3815386990
Short name T631
Test name
Test status
Simulation time 156895284 ps
CPU time 0.78 seconds
Started Jun 23 05:20:17 PM PDT 24
Finished Jun 23 05:20:18 PM PDT 24
Peak memory 206108 kb
Host smart-4a8cb545-bab3-4cf8-beea-e9fb94aed9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38153
86990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3815386990
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2797821622
Short name T129
Test name
Test status
Simulation time 182214483 ps
CPU time 0.86 seconds
Started Jun 23 05:20:14 PM PDT 24
Finished Jun 23 05:20:15 PM PDT 24
Peak memory 206120 kb
Host smart-59935c2b-bf29-4d40-a236-b62f18e5c5b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27978
21622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2797821622
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.747840466
Short name T2281
Test name
Test status
Simulation time 206598219 ps
CPU time 0.89 seconds
Started Jun 23 05:20:21 PM PDT 24
Finished Jun 23 05:20:23 PM PDT 24
Peak memory 206100 kb
Host smart-a827a7b2-c45c-4bb3-9d9c-793eededda59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74784
0466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.747840466
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.476096693
Short name T2226
Test name
Test status
Simulation time 147590554 ps
CPU time 0.83 seconds
Started Jun 23 05:20:19 PM PDT 24
Finished Jun 23 05:20:20 PM PDT 24
Peak memory 206020 kb
Host smart-3f0c7786-2d30-4c1e-837f-e2a801e95a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47609
6693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.476096693
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3238502582
Short name T2138
Test name
Test status
Simulation time 164272546 ps
CPU time 0.8 seconds
Started Jun 23 05:20:14 PM PDT 24
Finished Jun 23 05:20:16 PM PDT 24
Peak memory 206072 kb
Host smart-dc90d0a3-daa7-4cb0-b4e3-54cffa231690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32385
02582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3238502582
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.412047807
Short name T1720
Test name
Test status
Simulation time 164644992 ps
CPU time 0.82 seconds
Started Jun 23 05:20:21 PM PDT 24
Finished Jun 23 05:20:22 PM PDT 24
Peak memory 206092 kb
Host smart-b85a47c2-8a9e-464f-a793-971bb03b91cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41204
7807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.412047807
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.2204406437
Short name T1887
Test name
Test status
Simulation time 247332877 ps
CPU time 0.96 seconds
Started Jun 23 05:20:13 PM PDT 24
Finished Jun 23 05:20:15 PM PDT 24
Peak memory 206112 kb
Host smart-f49d5f55-5d88-4d36-9d54-a7f9a2de549a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2204406437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.2204406437
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1207100140
Short name T1284
Test name
Test status
Simulation time 198911557 ps
CPU time 0.8 seconds
Started Jun 23 05:20:18 PM PDT 24
Finished Jun 23 05:20:19 PM PDT 24
Peak memory 206112 kb
Host smart-feb51538-d4fb-4b88-bb22-1329bc93458e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12071
00140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1207100140
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1091548015
Short name T1637
Test name
Test status
Simulation time 38203966 ps
CPU time 0.69 seconds
Started Jun 23 05:20:19 PM PDT 24
Finished Jun 23 05:20:20 PM PDT 24
Peak memory 206108 kb
Host smart-29e09793-fb41-4b87-8786-6452ac6487f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10915
48015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1091548015
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.776640647
Short name T2373
Test name
Test status
Simulation time 13840543841 ps
CPU time 31.7 seconds
Started Jun 23 05:20:16 PM PDT 24
Finished Jun 23 05:20:49 PM PDT 24
Peak memory 206348 kb
Host smart-b3f62381-9c27-41ce-8801-ca7ef4b08cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77664
0647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.776640647
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2441698689
Short name T1806
Test name
Test status
Simulation time 153105914 ps
CPU time 0.83 seconds
Started Jun 23 05:20:16 PM PDT 24
Finished Jun 23 05:20:18 PM PDT 24
Peak memory 206104 kb
Host smart-159fc5cd-af0b-40ed-aed0-e29d2e3b6e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24416
98689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2441698689
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.119682998
Short name T731
Test name
Test status
Simulation time 236451102 ps
CPU time 0.91 seconds
Started Jun 23 05:20:15 PM PDT 24
Finished Jun 23 05:20:16 PM PDT 24
Peak memory 206032 kb
Host smart-bf512de2-a4f7-404c-9815-e62484757343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11968
2998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.119682998
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.3788299724
Short name T281
Test name
Test status
Simulation time 230731804 ps
CPU time 0.87 seconds
Started Jun 23 05:20:20 PM PDT 24
Finished Jun 23 05:20:21 PM PDT 24
Peak memory 206108 kb
Host smart-a3832c6d-5eb1-4957-b0ad-981336892148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37882
99724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.3788299724
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.2748893005
Short name T513
Test name
Test status
Simulation time 202940649 ps
CPU time 0.87 seconds
Started Jun 23 05:20:15 PM PDT 24
Finished Jun 23 05:20:17 PM PDT 24
Peak memory 206116 kb
Host smart-3e5873f3-c784-4e3d-a8fe-d05f443ed95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27488
93005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.2748893005
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.413761306
Short name T596
Test name
Test status
Simulation time 141545819 ps
CPU time 0.75 seconds
Started Jun 23 05:20:14 PM PDT 24
Finished Jun 23 05:20:15 PM PDT 24
Peak memory 206096 kb
Host smart-6ec00e80-4933-419f-a973-2acf5ef30ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41376
1306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.413761306
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.3364574734
Short name T2337
Test name
Test status
Simulation time 149588033 ps
CPU time 0.79 seconds
Started Jun 23 05:20:16 PM PDT 24
Finished Jun 23 05:20:17 PM PDT 24
Peak memory 206100 kb
Host smart-d09f59e4-97d1-414e-ac5a-810bc0d67772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33645
74734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.3364574734
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2481317507
Short name T454
Test name
Test status
Simulation time 168050964 ps
CPU time 0.76 seconds
Started Jun 23 05:20:14 PM PDT 24
Finished Jun 23 05:20:16 PM PDT 24
Peak memory 206108 kb
Host smart-a221644b-4b29-416e-b64a-39db5be2d459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24813
17507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2481317507
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3342020497
Short name T1269
Test name
Test status
Simulation time 223464883 ps
CPU time 0.87 seconds
Started Jun 23 05:20:10 PM PDT 24
Finished Jun 23 05:20:12 PM PDT 24
Peak memory 205996 kb
Host smart-e74857c3-f61f-47a8-acc9-6b1b79ee5f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33420
20497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3342020497
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.422456755
Short name T1964
Test name
Test status
Simulation time 4642834183 ps
CPU time 134.43 seconds
Started Jun 23 05:20:14 PM PDT 24
Finished Jun 23 05:22:29 PM PDT 24
Peak memory 206376 kb
Host smart-af65e0ee-8e33-4c19-a370-7790b7c3e9df
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=422456755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.422456755
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1155363100
Short name T798
Test name
Test status
Simulation time 147551399 ps
CPU time 0.78 seconds
Started Jun 23 05:20:16 PM PDT 24
Finished Jun 23 05:20:18 PM PDT 24
Peak memory 206008 kb
Host smart-9e89077e-3232-4cfc-94bb-04ca1416e4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11553
63100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1155363100
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1886575301
Short name T591
Test name
Test status
Simulation time 154302977 ps
CPU time 0.79 seconds
Started Jun 23 05:20:19 PM PDT 24
Finished Jun 23 05:20:20 PM PDT 24
Peak memory 206016 kb
Host smart-1351c9a0-e4d0-4602-8316-cb4c80126a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18865
75301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1886575301
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3494994641
Short name T1759
Test name
Test status
Simulation time 4119969901 ps
CPU time 112.48 seconds
Started Jun 23 05:20:21 PM PDT 24
Finished Jun 23 05:22:14 PM PDT 24
Peak memory 206320 kb
Host smart-4b45f99a-d408-4db9-934d-3b14fa433dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34949
94641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3494994641
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.516958179
Short name T768
Test name
Test status
Simulation time 3722583843 ps
CPU time 4.62 seconds
Started Jun 23 05:20:20 PM PDT 24
Finished Jun 23 05:20:25 PM PDT 24
Peak memory 206128 kb
Host smart-588d6daa-7542-4794-9ab4-a1b8f9e8145b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=516958179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.516958179
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.1131117165
Short name T924
Test name
Test status
Simulation time 13384941297 ps
CPU time 15.43 seconds
Started Jun 23 05:20:20 PM PDT 24
Finished Jun 23 05:20:36 PM PDT 24
Peak memory 206188 kb
Host smart-95dc65af-8bb7-40f0-b666-2776c9f97315
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1131117165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.1131117165
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.3363448676
Short name T2346
Test name
Test status
Simulation time 23518609339 ps
CPU time 23.83 seconds
Started Jun 23 05:20:21 PM PDT 24
Finished Jun 23 05:20:45 PM PDT 24
Peak memory 206264 kb
Host smart-25143f2c-34f9-44a8-a717-d9ba7e5e52f3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3363448676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.3363448676
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2223984090
Short name T763
Test name
Test status
Simulation time 150100491 ps
CPU time 0.77 seconds
Started Jun 23 05:20:22 PM PDT 24
Finished Jun 23 05:20:23 PM PDT 24
Peak memory 206124 kb
Host smart-d269bf5d-300b-47e5-98b0-59acc7afebac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22239
84090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2223984090
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.3113872732
Short name T1554
Test name
Test status
Simulation time 141595831 ps
CPU time 0.73 seconds
Started Jun 23 05:20:26 PM PDT 24
Finished Jun 23 05:20:27 PM PDT 24
Peak memory 206044 kb
Host smart-2adfadca-d2f9-4294-9278-64f4c2412ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31138
72732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.3113872732
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3286311011
Short name T1232
Test name
Test status
Simulation time 150752122 ps
CPU time 0.8 seconds
Started Jun 23 05:20:27 PM PDT 24
Finished Jun 23 05:20:29 PM PDT 24
Peak memory 206100 kb
Host smart-690ef47b-7c72-4d43-a416-2557447ebd17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32863
11011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3286311011
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.3194261777
Short name T1661
Test name
Test status
Simulation time 978746559 ps
CPU time 2.45 seconds
Started Jun 23 05:20:18 PM PDT 24
Finished Jun 23 05:20:21 PM PDT 24
Peak memory 206328 kb
Host smart-8e019b09-5be5-4364-a7d5-c7157ec89c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31942
61777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3194261777
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.1850596470
Short name T1236
Test name
Test status
Simulation time 19516545414 ps
CPU time 35.7 seconds
Started Jun 23 05:20:21 PM PDT 24
Finished Jun 23 05:20:58 PM PDT 24
Peak memory 206240 kb
Host smart-24234201-974a-4799-bed2-ad4298b4f165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18505
96470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.1850596470
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.1724150233
Short name T1948
Test name
Test status
Simulation time 418069076 ps
CPU time 1.19 seconds
Started Jun 23 05:20:21 PM PDT 24
Finished Jun 23 05:20:23 PM PDT 24
Peak memory 206108 kb
Host smart-7aa6ee4f-971d-4b5e-9818-c1983b8e3400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17241
50233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.1724150233
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.129068057
Short name T519
Test name
Test status
Simulation time 138000058 ps
CPU time 0.83 seconds
Started Jun 23 05:20:20 PM PDT 24
Finished Jun 23 05:20:22 PM PDT 24
Peak memory 206100 kb
Host smart-86787d28-42d9-4798-b89f-e1cd49128535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12906
8057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.129068057
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1775847286
Short name T340
Test name
Test status
Simulation time 38224605 ps
CPU time 0.68 seconds
Started Jun 23 05:20:26 PM PDT 24
Finished Jun 23 05:20:27 PM PDT 24
Peak memory 206008 kb
Host smart-6389162c-28fc-450e-bb90-b0137f36845f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17758
47286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1775847286
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.2617704739
Short name T2273
Test name
Test status
Simulation time 1086154720 ps
CPU time 2.41 seconds
Started Jun 23 05:20:21 PM PDT 24
Finished Jun 23 05:20:24 PM PDT 24
Peak memory 206336 kb
Host smart-dba9a71b-d4de-471e-873e-c083d64fa3f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26177
04739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.2617704739
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1246739872
Short name T180
Test name
Test status
Simulation time 169178950 ps
CPU time 1.68 seconds
Started Jun 23 05:20:20 PM PDT 24
Finished Jun 23 05:20:22 PM PDT 24
Peak memory 206260 kb
Host smart-48aa6f52-d590-4e86-a079-a1e9d6beae44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12467
39872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1246739872
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.833947732
Short name T1003
Test name
Test status
Simulation time 228688481 ps
CPU time 0.86 seconds
Started Jun 23 05:20:31 PM PDT 24
Finished Jun 23 05:20:32 PM PDT 24
Peak memory 206108 kb
Host smart-149eb073-1d10-4850-9a4b-2a6c87cb5487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83394
7732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.833947732
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1278793642
Short name T390
Test name
Test status
Simulation time 135670165 ps
CPU time 0.75 seconds
Started Jun 23 05:20:31 PM PDT 24
Finished Jun 23 05:20:33 PM PDT 24
Peak memory 206096 kb
Host smart-bcdd37ff-1f7a-4e72-9f19-5f209270fd4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12787
93642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1278793642
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3682492130
Short name T770
Test name
Test status
Simulation time 249716372 ps
CPU time 1.02 seconds
Started Jun 23 05:20:21 PM PDT 24
Finished Jun 23 05:20:23 PM PDT 24
Peak memory 206104 kb
Host smart-0fd0ac03-ed7a-4b07-9b90-857984446cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36824
92130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3682492130
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.707107946
Short name T1453
Test name
Test status
Simulation time 5662933509 ps
CPU time 153.2 seconds
Started Jun 23 05:20:20 PM PDT 24
Finished Jun 23 05:22:54 PM PDT 24
Peak memory 206368 kb
Host smart-7417bd5b-053c-45a1-aa30-dffd5780a28b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=707107946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.707107946
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.2103980502
Short name T2194
Test name
Test status
Simulation time 224357612 ps
CPU time 0.89 seconds
Started Jun 23 05:20:21 PM PDT 24
Finished Jun 23 05:20:23 PM PDT 24
Peak memory 206220 kb
Host smart-b823419f-0481-46d6-a317-7cc111a87c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21039
80502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.2103980502
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.2003395276
Short name T2196
Test name
Test status
Simulation time 23283733617 ps
CPU time 22.35 seconds
Started Jun 23 05:20:20 PM PDT 24
Finished Jun 23 05:20:43 PM PDT 24
Peak memory 206348 kb
Host smart-f92b131e-ffe0-47ef-afb9-1770045659d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20033
95276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.2003395276
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3526549142
Short name T336
Test name
Test status
Simulation time 3353084865 ps
CPU time 4.22 seconds
Started Jun 23 05:20:20 PM PDT 24
Finished Jun 23 05:20:25 PM PDT 24
Peak memory 206128 kb
Host smart-faa02482-c8c1-4777-8aee-8e50a86137ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35265
49142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3526549142
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.2100494504
Short name T296
Test name
Test status
Simulation time 13072749486 ps
CPU time 93.3 seconds
Started Jun 23 05:20:24 PM PDT 24
Finished Jun 23 05:21:57 PM PDT 24
Peak memory 206312 kb
Host smart-2e4419c8-6afe-400e-898e-372b2baad6c3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2100494504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.2100494504
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1980515020
Short name T2027
Test name
Test status
Simulation time 255936048 ps
CPU time 0.89 seconds
Started Jun 23 05:20:30 PM PDT 24
Finished Jun 23 05:20:31 PM PDT 24
Peak memory 205468 kb
Host smart-0ee60cc9-1980-4bbc-9468-52b3443f1489
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1980515020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1980515020
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1189539569
Short name T654
Test name
Test status
Simulation time 186516768 ps
CPU time 0.86 seconds
Started Jun 23 05:20:26 PM PDT 24
Finished Jun 23 05:20:27 PM PDT 24
Peak memory 206060 kb
Host smart-7d96bed5-16c1-4792-b648-b817aa26496d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11895
39569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1189539569
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.1712956958
Short name T698
Test name
Test status
Simulation time 11415517437 ps
CPU time 298.49 seconds
Started Jun 23 05:20:32 PM PDT 24
Finished Jun 23 05:25:31 PM PDT 24
Peak memory 206328 kb
Host smart-9bb54497-acd4-445b-943d-a8c24022040c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17129
56958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.1712956958
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.1185660449
Short name T2329
Test name
Test status
Simulation time 3565226030 ps
CPU time 35.11 seconds
Started Jun 23 05:20:24 PM PDT 24
Finished Jun 23 05:20:59 PM PDT 24
Peak memory 206284 kb
Host smart-6d779092-9ebc-44e7-8d7d-f06d754fcc91
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1185660449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.1185660449
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.3858252049
Short name T339
Test name
Test status
Simulation time 160911567 ps
CPU time 0.86 seconds
Started Jun 23 05:20:29 PM PDT 24
Finished Jun 23 05:20:30 PM PDT 24
Peak memory 206128 kb
Host smart-e5502855-7cae-4b6e-b432-2f1f662e4567
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3858252049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.3858252049
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.436916976
Short name T2461
Test name
Test status
Simulation time 140577939 ps
CPU time 0.77 seconds
Started Jun 23 05:20:19 PM PDT 24
Finished Jun 23 05:20:20 PM PDT 24
Peak memory 206128 kb
Host smart-5fdc272c-a722-45fa-a15b-8459bc9fa166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43691
6976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.436916976
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2966057202
Short name T128
Test name
Test status
Simulation time 223986003 ps
CPU time 0.84 seconds
Started Jun 23 05:20:24 PM PDT 24
Finished Jun 23 05:20:25 PM PDT 24
Peak memory 206104 kb
Host smart-c85f4879-0067-4584-80a0-0e40a3baf6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29660
57202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2966057202
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.297585393
Short name T2074
Test name
Test status
Simulation time 196985662 ps
CPU time 0.89 seconds
Started Jun 23 05:20:24 PM PDT 24
Finished Jun 23 05:20:26 PM PDT 24
Peak memory 206060 kb
Host smart-8251c3b0-f8aa-45e4-90b1-09749e0043a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29758
5393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.297585393
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3019758218
Short name T1697
Test name
Test status
Simulation time 168977998 ps
CPU time 0.8 seconds
Started Jun 23 05:20:29 PM PDT 24
Finished Jun 23 05:20:30 PM PDT 24
Peak memory 206104 kb
Host smart-4c22131f-03d3-447b-87bd-d4a9da2c1314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30197
58218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3019758218
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.263912014
Short name T658
Test name
Test status
Simulation time 169064705 ps
CPU time 0.86 seconds
Started Jun 23 05:20:24 PM PDT 24
Finished Jun 23 05:20:26 PM PDT 24
Peak memory 206104 kb
Host smart-13c57b74-e04f-47fc-ad46-d6d49c1b2fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26391
2014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.263912014
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.221255248
Short name T1445
Test name
Test status
Simulation time 209828928 ps
CPU time 0.81 seconds
Started Jun 23 05:20:31 PM PDT 24
Finished Jun 23 05:20:33 PM PDT 24
Peak memory 206104 kb
Host smart-156969c7-a7c7-4576-8181-3cbce41aac75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22125
5248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.221255248
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.4242751754
Short name T1695
Test name
Test status
Simulation time 283481272 ps
CPU time 0.96 seconds
Started Jun 23 05:20:24 PM PDT 24
Finished Jun 23 05:20:25 PM PDT 24
Peak memory 206124 kb
Host smart-693571cc-e701-474a-8e0b-1815295ad730
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4242751754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.4242751754
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1147376181
Short name T794
Test name
Test status
Simulation time 173139573 ps
CPU time 0.79 seconds
Started Jun 23 05:20:26 PM PDT 24
Finished Jun 23 05:20:27 PM PDT 24
Peak memory 206124 kb
Host smart-26a94861-5389-4730-a3fb-40665d8fae35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11473
76181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1147376181
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.293735503
Short name T1764
Test name
Test status
Simulation time 46040138 ps
CPU time 0.68 seconds
Started Jun 23 05:20:25 PM PDT 24
Finished Jun 23 05:20:26 PM PDT 24
Peak memory 206112 kb
Host smart-145a2549-9d7c-4847-867a-0699bc296934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29373
5503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.293735503
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2052659072
Short name T226
Test name
Test status
Simulation time 20684197833 ps
CPU time 52.77 seconds
Started Jun 23 05:20:27 PM PDT 24
Finished Jun 23 05:21:20 PM PDT 24
Peak memory 206312 kb
Host smart-3326ed62-7e40-4578-a16c-4f09b2f76b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20526
59072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2052659072
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1226199251
Short name T1422
Test name
Test status
Simulation time 166842933 ps
CPU time 0.85 seconds
Started Jun 23 05:20:25 PM PDT 24
Finished Jun 23 05:20:26 PM PDT 24
Peak memory 206072 kb
Host smart-8740b1c0-5346-414a-953e-5de1b0d02f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12261
99251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1226199251
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1779631927
Short name T986
Test name
Test status
Simulation time 188161478 ps
CPU time 0.82 seconds
Started Jun 23 05:20:25 PM PDT 24
Finished Jun 23 05:20:26 PM PDT 24
Peak memory 206248 kb
Host smart-c2ec942b-a87c-4fc6-90f9-c4bcee6f6fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17796
31927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1779631927
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.4078619521
Short name T1394
Test name
Test status
Simulation time 182298984 ps
CPU time 0.86 seconds
Started Jun 23 05:20:32 PM PDT 24
Finished Jun 23 05:20:34 PM PDT 24
Peak memory 206108 kb
Host smart-8f4ccad1-2c1e-44c8-91cb-d73c1ed4f58e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40786
19521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.4078619521
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1107470614
Short name T2221
Test name
Test status
Simulation time 181360052 ps
CPU time 0.83 seconds
Started Jun 23 05:20:24 PM PDT 24
Finished Jun 23 05:20:25 PM PDT 24
Peak memory 206080 kb
Host smart-0b25a18a-e358-4344-ad6e-d6f8e711d834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11074
70614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1107470614
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.3106276691
Short name T2080
Test name
Test status
Simulation time 154362261 ps
CPU time 0.77 seconds
Started Jun 23 05:20:29 PM PDT 24
Finished Jun 23 05:20:30 PM PDT 24
Peak memory 206096 kb
Host smart-b28cdf99-abb7-4b1c-bf32-921287a13343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31062
76691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.3106276691
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.4043993117
Short name T1918
Test name
Test status
Simulation time 162044194 ps
CPU time 0.8 seconds
Started Jun 23 05:20:31 PM PDT 24
Finished Jun 23 05:20:33 PM PDT 24
Peak memory 206096 kb
Host smart-0fe53f48-1e9d-4d49-9ef3-bf383faac6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40439
93117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.4043993117
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2406438092
Short name T855
Test name
Test status
Simulation time 165701734 ps
CPU time 0.79 seconds
Started Jun 23 05:20:23 PM PDT 24
Finished Jun 23 05:20:24 PM PDT 24
Peak memory 206104 kb
Host smart-30163ba2-181e-4ebb-b861-94dd6b3b2808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24064
38092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2406438092
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.556974635
Short name T2053
Test name
Test status
Simulation time 276287938 ps
CPU time 0.95 seconds
Started Jun 23 05:20:19 PM PDT 24
Finished Jun 23 05:20:21 PM PDT 24
Peak memory 206100 kb
Host smart-2bf4c45a-58c2-4eee-9346-fe1337484100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55697
4635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.556974635
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.502216852
Short name T1709
Test name
Test status
Simulation time 7676588648 ps
CPU time 74.72 seconds
Started Jun 23 05:20:26 PM PDT 24
Finished Jun 23 05:21:41 PM PDT 24
Peak memory 206264 kb
Host smart-eb23c8e4-7ec4-4fc9-bb8e-241ae31a20a2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=502216852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.502216852
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.420731704
Short name T2285
Test name
Test status
Simulation time 180039471 ps
CPU time 0.82 seconds
Started Jun 23 05:20:26 PM PDT 24
Finished Jun 23 05:20:27 PM PDT 24
Peak memory 206012 kb
Host smart-361e1ae7-4269-4de8-b777-80a533f89f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42073
1704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.420731704
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.493128179
Short name T921
Test name
Test status
Simulation time 235102055 ps
CPU time 0.85 seconds
Started Jun 23 05:20:25 PM PDT 24
Finished Jun 23 05:20:26 PM PDT 24
Peak memory 206096 kb
Host smart-4eab9534-88c8-4f34-bd4b-5b051e60fef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49312
8179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.493128179
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.2795785574
Short name T835
Test name
Test status
Simulation time 3654375449 ps
CPU time 24.94 seconds
Started Jun 23 05:20:30 PM PDT 24
Finished Jun 23 05:20:55 PM PDT 24
Peak memory 206340 kb
Host smart-b6c2e743-5dba-4fb1-bd37-921c729fa5af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27957
85574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.2795785574
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.1201909768
Short name T1502
Test name
Test status
Simulation time 3847737895 ps
CPU time 4.49 seconds
Started Jun 23 05:15:21 PM PDT 24
Finished Jun 23 05:15:26 PM PDT 24
Peak memory 206288 kb
Host smart-1a949126-af46-4e32-a127-b6e1a8f45e2a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1201909768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.1201909768
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.4008420712
Short name T967
Test name
Test status
Simulation time 13350331101 ps
CPU time 15.07 seconds
Started Jun 23 05:15:22 PM PDT 24
Finished Jun 23 05:15:37 PM PDT 24
Peak memory 206280 kb
Host smart-00a8ebe6-c2e7-4103-842c-fabef257c98f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4008420712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.4008420712
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.3006629683
Short name T615
Test name
Test status
Simulation time 23354681977 ps
CPU time 22.39 seconds
Started Jun 23 05:15:26 PM PDT 24
Finished Jun 23 05:15:49 PM PDT 24
Peak memory 206164 kb
Host smart-b2beafdc-bb69-4ffd-8550-9f6b7a1fee9a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3006629683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.3006629683
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1762653381
Short name T850
Test name
Test status
Simulation time 156574752 ps
CPU time 0.77 seconds
Started Jun 23 05:15:22 PM PDT 24
Finished Jun 23 05:15:23 PM PDT 24
Peak memory 206016 kb
Host smart-de22443d-7e48-4e0b-a178-79289fb66902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17626
53381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1762653381
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.3451736708
Short name T2173
Test name
Test status
Simulation time 156217746 ps
CPU time 0.8 seconds
Started Jun 23 05:15:22 PM PDT 24
Finished Jun 23 05:15:23 PM PDT 24
Peak memory 206088 kb
Host smart-85135ac0-4a15-49de-a8d1-d6b0ee3f4a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34517
36708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.3451736708
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.4123890846
Short name T803
Test name
Test status
Simulation time 168118550 ps
CPU time 0.77 seconds
Started Jun 23 05:15:22 PM PDT 24
Finished Jun 23 05:15:23 PM PDT 24
Peak memory 206056 kb
Host smart-64965dc9-4fc2-4b94-b6e9-6b560e9928fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41238
90846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.4123890846
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.4065587728
Short name T2135
Test name
Test status
Simulation time 557527042 ps
CPU time 1.65 seconds
Started Jun 23 05:15:27 PM PDT 24
Finished Jun 23 05:15:29 PM PDT 24
Peak memory 206332 kb
Host smart-c7ba4183-995e-4bf4-b629-c79e2eb0560d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40655
87728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.4065587728
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3937946071
Short name T1316
Test name
Test status
Simulation time 337529280 ps
CPU time 1.06 seconds
Started Jun 23 05:15:27 PM PDT 24
Finished Jun 23 05:15:28 PM PDT 24
Peak memory 206060 kb
Host smart-905625ac-2473-48fe-924d-a7161c4ecaf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39379
46071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3937946071
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.282068609
Short name T148
Test name
Test status
Simulation time 10222816529 ps
CPU time 19.57 seconds
Started Jun 23 05:15:26 PM PDT 24
Finished Jun 23 05:15:46 PM PDT 24
Peak memory 206276 kb
Host smart-86261381-26aa-4e16-b5cd-d634e7e52b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28206
8609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.282068609
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.3344953065
Short name T1905
Test name
Test status
Simulation time 381079439 ps
CPU time 1.19 seconds
Started Jun 23 05:15:32 PM PDT 24
Finished Jun 23 05:15:33 PM PDT 24
Peak memory 206044 kb
Host smart-bfe9f3a8-4c85-43b7-a0d4-a00d415731d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33449
53065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3344953065
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.3092570684
Short name T1302
Test name
Test status
Simulation time 203386510 ps
CPU time 0.83 seconds
Started Jun 23 05:15:29 PM PDT 24
Finished Jun 23 05:15:30 PM PDT 24
Peak memory 206104 kb
Host smart-56b365a5-9228-4066-8dca-f7391acb51bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30925
70684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.3092570684
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1001334658
Short name T1669
Test name
Test status
Simulation time 31125889 ps
CPU time 0.67 seconds
Started Jun 23 05:15:27 PM PDT 24
Finished Jun 23 05:15:28 PM PDT 24
Peak memory 206100 kb
Host smart-ffd2fa97-947c-4f64-a448-429362f8e8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10013
34658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1001334658
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3177594141
Short name T784
Test name
Test status
Simulation time 806624210 ps
CPU time 2.18 seconds
Started Jun 23 05:15:29 PM PDT 24
Finished Jun 23 05:15:31 PM PDT 24
Peak memory 206340 kb
Host smart-b775b8b0-3e43-4c9c-b34f-f8662657ba9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31775
94141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3177594141
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.2753937431
Short name T1773
Test name
Test status
Simulation time 178969795 ps
CPU time 1.9 seconds
Started Jun 23 05:15:27 PM PDT 24
Finished Jun 23 05:15:30 PM PDT 24
Peak memory 206324 kb
Host smart-b79382e5-359f-481c-a069-1f3ada7e5667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27539
37431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.2753937431
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.2920318526
Short name T2056
Test name
Test status
Simulation time 204256929 ps
CPU time 0.88 seconds
Started Jun 23 05:15:38 PM PDT 24
Finished Jun 23 05:15:40 PM PDT 24
Peak memory 205992 kb
Host smart-c083c85f-3a60-46b6-bea9-cb9be5979c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29203
18526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.2920318526
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2720019414
Short name T2036
Test name
Test status
Simulation time 173393021 ps
CPU time 0.78 seconds
Started Jun 23 05:15:40 PM PDT 24
Finished Jun 23 05:15:41 PM PDT 24
Peak memory 206040 kb
Host smart-9fbaeb2f-b0dc-4752-a117-31acbe7c437e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27200
19414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2720019414
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2938554802
Short name T1980
Test name
Test status
Simulation time 249496641 ps
CPU time 0.9 seconds
Started Jun 23 05:15:35 PM PDT 24
Finished Jun 23 05:15:36 PM PDT 24
Peak memory 205880 kb
Host smart-0514d21b-a0dc-483e-aa0c-68fe23d430de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29385
54802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2938554802
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.2469470418
Short name T724
Test name
Test status
Simulation time 189480496 ps
CPU time 0.88 seconds
Started Jun 23 05:15:32 PM PDT 24
Finished Jun 23 05:15:33 PM PDT 24
Peak memory 206036 kb
Host smart-a1c206d1-5c12-4c80-aa80-b1c5e0055b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24694
70418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.2469470418
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.2568383237
Short name T693
Test name
Test status
Simulation time 23278614476 ps
CPU time 22.77 seconds
Started Jun 23 05:15:28 PM PDT 24
Finished Jun 23 05:15:51 PM PDT 24
Peak memory 206068 kb
Host smart-dd0ec6e3-33da-4cd8-835d-b9171f28f7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25683
83237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.2568383237
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.646051658
Short name T560
Test name
Test status
Simulation time 3342236436 ps
CPU time 3.83 seconds
Started Jun 23 05:15:26 PM PDT 24
Finished Jun 23 05:15:30 PM PDT 24
Peak memory 206092 kb
Host smart-80e10a94-ff1c-4ac2-9e2f-c50542aa0562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64605
1658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.646051658
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.988003998
Short name T2475
Test name
Test status
Simulation time 9387287050 ps
CPU time 246.69 seconds
Started Jun 23 05:15:35 PM PDT 24
Finished Jun 23 05:19:42 PM PDT 24
Peak memory 206124 kb
Host smart-68937552-0c43-4b3b-9ffe-62f672dc2a16
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=988003998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.988003998
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.2921040082
Short name T2136
Test name
Test status
Simulation time 321420270 ps
CPU time 0.94 seconds
Started Jun 23 05:15:37 PM PDT 24
Finished Jun 23 05:15:38 PM PDT 24
Peak memory 206128 kb
Host smart-ea7ca2ca-0ae7-4a1d-bbe8-0f2e87e11754
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2921040082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.2921040082
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2055117080
Short name T926
Test name
Test status
Simulation time 190793693 ps
CPU time 0.84 seconds
Started Jun 23 05:15:36 PM PDT 24
Finished Jun 23 05:15:38 PM PDT 24
Peak memory 205816 kb
Host smart-de8e93b0-10e8-4614-9ff3-58cac0002abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20551
17080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2055117080
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.592425603
Short name T1207
Test name
Test status
Simulation time 7625064691 ps
CPU time 74.83 seconds
Started Jun 23 05:15:32 PM PDT 24
Finished Jun 23 05:16:47 PM PDT 24
Peak memory 206284 kb
Host smart-c2f95aac-4967-4b71-bcb0-03691fc245b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59242
5603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.592425603
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.4274371265
Short name T1815
Test name
Test status
Simulation time 4954181595 ps
CPU time 47.25 seconds
Started Jun 23 05:15:28 PM PDT 24
Finished Jun 23 05:16:16 PM PDT 24
Peak memory 206292 kb
Host smart-4d73cf51-298a-41be-af64-b9bb68d57959
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4274371265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.4274371265
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3326818166
Short name T2269
Test name
Test status
Simulation time 171821402 ps
CPU time 0.81 seconds
Started Jun 23 05:15:37 PM PDT 24
Finished Jun 23 05:15:39 PM PDT 24
Peak memory 206128 kb
Host smart-7cbab401-9fab-427a-9ebb-3ca7488c822d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3326818166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3326818166
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2959572984
Short name T2048
Test name
Test status
Simulation time 152063543 ps
CPU time 0.8 seconds
Started Jun 23 05:15:28 PM PDT 24
Finished Jun 23 05:15:29 PM PDT 24
Peak memory 206100 kb
Host smart-f5ab61a9-ef21-4059-a81d-a8d0ee18e4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29595
72984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2959572984
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2439801944
Short name T542
Test name
Test status
Simulation time 158193163 ps
CPU time 0.79 seconds
Started Jun 23 05:15:35 PM PDT 24
Finished Jun 23 05:15:36 PM PDT 24
Peak memory 205872 kb
Host smart-1b5ac3dc-f447-4182-be36-8163949bbb94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24398
01944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2439801944
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3156130697
Short name T2088
Test name
Test status
Simulation time 160000782 ps
CPU time 0.77 seconds
Started Jun 23 05:15:26 PM PDT 24
Finished Jun 23 05:15:27 PM PDT 24
Peak memory 206108 kb
Host smart-0d572e43-ba69-4d60-866c-8c6056fface7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31561
30697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3156130697
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3211986660
Short name T471
Test name
Test status
Simulation time 156936638 ps
CPU time 0.76 seconds
Started Jun 23 05:15:36 PM PDT 24
Finished Jun 23 05:15:38 PM PDT 24
Peak memory 205788 kb
Host smart-1ee24494-0324-4104-a8eb-cc2c7ac99687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32119
86660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3211986660
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.726556954
Short name T2028
Test name
Test status
Simulation time 191275461 ps
CPU time 0.83 seconds
Started Jun 23 05:15:33 PM PDT 24
Finished Jun 23 05:15:34 PM PDT 24
Peak memory 206096 kb
Host smart-e7262671-0302-404e-a646-c3e6b7fbf80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72655
6954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.726556954
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.1449789450
Short name T503
Test name
Test status
Simulation time 211658248 ps
CPU time 0.96 seconds
Started Jun 23 05:15:33 PM PDT 24
Finished Jun 23 05:15:34 PM PDT 24
Peak memory 206144 kb
Host smart-72cec719-e13c-4243-9056-cc5548e2ec15
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1449789450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.1449789450
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2823776174
Short name T2325
Test name
Test status
Simulation time 145702572 ps
CPU time 0.79 seconds
Started Jun 23 05:15:34 PM PDT 24
Finished Jun 23 05:15:35 PM PDT 24
Peak memory 206120 kb
Host smart-66d7303e-2ea8-450c-81dc-2c5693af3eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28237
76174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2823776174
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1304905082
Short name T1110
Test name
Test status
Simulation time 39641193 ps
CPU time 0.7 seconds
Started Jun 23 05:15:35 PM PDT 24
Finished Jun 23 05:15:36 PM PDT 24
Peak memory 206116 kb
Host smart-16eaceff-42b1-4ca4-8e9a-f13fd35a09a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13049
05082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1304905082
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2574442501
Short name T1605
Test name
Test status
Simulation time 11823958663 ps
CPU time 24.98 seconds
Started Jun 23 05:15:27 PM PDT 24
Finished Jun 23 05:15:52 PM PDT 24
Peak memory 206296 kb
Host smart-b8c723c6-7357-437e-8947-28e1fd80c124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25744
42501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2574442501
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1081260658
Short name T1088
Test name
Test status
Simulation time 150515141 ps
CPU time 0.76 seconds
Started Jun 23 05:15:31 PM PDT 24
Finished Jun 23 05:15:33 PM PDT 24
Peak memory 206048 kb
Host smart-c81e0b7f-f270-4db1-9cc4-41737af88ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10812
60658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1081260658
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.582661706
Short name T1460
Test name
Test status
Simulation time 204358883 ps
CPU time 0.88 seconds
Started Jun 23 05:15:26 PM PDT 24
Finished Jun 23 05:15:28 PM PDT 24
Peak memory 206120 kb
Host smart-ce916d3c-374a-41a4-9e62-97e5c3154e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58266
1706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.582661706
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.2786984043
Short name T1919
Test name
Test status
Simulation time 17564025688 ps
CPU time 96.63 seconds
Started Jun 23 05:15:26 PM PDT 24
Finished Jun 23 05:17:03 PM PDT 24
Peak memory 206404 kb
Host smart-8de17547-9bfc-49de-b25d-16a0a0e0609c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2786984043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.2786984043
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.3884505403
Short name T153
Test name
Test status
Simulation time 13344159430 ps
CPU time 87.63 seconds
Started Jun 23 05:15:27 PM PDT 24
Finished Jun 23 05:16:55 PM PDT 24
Peak memory 206256 kb
Host smart-4d78a8ce-9952-4f1c-890c-c584493cb2ee
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3884505403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.3884505403
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.125100020
Short name T1131
Test name
Test status
Simulation time 18785276772 ps
CPU time 432.07 seconds
Started Jun 23 05:15:33 PM PDT 24
Finished Jun 23 05:22:46 PM PDT 24
Peak memory 206316 kb
Host smart-d2c9e5e2-8abb-43a6-84ee-44b76d662c03
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=125100020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.125100020
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.260685516
Short name T287
Test name
Test status
Simulation time 196863367 ps
CPU time 0.83 seconds
Started Jun 23 05:15:37 PM PDT 24
Finished Jun 23 05:15:38 PM PDT 24
Peak memory 206100 kb
Host smart-dcb01199-335e-4178-a31d-a20fd37fc19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26068
5516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.260685516
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.3402620303
Short name T1492
Test name
Test status
Simulation time 159845586 ps
CPU time 0.79 seconds
Started Jun 23 05:15:31 PM PDT 24
Finished Jun 23 05:15:33 PM PDT 24
Peak memory 206112 kb
Host smart-d1f8b402-536c-4654-acff-87ffe3fc79b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34026
20303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.3402620303
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3232855624
Short name T1362
Test name
Test status
Simulation time 153165154 ps
CPU time 0.77 seconds
Started Jun 23 05:15:33 PM PDT 24
Finished Jun 23 05:15:34 PM PDT 24
Peak memory 206056 kb
Host smart-efae26aa-ad15-412f-bcd8-b75bfcbb2597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32328
55624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3232855624
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1326065730
Short name T187
Test name
Test status
Simulation time 432697998 ps
CPU time 1.25 seconds
Started Jun 23 05:15:38 PM PDT 24
Finished Jun 23 05:15:40 PM PDT 24
Peak memory 223888 kb
Host smart-41faebab-17b0-482b-a0be-5ee8f1ffc115
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1326065730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1326065730
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.1027706621
Short name T2206
Test name
Test status
Simulation time 359986916 ps
CPU time 1.24 seconds
Started Jun 23 05:15:36 PM PDT 24
Finished Jun 23 05:15:37 PM PDT 24
Peak memory 206080 kb
Host smart-9761b9c1-33f7-433e-a261-d74bd4e817ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10277
06621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.1027706621
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2509809500
Short name T2011
Test name
Test status
Simulation time 186178872 ps
CPU time 0.88 seconds
Started Jun 23 05:15:32 PM PDT 24
Finished Jun 23 05:15:33 PM PDT 24
Peak memory 206088 kb
Host smart-8d2ef76c-6927-43dc-8d0a-75dc58e315d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25098
09500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2509809500
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1431897358
Short name T1702
Test name
Test status
Simulation time 162513485 ps
CPU time 0.77 seconds
Started Jun 23 05:15:32 PM PDT 24
Finished Jun 23 05:15:33 PM PDT 24
Peak memory 206052 kb
Host smart-2e65684a-5cdf-4317-ae06-9af49a1a6db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14318
97358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1431897358
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1576247281
Short name T485
Test name
Test status
Simulation time 286726565 ps
CPU time 1.08 seconds
Started Jun 23 05:15:26 PM PDT 24
Finished Jun 23 05:15:28 PM PDT 24
Peak memory 206108 kb
Host smart-84534df2-2177-4118-86fe-43e40ea229cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15762
47281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1576247281
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.2215658851
Short name T1112
Test name
Test status
Simulation time 8983431793 ps
CPU time 86.24 seconds
Started Jun 23 05:15:32 PM PDT 24
Finished Jun 23 05:16:59 PM PDT 24
Peak memory 206276 kb
Host smart-08610bb3-153d-4df4-97e0-db747798912c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2215658851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.2215658851
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.1796079109
Short name T2272
Test name
Test status
Simulation time 203403906 ps
CPU time 0.88 seconds
Started Jun 23 05:15:34 PM PDT 24
Finished Jun 23 05:15:36 PM PDT 24
Peak memory 206012 kb
Host smart-7299e3f9-3127-4e41-832f-3b7191b17e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17960
79109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1796079109
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.1556681880
Short name T943
Test name
Test status
Simulation time 168333532 ps
CPU time 0.78 seconds
Started Jun 23 05:15:31 PM PDT 24
Finished Jun 23 05:15:33 PM PDT 24
Peak memory 206100 kb
Host smart-1312f722-f3e8-4886-b65e-926d6038a35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15566
81880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.1556681880
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2850031951
Short name T19
Test name
Test status
Simulation time 6701253836 ps
CPU time 188.6 seconds
Started Jun 23 05:15:33 PM PDT 24
Finished Jun 23 05:18:42 PM PDT 24
Peak memory 206328 kb
Host smart-e3c7623a-b1a2-4c73-bb68-93fbfdab46ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28500
31951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2850031951
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.2126868176
Short name T166
Test name
Test status
Simulation time 25827100647 ps
CPU time 239.17 seconds
Started Jun 23 05:15:31 PM PDT 24
Finished Jun 23 05:19:31 PM PDT 24
Peak memory 206416 kb
Host smart-43152b36-af74-401c-b304-e0605f1fd466
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2126868176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.2126868176
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3354466630
Short name T1407
Test name
Test status
Simulation time 4004758938 ps
CPU time 5 seconds
Started Jun 23 05:20:24 PM PDT 24
Finished Jun 23 05:20:30 PM PDT 24
Peak memory 206180 kb
Host smart-4fa9fef0-7441-4729-b3c4-f39b441c8d50
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3354466630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.3354466630
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2387638260
Short name T516
Test name
Test status
Simulation time 13536335399 ps
CPU time 16.61 seconds
Started Jun 23 05:20:25 PM PDT 24
Finished Jun 23 05:20:42 PM PDT 24
Peak memory 206396 kb
Host smart-1695554f-a404-4a29-90a7-49754e1a728b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2387638260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2387638260
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.4029929468
Short name T464
Test name
Test status
Simulation time 23346110075 ps
CPU time 20.8 seconds
Started Jun 23 05:20:26 PM PDT 24
Finished Jun 23 05:20:47 PM PDT 24
Peak memory 206320 kb
Host smart-2003a092-b5a8-499c-809b-b238c6b68259
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4029929468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.4029929468
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.3559834557
Short name T1065
Test name
Test status
Simulation time 178431446 ps
CPU time 0.81 seconds
Started Jun 23 05:20:31 PM PDT 24
Finished Jun 23 05:20:33 PM PDT 24
Peak memory 206092 kb
Host smart-2641d6af-48f0-48f0-9f1c-92a3592a2089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35598
34557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.3559834557
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.3628073840
Short name T203
Test name
Test status
Simulation time 187756571 ps
CPU time 0.8 seconds
Started Jun 23 05:20:31 PM PDT 24
Finished Jun 23 05:20:33 PM PDT 24
Peak memory 206104 kb
Host smart-3e2d2db3-c578-4ae1-bef1-144ab962bf4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36280
73840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.3628073840
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.1375236915
Short name T80
Test name
Test status
Simulation time 187034136 ps
CPU time 0.9 seconds
Started Jun 23 05:20:32 PM PDT 24
Finished Jun 23 05:20:34 PM PDT 24
Peak memory 206104 kb
Host smart-1aeddb0e-98e5-4ef6-8542-8a236a8f323c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13752
36915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.1375236915
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.1106402700
Short name T96
Test name
Test status
Simulation time 909145504 ps
CPU time 1.91 seconds
Started Jun 23 05:20:31 PM PDT 24
Finished Jun 23 05:20:34 PM PDT 24
Peak memory 206260 kb
Host smart-3576217e-bb3b-451a-85bb-b8457ec6f0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11064
02700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.1106402700
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.3713060599
Short name T1842
Test name
Test status
Simulation time 22141854138 ps
CPU time 39.56 seconds
Started Jun 23 05:20:33 PM PDT 24
Finished Jun 23 05:21:13 PM PDT 24
Peak memory 206352 kb
Host smart-9f5a3200-1c40-4cfa-a232-f773df59ccfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37130
60599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.3713060599
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.2783390753
Short name T725
Test name
Test status
Simulation time 421383089 ps
CPU time 1.28 seconds
Started Jun 23 05:20:33 PM PDT 24
Finished Jun 23 05:20:35 PM PDT 24
Peak memory 206116 kb
Host smart-d8e3cf6c-d5a4-4af9-81d6-e4dae23c19b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27833
90753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.2783390753
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.2735507170
Short name T398
Test name
Test status
Simulation time 136835144 ps
CPU time 0.71 seconds
Started Jun 23 05:20:31 PM PDT 24
Finished Jun 23 05:20:33 PM PDT 24
Peak memory 206100 kb
Host smart-691585e2-cb4e-472b-a06d-608d21c83576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27355
07170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2735507170
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2088271901
Short name T1581
Test name
Test status
Simulation time 47997616 ps
CPU time 0.66 seconds
Started Jun 23 05:20:32 PM PDT 24
Finished Jun 23 05:20:34 PM PDT 24
Peak memory 206112 kb
Host smart-15599802-b027-4bb1-9e26-b3ec6ac660eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20882
71901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2088271901
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3501917494
Short name T345
Test name
Test status
Simulation time 1115364775 ps
CPU time 2.54 seconds
Started Jun 23 05:20:31 PM PDT 24
Finished Jun 23 05:20:34 PM PDT 24
Peak memory 206260 kb
Host smart-8071cf48-9639-4044-b7fa-2b3cc672b2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35019
17494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3501917494
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2468580005
Short name T2018
Test name
Test status
Simulation time 194400627 ps
CPU time 1.48 seconds
Started Jun 23 05:20:33 PM PDT 24
Finished Jun 23 05:20:36 PM PDT 24
Peak memory 206256 kb
Host smart-9da8cac3-ba11-400d-bfcf-a444ccdda227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24685
80005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2468580005
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.86555013
Short name T486
Test name
Test status
Simulation time 220949041 ps
CPU time 0.9 seconds
Started Jun 23 05:20:44 PM PDT 24
Finished Jun 23 05:20:46 PM PDT 24
Peak memory 206040 kb
Host smart-717fb795-323c-4d92-b26b-dc99fb4f0ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86555
013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.86555013
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2575758433
Short name T2404
Test name
Test status
Simulation time 163895157 ps
CPU time 0.83 seconds
Started Jun 23 05:20:37 PM PDT 24
Finished Jun 23 05:20:38 PM PDT 24
Peak memory 206100 kb
Host smart-c2db9435-aac8-4bf8-a9fd-7f242a65bfc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25757
58433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2575758433
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1427524612
Short name T1320
Test name
Test status
Simulation time 284580816 ps
CPU time 0.97 seconds
Started Jun 23 05:20:34 PM PDT 24
Finished Jun 23 05:20:36 PM PDT 24
Peak memory 206096 kb
Host smart-aae1ccb6-a689-4dc6-8375-43c88fe8b4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14275
24612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1427524612
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.2548448646
Short name T1726
Test name
Test status
Simulation time 10567385874 ps
CPU time 282.5 seconds
Started Jun 23 05:20:33 PM PDT 24
Finished Jun 23 05:25:16 PM PDT 24
Peak memory 206344 kb
Host smart-dc442d46-c918-4ca2-9aba-22e42371501e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2548448646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.2548448646
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1592153024
Short name T947
Test name
Test status
Simulation time 213278133 ps
CPU time 0.92 seconds
Started Jun 23 05:20:31 PM PDT 24
Finished Jun 23 05:20:32 PM PDT 24
Peak memory 206100 kb
Host smart-89ac7be6-7749-4fd2-856f-b98eaf8c8985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15921
53024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1592153024
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.1812419876
Short name T1123
Test name
Test status
Simulation time 23306607152 ps
CPU time 23.57 seconds
Started Jun 23 05:20:32 PM PDT 24
Finished Jun 23 05:20:57 PM PDT 24
Peak memory 206284 kb
Host smart-2e2faeb4-04a7-403f-a90f-7b7c5ab3d74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18124
19876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.1812419876
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3278451613
Short name T1019
Test name
Test status
Simulation time 3331324654 ps
CPU time 4.1 seconds
Started Jun 23 05:20:32 PM PDT 24
Finished Jun 23 05:20:37 PM PDT 24
Peak memory 206084 kb
Host smart-53e14bf0-8bd0-4c77-a495-078f976f2821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32784
51613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3278451613
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1341065281
Short name T609
Test name
Test status
Simulation time 3016065138 ps
CPU time 75.25 seconds
Started Jun 23 05:20:33 PM PDT 24
Finished Jun 23 05:21:49 PM PDT 24
Peak memory 206348 kb
Host smart-0bd3d186-34a7-44c9-ba9e-4eed764d36b9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1341065281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1341065281
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.2310841518
Short name T290
Test name
Test status
Simulation time 268126664 ps
CPU time 0.95 seconds
Started Jun 23 05:20:45 PM PDT 24
Finished Jun 23 05:20:47 PM PDT 24
Peak memory 206128 kb
Host smart-0aa0db7c-a331-4259-8b17-550832fa96a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2310841518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.2310841518
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2895719922
Short name T585
Test name
Test status
Simulation time 189821963 ps
CPU time 0.86 seconds
Started Jun 23 05:20:32 PM PDT 24
Finished Jun 23 05:20:33 PM PDT 24
Peak memory 206120 kb
Host smart-f9f1668b-ff28-48ba-9a1b-180b693f0752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28957
19922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2895719922
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.2920442378
Short name T1540
Test name
Test status
Simulation time 9732555973 ps
CPU time 88.86 seconds
Started Jun 23 05:20:31 PM PDT 24
Finished Jun 23 05:22:01 PM PDT 24
Peak memory 206328 kb
Host smart-e5fa79eb-2b43-47e7-a750-c02042fbc48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29204
42378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.2920442378
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.1519471880
Short name T2342
Test name
Test status
Simulation time 9695177267 ps
CPU time 275.9 seconds
Started Jun 23 05:20:32 PM PDT 24
Finished Jun 23 05:25:09 PM PDT 24
Peak memory 206352 kb
Host smart-ec76ae8e-a091-498e-833e-6b396b17d5d8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1519471880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.1519471880
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.3670512727
Short name T1854
Test name
Test status
Simulation time 160982310 ps
CPU time 0.85 seconds
Started Jun 23 05:20:45 PM PDT 24
Finished Jun 23 05:20:47 PM PDT 24
Peak memory 206128 kb
Host smart-a3a8edeb-8f9f-4d13-8432-605d9ff3788a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3670512727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.3670512727
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.451026714
Short name T2312
Test name
Test status
Simulation time 143810713 ps
CPU time 0.8 seconds
Started Jun 23 05:20:33 PM PDT 24
Finished Jun 23 05:20:35 PM PDT 24
Peak memory 206128 kb
Host smart-d511ba67-5355-4610-8b1c-3dd110202498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45102
6714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.451026714
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1925409997
Short name T1555
Test name
Test status
Simulation time 186473339 ps
CPU time 0.79 seconds
Started Jun 23 05:20:30 PM PDT 24
Finished Jun 23 05:20:31 PM PDT 24
Peak memory 205988 kb
Host smart-8c49bfe1-d0b7-40a6-91fa-8c6468c4336c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19254
09997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1925409997
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.2990817719
Short name T1667
Test name
Test status
Simulation time 190141689 ps
CPU time 0.91 seconds
Started Jun 23 05:20:32 PM PDT 24
Finished Jun 23 05:20:33 PM PDT 24
Peak memory 206096 kb
Host smart-6974ea5d-006d-4e9b-8686-5c93263f9079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29908
17719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.2990817719
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.361683477
Short name T1586
Test name
Test status
Simulation time 177740382 ps
CPU time 0.83 seconds
Started Jun 23 05:20:32 PM PDT 24
Finished Jun 23 05:20:33 PM PDT 24
Peak memory 206016 kb
Host smart-9002cc08-a122-4cbb-8835-4cf0799f5719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36168
3477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.361683477
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2145064927
Short name T1111
Test name
Test status
Simulation time 173344764 ps
CPU time 0.86 seconds
Started Jun 23 05:20:38 PM PDT 24
Finished Jun 23 05:20:39 PM PDT 24
Peak memory 206132 kb
Host smart-bd826820-131f-4259-b98d-ce1a50b4f6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21450
64927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2145064927
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.1474940990
Short name T666
Test name
Test status
Simulation time 156409273 ps
CPU time 0.79 seconds
Started Jun 23 05:20:51 PM PDT 24
Finished Jun 23 05:20:53 PM PDT 24
Peak memory 206292 kb
Host smart-ab4cbbfa-dddb-491b-bf09-50206de90e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14749
40990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.1474940990
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.3603545828
Short name T810
Test name
Test status
Simulation time 226712590 ps
CPU time 0.97 seconds
Started Jun 23 05:20:45 PM PDT 24
Finished Jun 23 05:20:47 PM PDT 24
Peak memory 206144 kb
Host smart-f1008c59-ffc9-454e-afc6-9cf0aedb72a4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3603545828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.3603545828
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1508495245
Short name T1617
Test name
Test status
Simulation time 143228235 ps
CPU time 0.73 seconds
Started Jun 23 05:20:46 PM PDT 24
Finished Jun 23 05:20:48 PM PDT 24
Peak memory 206104 kb
Host smart-03a030d4-3251-4dac-b2b2-cec110624a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15084
95245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1508495245
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.621832721
Short name T1129
Test name
Test status
Simulation time 36411212 ps
CPU time 0.68 seconds
Started Jun 23 05:20:36 PM PDT 24
Finished Jun 23 05:20:37 PM PDT 24
Peak memory 206068 kb
Host smart-3c0de46b-b328-472d-92cb-424a92d6fae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62183
2721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.621832721
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2812019401
Short name T1168
Test name
Test status
Simulation time 8350792708 ps
CPU time 17.6 seconds
Started Jun 23 05:20:32 PM PDT 24
Finished Jun 23 05:20:51 PM PDT 24
Peak memory 206436 kb
Host smart-70fc8723-0bf0-403a-9856-b51903adf2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28120
19401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2812019401
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1476141143
Short name T1182
Test name
Test status
Simulation time 204879949 ps
CPU time 0.95 seconds
Started Jun 23 05:20:32 PM PDT 24
Finished Jun 23 05:20:34 PM PDT 24
Peak memory 206108 kb
Host smart-c97fa522-eaa3-414b-8d02-a75589d3367d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14761
41143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1476141143
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.284727380
Short name T1395
Test name
Test status
Simulation time 200350158 ps
CPU time 0.86 seconds
Started Jun 23 05:20:33 PM PDT 24
Finished Jun 23 05:20:35 PM PDT 24
Peak memory 206008 kb
Host smart-ec7d3ff3-c368-4f93-b6da-00c2531d3db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28472
7380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.284727380
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.4081782717
Short name T1146
Test name
Test status
Simulation time 232099734 ps
CPU time 0.95 seconds
Started Jun 23 05:20:44 PM PDT 24
Finished Jun 23 05:20:45 PM PDT 24
Peak memory 206108 kb
Host smart-dbfe0c61-34b6-45ec-98dc-5ca353fb1bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40817
82717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.4081782717
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.2208144485
Short name T1869
Test name
Test status
Simulation time 227734310 ps
CPU time 0.91 seconds
Started Jun 23 05:20:33 PM PDT 24
Finished Jun 23 05:20:35 PM PDT 24
Peak memory 206084 kb
Host smart-be006fa3-2df2-476a-b45f-3d7720514edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22081
44485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.2208144485
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3867230344
Short name T2424
Test name
Test status
Simulation time 206734459 ps
CPU time 0.79 seconds
Started Jun 23 05:20:43 PM PDT 24
Finished Jun 23 05:20:44 PM PDT 24
Peak memory 206092 kb
Host smart-e987e09e-f954-464e-bae7-f5fc61354ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38672
30344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3867230344
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2846209466
Short name T1737
Test name
Test status
Simulation time 147897137 ps
CPU time 0.81 seconds
Started Jun 23 05:20:46 PM PDT 24
Finished Jun 23 05:20:47 PM PDT 24
Peak memory 206024 kb
Host smart-09535fe8-9593-442e-87c7-32569481197b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28462
09466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2846209466
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.937358914
Short name T1620
Test name
Test status
Simulation time 163465676 ps
CPU time 0.78 seconds
Started Jun 23 05:20:43 PM PDT 24
Finished Jun 23 05:20:44 PM PDT 24
Peak memory 206004 kb
Host smart-335b34be-0603-45cf-8d64-787f7696cf77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93735
8914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.937358914
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3727734704
Short name T367
Test name
Test status
Simulation time 222984369 ps
CPU time 0.91 seconds
Started Jun 23 05:20:30 PM PDT 24
Finished Jun 23 05:20:31 PM PDT 24
Peak memory 205500 kb
Host smart-1c67387f-1b00-4d86-a024-74ee8c36e265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37277
34704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3727734704
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.3128853752
Short name T1101
Test name
Test status
Simulation time 4899588910 ps
CPU time 135.3 seconds
Started Jun 23 05:20:33 PM PDT 24
Finished Jun 23 05:22:49 PM PDT 24
Peak memory 206272 kb
Host smart-1c624a3a-0531-4759-a535-1fb8336df27f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3128853752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.3128853752
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1876404988
Short name T2407
Test name
Test status
Simulation time 160983284 ps
CPU time 0.75 seconds
Started Jun 23 05:20:39 PM PDT 24
Finished Jun 23 05:20:40 PM PDT 24
Peak memory 206032 kb
Host smart-3c2f49dc-7d59-4423-b49c-4aab120b9c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18764
04988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1876404988
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.1583668740
Short name T2148
Test name
Test status
Simulation time 181956374 ps
CPU time 0.83 seconds
Started Jun 23 05:20:37 PM PDT 24
Finished Jun 23 05:20:38 PM PDT 24
Peak memory 205996 kb
Host smart-f26a03bf-cd7b-4cba-8052-95c0e5fdf2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15836
68740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.1583668740
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.800870021
Short name T434
Test name
Test status
Simulation time 11295259529 ps
CPU time 104.17 seconds
Started Jun 23 05:20:36 PM PDT 24
Finished Jun 23 05:22:20 PM PDT 24
Peak memory 206328 kb
Host smart-8b29a9b3-4fec-41fa-8916-b006aa1c8c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80087
0021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.800870021
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3113328372
Short name T1162
Test name
Test status
Simulation time 4000897388 ps
CPU time 4.71 seconds
Started Jun 23 05:20:39 PM PDT 24
Finished Jun 23 05:20:44 PM PDT 24
Peak memory 206188 kb
Host smart-19970a4f-0350-46d7-b306-6d9cd0570e0c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3113328372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3113328372
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.1898542978
Short name T15
Test name
Test status
Simulation time 13314526334 ps
CPU time 15.98 seconds
Started Jun 23 05:20:49 PM PDT 24
Finished Jun 23 05:21:06 PM PDT 24
Peak memory 206172 kb
Host smart-33bb89b9-edee-4027-b1de-636bfa32ed43
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1898542978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.1898542978
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.2719897079
Short name T1693
Test name
Test status
Simulation time 23355484189 ps
CPU time 22.19 seconds
Started Jun 23 05:20:37 PM PDT 24
Finished Jun 23 05:20:59 PM PDT 24
Peak memory 206332 kb
Host smart-61627d5c-e011-46b3-be86-ee81571c4916
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2719897079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.2719897079
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2722211568
Short name T1306
Test name
Test status
Simulation time 218050620 ps
CPU time 0.85 seconds
Started Jun 23 05:20:43 PM PDT 24
Finished Jun 23 05:20:44 PM PDT 24
Peak memory 206104 kb
Host smart-50e9bce0-999d-48e3-bfd9-539a95084554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27222
11568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2722211568
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.175532059
Short name T1011
Test name
Test status
Simulation time 167053790 ps
CPU time 0.77 seconds
Started Jun 23 05:20:37 PM PDT 24
Finished Jun 23 05:20:38 PM PDT 24
Peak memory 206000 kb
Host smart-379f3ac6-cdbe-4b65-a89d-b991d2d5a520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17553
2059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.175532059
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.4294665853
Short name T1878
Test name
Test status
Simulation time 272362379 ps
CPU time 0.93 seconds
Started Jun 23 05:20:45 PM PDT 24
Finished Jun 23 05:20:47 PM PDT 24
Peak memory 206104 kb
Host smart-89b162de-75ec-4024-b0f8-1da5192cfedd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42946
65853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.4294665853
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.1520223036
Short name T939
Test name
Test status
Simulation time 713229842 ps
CPU time 1.89 seconds
Started Jun 23 05:20:45 PM PDT 24
Finished Jun 23 05:20:48 PM PDT 24
Peak memory 206216 kb
Host smart-b1b03e00-70ec-43d8-8e6c-435f40d51ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15202
23036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.1520223036
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.2779224104
Short name T938
Test name
Test status
Simulation time 10816876256 ps
CPU time 19.4 seconds
Started Jun 23 05:20:35 PM PDT 24
Finished Jun 23 05:20:55 PM PDT 24
Peak memory 206400 kb
Host smart-348a0e74-6b42-420a-8120-66cd75199ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27792
24104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.2779224104
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.315420173
Short name T2310
Test name
Test status
Simulation time 498602997 ps
CPU time 1.47 seconds
Started Jun 23 05:20:38 PM PDT 24
Finished Jun 23 05:20:39 PM PDT 24
Peak memory 206108 kb
Host smart-67638377-c3a5-4891-8288-a6aac246c26f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31542
0173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.315420173
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.3957825986
Short name T877
Test name
Test status
Simulation time 184894417 ps
CPU time 0.8 seconds
Started Jun 23 05:20:36 PM PDT 24
Finished Jun 23 05:20:37 PM PDT 24
Peak memory 206096 kb
Host smart-7ef2d904-9b85-4416-982c-08b244606264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39578
25986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3957825986
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.2037350727
Short name T805
Test name
Test status
Simulation time 67529306 ps
CPU time 0.69 seconds
Started Jun 23 05:20:46 PM PDT 24
Finished Jun 23 05:20:47 PM PDT 24
Peak memory 206044 kb
Host smart-9ba4ab9d-60fa-4bef-aca5-cd99d3016c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20373
50727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2037350727
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3058852591
Short name T1560
Test name
Test status
Simulation time 1031583732 ps
CPU time 2.3 seconds
Started Jun 23 05:20:49 PM PDT 24
Finished Jun 23 05:20:52 PM PDT 24
Peak memory 206308 kb
Host smart-4d996ca2-80b9-4890-9151-a6804b2cea76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30588
52591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3058852591
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1333415781
Short name T1440
Test name
Test status
Simulation time 371833055 ps
CPU time 2.41 seconds
Started Jun 23 05:20:44 PM PDT 24
Finished Jun 23 05:20:47 PM PDT 24
Peak memory 206268 kb
Host smart-c2263015-5082-478e-8495-872af9cae4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13334
15781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1333415781
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.3488270907
Short name T2071
Test name
Test status
Simulation time 189413934 ps
CPU time 0.85 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:54 PM PDT 24
Peak memory 206096 kb
Host smart-cf7d1518-09bd-48bd-8984-b00c8ea6319d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34882
70907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.3488270907
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.633025106
Short name T320
Test name
Test status
Simulation time 205710864 ps
CPU time 0.82 seconds
Started Jun 23 05:20:50 PM PDT 24
Finished Jun 23 05:20:52 PM PDT 24
Peak memory 206088 kb
Host smart-7c8cae3c-3bb1-488a-8549-b8801fd105d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63302
5106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.633025106
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1690294817
Short name T2073
Test name
Test status
Simulation time 231828666 ps
CPU time 0.9 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:20:49 PM PDT 24
Peak memory 206104 kb
Host smart-757c5f23-a6e7-4c84-892e-fab587b3a890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16902
94817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1690294817
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.995239673
Short name T1388
Test name
Test status
Simulation time 201922654 ps
CPU time 0.91 seconds
Started Jun 23 05:20:46 PM PDT 24
Finished Jun 23 05:20:47 PM PDT 24
Peak memory 206104 kb
Host smart-6d51a45e-1d10-4adc-acd8-7c77bd427872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99523
9673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.995239673
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3950010965
Short name T2115
Test name
Test status
Simulation time 23327039935 ps
CPU time 23.64 seconds
Started Jun 23 05:20:46 PM PDT 24
Finished Jun 23 05:21:11 PM PDT 24
Peak memory 206152 kb
Host smart-491b5217-2044-402a-b81d-3d08bd39e237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39500
10965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3950010965
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2780745751
Short name T2372
Test name
Test status
Simulation time 3286038099 ps
CPU time 3.81 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:20:52 PM PDT 24
Peak memory 206164 kb
Host smart-a451b6f8-21bb-4674-93d5-7b6077866d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27807
45751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2780745751
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.902754048
Short name T607
Test name
Test status
Simulation time 6754631270 ps
CPU time 48.53 seconds
Started Jun 23 05:20:49 PM PDT 24
Finished Jun 23 05:21:38 PM PDT 24
Peak memory 206392 kb
Host smart-05abe65f-f892-494b-98c0-925744357c76
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=902754048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.902754048
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.3163140051
Short name T842
Test name
Test status
Simulation time 269783101 ps
CPU time 0.94 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:54 PM PDT 24
Peak memory 206128 kb
Host smart-82c67621-6d25-4b71-904b-140dd546a548
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3163140051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.3163140051
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1558919991
Short name T1998
Test name
Test status
Simulation time 184947211 ps
CPU time 0.84 seconds
Started Jun 23 05:20:44 PM PDT 24
Finished Jun 23 05:20:45 PM PDT 24
Peak memory 206116 kb
Host smart-a121afdd-e646-466a-ab0f-8e22a9c4d47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15589
19991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1558919991
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.1211154800
Short name T1434
Test name
Test status
Simulation time 6242549541 ps
CPU time 59.7 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:21:47 PM PDT 24
Peak memory 206360 kb
Host smart-e19ba18e-8047-4033-b6ca-3474d7dcf4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12111
54800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.1211154800
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.52852099
Short name T1685
Test name
Test status
Simulation time 6492831025 ps
CPU time 179.67 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:23:48 PM PDT 24
Peak memory 206256 kb
Host smart-daec07a7-42fd-47be-85f4-a12d441f2f3e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=52852099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.52852099
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.3977319356
Short name T1606
Test name
Test status
Simulation time 151537832 ps
CPU time 0.79 seconds
Started Jun 23 05:20:50 PM PDT 24
Finished Jun 23 05:20:52 PM PDT 24
Peak memory 206120 kb
Host smart-ebf43e32-136d-4a67-904f-82a4d715cc39
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3977319356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3977319356
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3839468226
Short name T2114
Test name
Test status
Simulation time 141374673 ps
CPU time 0.74 seconds
Started Jun 23 05:20:51 PM PDT 24
Finished Jun 23 05:20:52 PM PDT 24
Peak memory 206300 kb
Host smart-eea9b6cb-8754-4f78-bba5-bf383bee3d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38394
68226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3839468226
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2700701145
Short name T135
Test name
Test status
Simulation time 192422675 ps
CPU time 0.83 seconds
Started Jun 23 05:20:48 PM PDT 24
Finished Jun 23 05:20:50 PM PDT 24
Peak memory 206016 kb
Host smart-6b32c1ce-7f12-4f47-b18a-b568eaacf3d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27007
01145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2700701145
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.401257837
Short name T1994
Test name
Test status
Simulation time 211126402 ps
CPU time 0.87 seconds
Started Jun 23 05:20:45 PM PDT 24
Finished Jun 23 05:20:47 PM PDT 24
Peak memory 206108 kb
Host smart-3ea99c56-6676-4395-9c71-7b384932fdd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40125
7837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.401257837
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.4288480306
Short name T1136
Test name
Test status
Simulation time 152904015 ps
CPU time 0.77 seconds
Started Jun 23 05:20:49 PM PDT 24
Finished Jun 23 05:20:50 PM PDT 24
Peak memory 206108 kb
Host smart-22250d90-91e1-4421-abc3-55bfb7d35707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42884
80306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.4288480306
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.144210817
Short name T1048
Test name
Test status
Simulation time 154556222 ps
CPU time 0.79 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:20:49 PM PDT 24
Peak memory 206036 kb
Host smart-6dada99d-ac85-49be-aa40-b45e001c45c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14421
0817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.144210817
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.700747573
Short name T552
Test name
Test status
Simulation time 149073437 ps
CPU time 0.79 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:20:48 PM PDT 24
Peak memory 206036 kb
Host smart-eb400cc2-5a56-4b52-ae36-9dcb01a369c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70074
7573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.700747573
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.1621085825
Short name T2105
Test name
Test status
Simulation time 226298667 ps
CPU time 0.93 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:20:49 PM PDT 24
Peak memory 206028 kb
Host smart-553f8db1-91f9-4cff-8de3-489cabe7fada
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1621085825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.1621085825
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1444496608
Short name T930
Test name
Test status
Simulation time 143863457 ps
CPU time 0.76 seconds
Started Jun 23 05:20:49 PM PDT 24
Finished Jun 23 05:20:50 PM PDT 24
Peak memory 206112 kb
Host smart-d6f72775-75ba-4c76-a5df-9a206eefa658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14444
96608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1444496608
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.139313686
Short name T2323
Test name
Test status
Simulation time 32929956 ps
CPU time 0.67 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:53 PM PDT 24
Peak memory 206080 kb
Host smart-793f0a67-b034-4db3-8fd6-998c123fc2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13931
3686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.139313686
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1986114828
Short name T534
Test name
Test status
Simulation time 19220507125 ps
CPU time 46.14 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:21:34 PM PDT 24
Peak memory 206312 kb
Host smart-47c74bb9-bf02-42aa-bed2-c3863474b261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19861
14828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1986114828
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2440471035
Short name T2003
Test name
Test status
Simulation time 155432667 ps
CPU time 0.79 seconds
Started Jun 23 05:20:45 PM PDT 24
Finished Jun 23 05:20:47 PM PDT 24
Peak memory 206104 kb
Host smart-e7b5ffcf-9cf0-4f0f-9814-2f869d101a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24404
71035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2440471035
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.156405529
Short name T972
Test name
Test status
Simulation time 212514940 ps
CPU time 0.86 seconds
Started Jun 23 05:20:43 PM PDT 24
Finished Jun 23 05:20:44 PM PDT 24
Peak memory 206076 kb
Host smart-b595c910-a9ef-4cdb-8dfc-054ca052c940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15640
5529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.156405529
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.1384131719
Short name T337
Test name
Test status
Simulation time 241739720 ps
CPU time 0.89 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:20:49 PM PDT 24
Peak memory 206028 kb
Host smart-0f2b55f4-6318-4be8-92ab-840e84a6b409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13841
31719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1384131719
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.867914576
Short name T1706
Test name
Test status
Simulation time 193941825 ps
CPU time 0.84 seconds
Started Jun 23 05:20:44 PM PDT 24
Finished Jun 23 05:20:46 PM PDT 24
Peak memory 206140 kb
Host smart-722a3fc2-2d13-49cb-8762-d08aaba01271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86791
4576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.867914576
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3462484845
Short name T2393
Test name
Test status
Simulation time 188352815 ps
CPU time 0.93 seconds
Started Jun 23 05:20:45 PM PDT 24
Finished Jun 23 05:20:47 PM PDT 24
Peak memory 206108 kb
Host smart-136611c6-c6ce-47fa-a82b-113d56b02dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34624
84845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3462484845
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.4150379326
Short name T885
Test name
Test status
Simulation time 168174927 ps
CPU time 0.81 seconds
Started Jun 23 05:20:48 PM PDT 24
Finished Jun 23 05:20:49 PM PDT 24
Peak memory 206052 kb
Host smart-7fe38f3b-4615-4afa-b09b-50f887602154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41503
79326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.4150379326
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3156267319
Short name T1681
Test name
Test status
Simulation time 147103542 ps
CPU time 0.78 seconds
Started Jun 23 05:20:44 PM PDT 24
Finished Jun 23 05:20:45 PM PDT 24
Peak memory 206032 kb
Host smart-f803bd25-1f37-4e2a-9bba-e29072a244fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31562
67319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3156267319
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1970389287
Short name T1094
Test name
Test status
Simulation time 197156649 ps
CPU time 0.89 seconds
Started Jun 23 05:20:43 PM PDT 24
Finished Jun 23 05:20:44 PM PDT 24
Peak memory 206100 kb
Host smart-c464796a-bc95-49f2-8627-3ba2018fdf56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19703
89287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1970389287
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.3922781983
Short name T1992
Test name
Test status
Simulation time 6401092931 ps
CPU time 47.14 seconds
Started Jun 23 05:20:45 PM PDT 24
Finished Jun 23 05:21:32 PM PDT 24
Peak memory 206328 kb
Host smart-79965c20-16a5-45f4-8fbb-93ec8766b6c5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3922781983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.3922781983
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3887546119
Short name T289
Test name
Test status
Simulation time 189500441 ps
CPU time 0.77 seconds
Started Jun 23 05:20:44 PM PDT 24
Finished Jun 23 05:20:45 PM PDT 24
Peak memory 206112 kb
Host smart-5c869838-3d0d-4534-afec-8750ecf6fa8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38875
46119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3887546119
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.568091107
Short name T1965
Test name
Test status
Simulation time 205082311 ps
CPU time 0.87 seconds
Started Jun 23 05:20:45 PM PDT 24
Finished Jun 23 05:20:46 PM PDT 24
Peak memory 206048 kb
Host smart-7d418407-970d-43ad-897e-faed510b1d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56809
1107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.568091107
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.4027572491
Short name T4
Test name
Test status
Simulation time 5229218323 ps
CPU time 142.27 seconds
Started Jun 23 05:20:48 PM PDT 24
Finished Jun 23 05:23:11 PM PDT 24
Peak memory 206244 kb
Host smart-9c886860-a9e7-4c6e-b800-0d854f004878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40275
72491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.4027572491
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.717983386
Short name T2282
Test name
Test status
Simulation time 3685396316 ps
CPU time 4.13 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:20:52 PM PDT 24
Peak memory 206388 kb
Host smart-6dddac05-3316-4469-a070-6281608c87f2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=717983386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.717983386
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.1683411956
Short name T735
Test name
Test status
Simulation time 13441469170 ps
CPU time 15.62 seconds
Started Jun 23 05:20:50 PM PDT 24
Finished Jun 23 05:21:07 PM PDT 24
Peak memory 206372 kb
Host smart-2549b507-bf17-4756-bdfc-7410a018e10e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1683411956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.1683411956
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.4259551219
Short name T2248
Test name
Test status
Simulation time 23440599412 ps
CPU time 25.22 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:21:18 PM PDT 24
Peak memory 206308 kb
Host smart-30dd9a64-71e7-4866-bb72-c0cf53ba33c9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4259551219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.4259551219
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2281266591
Short name T2303
Test name
Test status
Simulation time 198254248 ps
CPU time 0.81 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:20:48 PM PDT 24
Peak memory 206120 kb
Host smart-d96d9449-8d95-44c5-b7bd-8d4ab2d9a4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22812
66591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2281266591
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.2882234931
Short name T2345
Test name
Test status
Simulation time 159267422 ps
CPU time 0.79 seconds
Started Jun 23 05:20:53 PM PDT 24
Finished Jun 23 05:20:55 PM PDT 24
Peak memory 206104 kb
Host smart-19f9ea7a-8096-44b8-9c5d-d0c878771d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28822
34931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2882234931
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1069523545
Short name T1770
Test name
Test status
Simulation time 278863552 ps
CPU time 0.91 seconds
Started Jun 23 05:20:54 PM PDT 24
Finished Jun 23 05:20:56 PM PDT 24
Peak memory 206032 kb
Host smart-2d9ba727-1161-4b2b-b21b-a69f3269f6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10695
23545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1069523545
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1795732298
Short name T610
Test name
Test status
Simulation time 1261791773 ps
CPU time 2.7 seconds
Started Jun 23 05:20:49 PM PDT 24
Finished Jun 23 05:20:52 PM PDT 24
Peak memory 206220 kb
Host smart-cff00ba3-2114-4926-add2-89b22299a43f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17957
32298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1795732298
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.899337957
Short name T1761
Test name
Test status
Simulation time 22621016360 ps
CPU time 46.13 seconds
Started Jun 23 05:20:50 PM PDT 24
Finished Jun 23 05:21:37 PM PDT 24
Peak memory 206336 kb
Host smart-656f7bf2-2b6c-4a58-abe3-114155593ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89933
7957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.899337957
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.2160295296
Short name T2013
Test name
Test status
Simulation time 494459016 ps
CPU time 1.49 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:20:49 PM PDT 24
Peak memory 206108 kb
Host smart-6e330f3a-c722-424f-b442-9fae5e6115b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21602
95296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.2160295296
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.460441189
Short name T2425
Test name
Test status
Simulation time 133602862 ps
CPU time 0.74 seconds
Started Jun 23 05:20:50 PM PDT 24
Finished Jun 23 05:20:52 PM PDT 24
Peak memory 206092 kb
Host smart-077c5d33-7d9b-4183-a8f7-4a365b9066c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46044
1189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.460441189
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.3716984119
Short name T1921
Test name
Test status
Simulation time 31332944 ps
CPU time 0.64 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:54 PM PDT 24
Peak memory 206012 kb
Host smart-8a957ef4-686d-4212-a51f-52c019219b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37169
84119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3716984119
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1482562603
Short name T1405
Test name
Test status
Simulation time 1015926091 ps
CPU time 2.52 seconds
Started Jun 23 05:20:53 PM PDT 24
Finished Jun 23 05:20:57 PM PDT 24
Peak memory 206356 kb
Host smart-52821ff1-75e4-4a41-a894-20becf6ff09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14825
62603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1482562603
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1020984502
Short name T1929
Test name
Test status
Simulation time 202492134 ps
CPU time 2.1 seconds
Started Jun 23 05:20:46 PM PDT 24
Finished Jun 23 05:20:49 PM PDT 24
Peak memory 206260 kb
Host smart-808f8479-e6e8-43f4-9f5a-d2dd1a87dee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10209
84502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1020984502
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.3850507879
Short name T2267
Test name
Test status
Simulation time 154561822 ps
CPU time 0.78 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:54 PM PDT 24
Peak memory 206116 kb
Host smart-974b72e9-9222-459d-973b-460d13f5df35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38505
07879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.3850507879
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2883059341
Short name T312
Test name
Test status
Simulation time 154237616 ps
CPU time 0.76 seconds
Started Jun 23 05:21:00 PM PDT 24
Finished Jun 23 05:21:02 PM PDT 24
Peak memory 206092 kb
Host smart-f7a15d3e-6b75-4866-ab94-e2109954fac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28830
59341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2883059341
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1002167288
Short name T2204
Test name
Test status
Simulation time 179206674 ps
CPU time 0.81 seconds
Started Jun 23 05:20:49 PM PDT 24
Finished Jun 23 05:20:51 PM PDT 24
Peak memory 205896 kb
Host smart-770fd9a6-a552-420c-9ce9-4ea4ad762b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10021
67288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1002167288
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.683010319
Short name T1430
Test name
Test status
Simulation time 194443389 ps
CPU time 0.85 seconds
Started Jun 23 05:20:54 PM PDT 24
Finished Jun 23 05:20:56 PM PDT 24
Peak memory 206292 kb
Host smart-8aea3918-0d5d-498c-af0f-725b6fdde7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68301
0319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.683010319
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.3107000536
Short name T1851
Test name
Test status
Simulation time 23314375391 ps
CPU time 24.38 seconds
Started Jun 23 05:20:45 PM PDT 24
Finished Jun 23 05:21:10 PM PDT 24
Peak memory 206128 kb
Host smart-62620916-3292-4c5b-9c0d-55a21e6e437d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31070
00536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.3107000536
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.2420372072
Short name T1771
Test name
Test status
Simulation time 3306163833 ps
CPU time 4.09 seconds
Started Jun 23 05:20:48 PM PDT 24
Finished Jun 23 05:20:52 PM PDT 24
Peak memory 206084 kb
Host smart-eab619ae-2f01-4b03-9112-6399d3af4caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24203
72072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.2420372072
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.1787148037
Short name T1021
Test name
Test status
Simulation time 8130528211 ps
CPU time 231.34 seconds
Started Jun 23 05:20:49 PM PDT 24
Finished Jun 23 05:24:41 PM PDT 24
Peak memory 206344 kb
Host smart-d2f369b0-109b-4be4-9b21-2b492b15e367
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1787148037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.1787148037
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.2557747875
Short name T1618
Test name
Test status
Simulation time 241358151 ps
CPU time 0.88 seconds
Started Jun 23 05:20:53 PM PDT 24
Finished Jun 23 05:20:55 PM PDT 24
Peak memory 206044 kb
Host smart-64838377-6030-4e7e-9031-43fb3a620cd5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2557747875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.2557747875
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3225701219
Short name T1939
Test name
Test status
Simulation time 234452189 ps
CPU time 0.89 seconds
Started Jun 23 05:20:48 PM PDT 24
Finished Jun 23 05:20:50 PM PDT 24
Peak memory 206056 kb
Host smart-5930f790-93fb-4719-a66d-ccf6df9014a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32257
01219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3225701219
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.247348910
Short name T456
Test name
Test status
Simulation time 11338569622 ps
CPU time 77.06 seconds
Started Jun 23 05:20:50 PM PDT 24
Finished Jun 23 05:22:08 PM PDT 24
Peak memory 206360 kb
Host smart-95c4fa69-91f9-43e0-875f-f82221ec5840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24734
8910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.247348910
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.2791019668
Short name T1475
Test name
Test status
Simulation time 6198081116 ps
CPU time 56.89 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:21:50 PM PDT 24
Peak memory 206272 kb
Host smart-c2664f3b-b747-477c-9c5d-80965555add0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2791019668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.2791019668
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.172811166
Short name T1045
Test name
Test status
Simulation time 163065743 ps
CPU time 0.85 seconds
Started Jun 23 05:21:01 PM PDT 24
Finished Jun 23 05:21:03 PM PDT 24
Peak memory 206120 kb
Host smart-acbfd834-ceba-4453-88a8-413f2ade0c25
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=172811166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.172811166
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.4150029338
Short name T1707
Test name
Test status
Simulation time 151944723 ps
CPU time 0.79 seconds
Started Jun 23 05:20:48 PM PDT 24
Finished Jun 23 05:20:49 PM PDT 24
Peak memory 206112 kb
Host smart-77a868c2-9759-453a-b89d-59963283e65d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41500
29338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.4150029338
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.4264243649
Short name T125
Test name
Test status
Simulation time 189468866 ps
CPU time 0.84 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:54 PM PDT 24
Peak memory 206032 kb
Host smart-02a9e50c-d398-41c5-be64-26e5b3a153db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42642
43649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.4264243649
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.2517416880
Short name T1683
Test name
Test status
Simulation time 186215503 ps
CPU time 0.85 seconds
Started Jun 23 05:20:51 PM PDT 24
Finished Jun 23 05:20:53 PM PDT 24
Peak memory 206072 kb
Host smart-bdac4cc0-7730-45ef-a472-f52a91debea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25174
16880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.2517416880
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.2081877816
Short name T449
Test name
Test status
Simulation time 174152899 ps
CPU time 0.76 seconds
Started Jun 23 05:20:50 PM PDT 24
Finished Jun 23 05:20:52 PM PDT 24
Peak memory 206096 kb
Host smart-1ef0c112-a94c-4e6f-96de-5c264334a2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20818
77816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2081877816
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.91213092
Short name T279
Test name
Test status
Simulation time 195510779 ps
CPU time 0.85 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:54 PM PDT 24
Peak memory 206104 kb
Host smart-aa7ea1b3-c5fe-4734-b9b9-2930c75e0cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91213
092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.91213092
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3094847799
Short name T169
Test name
Test status
Simulation time 147988254 ps
CPU time 0.79 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:54 PM PDT 24
Peak memory 206060 kb
Host smart-bb7c0f8a-8d84-450c-b5d4-b2d417bc4172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30948
47799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3094847799
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.4215551809
Short name T828
Test name
Test status
Simulation time 259955404 ps
CPU time 0.94 seconds
Started Jun 23 05:20:53 PM PDT 24
Finished Jun 23 05:20:55 PM PDT 24
Peak memory 206124 kb
Host smart-e9ee67c0-1d11-409c-99f0-1fcbdc39edab
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4215551809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.4215551809
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.593409340
Short name T728
Test name
Test status
Simulation time 148429489 ps
CPU time 0.78 seconds
Started Jun 23 05:21:01 PM PDT 24
Finished Jun 23 05:21:02 PM PDT 24
Peak memory 206120 kb
Host smart-895b0fd8-35f4-40b3-8619-b13021c1d306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59340
9340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.593409340
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1089870478
Short name T2418
Test name
Test status
Simulation time 33569636 ps
CPU time 0.66 seconds
Started Jun 23 05:20:54 PM PDT 24
Finished Jun 23 05:20:56 PM PDT 24
Peak memory 206040 kb
Host smart-cb8644c8-eac5-4cd2-9341-d0d8e2ae4130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10898
70478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1089870478
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.132871853
Short name T150
Test name
Test status
Simulation time 14821789943 ps
CPU time 31.93 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:21:25 PM PDT 24
Peak memory 206332 kb
Host smart-fa25d5bc-4961-494b-82e0-54c1c173b0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13287
1853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.132871853
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1623931396
Short name T1216
Test name
Test status
Simulation time 148042345 ps
CPU time 0.78 seconds
Started Jun 23 05:20:53 PM PDT 24
Finished Jun 23 05:20:55 PM PDT 24
Peak memory 206100 kb
Host smart-4d6a0568-4753-4a7f-bdce-07c03f0e2582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16239
31396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1623931396
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2286361449
Short name T1171
Test name
Test status
Simulation time 224920880 ps
CPU time 0.85 seconds
Started Jun 23 05:20:53 PM PDT 24
Finished Jun 23 05:20:55 PM PDT 24
Peak memory 206104 kb
Host smart-9a654844-bd40-43cc-b38d-528dab6e56ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22863
61449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2286361449
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.2386185437
Short name T303
Test name
Test status
Simulation time 178212454 ps
CPU time 0.85 seconds
Started Jun 23 05:20:51 PM PDT 24
Finished Jun 23 05:20:53 PM PDT 24
Peak memory 206100 kb
Host smart-057d1aa4-7dda-4b62-bdeb-c7af2be6b24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23861
85437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.2386185437
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.535607272
Short name T1367
Test name
Test status
Simulation time 185537611 ps
CPU time 0.83 seconds
Started Jun 23 05:20:49 PM PDT 24
Finished Jun 23 05:20:51 PM PDT 24
Peak memory 205960 kb
Host smart-ea4e3822-19b1-4773-a8e7-20375975ab4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53560
7272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.535607272
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.2000927614
Short name T1278
Test name
Test status
Simulation time 157352483 ps
CPU time 0.84 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:20:49 PM PDT 24
Peak memory 206004 kb
Host smart-37005031-2708-4c75-9a06-71c598b3e41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20009
27614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.2000927614
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2501717639
Short name T1766
Test name
Test status
Simulation time 167607717 ps
CPU time 0.78 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:54 PM PDT 24
Peak memory 206068 kb
Host smart-c49f719c-169c-40d2-b675-0496f3234178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25017
17639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2501717639
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1909885797
Short name T792
Test name
Test status
Simulation time 197332935 ps
CPU time 0.82 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:20:48 PM PDT 24
Peak memory 206080 kb
Host smart-cbe995e7-402d-4ffd-a351-5c1e47091262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19098
85797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1909885797
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1278358972
Short name T933
Test name
Test status
Simulation time 227833709 ps
CPU time 0.94 seconds
Started Jun 23 05:20:51 PM PDT 24
Finished Jun 23 05:20:52 PM PDT 24
Peak memory 206292 kb
Host smart-769d18f5-2f12-4450-9458-3403d7dba7c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12783
58972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1278358972
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.3451901799
Short name T1457
Test name
Test status
Simulation time 4531227748 ps
CPU time 32.51 seconds
Started Jun 23 05:20:47 PM PDT 24
Finished Jun 23 05:21:21 PM PDT 24
Peak memory 206348 kb
Host smart-406253d7-4acd-4298-89d4-aa313c85548a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3451901799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.3451901799
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2306786870
Short name T1563
Test name
Test status
Simulation time 167055909 ps
CPU time 0.79 seconds
Started Jun 23 05:20:53 PM PDT 24
Finished Jun 23 05:20:55 PM PDT 24
Peak memory 206040 kb
Host smart-54bc07d8-a45b-4d18-a413-1f9cb300a378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23067
86870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.2306786870
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.3286100200
Short name T1986
Test name
Test status
Simulation time 198049902 ps
CPU time 0.88 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:54 PM PDT 24
Peak memory 206020 kb
Host smart-cb05455c-cb33-43ff-bff6-5f3c81a9ccea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32861
00200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3286100200
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.1628793629
Short name T1788
Test name
Test status
Simulation time 3893536483 ps
CPU time 112.52 seconds
Started Jun 23 05:20:50 PM PDT 24
Finished Jun 23 05:22:43 PM PDT 24
Peak memory 206320 kb
Host smart-4bf312eb-6289-4de3-bc05-224496ea5d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16287
93629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.1628793629
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.2539134464
Short name T781
Test name
Test status
Simulation time 13340188594 ps
CPU time 12.33 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:21:06 PM PDT 24
Peak memory 206396 kb
Host smart-36adec66-3d75-4b57-9525-7df3a953993b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2539134464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.2539134464
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1237126549
Short name T1027
Test name
Test status
Simulation time 23391175147 ps
CPU time 22.86 seconds
Started Jun 23 05:20:55 PM PDT 24
Finished Jun 23 05:21:19 PM PDT 24
Peak memory 206332 kb
Host smart-2482d9ab-b43e-456e-80a8-1a552103a540
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1237126549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.1237126549
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.635829081
Short name T1522
Test name
Test status
Simulation time 197302404 ps
CPU time 0.88 seconds
Started Jun 23 05:21:01 PM PDT 24
Finished Jun 23 05:21:02 PM PDT 24
Peak memory 206092 kb
Host smart-beff55ce-b774-4536-b14a-b4ac7639a27e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63582
9081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.635829081
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2798673470
Short name T992
Test name
Test status
Simulation time 146193280 ps
CPU time 0.76 seconds
Started Jun 23 05:20:54 PM PDT 24
Finished Jun 23 05:20:56 PM PDT 24
Peak memory 206032 kb
Host smart-4be6e8a3-e9be-45d1-8604-09f3c1fd9d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27986
73470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2798673470
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.3580060756
Short name T2107
Test name
Test status
Simulation time 280810981 ps
CPU time 1.08 seconds
Started Jun 23 05:20:53 PM PDT 24
Finished Jun 23 05:20:55 PM PDT 24
Peak memory 206112 kb
Host smart-40ef19c5-fa4f-41c7-bf42-7f9208f16d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35800
60756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.3580060756
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.1032260090
Short name T1654
Test name
Test status
Simulation time 517886568 ps
CPU time 1.56 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:55 PM PDT 24
Peak memory 206100 kb
Host smart-05f7ce79-9815-4070-88f8-81c33588a443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10322
60090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1032260090
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2307129334
Short name T1160
Test name
Test status
Simulation time 21457435108 ps
CPU time 48.44 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:21:42 PM PDT 24
Peak memory 206372 kb
Host smart-87db0058-64f5-4002-acc7-defcabeac52f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23071
29334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2307129334
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.2876285181
Short name T1209
Test name
Test status
Simulation time 455931050 ps
CPU time 1.29 seconds
Started Jun 23 05:20:54 PM PDT 24
Finished Jun 23 05:20:56 PM PDT 24
Peak memory 206292 kb
Host smart-36fce1a8-5c13-4992-b259-e6c7721a5aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28762
85181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.2876285181
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2703718083
Short name T814
Test name
Test status
Simulation time 148467919 ps
CPU time 0.74 seconds
Started Jun 23 05:20:54 PM PDT 24
Finished Jun 23 05:20:56 PM PDT 24
Peak memory 206100 kb
Host smart-7d3ae322-ebc7-4e0a-a8ad-8a0328eca6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27037
18083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2703718083
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.467670613
Short name T898
Test name
Test status
Simulation time 49300534 ps
CPU time 0.69 seconds
Started Jun 23 05:20:54 PM PDT 24
Finished Jun 23 05:20:55 PM PDT 24
Peak memory 206024 kb
Host smart-6ab31d01-8124-445e-ae91-14c2c706039b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46767
0613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.467670613
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.1067899752
Short name T1415
Test name
Test status
Simulation time 873777852 ps
CPU time 2.07 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:56 PM PDT 24
Peak memory 206316 kb
Host smart-86dac15b-6992-4ea4-b57a-a36b67783ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10678
99752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.1067899752
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2094862772
Short name T1139
Test name
Test status
Simulation time 259080062 ps
CPU time 1.64 seconds
Started Jun 23 05:20:51 PM PDT 24
Finished Jun 23 05:20:54 PM PDT 24
Peak memory 206256 kb
Host smart-ff97a20e-8711-4ba0-8014-9a1ef099946d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20948
62772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2094862772
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2673818376
Short name T1500
Test name
Test status
Simulation time 140562514 ps
CPU time 0.76 seconds
Started Jun 23 05:20:57 PM PDT 24
Finished Jun 23 05:20:59 PM PDT 24
Peak memory 206092 kb
Host smart-64968457-2881-4730-8183-6489fa741b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26738
18376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2673818376
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1477033729
Short name T1466
Test name
Test status
Simulation time 294981016 ps
CPU time 0.99 seconds
Started Jun 23 05:20:55 PM PDT 24
Finished Jun 23 05:20:57 PM PDT 24
Peak memory 206024 kb
Host smart-62d9a5ac-307d-421c-862f-3cab5d9e1930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14770
33729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1477033729
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.8282703
Short name T1450
Test name
Test status
Simulation time 227373149 ps
CPU time 0.87 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:55 PM PDT 24
Peak memory 206120 kb
Host smart-4a6248cb-5f4c-4ef2-af81-c6a34c228fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82827
03 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.8282703
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.1819033952
Short name T1428
Test name
Test status
Simulation time 23341615751 ps
CPU time 24.58 seconds
Started Jun 23 05:20:54 PM PDT 24
Finished Jun 23 05:21:19 PM PDT 24
Peak memory 206088 kb
Host smart-29e3ef6f-c5aa-41f2-bd81-1a34c89faf42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18190
33952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.1819033952
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3164361290
Short name T2356
Test name
Test status
Simulation time 3308259752 ps
CPU time 3.73 seconds
Started Jun 23 05:21:01 PM PDT 24
Finished Jun 23 05:21:05 PM PDT 24
Peak memory 206160 kb
Host smart-451d79ea-1f4a-44d7-a57f-abff2b021b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31643
61290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3164361290
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.812971947
Short name T529
Test name
Test status
Simulation time 9722666780 ps
CPU time 278.8 seconds
Started Jun 23 05:21:00 PM PDT 24
Finished Jun 23 05:25:39 PM PDT 24
Peak memory 206344 kb
Host smart-a42f04f9-b521-4e28-97e3-54427d3bf5eb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=812971947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.812971947
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.698439849
Short name T2175
Test name
Test status
Simulation time 238818794 ps
CPU time 0.88 seconds
Started Jun 23 05:21:04 PM PDT 24
Finished Jun 23 05:21:05 PM PDT 24
Peak memory 206120 kb
Host smart-3872696a-24e3-419e-a595-99cf849aba2e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=698439849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.698439849
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.4037650958
Short name T652
Test name
Test status
Simulation time 220227519 ps
CPU time 0.91 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:55 PM PDT 24
Peak memory 206072 kb
Host smart-95c37949-5d2c-4f0d-86be-840e50ee5fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40376
50958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.4037650958
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1624673071
Short name T1119
Test name
Test status
Simulation time 6412630415 ps
CPU time 175.38 seconds
Started Jun 23 05:20:59 PM PDT 24
Finished Jun 23 05:23:55 PM PDT 24
Peak memory 206248 kb
Host smart-9bc1e2ca-3aaf-4e9b-a8ec-670b4407a37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16246
73071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1624673071
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.4196086346
Short name T462
Test name
Test status
Simulation time 7898913348 ps
CPU time 234.55 seconds
Started Jun 23 05:20:59 PM PDT 24
Finished Jun 23 05:24:54 PM PDT 24
Peak memory 206364 kb
Host smart-ff1f61e9-33d7-4dd7-a502-edaecc7c0520
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4196086346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.4196086346
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.3813494212
Short name T2120
Test name
Test status
Simulation time 156010683 ps
CPU time 0.83 seconds
Started Jun 23 05:20:59 PM PDT 24
Finished Jun 23 05:21:00 PM PDT 24
Peak memory 206128 kb
Host smart-5515d494-94b8-4c76-9833-789525a8ffa9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3813494212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.3813494212
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1165423924
Short name T1497
Test name
Test status
Simulation time 155302007 ps
CPU time 0.82 seconds
Started Jun 23 05:21:01 PM PDT 24
Finished Jun 23 05:21:02 PM PDT 24
Peak memory 206104 kb
Host smart-a19eefb8-2e24-4ff0-aa60-785762450ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11654
23924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1165423924
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3969842815
Short name T127
Test name
Test status
Simulation time 194456189 ps
CPU time 0.87 seconds
Started Jun 23 05:20:57 PM PDT 24
Finished Jun 23 05:20:58 PM PDT 24
Peak memory 206096 kb
Host smart-4d9cbe2e-1500-41ec-b7f7-fd231189b645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39698
42815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3969842815
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2453816201
Short name T91
Test name
Test status
Simulation time 158535120 ps
CPU time 0.81 seconds
Started Jun 23 05:20:55 PM PDT 24
Finished Jun 23 05:20:56 PM PDT 24
Peak memory 206100 kb
Host smart-37c4747e-f8f1-4545-8001-2080a697c188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24538
16201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2453816201
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3335803862
Short name T987
Test name
Test status
Simulation time 178927848 ps
CPU time 0.8 seconds
Started Jun 23 05:20:57 PM PDT 24
Finished Jun 23 05:20:58 PM PDT 24
Peak memory 206104 kb
Host smart-ace6bcb9-107f-4d9a-a721-9771e2e95ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33358
03862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3335803862
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.386973907
Short name T1248
Test name
Test status
Simulation time 212163926 ps
CPU time 0.87 seconds
Started Jun 23 05:20:58 PM PDT 24
Finished Jun 23 05:21:00 PM PDT 24
Peak memory 206048 kb
Host smart-678f557f-5c17-43fb-8a0d-4722ec2079be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38697
3907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.386973907
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3986478826
Short name T1786
Test name
Test status
Simulation time 151022312 ps
CPU time 0.77 seconds
Started Jun 23 05:20:58 PM PDT 24
Finished Jun 23 05:21:00 PM PDT 24
Peak memory 206092 kb
Host smart-6c663e6c-9a09-45ba-b6a8-1efc90b1e398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39864
78826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3986478826
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.3552540591
Short name T2453
Test name
Test status
Simulation time 259150541 ps
CPU time 1.01 seconds
Started Jun 23 05:20:59 PM PDT 24
Finished Jun 23 05:21:00 PM PDT 24
Peak memory 206132 kb
Host smart-16397650-e2e3-44c8-aab7-0fc50ee9a5c7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3552540591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.3552540591
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.4106195427
Short name T1904
Test name
Test status
Simulation time 173928307 ps
CPU time 0.82 seconds
Started Jun 23 05:21:00 PM PDT 24
Finished Jun 23 05:21:02 PM PDT 24
Peak memory 206300 kb
Host smart-ad422dbb-f421-4c11-9c4b-754aafbd3c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41061
95427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.4106195427
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.283726876
Short name T2066
Test name
Test status
Simulation time 77084800 ps
CPU time 0.68 seconds
Started Jun 23 05:20:59 PM PDT 24
Finished Jun 23 05:21:00 PM PDT 24
Peak memory 206036 kb
Host smart-1a8e2b58-6d6a-405f-ab06-e897ef068aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28372
6876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.283726876
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.2101118058
Short name T1077
Test name
Test status
Simulation time 13635017209 ps
CPU time 32.07 seconds
Started Jun 23 05:20:56 PM PDT 24
Finished Jun 23 05:21:28 PM PDT 24
Peak memory 206376 kb
Host smart-61a1fb1d-acd7-4410-b6c8-3275183a8078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21011
18058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.2101118058
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2142308438
Short name T2201
Test name
Test status
Simulation time 177790961 ps
CPU time 0.82 seconds
Started Jun 23 05:20:58 PM PDT 24
Finished Jun 23 05:20:59 PM PDT 24
Peak memory 206100 kb
Host smart-67d438e1-1466-43ca-bbc3-c1a672664978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21423
08438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2142308438
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3584390515
Short name T1310
Test name
Test status
Simulation time 206815365 ps
CPU time 0.84 seconds
Started Jun 23 05:20:58 PM PDT 24
Finished Jun 23 05:20:59 PM PDT 24
Peak memory 206100 kb
Host smart-553e2ed2-0f61-43f1-a04b-e712fa75bc49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35843
90515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3584390515
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.157435545
Short name T547
Test name
Test status
Simulation time 252272457 ps
CPU time 0.87 seconds
Started Jun 23 05:20:59 PM PDT 24
Finished Jun 23 05:21:00 PM PDT 24
Peak memory 206108 kb
Host smart-918e892f-076b-4367-9da0-aad75170c105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15743
5545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.157435545
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.695339167
Short name T2033
Test name
Test status
Simulation time 183552889 ps
CPU time 0.92 seconds
Started Jun 23 05:20:59 PM PDT 24
Finished Jun 23 05:21:00 PM PDT 24
Peak memory 206116 kb
Host smart-54a6afdb-d470-4a5d-b54e-34f685d897df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69533
9167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.695339167
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.3744575152
Short name T1336
Test name
Test status
Simulation time 186543463 ps
CPU time 0.84 seconds
Started Jun 23 05:20:59 PM PDT 24
Finished Jun 23 05:21:01 PM PDT 24
Peak memory 206020 kb
Host smart-aec1b1dc-f7cd-4607-8c6a-e78f0e8e67b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37445
75152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.3744575152
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3034409688
Short name T1844
Test name
Test status
Simulation time 158263969 ps
CPU time 0.79 seconds
Started Jun 23 05:20:56 PM PDT 24
Finished Jun 23 05:20:58 PM PDT 24
Peak memory 205992 kb
Host smart-7b5fecf1-46e1-4e9f-9294-28205e96097d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30344
09688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3034409688
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3169896287
Short name T1853
Test name
Test status
Simulation time 215191741 ps
CPU time 0.88 seconds
Started Jun 23 05:20:59 PM PDT 24
Finished Jun 23 05:21:00 PM PDT 24
Peak memory 206104 kb
Host smart-b087eed9-cb5e-4d46-9fb0-ee48c4cafde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31698
96287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3169896287
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2192208125
Short name T489
Test name
Test status
Simulation time 256680921 ps
CPU time 1.04 seconds
Started Jun 23 05:20:52 PM PDT 24
Finished Jun 23 05:20:54 PM PDT 24
Peak memory 206100 kb
Host smart-2cd37382-68cb-4e22-8982-e4e5c9884ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21922
08125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2192208125
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.3213311116
Short name T2456
Test name
Test status
Simulation time 11984421493 ps
CPU time 339.83 seconds
Started Jun 23 05:20:59 PM PDT 24
Finished Jun 23 05:26:39 PM PDT 24
Peak memory 206372 kb
Host smart-16e14b70-41a1-4422-8c5b-15eb37fe0de2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3213311116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.3213311116
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1945532278
Short name T1708
Test name
Test status
Simulation time 175339061 ps
CPU time 0.85 seconds
Started Jun 23 05:20:57 PM PDT 24
Finished Jun 23 05:20:59 PM PDT 24
Peak memory 206012 kb
Host smart-a1a97edf-e03f-4c5c-99a8-94f994812ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19455
32278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1945532278
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.90993713
Short name T1913
Test name
Test status
Simulation time 175713269 ps
CPU time 0.81 seconds
Started Jun 23 05:21:00 PM PDT 24
Finished Jun 23 05:21:01 PM PDT 24
Peak memory 205856 kb
Host smart-66d863cb-81be-435a-b5ca-19770b0134dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90993
713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.90993713
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3689218245
Short name T2457
Test name
Test status
Simulation time 4487447098 ps
CPU time 31.6 seconds
Started Jun 23 05:20:57 PM PDT 24
Finished Jun 23 05:21:29 PM PDT 24
Peak memory 206256 kb
Host smart-db40d06b-5470-4366-8e7a-3c6b70fea61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36892
18245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3689218245
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1685932028
Short name T1296
Test name
Test status
Simulation time 3497738689 ps
CPU time 4.17 seconds
Started Jun 23 05:21:03 PM PDT 24
Finished Jun 23 05:21:08 PM PDT 24
Peak memory 206184 kb
Host smart-3dadfc69-a61b-4e6a-beb3-6f553e0f70e3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1685932028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.1685932028
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.253422902
Short name T445
Test name
Test status
Simulation time 13473591048 ps
CPU time 13.62 seconds
Started Jun 23 05:21:03 PM PDT 24
Finished Jun 23 05:21:17 PM PDT 24
Peak memory 206360 kb
Host smart-fd97bc2a-ff68-4c7c-9bb5-2be5dbd2e3f4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=253422902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.253422902
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.85656759
Short name T1611
Test name
Test status
Simulation time 23358311555 ps
CPU time 23.07 seconds
Started Jun 23 05:21:04 PM PDT 24
Finished Jun 23 05:21:28 PM PDT 24
Peak memory 206316 kb
Host smart-abcbcdc3-8687-4e3d-9763-9fefc9b24406
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=85656759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.85656759
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1744439772
Short name T891
Test name
Test status
Simulation time 156576606 ps
CPU time 0.84 seconds
Started Jun 23 05:21:05 PM PDT 24
Finished Jun 23 05:21:07 PM PDT 24
Peak memory 206104 kb
Host smart-1db6e75b-c44e-409f-b00a-34cc6f3d6d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17444
39772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1744439772
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.3748633469
Short name T2099
Test name
Test status
Simulation time 160860314 ps
CPU time 0.86 seconds
Started Jun 23 05:21:02 PM PDT 24
Finished Jun 23 05:21:04 PM PDT 24
Peak memory 206060 kb
Host smart-69fb2c67-3d83-457a-9d8f-299a6b87c0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37486
33469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.3748633469
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.1061565887
Short name T1977
Test name
Test status
Simulation time 273285785 ps
CPU time 1.12 seconds
Started Jun 23 05:21:02 PM PDT 24
Finished Jun 23 05:21:04 PM PDT 24
Peak memory 206096 kb
Host smart-52ab66b1-3d21-47ff-8a23-7ae2e7de9865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10615
65887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.1061565887
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2436582513
Short name T1026
Test name
Test status
Simulation time 1264503309 ps
CPU time 2.51 seconds
Started Jun 23 05:21:03 PM PDT 24
Finished Jun 23 05:21:06 PM PDT 24
Peak memory 206232 kb
Host smart-56e7561b-5ada-4b49-bf2b-539a0ad02c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24365
82513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2436582513
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.2480133201
Short name T603
Test name
Test status
Simulation time 14179310955 ps
CPU time 25.75 seconds
Started Jun 23 05:21:03 PM PDT 24
Finished Jun 23 05:21:29 PM PDT 24
Peak memory 206340 kb
Host smart-777bfc8e-317b-4f72-985d-521e81ed9683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24801
33201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.2480133201
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.1262330819
Short name T602
Test name
Test status
Simulation time 298064342 ps
CPU time 1.15 seconds
Started Jun 23 05:21:03 PM PDT 24
Finished Jun 23 05:21:05 PM PDT 24
Peak memory 206108 kb
Host smart-a83097d8-af10-46c2-8dff-e1c2b33fb078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12623
30819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.1262330819
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.3628851126
Short name T2197
Test name
Test status
Simulation time 140819731 ps
CPU time 0.75 seconds
Started Jun 23 05:21:01 PM PDT 24
Finished Jun 23 05:21:02 PM PDT 24
Peak memory 206036 kb
Host smart-2572006c-0776-4995-8e97-9a8afa68e51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36288
51126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.3628851126
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.1905113319
Short name T1953
Test name
Test status
Simulation time 33829431 ps
CPU time 0.64 seconds
Started Jun 23 05:21:05 PM PDT 24
Finished Jun 23 05:21:06 PM PDT 24
Peak memory 206064 kb
Host smart-57a404c6-6e72-4612-b270-aea4e895a171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19051
13319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1905113319
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.2464618982
Short name T1280
Test name
Test status
Simulation time 720866982 ps
CPU time 1.77 seconds
Started Jun 23 05:21:02 PM PDT 24
Finished Jun 23 05:21:04 PM PDT 24
Peak memory 206244 kb
Host smart-9f5ea90c-883c-4a0c-be7b-28a723627ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24646
18982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.2464618982
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.4287954001
Short name T1356
Test name
Test status
Simulation time 265880060 ps
CPU time 1.57 seconds
Started Jun 23 05:21:05 PM PDT 24
Finished Jun 23 05:21:07 PM PDT 24
Peak memory 206340 kb
Host smart-825a0557-c8be-4ee9-b180-1d81fc943cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42879
54001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.4287954001
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3969522635
Short name T2403
Test name
Test status
Simulation time 199853438 ps
CPU time 0.83 seconds
Started Jun 23 05:21:08 PM PDT 24
Finished Jun 23 05:21:09 PM PDT 24
Peak memory 206036 kb
Host smart-4237c361-c7b5-4059-8e9b-d70cc410b67c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39695
22635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3969522635
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2075676019
Short name T466
Test name
Test status
Simulation time 174414405 ps
CPU time 0.78 seconds
Started Jun 23 05:21:06 PM PDT 24
Finished Jun 23 05:21:07 PM PDT 24
Peak memory 206088 kb
Host smart-4d85fd37-4973-41b9-b765-c0f9518163be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20756
76019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2075676019
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.4227479777
Short name T1541
Test name
Test status
Simulation time 244565691 ps
CPU time 0.94 seconds
Started Jun 23 05:21:02 PM PDT 24
Finished Jun 23 05:21:03 PM PDT 24
Peak memory 206116 kb
Host smart-5f6b8e44-ddba-49ad-978e-ae31b89680c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42274
79777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.4227479777
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.1108948104
Short name T598
Test name
Test status
Simulation time 240683423 ps
CPU time 0.9 seconds
Started Jun 23 05:21:02 PM PDT 24
Finished Jun 23 05:21:03 PM PDT 24
Peak memory 206016 kb
Host smart-91733b34-d37e-451a-ad62-cd6c9f0da8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11089
48104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.1108948104
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.3431303514
Short name T383
Test name
Test status
Simulation time 23320936689 ps
CPU time 24.75 seconds
Started Jun 23 05:21:04 PM PDT 24
Finished Jun 23 05:21:29 PM PDT 24
Peak memory 206152 kb
Host smart-7142c1d5-92b5-44b6-b529-4894eee36599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34313
03514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.3431303514
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.2092369792
Short name T341
Test name
Test status
Simulation time 3269868530 ps
CPU time 3.69 seconds
Started Jun 23 05:21:03 PM PDT 24
Finished Jun 23 05:21:07 PM PDT 24
Peak memory 206168 kb
Host smart-36f5457d-c0f4-4f20-9b51-d40744b2596c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20923
69792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2092369792
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.1339513422
Short name T1780
Test name
Test status
Simulation time 7842240542 ps
CPU time 217.62 seconds
Started Jun 23 05:21:07 PM PDT 24
Finished Jun 23 05:24:45 PM PDT 24
Peak memory 206124 kb
Host smart-b9ce4726-fd27-4cb2-bcf7-f97583539f21
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1339513422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.1339513422
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1565705188
Short name T1175
Test name
Test status
Simulation time 257499248 ps
CPU time 0.96 seconds
Started Jun 23 05:21:10 PM PDT 24
Finished Jun 23 05:21:11 PM PDT 24
Peak memory 206120 kb
Host smart-c7c7a16e-7701-4b21-9220-a880d730e678
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1565705188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1565705188
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2663189531
Short name T1371
Test name
Test status
Simulation time 200430692 ps
CPU time 0.86 seconds
Started Jun 23 05:21:02 PM PDT 24
Finished Jun 23 05:21:04 PM PDT 24
Peak memory 206116 kb
Host smart-91a4c214-595d-47d7-9f34-b7f106e21855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26631
89531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2663189531
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.3822005327
Short name T928
Test name
Test status
Simulation time 4296846968 ps
CPU time 118.1 seconds
Started Jun 23 05:21:02 PM PDT 24
Finished Jun 23 05:23:00 PM PDT 24
Peak memory 206284 kb
Host smart-a92f0c16-3f48-4dfe-b31f-41553db9afde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38220
05327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.3822005327
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.253799034
Short name T709
Test name
Test status
Simulation time 4420804429 ps
CPU time 40.38 seconds
Started Jun 23 05:21:01 PM PDT 24
Finished Jun 23 05:21:42 PM PDT 24
Peak memory 206352 kb
Host smart-a91b70b8-3210-4e30-b25e-1a83e5d9ed34
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=253799034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.253799034
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.2946719932
Short name T2391
Test name
Test status
Simulation time 172846260 ps
CPU time 0.79 seconds
Started Jun 23 05:21:07 PM PDT 24
Finished Jun 23 05:21:08 PM PDT 24
Peak memory 206132 kb
Host smart-05d02faf-f712-4e44-84d6-418df05d3c4e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2946719932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.2946719932
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2936713590
Short name T2291
Test name
Test status
Simulation time 152242168 ps
CPU time 0.79 seconds
Started Jun 23 05:21:01 PM PDT 24
Finished Jun 23 05:21:02 PM PDT 24
Peak memory 205992 kb
Host smart-a872b5d0-0622-4f98-9038-314e06d29935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29367
13590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2936713590
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1346188305
Short name T126
Test name
Test status
Simulation time 202724880 ps
CPU time 0.85 seconds
Started Jun 23 05:21:02 PM PDT 24
Finished Jun 23 05:21:03 PM PDT 24
Peak memory 206108 kb
Host smart-7bbc9f80-e8bf-44f4-a1b9-c4ac671c1537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13461
88305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1346188305
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3618497989
Short name T588
Test name
Test status
Simulation time 173807363 ps
CPU time 0.84 seconds
Started Jun 23 05:21:04 PM PDT 24
Finished Jun 23 05:21:05 PM PDT 24
Peak memory 206100 kb
Host smart-c6635d19-4a8b-4f45-808a-cbf3a435b4d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36184
97989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3618497989
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.257780939
Short name T627
Test name
Test status
Simulation time 160769039 ps
CPU time 0.86 seconds
Started Jun 23 05:21:02 PM PDT 24
Finished Jun 23 05:21:04 PM PDT 24
Peak memory 206100 kb
Host smart-f75ea3f0-585e-45ad-aa22-653ccadf258c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25778
0939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.257780939
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1970471221
Short name T2159
Test name
Test status
Simulation time 176332600 ps
CPU time 0.82 seconds
Started Jun 23 05:21:05 PM PDT 24
Finished Jun 23 05:21:07 PM PDT 24
Peak memory 206040 kb
Host smart-69d4d099-e00e-4f0f-9148-be8734e5516c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19704
71221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1970471221
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.177042083
Short name T968
Test name
Test status
Simulation time 174046687 ps
CPU time 0.84 seconds
Started Jun 23 05:21:11 PM PDT 24
Finished Jun 23 05:21:12 PM PDT 24
Peak memory 205876 kb
Host smart-891df261-7656-4421-96a7-cf1e7dd2691e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17704
2083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.177042083
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.602847436
Short name T772
Test name
Test status
Simulation time 231098873 ps
CPU time 0.93 seconds
Started Jun 23 05:21:13 PM PDT 24
Finished Jun 23 05:21:15 PM PDT 24
Peak memory 206120 kb
Host smart-b2a6650b-b3d7-449a-9c4e-1ca345ff8898
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=602847436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.602847436
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.913006852
Short name T1321
Test name
Test status
Simulation time 149618773 ps
CPU time 0.77 seconds
Started Jun 23 05:21:11 PM PDT 24
Finished Jun 23 05:21:12 PM PDT 24
Peak memory 206116 kb
Host smart-39a796b5-a2f7-4850-be4e-04686c78cce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91300
6852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.913006852
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1888277663
Short name T736
Test name
Test status
Simulation time 61045374 ps
CPU time 0.73 seconds
Started Jun 23 05:21:08 PM PDT 24
Finished Jun 23 05:21:09 PM PDT 24
Peak memory 206044 kb
Host smart-bf81fb4b-28d7-409c-8826-4224e761b654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18882
77663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1888277663
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1374431125
Short name T227
Test name
Test status
Simulation time 6170790927 ps
CPU time 13.96 seconds
Started Jun 23 05:21:07 PM PDT 24
Finished Jun 23 05:21:22 PM PDT 24
Peak memory 206148 kb
Host smart-c69a6dad-c3e6-49d3-91bb-7d01d86dd15b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13744
31125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1374431125
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3703558201
Short name T1941
Test name
Test status
Simulation time 237681980 ps
CPU time 0.9 seconds
Started Jun 23 05:21:01 PM PDT 24
Finished Jun 23 05:21:03 PM PDT 24
Peak memory 206256 kb
Host smart-ace83bf8-a5a6-4d49-9db0-675277029130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37035
58201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3703558201
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1743695902
Short name T2224
Test name
Test status
Simulation time 208480267 ps
CPU time 0.88 seconds
Started Jun 23 05:21:11 PM PDT 24
Finished Jun 23 05:21:12 PM PDT 24
Peak memory 205876 kb
Host smart-324cdcd8-ae1b-4390-b782-d85eb3313243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17436
95902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1743695902
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3489332923
Short name T2338
Test name
Test status
Simulation time 204448925 ps
CPU time 0.85 seconds
Started Jun 23 05:21:06 PM PDT 24
Finished Jun 23 05:21:08 PM PDT 24
Peak memory 206124 kb
Host smart-966833a0-cf5f-4b84-bcc8-8ce8090a98b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34893
32923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3489332923
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.1972528720
Short name T551
Test name
Test status
Simulation time 218554373 ps
CPU time 0.88 seconds
Started Jun 23 05:21:10 PM PDT 24
Finished Jun 23 05:21:11 PM PDT 24
Peak memory 206124 kb
Host smart-ff87eaa5-953c-4295-bbb0-a7f078148c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19725
28720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.1972528720
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.2133184328
Short name T1538
Test name
Test status
Simulation time 224411982 ps
CPU time 0.91 seconds
Started Jun 23 05:21:08 PM PDT 24
Finished Jun 23 05:21:09 PM PDT 24
Peak memory 206068 kb
Host smart-70b25453-c4de-425b-b489-3ece43a5215e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21331
84328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.2133184328
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.4274193615
Short name T378
Test name
Test status
Simulation time 178335194 ps
CPU time 0.84 seconds
Started Jun 23 05:21:04 PM PDT 24
Finished Jun 23 05:21:06 PM PDT 24
Peak memory 206016 kb
Host smart-948c92f2-a91f-4566-bd07-47277fc02f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42741
93615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.4274193615
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1515152848
Short name T1988
Test name
Test status
Simulation time 179271538 ps
CPU time 0.81 seconds
Started Jun 23 05:21:06 PM PDT 24
Finished Jun 23 05:21:07 PM PDT 24
Peak memory 206060 kb
Host smart-42e01b97-b9d8-4416-b3a3-b4e6e7b56721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15151
52848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1515152848
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2670161824
Short name T1714
Test name
Test status
Simulation time 209411310 ps
CPU time 0.95 seconds
Started Jun 23 05:20:58 PM PDT 24
Finished Jun 23 05:20:59 PM PDT 24
Peak memory 206108 kb
Host smart-5f1009e9-3457-4c49-a489-863deaf79e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26701
61824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2670161824
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.320413970
Short name T1070
Test name
Test status
Simulation time 7369263550 ps
CPU time 56.39 seconds
Started Jun 23 05:21:06 PM PDT 24
Finished Jun 23 05:22:03 PM PDT 24
Peak memory 206520 kb
Host smart-8e9294e7-87f3-4ee3-8ea5-977c54e108bf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=320413970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.320413970
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2545232886
Short name T801
Test name
Test status
Simulation time 233580302 ps
CPU time 0.89 seconds
Started Jun 23 05:21:07 PM PDT 24
Finished Jun 23 05:21:08 PM PDT 24
Peak memory 206112 kb
Host smart-5901b5c0-826d-4fea-a8ca-980732c79445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25452
32886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2545232886
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.2416719293
Short name T2086
Test name
Test status
Simulation time 186233806 ps
CPU time 0.82 seconds
Started Jun 23 05:21:07 PM PDT 24
Finished Jun 23 05:21:08 PM PDT 24
Peak memory 206068 kb
Host smart-6b059149-21e1-4f07-9448-d2d676514fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24167
19293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.2416719293
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.2674368202
Short name T2324
Test name
Test status
Simulation time 5148327536 ps
CPU time 52.54 seconds
Started Jun 23 05:21:08 PM PDT 24
Finished Jun 23 05:22:01 PM PDT 24
Peak memory 206320 kb
Host smart-7eba62c4-e0a0-49e7-9669-d0540d44623f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26743
68202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.2674368202
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.3670980261
Short name T1195
Test name
Test status
Simulation time 4068369883 ps
CPU time 5.55 seconds
Started Jun 23 05:21:13 PM PDT 24
Finished Jun 23 05:21:19 PM PDT 24
Peak memory 206180 kb
Host smart-e936750a-d62b-4d44-b8bf-4c00b756c384
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3670980261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.3670980261
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2142190000
Short name T1261
Test name
Test status
Simulation time 13296090194 ps
CPU time 16.24 seconds
Started Jun 23 05:21:07 PM PDT 24
Finished Jun 23 05:21:24 PM PDT 24
Peak memory 206160 kb
Host smart-8777b8cd-6d5c-4a50-b7a8-75ada9988f6a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2142190000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2142190000
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.1212010290
Short name T2290
Test name
Test status
Simulation time 23370082978 ps
CPU time 22.99 seconds
Started Jun 23 05:21:07 PM PDT 24
Finished Jun 23 05:21:30 PM PDT 24
Peak memory 206376 kb
Host smart-eb161c2e-df2b-472d-8cef-e237b5e0ae15
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1212010290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.1212010290
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.404429520
Short name T32
Test name
Test status
Simulation time 145663192 ps
CPU time 0.8 seconds
Started Jun 23 05:21:12 PM PDT 24
Finished Jun 23 05:21:14 PM PDT 24
Peak memory 206108 kb
Host smart-8ea182e8-5097-44a5-8942-1cc6e5ca1eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40442
9520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.404429520
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.2482548384
Short name T2274
Test name
Test status
Simulation time 156805712 ps
CPU time 0.77 seconds
Started Jun 23 05:21:07 PM PDT 24
Finished Jun 23 05:21:09 PM PDT 24
Peak memory 206032 kb
Host smart-102dd696-3334-45e9-9256-8198e968a833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24825
48384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.2482548384
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.1630405979
Short name T1266
Test name
Test status
Simulation time 502878757 ps
CPU time 1.67 seconds
Started Jun 23 05:21:14 PM PDT 24
Finished Jun 23 05:21:16 PM PDT 24
Peak memory 206212 kb
Host smart-9dca9d86-2e4c-43cf-a470-f6d0a64183cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16304
05979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.1630405979
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.332876372
Short name T568
Test name
Test status
Simulation time 774397585 ps
CPU time 1.87 seconds
Started Jun 23 05:21:11 PM PDT 24
Finished Jun 23 05:21:13 PM PDT 24
Peak memory 206328 kb
Host smart-9760cfc4-88c2-42a5-8f51-0e5f9e581e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33287
6372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.332876372
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.3092113631
Short name T2040
Test name
Test status
Simulation time 11422060541 ps
CPU time 26.4 seconds
Started Jun 23 05:21:13 PM PDT 24
Finished Jun 23 05:21:40 PM PDT 24
Peak memory 206424 kb
Host smart-cdc5b33b-f366-4a0e-92d5-2ba8c91d68d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30921
13631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.3092113631
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.3411897659
Short name T1646
Test name
Test status
Simulation time 331910349 ps
CPU time 1.18 seconds
Started Jun 23 05:21:13 PM PDT 24
Finished Jun 23 05:21:14 PM PDT 24
Peak memory 206108 kb
Host smart-b7c8c46f-c684-442a-8dc6-7c6a2a6259ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34118
97659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.3411897659
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.2147644337
Short name T594
Test name
Test status
Simulation time 151351721 ps
CPU time 0.8 seconds
Started Jun 23 05:21:13 PM PDT 24
Finished Jun 23 05:21:14 PM PDT 24
Peak memory 206100 kb
Host smart-593e96e1-0f23-48c2-b7ff-eb876cf6dc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21476
44337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.2147644337
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.2930973657
Short name T1997
Test name
Test status
Simulation time 92002782 ps
CPU time 0.71 seconds
Started Jun 23 05:21:12 PM PDT 24
Finished Jun 23 05:21:13 PM PDT 24
Peak memory 206108 kb
Host smart-f8ccaba7-097c-40a3-ac40-c5cd31126df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29309
73657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2930973657
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.1754647449
Short name T1961
Test name
Test status
Simulation time 919242479 ps
CPU time 2.21 seconds
Started Jun 23 05:21:14 PM PDT 24
Finished Jun 23 05:21:17 PM PDT 24
Peak memory 206308 kb
Host smart-b071c3a2-e422-4b1a-82e8-b45515b2b717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17546
47449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.1754647449
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.238281853
Short name T1732
Test name
Test status
Simulation time 190240880 ps
CPU time 1.68 seconds
Started Jun 23 05:21:13 PM PDT 24
Finished Jun 23 05:21:15 PM PDT 24
Peak memory 206264 kb
Host smart-2f459839-2127-417f-ab70-85d72e0a0509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23828
1853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.238281853
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3203622651
Short name T754
Test name
Test status
Simulation time 210003611 ps
CPU time 0.86 seconds
Started Jun 23 05:21:18 PM PDT 24
Finished Jun 23 05:21:19 PM PDT 24
Peak memory 206104 kb
Host smart-a44cf1ce-d772-40ea-9dd2-def01b4ab105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32036
22651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3203622651
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.4250712246
Short name T2017
Test name
Test status
Simulation time 149845550 ps
CPU time 0.8 seconds
Started Jun 23 05:21:22 PM PDT 24
Finished Jun 23 05:21:23 PM PDT 24
Peak memory 206100 kb
Host smart-dc0f130d-24f7-497f-ba18-8425d073d819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42507
12246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.4250712246
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.807752927
Short name T1888
Test name
Test status
Simulation time 275081884 ps
CPU time 1.01 seconds
Started Jun 23 05:21:11 PM PDT 24
Finished Jun 23 05:21:12 PM PDT 24
Peak memory 205988 kb
Host smart-9db4ff81-c6e0-400a-85de-ec5ce2cc004c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80775
2927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.807752927
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.35641794
Short name T1132
Test name
Test status
Simulation time 245337977 ps
CPU time 0.98 seconds
Started Jun 23 05:21:16 PM PDT 24
Finished Jun 23 05:21:18 PM PDT 24
Peak memory 206052 kb
Host smart-6e4dd6bb-a36c-46e4-9b3e-10a4ddb270b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35641
794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.35641794
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.111399411
Short name T1952
Test name
Test status
Simulation time 23347947923 ps
CPU time 23.04 seconds
Started Jun 23 05:21:16 PM PDT 24
Finished Jun 23 05:21:40 PM PDT 24
Peak memory 206108 kb
Host smart-7c454d95-1f07-42ef-bc29-5bed789fa1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11139
9411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.111399411
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.1545759166
Short name T410
Test name
Test status
Simulation time 3283101770 ps
CPU time 4.15 seconds
Started Jun 23 05:21:14 PM PDT 24
Finished Jun 23 05:21:18 PM PDT 24
Peak memory 206164 kb
Host smart-d4822527-e515-4817-9f6b-7095e1037424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15457
59166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.1545759166
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.44378747
Short name T1544
Test name
Test status
Simulation time 13743424668 ps
CPU time 102.08 seconds
Started Jun 23 05:21:14 PM PDT 24
Finished Jun 23 05:22:56 PM PDT 24
Peak memory 206348 kb
Host smart-ba4f19cb-e54d-4a68-b9e0-b9e35caefe3a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=44378747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.44378747
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.4065678329
Short name T2326
Test name
Test status
Simulation time 240588868 ps
CPU time 0.9 seconds
Started Jun 23 05:21:18 PM PDT 24
Finished Jun 23 05:21:19 PM PDT 24
Peak memory 206128 kb
Host smart-1e9c61a2-cdc4-467e-9415-90326f87d41a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4065678329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.4065678329
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2784074252
Short name T1187
Test name
Test status
Simulation time 230448243 ps
CPU time 0.87 seconds
Started Jun 23 05:21:16 PM PDT 24
Finished Jun 23 05:21:18 PM PDT 24
Peak memory 206060 kb
Host smart-52903152-2821-4fe0-8de3-1b4cc9031c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27840
74252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2784074252
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.3285041848
Short name T1743
Test name
Test status
Simulation time 9619289921 ps
CPU time 87.53 seconds
Started Jun 23 05:21:14 PM PDT 24
Finished Jun 23 05:22:42 PM PDT 24
Peak memory 206368 kb
Host smart-c8a4708f-b00e-4528-95ee-1d1ca596c36e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32850
41848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.3285041848
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.262621473
Short name T1848
Test name
Test status
Simulation time 5611788905 ps
CPU time 156.15 seconds
Started Jun 23 05:21:13 PM PDT 24
Finished Jun 23 05:23:50 PM PDT 24
Peak memory 206344 kb
Host smart-1c44a85c-3ed1-43c1-8e25-35bce003e464
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=262621473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.262621473
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.3191660299
Short name T896
Test name
Test status
Simulation time 157606788 ps
CPU time 0.82 seconds
Started Jun 23 05:21:18 PM PDT 24
Finished Jun 23 05:21:20 PM PDT 24
Peak memory 206128 kb
Host smart-c73e969b-f718-485e-9d24-532158a478db
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3191660299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.3191660299
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.301723769
Short name T1882
Test name
Test status
Simulation time 155954277 ps
CPU time 0.78 seconds
Started Jun 23 05:21:14 PM PDT 24
Finished Jun 23 05:21:16 PM PDT 24
Peak memory 206044 kb
Host smart-dc187881-09e5-4d7a-80cc-fe7ac15afe63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30172
3769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.301723769
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3528722102
Short name T113
Test name
Test status
Simulation time 188548598 ps
CPU time 0.89 seconds
Started Jun 23 05:21:14 PM PDT 24
Finished Jun 23 05:21:15 PM PDT 24
Peak memory 206044 kb
Host smart-5edf19d4-b4db-4a8c-8e30-c1ab3c6eae90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35287
22102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3528722102
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.3690062855
Short name T1378
Test name
Test status
Simulation time 170770772 ps
CPU time 0.83 seconds
Started Jun 23 05:21:12 PM PDT 24
Finished Jun 23 05:21:13 PM PDT 24
Peak memory 206096 kb
Host smart-934abc5f-15f0-4834-9e50-953ba2409c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36900
62855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3690062855
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1919262451
Short name T354
Test name
Test status
Simulation time 180219777 ps
CPU time 0.81 seconds
Started Jun 23 05:21:14 PM PDT 24
Finished Jun 23 05:21:16 PM PDT 24
Peak memory 206104 kb
Host smart-87cbb357-8705-4ec2-a296-7d64f73b56eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19192
62451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1919262451
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1340684260
Short name T1025
Test name
Test status
Simulation time 151728030 ps
CPU time 0.79 seconds
Started Jun 23 05:21:12 PM PDT 24
Finished Jun 23 05:21:14 PM PDT 24
Peak memory 206120 kb
Host smart-c0a62749-786b-4e1d-9913-9d28d0059451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13406
84260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1340684260
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1119665676
Short name T2215
Test name
Test status
Simulation time 183633597 ps
CPU time 0.88 seconds
Started Jun 23 05:21:17 PM PDT 24
Finished Jun 23 05:21:18 PM PDT 24
Peak memory 206104 kb
Host smart-3b5782bc-c4ea-43e6-9003-a84004839aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11196
65676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1119665676
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.120867907
Short name T2315
Test name
Test status
Simulation time 221348279 ps
CPU time 1.05 seconds
Started Jun 23 05:21:19 PM PDT 24
Finished Jun 23 05:21:21 PM PDT 24
Peak memory 206120 kb
Host smart-aec50e2b-3ac0-4cfd-82ef-789fb8d39b06
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=120867907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.120867907
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3419755623
Short name T1322
Test name
Test status
Simulation time 143715733 ps
CPU time 0.82 seconds
Started Jun 23 05:21:22 PM PDT 24
Finished Jun 23 05:21:23 PM PDT 24
Peak memory 206112 kb
Host smart-eb346895-7d96-498a-8e21-0d46d39161cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34197
55623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3419755623
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.761375016
Short name T679
Test name
Test status
Simulation time 38077154 ps
CPU time 0.67 seconds
Started Jun 23 05:21:20 PM PDT 24
Finished Jun 23 05:21:21 PM PDT 24
Peak memory 206104 kb
Host smart-70c4edc9-d012-46ba-9518-36c0cb590a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76137
5016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.761375016
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1898315566
Short name T1508
Test name
Test status
Simulation time 11610115006 ps
CPU time 25.21 seconds
Started Jun 23 05:21:12 PM PDT 24
Finished Jun 23 05:21:38 PM PDT 24
Peak memory 206352 kb
Host smart-1ddcf173-c89b-4db9-ad44-196934a899a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18983
15566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1898315566
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3269268511
Short name T646
Test name
Test status
Simulation time 193408295 ps
CPU time 0.81 seconds
Started Jun 23 05:21:12 PM PDT 24
Finished Jun 23 05:21:13 PM PDT 24
Peak memory 206096 kb
Host smart-360063d9-230b-4cd3-aec8-a6b5b0c41e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32692
68511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3269268511
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2070367460
Short name T1808
Test name
Test status
Simulation time 163156746 ps
CPU time 0.86 seconds
Started Jun 23 05:21:12 PM PDT 24
Finished Jun 23 05:21:14 PM PDT 24
Peak memory 206056 kb
Host smart-6b200578-f87b-4228-8aff-3d6d71bd72d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20703
67460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2070367460
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.169148338
Short name T1855
Test name
Test status
Simulation time 234879055 ps
CPU time 0.9 seconds
Started Jun 23 05:21:18 PM PDT 24
Finished Jun 23 05:21:19 PM PDT 24
Peak memory 206072 kb
Host smart-b89ece6f-8e74-47ba-899b-ab4b5800cee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16914
8338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.169148338
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.3357502813
Short name T527
Test name
Test status
Simulation time 169140306 ps
CPU time 0.81 seconds
Started Jun 23 05:21:12 PM PDT 24
Finished Jun 23 05:21:13 PM PDT 24
Peak memory 206056 kb
Host smart-2f248c8b-17a3-4207-9f68-5cabfa4315d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33575
02813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3357502813
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2003710248
Short name T1392
Test name
Test status
Simulation time 140493966 ps
CPU time 0.77 seconds
Started Jun 23 05:21:19 PM PDT 24
Finished Jun 23 05:21:20 PM PDT 24
Peak memory 206100 kb
Host smart-05d4081a-5863-417c-b361-ae2c594a5355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20037
10248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2003710248
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2687071456
Short name T1937
Test name
Test status
Simulation time 157950289 ps
CPU time 0.77 seconds
Started Jun 23 05:21:19 PM PDT 24
Finished Jun 23 05:21:20 PM PDT 24
Peak memory 206116 kb
Host smart-5baad956-b630-4230-b3a7-3f9bea1fd7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26870
71456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2687071456
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2366934731
Short name T1665
Test name
Test status
Simulation time 149873961 ps
CPU time 0.79 seconds
Started Jun 23 05:21:17 PM PDT 24
Finished Jun 23 05:21:19 PM PDT 24
Peak memory 206060 kb
Host smart-ed4a58e0-4b2f-483a-acb1-3aefeb396438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23669
34731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2366934731
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2484438026
Short name T1418
Test name
Test status
Simulation time 246351757 ps
CPU time 0.93 seconds
Started Jun 23 05:21:08 PM PDT 24
Finished Jun 23 05:21:09 PM PDT 24
Peak memory 206124 kb
Host smart-36b7ea97-8d51-4ee5-8ad9-356ccf6876f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24844
38026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2484438026
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.925100512
Short name T1982
Test name
Test status
Simulation time 5840658483 ps
CPU time 55.75 seconds
Started Jun 23 05:21:18 PM PDT 24
Finished Jun 23 05:22:14 PM PDT 24
Peak memory 206356 kb
Host smart-fa725fdd-5ddc-40db-904f-d78f6347b03a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=925100512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.925100512
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3786185594
Short name T914
Test name
Test status
Simulation time 164997037 ps
CPU time 0.82 seconds
Started Jun 23 05:21:17 PM PDT 24
Finished Jun 23 05:21:19 PM PDT 24
Peak memory 206064 kb
Host smart-5a43cc07-063d-4dda-8534-28e0946156e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37861
85594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3786185594
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3640327349
Short name T2093
Test name
Test status
Simulation time 182814300 ps
CPU time 0.8 seconds
Started Jun 23 05:21:17 PM PDT 24
Finished Jun 23 05:21:19 PM PDT 24
Peak memory 206100 kb
Host smart-097d9c5e-49f0-4827-8ce6-605aa3cbaa95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36403
27349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3640327349
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2030662144
Short name T523
Test name
Test status
Simulation time 14664381533 ps
CPU time 404.12 seconds
Started Jun 23 05:21:16 PM PDT 24
Finished Jun 23 05:28:00 PM PDT 24
Peak memory 206324 kb
Host smart-19b48b22-9a65-48e4-ac68-ad000f8c8c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20306
62144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2030662144
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2613439731
Short name T905
Test name
Test status
Simulation time 4103631393 ps
CPU time 4.68 seconds
Started Jun 23 05:21:17 PM PDT 24
Finished Jun 23 05:21:22 PM PDT 24
Peak memory 206332 kb
Host smart-f91b4e36-bc07-4e4d-924d-138a7c14388e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2613439731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.2613439731
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.2612776534
Short name T1243
Test name
Test status
Simulation time 13395439074 ps
CPU time 13.61 seconds
Started Jun 23 05:21:22 PM PDT 24
Finished Jun 23 05:21:36 PM PDT 24
Peak memory 206164 kb
Host smart-d6b1d91f-6ea4-4d49-a949-ce2cacbc9d34
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2612776534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.2612776534
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.3807649302
Short name T1083
Test name
Test status
Simulation time 23359070942 ps
CPU time 28.69 seconds
Started Jun 23 05:21:25 PM PDT 24
Finished Jun 23 05:21:54 PM PDT 24
Peak memory 206164 kb
Host smart-91d71746-6860-4631-97f3-938db98add7b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3807649302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.3807649302
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.925863524
Short name T2262
Test name
Test status
Simulation time 178416344 ps
CPU time 0.81 seconds
Started Jun 23 05:21:23 PM PDT 24
Finished Jun 23 05:21:24 PM PDT 24
Peak memory 206116 kb
Host smart-298b1339-741e-4e01-a33a-b71cb0ee4535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92586
3524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.925863524
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.369452518
Short name T2436
Test name
Test status
Simulation time 145345637 ps
CPU time 0.78 seconds
Started Jun 23 05:21:22 PM PDT 24
Finished Jun 23 05:21:23 PM PDT 24
Peak memory 206044 kb
Host smart-66e1abb9-24ca-4818-9bf8-d8c95833f9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36945
2518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.369452518
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.4212499345
Short name T2443
Test name
Test status
Simulation time 315348522 ps
CPU time 1.07 seconds
Started Jun 23 05:21:24 PM PDT 24
Finished Jun 23 05:21:26 PM PDT 24
Peak memory 206024 kb
Host smart-d4067925-3b62-4169-8eb5-ca7dbdb053a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42124
99345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.4212499345
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.492479978
Short name T1189
Test name
Test status
Simulation time 395577052 ps
CPU time 1.19 seconds
Started Jun 23 05:21:23 PM PDT 24
Finished Jun 23 05:21:25 PM PDT 24
Peak memory 206052 kb
Host smart-98fbc487-9e14-45d0-b9ed-daeeb58b96de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49247
9978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.492479978
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.1824125231
Short name T1084
Test name
Test status
Simulation time 21342697037 ps
CPU time 43.44 seconds
Started Jun 23 05:21:24 PM PDT 24
Finished Jun 23 05:22:08 PM PDT 24
Peak memory 206384 kb
Host smart-115d7542-ec8a-4cff-b69a-ffd53bb14220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18241
25231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.1824125231
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.1230593358
Short name T2023
Test name
Test status
Simulation time 350611727 ps
CPU time 1.16 seconds
Started Jun 23 05:21:24 PM PDT 24
Finished Jun 23 05:21:26 PM PDT 24
Peak memory 206028 kb
Host smart-bbe25aac-d1c3-45b4-a033-5e6485282d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12305
93358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.1230593358
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2570913746
Short name T2484
Test name
Test status
Simulation time 146988976 ps
CPU time 0.75 seconds
Started Jun 23 05:21:22 PM PDT 24
Finished Jun 23 05:21:24 PM PDT 24
Peak memory 206116 kb
Host smart-4e8ff31a-6dc7-44d2-90d1-df184ac46caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25709
13746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2570913746
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.1431423132
Short name T2160
Test name
Test status
Simulation time 36543919 ps
CPU time 0.65 seconds
Started Jun 23 05:21:22 PM PDT 24
Finished Jun 23 05:21:23 PM PDT 24
Peak memory 206088 kb
Host smart-cb8b9dbc-dcb9-4c0e-a89b-72ec0341ba88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14314
23132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1431423132
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.517852560
Short name T1164
Test name
Test status
Simulation time 917764460 ps
CPU time 2.41 seconds
Started Jun 23 05:21:36 PM PDT 24
Finished Jun 23 05:21:39 PM PDT 24
Peak memory 206308 kb
Host smart-58a640af-fd44-4652-8fab-96eef6688ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51785
2560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.517852560
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3307880427
Short name T181
Test name
Test status
Simulation time 205526752 ps
CPU time 2.04 seconds
Started Jun 23 05:21:28 PM PDT 24
Finished Jun 23 05:21:31 PM PDT 24
Peak memory 206264 kb
Host smart-5be3d019-c53f-4b83-9831-9681b2434127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33078
80427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3307880427
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.2784968617
Short name T1382
Test name
Test status
Simulation time 235303933 ps
CPU time 0.91 seconds
Started Jun 23 05:21:29 PM PDT 24
Finished Jun 23 05:21:31 PM PDT 24
Peak memory 206024 kb
Host smart-6cb4ca9f-1400-409f-ad77-7934bcba4f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27849
68617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.2784968617
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.220107191
Short name T951
Test name
Test status
Simulation time 147952614 ps
CPU time 0.78 seconds
Started Jun 23 05:21:27 PM PDT 24
Finished Jun 23 05:21:28 PM PDT 24
Peak memory 206100 kb
Host smart-b782595c-fd80-4371-8e23-971d5e515bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22010
7191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.220107191
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2189241446
Short name T1212
Test name
Test status
Simulation time 206516144 ps
CPU time 0.98 seconds
Started Jun 23 05:21:26 PM PDT 24
Finished Jun 23 05:21:27 PM PDT 24
Peak memory 206292 kb
Host smart-34d98512-2aa7-4d38-b817-e4c80e1a7bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21892
41446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2189241446
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.2482751155
Short name T2038
Test name
Test status
Simulation time 177204315 ps
CPU time 0.79 seconds
Started Jun 23 05:21:22 PM PDT 24
Finished Jun 23 05:21:24 PM PDT 24
Peak memory 206032 kb
Host smart-138654e5-5e0a-4431-8255-8ef8e7812986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24827
51155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.2482751155
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.727975972
Short name T975
Test name
Test status
Simulation time 23333025927 ps
CPU time 22.95 seconds
Started Jun 23 05:21:26 PM PDT 24
Finished Jun 23 05:21:49 PM PDT 24
Peak memory 206060 kb
Host smart-be114e00-3d90-4f5d-9879-51fab42adb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72797
5972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.727975972
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.801299060
Short name T526
Test name
Test status
Simulation time 3281349671 ps
CPU time 4.19 seconds
Started Jun 23 05:21:25 PM PDT 24
Finished Jun 23 05:21:30 PM PDT 24
Peak memory 206168 kb
Host smart-4b089317-cb40-4b6f-8864-216f30263df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80129
9060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.801299060
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.32676485
Short name T1537
Test name
Test status
Simulation time 4950904035 ps
CPU time 33.05 seconds
Started Jun 23 05:21:22 PM PDT 24
Finished Jun 23 05:21:56 PM PDT 24
Peak memory 206368 kb
Host smart-f6834e6d-8333-418f-b8fc-5563aaf16ed5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=32676485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.32676485
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.927887979
Short name T2430
Test name
Test status
Simulation time 324436881 ps
CPU time 0.99 seconds
Started Jun 23 05:21:27 PM PDT 24
Finished Jun 23 05:21:29 PM PDT 24
Peak memory 206096 kb
Host smart-e8d5da79-1a6d-4608-873b-d6ee09c8a1a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=927887979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.927887979
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2707413041
Short name T374
Test name
Test status
Simulation time 227769984 ps
CPU time 0.9 seconds
Started Jun 23 05:21:25 PM PDT 24
Finished Jun 23 05:21:26 PM PDT 24
Peak memory 206052 kb
Host smart-ce8a2ba0-03ec-4c08-8f83-b66cc35188a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27074
13041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2707413041
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.327465859
Short name T993
Test name
Test status
Simulation time 11359727733 ps
CPU time 103.36 seconds
Started Jun 23 05:21:28 PM PDT 24
Finished Jun 23 05:23:13 PM PDT 24
Peak memory 206280 kb
Host smart-5eb4501b-5264-4f73-838b-a7b08dd3e4da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32746
5859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.327465859
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.3708629468
Short name T144
Test name
Test status
Simulation time 2753064209 ps
CPU time 27.72 seconds
Started Jun 23 05:21:23 PM PDT 24
Finished Jun 23 05:21:51 PM PDT 24
Peak memory 206344 kb
Host smart-9c16eb45-492c-43e0-8e0f-6ab1abca86ec
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3708629468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.3708629468
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.4267182723
Short name T1758
Test name
Test status
Simulation time 148975700 ps
CPU time 0.75 seconds
Started Jun 23 05:21:30 PM PDT 24
Finished Jun 23 05:21:32 PM PDT 24
Peak memory 206132 kb
Host smart-6cc2c46c-c4d5-4156-8c0a-1cebc89a6d5a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4267182723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.4267182723
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2085065523
Short name T2191
Test name
Test status
Simulation time 194223191 ps
CPU time 0.83 seconds
Started Jun 23 05:21:28 PM PDT 24
Finished Jun 23 05:21:30 PM PDT 24
Peak memory 206112 kb
Host smart-00239515-c21d-4071-aa8c-288ba05a6889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20850
65523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2085065523
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3238296337
Short name T1744
Test name
Test status
Simulation time 215359645 ps
CPU time 0.86 seconds
Started Jun 23 05:21:24 PM PDT 24
Finished Jun 23 05:21:26 PM PDT 24
Peak memory 206104 kb
Host smart-ef496a5b-54f4-4886-add2-7c04beeda297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32382
96337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3238296337
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.2171103455
Short name T1626
Test name
Test status
Simulation time 171471749 ps
CPU time 0.83 seconds
Started Jun 23 05:21:24 PM PDT 24
Finished Jun 23 05:21:26 PM PDT 24
Peak memory 206104 kb
Host smart-b9e63016-8a23-4aef-bb80-799157fa78f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21711
03455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.2171103455
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.79510244
Short name T2164
Test name
Test status
Simulation time 207176677 ps
CPU time 0.9 seconds
Started Jun 23 05:21:23 PM PDT 24
Finished Jun 23 05:21:24 PM PDT 24
Peak memory 206100 kb
Host smart-cfc2d6de-8512-4a45-ba4a-ad5a251994ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79510
244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.79510244
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1096108582
Short name T1154
Test name
Test status
Simulation time 170714021 ps
CPU time 0.8 seconds
Started Jun 23 05:21:24 PM PDT 24
Finished Jun 23 05:21:25 PM PDT 24
Peak memory 206132 kb
Host smart-e53bf7db-2abc-462f-88ef-c917aae0d4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10961
08582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1096108582
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3911056330
Short name T562
Test name
Test status
Simulation time 153937974 ps
CPU time 0.78 seconds
Started Jun 23 05:21:28 PM PDT 24
Finished Jun 23 05:21:30 PM PDT 24
Peak memory 206008 kb
Host smart-2b59bcfd-185f-475c-b48a-f44a859ae4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39110
56330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3911056330
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.3420624218
Short name T765
Test name
Test status
Simulation time 272493690 ps
CPU time 0.95 seconds
Started Jun 23 05:21:27 PM PDT 24
Finished Jun 23 05:21:28 PM PDT 24
Peak memory 206052 kb
Host smart-62f49c85-c675-42f2-b4f1-1f2b21b7a710
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3420624218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.3420624218
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.806991002
Short name T1756
Test name
Test status
Simulation time 145076618 ps
CPU time 0.76 seconds
Started Jun 23 05:21:29 PM PDT 24
Finished Jun 23 05:21:31 PM PDT 24
Peak memory 206144 kb
Host smart-45ad5daa-4934-4194-8a08-3e44bbfba6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80699
1002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.806991002
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.2598129406
Short name T756
Test name
Test status
Simulation time 38949101 ps
CPU time 0.69 seconds
Started Jun 23 05:21:29 PM PDT 24
Finished Jun 23 05:21:31 PM PDT 24
Peak memory 206124 kb
Host smart-bb20da50-7f30-4648-b1df-8f875120ca34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25981
29406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2598129406
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1861413662
Short name T1862
Test name
Test status
Simulation time 20441538292 ps
CPU time 48.82 seconds
Started Jun 23 05:21:21 PM PDT 24
Finished Jun 23 05:22:10 PM PDT 24
Peak memory 206416 kb
Host smart-a22f119e-775f-41cd-b111-42ebf5e125cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18614
13662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1861413662
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.173084636
Short name T2122
Test name
Test status
Simulation time 155474984 ps
CPU time 0.79 seconds
Started Jun 23 05:21:28 PM PDT 24
Finished Jun 23 05:21:30 PM PDT 24
Peak memory 206104 kb
Host smart-9ec51266-3dc2-4686-b0aa-9106c5995dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17308
4636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.173084636
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.2904969511
Short name T2400
Test name
Test status
Simulation time 257596898 ps
CPU time 0.87 seconds
Started Jun 23 05:21:22 PM PDT 24
Finished Jun 23 05:21:23 PM PDT 24
Peak memory 205988 kb
Host smart-150fde63-068b-48c6-9b9b-c82fee528509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29049
69511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2904969511
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.1308154670
Short name T572
Test name
Test status
Simulation time 177475314 ps
CPU time 0.81 seconds
Started Jun 23 05:21:27 PM PDT 24
Finished Jun 23 05:21:29 PM PDT 24
Peak memory 206108 kb
Host smart-d90dc734-d987-436a-9597-9cf087d9bdfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13081
54670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.1308154670
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.1151382870
Short name T2069
Test name
Test status
Simulation time 213343994 ps
CPU time 0.89 seconds
Started Jun 23 05:21:24 PM PDT 24
Finished Jun 23 05:21:26 PM PDT 24
Peak memory 206040 kb
Host smart-4200b88b-0b0a-462e-8f65-fe96b2d0cb77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11513
82870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.1151382870
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3173507606
Short name T1143
Test name
Test status
Simulation time 142427521 ps
CPU time 0.76 seconds
Started Jun 23 05:21:25 PM PDT 24
Finished Jun 23 05:21:27 PM PDT 24
Peak memory 206040 kb
Host smart-26405caf-3ae5-42f7-ae8e-9074e482ffd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31735
07606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3173507606
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.2315495055
Short name T1894
Test name
Test status
Simulation time 186120891 ps
CPU time 0.83 seconds
Started Jun 23 05:21:30 PM PDT 24
Finished Jun 23 05:21:32 PM PDT 24
Peak memory 206112 kb
Host smart-cd6129e1-e6cf-4313-bcfc-0d5be90a6120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23154
95055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.2315495055
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2834520348
Short name T305
Test name
Test status
Simulation time 151430349 ps
CPU time 0.87 seconds
Started Jun 23 05:21:26 PM PDT 24
Finished Jun 23 05:21:27 PM PDT 24
Peak memory 206020 kb
Host smart-8c429212-defc-4b77-aedd-1ada322ffc87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28345
20348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2834520348
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.642105504
Short name T979
Test name
Test status
Simulation time 253285322 ps
CPU time 0.96 seconds
Started Jun 23 05:21:18 PM PDT 24
Finished Jun 23 05:21:19 PM PDT 24
Peak memory 206072 kb
Host smart-0df55874-01f6-4c0e-9890-1652f8b3cbe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64210
5504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.642105504
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.4014559578
Short name T566
Test name
Test status
Simulation time 10798362056 ps
CPU time 310.79 seconds
Started Jun 23 05:21:24 PM PDT 24
Finished Jun 23 05:26:36 PM PDT 24
Peak memory 206260 kb
Host smart-63df783f-72c8-4ce3-8376-734c17a6b8e0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4014559578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.4014559578
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.20928341
Short name T742
Test name
Test status
Simulation time 186655307 ps
CPU time 0.78 seconds
Started Jun 23 05:21:21 PM PDT 24
Finished Jun 23 05:21:23 PM PDT 24
Peak memory 206104 kb
Host smart-30df50de-23d2-4193-ba6e-27e92f06b2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20928
341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.20928341
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2264854911
Short name T308
Test name
Test status
Simulation time 180361943 ps
CPU time 0.85 seconds
Started Jun 23 05:21:23 PM PDT 24
Finished Jun 23 05:21:25 PM PDT 24
Peak memory 206100 kb
Host smart-7d07c96f-06f9-4fa1-9078-51633b253e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22648
54911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2264854911
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.216719411
Short name T2167
Test name
Test status
Simulation time 10858624651 ps
CPU time 302.37 seconds
Started Jun 23 05:21:28 PM PDT 24
Finished Jun 23 05:26:32 PM PDT 24
Peak memory 206328 kb
Host smart-984aa00c-ad08-46f0-9451-ca7444061881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21671
9411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.216719411
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.904101030
Short name T442
Test name
Test status
Simulation time 4171774907 ps
CPU time 5.45 seconds
Started Jun 23 05:21:29 PM PDT 24
Finished Jun 23 05:21:36 PM PDT 24
Peak memory 206316 kb
Host smart-a404a008-073c-424b-ac75-f1cc1cc8f645
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=904101030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.904101030
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.1594790042
Short name T2447
Test name
Test status
Simulation time 13328297377 ps
CPU time 11.78 seconds
Started Jun 23 05:21:29 PM PDT 24
Finished Jun 23 05:21:41 PM PDT 24
Peak memory 206380 kb
Host smart-b6ee5fcb-a77b-4f3c-a781-40bc0c187e10
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1594790042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.1594790042
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.3941681406
Short name T1595
Test name
Test status
Simulation time 23317002342 ps
CPU time 22.86 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:22:02 PM PDT 24
Peak memory 206088 kb
Host smart-efa852de-9b84-4154-b1da-0297c33679ec
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3941681406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.3941681406
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2928890687
Short name T586
Test name
Test status
Simulation time 196821006 ps
CPU time 0.81 seconds
Started Jun 23 05:21:31 PM PDT 24
Finished Jun 23 05:21:32 PM PDT 24
Peak memory 206108 kb
Host smart-3b2d0428-6007-48c4-86b5-a87d872835bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29288
90687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2928890687
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.629673829
Short name T2366
Test name
Test status
Simulation time 149280588 ps
CPU time 0.8 seconds
Started Jun 23 05:21:27 PM PDT 24
Finished Jun 23 05:21:28 PM PDT 24
Peak memory 205876 kb
Host smart-3f425f96-5185-47fa-81db-db203d6ca0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62967
3829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.629673829
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.1680796272
Short name T176
Test name
Test status
Simulation time 387607866 ps
CPU time 1.34 seconds
Started Jun 23 05:21:28 PM PDT 24
Finished Jun 23 05:21:30 PM PDT 24
Peak memory 206100 kb
Host smart-d20cc795-b5a5-4b93-a2d0-7a69a80e2be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16807
96272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.1680796272
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3275853622
Short name T1900
Test name
Test status
Simulation time 496102943 ps
CPU time 1.35 seconds
Started Jun 23 05:21:27 PM PDT 24
Finished Jun 23 05:21:30 PM PDT 24
Peak memory 206108 kb
Host smart-da500e99-a3b3-4a86-a0bf-fc5eab9f0e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32758
53622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3275853622
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.1289735620
Short name T168
Test name
Test status
Simulation time 19906082942 ps
CPU time 37.07 seconds
Started Jun 23 05:21:29 PM PDT 24
Finished Jun 23 05:22:08 PM PDT 24
Peak memory 206284 kb
Host smart-d2ac4d78-aafa-42b4-ac8e-e7f0f379c6c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12897
35620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.1289735620
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.820211917
Short name T2015
Test name
Test status
Simulation time 422889434 ps
CPU time 1.35 seconds
Started Jun 23 05:21:27 PM PDT 24
Finished Jun 23 05:21:30 PM PDT 24
Peak memory 206104 kb
Host smart-7b8c1428-3687-4003-91ed-863d83fdf242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82021
1917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.820211917
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1783823631
Short name T1420
Test name
Test status
Simulation time 158513191 ps
CPU time 0.83 seconds
Started Jun 23 05:21:26 PM PDT 24
Finished Jun 23 05:21:27 PM PDT 24
Peak memory 206060 kb
Host smart-ccd992fa-2052-48e7-a84b-4b9a19879500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17838
23631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1783823631
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.1163292242
Short name T1638
Test name
Test status
Simulation time 32054114 ps
CPU time 0.63 seconds
Started Jun 23 05:21:29 PM PDT 24
Finished Jun 23 05:21:31 PM PDT 24
Peak memory 206040 kb
Host smart-9e2a05af-a743-4058-8420-27d9a6823870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11632
92242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1163292242
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3943311450
Short name T1631
Test name
Test status
Simulation time 866946609 ps
CPU time 2.06 seconds
Started Jun 23 05:21:27 PM PDT 24
Finished Jun 23 05:21:30 PM PDT 24
Peak memory 206200 kb
Host smart-d086613e-14eb-4db4-8173-2f9a450becde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39433
11450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3943311450
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1204924471
Short name T595
Test name
Test status
Simulation time 157935642 ps
CPU time 1.44 seconds
Started Jun 23 05:21:29 PM PDT 24
Finished Jun 23 05:21:32 PM PDT 24
Peak memory 206256 kb
Host smart-f99b2c00-d376-4a30-a621-94a83f4504d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12049
24471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1204924471
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3192165270
Short name T925
Test name
Test status
Simulation time 173951514 ps
CPU time 0.83 seconds
Started Jun 23 05:21:36 PM PDT 24
Finished Jun 23 05:21:38 PM PDT 24
Peak memory 206088 kb
Host smart-4e9ada87-f336-48f3-b52b-112ba28988c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31921
65270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3192165270
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.742303614
Short name T608
Test name
Test status
Simulation time 176800478 ps
CPU time 0.78 seconds
Started Jun 23 05:21:33 PM PDT 24
Finished Jun 23 05:21:34 PM PDT 24
Peak memory 206100 kb
Host smart-4379f8a3-bf61-438b-b6b0-548f2083e1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74230
3614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.742303614
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.1588562743
Short name T2039
Test name
Test status
Simulation time 228645287 ps
CPU time 0.88 seconds
Started Jun 23 05:21:28 PM PDT 24
Finished Jun 23 05:21:30 PM PDT 24
Peak memory 206080 kb
Host smart-cee5e5c9-b7bf-4e75-81fe-26a3bf916720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15885
62743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1588562743
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.936767327
Short name T2470
Test name
Test status
Simulation time 193630231 ps
CPU time 0.93 seconds
Started Jun 23 05:21:34 PM PDT 24
Finished Jun 23 05:21:35 PM PDT 24
Peak memory 206104 kb
Host smart-ed6b3ceb-9bd6-43c5-a563-8fca70a1e11b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93676
7327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.936767327
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.2000187453
Short name T2339
Test name
Test status
Simulation time 23264902398 ps
CPU time 27.81 seconds
Started Jun 23 05:21:28 PM PDT 24
Finished Jun 23 05:21:57 PM PDT 24
Peak memory 206140 kb
Host smart-967b1c6f-b4da-4181-b6df-39a25327c2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20001
87453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.2000187453
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.3227602373
Short name T2141
Test name
Test status
Simulation time 3278540914 ps
CPU time 3.62 seconds
Started Jun 23 05:21:30 PM PDT 24
Finished Jun 23 05:21:35 PM PDT 24
Peak memory 206168 kb
Host smart-a3ecbdbc-6acf-415e-b61d-81e10a739012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32276
02373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3227602373
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.756155673
Short name T1834
Test name
Test status
Simulation time 8967833207 ps
CPU time 85.89 seconds
Started Jun 23 05:21:30 PM PDT 24
Finished Jun 23 05:22:57 PM PDT 24
Peak memory 206416 kb
Host smart-22c604bd-150a-45a7-8a00-9885fe510a28
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=756155673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.756155673
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.1713438232
Short name T1090
Test name
Test status
Simulation time 272555980 ps
CPU time 0.91 seconds
Started Jun 23 05:21:35 PM PDT 24
Finished Jun 23 05:21:37 PM PDT 24
Peak memory 206128 kb
Host smart-901a2833-13c8-42f4-bada-3ca23a9b3f4c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1713438232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.1713438232
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3961544888
Short name T2364
Test name
Test status
Simulation time 191117389 ps
CPU time 0.87 seconds
Started Jun 23 05:21:28 PM PDT 24
Finished Jun 23 05:21:29 PM PDT 24
Peak memory 206116 kb
Host smart-b720d99d-579f-4809-89ce-6503f3ad9fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39615
44888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3961544888
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.2472628673
Short name T521
Test name
Test status
Simulation time 10036281582 ps
CPU time 264.39 seconds
Started Jun 23 05:21:28 PM PDT 24
Finished Jun 23 05:25:54 PM PDT 24
Peak memory 206276 kb
Host smart-2d6c5198-38eb-46a1-8a25-0e4cb46db209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24726
28673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.2472628673
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.617620194
Short name T838
Test name
Test status
Simulation time 8504500397 ps
CPU time 244.28 seconds
Started Jun 23 05:21:29 PM PDT 24
Finished Jun 23 05:25:34 PM PDT 24
Peak memory 206256 kb
Host smart-6067e69d-6daa-4ae0-a9e7-e4414101fbdc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=617620194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.617620194
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.1528906511
Short name T2268
Test name
Test status
Simulation time 155256571 ps
CPU time 0.84 seconds
Started Jun 23 05:21:34 PM PDT 24
Finished Jun 23 05:21:36 PM PDT 24
Peak memory 206084 kb
Host smart-5d4c6840-c90b-4066-a247-3ecf03e62266
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1528906511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1528906511
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1430746614
Short name T1287
Test name
Test status
Simulation time 138004494 ps
CPU time 0.78 seconds
Started Jun 23 05:21:30 PM PDT 24
Finished Jun 23 05:21:32 PM PDT 24
Peak memory 206112 kb
Host smart-3d367816-6d80-41d7-8ca9-132b5ab52b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14307
46614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1430746614
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.481752879
Short name T112
Test name
Test status
Simulation time 216516738 ps
CPU time 0.85 seconds
Started Jun 23 05:21:28 PM PDT 24
Finished Jun 23 05:21:30 PM PDT 24
Peak memory 206100 kb
Host smart-525fe224-e4e9-4d40-8872-d9f2d05134b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48175
2879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.481752879
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.3642644728
Short name T1515
Test name
Test status
Simulation time 174098997 ps
CPU time 0.83 seconds
Started Jun 23 05:21:31 PM PDT 24
Finished Jun 23 05:21:32 PM PDT 24
Peak memory 206060 kb
Host smart-014a7335-f173-4497-8769-1f57e51c6d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36426
44728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.3642644728
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1222245125
Short name T1108
Test name
Test status
Simulation time 175981413 ps
CPU time 0.88 seconds
Started Jun 23 05:21:31 PM PDT 24
Finished Jun 23 05:21:32 PM PDT 24
Peak memory 206096 kb
Host smart-80a22c2d-c31d-4c83-8f1c-ce400e5584ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12222
45125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1222245125
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3453029087
Short name T1347
Test name
Test status
Simulation time 212675531 ps
CPU time 0.85 seconds
Started Jun 23 05:21:29 PM PDT 24
Finished Jun 23 05:21:31 PM PDT 24
Peak memory 206116 kb
Host smart-48e18714-ca77-4044-9e17-c13fe6db6d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34530
29087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3453029087
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.4171232465
Short name T437
Test name
Test status
Simulation time 155064927 ps
CPU time 0.79 seconds
Started Jun 23 05:21:36 PM PDT 24
Finished Jun 23 05:21:38 PM PDT 24
Peak memory 206104 kb
Host smart-8cfb5a84-e78d-4e8d-b77d-332a1c8536da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41712
32465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.4171232465
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.4033335577
Short name T1156
Test name
Test status
Simulation time 268791694 ps
CPU time 1.04 seconds
Started Jun 23 05:21:33 PM PDT 24
Finished Jun 23 05:21:34 PM PDT 24
Peak memory 206096 kb
Host smart-304b2b0e-7fc3-40dc-ae81-d828e4621913
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4033335577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.4033335577
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2876400212
Short name T641
Test name
Test status
Simulation time 151094774 ps
CPU time 0.75 seconds
Started Jun 23 05:21:36 PM PDT 24
Finished Jun 23 05:21:38 PM PDT 24
Peak memory 206108 kb
Host smart-ed66a7f8-7856-4683-9b82-0e1e0a1c3bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28764
00212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2876400212
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2287410136
Short name T1498
Test name
Test status
Simulation time 42196916 ps
CPU time 0.67 seconds
Started Jun 23 05:21:32 PM PDT 24
Finished Jun 23 05:21:33 PM PDT 24
Peak memory 206056 kb
Host smart-bd5b01cc-188b-4ec4-809f-54c614688bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22874
10136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2287410136
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2554444045
Short name T1179
Test name
Test status
Simulation time 15494280588 ps
CPU time 35.51 seconds
Started Jun 23 05:21:30 PM PDT 24
Finished Jun 23 05:22:06 PM PDT 24
Peak memory 206404 kb
Host smart-0f91e26a-8f78-4cc8-a68a-54c86bcf6721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25544
44045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2554444045
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3963597472
Short name T2062
Test name
Test status
Simulation time 158066539 ps
CPU time 0.79 seconds
Started Jun 23 05:21:30 PM PDT 24
Finished Jun 23 05:21:32 PM PDT 24
Peak memory 206104 kb
Host smart-c25b3f37-8b46-48bf-8000-66f84650af7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39635
97472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3963597472
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.2464094737
Short name T2402
Test name
Test status
Simulation time 172030561 ps
CPU time 0.82 seconds
Started Jun 23 05:21:30 PM PDT 24
Finished Jun 23 05:21:31 PM PDT 24
Peak memory 206040 kb
Host smart-509cffe9-d325-4417-9afc-30c0d57020ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24640
94737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.2464094737
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2261782260
Short name T2101
Test name
Test status
Simulation time 172163267 ps
CPU time 0.85 seconds
Started Jun 23 05:21:34 PM PDT 24
Finished Jun 23 05:21:35 PM PDT 24
Peak memory 205988 kb
Host smart-def4b59a-cbb9-4530-a496-aec236323040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22617
82260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2261782260
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.2564801094
Short name T2228
Test name
Test status
Simulation time 183931775 ps
CPU time 0.84 seconds
Started Jun 23 05:21:26 PM PDT 24
Finished Jun 23 05:21:28 PM PDT 24
Peak memory 206060 kb
Host smart-a7aab6cb-d5db-4d07-a833-b1e5169c0ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25648
01094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.2564801094
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.1911134923
Short name T1053
Test name
Test status
Simulation time 159035454 ps
CPU time 0.84 seconds
Started Jun 23 05:21:33 PM PDT 24
Finished Jun 23 05:21:34 PM PDT 24
Peak memory 206088 kb
Host smart-a04ddc4a-5c12-460f-8ce8-749508d7be21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19111
34923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.1911134923
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3324239723
Short name T147
Test name
Test status
Simulation time 166977359 ps
CPU time 0.77 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:21:40 PM PDT 24
Peak memory 206100 kb
Host smart-10948268-46db-4700-a884-df296ac12856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33242
39723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3324239723
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.4045749667
Short name T2176
Test name
Test status
Simulation time 152054904 ps
CPU time 0.75 seconds
Started Jun 23 05:21:34 PM PDT 24
Finished Jun 23 05:21:36 PM PDT 24
Peak memory 206036 kb
Host smart-01ccad44-91ba-4b15-a4f4-1894c3fdc2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40457
49667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.4045749667
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1678678938
Short name T2130
Test name
Test status
Simulation time 195718771 ps
CPU time 0.88 seconds
Started Jun 23 05:21:29 PM PDT 24
Finished Jun 23 05:21:31 PM PDT 24
Peak memory 206100 kb
Host smart-4755af49-0a6a-4c23-91b4-982f8a118008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16786
78938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1678678938
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.3806362441
Short name T2058
Test name
Test status
Simulation time 6831765226 ps
CPU time 52.34 seconds
Started Jun 23 05:21:31 PM PDT 24
Finished Jun 23 05:22:24 PM PDT 24
Peak memory 206416 kb
Host smart-1b4b90fd-e89f-4996-9b85-a26ee39f561c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3806362441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.3806362441
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1459480992
Short name T1653
Test name
Test status
Simulation time 149409533 ps
CPU time 0.78 seconds
Started Jun 23 05:21:36 PM PDT 24
Finished Jun 23 05:21:38 PM PDT 24
Peak memory 206100 kb
Host smart-f553b919-3960-4270-b31d-ff724ebb37bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14594
80992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1459480992
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1478094054
Short name T887
Test name
Test status
Simulation time 163664733 ps
CPU time 0.78 seconds
Started Jun 23 05:21:27 PM PDT 24
Finished Jun 23 05:21:29 PM PDT 24
Peak memory 206108 kb
Host smart-d859ce3a-961a-4796-9811-d287b36c1ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14780
94054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1478094054
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.2748360272
Short name T1173
Test name
Test status
Simulation time 7817740585 ps
CPU time 55.12 seconds
Started Jun 23 05:21:35 PM PDT 24
Finished Jun 23 05:22:31 PM PDT 24
Peak memory 206332 kb
Host smart-e0ba7c51-cce8-4fab-a489-ae6bc6cf697c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27483
60272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2748360272
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2539848328
Short name T1307
Test name
Test status
Simulation time 3632863982 ps
CPU time 5.31 seconds
Started Jun 23 05:21:35 PM PDT 24
Finished Jun 23 05:21:42 PM PDT 24
Peak memory 206352 kb
Host smart-d14e52b4-92f7-4532-9dc3-cf345ec72c06
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2539848328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.2539848328
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.4164542740
Short name T1529
Test name
Test status
Simulation time 13358796520 ps
CPU time 14.61 seconds
Started Jun 23 05:21:35 PM PDT 24
Finished Jun 23 05:21:50 PM PDT 24
Peak memory 206248 kb
Host smart-b1784468-572a-4b1a-b254-0a9be47a2f05
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4164542740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.4164542740
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.1001896143
Short name T1348
Test name
Test status
Simulation time 23360006606 ps
CPU time 26.5 seconds
Started Jun 23 05:21:32 PM PDT 24
Finished Jun 23 05:21:59 PM PDT 24
Peak memory 206356 kb
Host smart-38562107-b956-4744-a4b3-9195c4adad4b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1001896143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.1001896143
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.791186455
Short name T295
Test name
Test status
Simulation time 184346947 ps
CPU time 0.85 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:21:39 PM PDT 24
Peak memory 206100 kb
Host smart-37bd8aaa-4456-4a86-a910-5c96a53c4a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79118
6455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.791186455
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.970261358
Short name T897
Test name
Test status
Simulation time 143465169 ps
CPU time 0.77 seconds
Started Jun 23 05:21:36 PM PDT 24
Finished Jun 23 05:21:38 PM PDT 24
Peak memory 206092 kb
Host smart-df5072a4-2f6b-4d40-a5d9-56e1e8ad375e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97026
1358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.970261358
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.719388196
Short name T165
Test name
Test status
Simulation time 243054495 ps
CPU time 1.02 seconds
Started Jun 23 05:21:33 PM PDT 24
Finished Jun 23 05:21:34 PM PDT 24
Peak memory 206064 kb
Host smart-1269be6b-2d41-4532-8516-91e2d24e4b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71938
8196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.719388196
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.1998051559
Short name T689
Test name
Test status
Simulation time 482203585 ps
CPU time 1.38 seconds
Started Jun 23 05:21:32 PM PDT 24
Finished Jun 23 05:21:33 PM PDT 24
Peak memory 206108 kb
Host smart-30e7dd99-8106-4315-a105-e9b0882dbd6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19980
51559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1998051559
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.932435098
Short name T1769
Test name
Test status
Simulation time 13816172722 ps
CPU time 27.39 seconds
Started Jun 23 05:21:36 PM PDT 24
Finished Jun 23 05:22:05 PM PDT 24
Peak memory 206344 kb
Host smart-869db719-3428-4336-8022-740b451bffdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93243
5098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.932435098
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.680637500
Short name T2059
Test name
Test status
Simulation time 348547393 ps
CPU time 1.16 seconds
Started Jun 23 05:21:36 PM PDT 24
Finished Jun 23 05:21:39 PM PDT 24
Peak memory 206012 kb
Host smart-7127ae31-9c8d-4d2e-b26b-eeb4e1ff6e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68063
7500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.680637500
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3069896985
Short name T2241
Test name
Test status
Simulation time 152664365 ps
CPU time 0.74 seconds
Started Jun 23 05:21:34 PM PDT 24
Finished Jun 23 05:21:36 PM PDT 24
Peak memory 206032 kb
Host smart-a9a46dbd-b606-4cf4-baf6-9a482ca38353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30698
96985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3069896985
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.392483834
Short name T2145
Test name
Test status
Simulation time 138559444 ps
CPU time 0.82 seconds
Started Jun 23 05:21:43 PM PDT 24
Finished Jun 23 05:21:45 PM PDT 24
Peak memory 206288 kb
Host smart-17da39bb-c2d5-47b9-8713-2e3354798226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39248
3834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.392483834
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.4165361723
Short name T2313
Test name
Test status
Simulation time 936493432 ps
CPU time 2.06 seconds
Started Jun 23 05:21:35 PM PDT 24
Finished Jun 23 05:21:39 PM PDT 24
Peak memory 206292 kb
Host smart-489bf603-6108-45fa-b73c-bec09ee16452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41653
61723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.4165361723
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1457656469
Short name T1531
Test name
Test status
Simulation time 171969767 ps
CPU time 1.81 seconds
Started Jun 23 05:21:34 PM PDT 24
Finished Jun 23 05:21:36 PM PDT 24
Peak memory 206108 kb
Host smart-bd17a189-0d4e-4f9c-b88b-6f5784995b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14576
56469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1457656469
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3238437310
Short name T1951
Test name
Test status
Simulation time 178189802 ps
CPU time 0.85 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:21:40 PM PDT 24
Peak memory 206036 kb
Host smart-cfd294cb-9f5d-4603-bb2a-6fb8a04f84da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32384
37310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3238437310
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1515368594
Short name T1645
Test name
Test status
Simulation time 145170872 ps
CPU time 0.73 seconds
Started Jun 23 05:21:39 PM PDT 24
Finished Jun 23 05:21:42 PM PDT 24
Peak memory 206020 kb
Host smart-d13a517a-d999-4394-b319-75e5863cc1f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15153
68594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1515368594
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.230187409
Short name T2216
Test name
Test status
Simulation time 180169089 ps
CPU time 0.87 seconds
Started Jun 23 05:21:32 PM PDT 24
Finished Jun 23 05:21:34 PM PDT 24
Peak memory 206024 kb
Host smart-72b2e1eb-2283-47b8-9c79-6aeaddfe68e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23018
7409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.230187409
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3099605921
Short name T2113
Test name
Test status
Simulation time 200215108 ps
CPU time 0.85 seconds
Started Jun 23 05:21:34 PM PDT 24
Finished Jun 23 05:21:35 PM PDT 24
Peak memory 206116 kb
Host smart-2879ad98-4ce3-4fdd-bfb6-a6f59b9622b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30996
05921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3099605921
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.3756345314
Short name T2162
Test name
Test status
Simulation time 23299731522 ps
CPU time 27.21 seconds
Started Jun 23 05:21:36 PM PDT 24
Finished Jun 23 05:22:05 PM PDT 24
Peak memory 206088 kb
Host smart-8b99f08f-b848-4a0e-9610-7bf986546184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37563
45314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.3756345314
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.1782711117
Short name T1217
Test name
Test status
Simulation time 3321282200 ps
CPU time 3.72 seconds
Started Jun 23 05:21:34 PM PDT 24
Finished Jun 23 05:21:39 PM PDT 24
Peak memory 206160 kb
Host smart-a0a285d6-f112-4d80-ba5e-50d929f113c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17827
11117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.1782711117
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3999531583
Short name T1635
Test name
Test status
Simulation time 13340750120 ps
CPU time 97.46 seconds
Started Jun 23 05:21:35 PM PDT 24
Finished Jun 23 05:23:13 PM PDT 24
Peak memory 206448 kb
Host smart-73133c20-c2ca-4286-b9c6-290ebfcc5891
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3999531583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3999531583
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.910444013
Short name T799
Test name
Test status
Simulation time 234031697 ps
CPU time 0.98 seconds
Started Jun 23 05:21:42 PM PDT 24
Finished Jun 23 05:21:43 PM PDT 24
Peak memory 206048 kb
Host smart-80c9a393-ea10-4367-b4a5-7422c6ba8da3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=910444013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.910444013
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1928411249
Short name T1679
Test name
Test status
Simulation time 194848609 ps
CPU time 0.85 seconds
Started Jun 23 05:21:34 PM PDT 24
Finished Jun 23 05:21:35 PM PDT 24
Peak memory 206032 kb
Host smart-3bd4f42b-140f-4044-9559-ed2bc2c48c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19284
11249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1928411249
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.3142554105
Short name T1178
Test name
Test status
Simulation time 7806070459 ps
CPU time 208.3 seconds
Started Jun 23 05:21:36 PM PDT 24
Finished Jun 23 05:25:06 PM PDT 24
Peak memory 206328 kb
Host smart-95b112fa-3851-4d0e-81f5-9749bf84e408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31425
54105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.3142554105
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.3786867868
Short name T771
Test name
Test status
Simulation time 14779168109 ps
CPU time 426.98 seconds
Started Jun 23 05:21:34 PM PDT 24
Finished Jun 23 05:28:42 PM PDT 24
Peak memory 206272 kb
Host smart-20858258-a850-4c64-9db5-7cc049257e8a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3786867868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.3786867868
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1605892165
Short name T2417
Test name
Test status
Simulation time 155683758 ps
CPU time 0.78 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:21:41 PM PDT 24
Peak memory 206032 kb
Host smart-c2d7b809-8238-491e-bb2c-a59407b783dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1605892165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1605892165
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3361945886
Short name T495
Test name
Test status
Simulation time 147057962 ps
CPU time 0.75 seconds
Started Jun 23 05:21:35 PM PDT 24
Finished Jun 23 05:21:37 PM PDT 24
Peak memory 206120 kb
Host smart-9fe383b2-9be1-4753-b493-ad5adfe61311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33619
45886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3361945886
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.261120512
Short name T114
Test name
Test status
Simulation time 188342719 ps
CPU time 0.81 seconds
Started Jun 23 05:21:35 PM PDT 24
Finished Jun 23 05:21:36 PM PDT 24
Peak memory 206108 kb
Host smart-642270be-a79f-4ca1-b74b-286ef5e619cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26112
0512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.261120512
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.3980950742
Short name T1333
Test name
Test status
Simulation time 173526487 ps
CPU time 0.86 seconds
Started Jun 23 05:21:36 PM PDT 24
Finished Jun 23 05:21:38 PM PDT 24
Peak memory 206092 kb
Host smart-dfdc5814-9558-4fb0-bf56-745249f8bbb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39809
50742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.3980950742
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2365551343
Short name T306
Test name
Test status
Simulation time 182110504 ps
CPU time 0.81 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:21:39 PM PDT 24
Peak memory 206108 kb
Host smart-927a362e-7284-47e5-b34d-5ce5a250aba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23655
51343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2365551343
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.4060603043
Short name T335
Test name
Test status
Simulation time 155295189 ps
CPU time 0.83 seconds
Started Jun 23 05:21:41 PM PDT 24
Finished Jun 23 05:21:43 PM PDT 24
Peak memory 206016 kb
Host smart-21f603a4-5b06-4704-8e8b-30b2b496b9cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40606
03043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.4060603043
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.260478548
Short name T163
Test name
Test status
Simulation time 163369473 ps
CPU time 0.77 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:21:41 PM PDT 24
Peak memory 206108 kb
Host smart-db49702f-a47d-40d4-b695-cc5ef4db2478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26047
8548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.260478548
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.616217741
Short name T577
Test name
Test status
Simulation time 191155287 ps
CPU time 0.93 seconds
Started Jun 23 05:21:42 PM PDT 24
Finished Jun 23 05:21:44 PM PDT 24
Peak memory 206128 kb
Host smart-f6e72a85-f756-4215-8bdf-dcfcb16de2a8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=616217741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.616217741
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.4068771772
Short name T1255
Test name
Test status
Simulation time 155401076 ps
CPU time 0.76 seconds
Started Jun 23 05:21:40 PM PDT 24
Finished Jun 23 05:21:42 PM PDT 24
Peak memory 206104 kb
Host smart-787e382b-c776-43c0-9667-46ac887f2db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40687
71772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.4068771772
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2069221755
Short name T1857
Test name
Test status
Simulation time 39055105 ps
CPU time 0.66 seconds
Started Jun 23 05:21:41 PM PDT 24
Finished Jun 23 05:21:43 PM PDT 24
Peak memory 206012 kb
Host smart-eed68116-524e-42b0-b05b-1048ea4e7f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20692
21755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2069221755
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1552136795
Short name T2305
Test name
Test status
Simulation time 21601285987 ps
CPU time 41.1 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:22:20 PM PDT 24
Peak memory 206388 kb
Host smart-abf42b17-11cf-4297-a4f1-7fe86eef4894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15521
36795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1552136795
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.247849125
Short name T359
Test name
Test status
Simulation time 240329350 ps
CPU time 0.95 seconds
Started Jun 23 05:21:43 PM PDT 24
Finished Jun 23 05:21:45 PM PDT 24
Peak memory 206288 kb
Host smart-e9e6c047-145c-40b9-bb2c-6453138a2ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24784
9125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.247849125
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1708935158
Short name T941
Test name
Test status
Simulation time 178182067 ps
CPU time 0.88 seconds
Started Jun 23 05:21:41 PM PDT 24
Finished Jun 23 05:21:43 PM PDT 24
Peak memory 205872 kb
Host smart-6f307a24-1699-4f09-bab1-89252d04ac2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17089
35158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1708935158
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.3012156074
Short name T1609
Test name
Test status
Simulation time 229565084 ps
CPU time 1 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:21:40 PM PDT 24
Peak memory 206108 kb
Host smart-3f0516ed-3884-4afc-a270-922053403cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30121
56074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.3012156074
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.1408371959
Short name T2016
Test name
Test status
Simulation time 171194255 ps
CPU time 0.86 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:21:41 PM PDT 24
Peak memory 206160 kb
Host smart-d260bc30-2864-4394-8e6b-5cc814108be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14083
71959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.1408371959
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.4144673635
Short name T1034
Test name
Test status
Simulation time 160620474 ps
CPU time 0.77 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:21:40 PM PDT 24
Peak memory 206092 kb
Host smart-93d25752-a9ef-4241-85c1-abda37666c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41446
73635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.4144673635
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1468690630
Short name T1013
Test name
Test status
Simulation time 152864755 ps
CPU time 0.82 seconds
Started Jun 23 05:21:39 PM PDT 24
Finished Jun 23 05:21:41 PM PDT 24
Peak memory 206220 kb
Host smart-bc3a05f9-17d1-41ce-a38d-f7efb945c529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14686
90630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1468690630
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1288367564
Short name T1381
Test name
Test status
Simulation time 157990277 ps
CPU time 0.74 seconds
Started Jun 23 05:21:40 PM PDT 24
Finished Jun 23 05:21:42 PM PDT 24
Peak memory 206104 kb
Host smart-558c84a9-8e88-4f4d-83b1-8cc8b4863bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12883
67564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1288367564
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3176058918
Short name T2481
Test name
Test status
Simulation time 219189772 ps
CPU time 0.87 seconds
Started Jun 23 05:21:33 PM PDT 24
Finished Jun 23 05:21:34 PM PDT 24
Peak memory 206100 kb
Host smart-5d96c2ab-790c-4d66-9902-9b8befdc429c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31760
58918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3176058918
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.4037655974
Short name T1978
Test name
Test status
Simulation time 6663819477 ps
CPU time 183.33 seconds
Started Jun 23 05:21:40 PM PDT 24
Finished Jun 23 05:24:44 PM PDT 24
Peak memory 206340 kb
Host smart-5f3338a2-fad4-4713-b44c-fe596e863892
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4037655974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.4037655974
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2471555602
Short name T365
Test name
Test status
Simulation time 145420971 ps
CPU time 0.79 seconds
Started Jun 23 05:21:43 PM PDT 24
Finished Jun 23 05:21:45 PM PDT 24
Peak memory 206296 kb
Host smart-26bb7a80-cf99-465c-a85f-5020cb2d86bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24715
55602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2471555602
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.371162683
Short name T655
Test name
Test status
Simulation time 183122329 ps
CPU time 0.8 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:21:40 PM PDT 24
Peak memory 206104 kb
Host smart-b6f7c066-76e3-4a6e-b883-84cbfa36c422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37116
2683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.371162683
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.2752501750
Short name T149
Test name
Test status
Simulation time 3844798934 ps
CPU time 27.4 seconds
Started Jun 23 05:21:42 PM PDT 24
Finished Jun 23 05:22:10 PM PDT 24
Peak memory 206336 kb
Host smart-af4c4763-d8eb-48b8-ba80-bf69a0eb0ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27525
01750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.2752501750
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1751806649
Short name T10
Test name
Test status
Simulation time 3987255211 ps
CPU time 5.48 seconds
Started Jun 23 05:21:43 PM PDT 24
Finished Jun 23 05:21:50 PM PDT 24
Peak memory 206320 kb
Host smart-47626867-1644-4507-b82b-173b0d032a98
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1751806649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.1751806649
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.4250144400
Short name T1199
Test name
Test status
Simulation time 13417178869 ps
CPU time 15.69 seconds
Started Jun 23 05:21:43 PM PDT 24
Finished Jun 23 05:22:00 PM PDT 24
Peak memory 206336 kb
Host smart-0ab6a0f8-5dbd-4cff-a41f-7602fa56e27e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4250144400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.4250144400
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.2786129735
Short name T908
Test name
Test status
Simulation time 23367075190 ps
CPU time 28.37 seconds
Started Jun 23 05:21:37 PM PDT 24
Finished Jun 23 05:22:06 PM PDT 24
Peak memory 206052 kb
Host smart-dec646cb-8157-487e-a3f0-8790eb8929ed
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2786129735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.2786129735
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.845939197
Short name T2104
Test name
Test status
Simulation time 149156859 ps
CPU time 0.82 seconds
Started Jun 23 05:21:41 PM PDT 24
Finished Jun 23 05:21:43 PM PDT 24
Peak memory 206100 kb
Host smart-c86bd960-7711-46e4-8d4c-f9cf81dbfdc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84593
9197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.845939197
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.3762358615
Short name T1641
Test name
Test status
Simulation time 223170822 ps
CPU time 0.85 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:21:40 PM PDT 24
Peak memory 206052 kb
Host smart-c5cf8fe8-b143-430e-852e-379a45bff7c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37623
58615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.3762358615
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.1201592704
Short name T316
Test name
Test status
Simulation time 319985411 ps
CPU time 1.11 seconds
Started Jun 23 05:21:39 PM PDT 24
Finished Jun 23 05:21:41 PM PDT 24
Peak memory 206096 kb
Host smart-f8ee4e54-f7bc-492a-bb4f-48fdd9761b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12015
92704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.1201592704
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.243380233
Short name T95
Test name
Test status
Simulation time 617610984 ps
CPU time 1.55 seconds
Started Jun 23 05:21:42 PM PDT 24
Finished Jun 23 05:21:44 PM PDT 24
Peak memory 206044 kb
Host smart-0f3d2718-cec8-412b-9732-cf26a38c35cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24338
0233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.243380233
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.2822391751
Short name T97
Test name
Test status
Simulation time 16944837603 ps
CPU time 33.54 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:22:12 PM PDT 24
Peak memory 206384 kb
Host smart-2b1cf2ef-970a-47f7-ba02-e15c480de3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28223
91751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2822391751
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.2037882867
Short name T2382
Test name
Test status
Simulation time 423933075 ps
CPU time 1.22 seconds
Started Jun 23 05:21:37 PM PDT 24
Finished Jun 23 05:21:39 PM PDT 24
Peak memory 206036 kb
Host smart-517c4292-4156-4980-b309-2ee19081c48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20378
82867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.2037882867
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3105576325
Short name T612
Test name
Test status
Simulation time 172658171 ps
CPU time 0.78 seconds
Started Jun 23 05:21:41 PM PDT 24
Finished Jun 23 05:21:43 PM PDT 24
Peak memory 206092 kb
Host smart-b089cc8a-a568-43db-89c7-3c3cc1c6fe8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31055
76325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3105576325
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.1527709708
Short name T1074
Test name
Test status
Simulation time 43770046 ps
CPU time 0.68 seconds
Started Jun 23 05:21:40 PM PDT 24
Finished Jun 23 05:21:42 PM PDT 24
Peak memory 206096 kb
Host smart-a4fd1242-68bb-4294-9977-9a232c62bdd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15277
09708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1527709708
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.552371097
Short name T922
Test name
Test status
Simulation time 833483508 ps
CPU time 1.9 seconds
Started Jun 23 05:21:41 PM PDT 24
Finished Jun 23 05:21:44 PM PDT 24
Peak memory 206260 kb
Host smart-f6722d01-58fd-4893-b8a6-3fe1256af9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55237
1097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.552371097
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3154705453
Short name T206
Test name
Test status
Simulation time 277550788 ps
CPU time 1.73 seconds
Started Jun 23 05:21:39 PM PDT 24
Finished Jun 23 05:21:42 PM PDT 24
Peak memory 206288 kb
Host smart-b72ddaa6-37c6-4885-88a2-098dbfca2ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31547
05453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3154705453
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.1406021394
Short name T1299
Test name
Test status
Simulation time 213743088 ps
CPU time 0.87 seconds
Started Jun 23 05:21:48 PM PDT 24
Finished Jun 23 05:21:50 PM PDT 24
Peak memory 206104 kb
Host smart-d1c58190-a395-4cdb-88d1-7596b76ee044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14060
21394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1406021394
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1593345379
Short name T1945
Test name
Test status
Simulation time 151066929 ps
CPU time 0.83 seconds
Started Jun 23 05:21:43 PM PDT 24
Finished Jun 23 05:21:45 PM PDT 24
Peak memory 206060 kb
Host smart-094ecec9-e62c-4b14-acb0-143ee6a3fbad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15933
45379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1593345379
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.1731710631
Short name T988
Test name
Test status
Simulation time 252307301 ps
CPU time 0.88 seconds
Started Jun 23 05:21:39 PM PDT 24
Finished Jun 23 05:21:41 PM PDT 24
Peak memory 206104 kb
Host smart-a151708a-bf16-4b23-b057-46e9a6a023c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17317
10631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.1731710631
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.2499648678
Short name T63
Test name
Test status
Simulation time 211880509 ps
CPU time 0.91 seconds
Started Jun 23 05:21:44 PM PDT 24
Finished Jun 23 05:21:46 PM PDT 24
Peak memory 206092 kb
Host smart-1e980be7-0618-4994-b765-f1dd59eed8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24996
48678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.2499648678
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.2701800056
Short name T1435
Test name
Test status
Simulation time 23315841891 ps
CPU time 24.85 seconds
Started Jun 23 05:21:44 PM PDT 24
Finished Jun 23 05:22:10 PM PDT 24
Peak memory 206152 kb
Host smart-24b44be8-a88d-4d3d-8643-c7c218d8f27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27018
00056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.2701800056
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.224660157
Short name T1326
Test name
Test status
Simulation time 3327743973 ps
CPU time 3.93 seconds
Started Jun 23 05:21:43 PM PDT 24
Finished Jun 23 05:21:47 PM PDT 24
Peak memory 206320 kb
Host smart-edce40ec-3672-432c-8c07-846ea033eaac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22466
0157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.224660157
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.1603344331
Short name T2095
Test name
Test status
Simulation time 8745749235 ps
CPU time 65.21 seconds
Started Jun 23 05:21:44 PM PDT 24
Finished Jun 23 05:22:50 PM PDT 24
Peak memory 206332 kb
Host smart-e8ca628a-66df-425e-86c4-c0cbfe5cf474
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1603344331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.1603344331
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.3215786832
Short name T1783
Test name
Test status
Simulation time 274371405 ps
CPU time 0.97 seconds
Started Jun 23 05:21:51 PM PDT 24
Finished Jun 23 05:21:53 PM PDT 24
Peak memory 206128 kb
Host smart-98684b82-5e1e-4ec9-8f48-b61a848e6bd4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3215786832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.3215786832
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2637362339
Short name T773
Test name
Test status
Simulation time 198184665 ps
CPU time 0.93 seconds
Started Jun 23 05:21:44 PM PDT 24
Finished Jun 23 05:21:45 PM PDT 24
Peak memory 206112 kb
Host smart-3db52093-dba4-4940-a321-08ee13cb109d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26373
62339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2637362339
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.450439075
Short name T1922
Test name
Test status
Simulation time 4296779746 ps
CPU time 116.03 seconds
Started Jun 23 05:21:44 PM PDT 24
Finished Jun 23 05:23:40 PM PDT 24
Peak memory 206100 kb
Host smart-3ec8487c-3971-4acc-b2be-7ed3d6677016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45043
9075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.450439075
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.331763726
Short name T858
Test name
Test status
Simulation time 5752544628 ps
CPU time 158.94 seconds
Started Jun 23 05:21:54 PM PDT 24
Finished Jun 23 05:24:33 PM PDT 24
Peak memory 206352 kb
Host smart-f90ede06-9b27-4fd1-b02d-00c78555bd82
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=331763726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.331763726
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.3675506728
Short name T620
Test name
Test status
Simulation time 183862270 ps
CPU time 0.9 seconds
Started Jun 23 05:21:49 PM PDT 24
Finished Jun 23 05:21:51 PM PDT 24
Peak memory 206144 kb
Host smart-2317b110-e290-430c-af78-e9f3ff7369ce
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3675506728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.3675506728
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.2954114987
Short name T820
Test name
Test status
Simulation time 142464022 ps
CPU time 0.74 seconds
Started Jun 23 05:21:47 PM PDT 24
Finished Jun 23 05:21:48 PM PDT 24
Peak memory 206112 kb
Host smart-e5792e01-f086-475f-9a0e-ba197ebfc8d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29541
14987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2954114987
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.968581008
Short name T121
Test name
Test status
Simulation time 239098489 ps
CPU time 0.9 seconds
Started Jun 23 05:21:48 PM PDT 24
Finished Jun 23 05:21:50 PM PDT 24
Peak memory 206092 kb
Host smart-e4714523-db22-4577-8afc-9ab1a694cb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96858
1008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.968581008
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1263957118
Short name T1810
Test name
Test status
Simulation time 232077466 ps
CPU time 0.92 seconds
Started Jun 23 05:21:53 PM PDT 24
Finished Jun 23 05:21:55 PM PDT 24
Peak memory 206100 kb
Host smart-911e63de-cafe-4673-9521-df6273078c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12639
57118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1263957118
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2927082633
Short name T1495
Test name
Test status
Simulation time 160614871 ps
CPU time 0.79 seconds
Started Jun 23 05:21:43 PM PDT 24
Finished Jun 23 05:21:45 PM PDT 24
Peak memory 206040 kb
Host smart-28b1e427-56f6-4541-a2f5-57c290e1e7ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29270
82633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2927082633
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1321532213
Short name T376
Test name
Test status
Simulation time 184832933 ps
CPU time 0.84 seconds
Started Jun 23 05:21:43 PM PDT 24
Finished Jun 23 05:21:45 PM PDT 24
Peak memory 206120 kb
Host smart-0b297bb5-54a0-4ea5-a193-d89fff806788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13215
32213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1321532213
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.2434532781
Short name T1413
Test name
Test status
Simulation time 159597789 ps
CPU time 0.83 seconds
Started Jun 23 05:21:45 PM PDT 24
Finished Jun 23 05:21:46 PM PDT 24
Peak memory 206104 kb
Host smart-72145ad6-e97c-4c8f-9303-1504dcd5c222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24345
32781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.2434532781
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.1003330092
Short name T79
Test name
Test status
Simulation time 237401489 ps
CPU time 0.95 seconds
Started Jun 23 05:21:51 PM PDT 24
Finished Jun 23 05:21:52 PM PDT 24
Peak memory 206116 kb
Host smart-c91e1096-8978-479c-bcb5-8acd187178a9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1003330092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.1003330092
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.4085244458
Short name T1925
Test name
Test status
Simulation time 176298868 ps
CPU time 0.81 seconds
Started Jun 23 05:21:53 PM PDT 24
Finished Jun 23 05:21:55 PM PDT 24
Peak memory 206124 kb
Host smart-d0c9b5dc-4339-4793-a7f3-54f13d91c627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40852
44458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.4085244458
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3987122780
Short name T28
Test name
Test status
Simulation time 27123570 ps
CPU time 0.63 seconds
Started Jun 23 05:21:44 PM PDT 24
Finished Jun 23 05:21:45 PM PDT 24
Peak memory 206128 kb
Host smart-b9df181e-b8b9-45b6-9f8f-ed5fda70c18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39871
22780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3987122780
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.866557568
Short name T1141
Test name
Test status
Simulation time 6265485119 ps
CPU time 14.3 seconds
Started Jun 23 05:21:43 PM PDT 24
Finished Jun 23 05:21:58 PM PDT 24
Peak memory 206368 kb
Host smart-33cd53ea-b26f-44fc-a547-51b36348fc5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86655
7568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.866557568
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.854711949
Short name T2083
Test name
Test status
Simulation time 182235883 ps
CPU time 0.87 seconds
Started Jun 23 05:21:54 PM PDT 24
Finished Jun 23 05:21:55 PM PDT 24
Peak memory 206108 kb
Host smart-376457b6-cc0c-4961-a61a-c8a897ed9e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85471
1949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.854711949
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.3870143422
Short name T477
Test name
Test status
Simulation time 196183755 ps
CPU time 0.82 seconds
Started Jun 23 05:21:43 PM PDT 24
Finished Jun 23 05:21:44 PM PDT 24
Peak memory 206100 kb
Host smart-72f25718-5854-4587-969d-08d49f8bdd2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38701
43422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3870143422
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.4000240921
Short name T419
Test name
Test status
Simulation time 212079010 ps
CPU time 0.95 seconds
Started Jun 23 05:21:50 PM PDT 24
Finished Jun 23 05:21:52 PM PDT 24
Peak memory 206124 kb
Host smart-d02cc925-0f48-4761-8291-78f0c4b4b56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40002
40921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.4000240921
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.450027724
Short name T2341
Test name
Test status
Simulation time 215367942 ps
CPU time 0.91 seconds
Started Jun 23 05:21:53 PM PDT 24
Finished Jun 23 05:21:55 PM PDT 24
Peak memory 206124 kb
Host smart-d2b1b3d2-6398-4649-88e2-a1ef0093ef7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45002
7724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.450027724
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2589848377
Short name T1678
Test name
Test status
Simulation time 142783380 ps
CPU time 0.82 seconds
Started Jun 23 05:21:53 PM PDT 24
Finished Jun 23 05:21:55 PM PDT 24
Peak memory 206096 kb
Host smart-1e92ddeb-7088-41fe-9b5e-ce3fc7338f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25898
48377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2589848377
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3812534391
Short name T2134
Test name
Test status
Simulation time 155780403 ps
CPU time 0.77 seconds
Started Jun 23 05:21:45 PM PDT 24
Finished Jun 23 05:21:46 PM PDT 24
Peak memory 206016 kb
Host smart-d807223b-b8bd-4efb-a41e-8670c8df1aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38125
34391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3812534391
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.985643892
Short name T2485
Test name
Test status
Simulation time 159580639 ps
CPU time 0.8 seconds
Started Jun 23 05:21:43 PM PDT 24
Finished Jun 23 05:21:44 PM PDT 24
Peak memory 206120 kb
Host smart-49e79d1f-5c80-4293-b9f0-ed0c65bd6d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98564
3892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.985643892
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.4207923693
Short name T865
Test name
Test status
Simulation time 230097494 ps
CPU time 1 seconds
Started Jun 23 05:21:38 PM PDT 24
Finished Jun 23 05:21:40 PM PDT 24
Peak memory 206060 kb
Host smart-41717697-5a62-4f95-81e4-7c88159040bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42079
23693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.4207923693
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.3363427029
Short name T1474
Test name
Test status
Simulation time 12635262031 ps
CPU time 121.15 seconds
Started Jun 23 05:21:42 PM PDT 24
Finished Jun 23 05:23:44 PM PDT 24
Peak memory 206388 kb
Host smart-be538842-cbb2-4c46-91dd-50b9c880dcd8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3363427029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.3363427029
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.141948819
Short name T1064
Test name
Test status
Simulation time 157271928 ps
CPU time 0.77 seconds
Started Jun 23 05:21:44 PM PDT 24
Finished Jun 23 05:21:46 PM PDT 24
Peak memory 206104 kb
Host smart-5f8e5d33-8b12-4c2e-af77-dc4e5e685d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14194
8819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.141948819
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.2875659463
Short name T2051
Test name
Test status
Simulation time 178977197 ps
CPU time 0.8 seconds
Started Jun 23 05:21:45 PM PDT 24
Finished Jun 23 05:21:46 PM PDT 24
Peak memory 206100 kb
Host smart-08176653-9806-4f3c-b34d-eff00f39b513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28756
59463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.2875659463
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.1286652201
Short name T2143
Test name
Test status
Simulation time 4717023672 ps
CPU time 34.35 seconds
Started Jun 23 05:21:47 PM PDT 24
Finished Jun 23 05:22:22 PM PDT 24
Peak memory 206328 kb
Host smart-bd0abe69-7cc8-454d-b7d8-2fc3631ceb6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12866
52201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.1286652201
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.3132200777
Short name T638
Test name
Test status
Simulation time 4128800482 ps
CPU time 4.6 seconds
Started Jun 23 05:15:42 PM PDT 24
Finished Jun 23 05:15:47 PM PDT 24
Peak memory 206164 kb
Host smart-35c72e1c-67bf-4137-8201-32ceecaa06b1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3132200777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.3132200777
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.1834054675
Short name T2070
Test name
Test status
Simulation time 13424173843 ps
CPU time 12.03 seconds
Started Jun 23 05:15:38 PM PDT 24
Finished Jun 23 05:15:50 PM PDT 24
Peak memory 206128 kb
Host smart-c7f373d2-d678-4a24-93b0-ae20e43d33b2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1834054675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1834054675
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.1786697307
Short name T2026
Test name
Test status
Simulation time 23374350629 ps
CPU time 21.78 seconds
Started Jun 23 05:15:41 PM PDT 24
Finished Jun 23 05:16:03 PM PDT 24
Peak memory 206272 kb
Host smart-99c4c144-8c6a-4f0c-a22d-d84e3a5460e4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1786697307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.1786697307
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.820289798
Short name T412
Test name
Test status
Simulation time 154832499 ps
CPU time 0.83 seconds
Started Jun 23 05:15:36 PM PDT 24
Finished Jun 23 05:15:37 PM PDT 24
Peak memory 206100 kb
Host smart-92e770c9-d24f-4d74-bd7c-697326c19475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82028
9798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.820289798
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.3739793793
Short name T59
Test name
Test status
Simulation time 204665471 ps
CPU time 0.93 seconds
Started Jun 23 05:15:36 PM PDT 24
Finished Jun 23 05:15:37 PM PDT 24
Peak memory 206256 kb
Host smart-35df4022-e996-4928-9c1c-483e1f39556a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37397
93793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.3739793793
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.2809428784
Short name T70
Test name
Test status
Simulation time 141845930 ps
CPU time 0.84 seconds
Started Jun 23 05:15:39 PM PDT 24
Finished Jun 23 05:15:40 PM PDT 24
Peak memory 206056 kb
Host smart-732a6ba7-e979-4050-87fe-e63a27758d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28094
28784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.2809428784
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.726810749
Short name T286
Test name
Test status
Simulation time 162780401 ps
CPU time 0.76 seconds
Started Jun 23 05:15:37 PM PDT 24
Finished Jun 23 05:15:38 PM PDT 24
Peak memory 206288 kb
Host smart-308bdd49-c476-4193-bf58-925e3d111a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72681
0749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.726810749
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.799230720
Short name T1823
Test name
Test status
Simulation time 202827684 ps
CPU time 0.94 seconds
Started Jun 23 05:15:37 PM PDT 24
Finished Jun 23 05:15:39 PM PDT 24
Peak memory 206100 kb
Host smart-284801b3-d14a-4219-ae8b-88a243796e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79923
0720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.799230720
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.3328226868
Short name T1226
Test name
Test status
Simulation time 896650505 ps
CPU time 1.97 seconds
Started Jun 23 05:15:37 PM PDT 24
Finished Jun 23 05:15:40 PM PDT 24
Peak memory 206280 kb
Host smart-7bf2cec5-9060-48a2-b6b0-2827d60a32b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33282
26868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.3328226868
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.3252057022
Short name T629
Test name
Test status
Simulation time 16983328598 ps
CPU time 37.09 seconds
Started Jun 23 05:15:38 PM PDT 24
Finished Jun 23 05:16:15 PM PDT 24
Peak memory 206412 kb
Host smart-4b71546a-acd0-45cf-ba2e-4a6f483bc643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32520
57022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.3252057022
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1557785366
Short name T544
Test name
Test status
Simulation time 384744543 ps
CPU time 1.19 seconds
Started Jun 23 05:15:44 PM PDT 24
Finished Jun 23 05:15:46 PM PDT 24
Peak memory 206064 kb
Host smart-a5095229-b384-4a1b-a536-3ee6f532a0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15577
85366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1557785366
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3969590233
Short name T422
Test name
Test status
Simulation time 140211318 ps
CPU time 0.78 seconds
Started Jun 23 05:15:44 PM PDT 24
Finished Jun 23 05:15:46 PM PDT 24
Peak memory 206060 kb
Host smart-efa9b57d-15c9-4c34-a0e6-5b8221a04448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39695
90233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3969590233
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.3661134612
Short name T2112
Test name
Test status
Simulation time 116408098 ps
CPU time 0.7 seconds
Started Jun 23 05:15:46 PM PDT 24
Finished Jun 23 05:15:48 PM PDT 24
Peak memory 206096 kb
Host smart-37720aa2-8ae8-42a4-935d-75d83a6f50f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36611
34612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3661134612
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2403868012
Short name T1254
Test name
Test status
Simulation time 748124399 ps
CPU time 1.81 seconds
Started Jun 23 05:15:43 PM PDT 24
Finished Jun 23 05:15:45 PM PDT 24
Peak memory 206544 kb
Host smart-d7f654d7-a5a2-406b-ad09-a7c583cd6540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24038
68012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2403868012
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.3242574049
Short name T738
Test name
Test status
Simulation time 171146765 ps
CPU time 1.69 seconds
Started Jun 23 05:15:44 PM PDT 24
Finished Jun 23 05:15:47 PM PDT 24
Peak memory 206260 kb
Host smart-69400b55-3b3c-404b-b2ac-56876f56c24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32425
74049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3242574049
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3823557785
Short name T940
Test name
Test status
Simulation time 249160641 ps
CPU time 0.86 seconds
Started Jun 23 05:15:47 PM PDT 24
Finished Jun 23 05:15:49 PM PDT 24
Peak memory 206076 kb
Host smart-23b4ffe0-4b11-4080-880c-74475fcbb8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38235
57785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3823557785
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.2640400972
Short name T201
Test name
Test status
Simulation time 140674846 ps
CPU time 0.76 seconds
Started Jun 23 05:15:48 PM PDT 24
Finished Jun 23 05:15:50 PM PDT 24
Peak memory 206100 kb
Host smart-73cd65e9-77d3-40d1-aa08-e559b90125e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26404
00972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.2640400972
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2869830004
Short name T2423
Test name
Test status
Simulation time 202536199 ps
CPU time 0.87 seconds
Started Jun 23 05:15:44 PM PDT 24
Finished Jun 23 05:15:46 PM PDT 24
Peak memory 206104 kb
Host smart-96a3c31c-8d20-4695-b568-f5283f352c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28698
30004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2869830004
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.594139846
Short name T2348
Test name
Test status
Simulation time 200300949 ps
CPU time 0.84 seconds
Started Jun 23 05:15:43 PM PDT 24
Finished Jun 23 05:15:45 PM PDT 24
Peak memory 206028 kb
Host smart-f06101ca-4879-48fe-a960-7ce8d50e72ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59413
9846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.594139846
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.4019795742
Short name T1730
Test name
Test status
Simulation time 23326246242 ps
CPU time 22.45 seconds
Started Jun 23 05:15:42 PM PDT 24
Finished Jun 23 05:16:05 PM PDT 24
Peak memory 206160 kb
Host smart-2e44e687-70e2-41c2-8a5d-77862d8786c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40197
95742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.4019795742
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.2166162348
Short name T2213
Test name
Test status
Simulation time 3389999624 ps
CPU time 4.18 seconds
Started Jun 23 05:15:42 PM PDT 24
Finished Jun 23 05:15:47 PM PDT 24
Peak memory 206132 kb
Host smart-ad39bbe6-4a75-4a0a-ac55-f23f3094f597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21661
62348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2166162348
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.1965360789
Short name T579
Test name
Test status
Simulation time 6688469863 ps
CPU time 49.12 seconds
Started Jun 23 05:15:44 PM PDT 24
Finished Jun 23 05:16:34 PM PDT 24
Peak memory 206440 kb
Host smart-7b2f28fc-d529-4857-87dd-212f5e6840ed
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1965360789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.1965360789
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.3867090332
Short name T1398
Test name
Test status
Simulation time 237551700 ps
CPU time 0.88 seconds
Started Jun 23 05:15:51 PM PDT 24
Finished Jun 23 05:15:53 PM PDT 24
Peak memory 206024 kb
Host smart-0568f2cc-9884-481b-8b38-41a47c416857
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3867090332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.3867090332
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.399711186
Short name T1584
Test name
Test status
Simulation time 189367394 ps
CPU time 0.83 seconds
Started Jun 23 05:15:43 PM PDT 24
Finished Jun 23 05:15:44 PM PDT 24
Peak memory 206064 kb
Host smart-4db3003c-4186-41ec-87c8-435e152e7a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39971
1186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.399711186
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.2267270066
Short name T1876
Test name
Test status
Simulation time 4371797517 ps
CPU time 31.47 seconds
Started Jun 23 05:15:43 PM PDT 24
Finished Jun 23 05:16:15 PM PDT 24
Peak memory 206352 kb
Host smart-b9fddff7-381a-4b05-b750-d1eb393e942e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22672
70066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.2267270066
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.3400261924
Short name T2478
Test name
Test status
Simulation time 14721306786 ps
CPU time 138.18 seconds
Started Jun 23 05:15:44 PM PDT 24
Finished Jun 23 05:18:03 PM PDT 24
Peak memory 206344 kb
Host smart-f803d66b-7eef-4b98-8c0c-c4980220760c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3400261924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.3400261924
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1058352703
Short name T1360
Test name
Test status
Simulation time 145904249 ps
CPU time 0.78 seconds
Started Jun 23 05:15:49 PM PDT 24
Finished Jun 23 05:15:50 PM PDT 24
Peak memory 206144 kb
Host smart-1a9b9012-c02e-48df-b48c-3d20b795a21e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1058352703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1058352703
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2393591890
Short name T797
Test name
Test status
Simulation time 173792953 ps
CPU time 0.79 seconds
Started Jun 23 05:15:44 PM PDT 24
Finished Jun 23 05:15:45 PM PDT 24
Peak memory 206100 kb
Host smart-ffc81ae7-2849-457b-acb2-048cc64f44cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23935
91890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2393591890
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3027806735
Short name T123
Test name
Test status
Simulation time 205308736 ps
CPU time 0.88 seconds
Started Jun 23 05:15:47 PM PDT 24
Finished Jun 23 05:15:48 PM PDT 24
Peak memory 206108 kb
Host smart-38e1f368-2408-4d10-a874-8a776225c5f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30278
06735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3027806735
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.3849443701
Short name T1349
Test name
Test status
Simulation time 203124236 ps
CPU time 0.88 seconds
Started Jun 23 05:15:48 PM PDT 24
Finished Jun 23 05:15:49 PM PDT 24
Peak memory 206100 kb
Host smart-4144c54b-fd60-46a7-9d10-069a4a6aafbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38494
43701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.3849443701
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2474327599
Short name T2410
Test name
Test status
Simulation time 188484710 ps
CPU time 0.85 seconds
Started Jun 23 05:15:47 PM PDT 24
Finished Jun 23 05:15:49 PM PDT 24
Peak memory 206104 kb
Host smart-38b5a0bd-f8e8-411c-bdcc-75e9e6f6f3ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24743
27599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2474327599
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3570429373
Short name T1340
Test name
Test status
Simulation time 151149887 ps
CPU time 0.79 seconds
Started Jun 23 05:15:44 PM PDT 24
Finished Jun 23 05:15:46 PM PDT 24
Peak memory 206100 kb
Host smart-c6ae9ec3-e4da-4b8e-af46-14e9555f24a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35704
29373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3570429373
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.67366423
Short name T2192
Test name
Test status
Simulation time 144829178 ps
CPU time 0.79 seconds
Started Jun 23 05:15:48 PM PDT 24
Finished Jun 23 05:15:49 PM PDT 24
Peak memory 206036 kb
Host smart-9d6806ff-483f-420f-87c1-2d711a231fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67366
423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.67366423
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.3546281445
Short name T2043
Test name
Test status
Simulation time 208839266 ps
CPU time 0.91 seconds
Started Jun 23 05:15:48 PM PDT 24
Finished Jun 23 05:15:50 PM PDT 24
Peak memory 206044 kb
Host smart-ddcbbeea-3e6c-483b-b715-4df28d13d91f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3546281445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.3546281445
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2616932475
Short name T406
Test name
Test status
Simulation time 145593379 ps
CPU time 0.74 seconds
Started Jun 23 05:15:49 PM PDT 24
Finished Jun 23 05:15:51 PM PDT 24
Peak memory 206056 kb
Host smart-4d1a1cca-44df-4b57-bef9-3d13c9c21d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26169
32475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2616932475
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3695390246
Short name T1240
Test name
Test status
Simulation time 28478320 ps
CPU time 0.69 seconds
Started Jun 23 05:15:47 PM PDT 24
Finished Jun 23 05:15:48 PM PDT 24
Peak memory 206060 kb
Host smart-a3ff8039-29df-4598-9da0-b4093a5b461b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36953
90246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3695390246
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.619617046
Short name T2161
Test name
Test status
Simulation time 17031792248 ps
CPU time 37.7 seconds
Started Jun 23 05:15:47 PM PDT 24
Finished Jun 23 05:16:25 PM PDT 24
Peak memory 206336 kb
Host smart-65d7497e-74b3-459d-b142-8c037e970294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61961
7046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.619617046
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.533799415
Short name T1957
Test name
Test status
Simulation time 142927987 ps
CPU time 0.78 seconds
Started Jun 23 05:15:43 PM PDT 24
Finished Jun 23 05:15:44 PM PDT 24
Peak memory 206060 kb
Host smart-d229bcda-055d-469d-b5a5-c0d97eb7f6b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53379
9415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.533799415
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.48772022
Short name T982
Test name
Test status
Simulation time 226253866 ps
CPU time 0.93 seconds
Started Jun 23 05:15:44 PM PDT 24
Finished Jun 23 05:15:46 PM PDT 24
Peak memory 206028 kb
Host smart-b4f9a0cf-f63b-4436-964a-2fe08ed58b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48772
022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.48772022
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.890593392
Short name T1845
Test name
Test status
Simulation time 24652588400 ps
CPU time 155.38 seconds
Started Jun 23 05:15:46 PM PDT 24
Finished Jun 23 05:18:22 PM PDT 24
Peak memory 206420 kb
Host smart-06ee054d-068e-41b3-a8aa-c39516bd2248
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=890593392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.890593392
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.3007656547
Short name T167
Test name
Test status
Simulation time 25644433716 ps
CPU time 678.37 seconds
Started Jun 23 05:15:44 PM PDT 24
Finished Jun 23 05:27:03 PM PDT 24
Peak memory 206352 kb
Host smart-89108a7d-4da1-41ce-9e0f-87867b2a0234
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3007656547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.3007656547
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.52140073
Short name T1014
Test name
Test status
Simulation time 18822104666 ps
CPU time 429.74 seconds
Started Jun 23 05:15:46 PM PDT 24
Finished Jun 23 05:22:57 PM PDT 24
Peak memory 206408 kb
Host smart-f5ebf376-14fb-486f-8488-656f9309a839
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=52140073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.52140073
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.1493194097
Short name T1476
Test name
Test status
Simulation time 226677359 ps
CPU time 0.81 seconds
Started Jun 23 05:15:47 PM PDT 24
Finished Jun 23 05:15:49 PM PDT 24
Peak memory 205880 kb
Host smart-20719f6e-41f6-49f9-ac36-8a117d55a842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14931
94097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.1493194097
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3149834168
Short name T1935
Test name
Test status
Simulation time 148887338 ps
CPU time 0.86 seconds
Started Jun 23 05:15:47 PM PDT 24
Finished Jun 23 05:15:49 PM PDT 24
Peak memory 206120 kb
Host smart-cf6b069a-1410-41f7-948f-7f44656566b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31498
34168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3149834168
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2841224651
Short name T860
Test name
Test status
Simulation time 156388958 ps
CPU time 0.83 seconds
Started Jun 23 05:15:46 PM PDT 24
Finished Jun 23 05:15:48 PM PDT 24
Peak memory 206084 kb
Host smart-4c125cdf-b4a3-40d3-8725-47e5e8f5d42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28412
24651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2841224651
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3489241504
Short name T188
Test name
Test status
Simulation time 217542872 ps
CPU time 1.04 seconds
Started Jun 23 05:15:51 PM PDT 24
Finished Jun 23 05:15:52 PM PDT 24
Peak memory 223872 kb
Host smart-230dcf28-6b53-4e5e-b0fd-090261b4d81b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3489241504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3489241504
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.264814400
Short name T55
Test name
Test status
Simulation time 394754130 ps
CPU time 1.32 seconds
Started Jun 23 05:15:49 PM PDT 24
Finished Jun 23 05:15:51 PM PDT 24
Peak memory 205840 kb
Host smart-48a3e194-db59-4ddc-87a0-99b03bea3907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26481
4400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.264814400
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3098935004
Short name T983
Test name
Test status
Simulation time 151900549 ps
CPU time 0.76 seconds
Started Jun 23 05:15:49 PM PDT 24
Finished Jun 23 05:15:51 PM PDT 24
Peak memory 206096 kb
Host smart-06ec14ae-896a-40b1-b039-456a99b5fe0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30989
35004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3098935004
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2583033635
Short name T1427
Test name
Test status
Simulation time 172190718 ps
CPU time 0.8 seconds
Started Jun 23 05:15:43 PM PDT 24
Finished Jun 23 05:15:44 PM PDT 24
Peak memory 206048 kb
Host smart-4750084b-a075-43fd-8b4d-235f20b5b2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25830
33635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2583033635
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1279664490
Short name T474
Test name
Test status
Simulation time 218473949 ps
CPU time 0.89 seconds
Started Jun 23 05:15:38 PM PDT 24
Finished Jun 23 05:15:39 PM PDT 24
Peak memory 206108 kb
Host smart-1fce3eab-6082-4856-bb03-39b87599ec77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12796
64490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1279664490
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.1606745521
Short name T2433
Test name
Test status
Simulation time 5840894960 ps
CPU time 42.17 seconds
Started Jun 23 05:15:47 PM PDT 24
Finished Jun 23 05:16:30 PM PDT 24
Peak memory 206436 kb
Host smart-5eac4c47-1d18-40fa-a90d-ccbf77309de4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1606745521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.1606745521
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1535410334
Short name T1634
Test name
Test status
Simulation time 257655944 ps
CPU time 0.88 seconds
Started Jun 23 05:15:49 PM PDT 24
Finished Jun 23 05:15:51 PM PDT 24
Peak memory 206036 kb
Host smart-379a7ec9-282b-4358-9973-b6d164e6e8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15354
10334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1535410334
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.2985157209
Short name T33
Test name
Test status
Simulation time 188333000 ps
CPU time 0.79 seconds
Started Jun 23 05:15:47 PM PDT 24
Finished Jun 23 05:15:49 PM PDT 24
Peak memory 206096 kb
Host smart-53b16e0d-400f-4317-a8ae-4821652ffb27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29851
57209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.2985157209
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.887088389
Short name T469
Test name
Test status
Simulation time 4791588455 ps
CPU time 143.05 seconds
Started Jun 23 05:15:47 PM PDT 24
Finished Jun 23 05:18:11 PM PDT 24
Peak memory 206328 kb
Host smart-0493adc8-ff18-4476-a00d-d34440bfe71f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88708
8389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.887088389
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.99988354
Short name T2205
Test name
Test status
Simulation time 17066750020 ps
CPU time 100.72 seconds
Started Jun 23 05:15:49 PM PDT 24
Finished Jun 23 05:17:30 PM PDT 24
Peak memory 206152 kb
Host smart-fed9c83b-31fd-483a-8a45-4fcdc9b5284e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=99988354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.99988354
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.3372315028
Short name T1701
Test name
Test status
Simulation time 3636463772 ps
CPU time 4.33 seconds
Started Jun 23 05:21:48 PM PDT 24
Finished Jun 23 05:21:53 PM PDT 24
Peak memory 206144 kb
Host smart-765cad86-7464-43c7-bc1a-24d89a18804a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3372315028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.3372315028
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2054748318
Short name T2220
Test name
Test status
Simulation time 13371876018 ps
CPU time 11.94 seconds
Started Jun 23 05:21:49 PM PDT 24
Finished Jun 23 05:22:01 PM PDT 24
Peak memory 206148 kb
Host smart-3aa490e8-d0c5-4904-81d0-10f26b97bfbc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2054748318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2054748318
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.171062953
Short name T729
Test name
Test status
Simulation time 23460326781 ps
CPU time 30.26 seconds
Started Jun 23 05:21:53 PM PDT 24
Finished Jun 23 05:22:24 PM PDT 24
Peak memory 206408 kb
Host smart-deaabd5a-35ef-4b85-88ec-922ca2a043a6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=171062953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.171062953
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.4169790615
Short name T686
Test name
Test status
Simulation time 163415581 ps
CPU time 0.92 seconds
Started Jun 23 05:21:49 PM PDT 24
Finished Jun 23 05:21:51 PM PDT 24
Peak memory 206036 kb
Host smart-3198ba3b-0f15-4fc1-8df7-24280cbbc382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41697
90615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.4169790615
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.4264650883
Short name T2383
Test name
Test status
Simulation time 158225665 ps
CPU time 0.79 seconds
Started Jun 23 05:21:50 PM PDT 24
Finished Jun 23 05:21:52 PM PDT 24
Peak memory 206104 kb
Host smart-e338b285-5071-43bd-93fb-071d0c55e7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42646
50883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.4264650883
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.2694829954
Short name T1847
Test name
Test status
Simulation time 207459752 ps
CPU time 0.97 seconds
Started Jun 23 05:21:46 PM PDT 24
Finished Jun 23 05:21:48 PM PDT 24
Peak memory 206116 kb
Host smart-dc2f06f2-db80-41eb-be89-5e3cbb83a6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26948
29954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.2694829954
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.558042639
Short name T1451
Test name
Test status
Simulation time 600763031 ps
CPU time 1.51 seconds
Started Jun 23 05:21:49 PM PDT 24
Finished Jun 23 05:21:51 PM PDT 24
Peak memory 206124 kb
Host smart-94106afb-0262-4158-8048-fe6afde30cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55804
2639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.558042639
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.157398195
Short name T2094
Test name
Test status
Simulation time 15381566256 ps
CPU time 26.42 seconds
Started Jun 23 05:21:54 PM PDT 24
Finished Jun 23 05:22:22 PM PDT 24
Peak memory 206404 kb
Host smart-f9ca5cd4-0b04-492f-a65e-784ac608c298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15739
8195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.157398195
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2054215691
Short name T476
Test name
Test status
Simulation time 424344660 ps
CPU time 1.16 seconds
Started Jun 23 05:21:54 PM PDT 24
Finished Jun 23 05:21:56 PM PDT 24
Peak memory 206100 kb
Host smart-c6b9b354-19f9-4716-b171-65d60626889a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20542
15691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2054215691
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1345229553
Short name T1040
Test name
Test status
Simulation time 145838318 ps
CPU time 0.77 seconds
Started Jun 23 05:21:47 PM PDT 24
Finished Jun 23 05:21:48 PM PDT 24
Peak memory 206032 kb
Host smart-181817c4-9e81-48b7-8149-ba34f660368a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13452
29553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1345229553
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.3173753606
Short name T2081
Test name
Test status
Simulation time 40298279 ps
CPU time 0.67 seconds
Started Jun 23 05:21:48 PM PDT 24
Finished Jun 23 05:21:49 PM PDT 24
Peak memory 206064 kb
Host smart-8dcf8843-a715-40c3-88ab-220668151bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31737
53606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3173753606
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3071974692
Short name T1564
Test name
Test status
Simulation time 1110132385 ps
CPU time 2.37 seconds
Started Jun 23 05:21:47 PM PDT 24
Finished Jun 23 05:21:50 PM PDT 24
Peak memory 206260 kb
Host smart-485f8c6b-a7ab-44c9-9176-15a4d72365ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30719
74692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3071974692
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.4225604216
Short name T1386
Test name
Test status
Simulation time 156888400 ps
CPU time 1.42 seconds
Started Jun 23 05:21:47 PM PDT 24
Finished Jun 23 05:21:49 PM PDT 24
Peak memory 206284 kb
Host smart-1612e059-dfdc-4ce7-95cb-fe33b63d37d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42256
04216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.4225604216
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.2147635597
Short name T2200
Test name
Test status
Simulation time 232585373 ps
CPU time 0.9 seconds
Started Jun 23 05:21:55 PM PDT 24
Finished Jun 23 05:21:57 PM PDT 24
Peak memory 206116 kb
Host smart-466f9c97-116c-42aa-98c6-c99bf30c330c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21476
35597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.2147635597
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3722453800
Short name T863
Test name
Test status
Simulation time 176011900 ps
CPU time 0.82 seconds
Started Jun 23 05:21:52 PM PDT 24
Finished Jun 23 05:21:53 PM PDT 24
Peak memory 206088 kb
Host smart-a180af8f-f6e9-4804-b6f7-b7052e07cc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37224
53800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3722453800
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.376075251
Short name T2318
Test name
Test status
Simulation time 228295157 ps
CPU time 0.9 seconds
Started Jun 23 05:21:55 PM PDT 24
Finished Jun 23 05:21:57 PM PDT 24
Peak memory 206096 kb
Host smart-be3ba3ec-7843-4120-a3fe-56a1cc62ddd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37607
5251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.376075251
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.1319539367
Short name T2022
Test name
Test status
Simulation time 175337979 ps
CPU time 0.83 seconds
Started Jun 23 05:21:50 PM PDT 24
Finished Jun 23 05:21:52 PM PDT 24
Peak memory 206100 kb
Host smart-ec564c20-7f3a-4f0e-8572-a7111f81cfbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13195
39367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1319539367
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.85080528
Short name T2077
Test name
Test status
Simulation time 23351167514 ps
CPU time 25 seconds
Started Jun 23 05:21:48 PM PDT 24
Finished Jun 23 05:22:14 PM PDT 24
Peak memory 206136 kb
Host smart-70483b29-d5e5-4d39-8b92-644db7f45401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85080
528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.85080528
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.1822454318
Short name T1552
Test name
Test status
Simulation time 3371941023 ps
CPU time 4.69 seconds
Started Jun 23 05:21:53 PM PDT 24
Finished Jun 23 05:21:58 PM PDT 24
Peak memory 206156 kb
Host smart-16777338-d6e0-4470-9847-785cb9a0454b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18224
54318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.1822454318
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2644925166
Short name T2468
Test name
Test status
Simulation time 7245378979 ps
CPU time 50.78 seconds
Started Jun 23 05:21:54 PM PDT 24
Finished Jun 23 05:22:46 PM PDT 24
Peak memory 206352 kb
Host smart-864ad494-09ce-4486-965c-2f2011820215
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2644925166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2644925166
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.929701271
Short name T23
Test name
Test status
Simulation time 234195180 ps
CPU time 0.89 seconds
Started Jun 23 05:21:55 PM PDT 24
Finished Jun 23 05:21:57 PM PDT 24
Peak memory 206056 kb
Host smart-58aa8639-d817-4585-a1db-2e72d9fb60bf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=929701271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.929701271
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3330972086
Short name T1346
Test name
Test status
Simulation time 241725126 ps
CPU time 0.89 seconds
Started Jun 23 05:21:49 PM PDT 24
Finished Jun 23 05:21:51 PM PDT 24
Peak memory 206116 kb
Host smart-9bb06ce7-5974-4316-9812-b2d3550d747e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33309
72086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3330972086
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.762734782
Short name T851
Test name
Test status
Simulation time 4053064782 ps
CPU time 114.06 seconds
Started Jun 23 05:21:54 PM PDT 24
Finished Jun 23 05:23:49 PM PDT 24
Peak memory 206212 kb
Host smart-1cc599bf-5a13-487a-ab65-61944ea7db58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76273
4782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.762734782
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.1722477296
Short name T714
Test name
Test status
Simulation time 8391442336 ps
CPU time 79.73 seconds
Started Jun 23 05:21:57 PM PDT 24
Finished Jun 23 05:23:17 PM PDT 24
Peak memory 206320 kb
Host smart-a2c788c6-16a3-4322-833f-c8a2b691e0b8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1722477296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.1722477296
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3365496339
Short name T780
Test name
Test status
Simulation time 199944092 ps
CPU time 0.8 seconds
Started Jun 23 05:21:58 PM PDT 24
Finished Jun 23 05:21:59 PM PDT 24
Peak memory 205900 kb
Host smart-dac28ce7-6af3-4d92-9e4a-b6ec04f0bbc3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3365496339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3365496339
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.390231817
Short name T1176
Test name
Test status
Simulation time 151352852 ps
CPU time 0.83 seconds
Started Jun 23 05:21:57 PM PDT 24
Finished Jun 23 05:21:59 PM PDT 24
Peak memory 206080 kb
Host smart-429cb0d3-744e-4abf-903a-03b560f5c2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39023
1817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.390231817
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.247118703
Short name T2413
Test name
Test status
Simulation time 208442272 ps
CPU time 0.85 seconds
Started Jun 23 05:21:55 PM PDT 24
Finished Jun 23 05:21:57 PM PDT 24
Peak memory 206104 kb
Host smart-aaac7255-6b51-4492-9441-ce1af6fcd339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24711
8703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.247118703
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.64066499
Short name T2181
Test name
Test status
Simulation time 159994386 ps
CPU time 0.8 seconds
Started Jun 23 05:21:56 PM PDT 24
Finished Jun 23 05:21:58 PM PDT 24
Peak memory 206024 kb
Host smart-5c372d78-4a9c-40ee-8300-470abd9b2f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64066
499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.64066499
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.735496937
Short name T1145
Test name
Test status
Simulation time 193815438 ps
CPU time 0.93 seconds
Started Jun 23 05:21:55 PM PDT 24
Finished Jun 23 05:21:57 PM PDT 24
Peak memory 206032 kb
Host smart-2f86f779-7454-4779-999b-ac0d6f2c81c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73549
6937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.735496937
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3349493330
Short name T539
Test name
Test status
Simulation time 202725619 ps
CPU time 0.87 seconds
Started Jun 23 05:21:54 PM PDT 24
Finished Jun 23 05:21:56 PM PDT 24
Peak memory 206156 kb
Host smart-ca46c613-f097-4d15-b5e3-7e133bac3e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33494
93330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3349493330
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1778362610
Short name T2452
Test name
Test status
Simulation time 176047795 ps
CPU time 0.83 seconds
Started Jun 23 05:21:55 PM PDT 24
Finished Jun 23 05:21:57 PM PDT 24
Peak memory 206112 kb
Host smart-c738011a-f0f2-4b3c-bf8e-1fbb202e28de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17783
62610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1778362610
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.478972082
Short name T1494
Test name
Test status
Simulation time 206440929 ps
CPU time 0.91 seconds
Started Jun 23 05:21:58 PM PDT 24
Finished Jun 23 05:21:59 PM PDT 24
Peak memory 205900 kb
Host smart-57087110-095c-454b-ac17-5ec40987859d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=478972082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.478972082
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.4276189787
Short name T2265
Test name
Test status
Simulation time 165270486 ps
CPU time 0.76 seconds
Started Jun 23 05:21:55 PM PDT 24
Finished Jun 23 05:21:57 PM PDT 24
Peak memory 206028 kb
Host smart-04bbd638-1db8-464c-bd14-5fb8776ac2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42761
89787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.4276189787
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1604356196
Short name T1157
Test name
Test status
Simulation time 66937356 ps
CPU time 0.71 seconds
Started Jun 23 05:21:58 PM PDT 24
Finished Jun 23 05:21:59 PM PDT 24
Peak memory 205864 kb
Host smart-bd9ba81e-37e6-4376-89c5-6b5afd018540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16043
56196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1604356196
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.4125157820
Short name T1873
Test name
Test status
Simulation time 18450353831 ps
CPU time 42.35 seconds
Started Jun 23 05:21:56 PM PDT 24
Finished Jun 23 05:22:39 PM PDT 24
Peak memory 206344 kb
Host smart-7e0b4113-7061-4607-b388-354ac11f8d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41251
57820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.4125157820
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.565564993
Short name T525
Test name
Test status
Simulation time 194810477 ps
CPU time 0.87 seconds
Started Jun 23 05:21:56 PM PDT 24
Finished Jun 23 05:21:58 PM PDT 24
Peak memory 206028 kb
Host smart-855bf9c8-2f04-4c38-b1a4-e7f89d98ba7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56556
4993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.565564993
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3522665885
Short name T669
Test name
Test status
Simulation time 164357717 ps
CPU time 0.86 seconds
Started Jun 23 05:21:58 PM PDT 24
Finished Jun 23 05:21:59 PM PDT 24
Peak memory 206104 kb
Host smart-4684b9f9-12ae-440c-8bba-04aad02b0ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35226
65885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3522665885
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.551596993
Short name T356
Test name
Test status
Simulation time 193092114 ps
CPU time 0.82 seconds
Started Jun 23 05:21:53 PM PDT 24
Finished Jun 23 05:21:55 PM PDT 24
Peak memory 206104 kb
Host smart-b4e7a3d8-241d-456e-984f-0bef17e31a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55159
6993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.551596993
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.137602158
Short name T1257
Test name
Test status
Simulation time 189532512 ps
CPU time 0.86 seconds
Started Jun 23 05:21:53 PM PDT 24
Finished Jun 23 05:21:54 PM PDT 24
Peak memory 206116 kb
Host smart-a758d5c7-8631-40f6-be19-42649895de33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13760
2158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.137602158
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.4172037821
Short name T965
Test name
Test status
Simulation time 130195644 ps
CPU time 0.74 seconds
Started Jun 23 05:22:01 PM PDT 24
Finished Jun 23 05:22:02 PM PDT 24
Peak memory 206004 kb
Host smart-eb8d0cb4-17e0-47cd-8bd2-c1f55fb0b383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41720
37821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.4172037821
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2216127430
Short name T2378
Test name
Test status
Simulation time 142771040 ps
CPU time 0.73 seconds
Started Jun 23 05:21:55 PM PDT 24
Finished Jun 23 05:21:57 PM PDT 24
Peak memory 206092 kb
Host smart-6a0bf078-754e-446d-9a32-eaed8c1c610d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22161
27430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2216127430
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2418236594
Short name T1202
Test name
Test status
Simulation time 154534589 ps
CPU time 0.83 seconds
Started Jun 23 05:21:53 PM PDT 24
Finished Jun 23 05:21:55 PM PDT 24
Peak memory 206024 kb
Host smart-d030d13c-d36f-4708-923a-0841dad6ffd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24182
36594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2418236594
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3493240382
Short name T2010
Test name
Test status
Simulation time 253537396 ps
CPU time 1.02 seconds
Started Jun 23 05:21:49 PM PDT 24
Finished Jun 23 05:21:51 PM PDT 24
Peak memory 206064 kb
Host smart-217e0942-0d5e-43d3-8133-96a2d24f78d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34932
40382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3493240382
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.4105982456
Short name T1421
Test name
Test status
Simulation time 6130283917 ps
CPU time 43.04 seconds
Started Jun 23 05:22:00 PM PDT 24
Finished Jun 23 05:22:44 PM PDT 24
Peak memory 206296 kb
Host smart-27afb1f9-b101-4810-83d3-95987c2b6052
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4105982456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.4105982456
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1810802620
Short name T24
Test name
Test status
Simulation time 151678692 ps
CPU time 0.88 seconds
Started Jun 23 05:21:57 PM PDT 24
Finished Jun 23 05:21:58 PM PDT 24
Peak memory 206036 kb
Host smart-a0c4db01-0db8-418d-8591-2fcd13f98b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18108
02620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1810802620
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1456146278
Short name T1846
Test name
Test status
Simulation time 152195709 ps
CPU time 0.82 seconds
Started Jun 23 05:21:54 PM PDT 24
Finished Jun 23 05:21:57 PM PDT 24
Peak memory 206040 kb
Host smart-e7bddef1-08ce-41b6-8e14-66cc1d5a2834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14561
46278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1456146278
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.2965112973
Short name T977
Test name
Test status
Simulation time 8408604656 ps
CPU time 230.29 seconds
Started Jun 23 05:21:57 PM PDT 24
Finished Jun 23 05:25:48 PM PDT 24
Peak memory 206320 kb
Host smart-9f9ddf91-cefb-40ce-9a7e-3e1bdda9ed28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29651
12973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.2965112973
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2733912785
Short name T825
Test name
Test status
Simulation time 3823482000 ps
CPU time 4.98 seconds
Started Jun 23 05:22:02 PM PDT 24
Finished Jun 23 05:22:07 PM PDT 24
Peak memory 206116 kb
Host smart-319487ed-4f32-438c-94f4-26cb7323dcd5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2733912785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.2733912785
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.1094616135
Short name T1528
Test name
Test status
Simulation time 13403784121 ps
CPU time 12.12 seconds
Started Jun 23 05:22:00 PM PDT 24
Finished Jun 23 05:22:12 PM PDT 24
Peak memory 206172 kb
Host smart-b8cc24eb-dcd8-4127-9382-b6756f6ce295
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1094616135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1094616135
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.523616924
Short name T1750
Test name
Test status
Simulation time 23413049397 ps
CPU time 28.8 seconds
Started Jun 23 05:22:01 PM PDT 24
Finished Jun 23 05:22:30 PM PDT 24
Peak memory 206088 kb
Host smart-7cea10cb-a842-449d-8966-a390d2867323
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=523616924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.523616924
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3256158481
Short name T548
Test name
Test status
Simulation time 151876241 ps
CPU time 0.83 seconds
Started Jun 23 05:22:00 PM PDT 24
Finished Jun 23 05:22:01 PM PDT 24
Peak memory 206064 kb
Host smart-0c7d21a7-0ca0-4a81-9464-1de794be8d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32561
58481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3256158481
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.3146015551
Short name T1263
Test name
Test status
Simulation time 151123265 ps
CPU time 0.78 seconds
Started Jun 23 05:21:59 PM PDT 24
Finished Jun 23 05:22:00 PM PDT 24
Peak memory 206068 kb
Host smart-7b51df28-e798-40c2-86ce-ab1f45373767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31460
15551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.3146015551
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.368385286
Short name T2109
Test name
Test status
Simulation time 301170469 ps
CPU time 1.09 seconds
Started Jun 23 05:21:59 PM PDT 24
Finished Jun 23 05:22:01 PM PDT 24
Peak memory 206104 kb
Host smart-e7d23cc1-eb1f-4549-89d5-5ffed9a8a92a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36838
5286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.368385286
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.2915471304
Short name T158
Test name
Test status
Simulation time 894791196 ps
CPU time 2.06 seconds
Started Jun 23 05:21:59 PM PDT 24
Finished Jun 23 05:22:01 PM PDT 24
Peak memory 206272 kb
Host smart-2d7d4de6-094e-4ae4-8ace-3a032a09a746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29154
71304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.2915471304
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.3353127209
Short name T980
Test name
Test status
Simulation time 15804623533 ps
CPU time 33.43 seconds
Started Jun 23 05:22:02 PM PDT 24
Finished Jun 23 05:22:36 PM PDT 24
Peak memory 206404 kb
Host smart-d049d5c0-74b6-4819-b909-744c8bbf998d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33531
27209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.3353127209
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.2321708143
Short name T701
Test name
Test status
Simulation time 311976015 ps
CPU time 1.09 seconds
Started Jun 23 05:21:59 PM PDT 24
Finished Jun 23 05:22:01 PM PDT 24
Peak memory 206108 kb
Host smart-9197ac0b-02bb-46b4-923b-4e3bbba3a45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23217
08143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.2321708143
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.2457010781
Short name T473
Test name
Test status
Simulation time 142182159 ps
CPU time 0.76 seconds
Started Jun 23 05:22:00 PM PDT 24
Finished Jun 23 05:22:01 PM PDT 24
Peak memory 205872 kb
Host smart-06e7e96e-9c85-40ae-a2c8-db64051bfd44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24570
10781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.2457010781
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3527092832
Short name T739
Test name
Test status
Simulation time 37700228 ps
CPU time 0.68 seconds
Started Jun 23 05:21:58 PM PDT 24
Finished Jun 23 05:22:00 PM PDT 24
Peak memory 206012 kb
Host smart-c0cd2635-48ca-490a-91f9-3caa87fb45e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35270
92832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3527092832
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.4005212598
Short name T2163
Test name
Test status
Simulation time 837764442 ps
CPU time 2.04 seconds
Started Jun 23 05:22:01 PM PDT 24
Finished Jun 23 05:22:04 PM PDT 24
Peak memory 206336 kb
Host smart-3d68e6ae-52da-4ac8-bf59-0d55e96b4832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40052
12598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.4005212598
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3615351443
Short name T583
Test name
Test status
Simulation time 219991602 ps
CPU time 1.49 seconds
Started Jun 23 05:22:01 PM PDT 24
Finished Jun 23 05:22:03 PM PDT 24
Peak memory 206364 kb
Host smart-237712b4-2895-4f85-be6b-baa9df497b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36153
51443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3615351443
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1996677191
Short name T30
Test name
Test status
Simulation time 166699355 ps
CPU time 0.82 seconds
Started Jun 23 05:22:08 PM PDT 24
Finished Jun 23 05:22:10 PM PDT 24
Peak memory 206020 kb
Host smart-402a71c2-de95-4a96-925b-54f81bf683f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19966
77191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1996677191
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1687556988
Short name T2046
Test name
Test status
Simulation time 157054110 ps
CPU time 0.79 seconds
Started Jun 23 05:22:06 PM PDT 24
Finished Jun 23 05:22:08 PM PDT 24
Peak memory 206040 kb
Host smart-c4b6c5f9-d61d-4ef0-84f0-45c4e026e6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16875
56988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1687556988
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3410945878
Short name T1041
Test name
Test status
Simulation time 160688466 ps
CPU time 0.8 seconds
Started Jun 23 05:21:59 PM PDT 24
Finished Jun 23 05:22:00 PM PDT 24
Peak memory 206284 kb
Host smart-1f4d37fe-d670-4dd3-9b01-26737dba72cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34109
45878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3410945878
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.1384144947
Short name T1914
Test name
Test status
Simulation time 18719595220 ps
CPU time 540.02 seconds
Started Jun 23 05:21:59 PM PDT 24
Finished Jun 23 05:31:00 PM PDT 24
Peak memory 206344 kb
Host smart-2c80a20d-fae9-4e91-8575-3f44e61a2bfd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1384144947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.1384144947
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.661272735
Short name T1079
Test name
Test status
Simulation time 217360553 ps
CPU time 0.86 seconds
Started Jun 23 05:22:00 PM PDT 24
Finished Jun 23 05:22:02 PM PDT 24
Peak memory 206104 kb
Host smart-715d35e4-640b-491e-b23a-c39835b3d174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66127
2735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.661272735
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.1733364446
Short name T39
Test name
Test status
Simulation time 23349548655 ps
CPU time 28.42 seconds
Started Jun 23 05:21:59 PM PDT 24
Finished Jun 23 05:22:28 PM PDT 24
Peak memory 206152 kb
Host smart-b0be8b98-d4d3-4a20-857c-411564d299bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17333
64446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.1733364446
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.50653033
Short name T2128
Test name
Test status
Simulation time 3264040520 ps
CPU time 4.6 seconds
Started Jun 23 05:22:00 PM PDT 24
Finished Jun 23 05:22:05 PM PDT 24
Peak memory 206172 kb
Host smart-6f65a002-f75d-4ab0-b152-a0fbb264f508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50653
033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.50653033
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.4291880710
Short name T5
Test name
Test status
Simulation time 8472659391 ps
CPU time 245.64 seconds
Started Jun 23 05:22:00 PM PDT 24
Finished Jun 23 05:26:07 PM PDT 24
Peak memory 206320 kb
Host smart-933268ef-ba79-469a-b9b9-b6c199f53b37
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4291880710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.4291880710
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1799413424
Short name T298
Test name
Test status
Simulation time 261547541 ps
CPU time 0.88 seconds
Started Jun 23 05:22:06 PM PDT 24
Finished Jun 23 05:22:08 PM PDT 24
Peak memory 206060 kb
Host smart-f7e19d97-a144-4712-8dab-2719bc322c7a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1799413424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1799413424
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2648754120
Short name T1514
Test name
Test status
Simulation time 203261681 ps
CPU time 0.91 seconds
Started Jun 23 05:22:00 PM PDT 24
Finished Jun 23 05:22:02 PM PDT 24
Peak memory 206116 kb
Host smart-c4e2304e-3cd1-4bae-a9f3-290119e99dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26487
54120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2648754120
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.2415211142
Short name T2469
Test name
Test status
Simulation time 10370699741 ps
CPU time 95.12 seconds
Started Jun 23 05:21:58 PM PDT 24
Finished Jun 23 05:23:34 PM PDT 24
Peak memory 206380 kb
Host smart-22d73ac2-6d6d-44f0-b1e3-eda67af2b382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24152
11142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.2415211142
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.2338297921
Short name T451
Test name
Test status
Simulation time 6240985008 ps
CPU time 58.27 seconds
Started Jun 23 05:22:00 PM PDT 24
Finished Jun 23 05:22:59 PM PDT 24
Peak memory 206352 kb
Host smart-71f4b3bf-a0bd-4287-b9b7-e33f1d565fe7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2338297921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.2338297921
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.3370531172
Short name T327
Test name
Test status
Simulation time 161951295 ps
CPU time 0.82 seconds
Started Jun 23 05:22:05 PM PDT 24
Finished Jun 23 05:22:06 PM PDT 24
Peak memory 206084 kb
Host smart-06f7b470-b69e-403f-b22e-b5ff2a2c8033
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3370531172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.3370531172
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.3327659297
Short name T696
Test name
Test status
Simulation time 159303615 ps
CPU time 0.8 seconds
Started Jun 23 05:22:02 PM PDT 24
Finished Jun 23 05:22:03 PM PDT 24
Peak memory 206028 kb
Host smart-2c6cbcaa-504e-4596-a0cd-aa03692f22a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33276
59297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.3327659297
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.500385957
Short name T2355
Test name
Test status
Simulation time 214666743 ps
CPU time 0.89 seconds
Started Jun 23 05:22:09 PM PDT 24
Finished Jun 23 05:22:10 PM PDT 24
Peak memory 206036 kb
Host smart-6ba0877e-26cd-4815-a998-f9627495d540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50038
5957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.500385957
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1928340686
Short name T1032
Test name
Test status
Simulation time 148045687 ps
CPU time 0.82 seconds
Started Jun 23 05:22:06 PM PDT 24
Finished Jun 23 05:22:08 PM PDT 24
Peak memory 206040 kb
Host smart-6769aeb0-f9ae-42f3-a042-c602afbb7f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19283
40686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1928340686
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3994534465
Short name T1757
Test name
Test status
Simulation time 244917924 ps
CPU time 0.86 seconds
Started Jun 23 05:22:06 PM PDT 24
Finished Jun 23 05:22:08 PM PDT 24
Peak memory 206120 kb
Host smart-e7153a60-bfb9-4971-a4f7-1cc2985036d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39945
34465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3994534465
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1208603758
Short name T1496
Test name
Test status
Simulation time 142835233 ps
CPU time 0.75 seconds
Started Jun 23 05:22:06 PM PDT 24
Finished Jun 23 05:22:07 PM PDT 24
Peak memory 206052 kb
Host smart-ee03a871-c31a-4d32-ba10-7c9af958a43f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12086
03758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1208603758
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.1558371958
Short name T1933
Test name
Test status
Simulation time 186602497 ps
CPU time 0.82 seconds
Started Jun 23 05:22:04 PM PDT 24
Finished Jun 23 05:22:05 PM PDT 24
Peak memory 205988 kb
Host smart-d8537805-97c9-4f60-97ce-80a1f2459be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15583
71958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.1558371958
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.981344242
Short name T372
Test name
Test status
Simulation time 236669834 ps
CPU time 0.91 seconds
Started Jun 23 05:22:06 PM PDT 24
Finished Jun 23 05:22:08 PM PDT 24
Peak memory 206056 kb
Host smart-ade3fe9f-7dca-4a73-b7dd-9ebd2b187cd8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=981344242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.981344242
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2122993219
Short name T1290
Test name
Test status
Simulation time 168679934 ps
CPU time 0.83 seconds
Started Jun 23 05:22:08 PM PDT 24
Finished Jun 23 05:22:10 PM PDT 24
Peak memory 206100 kb
Host smart-6d04b9eb-d2e3-4321-bfd4-15ffc9c936c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21229
93219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2122993219
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3273953064
Short name T35
Test name
Test status
Simulation time 39668665 ps
CPU time 0.67 seconds
Started Jun 23 05:22:07 PM PDT 24
Finished Jun 23 05:22:09 PM PDT 24
Peak memory 206112 kb
Host smart-0eb42460-cb59-40a6-b52b-1c3717b29fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32739
53064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3273953064
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.296523735
Short name T86
Test name
Test status
Simulation time 16483367224 ps
CPU time 37.63 seconds
Started Jun 23 05:22:04 PM PDT 24
Finished Jun 23 05:22:43 PM PDT 24
Peak memory 206432 kb
Host smart-d1e3c587-0106-469b-bd3e-3dfcda9941e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29652
3735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.296523735
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.2187671922
Short name T2119
Test name
Test status
Simulation time 152726105 ps
CPU time 0.82 seconds
Started Jun 23 05:22:09 PM PDT 24
Finished Jun 23 05:22:11 PM PDT 24
Peak memory 206104 kb
Host smart-11b7af17-9fe2-4c00-8c82-5f8d29e6fc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21876
71922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2187671922
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.1587059489
Short name T403
Test name
Test status
Simulation time 218816707 ps
CPU time 0.93 seconds
Started Jun 23 05:22:02 PM PDT 24
Finished Jun 23 05:22:03 PM PDT 24
Peak memory 206068 kb
Host smart-c84c8efe-df3d-4570-a197-44461493ca1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15870
59489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1587059489
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3208007223
Short name T1530
Test name
Test status
Simulation time 230237870 ps
CPU time 0.89 seconds
Started Jun 23 05:22:06 PM PDT 24
Finished Jun 23 05:22:07 PM PDT 24
Peak memory 206124 kb
Host smart-804079d8-2a3b-4f62-8a13-b6a07f2bca0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32080
07223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3208007223
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.1161237611
Short name T2352
Test name
Test status
Simulation time 193739220 ps
CPU time 0.89 seconds
Started Jun 23 05:22:07 PM PDT 24
Finished Jun 23 05:22:09 PM PDT 24
Peak memory 206116 kb
Host smart-c7b25c05-0e69-4b19-9272-50e8016b78e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11612
37611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.1161237611
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1370402594
Short name T388
Test name
Test status
Simulation time 177697203 ps
CPU time 0.79 seconds
Started Jun 23 05:22:07 PM PDT 24
Finished Jun 23 05:22:09 PM PDT 24
Peak memory 206088 kb
Host smart-11ab9062-01e9-4d8c-829a-049abf53c26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13704
02594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1370402594
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.1162031094
Short name T532
Test name
Test status
Simulation time 154268386 ps
CPU time 0.78 seconds
Started Jun 23 05:22:09 PM PDT 24
Finished Jun 23 05:22:10 PM PDT 24
Peak memory 206036 kb
Host smart-28115319-2987-4356-abec-f9b33bb9960c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11620
31094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1162031094
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.862316980
Short name T1582
Test name
Test status
Simulation time 159975249 ps
CPU time 0.79 seconds
Started Jun 23 05:22:04 PM PDT 24
Finished Jun 23 05:22:05 PM PDT 24
Peak memory 206060 kb
Host smart-15aac52e-86e5-4ceb-991b-ad70fde5e193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86231
6980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.862316980
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3915959680
Short name T1005
Test name
Test status
Simulation time 214563357 ps
CPU time 0.87 seconds
Started Jun 23 05:21:59 PM PDT 24
Finished Jun 23 05:22:01 PM PDT 24
Peak memory 206100 kb
Host smart-6b9d86ac-37b8-465e-ba4d-9bade7854ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39159
59680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3915959680
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3475321485
Short name T1241
Test name
Test status
Simulation time 12509506616 ps
CPU time 87.66 seconds
Started Jun 23 05:22:05 PM PDT 24
Finished Jun 23 05:23:33 PM PDT 24
Peak memory 206340 kb
Host smart-7630ac58-6362-4ab9-9ccf-17bfed8e42f6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3475321485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3475321485
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2585431128
Short name T2235
Test name
Test status
Simulation time 216418752 ps
CPU time 0.81 seconds
Started Jun 23 05:22:04 PM PDT 24
Finished Jun 23 05:22:05 PM PDT 24
Peak memory 206028 kb
Host smart-552edc64-53f2-4271-9c33-4fd0073032a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25854
31128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2585431128
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.3860643090
Short name T2232
Test name
Test status
Simulation time 178076072 ps
CPU time 0.79 seconds
Started Jun 23 05:22:04 PM PDT 24
Finished Jun 23 05:22:05 PM PDT 24
Peak memory 206056 kb
Host smart-abde1f3d-86a8-4060-b296-c51d9aab0a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38606
43090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3860643090
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.1629016403
Short name T142
Test name
Test status
Simulation time 9406112294 ps
CPU time 83.41 seconds
Started Jun 23 05:22:06 PM PDT 24
Finished Jun 23 05:23:30 PM PDT 24
Peak memory 206260 kb
Host smart-e8b45a81-909e-4b2a-aa60-d861cde94abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16290
16403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.1629016403
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3187965859
Short name T625
Test name
Test status
Simulation time 4110608435 ps
CPU time 4.71 seconds
Started Jun 23 05:22:04 PM PDT 24
Finished Jun 23 05:22:09 PM PDT 24
Peak memory 206156 kb
Host smart-abe80fcb-bf29-45ac-8bcf-190790180f96
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3187965859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.3187965859
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.2743396148
Short name T959
Test name
Test status
Simulation time 13499991916 ps
CPU time 12.49 seconds
Started Jun 23 05:22:08 PM PDT 24
Finished Jun 23 05:22:21 PM PDT 24
Peak memory 206252 kb
Host smart-8b04030c-0ffc-4e64-a610-b6bd1baaf9de
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2743396148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.2743396148
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.2245377520
Short name T1532
Test name
Test status
Simulation time 23329797460 ps
CPU time 22.56 seconds
Started Jun 23 05:22:06 PM PDT 24
Finished Jun 23 05:22:29 PM PDT 24
Peak memory 206168 kb
Host smart-cc83f6ba-1191-4890-9751-04123b95c0b3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2245377520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.2245377520
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3380295518
Short name T1292
Test name
Test status
Simulation time 149448468 ps
CPU time 0.81 seconds
Started Jun 23 05:22:03 PM PDT 24
Finished Jun 23 05:22:05 PM PDT 24
Peak memory 206104 kb
Host smart-2a811032-bac8-470b-b817-e21ad4a63c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33802
95518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3380295518
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3044839130
Short name T1833
Test name
Test status
Simulation time 172829527 ps
CPU time 0.8 seconds
Started Jun 23 05:22:03 PM PDT 24
Finished Jun 23 05:22:04 PM PDT 24
Peak memory 206000 kb
Host smart-89050d19-07de-4cc9-8b37-5d44829d7b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30448
39130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3044839130
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.1951377537
Short name T1570
Test name
Test status
Simulation time 257280143 ps
CPU time 0.9 seconds
Started Jun 23 05:22:07 PM PDT 24
Finished Jun 23 05:22:08 PM PDT 24
Peak memory 206032 kb
Host smart-2a3744dc-0a9d-494b-bad6-e950d5cd8a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19513
77537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.1951377537
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.801073373
Short name T1424
Test name
Test status
Simulation time 1656731987 ps
CPU time 3.75 seconds
Started Jun 23 05:22:07 PM PDT 24
Finished Jun 23 05:22:12 PM PDT 24
Peak memory 206344 kb
Host smart-d97b419a-b1ab-42c3-836b-ffc5df367fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80107
3373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.801073373
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.483924294
Short name T904
Test name
Test status
Simulation time 14073484302 ps
CPU time 30.37 seconds
Started Jun 23 05:22:04 PM PDT 24
Finished Jun 23 05:22:35 PM PDT 24
Peak memory 206316 kb
Host smart-d6e3e575-3c22-4644-bb4b-68a33e6b5fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48392
4294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.483924294
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.727911415
Short name T1218
Test name
Test status
Simulation time 414009108 ps
CPU time 1.3 seconds
Started Jun 23 05:22:07 PM PDT 24
Finished Jun 23 05:22:10 PM PDT 24
Peak memory 206108 kb
Host smart-c644867f-b44a-4072-9e03-b9f692c7f1f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72791
1415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.727911415
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3780185614
Short name T1574
Test name
Test status
Simulation time 168158187 ps
CPU time 0.92 seconds
Started Jun 23 05:22:05 PM PDT 24
Finished Jun 23 05:22:06 PM PDT 24
Peak memory 206092 kb
Host smart-aea0182d-f8a0-4ba3-b3b4-fb199a9d2507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37801
85614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3780185614
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.336839033
Short name T1863
Test name
Test status
Simulation time 40639909 ps
CPU time 0.65 seconds
Started Jun 23 05:22:07 PM PDT 24
Finished Jun 23 05:22:09 PM PDT 24
Peak memory 206112 kb
Host smart-d6cb12a9-650e-43fe-8984-21f80d168ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33683
9033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.336839033
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2563807915
Short name T699
Test name
Test status
Simulation time 979737092 ps
CPU time 2.54 seconds
Started Jun 23 05:22:05 PM PDT 24
Finished Jun 23 05:22:08 PM PDT 24
Peak memory 206308 kb
Host smart-e5c112d7-0549-48c1-8fcb-ef76599771c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25638
07915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2563807915
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2801395906
Short name T845
Test name
Test status
Simulation time 319190772 ps
CPU time 1.73 seconds
Started Jun 23 05:22:08 PM PDT 24
Finished Jun 23 05:22:11 PM PDT 24
Peak memory 206484 kb
Host smart-92a565b5-e23f-4b5c-838b-1be204e51a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28013
95906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2801395906
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.1330624851
Short name T1043
Test name
Test status
Simulation time 215106217 ps
CPU time 0.92 seconds
Started Jun 23 05:22:10 PM PDT 24
Finished Jun 23 05:22:12 PM PDT 24
Peak memory 206104 kb
Host smart-fe08af93-a146-4751-a9bc-4e7d2c8839a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13306
24851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1330624851
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1821358563
Short name T1117
Test name
Test status
Simulation time 169684843 ps
CPU time 0.75 seconds
Started Jun 23 05:22:12 PM PDT 24
Finished Jun 23 05:22:13 PM PDT 24
Peak memory 205868 kb
Host smart-3f89f0cc-5dc8-4ce6-bdd6-9d29a7fdf6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18213
58563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1821358563
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2437009443
Short name T1657
Test name
Test status
Simulation time 201130406 ps
CPU time 0.87 seconds
Started Jun 23 05:22:10 PM PDT 24
Finished Jun 23 05:22:12 PM PDT 24
Peak memory 206024 kb
Host smart-bcfda88c-8717-4486-89a4-ed040917b19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24370
09443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2437009443
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.2114693399
Short name T1565
Test name
Test status
Simulation time 201560960 ps
CPU time 0.84 seconds
Started Jun 23 05:22:13 PM PDT 24
Finished Jun 23 05:22:14 PM PDT 24
Peak memory 206092 kb
Host smart-dfa2ee4d-7bfd-4afe-919e-220136512958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21146
93399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.2114693399
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.3658147780
Short name T1967
Test name
Test status
Simulation time 23301869914 ps
CPU time 23.95 seconds
Started Jun 23 05:22:10 PM PDT 24
Finished Jun 23 05:22:35 PM PDT 24
Peak memory 206164 kb
Host smart-f37e907e-de38-4103-b0fd-3db83f130414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36581
47780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.3658147780
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1826405731
Short name T2261
Test name
Test status
Simulation time 3277796151 ps
CPU time 3.95 seconds
Started Jun 23 05:22:10 PM PDT 24
Finished Jun 23 05:22:14 PM PDT 24
Peak memory 206104 kb
Host smart-81c5fc37-d0bf-4f8f-a4fe-dee596d12801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18264
05731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1826405731
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.3545375119
Short name T1448
Test name
Test status
Simulation time 10869720700 ps
CPU time 297.74 seconds
Started Jun 23 05:22:12 PM PDT 24
Finished Jun 23 05:27:10 PM PDT 24
Peak memory 206368 kb
Host smart-07ab0b9b-7e6a-4370-a99f-33fe49bd012f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3545375119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.3545375119
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.4289297080
Short name T883
Test name
Test status
Simulation time 255629947 ps
CPU time 0.9 seconds
Started Jun 23 05:22:10 PM PDT 24
Finished Jun 23 05:22:12 PM PDT 24
Peak memory 206140 kb
Host smart-3681378c-2b35-4f60-bed4-5ae99bb7d26e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4289297080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.4289297080
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3280729151
Short name T285
Test name
Test status
Simulation time 221655948 ps
CPU time 0.87 seconds
Started Jun 23 05:22:12 PM PDT 24
Finished Jun 23 05:22:14 PM PDT 24
Peak memory 206132 kb
Host smart-2c9176b7-c7ed-44fa-a396-49b268766751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32807
29151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3280729151
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.1365807603
Short name T502
Test name
Test status
Simulation time 11055002477 ps
CPU time 84.79 seconds
Started Jun 23 05:22:08 PM PDT 24
Finished Jun 23 05:23:34 PM PDT 24
Peak memory 206432 kb
Host smart-1fdc6631-57df-4b2a-8435-ee203f525052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13658
07603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.1365807603
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.1123468792
Short name T1760
Test name
Test status
Simulation time 3543446780 ps
CPU time 33.68 seconds
Started Jun 23 05:22:09 PM PDT 24
Finished Jun 23 05:22:43 PM PDT 24
Peak memory 206352 kb
Host smart-f1544ed0-a4a1-47d7-9c08-61fafc7b8bf3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1123468792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.1123468792
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.1429181686
Short name T730
Test name
Test status
Simulation time 158679161 ps
CPU time 0.76 seconds
Started Jun 23 05:22:11 PM PDT 24
Finished Jun 23 05:22:13 PM PDT 24
Peak memory 206128 kb
Host smart-26d431da-a640-4463-a1f6-a230f5ac5bd2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1429181686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.1429181686
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.4112105533
Short name T2222
Test name
Test status
Simulation time 166751868 ps
CPU time 0.81 seconds
Started Jun 23 05:22:10 PM PDT 24
Finished Jun 23 05:22:11 PM PDT 24
Peak memory 206112 kb
Host smart-35c0d9df-ec95-46ef-b1f7-f2b2f7bbe43d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41121
05533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.4112105533
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2743544124
Short name T119
Test name
Test status
Simulation time 217237480 ps
CPU time 0.92 seconds
Started Jun 23 05:22:10 PM PDT 24
Finished Jun 23 05:22:12 PM PDT 24
Peak memory 206024 kb
Host smart-ff167627-fa42-4f2d-9291-2a90f7b1042a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27435
44124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2743544124
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.78080567
Short name T92
Test name
Test status
Simulation time 163490186 ps
CPU time 0.82 seconds
Started Jun 23 05:22:08 PM PDT 24
Finished Jun 23 05:22:10 PM PDT 24
Peak memory 206080 kb
Host smart-d9132ed0-77bc-4a61-bcf4-f512903dcb3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78080
567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.78080567
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1754370293
Short name T1699
Test name
Test status
Simulation time 193081866 ps
CPU time 0.84 seconds
Started Jun 23 05:22:11 PM PDT 24
Finished Jun 23 05:22:13 PM PDT 24
Peak memory 206004 kb
Host smart-c5e8c6d3-2d15-47ea-a002-c7d4e7dea314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17543
70293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1754370293
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3358146384
Short name T1718
Test name
Test status
Simulation time 188006284 ps
CPU time 0.78 seconds
Started Jun 23 05:22:10 PM PDT 24
Finished Jun 23 05:22:12 PM PDT 24
Peak memory 206116 kb
Host smart-d0dc3acf-99c1-4994-92b2-51f1a2d6181a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33581
46384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3358146384
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3530675534
Short name T1549
Test name
Test status
Simulation time 156337179 ps
CPU time 0.79 seconds
Started Jun 23 05:22:09 PM PDT 24
Finished Jun 23 05:22:11 PM PDT 24
Peak memory 206100 kb
Host smart-9bf1211f-3730-4699-861f-06063dfa7530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35306
75534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3530675534
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.2209785883
Short name T2440
Test name
Test status
Simulation time 225481151 ps
CPU time 0.93 seconds
Started Jun 23 05:22:10 PM PDT 24
Finished Jun 23 05:22:12 PM PDT 24
Peak memory 206120 kb
Host smart-75550b00-e91a-439a-a9fc-33c52cb2dde6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2209785883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.2209785883
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.944636748
Short name T1253
Test name
Test status
Simulation time 144765653 ps
CPU time 0.74 seconds
Started Jun 23 05:22:11 PM PDT 24
Finished Jun 23 05:22:13 PM PDT 24
Peak memory 206120 kb
Host smart-78882214-f8e7-4ed7-b8b9-9ada95b16fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94463
6748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.944636748
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2969459573
Short name T998
Test name
Test status
Simulation time 59619634 ps
CPU time 0.69 seconds
Started Jun 23 05:22:11 PM PDT 24
Finished Jun 23 05:22:13 PM PDT 24
Peak memory 206100 kb
Host smart-3f8eff0b-9c8d-4132-968e-71f2ec35ec05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29694
59573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2969459573
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3522374511
Short name T1509
Test name
Test status
Simulation time 14819325479 ps
CPU time 36.44 seconds
Started Jun 23 05:22:09 PM PDT 24
Finished Jun 23 05:22:46 PM PDT 24
Peak memory 206348 kb
Host smart-41f79f2a-2828-4210-8b40-1128678d95fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35223
74511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3522374511
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1945963865
Short name T674
Test name
Test status
Simulation time 208331878 ps
CPU time 0.86 seconds
Started Jun 23 05:22:10 PM PDT 24
Finished Jun 23 05:22:12 PM PDT 24
Peak memory 206108 kb
Host smart-9ad0b586-ce4a-475d-9cae-51253df524a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19459
63865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1945963865
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.686525491
Short name T498
Test name
Test status
Simulation time 195852568 ps
CPU time 0.86 seconds
Started Jun 23 05:22:11 PM PDT 24
Finished Jun 23 05:22:13 PM PDT 24
Peak memory 206096 kb
Host smart-de1a6136-f568-4ce5-ba0e-b728ffd7cb85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68652
5491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.686525491
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.4076123322
Short name T1425
Test name
Test status
Simulation time 191982438 ps
CPU time 0.83 seconds
Started Jun 23 05:22:10 PM PDT 24
Finished Jun 23 05:22:12 PM PDT 24
Peak memory 206064 kb
Host smart-f54d2293-06fb-4dd5-aeac-ccd40c723e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40761
23322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.4076123322
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3718249720
Short name T1343
Test name
Test status
Simulation time 176777083 ps
CPU time 0.79 seconds
Started Jun 23 05:22:10 PM PDT 24
Finished Jun 23 05:22:12 PM PDT 24
Peak memory 206056 kb
Host smart-581099d6-1b39-4002-994d-121f4dc7c9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37182
49720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3718249720
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.2976785646
Short name T695
Test name
Test status
Simulation time 259020777 ps
CPU time 0.9 seconds
Started Jun 23 05:22:10 PM PDT 24
Finished Jun 23 05:22:11 PM PDT 24
Peak memory 206040 kb
Host smart-6a9ee39e-cd21-42e2-87d7-b11512eeacc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29767
85646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.2976785646
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3281297160
Short name T1777
Test name
Test status
Simulation time 174115730 ps
CPU time 0.85 seconds
Started Jun 23 05:22:09 PM PDT 24
Finished Jun 23 05:22:11 PM PDT 24
Peak memory 206016 kb
Host smart-463dcef6-a82a-4004-91d2-673bc4424052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32812
97160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3281297160
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3207776203
Short name T1871
Test name
Test status
Simulation time 154385644 ps
CPU time 0.78 seconds
Started Jun 23 05:22:11 PM PDT 24
Finished Jun 23 05:22:12 PM PDT 24
Peak memory 206104 kb
Host smart-a3d0195b-e926-45e1-8a7a-c441a8e9a375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32077
76203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3207776203
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3846048631
Short name T1516
Test name
Test status
Simulation time 181382535 ps
CPU time 0.85 seconds
Started Jun 23 05:22:06 PM PDT 24
Finished Jun 23 05:22:07 PM PDT 24
Peak memory 206108 kb
Host smart-5158109d-783d-4969-b74a-029430fc8147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38460
48631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3846048631
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.2283627088
Short name T744
Test name
Test status
Simulation time 8479528239 ps
CPU time 246.2 seconds
Started Jun 23 05:22:09 PM PDT 24
Finished Jun 23 05:26:16 PM PDT 24
Peak memory 206472 kb
Host smart-e8eb5845-5070-4d42-aa72-3e085ae542e9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2283627088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.2283627088
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.900827677
Short name T2422
Test name
Test status
Simulation time 169533360 ps
CPU time 0.78 seconds
Started Jun 23 05:22:11 PM PDT 24
Finished Jun 23 05:22:13 PM PDT 24
Peak memory 206096 kb
Host smart-23068751-d65a-4b5b-8b9c-7f408b372f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90082
7677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.900827677
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.131344408
Short name T990
Test name
Test status
Simulation time 205066179 ps
CPU time 0.83 seconds
Started Jun 23 05:22:11 PM PDT 24
Finished Jun 23 05:22:13 PM PDT 24
Peak memory 206092 kb
Host smart-2e9cd368-4c89-4121-8007-82dbf6a9a58f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13134
4408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.131344408
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2017029552
Short name T1354
Test name
Test status
Simulation time 13790177800 ps
CPU time 127.82 seconds
Started Jun 23 05:22:07 PM PDT 24
Finished Jun 23 05:24:16 PM PDT 24
Peak memory 206272 kb
Host smart-35da1d1f-aac3-41d1-b64c-f8304030762d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20170
29552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2017029552
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.355260531
Short name T435
Test name
Test status
Simulation time 3930108609 ps
CPU time 4.64 seconds
Started Jun 23 05:22:09 PM PDT 24
Finished Jun 23 05:22:14 PM PDT 24
Peak memory 206352 kb
Host smart-b73b6279-8d20-40e8-a876-a92d930595d3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=355260531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.355260531
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.2285230976
Short name T2428
Test name
Test status
Simulation time 13323368453 ps
CPU time 13.17 seconds
Started Jun 23 05:22:13 PM PDT 24
Finished Jun 23 05:22:26 PM PDT 24
Peak memory 206168 kb
Host smart-cff43bdf-c50f-4f7e-825d-348bdaad9b2f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2285230976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.2285230976
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.785570422
Short name T183
Test name
Test status
Simulation time 23335832968 ps
CPU time 27.81 seconds
Started Jun 23 05:22:16 PM PDT 24
Finished Jun 23 05:22:44 PM PDT 24
Peak memory 206308 kb
Host smart-f0d5dfea-d693-499d-b4fa-3f3e90068981
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=785570422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.785570422
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1730305151
Short name T1463
Test name
Test status
Simulation time 185549089 ps
CPU time 0.92 seconds
Started Jun 23 05:22:15 PM PDT 24
Finished Jun 23 05:22:17 PM PDT 24
Peak memory 206064 kb
Host smart-9b78e910-da58-4b02-8754-560487549278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17303
05151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1730305151
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.2614080408
Short name T1396
Test name
Test status
Simulation time 152657623 ps
CPU time 0.83 seconds
Started Jun 23 05:22:15 PM PDT 24
Finished Jun 23 05:22:17 PM PDT 24
Peak memory 206104 kb
Host smart-4387c685-1042-4faa-9e0e-baa4b3710529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26140
80408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.2614080408
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.478263503
Short name T2090
Test name
Test status
Simulation time 229577181 ps
CPU time 0.94 seconds
Started Jun 23 05:22:14 PM PDT 24
Finished Jun 23 05:22:15 PM PDT 24
Peak memory 205832 kb
Host smart-5d4f7f22-fa87-4bf6-b13a-f12f3327352e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47826
3503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.478263503
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1395499044
Short name T2076
Test name
Test status
Simulation time 748415550 ps
CPU time 1.82 seconds
Started Jun 23 05:22:16 PM PDT 24
Finished Jun 23 05:22:18 PM PDT 24
Peak memory 206196 kb
Host smart-bfc4d4e9-08ee-45fc-a96d-46220b9dda0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13954
99044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1395499044
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.3052262858
Short name T1877
Test name
Test status
Simulation time 11549506700 ps
CPU time 20.92 seconds
Started Jun 23 05:22:18 PM PDT 24
Finished Jun 23 05:22:40 PM PDT 24
Peak memory 206188 kb
Host smart-14bb931b-4619-46f6-b5e5-7fdf0b22b588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30522
62858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.3052262858
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.1523750231
Short name T1817
Test name
Test status
Simulation time 419182496 ps
CPU time 1.36 seconds
Started Jun 23 05:22:22 PM PDT 24
Finished Jun 23 05:22:25 PM PDT 24
Peak memory 206036 kb
Host smart-3784a9d2-76e8-4649-9981-e282b94e66d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15237
50231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.1523750231
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.2541923347
Short name T853
Test name
Test status
Simulation time 154172955 ps
CPU time 0.77 seconds
Started Jun 23 05:22:16 PM PDT 24
Finished Jun 23 05:22:17 PM PDT 24
Peak memory 206068 kb
Host smart-88095ebf-a06d-409b-91cc-01b34f643c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25419
23347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.2541923347
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1288366949
Short name T1042
Test name
Test status
Simulation time 32821028 ps
CPU time 0.63 seconds
Started Jun 23 05:22:15 PM PDT 24
Finished Jun 23 05:22:16 PM PDT 24
Peak memory 206016 kb
Host smart-719fdad2-e0f7-42d8-9454-0d661b56844e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12883
66949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1288366949
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1409639108
Short name T1185
Test name
Test status
Simulation time 882520148 ps
CPU time 2 seconds
Started Jun 23 05:22:17 PM PDT 24
Finished Jun 23 05:22:19 PM PDT 24
Peak memory 206260 kb
Host smart-69fa4c27-9d31-4470-a389-4f6986475b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14096
39108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1409639108
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3542831762
Short name T1203
Test name
Test status
Simulation time 271526487 ps
CPU time 1.88 seconds
Started Jun 23 05:22:13 PM PDT 24
Finished Jun 23 05:22:15 PM PDT 24
Peak memory 206344 kb
Host smart-16a6be64-8c4f-4945-b19f-63d6be4d49ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35428
31762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3542831762
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.6305157
Short name T635
Test name
Test status
Simulation time 242661339 ps
CPU time 0.91 seconds
Started Jun 23 05:22:23 PM PDT 24
Finished Jun 23 05:22:25 PM PDT 24
Peak memory 205920 kb
Host smart-ef8d9c54-3b28-460a-b61d-6acd01445499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63051
57 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.6305157
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.4135607515
Short name T1252
Test name
Test status
Simulation time 145707961 ps
CPU time 0.78 seconds
Started Jun 23 05:22:18 PM PDT 24
Finished Jun 23 05:22:20 PM PDT 24
Peak memory 206056 kb
Host smart-84022903-b7e4-4129-ad20-36ebe5f9a84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41356
07515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.4135607515
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3435847390
Short name T2363
Test name
Test status
Simulation time 238637237 ps
CPU time 0.91 seconds
Started Jun 23 05:22:16 PM PDT 24
Finished Jun 23 05:22:18 PM PDT 24
Peak memory 206104 kb
Host smart-e3ecfa49-4bc3-44b0-92b3-bf403e26d13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34358
47390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3435847390
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.205038642
Short name T1983
Test name
Test status
Simulation time 159440377 ps
CPU time 0.82 seconds
Started Jun 23 05:22:17 PM PDT 24
Finished Jun 23 05:22:19 PM PDT 24
Peak memory 206096 kb
Host smart-26105e5d-1c22-483a-a08b-63bd55aceb38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20503
8642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.205038642
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.2869536465
Short name T2454
Test name
Test status
Simulation time 23341864262 ps
CPU time 24.75 seconds
Started Jun 23 05:22:15 PM PDT 24
Finished Jun 23 05:22:40 PM PDT 24
Peak memory 206160 kb
Host smart-e30a0719-3e2d-4a82-8f42-9d5129a6b85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28695
36465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.2869536465
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3051099425
Short name T505
Test name
Test status
Simulation time 3344792421 ps
CPU time 4.49 seconds
Started Jun 23 05:22:16 PM PDT 24
Finished Jun 23 05:22:21 PM PDT 24
Peak memory 206076 kb
Host smart-3e279d1c-ceb5-40e0-9679-0eb37ee74f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30510
99425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3051099425
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.4283967918
Short name T1228
Test name
Test status
Simulation time 8783966971 ps
CPU time 61.16 seconds
Started Jun 23 05:22:14 PM PDT 24
Finished Jun 23 05:23:16 PM PDT 24
Peak memory 206304 kb
Host smart-9c5ddec0-ace6-49ca-b214-bfd4f73a000c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4283967918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.4283967918
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.1416771306
Short name T1795
Test name
Test status
Simulation time 264211282 ps
CPU time 0.93 seconds
Started Jun 23 05:22:20 PM PDT 24
Finished Jun 23 05:22:22 PM PDT 24
Peak memory 206128 kb
Host smart-4e090907-1454-4abc-88a7-c0413c556ce8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1416771306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.1416771306
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2682623345
Short name T1692
Test name
Test status
Simulation time 208081446 ps
CPU time 0.95 seconds
Started Jun 23 05:22:15 PM PDT 24
Finished Jun 23 05:22:16 PM PDT 24
Peak memory 206084 kb
Host smart-22e852da-ec6a-4073-bb5e-003b3f9df86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26826
23345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2682623345
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.317119011
Short name T1379
Test name
Test status
Simulation time 11044936105 ps
CPU time 317.77 seconds
Started Jun 23 05:22:18 PM PDT 24
Finished Jun 23 05:27:37 PM PDT 24
Peak memory 206256 kb
Host smart-73c5d901-eb8c-4bd4-8a23-7324e6bc637f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31711
9011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.317119011
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3376477987
Short name T970
Test name
Test status
Simulation time 8515864301 ps
CPU time 65.67 seconds
Started Jun 23 05:22:12 PM PDT 24
Finished Jun 23 05:23:19 PM PDT 24
Peak memory 206312 kb
Host smart-a0df3f78-d59f-40ff-b1f2-faf0b48f77f6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3376477987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3376477987
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.1536932750
Short name T1015
Test name
Test status
Simulation time 158530594 ps
CPU time 0.78 seconds
Started Jun 23 05:22:21 PM PDT 24
Finished Jun 23 05:22:23 PM PDT 24
Peak memory 206128 kb
Host smart-bc6336fd-0215-4075-a284-da758200dd5a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1536932750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.1536932750
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.712246849
Short name T1300
Test name
Test status
Simulation time 174225405 ps
CPU time 0.8 seconds
Started Jun 23 05:22:17 PM PDT 24
Finished Jun 23 05:22:18 PM PDT 24
Peak memory 206060 kb
Host smart-195cc649-b40c-436a-a6f5-22e480251d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71224
6849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.712246849
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1188295163
Short name T1927
Test name
Test status
Simulation time 233906090 ps
CPU time 0.97 seconds
Started Jun 23 05:22:16 PM PDT 24
Finished Jun 23 05:22:17 PM PDT 24
Peak memory 206060 kb
Host smart-a35c4be2-ea7b-4222-b530-c11c6b491069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11882
95163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1188295163
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2544316294
Short name T1118
Test name
Test status
Simulation time 173214461 ps
CPU time 0.83 seconds
Started Jun 23 05:22:14 PM PDT 24
Finished Jun 23 05:22:15 PM PDT 24
Peak memory 205860 kb
Host smart-caac0eeb-8871-4661-a1a6-a9a1fcdf057e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25443
16294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2544316294
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3767144753
Short name T2330
Test name
Test status
Simulation time 179531183 ps
CPU time 0.84 seconds
Started Jun 23 05:22:19 PM PDT 24
Finished Jun 23 05:22:21 PM PDT 24
Peak memory 206104 kb
Host smart-14c0c60a-3c22-4ec4-bb5d-ea41da59843b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37671
44753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3767144753
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2198599300
Short name T315
Test name
Test status
Simulation time 199751443 ps
CPU time 0.83 seconds
Started Jun 23 05:22:16 PM PDT 24
Finished Jun 23 05:22:18 PM PDT 24
Peak memory 206008 kb
Host smart-f8d7af08-83a4-4b2c-a6ca-c56832c1d114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21985
99300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2198599300
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.364590090
Short name T630
Test name
Test status
Simulation time 159200777 ps
CPU time 0.8 seconds
Started Jun 23 05:22:19 PM PDT 24
Finished Jun 23 05:22:20 PM PDT 24
Peak memory 206096 kb
Host smart-8318589a-11ae-4686-b36a-ca4d401a060e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36459
0090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.364590090
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.1815676067
Short name T1259
Test name
Test status
Simulation time 203547726 ps
CPU time 0.92 seconds
Started Jun 23 05:22:21 PM PDT 24
Finished Jun 23 05:22:23 PM PDT 24
Peak memory 206020 kb
Host smart-4ae063ff-e9c1-4c8a-9ea8-7a688775f99c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1815676067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.1815676067
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.561460581
Short name T1559
Test name
Test status
Simulation time 141303771 ps
CPU time 0.81 seconds
Started Jun 23 05:22:19 PM PDT 24
Finished Jun 23 05:22:21 PM PDT 24
Peak memory 206128 kb
Host smart-07291cfe-26f5-473e-a1ce-3bfc133a48d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56146
0581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.561460581
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.283744098
Short name T720
Test name
Test status
Simulation time 65690884 ps
CPU time 0.72 seconds
Started Jun 23 05:22:19 PM PDT 24
Finished Jun 23 05:22:20 PM PDT 24
Peak memory 206152 kb
Host smart-a50aa2d1-1b16-43e0-9632-094b571eb1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28374
4098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.283744098
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2242713760
Short name T174
Test name
Test status
Simulation time 5702308825 ps
CPU time 13.28 seconds
Started Jun 23 05:22:14 PM PDT 24
Finished Jun 23 05:22:28 PM PDT 24
Peak memory 206440 kb
Host smart-160e07a0-7443-499d-800a-1e457e9fd297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22427
13760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2242713760
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2158261078
Short name T496
Test name
Test status
Simulation time 180503069 ps
CPU time 0.82 seconds
Started Jun 23 05:22:20 PM PDT 24
Finished Jun 23 05:22:22 PM PDT 24
Peak memory 206032 kb
Host smart-44323bc6-b873-45ee-bf4d-5af09fd54d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21582
61078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2158261078
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2502734830
Short name T2309
Test name
Test status
Simulation time 182999084 ps
CPU time 0.87 seconds
Started Jun 23 05:22:16 PM PDT 24
Finished Jun 23 05:22:17 PM PDT 24
Peak memory 206100 kb
Host smart-f377df22-fd91-4d2b-928e-2526e5e2c7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25027
34830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2502734830
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.3848355787
Short name T1172
Test name
Test status
Simulation time 167430461 ps
CPU time 0.79 seconds
Started Jun 23 05:22:20 PM PDT 24
Finished Jun 23 05:22:22 PM PDT 24
Peak memory 206260 kb
Host smart-7f4e35a5-f7aa-4078-b67c-0e4df3ac2255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38483
55787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.3848355787
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2622912576
Short name T2156
Test name
Test status
Simulation time 172110774 ps
CPU time 0.81 seconds
Started Jun 23 05:22:14 PM PDT 24
Finished Jun 23 05:22:15 PM PDT 24
Peak memory 206120 kb
Host smart-1670aa49-beee-4b77-bcb7-11a126b99443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26229
12576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2622912576
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3603158090
Short name T755
Test name
Test status
Simulation time 181960768 ps
CPU time 0.79 seconds
Started Jun 23 05:22:18 PM PDT 24
Finished Jun 23 05:22:19 PM PDT 24
Peak memory 205884 kb
Host smart-74bbb7a3-7344-4a54-af6c-40a0fc8e8383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36031
58090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3603158090
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.2556113811
Short name T2333
Test name
Test status
Simulation time 186330915 ps
CPU time 0.94 seconds
Started Jun 23 05:22:20 PM PDT 24
Finished Jun 23 05:22:22 PM PDT 24
Peak memory 206028 kb
Host smart-84dcb61a-3dcf-4fbd-906e-78547d766297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25561
13811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2556113811
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3740302463
Short name T2054
Test name
Test status
Simulation time 204017331 ps
CPU time 0.86 seconds
Started Jun 23 05:22:19 PM PDT 24
Finished Jun 23 05:22:21 PM PDT 24
Peak memory 206104 kb
Host smart-ef818a72-bc98-46a3-a7f8-3e7727190af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37403
02463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3740302463
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.143564805
Short name T815
Test name
Test status
Simulation time 197948438 ps
CPU time 0.9 seconds
Started Jun 23 05:22:11 PM PDT 24
Finished Jun 23 05:22:13 PM PDT 24
Peak memory 206108 kb
Host smart-4d794b07-4a6b-4f75-aa10-fa8de79ddf91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14356
4805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.143564805
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.1335977040
Short name T334
Test name
Test status
Simulation time 3798735432 ps
CPU time 103.92 seconds
Started Jun 23 05:22:16 PM PDT 24
Finished Jun 23 05:24:00 PM PDT 24
Peak memory 206296 kb
Host smart-f5b4c52d-069a-4f4f-88ca-47ba4573d5ee
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1335977040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.1335977040
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3082293738
Short name T536
Test name
Test status
Simulation time 154665186 ps
CPU time 0.83 seconds
Started Jun 23 05:22:18 PM PDT 24
Finished Jun 23 05:22:20 PM PDT 24
Peak memory 206044 kb
Host smart-825235fc-cb58-4a91-80c0-94669db775cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30822
93738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3082293738
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.1570298022
Short name T1282
Test name
Test status
Simulation time 168909450 ps
CPU time 0.81 seconds
Started Jun 23 05:22:17 PM PDT 24
Finished Jun 23 05:22:18 PM PDT 24
Peak memory 206032 kb
Host smart-8662043e-550d-4963-898d-8864a8450e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15702
98022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.1570298022
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.3414225740
Short name T722
Test name
Test status
Simulation time 5076182750 ps
CPU time 37.74 seconds
Started Jun 23 05:22:19 PM PDT 24
Finished Jun 23 05:22:57 PM PDT 24
Peak memory 206340 kb
Host smart-635775fb-6166-4ed0-be29-8788f06c0ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34142
25740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.3414225740
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3749362462
Short name T1682
Test name
Test status
Simulation time 4259528678 ps
CPU time 5.72 seconds
Started Jun 23 05:22:20 PM PDT 24
Finished Jun 23 05:22:27 PM PDT 24
Peak memory 206188 kb
Host smart-647c0d5f-d706-4c9d-9537-6c7dbb56ca7b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3749362462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.3749362462
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.2451257394
Short name T2279
Test name
Test status
Simulation time 13343713416 ps
CPU time 14.39 seconds
Started Jun 23 05:22:22 PM PDT 24
Finished Jun 23 05:22:38 PM PDT 24
Peak memory 206168 kb
Host smart-277fe33f-a5c2-4ef6-b1a5-e37c4855f0b2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2451257394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.2451257394
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.3004065360
Short name T12
Test name
Test status
Simulation time 23498954602 ps
CPU time 21.98 seconds
Started Jun 23 05:22:22 PM PDT 24
Finished Jun 23 05:22:45 PM PDT 24
Peak memory 206408 kb
Host smart-4e4933b8-be75-4c8c-9c85-318f0a9821e1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3004065360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.3004065360
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.793664427
Short name T1318
Test name
Test status
Simulation time 180527815 ps
CPU time 0.87 seconds
Started Jun 23 05:22:22 PM PDT 24
Finished Jun 23 05:22:24 PM PDT 24
Peak memory 206104 kb
Host smart-4669b097-bd31-42c1-a1f0-d738bbc12e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79366
4427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.793664427
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.3918614751
Short name T895
Test name
Test status
Simulation time 142154097 ps
CPU time 0.81 seconds
Started Jun 23 05:22:19 PM PDT 24
Finished Jun 23 05:22:21 PM PDT 24
Peak memory 206096 kb
Host smart-5ca8003f-c177-46bf-8b6c-a64d7c94cc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39186
14751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.3918614751
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.3960639822
Short name T61
Test name
Test status
Simulation time 470374838 ps
CPU time 1.32 seconds
Started Jun 23 05:22:20 PM PDT 24
Finished Jun 23 05:22:23 PM PDT 24
Peak memory 206104 kb
Host smart-e79c38a1-490a-4cb8-834e-7c93b1092c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39606
39822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.3960639822
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1210117716
Short name T1624
Test name
Test status
Simulation time 669906538 ps
CPU time 1.68 seconds
Started Jun 23 05:22:23 PM PDT 24
Finished Jun 23 05:22:26 PM PDT 24
Peak memory 205944 kb
Host smart-1fe08ff2-3c94-45d2-a561-4006f864afbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12101
17716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1210117716
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.1844140604
Short name T1911
Test name
Test status
Simulation time 18559022327 ps
CPU time 35.9 seconds
Started Jun 23 05:22:18 PM PDT 24
Finished Jun 23 05:22:55 PM PDT 24
Peak memory 206292 kb
Host smart-158ae349-3dad-4bce-8af5-ce9e7acd424f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18441
40604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1844140604
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2925127324
Short name T1804
Test name
Test status
Simulation time 396945773 ps
CPU time 1.27 seconds
Started Jun 23 05:22:21 PM PDT 24
Finished Jun 23 05:22:24 PM PDT 24
Peak memory 206100 kb
Host smart-e6a0b6df-a0a0-4c22-8b31-d15f4ba33098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29251
27324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2925127324
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3027557698
Short name T511
Test name
Test status
Simulation time 139204082 ps
CPU time 0.79 seconds
Started Jun 23 05:22:22 PM PDT 24
Finished Jun 23 05:22:24 PM PDT 24
Peak memory 206100 kb
Host smart-76205831-4675-4a40-afd2-eade1dc03403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30275
57698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3027557698
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.2248111477
Short name T375
Test name
Test status
Simulation time 28997908 ps
CPU time 0.65 seconds
Started Jun 23 05:22:19 PM PDT 24
Finished Jun 23 05:22:21 PM PDT 24
Peak memory 206048 kb
Host smart-abd582a8-a73f-45ca-a395-68dadc0b2598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22481
11477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2248111477
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.2147780382
Short name T619
Test name
Test status
Simulation time 875213136 ps
CPU time 2.1 seconds
Started Jun 23 05:22:22 PM PDT 24
Finished Jun 23 05:22:25 PM PDT 24
Peak memory 206336 kb
Host smart-0be60a29-b88c-44ff-8b11-2218194b3fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21477
80382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2147780382
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1593205057
Short name T182
Test name
Test status
Simulation time 164414333 ps
CPU time 1.16 seconds
Started Jun 23 05:22:21 PM PDT 24
Finished Jun 23 05:22:23 PM PDT 24
Peak memory 206236 kb
Host smart-a572e0a3-a872-49f5-83f1-4adef1237b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15932
05057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1593205057
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.4003951494
Short name T1125
Test name
Test status
Simulation time 202889571 ps
CPU time 0.88 seconds
Started Jun 23 05:22:25 PM PDT 24
Finished Jun 23 05:22:26 PM PDT 24
Peak memory 206092 kb
Host smart-8387fbd6-6935-40c6-9bab-0ff8c23b0342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40039
51494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.4003951494
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3807010107
Short name T2230
Test name
Test status
Simulation time 150666537 ps
CPU time 0.83 seconds
Started Jun 23 05:22:26 PM PDT 24
Finished Jun 23 05:22:28 PM PDT 24
Peak memory 206096 kb
Host smart-8209153e-46ab-4d83-9ce7-546aadc6d23b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38070
10107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3807010107
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.847671767
Short name T2437
Test name
Test status
Simulation time 232068746 ps
CPU time 0.88 seconds
Started Jun 23 05:22:20 PM PDT 24
Finished Jun 23 05:22:22 PM PDT 24
Peak memory 206104 kb
Host smart-0460f934-4957-4817-8493-bdd45a33a8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84767
1767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.847671767
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1230312014
Short name T488
Test name
Test status
Simulation time 194660710 ps
CPU time 0.85 seconds
Started Jun 23 05:22:19 PM PDT 24
Finished Jun 23 05:22:21 PM PDT 24
Peak memory 206028 kb
Host smart-7ff649f3-1c8a-4122-b16c-4c3de7698467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12303
12014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1230312014
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.943676353
Short name T1444
Test name
Test status
Simulation time 23348905829 ps
CPU time 20.69 seconds
Started Jun 23 05:22:19 PM PDT 24
Finished Jun 23 05:22:41 PM PDT 24
Peak memory 206156 kb
Host smart-fbc728ce-c22c-4293-8926-69446f5be33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94367
6353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.943676353
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.1626711601
Short name T1443
Test name
Test status
Simulation time 3343041637 ps
CPU time 4.17 seconds
Started Jun 23 05:22:22 PM PDT 24
Finished Jun 23 05:22:28 PM PDT 24
Peak memory 206164 kb
Host smart-c844d6ef-fba7-4138-ab28-06d67862997e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16267
11601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.1626711601
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.4101451989
Short name T2488
Test name
Test status
Simulation time 8891657837 ps
CPU time 245.99 seconds
Started Jun 23 05:22:21 PM PDT 24
Finished Jun 23 05:26:28 PM PDT 24
Peak memory 206352 kb
Host smart-65890e2e-ee2e-4d19-a492-a56c386cac8c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4101451989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.4101451989
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.1393927322
Short name T1892
Test name
Test status
Simulation time 267491259 ps
CPU time 0.95 seconds
Started Jun 23 05:22:26 PM PDT 24
Finished Jun 23 05:22:27 PM PDT 24
Peak memory 205812 kb
Host smart-3f09d510-e117-4cde-9ddf-8e7e28087701
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1393927322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.1393927322
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1606608157
Short name T617
Test name
Test status
Simulation time 214890571 ps
CPU time 0.85 seconds
Started Jun 23 05:22:19 PM PDT 24
Finished Jun 23 05:22:20 PM PDT 24
Peak memory 206108 kb
Host smart-4db8a447-f61f-4258-97b1-74fc2951d35b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16066
08157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1606608157
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3121056148
Short name T802
Test name
Test status
Simulation time 12809668775 ps
CPU time 113.36 seconds
Started Jun 23 05:22:22 PM PDT 24
Finished Jun 23 05:24:17 PM PDT 24
Peak memory 206328 kb
Host smart-228ac8e8-f5bd-4966-b3db-0e7f6185acac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31210
56148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3121056148
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.3155301379
Short name T493
Test name
Test status
Simulation time 5585873102 ps
CPU time 40.97 seconds
Started Jun 23 05:22:19 PM PDT 24
Finished Jun 23 05:23:02 PM PDT 24
Peak memory 206380 kb
Host smart-e752e35e-2a6e-4ba4-b12f-7b2817c14f52
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3155301379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.3155301379
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.1342073391
Short name T884
Test name
Test status
Simulation time 164921554 ps
CPU time 0.84 seconds
Started Jun 23 05:22:24 PM PDT 24
Finished Jun 23 05:22:26 PM PDT 24
Peak memory 206128 kb
Host smart-8492e67d-7f7b-4a22-9069-4430a7b1f2d3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1342073391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.1342073391
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2858650267
Short name T2208
Test name
Test status
Simulation time 164342701 ps
CPU time 0.84 seconds
Started Jun 23 05:22:19 PM PDT 24
Finished Jun 23 05:22:21 PM PDT 24
Peak memory 206112 kb
Host smart-68e43dbe-b13f-4dcf-b0a0-1009dd758f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28586
50267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2858650267
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2212531028
Short name T2055
Test name
Test status
Simulation time 282063963 ps
CPU time 0.92 seconds
Started Jun 23 05:22:20 PM PDT 24
Finished Jun 23 05:22:22 PM PDT 24
Peak memory 206096 kb
Host smart-3705aa3e-b6d4-4002-b5f3-81be2a4fdf32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22125
31028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2212531028
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2714750165
Short name T1874
Test name
Test status
Simulation time 253858601 ps
CPU time 0.98 seconds
Started Jun 23 05:22:21 PM PDT 24
Finished Jun 23 05:22:23 PM PDT 24
Peak memory 206036 kb
Host smart-f6040617-8c3d-4da6-bb56-55ca082d2899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27147
50165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2714750165
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.1907124253
Short name T1335
Test name
Test status
Simulation time 145161431 ps
CPU time 0.75 seconds
Started Jun 23 05:22:24 PM PDT 24
Finished Jun 23 05:22:25 PM PDT 24
Peak memory 206096 kb
Host smart-9b678eb5-2904-4620-a435-681b7efe7176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19071
24253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1907124253
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1320761214
Short name T2444
Test name
Test status
Simulation time 148305914 ps
CPU time 0.78 seconds
Started Jun 23 05:22:26 PM PDT 24
Finished Jun 23 05:22:27 PM PDT 24
Peak memory 206124 kb
Host smart-87bbb15a-4202-42d3-8dd7-290340d94307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13207
61214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1320761214
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3800241237
Short name T2042
Test name
Test status
Simulation time 147667530 ps
CPU time 0.77 seconds
Started Jun 23 05:22:24 PM PDT 24
Finished Jun 23 05:22:26 PM PDT 24
Peak memory 206112 kb
Host smart-6aaf4579-29a9-4d8f-ad8b-fd506797f749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38002
41237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3800241237
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.3535878347
Short name T51
Test name
Test status
Simulation time 241756538 ps
CPU time 1 seconds
Started Jun 23 05:22:25 PM PDT 24
Finished Jun 23 05:22:27 PM PDT 24
Peak memory 206048 kb
Host smart-e347fbb8-74ba-45b9-b173-85273d43a5ea
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3535878347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.3535878347
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3438926735
Short name T1046
Test name
Test status
Simulation time 206487431 ps
CPU time 0.86 seconds
Started Jun 23 05:22:28 PM PDT 24
Finished Jun 23 05:22:29 PM PDT 24
Peak memory 206108 kb
Host smart-b10b3dbe-1562-4e7d-808e-550e49acd6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34389
26735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3438926735
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2248565274
Short name T2188
Test name
Test status
Simulation time 46939391 ps
CPU time 0.64 seconds
Started Jun 23 05:22:21 PM PDT 24
Finished Jun 23 05:22:22 PM PDT 24
Peak memory 205864 kb
Host smart-041e3fee-5a49-4065-b39f-4d867c85b907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22485
65274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2248565274
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1517496602
Short name T1135
Test name
Test status
Simulation time 19233293481 ps
CPU time 40.49 seconds
Started Jun 23 05:22:23 PM PDT 24
Finished Jun 23 05:23:05 PM PDT 24
Peak memory 206396 kb
Host smart-30d921ba-66bb-446d-b60f-fc957d3521a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15174
96602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1517496602
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.865064272
Short name T262
Test name
Test status
Simulation time 148578698 ps
CPU time 0.79 seconds
Started Jun 23 05:22:23 PM PDT 24
Finished Jun 23 05:22:25 PM PDT 24
Peak memory 206028 kb
Host smart-dc493755-6281-49fd-84d4-d07a0074eb01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86506
4272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.865064272
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.850207355
Short name T1883
Test name
Test status
Simulation time 174249748 ps
CPU time 0.88 seconds
Started Jun 23 05:22:25 PM PDT 24
Finished Jun 23 05:22:26 PM PDT 24
Peak memory 206016 kb
Host smart-bb324569-eb1a-4673-beda-0c3c06199210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85020
7355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.850207355
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.3414283352
Short name T1782
Test name
Test status
Simulation time 193396769 ps
CPU time 0.91 seconds
Started Jun 23 05:22:26 PM PDT 24
Finished Jun 23 05:22:27 PM PDT 24
Peak memory 206012 kb
Host smart-c43d2779-4e2f-4e8c-ae06-0e7a50088031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34142
83352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.3414283352
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.1907345732
Short name T533
Test name
Test status
Simulation time 173041880 ps
CPU time 0.87 seconds
Started Jun 23 05:22:25 PM PDT 24
Finished Jun 23 05:22:26 PM PDT 24
Peak memory 206260 kb
Host smart-6cbc6385-3340-4738-8648-af64cb0766c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19073
45732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.1907345732
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.3408774445
Short name T1076
Test name
Test status
Simulation time 145792485 ps
CPU time 0.77 seconds
Started Jun 23 05:22:24 PM PDT 24
Finished Jun 23 05:22:26 PM PDT 24
Peak memory 206100 kb
Host smart-d4f21029-a75c-4757-824a-ad9f3606d2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34087
74445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.3408774445
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.290103989
Short name T1820
Test name
Test status
Simulation time 151309942 ps
CPU time 0.84 seconds
Started Jun 23 05:22:27 PM PDT 24
Finished Jun 23 05:22:28 PM PDT 24
Peak memory 205996 kb
Host smart-b1f28edc-e910-41d2-b25b-549d5bc1643b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29010
3989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.290103989
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.955445280
Short name T1137
Test name
Test status
Simulation time 157581309 ps
CPU time 0.76 seconds
Started Jun 23 05:22:24 PM PDT 24
Finished Jun 23 05:22:25 PM PDT 24
Peak memory 206120 kb
Host smart-dc9edd64-295b-4a06-a0f5-5dc2e72fbbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95544
5280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.955445280
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1745245555
Short name T401
Test name
Test status
Simulation time 218884915 ps
CPU time 0.87 seconds
Started Jun 23 05:22:22 PM PDT 24
Finished Jun 23 05:22:25 PM PDT 24
Peak memory 206108 kb
Host smart-3b06c15c-4354-4088-9b19-562c9c19b70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17452
45555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1745245555
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.3301153741
Short name T2294
Test name
Test status
Simulation time 9023153380 ps
CPU time 85.28 seconds
Started Jun 23 05:22:24 PM PDT 24
Finished Jun 23 05:23:50 PM PDT 24
Peak memory 206340 kb
Host smart-4f3ae7ae-fa76-427f-ad66-914a3a1c5f34
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3301153741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.3301153741
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1335832650
Short name T1355
Test name
Test status
Simulation time 201373676 ps
CPU time 0.85 seconds
Started Jun 23 05:22:24 PM PDT 24
Finished Jun 23 05:22:26 PM PDT 24
Peak memory 206112 kb
Host smart-6de0380c-65fe-42a9-820e-4f3b97a68e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13358
32650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1335832650
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2113246196
Short name T2398
Test name
Test status
Simulation time 188816739 ps
CPU time 0.86 seconds
Started Jun 23 05:22:22 PM PDT 24
Finished Jun 23 05:22:25 PM PDT 24
Peak memory 206036 kb
Host smart-5d51aaed-4f39-4a16-bb18-0f0005ed375a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21132
46196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2113246196
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.1156227440
Short name T537
Test name
Test status
Simulation time 11197821288 ps
CPU time 107.44 seconds
Started Jun 23 05:22:25 PM PDT 24
Finished Jun 23 05:24:13 PM PDT 24
Peak memory 205988 kb
Host smart-afdcf24d-3e21-48d9-9dce-159a3e2ca55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11562
27440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.1156227440
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.4200315567
Short name T1521
Test name
Test status
Simulation time 3554960641 ps
CPU time 4.22 seconds
Started Jun 23 05:22:33 PM PDT 24
Finished Jun 23 05:22:38 PM PDT 24
Peak memory 206188 kb
Host smart-21c11ad3-666f-473f-8b39-062a491ca82f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4200315567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.4200315567
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.2069732465
Short name T205
Test name
Test status
Simulation time 13386462077 ps
CPU time 14.98 seconds
Started Jun 23 05:22:30 PM PDT 24
Finished Jun 23 05:22:45 PM PDT 24
Peak memory 206148 kb
Host smart-cf2c47e8-31b3-4c94-9580-b4b4cea66cac
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2069732465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.2069732465
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.2720206486
Short name T538
Test name
Test status
Simulation time 23373296633 ps
CPU time 22.19 seconds
Started Jun 23 05:22:31 PM PDT 24
Finished Jun 23 05:22:53 PM PDT 24
Peak memory 206160 kb
Host smart-b2d3a205-3cf1-43ce-a3ab-87e44b564705
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2720206486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.2720206486
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3303131302
Short name T2075
Test name
Test status
Simulation time 186705387 ps
CPU time 0.83 seconds
Started Jun 23 05:22:32 PM PDT 24
Finished Jun 23 05:22:34 PM PDT 24
Peak memory 206108 kb
Host smart-b8035e7e-3e75-4170-b37a-0af1bde7c7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33031
31302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3303131302
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.1021644568
Short name T2292
Test name
Test status
Simulation time 191203422 ps
CPU time 0.89 seconds
Started Jun 23 05:22:29 PM PDT 24
Finished Jun 23 05:22:30 PM PDT 24
Peak memory 206060 kb
Host smart-ea3cc79f-e7ff-4f77-aef2-aa4e8f993c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10216
44568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.1021644568
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.678788264
Short name T774
Test name
Test status
Simulation time 303964823 ps
CPU time 1.06 seconds
Started Jun 23 05:22:30 PM PDT 24
Finished Jun 23 05:22:32 PM PDT 24
Peak memory 206100 kb
Host smart-69213a09-069d-42e3-b59c-37f664215195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67878
8264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.678788264
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1160412033
Short name T1511
Test name
Test status
Simulation time 597427342 ps
CPU time 1.67 seconds
Started Jun 23 05:22:32 PM PDT 24
Finished Jun 23 05:22:34 PM PDT 24
Peak memory 206100 kb
Host smart-988e0cf8-b70a-4121-8529-9f7557cc6a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11604
12033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1160412033
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.113224795
Short name T1885
Test name
Test status
Simulation time 19402168486 ps
CPU time 35.47 seconds
Started Jun 23 05:22:32 PM PDT 24
Finished Jun 23 05:23:08 PM PDT 24
Peak memory 206392 kb
Host smart-de4d03b6-4fd3-4290-96c3-a5a3ea54f534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11322
4795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.113224795
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.199166228
Short name T584
Test name
Test status
Simulation time 439150766 ps
CPU time 1.43 seconds
Started Jun 23 05:22:31 PM PDT 24
Finished Jun 23 05:22:33 PM PDT 24
Peak memory 206040 kb
Host smart-5998baf8-7537-4f25-84a9-d792da9ef5a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19916
6228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.199166228
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.1247066271
Short name T704
Test name
Test status
Simulation time 207754359 ps
CPU time 0.83 seconds
Started Jun 23 05:22:30 PM PDT 24
Finished Jun 23 05:22:31 PM PDT 24
Peak memory 206072 kb
Host smart-6cb7c13a-d3c0-4782-9094-34f8030a252c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12470
66271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.1247066271
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2178916058
Short name T2374
Test name
Test status
Simulation time 81413711 ps
CPU time 0.7 seconds
Started Jun 23 05:22:31 PM PDT 24
Finished Jun 23 05:22:32 PM PDT 24
Peak memory 206012 kb
Host smart-00841e1a-3ba4-434c-8b41-4a1ad0e2317e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21789
16058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2178916058
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.4270923910
Short name T806
Test name
Test status
Simulation time 827385551 ps
CPU time 2.01 seconds
Started Jun 23 05:22:32 PM PDT 24
Finished Jun 23 05:22:35 PM PDT 24
Peak memory 206336 kb
Host smart-54286fc6-f2ac-4546-afbb-8dd9afe77a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42709
23910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.4270923910
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.396589731
Short name T1138
Test name
Test status
Simulation time 175478299 ps
CPU time 1.33 seconds
Started Jun 23 05:22:31 PM PDT 24
Finished Jun 23 05:22:32 PM PDT 24
Peak memory 206292 kb
Host smart-cf84bac4-09bb-4e90-9894-eef288f3e6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39658
9731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.396589731
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.526206908
Short name T2202
Test name
Test status
Simulation time 166341642 ps
CPU time 0.82 seconds
Started Jun 23 05:22:42 PM PDT 24
Finished Jun 23 05:22:43 PM PDT 24
Peak memory 206104 kb
Host smart-bb937d64-765a-4d44-a397-d3d541234cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52620
6908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.526206908
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2919771479
Short name T1938
Test name
Test status
Simulation time 147666194 ps
CPU time 0.75 seconds
Started Jun 23 05:22:34 PM PDT 24
Finished Jun 23 05:22:35 PM PDT 24
Peak memory 206096 kb
Host smart-0cb9aa34-b67b-4064-bae6-610c29549dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29197
71479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2919771479
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3900139810
Short name T1931
Test name
Test status
Simulation time 220238801 ps
CPU time 0.87 seconds
Started Jun 23 05:22:32 PM PDT 24
Finished Jun 23 05:22:33 PM PDT 24
Peak memory 206028 kb
Host smart-eb43dd49-4a50-41ff-b4dd-50cba241c8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39001
39810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3900139810
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.15501473
Short name T93
Test name
Test status
Simulation time 6166668992 ps
CPU time 175.45 seconds
Started Jun 23 05:22:30 PM PDT 24
Finished Jun 23 05:25:26 PM PDT 24
Peak memory 206336 kb
Host smart-c63a373e-3c4b-44cf-a692-085845a6bd1e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=15501473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.15501473
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.3894157591
Short name T2500
Test name
Test status
Simulation time 248555285 ps
CPU time 1.02 seconds
Started Jun 23 05:22:28 PM PDT 24
Finished Jun 23 05:22:30 PM PDT 24
Peak memory 206092 kb
Host smart-8507ef50-36d0-421f-96c0-771005bb520b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38941
57591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.3894157591
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.3176977711
Short name T2127
Test name
Test status
Simulation time 23292713427 ps
CPU time 23.31 seconds
Started Jun 23 05:22:31 PM PDT 24
Finished Jun 23 05:22:54 PM PDT 24
Peak memory 206156 kb
Host smart-f5cc0fb1-6232-4d32-b07b-b3c113d71c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31769
77711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.3176977711
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3058034446
Short name T1512
Test name
Test status
Simulation time 3338748057 ps
CPU time 3.81 seconds
Started Jun 23 05:22:30 PM PDT 24
Finished Jun 23 05:22:34 PM PDT 24
Peak memory 206156 kb
Host smart-7a4b392a-cb23-4629-986b-f2c142fbb5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30580
34446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3058034446
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.398037549
Short name T413
Test name
Test status
Simulation time 13886640403 ps
CPU time 97 seconds
Started Jun 23 05:22:30 PM PDT 24
Finished Jun 23 05:24:07 PM PDT 24
Peak memory 206372 kb
Host smart-6998b8b5-d56d-4b1c-ae37-93f3a7a6f068
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=398037549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.398037549
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.635667923
Short name T2278
Test name
Test status
Simulation time 249774641 ps
CPU time 0.99 seconds
Started Jun 23 05:22:34 PM PDT 24
Finished Jun 23 05:22:36 PM PDT 24
Peak memory 206064 kb
Host smart-81c9a680-7714-4f7e-b55f-ab1ae1807765
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=635667923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.635667923
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.2908856503
Short name T2419
Test name
Test status
Simulation time 241138801 ps
CPU time 0.91 seconds
Started Jun 23 05:22:29 PM PDT 24
Finished Jun 23 05:22:30 PM PDT 24
Peak memory 206036 kb
Host smart-f64a2450-f2e5-4344-8042-dc19ab9b8264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29088
56503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.2908856503
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.3713819173
Short name T1728
Test name
Test status
Simulation time 5099947483 ps
CPU time 47.57 seconds
Started Jun 23 05:22:31 PM PDT 24
Finished Jun 23 05:23:19 PM PDT 24
Peak memory 206356 kb
Host smart-f603415d-cf94-4d14-b217-553689c59e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37138
19173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.3713819173
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.2016700742
Short name T1686
Test name
Test status
Simulation time 4000814043 ps
CPU time 28.77 seconds
Started Jun 23 05:22:30 PM PDT 24
Finished Jun 23 05:22:59 PM PDT 24
Peak memory 206240 kb
Host smart-1d777634-24ed-4de7-b1f7-26eb0227ba82
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2016700742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.2016700742
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.773216272
Short name T379
Test name
Test status
Simulation time 155266405 ps
CPU time 0.83 seconds
Started Jun 23 05:22:36 PM PDT 24
Finished Jun 23 05:22:37 PM PDT 24
Peak memory 206120 kb
Host smart-07ba2f04-ba35-4443-80fc-f17bb24fe319
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=773216272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.773216272
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2424221978
Short name T1677
Test name
Test status
Simulation time 171426561 ps
CPU time 0.77 seconds
Started Jun 23 05:22:30 PM PDT 24
Finished Jun 23 05:22:31 PM PDT 24
Peak memory 206004 kb
Host smart-49e77298-6fd3-4670-be66-a40cb8fed5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24242
21978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2424221978
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3045121959
Short name T133
Test name
Test status
Simulation time 175886592 ps
CPU time 0.81 seconds
Started Jun 23 05:22:34 PM PDT 24
Finished Jun 23 05:22:36 PM PDT 24
Peak memory 206104 kb
Host smart-54a6961b-46ae-420f-be2e-e779d9c0bf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30451
21959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3045121959
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.844701114
Short name T1673
Test name
Test status
Simulation time 181262661 ps
CPU time 0.86 seconds
Started Jun 23 05:22:36 PM PDT 24
Finished Jun 23 05:22:38 PM PDT 24
Peak memory 206108 kb
Host smart-74f62888-7aaf-4a48-b829-7bdaadda56eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84470
1114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.844701114
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2341925299
Short name T2177
Test name
Test status
Simulation time 154961616 ps
CPU time 0.77 seconds
Started Jun 23 05:22:33 PM PDT 24
Finished Jun 23 05:22:35 PM PDT 24
Peak memory 206036 kb
Host smart-ef9def88-5801-4b30-8e13-de4138f6261f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23419
25299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2341925299
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.17104047
Short name T1490
Test name
Test status
Simulation time 187934203 ps
CPU time 0.83 seconds
Started Jun 23 05:22:33 PM PDT 24
Finished Jun 23 05:22:34 PM PDT 24
Peak memory 206052 kb
Host smart-6bbf302c-ecad-4848-a02c-ba6ef463645c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17104
047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.17104047
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.972493668
Short name T1235
Test name
Test status
Simulation time 150545906 ps
CPU time 0.82 seconds
Started Jun 23 05:22:37 PM PDT 24
Finished Jun 23 05:22:38 PM PDT 24
Peak memory 206020 kb
Host smart-68954414-e47b-4f26-9f1d-7f783a06a045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97249
3668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.972493668
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.2773243805
Short name T713
Test name
Test status
Simulation time 257462948 ps
CPU time 1.02 seconds
Started Jun 23 05:22:37 PM PDT 24
Finished Jun 23 05:22:38 PM PDT 24
Peak memory 206052 kb
Host smart-9dd4f06d-37c4-4e09-a297-a2e8f624bf6d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2773243805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.2773243805
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.4016195485
Short name T482
Test name
Test status
Simulation time 197925922 ps
CPU time 0.9 seconds
Started Jun 23 05:22:36 PM PDT 24
Finished Jun 23 05:22:37 PM PDT 24
Peak memory 206112 kb
Host smart-d27d768f-45ab-4f79-849f-e23ed624b00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40161
95485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.4016195485
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.4148077728
Short name T1729
Test name
Test status
Simulation time 57205541 ps
CPU time 0.69 seconds
Started Jun 23 05:22:37 PM PDT 24
Finished Jun 23 05:22:38 PM PDT 24
Peak memory 206068 kb
Host smart-2b39d374-8b09-425b-8670-edde704282ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41480
77728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.4148077728
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1796151026
Short name T1558
Test name
Test status
Simulation time 6591974882 ps
CPU time 15.31 seconds
Started Jun 23 05:22:35 PM PDT 24
Finished Jun 23 05:22:50 PM PDT 24
Peak memory 206480 kb
Host smart-fdd11453-903b-46f0-ab69-36cf3fe8b218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17961
51026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1796151026
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1603545426
Short name T661
Test name
Test status
Simulation time 172105759 ps
CPU time 0.85 seconds
Started Jun 23 05:22:35 PM PDT 24
Finished Jun 23 05:22:36 PM PDT 24
Peak memory 206076 kb
Host smart-ed841c4a-ec53-42ef-ad42-19966f4cc36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16035
45426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1603545426
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3390575944
Short name T1805
Test name
Test status
Simulation time 175508735 ps
CPU time 0.81 seconds
Started Jun 23 05:22:35 PM PDT 24
Finished Jun 23 05:22:36 PM PDT 24
Peak memory 206104 kb
Host smart-b01b2c14-5120-4a19-bc93-df1639aed7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33905
75944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3390575944
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.1645291497
Short name T481
Test name
Test status
Simulation time 221020082 ps
CPU time 0.87 seconds
Started Jun 23 05:22:36 PM PDT 24
Finished Jun 23 05:22:38 PM PDT 24
Peak memory 206124 kb
Host smart-a65e5240-ac0d-4bf4-b247-0fe206356bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16452
91497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.1645291497
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.389815117
Short name T349
Test name
Test status
Simulation time 186475668 ps
CPU time 0.84 seconds
Started Jun 23 05:22:35 PM PDT 24
Finished Jun 23 05:22:37 PM PDT 24
Peak memory 206036 kb
Host smart-b9d31813-ee84-4256-8abf-9d65a19ab057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38981
5117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.389815117
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.3681247380
Short name T680
Test name
Test status
Simulation time 159283056 ps
CPU time 0.79 seconds
Started Jun 23 05:22:35 PM PDT 24
Finished Jun 23 05:22:36 PM PDT 24
Peak memory 206100 kb
Host smart-a03e5709-b6f6-4d42-8f6d-03adc2c33d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36812
47380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.3681247380
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3990925882
Short name T1580
Test name
Test status
Simulation time 161606967 ps
CPU time 0.78 seconds
Started Jun 23 05:22:37 PM PDT 24
Finished Jun 23 05:22:38 PM PDT 24
Peak memory 206100 kb
Host smart-f3568834-3110-4ef2-a8ba-5d3fd9c826d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39909
25882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3990925882
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2523865508
Short name T1163
Test name
Test status
Simulation time 184097237 ps
CPU time 0.81 seconds
Started Jun 23 05:22:33 PM PDT 24
Finished Jun 23 05:22:35 PM PDT 24
Peak memory 206040 kb
Host smart-d8ea2419-b89e-439e-944c-0fc86febb167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25238
65508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2523865508
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2106684808
Short name T1150
Test name
Test status
Simulation time 230919517 ps
CPU time 0.98 seconds
Started Jun 23 05:22:32 PM PDT 24
Finished Jun 23 05:22:33 PM PDT 24
Peak memory 206124 kb
Host smart-a0f7fb92-67c0-4035-a69a-401f56942ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21066
84808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2106684808
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.4247770727
Short name T697
Test name
Test status
Simulation time 5105435631 ps
CPU time 149.58 seconds
Started Jun 23 05:22:38 PM PDT 24
Finished Jun 23 05:25:08 PM PDT 24
Peak memory 206260 kb
Host smart-d5c0d541-a12b-44e3-ada1-fb0b76521feb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4247770727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.4247770727
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.96163252
Short name T2157
Test name
Test status
Simulation time 198693696 ps
CPU time 0.79 seconds
Started Jun 23 05:22:37 PM PDT 24
Finished Jun 23 05:22:38 PM PDT 24
Peak memory 206092 kb
Host smart-1be9370c-470b-488f-94d2-36b04ddea2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96163
252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.96163252
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.719264944
Short name T1610
Test name
Test status
Simulation time 191447950 ps
CPU time 0.83 seconds
Started Jun 23 05:22:33 PM PDT 24
Finished Jun 23 05:22:35 PM PDT 24
Peak memory 205988 kb
Host smart-4a602252-9393-409b-a955-9cc9d3ee8421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71926
4944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.719264944
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1425043503
Short name T1410
Test name
Test status
Simulation time 2895034686 ps
CPU time 82.28 seconds
Started Jun 23 05:22:42 PM PDT 24
Finished Jun 23 05:24:05 PM PDT 24
Peak memory 206328 kb
Host smart-1b726c82-d4e9-4d9b-97b8-8c71e498715b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14250
43503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1425043503
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.795363958
Short name T1165
Test name
Test status
Simulation time 3713494499 ps
CPU time 4.22 seconds
Started Jun 23 05:22:35 PM PDT 24
Finished Jun 23 05:22:40 PM PDT 24
Peak memory 206188 kb
Host smart-18151539-b322-4bf2-8328-6ab0fbc6e128
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=795363958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.795363958
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.3142382359
Short name T2335
Test name
Test status
Simulation time 13329486524 ps
CPU time 12.83 seconds
Started Jun 23 05:22:37 PM PDT 24
Finished Jun 23 05:22:50 PM PDT 24
Peak memory 206092 kb
Host smart-535012e7-f3e1-464a-8bd5-e89e411a5a80
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3142382359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.3142382359
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.2058545024
Short name T192
Test name
Test status
Simulation time 23363737866 ps
CPU time 23.55 seconds
Started Jun 23 05:22:41 PM PDT 24
Finished Jun 23 05:23:05 PM PDT 24
Peak memory 206368 kb
Host smart-765c0ec7-6ad4-4039-a3c0-2d88128115e5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2058545024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.2058545024
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3584661251
Short name T344
Test name
Test status
Simulation time 154992975 ps
CPU time 0.82 seconds
Started Jun 23 05:22:41 PM PDT 24
Finished Jun 23 05:22:43 PM PDT 24
Peak memory 206108 kb
Host smart-b2898f64-7065-40ac-a06b-c63730bbc9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35846
61251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3584661251
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.3377615666
Short name T1548
Test name
Test status
Simulation time 162380274 ps
CPU time 0.76 seconds
Started Jun 23 05:22:35 PM PDT 24
Finished Jun 23 05:22:37 PM PDT 24
Peak memory 206080 kb
Host smart-a967a9fd-8380-45dd-8a24-37899705695f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33776
15666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.3377615666
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.2506944951
Short name T1374
Test name
Test status
Simulation time 191048939 ps
CPU time 0.9 seconds
Started Jun 23 05:22:41 PM PDT 24
Finished Jun 23 05:22:42 PM PDT 24
Peak memory 206120 kb
Host smart-a1cf3ee8-72ad-41d5-a95b-9b4537e4f883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25069
44951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.2506944951
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.3788804493
Short name T1993
Test name
Test status
Simulation time 1053768214 ps
CPU time 2.51 seconds
Started Jun 23 05:22:38 PM PDT 24
Finished Jun 23 05:22:41 PM PDT 24
Peak memory 206228 kb
Host smart-75b02613-2ba7-4190-800d-8472fa6173eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37888
04493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3788804493
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.88700221
Short name T1691
Test name
Test status
Simulation time 13384156317 ps
CPU time 28.21 seconds
Started Jun 23 05:22:44 PM PDT 24
Finished Jun 23 05:23:12 PM PDT 24
Peak memory 206416 kb
Host smart-81f2b54a-3839-4a4d-aee0-a842e9811e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88700
221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.88700221
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.3954209038
Short name T1223
Test name
Test status
Simulation time 403236455 ps
CPU time 1.34 seconds
Started Jun 23 05:22:42 PM PDT 24
Finished Jun 23 05:22:43 PM PDT 24
Peak memory 206108 kb
Host smart-1e857134-17e4-446f-b8ac-3c2f0d73fe0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39542
09038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3954209038
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.1989010545
Short name T377
Test name
Test status
Simulation time 131072871 ps
CPU time 0.75 seconds
Started Jun 23 05:22:34 PM PDT 24
Finished Jun 23 05:22:36 PM PDT 24
Peak memory 206108 kb
Host smart-1afd8c66-0790-4dbd-b650-58694b544f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19890
10545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.1989010545
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2024472161
Short name T1031
Test name
Test status
Simulation time 50963097 ps
CPU time 0.67 seconds
Started Jun 23 05:22:38 PM PDT 24
Finished Jun 23 05:22:39 PM PDT 24
Peak memory 206092 kb
Host smart-ca712c66-7a10-4586-b010-2f1316461f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20244
72161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2024472161
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.566868375
Short name T915
Test name
Test status
Simulation time 829824945 ps
CPU time 2 seconds
Started Jun 23 05:22:44 PM PDT 24
Finished Jun 23 05:22:46 PM PDT 24
Peak memory 206372 kb
Host smart-ce5f88ee-d8a5-4407-b69a-3baf9b4e20d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56686
8375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.566868375
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2011110170
Short name T592
Test name
Test status
Simulation time 282197714 ps
CPU time 2.09 seconds
Started Jun 23 05:22:42 PM PDT 24
Finished Jun 23 05:22:44 PM PDT 24
Peak memory 206260 kb
Host smart-717a71f3-9c99-4ccb-9132-a961ed56d8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20111
10170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2011110170
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.981559951
Short name T1903
Test name
Test status
Simulation time 237670590 ps
CPU time 0.96 seconds
Started Jun 23 05:22:48 PM PDT 24
Finished Jun 23 05:22:50 PM PDT 24
Peak memory 205988 kb
Host smart-c3e9bcfd-a430-4e96-aee9-1a2c7b6befef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98155
9951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.981559951
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3845917521
Short name T985
Test name
Test status
Simulation time 144563533 ps
CPU time 0.73 seconds
Started Jun 23 05:22:50 PM PDT 24
Finished Jun 23 05:22:52 PM PDT 24
Peak memory 205976 kb
Host smart-87377cc7-f954-48f0-a8f5-beb56ee2366a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38459
17521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3845917521
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2414001338
Short name T2411
Test name
Test status
Simulation time 237993555 ps
CPU time 1.05 seconds
Started Jun 23 05:22:37 PM PDT 24
Finished Jun 23 05:22:39 PM PDT 24
Peak memory 206120 kb
Host smart-ae826a0a-2291-4a89-b0af-00ee39f9e063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24140
01338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2414001338
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.43671462
Short name T2381
Test name
Test status
Simulation time 247990338 ps
CPU time 0.89 seconds
Started Jun 23 05:22:41 PM PDT 24
Finished Jun 23 05:22:42 PM PDT 24
Peak memory 206060 kb
Host smart-f7dd50dc-10ac-46fb-96a2-933495c5ae54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43671
462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.43671462
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.2113134110
Short name T1577
Test name
Test status
Simulation time 23278214338 ps
CPU time 23.25 seconds
Started Jun 23 05:22:52 PM PDT 24
Finished Jun 23 05:23:17 PM PDT 24
Peak memory 206160 kb
Host smart-79db39cb-7f28-4393-a847-d77f805f1714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21131
34110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2113134110
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.128511549
Short name T1872
Test name
Test status
Simulation time 3325367434 ps
CPU time 3.91 seconds
Started Jun 23 05:22:41 PM PDT 24
Finished Jun 23 05:22:45 PM PDT 24
Peak memory 206168 kb
Host smart-7a60efa3-7e87-4057-8222-c5a7be448081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12851
1549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.128511549
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.2883319488
Short name T1377
Test name
Test status
Simulation time 9233146750 ps
CPU time 258.12 seconds
Started Jun 23 05:22:39 PM PDT 24
Finished Jun 23 05:26:57 PM PDT 24
Peak memory 206280 kb
Host smart-f1dc2943-ec4b-4697-83c3-fcc0f6ba3d4c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2883319488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.2883319488
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.216716817
Short name T2005
Test name
Test status
Simulation time 241786883 ps
CPU time 0.9 seconds
Started Jun 23 05:22:45 PM PDT 24
Finished Jun 23 05:22:47 PM PDT 24
Peak memory 206052 kb
Host smart-49b554de-78ba-4cea-9bf7-341ed9e25e8e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=216716817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.216716817
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2522316642
Short name T2257
Test name
Test status
Simulation time 218941401 ps
CPU time 0.94 seconds
Started Jun 23 05:22:52 PM PDT 24
Finished Jun 23 05:22:54 PM PDT 24
Peak memory 206116 kb
Host smart-3051c42e-7b9d-4a1b-8497-74c7aa68cd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25223
16642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2522316642
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.4281107063
Short name T1264
Test name
Test status
Simulation time 12489835706 ps
CPU time 87.2 seconds
Started Jun 23 05:22:53 PM PDT 24
Finished Jun 23 05:24:21 PM PDT 24
Peak memory 206392 kb
Host smart-06bdc7c2-b4ee-49d9-855d-b8b5d3c95735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42811
07063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.4281107063
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.1310970976
Short name T1818
Test name
Test status
Simulation time 10649693605 ps
CPU time 306.01 seconds
Started Jun 23 05:22:53 PM PDT 24
Finished Jun 23 05:28:00 PM PDT 24
Peak memory 206292 kb
Host smart-24bd19a8-26bc-4dc4-924f-41bac50021c1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1310970976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.1310970976
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.95294210
Short name T1763
Test name
Test status
Simulation time 154645036 ps
CPU time 0.81 seconds
Started Jun 23 05:22:46 PM PDT 24
Finished Jun 23 05:22:47 PM PDT 24
Peak memory 206128 kb
Host smart-d274215d-c065-48dc-a7ac-8669a20d3768
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=95294210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.95294210
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1568084793
Short name T823
Test name
Test status
Simulation time 167875694 ps
CPU time 0.8 seconds
Started Jun 23 05:22:38 PM PDT 24
Finished Jun 23 05:22:39 PM PDT 24
Peak memory 206060 kb
Host smart-70385948-348b-4aa4-a8fb-b8b5e3908c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15680
84793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1568084793
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1833919897
Short name T132
Test name
Test status
Simulation time 228908920 ps
CPU time 0.92 seconds
Started Jun 23 05:22:40 PM PDT 24
Finished Jun 23 05:22:42 PM PDT 24
Peak memory 206108 kb
Host smart-ded5f2ab-e7db-433b-9e29-19cd1e081655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18339
19897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1833919897
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3976675990
Short name T830
Test name
Test status
Simulation time 185792072 ps
CPU time 0.86 seconds
Started Jun 23 05:22:40 PM PDT 24
Finished Jun 23 05:22:42 PM PDT 24
Peak memory 206024 kb
Host smart-35887211-fe99-4d93-a5ba-328d574fc634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39766
75990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3976675990
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2144814014
Short name T1455
Test name
Test status
Simulation time 178579872 ps
CPU time 0.84 seconds
Started Jun 23 05:22:40 PM PDT 24
Finished Jun 23 05:22:42 PM PDT 24
Peak memory 206104 kb
Host smart-662cffe7-9350-40d4-9387-61d56aba3b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21448
14014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2144814014
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3502504921
Short name T1523
Test name
Test status
Simulation time 177348858 ps
CPU time 0.82 seconds
Started Jun 23 05:22:40 PM PDT 24
Finished Jun 23 05:22:42 PM PDT 24
Peak memory 206108 kb
Host smart-32dde2e7-bfd0-48e2-9c42-6b8b73850d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35025
04921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3502504921
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.2479973605
Short name T910
Test name
Test status
Simulation time 204373966 ps
CPU time 0.81 seconds
Started Jun 23 05:22:45 PM PDT 24
Finished Jun 23 05:22:46 PM PDT 24
Peak memory 206104 kb
Host smart-81c63813-738f-45dc-b0dd-6a5d557e2769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24799
73605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.2479973605
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.3073838044
Short name T800
Test name
Test status
Simulation time 237534523 ps
CPU time 1.01 seconds
Started Jun 23 05:22:42 PM PDT 24
Finished Jun 23 05:22:44 PM PDT 24
Peak memory 206124 kb
Host smart-2dc700dd-6f63-405b-9f58-70cc92c0f77d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3073838044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3073838044
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.221381420
Short name T2343
Test name
Test status
Simulation time 173355948 ps
CPU time 0.8 seconds
Started Jun 23 05:22:53 PM PDT 24
Finished Jun 23 05:22:55 PM PDT 24
Peak memory 206124 kb
Host smart-3651dfbf-c1d2-4f3b-9e9a-a26b223dce84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22138
1420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.221381420
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2216917175
Short name T1768
Test name
Test status
Simulation time 64416623 ps
CPU time 0.67 seconds
Started Jun 23 05:22:48 PM PDT 24
Finished Jun 23 05:22:50 PM PDT 24
Peak memory 206044 kb
Host smart-ad8819f7-2c5e-4bd1-bfa1-94084b3ccb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22169
17175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2216917175
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.403590522
Short name T2492
Test name
Test status
Simulation time 23486559399 ps
CPU time 53.75 seconds
Started Jun 23 05:22:40 PM PDT 24
Finished Jun 23 05:23:35 PM PDT 24
Peak memory 206428 kb
Host smart-a79b723c-4b05-492c-b748-b68565189541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40359
0522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.403590522
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2890451483
Short name T1230
Test name
Test status
Simulation time 216400688 ps
CPU time 0.83 seconds
Started Jun 23 05:22:40 PM PDT 24
Finished Jun 23 05:22:41 PM PDT 24
Peak memory 206104 kb
Host smart-397d9121-3458-4d22-8b75-be2ae84e7e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28904
51483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2890451483
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.4101671536
Short name T1018
Test name
Test status
Simulation time 177919354 ps
CPU time 0.83 seconds
Started Jun 23 05:22:42 PM PDT 24
Finished Jun 23 05:22:43 PM PDT 24
Peak memory 206016 kb
Host smart-c5561452-cc64-4171-99f6-760926838db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41016
71536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.4101671536
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.69015918
Short name T1849
Test name
Test status
Simulation time 186273649 ps
CPU time 0.79 seconds
Started Jun 23 05:22:47 PM PDT 24
Finished Jun 23 05:22:49 PM PDT 24
Peak memory 206060 kb
Host smart-db72d973-2df3-4269-8ebb-e4b00562f918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69015
918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.69015918
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1505409369
Short name T2029
Test name
Test status
Simulation time 190319777 ps
CPU time 0.85 seconds
Started Jun 23 05:22:53 PM PDT 24
Finished Jun 23 05:22:55 PM PDT 24
Peak memory 206128 kb
Host smart-18f97db9-1591-454c-aa55-1478d0aa59bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15054
09369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1505409369
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.1234728982
Short name T1097
Test name
Test status
Simulation time 146232182 ps
CPU time 0.76 seconds
Started Jun 23 05:22:42 PM PDT 24
Finished Jun 23 05:22:43 PM PDT 24
Peak memory 206000 kb
Host smart-99cf3ec9-a85a-4ec7-ae70-6435d6c1df31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12347
28982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.1234728982
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3034877961
Short name T1000
Test name
Test status
Simulation time 149869148 ps
CPU time 0.76 seconds
Started Jun 23 05:22:53 PM PDT 24
Finished Jun 23 05:22:55 PM PDT 24
Peak memory 206096 kb
Host smart-a093bb88-9460-43cd-bd13-a3766de8f1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30348
77961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3034877961
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.4149182698
Short name T328
Test name
Test status
Simulation time 173837422 ps
CPU time 0.85 seconds
Started Jun 23 05:22:39 PM PDT 24
Finished Jun 23 05:22:40 PM PDT 24
Peak memory 206096 kb
Host smart-2963803a-a834-4149-b306-613ff250f10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41491
82698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.4149182698
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1336114724
Short name T1612
Test name
Test status
Simulation time 250993727 ps
CPU time 0.92 seconds
Started Jun 23 05:22:34 PM PDT 24
Finished Jun 23 05:22:35 PM PDT 24
Peak memory 206100 kb
Host smart-4993040b-3d9d-4cb4-b76b-d818a2f87c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13361
14724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1336114724
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.3603277744
Short name T1765
Test name
Test status
Simulation time 10898568951 ps
CPU time 104.13 seconds
Started Jun 23 05:22:42 PM PDT 24
Finished Jun 23 05:24:27 PM PDT 24
Peak memory 206288 kb
Host smart-3526defa-4438-4b42-b705-6b74bd2471be
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3603277744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.3603277744
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.3906709401
Short name T1875
Test name
Test status
Simulation time 228030600 ps
CPU time 0.88 seconds
Started Jun 23 05:22:42 PM PDT 24
Finished Jun 23 05:22:43 PM PDT 24
Peak memory 206068 kb
Host smart-e192d6dd-d73c-4629-9a8e-3bcf3cb71795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39067
09401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.3906709401
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1099084652
Short name T2180
Test name
Test status
Simulation time 207026209 ps
CPU time 0.84 seconds
Started Jun 23 05:22:40 PM PDT 24
Finished Jun 23 05:22:41 PM PDT 24
Peak memory 206116 kb
Host smart-a24549a8-cd29-4391-97f7-cf7c709ba503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10990
84652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1099084652
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.4231736371
Short name T524
Test name
Test status
Simulation time 10795031721 ps
CPU time 305.23 seconds
Started Jun 23 05:22:42 PM PDT 24
Finished Jun 23 05:27:48 PM PDT 24
Peak memory 206328 kb
Host smart-326cfd0a-f6e8-43d6-a268-8ffa17ef51fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42317
36371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.4231736371
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.625235319
Short name T936
Test name
Test status
Simulation time 3859744731 ps
CPU time 4.6 seconds
Started Jun 23 05:22:46 PM PDT 24
Finished Jun 23 05:22:51 PM PDT 24
Peak memory 206364 kb
Host smart-2c306989-0569-41e8-877e-058545254b74
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=625235319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.625235319
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.3528489491
Short name T1376
Test name
Test status
Simulation time 13403786093 ps
CPU time 13.54 seconds
Started Jun 23 05:22:46 PM PDT 24
Finished Jun 23 05:23:00 PM PDT 24
Peak memory 206412 kb
Host smart-c7225799-1d6d-4350-930c-6d56173ffbd9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3528489491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.3528489491
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.392677429
Short name T1128
Test name
Test status
Simulation time 23312303712 ps
CPU time 26.87 seconds
Started Jun 23 05:22:45 PM PDT 24
Finished Jun 23 05:23:12 PM PDT 24
Peak memory 206336 kb
Host smart-2facefa4-092b-4598-a1ec-a77a62a0737b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=392677429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.392677429
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1120006410
Short name T490
Test name
Test status
Simulation time 142575590 ps
CPU time 0.72 seconds
Started Jun 23 05:22:49 PM PDT 24
Finished Jun 23 05:22:51 PM PDT 24
Peak memory 206000 kb
Host smart-c0dd508f-3ba3-4048-81c5-cc6543cc6761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11200
06410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1120006410
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.3108388144
Short name T593
Test name
Test status
Simulation time 146733108 ps
CPU time 0.73 seconds
Started Jun 23 05:22:50 PM PDT 24
Finished Jun 23 05:22:51 PM PDT 24
Peak memory 205996 kb
Host smart-571045b1-dde5-4c77-a56b-405d2ddf0aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31083
88144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.3108388144
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.2983571456
Short name T834
Test name
Test status
Simulation time 553530671 ps
CPU time 1.6 seconds
Started Jun 23 05:22:46 PM PDT 24
Finished Jun 23 05:22:49 PM PDT 24
Peak memory 206260 kb
Host smart-2d919094-585e-4135-b645-bfd3f1c1f8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29835
71456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.2983571456
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3994606694
Short name T1370
Test name
Test status
Simulation time 754291291 ps
CPU time 1.73 seconds
Started Jun 23 05:22:50 PM PDT 24
Finished Jun 23 05:22:53 PM PDT 24
Peak memory 206208 kb
Host smart-f023d3af-f94b-4126-ac8d-da9a895b8f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39946
06694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3994606694
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.2798874023
Short name T1711
Test name
Test status
Simulation time 406529693 ps
CPU time 1.39 seconds
Started Jun 23 05:22:44 PM PDT 24
Finished Jun 23 05:22:46 PM PDT 24
Peak memory 206048 kb
Host smart-eefa12fe-3810-4cbf-8592-3b63f0d6131c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27988
74023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.2798874023
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2478567576
Short name T1917
Test name
Test status
Simulation time 140381772 ps
CPU time 0.81 seconds
Started Jun 23 05:22:48 PM PDT 24
Finished Jun 23 05:22:50 PM PDT 24
Peak memory 206100 kb
Host smart-0a2f1d5a-41f3-4a81-8bb6-5b5bd44ca2bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24785
67576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2478567576
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.1819274242
Short name T1049
Test name
Test status
Simulation time 81238935 ps
CPU time 0.7 seconds
Started Jun 23 05:22:47 PM PDT 24
Finished Jun 23 05:22:48 PM PDT 24
Peak memory 206036 kb
Host smart-5b2ce4ef-dd8b-44b8-b568-c12eae8c9403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18192
74242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1819274242
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.3710329246
Short name T1723
Test name
Test status
Simulation time 885981151 ps
CPU time 1.95 seconds
Started Jun 23 05:22:50 PM PDT 24
Finished Jun 23 05:22:53 PM PDT 24
Peak memory 206212 kb
Host smart-c98f33bd-6d9d-4697-9fa6-8e0397909977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37103
29246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.3710329246
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1885822667
Short name T1504
Test name
Test status
Simulation time 223363208 ps
CPU time 2.32 seconds
Started Jun 23 05:22:55 PM PDT 24
Finished Jun 23 05:22:58 PM PDT 24
Peak memory 206224 kb
Host smart-97594731-8f77-47c9-a898-9f2ebbd500da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18858
22667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1885822667
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2456499564
Short name T104
Test name
Test status
Simulation time 233066157 ps
CPU time 0.88 seconds
Started Jun 23 05:22:53 PM PDT 24
Finished Jun 23 05:22:55 PM PDT 24
Peak memory 206092 kb
Host smart-c4d20b23-350a-42dd-9152-641d20b3dd46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24564
99564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2456499564
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2467295373
Short name T2415
Test name
Test status
Simulation time 157344537 ps
CPU time 0.84 seconds
Started Jun 23 05:22:55 PM PDT 24
Finished Jun 23 05:22:56 PM PDT 24
Peak memory 206096 kb
Host smart-ba4f078c-fcb5-4eba-8fd2-007c7ac5245f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24672
95373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2467295373
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1098930154
Short name T2486
Test name
Test status
Simulation time 204985805 ps
CPU time 0.84 seconds
Started Jun 23 05:22:48 PM PDT 24
Finished Jun 23 05:22:49 PM PDT 24
Peak memory 206092 kb
Host smart-ede30be1-bb72-4e3f-a181-a591d2dafa77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10989
30154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1098930154
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.1394557586
Short name T1747
Test name
Test status
Simulation time 219420749 ps
CPU time 0.88 seconds
Started Jun 23 05:22:48 PM PDT 24
Finished Jun 23 05:22:49 PM PDT 24
Peak memory 206064 kb
Host smart-bbdd57b1-c388-4ad2-a17d-42f5e9556dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13945
57586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.1394557586
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.3453979111
Short name T1594
Test name
Test status
Simulation time 23304441933 ps
CPU time 23.35 seconds
Started Jun 23 05:22:47 PM PDT 24
Finished Jun 23 05:23:11 PM PDT 24
Peak memory 206160 kb
Host smart-c4e2f724-199c-4cf1-b683-01bbb150cf10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34539
79111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.3453979111
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1268304647
Short name T1309
Test name
Test status
Simulation time 3307585574 ps
CPU time 3.7 seconds
Started Jun 23 05:22:47 PM PDT 24
Finished Jun 23 05:22:51 PM PDT 24
Peak memory 206100 kb
Host smart-d41115e6-3b48-45ce-ada3-f0fe17e9084c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12683
04647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1268304647
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.1270406249
Short name T732
Test name
Test status
Simulation time 7490348692 ps
CPU time 213.98 seconds
Started Jun 23 05:22:46 PM PDT 24
Finished Jun 23 05:26:20 PM PDT 24
Peak memory 206268 kb
Host smart-102bec9d-96e5-47f7-a3b6-28a712e3aa9a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1270406249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.1270406249
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.515739855
Short name T1186
Test name
Test status
Simulation time 269876727 ps
CPU time 0.94 seconds
Started Jun 23 05:22:52 PM PDT 24
Finished Jun 23 05:22:53 PM PDT 24
Peak memory 206128 kb
Host smart-7dcb9e0b-6dc5-4927-b2cd-0cf587243fd0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=515739855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.515739855
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.513703569
Short name T1198
Test name
Test status
Simulation time 193196362 ps
CPU time 0.83 seconds
Started Jun 23 05:22:47 PM PDT 24
Finished Jun 23 05:22:49 PM PDT 24
Peak memory 206076 kb
Host smart-f246c762-21fe-498f-addb-2873aa6ea7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51370
3569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.513703569
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.2395634761
Short name T145
Test name
Test status
Simulation time 7343241881 ps
CPU time 69.78 seconds
Started Jun 23 05:22:48 PM PDT 24
Finished Jun 23 05:23:58 PM PDT 24
Peak memory 206308 kb
Host smart-a0e8ca26-ea7c-4ed5-8e01-757a1e02c9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23956
34761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.2395634761
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.76373035
Short name T876
Test name
Test status
Simulation time 7660797595 ps
CPU time 50.79 seconds
Started Jun 23 05:22:47 PM PDT 24
Finished Jun 23 05:23:39 PM PDT 24
Peak memory 206296 kb
Host smart-35cbbc36-a44e-46e8-90aa-6971f2c5a11e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=76373035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.76373035
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.3881121090
Short name T907
Test name
Test status
Simulation time 161277871 ps
CPU time 0.79 seconds
Started Jun 23 05:22:55 PM PDT 24
Finished Jun 23 05:22:56 PM PDT 24
Peak memory 206144 kb
Host smart-137e7379-d447-4912-bdb2-f49c796190d2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3881121090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.3881121090
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.4150302459
Short name T1237
Test name
Test status
Simulation time 139443382 ps
CPU time 0.76 seconds
Started Jun 23 05:22:49 PM PDT 24
Finished Jun 23 05:22:50 PM PDT 24
Peak memory 206040 kb
Host smart-0775bf44-c374-440e-b871-14ec9bbc8234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41503
02459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.4150302459
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.591281066
Short name T120
Test name
Test status
Simulation time 185093838 ps
CPU time 0.82 seconds
Started Jun 23 05:22:49 PM PDT 24
Finished Jun 23 05:22:50 PM PDT 24
Peak memory 206028 kb
Host smart-8d91c2b4-3a39-4201-9d26-85b467a00349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59128
1066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.591281066
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.643445130
Short name T1204
Test name
Test status
Simulation time 192249118 ps
CPU time 0.88 seconds
Started Jun 23 05:22:47 PM PDT 24
Finished Jun 23 05:22:49 PM PDT 24
Peak memory 206104 kb
Host smart-7f32c665-3231-4b27-af37-d62d01920c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64344
5130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.643445130
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2847060542
Short name T1912
Test name
Test status
Simulation time 149535465 ps
CPU time 0.77 seconds
Started Jun 23 05:22:48 PM PDT 24
Finished Jun 23 05:22:49 PM PDT 24
Peak memory 205984 kb
Host smart-ca2013fc-8803-470d-a8dc-87a2d272ac79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28470
60542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2847060542
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.939029725
Short name T518
Test name
Test status
Simulation time 208754892 ps
CPU time 0.87 seconds
Started Jun 23 05:22:47 PM PDT 24
Finished Jun 23 05:22:49 PM PDT 24
Peak memory 206120 kb
Host smart-f1aa78d6-b7c7-4d89-86eb-4dabddb91d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93902
9725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.939029725
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.1073908144
Short name T929
Test name
Test status
Simulation time 152410391 ps
CPU time 0.82 seconds
Started Jun 23 05:22:54 PM PDT 24
Finished Jun 23 05:22:56 PM PDT 24
Peak memory 206040 kb
Host smart-e9b331e2-3ed6-4475-8a53-f34e90cb0d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10739
08144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.1073908144
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.499464848
Short name T962
Test name
Test status
Simulation time 222152837 ps
CPU time 0.91 seconds
Started Jun 23 05:22:52 PM PDT 24
Finished Jun 23 05:22:54 PM PDT 24
Peak memory 206048 kb
Host smart-75aae493-2009-4cb3-bd67-0075f5258e3f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=499464848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.499464848
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2591332358
Short name T1520
Test name
Test status
Simulation time 147369553 ps
CPU time 0.83 seconds
Started Jun 23 05:22:50 PM PDT 24
Finished Jun 23 05:22:52 PM PDT 24
Peak memory 206168 kb
Host smart-b7e38de5-e53d-46fd-b685-e240da0aa9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25913
32358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2591332358
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.3783687254
Short name T1828
Test name
Test status
Simulation time 34996110 ps
CPU time 0.66 seconds
Started Jun 23 05:22:50 PM PDT 24
Finished Jun 23 05:22:52 PM PDT 24
Peak memory 206052 kb
Host smart-c1cec5ce-1472-4a33-98e9-4cc0be6754d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37836
87254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.3783687254
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2776847768
Short name T1578
Test name
Test status
Simulation time 6614529553 ps
CPU time 14.47 seconds
Started Jun 23 05:22:47 PM PDT 24
Finished Jun 23 05:23:03 PM PDT 24
Peak memory 206404 kb
Host smart-3ae00c13-80b2-456e-9967-deeee26b9a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27768
47768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2776847768
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.471640503
Short name T263
Test name
Test status
Simulation time 231815679 ps
CPU time 0.9 seconds
Started Jun 23 05:22:45 PM PDT 24
Finished Jun 23 05:22:47 PM PDT 24
Peak memory 206096 kb
Host smart-c45fc3e9-b54e-47a9-9ee3-8763ae641af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47164
0503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.471640503
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3550176938
Short name T2387
Test name
Test status
Simulation time 189532339 ps
CPU time 0.89 seconds
Started Jun 23 05:22:46 PM PDT 24
Finished Jun 23 05:22:47 PM PDT 24
Peak memory 206248 kb
Host smart-92b0d8b4-0d72-473c-9152-4a347d959ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35501
76938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3550176938
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.2300159346
Short name T292
Test name
Test status
Simulation time 178812838 ps
CPU time 0.82 seconds
Started Jun 23 05:22:53 PM PDT 24
Finished Jun 23 05:22:55 PM PDT 24
Peak memory 206088 kb
Host smart-3220893f-23aa-420d-9c26-68144f5775de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23001
59346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.2300159346
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.4106650615
Short name T2032
Test name
Test status
Simulation time 163101977 ps
CPU time 0.81 seconds
Started Jun 23 05:22:53 PM PDT 24
Finished Jun 23 05:22:55 PM PDT 24
Peak memory 206116 kb
Host smart-0b869904-239f-4c8a-a987-35710385f7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41066
50615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.4106650615
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.1240189789
Short name T1963
Test name
Test status
Simulation time 181574758 ps
CPU time 0.82 seconds
Started Jun 23 05:22:56 PM PDT 24
Finished Jun 23 05:22:57 PM PDT 24
Peak memory 206096 kb
Host smart-eb006b56-adc8-4bf6-8ac1-7553e6ba0757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12401
89789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1240189789
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.2458371483
Short name T1314
Test name
Test status
Simulation time 149169770 ps
CPU time 0.8 seconds
Started Jun 23 05:22:54 PM PDT 24
Finished Jun 23 05:22:56 PM PDT 24
Peak memory 206096 kb
Host smart-fae08f14-f949-44fd-910f-2f304b0996c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24583
71483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2458371483
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1537721031
Short name T1633
Test name
Test status
Simulation time 179389659 ps
CPU time 0.81 seconds
Started Jun 23 05:22:51 PM PDT 24
Finished Jun 23 05:22:53 PM PDT 24
Peak memory 206112 kb
Host smart-c7167dde-d84a-46fd-8ebb-bc8dd07a23c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15377
21031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1537721031
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3458659955
Short name T362
Test name
Test status
Simulation time 218324189 ps
CPU time 0.91 seconds
Started Jun 23 05:22:47 PM PDT 24
Finished Jun 23 05:22:49 PM PDT 24
Peak memory 206048 kb
Host smart-b245b396-5a30-4963-a0aa-1d3d1d7b96c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34586
59955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3458659955
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.3015769892
Short name T872
Test name
Test status
Simulation time 9924710316 ps
CPU time 99.73 seconds
Started Jun 23 05:22:52 PM PDT 24
Finished Jun 23 05:24:33 PM PDT 24
Peak memory 206372 kb
Host smart-20749d27-8dbb-44a3-9bb7-495d622fae2f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3015769892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.3015769892
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.2926931779
Short name T300
Test name
Test status
Simulation time 164077563 ps
CPU time 0.84 seconds
Started Jun 23 05:22:54 PM PDT 24
Finished Jun 23 05:22:56 PM PDT 24
Peak memory 206104 kb
Host smart-ae34f21f-f687-48d0-ad54-aabe1fd60486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29269
31779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.2926931779
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.253489214
Short name T1414
Test name
Test status
Simulation time 215650174 ps
CPU time 0.87 seconds
Started Jun 23 05:22:55 PM PDT 24
Finished Jun 23 05:22:56 PM PDT 24
Peak memory 206120 kb
Host smart-bfa7dfee-1297-432e-9834-4f67614ab9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25348
9214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.253489214
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.1538440174
Short name T1200
Test name
Test status
Simulation time 4086305418 ps
CPU time 40.61 seconds
Started Jun 23 05:22:51 PM PDT 24
Finished Jun 23 05:23:32 PM PDT 24
Peak memory 206344 kb
Host smart-33651aa3-2e38-4c8a-a19f-90f3c27058c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15384
40174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1538440174
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1983991444
Short name T1267
Test name
Test status
Simulation time 4193161862 ps
CPU time 4.69 seconds
Started Jun 23 05:22:56 PM PDT 24
Finished Jun 23 05:23:01 PM PDT 24
Peak memory 206156 kb
Host smart-c7477ba7-5892-4625-8dc8-7c149c23497b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1983991444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.1983991444
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.3558036794
Short name T712
Test name
Test status
Simulation time 13410451405 ps
CPU time 12.67 seconds
Started Jun 23 05:22:55 PM PDT 24
Finished Jun 23 05:23:09 PM PDT 24
Peak memory 206160 kb
Host smart-5fcd5ab4-fe81-4b12-b0da-5d0d213470f2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3558036794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.3558036794
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.890272340
Short name T919
Test name
Test status
Simulation time 23383998262 ps
CPU time 25.53 seconds
Started Jun 23 05:22:53 PM PDT 24
Finished Jun 23 05:23:20 PM PDT 24
Peak memory 206168 kb
Host smart-f66a8827-22d5-4f83-befb-bb63a716c482
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=890272340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.890272340
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3158034813
Short name T433
Test name
Test status
Simulation time 199138798 ps
CPU time 0.87 seconds
Started Jun 23 05:22:51 PM PDT 24
Finished Jun 23 05:22:53 PM PDT 24
Peak memory 206072 kb
Host smart-d4af1d88-d974-4faa-a655-b36edbe144cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31580
34813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3158034813
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.3410298369
Short name T1506
Test name
Test status
Simulation time 202588779 ps
CPU time 0.84 seconds
Started Jun 23 05:22:53 PM PDT 24
Finished Jun 23 05:22:55 PM PDT 24
Peak memory 206104 kb
Host smart-45cbc49f-9a17-4d37-af33-3ea03a2da0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34102
98369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.3410298369
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.2190686770
Short name T1245
Test name
Test status
Simulation time 450608220 ps
CPU time 1.3 seconds
Started Jun 23 05:22:51 PM PDT 24
Finished Jun 23 05:22:54 PM PDT 24
Peak memory 206036 kb
Host smart-bf328245-25fb-41d0-9556-45e39679d905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21906
86770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2190686770
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1751495186
Short name T2445
Test name
Test status
Simulation time 485546910 ps
CPU time 1.3 seconds
Started Jun 23 05:22:51 PM PDT 24
Finished Jun 23 05:22:53 PM PDT 24
Peak memory 206108 kb
Host smart-6d585de6-0ea3-4895-bab2-2c7961f9473a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17514
95186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1751495186
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.537809110
Short name T426
Test name
Test status
Simulation time 12845707612 ps
CPU time 23.15 seconds
Started Jun 23 05:22:52 PM PDT 24
Finished Jun 23 05:23:16 PM PDT 24
Peak memory 206344 kb
Host smart-74834c36-3b4a-40c8-8638-d8e208f12610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53780
9110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.537809110
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.1367898694
Short name T2474
Test name
Test status
Simulation time 353422194 ps
CPU time 1.15 seconds
Started Jun 23 05:22:54 PM PDT 24
Finished Jun 23 05:22:56 PM PDT 24
Peak memory 206100 kb
Host smart-0fd8c73a-6bfa-402e-82b6-fbb73b01e7ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13678
98694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.1367898694
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.2469317909
Short name T443
Test name
Test status
Simulation time 176036315 ps
CPU time 0.75 seconds
Started Jun 23 05:22:51 PM PDT 24
Finished Jun 23 05:22:52 PM PDT 24
Peak memory 206100 kb
Host smart-da4d2f0e-182a-44ef-9e21-2de88f309196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24693
17909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.2469317909
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.3693680606
Short name T912
Test name
Test status
Simulation time 42433431 ps
CPU time 0.66 seconds
Started Jun 23 05:22:53 PM PDT 24
Finished Jun 23 05:22:55 PM PDT 24
Peak memory 206012 kb
Host smart-c977817b-3ee4-460b-bcf4-6abc54f91c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36936
80606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3693680606
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.3863343095
Short name T1285
Test name
Test status
Simulation time 891293467 ps
CPU time 2.12 seconds
Started Jun 23 05:22:53 PM PDT 24
Finished Jun 23 05:22:56 PM PDT 24
Peak memory 206336 kb
Host smart-f733b621-1c94-4d37-afd9-f873ae61dcaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38633
43095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.3863343095
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1476234599
Short name T1459
Test name
Test status
Simulation time 258939864 ps
CPU time 1.91 seconds
Started Jun 23 05:22:51 PM PDT 24
Finished Jun 23 05:22:54 PM PDT 24
Peak memory 206340 kb
Host smart-e8facd56-bad6-427d-b1ba-458485b511c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14762
34599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1476234599
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2431749554
Short name T1105
Test name
Test status
Simulation time 176388819 ps
CPU time 0.79 seconds
Started Jun 23 05:22:57 PM PDT 24
Finished Jun 23 05:22:58 PM PDT 24
Peak memory 206100 kb
Host smart-ddbc4994-4819-411b-87a6-ec04ea58fa6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24317
49554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2431749554
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.358996797
Short name T827
Test name
Test status
Simulation time 148065723 ps
CPU time 0.76 seconds
Started Jun 23 05:22:57 PM PDT 24
Finished Jun 23 05:22:59 PM PDT 24
Peak memory 206052 kb
Host smart-69a8511d-9e98-45f1-8d29-049af85341ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35899
6797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.358996797
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3726879844
Short name T21
Test name
Test status
Simulation time 204341318 ps
CPU time 0.95 seconds
Started Jun 23 05:22:55 PM PDT 24
Finished Jun 23 05:22:57 PM PDT 24
Peak memory 206092 kb
Host smart-d23c1f53-43ba-4623-a22d-b35f94078081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37268
79844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3726879844
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3974695216
Short name T1170
Test name
Test status
Simulation time 205133566 ps
CPU time 0.86 seconds
Started Jun 23 05:22:55 PM PDT 24
Finished Jun 23 05:22:56 PM PDT 24
Peak memory 206072 kb
Host smart-3f33197f-5413-47a7-ba59-a067740b773a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39746
95216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3974695216
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.738296027
Short name T1812
Test name
Test status
Simulation time 23284560570 ps
CPU time 23.33 seconds
Started Jun 23 05:22:55 PM PDT 24
Finished Jun 23 05:23:19 PM PDT 24
Peak memory 206180 kb
Host smart-da62ac0c-aa9d-4dad-813e-45ae88867cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73829
6027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.738296027
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.3072536826
Short name T1201
Test name
Test status
Simulation time 3333851146 ps
CPU time 4.87 seconds
Started Jun 23 05:22:52 PM PDT 24
Finished Jun 23 05:22:58 PM PDT 24
Peak memory 206156 kb
Host smart-6fdec60f-b91e-4cb8-856e-3a830d62a25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30725
36826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.3072536826
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2542122639
Short name T2427
Test name
Test status
Simulation time 12457730431 ps
CPU time 349.76 seconds
Started Jun 23 05:22:52 PM PDT 24
Finished Jun 23 05:28:43 PM PDT 24
Peak memory 206384 kb
Host smart-4abbcba4-ab12-47f4-a5dc-88023f2b3eac
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2542122639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2542122639
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.360486923
Short name T1109
Test name
Test status
Simulation time 293179580 ps
CPU time 0.94 seconds
Started Jun 23 05:23:01 PM PDT 24
Finished Jun 23 05:23:03 PM PDT 24
Peak memory 205900 kb
Host smart-2b781b02-192c-4d0d-a3b2-dd219bdf7438
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=360486923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.360486923
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2690653760
Short name T567
Test name
Test status
Simulation time 239206338 ps
CPU time 0.87 seconds
Started Jun 23 05:22:51 PM PDT 24
Finished Jun 23 05:22:53 PM PDT 24
Peak memory 206032 kb
Host smart-b099e176-caa0-41c8-992a-920cfecf7a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26906
53760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2690653760
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.2036685365
Short name T2078
Test name
Test status
Simulation time 6695474869 ps
CPU time 47.24 seconds
Started Jun 23 05:22:56 PM PDT 24
Finished Jun 23 05:23:44 PM PDT 24
Peak memory 206404 kb
Host smart-d2fda8cf-29a9-48a8-a92d-3e3138b7458b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20366
85365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.2036685365
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.4042386030
Short name T480
Test name
Test status
Simulation time 4976926210 ps
CPU time 140.42 seconds
Started Jun 23 05:22:50 PM PDT 24
Finished Jun 23 05:25:12 PM PDT 24
Peak memory 206308 kb
Host smart-919cf56d-ef3b-4895-b06e-3b9df57e6be4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4042386030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.4042386030
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.1509921952
Short name T743
Test name
Test status
Simulation time 146946766 ps
CPU time 0.8 seconds
Started Jun 23 05:23:00 PM PDT 24
Finished Jun 23 05:23:01 PM PDT 24
Peak memory 206068 kb
Host smart-f067110d-c25f-4557-989e-4876d276a43c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1509921952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.1509921952
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.873846999
Short name T2008
Test name
Test status
Simulation time 156796614 ps
CPU time 0.82 seconds
Started Jun 23 05:22:52 PM PDT 24
Finished Jun 23 05:22:55 PM PDT 24
Peak memory 206032 kb
Host smart-57f1c44f-3476-4060-ae95-be4a35596cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87384
6999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.873846999
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.3361898503
Short name T2198
Test name
Test status
Simulation time 228651152 ps
CPU time 0.92 seconds
Started Jun 23 05:22:53 PM PDT 24
Finished Jun 23 05:22:56 PM PDT 24
Peak memory 206020 kb
Host smart-12b30f48-a31b-4fb9-89c8-c817b5ce14ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33618
98503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3361898503
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.182352933
Short name T890
Test name
Test status
Simulation time 172803833 ps
CPU time 0.83 seconds
Started Jun 23 05:22:51 PM PDT 24
Finished Jun 23 05:22:53 PM PDT 24
Peak memory 206104 kb
Host smart-94a3ba68-2908-42f1-999e-b425ff39834d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18235
2933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.182352933
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1800669110
Short name T546
Test name
Test status
Simulation time 169401194 ps
CPU time 0.78 seconds
Started Jun 23 05:22:59 PM PDT 24
Finished Jun 23 05:23:00 PM PDT 24
Peak memory 206032 kb
Host smart-143f09c6-b6b6-43bc-9790-0d20c4f4ae25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18006
69110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1800669110
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1584587146
Short name T2259
Test name
Test status
Simulation time 172948607 ps
CPU time 0.81 seconds
Started Jun 23 05:22:58 PM PDT 24
Finished Jun 23 05:22:59 PM PDT 24
Peak memory 206056 kb
Host smart-c32ecd21-4671-46f9-a0d9-687eafe60aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15845
87146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1584587146
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1698263273
Short name T162
Test name
Test status
Simulation time 152926349 ps
CPU time 0.77 seconds
Started Jun 23 05:23:03 PM PDT 24
Finished Jun 23 05:23:04 PM PDT 24
Peak memory 206092 kb
Host smart-830c3e01-7b69-4e4e-8a0b-9bd5c09bf85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16982
63273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1698263273
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.3478871024
Short name T956
Test name
Test status
Simulation time 224248579 ps
CPU time 0.92 seconds
Started Jun 23 05:22:57 PM PDT 24
Finished Jun 23 05:22:59 PM PDT 24
Peak memory 206128 kb
Host smart-e4699fb0-fd94-43b4-9cf9-691661596890
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3478871024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.3478871024
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3131580053
Short name T1142
Test name
Test status
Simulation time 141056140 ps
CPU time 0.76 seconds
Started Jun 23 05:22:59 PM PDT 24
Finished Jun 23 05:23:00 PM PDT 24
Peak memory 206084 kb
Host smart-e3b03d85-7eb8-4eb4-837a-ef331a2074ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31315
80053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3131580053
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.3247326333
Short name T37
Test name
Test status
Simulation time 37950582 ps
CPU time 0.63 seconds
Started Jun 23 05:23:01 PM PDT 24
Finished Jun 23 05:23:02 PM PDT 24
Peak memory 205860 kb
Host smart-841e1701-2d65-4ecd-9c74-024c37b40e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32473
26333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.3247326333
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.2381613164
Short name T1576
Test name
Test status
Simulation time 12743967636 ps
CPU time 26.41 seconds
Started Jun 23 05:22:59 PM PDT 24
Finished Jun 23 05:23:26 PM PDT 24
Peak memory 206360 kb
Host smart-0a815d16-6abc-4bf7-8cfb-e84ea6463d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23816
13164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.2381613164
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3760836789
Short name T2299
Test name
Test status
Simulation time 188702979 ps
CPU time 0.78 seconds
Started Jun 23 05:23:01 PM PDT 24
Finished Jun 23 05:23:02 PM PDT 24
Peak memory 205868 kb
Host smart-78869bed-8baf-4d51-9b03-c986eeaa20c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37608
36789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3760836789
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3847244196
Short name T1477
Test name
Test status
Simulation time 256099234 ps
CPU time 0.92 seconds
Started Jun 23 05:23:05 PM PDT 24
Finished Jun 23 05:23:07 PM PDT 24
Peak memory 206080 kb
Host smart-ebb44884-9788-4da0-8597-675b2d8271ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38472
44196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3847244196
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1692330728
Short name T1275
Test name
Test status
Simulation time 179013332 ps
CPU time 0.86 seconds
Started Jun 23 05:22:55 PM PDT 24
Finished Jun 23 05:22:57 PM PDT 24
Peak memory 206076 kb
Host smart-5b7aaa10-7f20-4ea6-b987-941cd7e6431b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16923
30728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1692330728
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.3471050064
Short name T1591
Test name
Test status
Simulation time 188416452 ps
CPU time 0.84 seconds
Started Jun 23 05:22:58 PM PDT 24
Finished Jun 23 05:22:59 PM PDT 24
Peak memory 206116 kb
Host smart-f64d39e4-16d5-441b-83bd-8c5cbe74c450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34710
50064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.3471050064
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1192082944
Short name T1
Test name
Test status
Simulation time 148983140 ps
CPU time 0.77 seconds
Started Jun 23 05:22:57 PM PDT 24
Finished Jun 23 05:22:59 PM PDT 24
Peak memory 206088 kb
Host smart-b0b345d6-2008-4675-9a6a-56fe2f69a389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11920
82944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1192082944
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3985098571
Short name T984
Test name
Test status
Simulation time 165909648 ps
CPU time 0.82 seconds
Started Jun 23 05:22:56 PM PDT 24
Finished Jun 23 05:22:57 PM PDT 24
Peak memory 206112 kb
Host smart-0d880001-e4e1-440a-9c14-d548cf048b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39850
98571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3985098571
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2557090472
Short name T2277
Test name
Test status
Simulation time 148767021 ps
CPU time 0.78 seconds
Started Jun 23 05:23:00 PM PDT 24
Finished Jun 23 05:23:01 PM PDT 24
Peak memory 206044 kb
Host smart-83c5a988-d6c4-4d36-8f36-5f460e94a4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25570
90472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2557090472
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.906756457
Short name T1061
Test name
Test status
Simulation time 200768085 ps
CPU time 0.91 seconds
Started Jun 23 05:22:51 PM PDT 24
Finished Jun 23 05:22:53 PM PDT 24
Peak memory 206104 kb
Host smart-c905e75e-dc51-45cd-b3a1-2927c6122f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90675
6457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.906756457
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.4113245139
Short name T1120
Test name
Test status
Simulation time 6982189695 ps
CPU time 50.17 seconds
Started Jun 23 05:22:58 PM PDT 24
Finished Jun 23 05:23:49 PM PDT 24
Peak memory 206340 kb
Host smart-fc1817c0-5b20-4813-93a6-813c5398a881
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4113245139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.4113245139
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2518358551
Short name T692
Test name
Test status
Simulation time 187368930 ps
CPU time 0.88 seconds
Started Jun 23 05:22:57 PM PDT 24
Finished Jun 23 05:22:58 PM PDT 24
Peak memory 206068 kb
Host smart-2da52512-e1e1-4b2f-b91b-3c3713d02b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25183
58551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2518358551
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.2308641230
Short name T1196
Test name
Test status
Simulation time 174172864 ps
CPU time 0.83 seconds
Started Jun 23 05:23:00 PM PDT 24
Finished Jun 23 05:23:01 PM PDT 24
Peak memory 206040 kb
Host smart-5fbb662c-38e6-457d-9d0a-a51283949219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23086
41230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.2308641230
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3360547705
Short name T1238
Test name
Test status
Simulation time 10161264905 ps
CPU time 265.82 seconds
Started Jun 23 05:22:57 PM PDT 24
Finished Jun 23 05:27:23 PM PDT 24
Peak memory 206256 kb
Host smart-71a353dd-6d19-4ac9-8739-33835b910bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33605
47705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3360547705
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.1055567234
Short name T14
Test name
Test status
Simulation time 4165879230 ps
CPU time 4.56 seconds
Started Jun 23 05:22:57 PM PDT 24
Finished Jun 23 05:23:02 PM PDT 24
Peak memory 206108 kb
Host smart-9e2ff7f5-e34e-4ad0-8978-6da47794b5f2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1055567234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.1055567234
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.2655074394
Short name T8
Test name
Test status
Simulation time 13371947074 ps
CPU time 12.43 seconds
Started Jun 23 05:22:56 PM PDT 24
Finished Jun 23 05:23:09 PM PDT 24
Peak memory 206316 kb
Host smart-464e5824-508d-4540-b77b-a302c68b4c47
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2655074394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2655074394
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1745768314
Short name T407
Test name
Test status
Simulation time 23313026189 ps
CPU time 22.17 seconds
Started Jun 23 05:22:56 PM PDT 24
Finished Jun 23 05:23:19 PM PDT 24
Peak memory 206332 kb
Host smart-57da8eec-c36c-42c3-9580-aa6aa326300a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1745768314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.1745768314
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1356562213
Short name T2154
Test name
Test status
Simulation time 154495225 ps
CPU time 0.77 seconds
Started Jun 23 05:23:01 PM PDT 24
Finished Jun 23 05:23:03 PM PDT 24
Peak memory 205876 kb
Host smart-745897c3-406b-4ce1-9a47-dd626cc1a2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13565
62213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1356562213
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2996534766
Short name T1809
Test name
Test status
Simulation time 159841733 ps
CPU time 0.77 seconds
Started Jun 23 05:23:03 PM PDT 24
Finished Jun 23 05:23:05 PM PDT 24
Peak memory 206096 kb
Host smart-6d6445b5-ec88-419b-9138-6790804b054e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29965
34766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2996534766
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.2468146664
Short name T1813
Test name
Test status
Simulation time 222036129 ps
CPU time 0.96 seconds
Started Jun 23 05:23:00 PM PDT 24
Finished Jun 23 05:23:01 PM PDT 24
Peak memory 206104 kb
Host smart-cf0dd928-e406-4991-9ebf-b1d773bdc038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24681
46664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.2468146664
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_device_address.3670681359
Short name T178
Test name
Test status
Simulation time 17476489515 ps
CPU time 36.69 seconds
Started Jun 23 05:23:04 PM PDT 24
Finished Jun 23 05:23:41 PM PDT 24
Peak memory 206352 kb
Host smart-2f3a0234-7fe8-4a31-a155-3bde2bc82af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36706
81359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.3670681359
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.367890718
Short name T1526
Test name
Test status
Simulation time 497673416 ps
CPU time 1.41 seconds
Started Jun 23 05:23:01 PM PDT 24
Finished Jun 23 05:23:03 PM PDT 24
Peak memory 206108 kb
Host smart-5a6370cd-f4bb-446f-90d8-650b37a589a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36789
0718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.367890718
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.3715596013
Short name T1004
Test name
Test status
Simulation time 146498163 ps
CPU time 0.75 seconds
Started Jun 23 05:23:00 PM PDT 24
Finished Jun 23 05:23:01 PM PDT 24
Peak memory 206100 kb
Host smart-440b5309-be04-4ca5-94de-55798ba2d006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37155
96013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3715596013
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2314617267
Short name T1569
Test name
Test status
Simulation time 39925603 ps
CPU time 0.72 seconds
Started Jun 23 05:23:02 PM PDT 24
Finished Jun 23 05:23:03 PM PDT 24
Peak memory 206028 kb
Host smart-c537cade-80e7-47cf-8ddd-390871b59f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23146
17267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2314617267
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1722671883
Short name T81
Test name
Test status
Simulation time 858591427 ps
CPU time 2.01 seconds
Started Jun 23 05:23:05 PM PDT 24
Finished Jun 23 05:23:08 PM PDT 24
Peak memory 206300 kb
Host smart-c73be0d4-28b2-4289-af60-d02f471958f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17226
71883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1722671883
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.221985803
Short name T1393
Test name
Test status
Simulation time 305329426 ps
CPU time 2.04 seconds
Started Jun 23 05:23:00 PM PDT 24
Finished Jun 23 05:23:02 PM PDT 24
Peak memory 206276 kb
Host smart-6ee5374e-cbf3-49d7-ab7d-8b862a131c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22198
5803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.221985803
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2620310505
Short name T2286
Test name
Test status
Simulation time 182882224 ps
CPU time 0.8 seconds
Started Jun 23 05:23:07 PM PDT 24
Finished Jun 23 05:23:09 PM PDT 24
Peak memory 206100 kb
Host smart-aade60c7-0b43-4988-974d-6eda34968c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26203
10505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2620310505
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.4294878902
Short name T2025
Test name
Test status
Simulation time 150851821 ps
CPU time 0.85 seconds
Started Jun 23 05:23:03 PM PDT 24
Finished Jun 23 05:23:04 PM PDT 24
Peak memory 206052 kb
Host smart-1102080c-09cf-4583-955a-d23651cece68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42948
78902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.4294878902
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1332602193
Short name T715
Test name
Test status
Simulation time 238862444 ps
CPU time 0.9 seconds
Started Jun 23 05:23:02 PM PDT 24
Finished Jun 23 05:23:04 PM PDT 24
Peak memory 206036 kb
Host smart-6d625c69-9df2-479a-a830-1692be12a393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13326
02193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1332602193
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.1984159259
Short name T222
Test name
Test status
Simulation time 17760643325 ps
CPU time 127.26 seconds
Started Jun 23 05:23:02 PM PDT 24
Finished Jun 23 05:25:12 PM PDT 24
Peak memory 206364 kb
Host smart-08cc823c-2c40-4b11-8e03-d025becd190d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1984159259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.1984159259
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1025322897
Short name T2334
Test name
Test status
Simulation time 215306169 ps
CPU time 0.94 seconds
Started Jun 23 05:23:02 PM PDT 24
Finished Jun 23 05:23:04 PM PDT 24
Peak memory 206028 kb
Host smart-b125fdc7-2e63-46b2-898c-96f4772a255c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10253
22897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1025322897
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.3756988535
Short name T501
Test name
Test status
Simulation time 23261979892 ps
CPU time 22.5 seconds
Started Jun 23 05:23:01 PM PDT 24
Finished Jun 23 05:23:25 PM PDT 24
Peak memory 206164 kb
Host smart-e2db8c59-69b4-4c94-9b5c-734aad1634c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37569
88535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.3756988535
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3061335972
Short name T2421
Test name
Test status
Simulation time 3322144552 ps
CPU time 3.8 seconds
Started Jun 23 05:23:02 PM PDT 24
Finished Jun 23 05:23:07 PM PDT 24
Peak memory 206068 kb
Host smart-3d46a698-6046-42c4-83a1-b27d218003e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30613
35972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3061335972
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.755856929
Short name T1184
Test name
Test status
Simulation time 4794895319 ps
CPU time 32.5 seconds
Started Jun 23 05:23:02 PM PDT 24
Finished Jun 23 05:23:36 PM PDT 24
Peak memory 206112 kb
Host smart-7d5e9abc-1a4a-465d-b146-8277040d60e4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=755856929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.755856929
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.631370810
Short name T1151
Test name
Test status
Simulation time 245844278 ps
CPU time 0.92 seconds
Started Jun 23 05:23:04 PM PDT 24
Finished Jun 23 05:23:06 PM PDT 24
Peak memory 206076 kb
Host smart-e43cbbde-4133-4e83-9482-ffd14eebfb91
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=631370810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.631370810
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.4281689566
Short name T1510
Test name
Test status
Simulation time 191181698 ps
CPU time 0.88 seconds
Started Jun 23 05:23:00 PM PDT 24
Finished Jun 23 05:23:01 PM PDT 24
Peak memory 206060 kb
Host smart-4c1297f3-e8ec-4823-b41e-1ec38487cb45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42816
89566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.4281689566
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.3809261505
Short name T1668
Test name
Test status
Simulation time 11881874042 ps
CPU time 103.59 seconds
Started Jun 23 05:23:04 PM PDT 24
Finished Jun 23 05:24:48 PM PDT 24
Peak memory 206256 kb
Host smart-80773460-d438-48b7-b424-5934ebf905df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38092
61505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.3809261505
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.4257195385
Short name T2009
Test name
Test status
Simulation time 13291531445 ps
CPU time 98.04 seconds
Started Jun 23 05:23:04 PM PDT 24
Finished Jun 23 05:24:42 PM PDT 24
Peak memory 206292 kb
Host smart-63b02d61-d903-4b84-9f71-d5d03575ac8c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4257195385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.4257195385
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1133828548
Short name T453
Test name
Test status
Simulation time 158466874 ps
CPU time 0.81 seconds
Started Jun 23 05:23:05 PM PDT 24
Finished Jun 23 05:23:06 PM PDT 24
Peak memory 206104 kb
Host smart-3f4ec113-a588-4951-8f9f-36db2184abd0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1133828548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1133828548
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1189275209
Short name T1467
Test name
Test status
Simulation time 177965215 ps
CPU time 0.78 seconds
Started Jun 23 05:23:01 PM PDT 24
Finished Jun 23 05:23:03 PM PDT 24
Peak memory 206112 kb
Host smart-d420ba4d-53d2-4c73-baeb-6370b150749e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11892
75209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1189275209
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.682952773
Short name T116
Test name
Test status
Simulation time 198405704 ps
CPU time 0.82 seconds
Started Jun 23 05:23:02 PM PDT 24
Finished Jun 23 05:23:04 PM PDT 24
Peak memory 206248 kb
Host smart-7b67cb31-5059-45c6-8c8e-d87db3f5f9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68295
2773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.682952773
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.228312360
Short name T733
Test name
Test status
Simulation time 184439861 ps
CPU time 0.91 seconds
Started Jun 23 05:23:02 PM PDT 24
Finished Jun 23 05:23:04 PM PDT 24
Peak memory 206100 kb
Host smart-cb808042-3797-4194-83f0-1bd892d05f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22831
2360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.228312360
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2093620068
Short name T29
Test name
Test status
Simulation time 176065998 ps
CPU time 0.89 seconds
Started Jun 23 05:23:01 PM PDT 24
Finished Jun 23 05:23:02 PM PDT 24
Peak memory 206100 kb
Host smart-9487d95f-24ab-44c9-b76f-5d7e81a2519b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20936
20068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2093620068
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2945398094
Short name T2327
Test name
Test status
Simulation time 165565435 ps
CPU time 0.79 seconds
Started Jun 23 05:23:04 PM PDT 24
Finished Jun 23 05:23:06 PM PDT 24
Peak memory 206120 kb
Host smart-ded003aa-196d-4ede-80aa-1301515ba2b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29453
98094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2945398094
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1095830434
Short name T1155
Test name
Test status
Simulation time 146658323 ps
CPU time 0.78 seconds
Started Jun 23 05:23:02 PM PDT 24
Finished Jun 23 05:23:04 PM PDT 24
Peak memory 206104 kb
Host smart-584b7510-c37b-4720-9d0a-ad6628c83ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10958
30434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1095830434
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.894315802
Short name T857
Test name
Test status
Simulation time 210622795 ps
CPU time 0.95 seconds
Started Jun 23 05:23:07 PM PDT 24
Finished Jun 23 05:23:09 PM PDT 24
Peak memory 206128 kb
Host smart-3da65e04-bfd1-40b5-bca0-0c4b8c0c7444
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=894315802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.894315802
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.1800502815
Short name T465
Test name
Test status
Simulation time 164917323 ps
CPU time 0.78 seconds
Started Jun 23 05:23:04 PM PDT 24
Finished Jun 23 05:23:05 PM PDT 24
Peak memory 206108 kb
Host smart-c1154100-4f7e-43c8-b9ae-68f7ea484296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18005
02815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.1800502815
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2943871724
Short name T1473
Test name
Test status
Simulation time 85188564 ps
CPU time 0.73 seconds
Started Jun 23 05:23:02 PM PDT 24
Finished Jun 23 05:23:04 PM PDT 24
Peak memory 206044 kb
Host smart-b8035502-631c-4770-ad02-fd489d75447f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29438
71724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2943871724
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.279172794
Short name T2401
Test name
Test status
Simulation time 7251885455 ps
CPU time 15.76 seconds
Started Jun 23 05:23:08 PM PDT 24
Finished Jun 23 05:23:24 PM PDT 24
Peak memory 206432 kb
Host smart-a63f08b0-449f-4810-9360-c118a890510f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27917
2794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.279172794
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1738549210
Short name T678
Test name
Test status
Simulation time 188238316 ps
CPU time 0.86 seconds
Started Jun 23 05:23:08 PM PDT 24
Finished Jun 23 05:23:10 PM PDT 24
Peak memory 206108 kb
Host smart-4ae77b04-c1f2-4bd1-be9a-be27bcc0b6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17385
49210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1738549210
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.308639141
Short name T751
Test name
Test status
Simulation time 213629799 ps
CPU time 0.9 seconds
Started Jun 23 05:23:03 PM PDT 24
Finished Jun 23 05:23:04 PM PDT 24
Peak memory 206092 kb
Host smart-4bc94175-ba50-45b7-b936-e6361c05507d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30863
9141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.308639141
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.1871582905
Short name T854
Test name
Test status
Simulation time 199181983 ps
CPU time 0.91 seconds
Started Jun 23 05:23:01 PM PDT 24
Finished Jun 23 05:23:02 PM PDT 24
Peak memory 206064 kb
Host smart-28a2227c-a138-4fd8-878e-46d5760e6093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18715
82905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.1871582905
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.4010249675
Short name T2190
Test name
Test status
Simulation time 170160080 ps
CPU time 0.85 seconds
Started Jun 23 05:23:02 PM PDT 24
Finished Jun 23 05:23:04 PM PDT 24
Peak memory 206124 kb
Host smart-fb3c1e20-6ab3-4257-bfec-9448d7b2d792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40102
49675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.4010249675
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.731901195
Short name T1930
Test name
Test status
Simulation time 203914984 ps
CPU time 0.87 seconds
Started Jun 23 05:23:00 PM PDT 24
Finished Jun 23 05:23:02 PM PDT 24
Peak memory 206104 kb
Host smart-5bc24567-ebfb-461c-ac62-749a612c494a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73190
1195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.731901195
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.3020117768
Short name T143
Test name
Test status
Simulation time 145815103 ps
CPU time 0.75 seconds
Started Jun 23 05:23:07 PM PDT 24
Finished Jun 23 05:23:09 PM PDT 24
Peak memory 206096 kb
Host smart-69cbae15-822f-4292-bdfb-4e2591d0b9b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30201
17768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.3020117768
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.552523182
Short name T1044
Test name
Test status
Simulation time 155057697 ps
CPU time 0.89 seconds
Started Jun 23 05:23:01 PM PDT 24
Finished Jun 23 05:23:03 PM PDT 24
Peak memory 206116 kb
Host smart-730ae8f7-be3b-427e-8089-84128d55b050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55252
3182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.552523182
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.2733148434
Short name T2126
Test name
Test status
Simulation time 186511363 ps
CPU time 0.85 seconds
Started Jun 23 05:22:59 PM PDT 24
Finished Jun 23 05:23:01 PM PDT 24
Peak memory 206108 kb
Host smart-dc485604-0fd9-4379-8d7c-c9aee666bad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27331
48434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2733148434
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.2424733133
Short name T2065
Test name
Test status
Simulation time 9729103323 ps
CPU time 71.22 seconds
Started Jun 23 05:23:03 PM PDT 24
Finished Jun 23 05:24:15 PM PDT 24
Peak memory 206416 kb
Host smart-f9c99826-b42b-4993-a232-778ce2f35e5c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2424733133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.2424733133
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1051942123
Short name T1215
Test name
Test status
Simulation time 199066645 ps
CPU time 0.82 seconds
Started Jun 23 05:23:04 PM PDT 24
Finished Jun 23 05:23:05 PM PDT 24
Peak memory 206040 kb
Host smart-452f209f-64b2-4b8f-bbfd-f6dad043d478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10519
42123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1051942123
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.4874626
Short name T432
Test name
Test status
Simulation time 160020446 ps
CPU time 0.79 seconds
Started Jun 23 05:23:02 PM PDT 24
Finished Jun 23 05:23:03 PM PDT 24
Peak memory 206108 kb
Host smart-c853075f-28e7-4b13-99c6-1eaf897e23a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48746
26 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.4874626
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.3464722971
Short name T302
Test name
Test status
Simulation time 13886690639 ps
CPU time 134.88 seconds
Started Jun 23 05:23:04 PM PDT 24
Finished Jun 23 05:25:20 PM PDT 24
Peak memory 206344 kb
Host smart-f3355dfa-d8e2-45ba-869a-521ccc2b9602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34647
22971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.3464722971
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.4050678616
Short name T2082
Test name
Test status
Simulation time 3474599744 ps
CPU time 3.93 seconds
Started Jun 23 05:15:48 PM PDT 24
Finished Jun 23 05:15:52 PM PDT 24
Peak memory 206092 kb
Host smart-588af4ef-5f2f-4a97-b6db-037a9248db10
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4050678616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.4050678616
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2971828989
Short name T1719
Test name
Test status
Simulation time 13351732323 ps
CPU time 11.41 seconds
Started Jun 23 05:15:50 PM PDT 24
Finished Jun 23 05:16:02 PM PDT 24
Peak memory 206400 kb
Host smart-00ce263d-c492-40b8-acb7-6de6ac9780f3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2971828989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2971828989
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.1979293420
Short name T1483
Test name
Test status
Simulation time 23337877485 ps
CPU time 24.77 seconds
Started Jun 23 05:15:50 PM PDT 24
Finished Jun 23 05:16:16 PM PDT 24
Peak memory 206092 kb
Host smart-316625c3-9cfb-4e94-9d24-14467624e96d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1979293420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.1979293420
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2005011169
Short name T2289
Test name
Test status
Simulation time 171031565 ps
CPU time 0.81 seconds
Started Jun 23 05:15:50 PM PDT 24
Finished Jun 23 05:15:52 PM PDT 24
Peak memory 206032 kb
Host smart-4fd9d36a-0949-41c5-b2fa-12f019838d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20050
11169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2005011169
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.1842785769
Short name T2132
Test name
Test status
Simulation time 173697639 ps
CPU time 0.87 seconds
Started Jun 23 05:15:49 PM PDT 24
Finished Jun 23 05:15:51 PM PDT 24
Peak memory 206120 kb
Host smart-6d39d689-ff3c-4bd7-ad65-1bf0ecb46bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18427
85769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.1842785769
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.3438021071
Short name T829
Test name
Test status
Simulation time 455359448 ps
CPU time 1.44 seconds
Started Jun 23 05:15:50 PM PDT 24
Finished Jun 23 05:15:52 PM PDT 24
Peak memory 206104 kb
Host smart-f379b081-5bc2-4fa3-915f-caaeac86d696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34380
21071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.3438021071
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1496371629
Short name T1547
Test name
Test status
Simulation time 1457722176 ps
CPU time 3.08 seconds
Started Jun 23 05:15:49 PM PDT 24
Finished Jun 23 05:15:52 PM PDT 24
Peak memory 206312 kb
Host smart-3ecf099c-df79-418c-9c50-97c84b2d93ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14963
71629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1496371629
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.3074198662
Short name T2245
Test name
Test status
Simulation time 15991469356 ps
CPU time 30.49 seconds
Started Jun 23 05:15:52 PM PDT 24
Finished Jun 23 05:16:24 PM PDT 24
Peak memory 206312 kb
Host smart-7154b373-49e3-4f64-a7e5-dd9f729c0b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30741
98662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.3074198662
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3109913121
Short name T1098
Test name
Test status
Simulation time 365813368 ps
CPU time 1.21 seconds
Started Jun 23 05:15:55 PM PDT 24
Finished Jun 23 05:15:57 PM PDT 24
Peak memory 205996 kb
Host smart-87a90f16-cddd-454f-a835-2a0ed9f0551a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31099
13121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3109913121
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1890820371
Short name T2490
Test name
Test status
Simulation time 155560113 ps
CPU time 0.82 seconds
Started Jun 23 05:15:54 PM PDT 24
Finished Jun 23 05:15:55 PM PDT 24
Peak memory 206104 kb
Host smart-794a296c-709b-45fe-ab3f-bae886db0400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18908
20371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1890820371
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.657786451
Short name T786
Test name
Test status
Simulation time 50284680 ps
CPU time 0.71 seconds
Started Jun 23 05:15:54 PM PDT 24
Finished Jun 23 05:15:56 PM PDT 24
Peak memory 206152 kb
Host smart-4e0c9141-9f4b-4d44-bf56-0b1ca6cd3d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65778
6451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.657786451
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.1756092509
Short name T17
Test name
Test status
Simulation time 898282274 ps
CPU time 2.2 seconds
Started Jun 23 05:15:54 PM PDT 24
Finished Jun 23 05:15:57 PM PDT 24
Peak memory 206244 kb
Host smart-0c15c206-7f0d-49be-be94-20f3f6cef3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17560
92509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1756092509
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1772055363
Short name T2340
Test name
Test status
Simulation time 167086777 ps
CPU time 1.76 seconds
Started Jun 23 05:15:52 PM PDT 24
Finished Jun 23 05:15:55 PM PDT 24
Peak memory 206352 kb
Host smart-4403736a-5257-448b-bd2a-de705cf542ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17720
55363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1772055363
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.999750776
Short name T1485
Test name
Test status
Simulation time 239461701 ps
CPU time 0.98 seconds
Started Jun 23 05:16:05 PM PDT 24
Finished Jun 23 05:16:06 PM PDT 24
Peak memory 206108 kb
Host smart-75e2e9ef-8137-4ac3-9f55-907f0e371a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99975
0776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.999750776
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1344975986
Short name T405
Test name
Test status
Simulation time 142103945 ps
CPU time 0.82 seconds
Started Jun 23 05:16:15 PM PDT 24
Finished Jun 23 05:16:17 PM PDT 24
Peak memory 206032 kb
Host smart-f1dbb4ba-dd60-4611-8080-ee4d7ee1e888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13449
75986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1344975986
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2569400677
Short name T1177
Test name
Test status
Simulation time 187735947 ps
CPU time 0.89 seconds
Started Jun 23 05:15:53 PM PDT 24
Finished Jun 23 05:15:54 PM PDT 24
Peak memory 206104 kb
Host smart-04381d82-3e38-478d-b682-d55e52b98ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25694
00677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2569400677
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.153762485
Short name T2137
Test name
Test status
Simulation time 203546496 ps
CPU time 0.85 seconds
Started Jun 23 05:15:54 PM PDT 24
Finished Jun 23 05:15:55 PM PDT 24
Peak memory 206108 kb
Host smart-267a8bdb-e2b8-4609-ba09-a0b92300c491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15376
2485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.153762485
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.1359627059
Short name T2189
Test name
Test status
Simulation time 23326052346 ps
CPU time 21.24 seconds
Started Jun 23 05:15:54 PM PDT 24
Finished Jun 23 05:16:16 PM PDT 24
Peak memory 206084 kb
Host smart-f2e155de-eb4a-4fce-a859-e82234d62543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13596
27059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.1359627059
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1559738006
Short name T2006
Test name
Test status
Simulation time 3274267224 ps
CPU time 3.6 seconds
Started Jun 23 05:15:52 PM PDT 24
Finished Jun 23 05:15:56 PM PDT 24
Peak memory 206168 kb
Host smart-19cfbb7d-8e9d-4753-8cfa-afd99c90f423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15597
38006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1559738006
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.1771512193
Short name T2007
Test name
Test status
Simulation time 4750645751 ps
CPU time 128.88 seconds
Started Jun 23 05:15:57 PM PDT 24
Finished Jun 23 05:18:07 PM PDT 24
Peak memory 206352 kb
Host smart-15f76d3a-963f-4ae5-bbf9-664cccf3f77e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1771512193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.1771512193
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2547360774
Short name T1840
Test name
Test status
Simulation time 264230546 ps
CPU time 0.99 seconds
Started Jun 23 05:16:03 PM PDT 24
Finished Jun 23 05:16:04 PM PDT 24
Peak memory 206092 kb
Host smart-739d78a2-dfaa-47e9-a15b-700c61e25927
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2547360774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2547360774
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.15073502
Short name T1426
Test name
Test status
Simulation time 212396924 ps
CPU time 0.89 seconds
Started Jun 23 05:15:53 PM PDT 24
Finished Jun 23 05:15:54 PM PDT 24
Peak memory 206128 kb
Host smart-40429421-e90f-4515-9fa6-083443a69b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15073
502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.15073502
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.886522589
Short name T2244
Test name
Test status
Simulation time 13071021888 ps
CPU time 374.85 seconds
Started Jun 23 05:15:55 PM PDT 24
Finished Jun 23 05:22:10 PM PDT 24
Peak memory 206312 kb
Host smart-bd409bcb-c741-428a-9a0f-5b671948d5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88652
2589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.886522589
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.492922224
Short name T1470
Test name
Test status
Simulation time 13563141478 ps
CPU time 101.8 seconds
Started Jun 23 05:16:03 PM PDT 24
Finished Jun 23 05:17:45 PM PDT 24
Peak memory 206412 kb
Host smart-c01fa890-eb7c-4f18-8229-c988f67a2ce4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=492922224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.492922224
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.255106876
Short name T1568
Test name
Test status
Simulation time 155578718 ps
CPU time 0.8 seconds
Started Jun 23 05:16:02 PM PDT 24
Finished Jun 23 05:16:04 PM PDT 24
Peak memory 206104 kb
Host smart-a99049b4-f931-488a-81f8-c5b0b4be9c53
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=255106876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.255106876
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.232608417
Short name T675
Test name
Test status
Simulation time 161093983 ps
CPU time 0.83 seconds
Started Jun 23 05:15:53 PM PDT 24
Finished Jun 23 05:15:55 PM PDT 24
Peak memory 206128 kb
Host smart-43bdeff2-d61e-43dc-88f7-be87c540ad40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23260
8417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.232608417
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1885781554
Short name T2024
Test name
Test status
Simulation time 166926020 ps
CPU time 0.81 seconds
Started Jun 23 05:16:00 PM PDT 24
Finished Jun 23 05:16:01 PM PDT 24
Peak memory 206052 kb
Host smart-b206f182-bdaf-4db9-bfdc-269c9d012928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18857
81554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1885781554
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.3797654455
Short name T1350
Test name
Test status
Simulation time 204990699 ps
CPU time 0.81 seconds
Started Jun 23 05:16:04 PM PDT 24
Finished Jun 23 05:16:05 PM PDT 24
Peak memory 206092 kb
Host smart-16acfda4-b94b-40ea-b3c5-f77b2ef0f81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37976
54455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.3797654455
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.261364180
Short name T942
Test name
Test status
Simulation time 164988147 ps
CPU time 0.84 seconds
Started Jun 23 05:16:03 PM PDT 24
Finished Jun 23 05:16:05 PM PDT 24
Peak memory 206092 kb
Host smart-8ae546b3-172e-4cde-b9e6-0dacd65726bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26136
4180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.261364180
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2898609368
Short name T1794
Test name
Test status
Simulation time 179364273 ps
CPU time 0.82 seconds
Started Jun 23 05:15:57 PM PDT 24
Finished Jun 23 05:15:58 PM PDT 24
Peak memory 206096 kb
Host smart-3e51c696-33ff-42e8-ba47-fa0481989509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28986
09368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2898609368
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3268693541
Short name T3
Test name
Test status
Simulation time 164575667 ps
CPU time 0.81 seconds
Started Jun 23 05:15:57 PM PDT 24
Finished Jun 23 05:15:58 PM PDT 24
Peak memory 206032 kb
Host smart-0a42d4ed-93db-414e-9fe1-3bd327de4846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32686
93541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3268693541
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.3418429008
Short name T1652
Test name
Test status
Simulation time 212511700 ps
CPU time 0.91 seconds
Started Jun 23 05:15:59 PM PDT 24
Finished Jun 23 05:16:00 PM PDT 24
Peak memory 206096 kb
Host smart-4bc82c2d-8a13-42b4-aa9a-8b2e83014ad7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3418429008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.3418429008
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2818009271
Short name T1787
Test name
Test status
Simulation time 137941294 ps
CPU time 0.73 seconds
Started Jun 23 05:16:00 PM PDT 24
Finished Jun 23 05:16:01 PM PDT 24
Peak memory 206068 kb
Host smart-b7c8aff3-3167-45c9-b3b0-ff6624273354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28180
09271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2818009271
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2244118590
Short name T659
Test name
Test status
Simulation time 86913235 ps
CPU time 0.68 seconds
Started Jun 23 05:15:58 PM PDT 24
Finished Jun 23 05:15:59 PM PDT 24
Peak memory 206128 kb
Host smart-80d8eba7-66b7-4d02-b741-84755366951a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22441
18590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2244118590
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2219212258
Short name T2264
Test name
Test status
Simulation time 12083215144 ps
CPU time 28.79 seconds
Started Jun 23 05:15:56 PM PDT 24
Finished Jun 23 05:16:25 PM PDT 24
Peak memory 206356 kb
Host smart-b95df6a1-dec9-42a3-99dd-057296b9821d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22192
12258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2219212258
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2836768084
Short name T590
Test name
Test status
Simulation time 197837257 ps
CPU time 0.85 seconds
Started Jun 23 05:16:00 PM PDT 24
Finished Jun 23 05:16:02 PM PDT 24
Peak memory 206056 kb
Host smart-638511a0-cb13-4e1b-a500-f6ee64a3d5ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28367
68084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2836768084
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.4270583163
Short name T1959
Test name
Test status
Simulation time 194655180 ps
CPU time 0.81 seconds
Started Jun 23 05:15:58 PM PDT 24
Finished Jun 23 05:15:59 PM PDT 24
Peak memory 206124 kb
Host smart-e8708cfc-5f88-437c-845e-7e20145f0287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42705
83163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.4270583163
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2993684846
Short name T1294
Test name
Test status
Simulation time 12597016326 ps
CPU time 82.66 seconds
Started Jun 23 05:16:04 PM PDT 24
Finished Jun 23 05:17:27 PM PDT 24
Peak memory 206440 kb
Host smart-399ecf5e-c5b2-4d16-8d64-e4d0c4aa1124
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2993684846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2993684846
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.3610925323
Short name T152
Test name
Test status
Simulation time 29207028884 ps
CPU time 248.5 seconds
Started Jun 23 05:15:59 PM PDT 24
Finished Jun 23 05:20:08 PM PDT 24
Peak memory 206416 kb
Host smart-5befcb33-0a28-4c7b-a8f8-8a12e03360f5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3610925323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.3610925323
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.3932665983
Short name T1007
Test name
Test status
Simulation time 17847200357 ps
CPU time 135.11 seconds
Started Jun 23 05:16:02 PM PDT 24
Finished Jun 23 05:18:17 PM PDT 24
Peak memory 206400 kb
Host smart-c50cb112-310c-470f-928d-294b4bd253be
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3932665983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3932665983
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.3224219114
Short name T1055
Test name
Test status
Simulation time 241276509 ps
CPU time 0.93 seconds
Started Jun 23 05:16:02 PM PDT 24
Finished Jun 23 05:16:03 PM PDT 24
Peak memory 206108 kb
Host smart-987a7b63-5784-4128-9861-35d659d1f162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32242
19114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.3224219114
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.690656289
Short name T1687
Test name
Test status
Simulation time 178179310 ps
CPU time 0.86 seconds
Started Jun 23 05:15:59 PM PDT 24
Finished Jun 23 05:16:00 PM PDT 24
Peak memory 206168 kb
Host smart-712ca2a8-41e3-4491-affb-864e1e54cb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69065
6289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.690656289
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.443555699
Short name T1545
Test name
Test status
Simulation time 158753095 ps
CPU time 0.82 seconds
Started Jun 23 05:16:00 PM PDT 24
Finished Jun 23 05:16:02 PM PDT 24
Peak memory 206000 kb
Host smart-059ea8e4-adeb-4b28-b70c-a0bbaed38730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44355
5699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.443555699
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3186362633
Short name T649
Test name
Test status
Simulation time 182441545 ps
CPU time 0.87 seconds
Started Jun 23 05:15:59 PM PDT 24
Finished Jun 23 05:16:00 PM PDT 24
Peak memory 206052 kb
Host smart-d6aa6cc7-1425-46bc-bd6a-3dc4e759c489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31863
62633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3186362633
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.642190794
Short name T1274
Test name
Test status
Simulation time 208980872 ps
CPU time 0.85 seconds
Started Jun 23 05:16:03 PM PDT 24
Finished Jun 23 05:16:04 PM PDT 24
Peak memory 206108 kb
Host smart-fa48853d-9aa5-422b-9297-f89d694d2916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64219
0794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.642190794
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1389033505
Short name T1799
Test name
Test status
Simulation time 246422285 ps
CPU time 0.96 seconds
Started Jun 23 05:15:51 PM PDT 24
Finished Jun 23 05:15:52 PM PDT 24
Peak memory 206004 kb
Host smart-a9fe13e2-b483-403c-94f0-1aacc5d960f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13890
33505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1389033505
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.4245202963
Short name T2118
Test name
Test status
Simulation time 5603629822 ps
CPU time 157.98 seconds
Started Jun 23 05:15:58 PM PDT 24
Finished Jun 23 05:18:36 PM PDT 24
Peak memory 206332 kb
Host smart-389609ca-fd08-4ebc-9fb7-554c06ca2f8d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4245202963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.4245202963
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3293658795
Short name T881
Test name
Test status
Simulation time 153656577 ps
CPU time 0.81 seconds
Started Jun 23 05:16:01 PM PDT 24
Finished Jun 23 05:16:02 PM PDT 24
Peak memory 206080 kb
Host smart-4bae180a-0172-4f83-ade2-e845a2fa49dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32936
58795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3293658795
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2416281514
Short name T1449
Test name
Test status
Simulation time 236505666 ps
CPU time 0.88 seconds
Started Jun 23 05:15:58 PM PDT 24
Finished Jun 23 05:15:59 PM PDT 24
Peak memory 206092 kb
Host smart-06b1261d-87b4-4a2a-a13a-59cba0b2d649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24162
81514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2416281514
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.1351674741
Short name T2168
Test name
Test status
Simulation time 3609657171 ps
CPU time 32.83 seconds
Started Jun 23 05:15:59 PM PDT 24
Finished Jun 23 05:16:32 PM PDT 24
Peak memory 206328 kb
Host smart-22f452b8-859b-4de3-9c5e-a527dcf8865d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13516
74741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.1351674741
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3675656325
Short name T16
Test name
Test status
Simulation time 3842178132 ps
CPU time 4.41 seconds
Started Jun 23 05:16:03 PM PDT 24
Finished Jun 23 05:16:08 PM PDT 24
Peak memory 206372 kb
Host smart-2da6f126-dbff-4308-a160-7513b0399243
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3675656325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.3675656325
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.1719846
Short name T2297
Test name
Test status
Simulation time 13388780720 ps
CPU time 12.12 seconds
Started Jun 23 05:16:06 PM PDT 24
Finished Jun 23 05:16:18 PM PDT 24
Peak memory 206144 kb
Host smart-981ebad6-ca37-47f2-ad00-c77d3fb87065
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1719846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.1719846
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.2395888877
Short name T13
Test name
Test status
Simulation time 23345427904 ps
CPU time 24.6 seconds
Started Jun 23 05:16:02 PM PDT 24
Finished Jun 23 05:16:27 PM PDT 24
Peak memory 206160 kb
Host smart-5bdf5cdf-3cb6-4fd8-91ab-0c6d3cd6d568
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2395888877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.2395888877
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.3078565832
Short name T545
Test name
Test status
Simulation time 157525413 ps
CPU time 0.81 seconds
Started Jun 23 05:16:04 PM PDT 24
Finished Jun 23 05:16:05 PM PDT 24
Peak memory 206100 kb
Host smart-a74878b6-02b6-4924-81ce-796c7753ad6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30785
65832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3078565832
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.3225311250
Short name T1082
Test name
Test status
Simulation time 143666519 ps
CPU time 0.82 seconds
Started Jun 23 05:16:18 PM PDT 24
Finished Jun 23 05:16:19 PM PDT 24
Peak memory 206064 kb
Host smart-d22a4848-e7ef-41f5-b7e0-0692e28ffd95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32253
11250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.3225311250
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.3608625579
Short name T1896
Test name
Test status
Simulation time 269184706 ps
CPU time 0.97 seconds
Started Jun 23 05:16:10 PM PDT 24
Finished Jun 23 05:16:11 PM PDT 24
Peak memory 206104 kb
Host smart-c0265de2-3ead-40b5-9a19-ab4943bfa3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36086
25579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.3608625579
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3966600662
Short name T164
Test name
Test status
Simulation time 730343072 ps
CPU time 1.83 seconds
Started Jun 23 05:16:09 PM PDT 24
Finished Jun 23 05:16:12 PM PDT 24
Peak memory 206232 kb
Host smart-bf8488c2-1cf4-4a30-95e2-4ffce07c2111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39666
00662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3966600662
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.3627488742
Short name T484
Test name
Test status
Simulation time 19132902649 ps
CPU time 32.69 seconds
Started Jun 23 05:16:09 PM PDT 24
Finished Jun 23 05:16:42 PM PDT 24
Peak memory 206384 kb
Host smart-b967af67-0bd8-4606-9fac-d94af5e4e1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36274
88742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.3627488742
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.927627144
Short name T758
Test name
Test status
Simulation time 376332267 ps
CPU time 1.16 seconds
Started Jun 23 05:16:07 PM PDT 24
Finished Jun 23 05:16:09 PM PDT 24
Peak memory 206036 kb
Host smart-9d8c3ee1-0edc-442b-8413-c62359e1ed56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92762
7144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.927627144
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.3668890939
Short name T411
Test name
Test status
Simulation time 188058267 ps
CPU time 0.79 seconds
Started Jun 23 05:16:08 PM PDT 24
Finished Jun 23 05:16:09 PM PDT 24
Peak memory 206104 kb
Host smart-cd5a04c2-1fe6-4755-a98e-80daaec6b9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36688
90939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3668890939
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.4116743927
Short name T470
Test name
Test status
Simulation time 53466855 ps
CPU time 0.65 seconds
Started Jun 23 05:16:09 PM PDT 24
Finished Jun 23 05:16:10 PM PDT 24
Peak memory 205980 kb
Host smart-c23ad58b-3436-4ec3-bfa7-4c2cef7d9883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41167
43927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.4116743927
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.2521456695
Short name T1689
Test name
Test status
Simulation time 916764452 ps
CPU time 2.27 seconds
Started Jun 23 05:16:08 PM PDT 24
Finished Jun 23 05:16:11 PM PDT 24
Peak memory 206232 kb
Host smart-110648ff-61a7-4638-a721-520a5ebb6e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25214
56695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.2521456695
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.92452284
Short name T2057
Test name
Test status
Simulation time 305315977 ps
CPU time 1.71 seconds
Started Jun 23 05:16:10 PM PDT 24
Finished Jun 23 05:16:12 PM PDT 24
Peak memory 206364 kb
Host smart-c9c7d86a-4b01-45db-a548-4b38c2c13a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92452
284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.92452284
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2706269099
Short name T2412
Test name
Test status
Simulation time 238279741 ps
CPU time 0.91 seconds
Started Jun 23 05:16:28 PM PDT 24
Finished Jun 23 05:16:30 PM PDT 24
Peak memory 205668 kb
Host smart-f115526b-6113-4fc9-a278-a159ad9643fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27062
69099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2706269099
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3173179361
Short name T2406
Test name
Test status
Simulation time 143581232 ps
CPU time 0.77 seconds
Started Jun 23 05:16:17 PM PDT 24
Finished Jun 23 05:16:19 PM PDT 24
Peak memory 206016 kb
Host smart-0141a361-fdf8-4365-b1b0-f30db38f9486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31731
79361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3173179361
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3521796740
Short name T1116
Test name
Test status
Simulation time 174173544 ps
CPU time 0.8 seconds
Started Jun 23 05:16:09 PM PDT 24
Finished Jun 23 05:16:10 PM PDT 24
Peak memory 206100 kb
Host smart-ee652343-25ad-4179-80a5-c4c3a5c68f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35217
96740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3521796740
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.3764237963
Short name T2414
Test name
Test status
Simulation time 237492487 ps
CPU time 0.91 seconds
Started Jun 23 05:16:09 PM PDT 24
Finished Jun 23 05:16:11 PM PDT 24
Peak memory 206092 kb
Host smart-461d35f1-b627-4a3e-ba73-dda4ec69c4c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37642
37963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.3764237963
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.2879750599
Short name T1035
Test name
Test status
Simulation time 23390054152 ps
CPU time 23.11 seconds
Started Jun 23 05:16:08 PM PDT 24
Finished Jun 23 05:16:32 PM PDT 24
Peak memory 206156 kb
Host smart-3d0ad27f-73c1-4f56-aae2-264a65c3505f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28797
50599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.2879750599
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.1766481814
Short name T1897
Test name
Test status
Simulation time 3320250154 ps
CPU time 3.48 seconds
Started Jun 23 05:16:08 PM PDT 24
Finished Jun 23 05:16:11 PM PDT 24
Peak memory 206112 kb
Host smart-3d635b0b-aaf1-4314-b9a6-7ce8d10df28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17664
81814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.1766481814
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.4113584238
Short name T1837
Test name
Test status
Simulation time 5640844754 ps
CPU time 161.32 seconds
Started Jun 23 05:16:11 PM PDT 24
Finished Jun 23 05:18:52 PM PDT 24
Peak memory 206288 kb
Host smart-84eb694b-70c0-4057-a9d5-e48ca6c72750
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4113584238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.4113584238
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.1709255381
Short name T463
Test name
Test status
Simulation time 239294520 ps
CPU time 0.93 seconds
Started Jun 23 05:16:21 PM PDT 24
Finished Jun 23 05:16:22 PM PDT 24
Peak memory 206048 kb
Host smart-21cd4bd6-20d5-49fb-8eac-713d4687d8a5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1709255381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.1709255381
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1832358191
Short name T1085
Test name
Test status
Simulation time 191193033 ps
CPU time 0.9 seconds
Started Jun 23 05:16:08 PM PDT 24
Finished Jun 23 05:16:10 PM PDT 24
Peak memory 206080 kb
Host smart-bc2aa815-8da7-4b36-b5c0-0bec80eabd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18323
58191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1832358191
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.3209165963
Short name T1865
Test name
Test status
Simulation time 8912558599 ps
CPU time 258.24 seconds
Started Jun 23 05:16:11 PM PDT 24
Finished Jun 23 05:20:30 PM PDT 24
Peak memory 206268 kb
Host smart-ce0ed5e4-d57f-4e66-aa71-c6173c879843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32091
65963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.3209165963
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.1694317976
Short name T1550
Test name
Test status
Simulation time 14574595329 ps
CPU time 426.95 seconds
Started Jun 23 05:16:10 PM PDT 24
Finished Jun 23 05:23:17 PM PDT 24
Peak memory 206500 kb
Host smart-44f25faa-7ea8-43ea-a952-60a8eca8b9e9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1694317976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.1694317976
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.2979148492
Short name T1906
Test name
Test status
Simulation time 167031906 ps
CPU time 0.86 seconds
Started Jun 23 05:16:21 PM PDT 24
Finished Jun 23 05:16:22 PM PDT 24
Peak memory 206128 kb
Host smart-5834612c-d150-4ea2-8d4f-30dba0797bd4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2979148492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2979148492
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.672860583
Short name T2350
Test name
Test status
Simulation time 134657134 ps
CPU time 0.76 seconds
Started Jun 23 05:16:09 PM PDT 24
Finished Jun 23 05:16:10 PM PDT 24
Peak memory 206128 kb
Host smart-cb28a942-dbea-4f36-97fc-abe87cc0096b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67286
0583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.672860583
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1154898359
Short name T124
Test name
Test status
Simulation time 205513357 ps
CPU time 0.89 seconds
Started Jun 23 05:16:18 PM PDT 24
Finished Jun 23 05:16:20 PM PDT 24
Peak memory 205992 kb
Host smart-d4f7167e-2821-4d87-9ec3-41c8d50cd676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11548
98359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1154898359
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1699663934
Short name T1608
Test name
Test status
Simulation time 157123005 ps
CPU time 0.82 seconds
Started Jun 23 05:16:18 PM PDT 24
Finished Jun 23 05:16:19 PM PDT 24
Peak memory 206100 kb
Host smart-9b9a8012-865d-4c64-92f6-ea5d9a2c5027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16996
63934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1699663934
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2680281236
Short name T958
Test name
Test status
Simulation time 175049828 ps
CPU time 0.81 seconds
Started Jun 23 05:16:18 PM PDT 24
Finished Jun 23 05:16:20 PM PDT 24
Peak memory 206108 kb
Host smart-7bc368b9-4e3e-42e1-9c15-372510a4a03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26802
81236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2680281236
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1454074741
Short name T1613
Test name
Test status
Simulation time 165017406 ps
CPU time 0.82 seconds
Started Jun 23 05:16:19 PM PDT 24
Finished Jun 23 05:16:20 PM PDT 24
Peak memory 206068 kb
Host smart-4e32d33f-ad67-4603-bca4-222689e7cb0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14540
74741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1454074741
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.1836499776
Short name T1884
Test name
Test status
Simulation time 155208825 ps
CPU time 0.79 seconds
Started Jun 23 05:16:20 PM PDT 24
Finished Jun 23 05:16:21 PM PDT 24
Peak memory 206092 kb
Host smart-fa71046c-1092-4e1b-939a-a8a2ab32b68e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18364
99776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.1836499776
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.3010724670
Short name T1662
Test name
Test status
Simulation time 199553573 ps
CPU time 0.86 seconds
Started Jun 23 05:16:14 PM PDT 24
Finished Jun 23 05:16:15 PM PDT 24
Peak memory 206064 kb
Host smart-e7994cbb-fdca-44c1-bced-517560bcfc78
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3010724670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.3010724670
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3155024141
Short name T1901
Test name
Test status
Simulation time 206368362 ps
CPU time 0.8 seconds
Started Jun 23 05:16:27 PM PDT 24
Finished Jun 23 05:16:28 PM PDT 24
Peak memory 206128 kb
Host smart-a55f3e6a-ce55-4b01-82c2-b926582e5882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31550
24141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3155024141
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.952236190
Short name T2314
Test name
Test status
Simulation time 38754503 ps
CPU time 0.69 seconds
Started Jun 23 05:16:29 PM PDT 24
Finished Jun 23 05:16:30 PM PDT 24
Peak memory 206116 kb
Host smart-14557232-bb78-4349-9740-39c993a65644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95223
6190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.952236190
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.798191459
Short name T818
Test name
Test status
Simulation time 8239517080 ps
CPU time 18.23 seconds
Started Jun 23 05:16:12 PM PDT 24
Finished Jun 23 05:16:31 PM PDT 24
Peak memory 206428 kb
Host smart-9b81c68b-d1b8-4748-9fc2-597dcc7713eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79819
1459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.798191459
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1503255782
Short name T384
Test name
Test status
Simulation time 168300571 ps
CPU time 0.84 seconds
Started Jun 23 05:16:19 PM PDT 24
Finished Jun 23 05:16:21 PM PDT 24
Peak memory 206100 kb
Host smart-a1bf98cf-d41f-4535-b950-5eec8e3579c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15032
55782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1503255782
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1491512137
Short name T690
Test name
Test status
Simulation time 205683217 ps
CPU time 0.91 seconds
Started Jun 23 05:16:19 PM PDT 24
Finished Jun 23 05:16:20 PM PDT 24
Peak memory 206124 kb
Host smart-a0557031-9ac3-404f-9413-7e8085e7c7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14915
12137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1491512137
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.953428847
Short name T487
Test name
Test status
Simulation time 7748840317 ps
CPU time 106.27 seconds
Started Jun 23 05:16:17 PM PDT 24
Finished Jun 23 05:18:03 PM PDT 24
Peak memory 206444 kb
Host smart-12bccc30-594a-4111-8e7f-ec9db8f36b4f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=953428847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.953428847
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.1200345363
Short name T1636
Test name
Test status
Simulation time 24446314756 ps
CPU time 197.8 seconds
Started Jun 23 05:16:21 PM PDT 24
Finished Jun 23 05:19:39 PM PDT 24
Peak memory 206616 kb
Host smart-0109736e-b5bb-400a-ac22-7ba37a0cfd42
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1200345363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.1200345363
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.1837896527
Short name T819
Test name
Test status
Simulation time 7873602940 ps
CPU time 120.2 seconds
Started Jun 23 05:16:17 PM PDT 24
Finished Jun 23 05:18:18 PM PDT 24
Peak memory 206392 kb
Host smart-10bc8c9f-64b7-4915-ad89-f19f2d22839e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1837896527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.1837896527
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.673275664
Short name T427
Test name
Test status
Simulation time 209776796 ps
CPU time 0.88 seconds
Started Jun 23 05:16:28 PM PDT 24
Finished Jun 23 05:16:30 PM PDT 24
Peak memory 205724 kb
Host smart-1366c65a-9ef3-450e-94c0-a1c5e5e14848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67327
5664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.673275664
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.3400586797
Short name T2316
Test name
Test status
Simulation time 157008894 ps
CPU time 0.78 seconds
Started Jun 23 05:16:14 PM PDT 24
Finished Jun 23 05:16:15 PM PDT 24
Peak memory 206060 kb
Host smart-755e1a89-6c04-404f-b08e-df566dd7755c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34005
86797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.3400586797
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.1425064724
Short name T832
Test name
Test status
Simulation time 192513558 ps
CPU time 0.78 seconds
Started Jun 23 05:16:13 PM PDT 24
Finished Jun 23 05:16:14 PM PDT 24
Peak memory 205992 kb
Host smart-14b03417-f033-4ece-b39d-6da7f0bbf502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14250
64724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1425064724
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.2582428424
Short name T571
Test name
Test status
Simulation time 218842203 ps
CPU time 0.82 seconds
Started Jun 23 05:16:13 PM PDT 24
Finished Jun 23 05:16:15 PM PDT 24
Peak memory 206088 kb
Host smart-87a75ece-9c04-4a70-9c5c-a1346c14faa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25824
28424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.2582428424
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.706979584
Short name T2331
Test name
Test status
Simulation time 147592195 ps
CPU time 0.75 seconds
Started Jun 23 05:16:12 PM PDT 24
Finished Jun 23 05:16:13 PM PDT 24
Peak memory 206056 kb
Host smart-26369435-b5d9-4d5a-a26b-67f6fde84e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70697
9584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.706979584
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.4059924614
Short name T448
Test name
Test status
Simulation time 263589231 ps
CPU time 1.12 seconds
Started Jun 23 05:16:06 PM PDT 24
Finished Jun 23 05:16:07 PM PDT 24
Peak memory 206028 kb
Host smart-96d82927-7a1e-42a2-8702-220811db53a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40599
24614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.4059924614
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.1791262739
Short name T508
Test name
Test status
Simulation time 4954034038 ps
CPU time 127.28 seconds
Started Jun 23 05:16:18 PM PDT 24
Finished Jun 23 05:18:26 PM PDT 24
Peak memory 206360 kb
Host smart-f4600e61-f95b-4798-9fe1-d67809e13618
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1791262739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.1791262739
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.4224118758
Short name T1406
Test name
Test status
Simulation time 178892458 ps
CPU time 0.87 seconds
Started Jun 23 05:16:18 PM PDT 24
Finished Jun 23 05:16:19 PM PDT 24
Peak memory 206108 kb
Host smart-f9f45ee1-3f3e-48de-89f1-ca478bcb9c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42241
18758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.4224118758
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.485660075
Short name T2000
Test name
Test status
Simulation time 164440174 ps
CPU time 0.77 seconds
Started Jun 23 05:16:19 PM PDT 24
Finished Jun 23 05:16:21 PM PDT 24
Peak memory 206260 kb
Host smart-67dfccf5-668e-4fa3-ab23-be605abb738a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48566
0075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.485660075
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3073998811
Short name T1816
Test name
Test status
Simulation time 8444909766 ps
CPU time 77.71 seconds
Started Jun 23 05:16:17 PM PDT 24
Finished Jun 23 05:17:35 PM PDT 24
Peak memory 206296 kb
Host smart-b244341d-6e21-4243-90b4-37d101cc16f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30739
98811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3073998811
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1634582894
Short name T2280
Test name
Test status
Simulation time 3727429838 ps
CPU time 4.08 seconds
Started Jun 23 05:16:19 PM PDT 24
Finished Jun 23 05:16:24 PM PDT 24
Peak memory 206288 kb
Host smart-667235b7-416d-4fc3-bd70-ccbf2f18970a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1634582894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.1634582894
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3280500008
Short name T1674
Test name
Test status
Simulation time 13431768636 ps
CPU time 12.71 seconds
Started Jun 23 05:16:18 PM PDT 24
Finished Jun 23 05:16:32 PM PDT 24
Peak memory 206392 kb
Host smart-5c9e141e-80cc-459c-aada-c2152ad91f0e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3280500008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3280500008
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.1683338584
Short name T582
Test name
Test status
Simulation time 23419268746 ps
CPU time 28.79 seconds
Started Jun 23 05:16:20 PM PDT 24
Finished Jun 23 05:16:49 PM PDT 24
Peak memory 206364 kb
Host smart-8a691f12-54ab-4706-a9dc-a8e50b0646f2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1683338584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.1683338584
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2208693999
Short name T459
Test name
Test status
Simulation time 154620287 ps
CPU time 0.83 seconds
Started Jun 23 05:16:21 PM PDT 24
Finished Jun 23 05:16:22 PM PDT 24
Peak memory 206028 kb
Host smart-405f757e-d5a9-4fa9-91be-860cbb0b7f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22086
93999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2208693999
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.1158334790
Short name T2394
Test name
Test status
Simulation time 171101638 ps
CPU time 0.82 seconds
Started Jun 23 05:16:20 PM PDT 24
Finished Jun 23 05:16:21 PM PDT 24
Peak memory 206108 kb
Host smart-5b716686-7ee2-4c96-8e59-0a29f4933bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11583
34790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.1158334790
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.588904465
Short name T170
Test name
Test status
Simulation time 474569132 ps
CPU time 1.4 seconds
Started Jun 23 05:16:20 PM PDT 24
Finished Jun 23 05:16:22 PM PDT 24
Peak memory 206000 kb
Host smart-533fe5a9-6bdf-4239-b87a-922008338157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58890
4465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.588904465
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.562303470
Short name T160
Test name
Test status
Simulation time 670471055 ps
CPU time 1.81 seconds
Started Jun 23 05:16:28 PM PDT 24
Finished Jun 23 05:16:31 PM PDT 24
Peak memory 206348 kb
Host smart-b039974c-c7e1-43dd-b545-370e38a11772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56230
3470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.562303470
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.1220496265
Short name T1324
Test name
Test status
Simulation time 19222871923 ps
CPU time 39.11 seconds
Started Jun 23 05:16:23 PM PDT 24
Finished Jun 23 05:17:03 PM PDT 24
Peak memory 206324 kb
Host smart-b826ecfb-2389-451f-a03b-fd9450ea0fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12204
96265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.1220496265
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.2389407026
Short name T1923
Test name
Test status
Simulation time 491095417 ps
CPU time 1.31 seconds
Started Jun 23 05:16:23 PM PDT 24
Finished Jun 23 05:16:24 PM PDT 24
Peak memory 206108 kb
Host smart-a0141ac7-23fd-446e-bc38-ba2bdda35731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23894
07026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.2389407026
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.942643697
Short name T1262
Test name
Test status
Simulation time 148658965 ps
CPU time 0.79 seconds
Started Jun 23 05:16:22 PM PDT 24
Finished Jun 23 05:16:23 PM PDT 24
Peak memory 206100 kb
Host smart-38b211dc-9e84-4d71-9dcb-5d11d48c90c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94264
3697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.942643697
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.739507310
Short name T2001
Test name
Test status
Simulation time 34267904 ps
CPU time 0.69 seconds
Started Jun 23 05:16:33 PM PDT 24
Finished Jun 23 05:16:35 PM PDT 24
Peak memory 205988 kb
Host smart-1f60a987-b07e-4fd6-8431-0daba0de4028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73950
7310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.739507310
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.27292297
Short name T1936
Test name
Test status
Simulation time 841512360 ps
CPU time 1.84 seconds
Started Jun 23 05:16:26 PM PDT 24
Finished Jun 23 05:16:28 PM PDT 24
Peak memory 206368 kb
Host smart-90179913-b163-4dea-af86-b6c86c783ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27292
297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.27292297
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.394585446
Short name T653
Test name
Test status
Simulation time 291240097 ps
CPU time 1.53 seconds
Started Jun 23 05:16:25 PM PDT 24
Finished Jun 23 05:16:27 PM PDT 24
Peak memory 206216 kb
Host smart-bee668b0-ea64-4cb9-8aab-8491d133157a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39458
5446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.394585446
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2599266326
Short name T553
Test name
Test status
Simulation time 201349755 ps
CPU time 0.83 seconds
Started Jun 23 05:16:30 PM PDT 24
Finished Jun 23 05:16:31 PM PDT 24
Peak memory 206100 kb
Host smart-0323333a-b646-46e2-abe6-b9cd201011a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25992
66326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2599266326
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.458469730
Short name T450
Test name
Test status
Simulation time 185846766 ps
CPU time 0.81 seconds
Started Jun 23 05:16:32 PM PDT 24
Finished Jun 23 05:16:33 PM PDT 24
Peak memory 206088 kb
Host smart-3dd7e116-8d50-43ce-a465-9a7b51047748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45846
9730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.458469730
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2458766803
Short name T1329
Test name
Test status
Simulation time 201722758 ps
CPU time 0.86 seconds
Started Jun 23 05:16:25 PM PDT 24
Finished Jun 23 05:16:26 PM PDT 24
Peak memory 206108 kb
Host smart-a4646ca6-e9ff-4c5e-96ed-17de9c36e703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24587
66803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2458766803
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.1815598911
Short name T2219
Test name
Test status
Simulation time 5263818691 ps
CPU time 143.55 seconds
Started Jun 23 05:16:25 PM PDT 24
Finished Jun 23 05:18:49 PM PDT 24
Peak memory 206276 kb
Host smart-bf434d4f-5bce-4ace-a581-d56bd42e2c69
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1815598911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.1815598911
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.4103470275
Short name T964
Test name
Test status
Simulation time 233935981 ps
CPU time 0.96 seconds
Started Jun 23 05:16:24 PM PDT 24
Finished Jun 23 05:16:26 PM PDT 24
Peak memory 206100 kb
Host smart-6b9d1cf1-a1cc-4fad-8d80-90aeef058bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41034
70275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.4103470275
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.146398609
Short name T1130
Test name
Test status
Simulation time 23305283111 ps
CPU time 20.62 seconds
Started Jun 23 05:16:24 PM PDT 24
Finished Jun 23 05:16:45 PM PDT 24
Peak memory 206140 kb
Host smart-60d453ba-c61c-4a36-863c-051bb52e8f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14639
8609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.146398609
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1695845324
Short name T821
Test name
Test status
Simulation time 3301985291 ps
CPU time 3.99 seconds
Started Jun 23 05:16:38 PM PDT 24
Finished Jun 23 05:16:42 PM PDT 24
Peak memory 206060 kb
Host smart-b96d1f1e-22ab-4eec-8200-8ef877a4b530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16958
45324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1695845324
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.4031720600
Short name T611
Test name
Test status
Simulation time 5724449369 ps
CPU time 39.51 seconds
Started Jun 23 05:16:23 PM PDT 24
Finished Jun 23 05:17:03 PM PDT 24
Peak memory 206432 kb
Host smart-eede4dda-0375-4b6e-b20b-5586eb61bbd1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4031720600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.4031720600
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.340687844
Short name T1246
Test name
Test status
Simulation time 233141401 ps
CPU time 0.92 seconds
Started Jun 23 05:16:33 PM PDT 24
Finished Jun 23 05:16:35 PM PDT 24
Peak memory 206148 kb
Host smart-1cba9519-15c3-4c6a-a179-03d9f09f505d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=340687844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.340687844
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3554155963
Short name T559
Test name
Test status
Simulation time 189527999 ps
CPU time 0.86 seconds
Started Jun 23 05:16:24 PM PDT 24
Finished Jun 23 05:16:25 PM PDT 24
Peak memory 206080 kb
Host smart-3fb057b2-fb08-44e8-88b0-20751eabf9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35541
55963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3554155963
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.737626648
Short name T1881
Test name
Test status
Simulation time 6655589700 ps
CPU time 48.31 seconds
Started Jun 23 05:16:24 PM PDT 24
Finished Jun 23 05:17:13 PM PDT 24
Peak memory 206360 kb
Host smart-25b7d085-af15-4592-a822-a923da4830e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73762
6648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.737626648
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.2013944148
Short name T1996
Test name
Test status
Simulation time 5190854359 ps
CPU time 137.14 seconds
Started Jun 23 05:16:23 PM PDT 24
Finished Jun 23 05:18:40 PM PDT 24
Peak memory 206492 kb
Host smart-78c18b6a-7ecd-4f10-9b75-65e26b742dd1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2013944148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.2013944148
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.2883371662
Short name T935
Test name
Test status
Simulation time 163315593 ps
CPU time 0.79 seconds
Started Jun 23 05:16:29 PM PDT 24
Finished Jun 23 05:16:31 PM PDT 24
Peak memory 206096 kb
Host smart-843df3e7-b3a2-4dc9-a8e5-2fce20140d1b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2883371662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.2883371662
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.4026885918
Short name T1643
Test name
Test status
Simulation time 165330930 ps
CPU time 0.74 seconds
Started Jun 23 05:16:24 PM PDT 24
Finished Jun 23 05:16:25 PM PDT 24
Peak memory 206120 kb
Host smart-db56b3da-9301-4afb-af5e-01cda947d303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40268
85918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.4026885918
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.75344488
Short name T2239
Test name
Test status
Simulation time 258692056 ps
CPU time 0.91 seconds
Started Jun 23 05:16:22 PM PDT 24
Finished Jun 23 05:16:23 PM PDT 24
Peak memory 206020 kb
Host smart-07eb6fa2-6a77-4459-917b-2fd190d5d5ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75344
488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.75344488
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.510279647
Short name T2195
Test name
Test status
Simulation time 187487728 ps
CPU time 0.83 seconds
Started Jun 23 05:16:34 PM PDT 24
Finished Jun 23 05:16:35 PM PDT 24
Peak memory 205992 kb
Host smart-7715d98f-5d61-4118-bb99-4f0720c4d770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51027
9647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.510279647
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2956153503
Short name T2179
Test name
Test status
Simulation time 207515902 ps
CPU time 0.83 seconds
Started Jun 23 05:16:24 PM PDT 24
Finished Jun 23 05:16:25 PM PDT 24
Peak memory 206108 kb
Host smart-0ec44d54-6fa0-40eb-bf5a-97e7bc9884e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29561
53503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2956153503
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2905162352
Short name T2293
Test name
Test status
Simulation time 183465282 ps
CPU time 0.82 seconds
Started Jun 23 05:16:24 PM PDT 24
Finished Jun 23 05:16:25 PM PDT 24
Peak memory 206048 kb
Host smart-68afc922-d349-4330-aee9-a799a653d120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29051
62352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2905162352
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.547118272
Short name T1519
Test name
Test status
Simulation time 170194103 ps
CPU time 0.83 seconds
Started Jun 23 05:16:31 PM PDT 24
Finished Jun 23 05:16:33 PM PDT 24
Peak memory 205996 kb
Host smart-5cc8c36f-6000-4beb-84e1-c390e31dcb96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54711
8272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.547118272
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.3769615199
Short name T325
Test name
Test status
Simulation time 281800993 ps
CPU time 0.96 seconds
Started Jun 23 05:16:30 PM PDT 24
Finished Jun 23 05:16:31 PM PDT 24
Peak memory 206124 kb
Host smart-02e3395c-9df9-48d6-b31d-0ed574318ac5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3769615199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.3769615199
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2732676332
Short name T1659
Test name
Test status
Simulation time 140225040 ps
CPU time 0.79 seconds
Started Jun 23 05:16:28 PM PDT 24
Finished Jun 23 05:16:29 PM PDT 24
Peak memory 206132 kb
Host smart-1562a7c1-2186-4885-a817-47aa5311ac2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27326
76332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2732676332
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2971321315
Short name T555
Test name
Test status
Simulation time 42798568 ps
CPU time 0.65 seconds
Started Jun 23 05:16:29 PM PDT 24
Finished Jun 23 05:16:30 PM PDT 24
Peak memory 206112 kb
Host smart-ebb4d3f3-41c9-43ef-a9c9-d71b3e3b800d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29713
21315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2971321315
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1185973292
Short name T228
Test name
Test status
Simulation time 23129084570 ps
CPU time 50.79 seconds
Started Jun 23 05:16:22 PM PDT 24
Finished Jun 23 05:17:13 PM PDT 24
Peak memory 206388 kb
Host smart-7a7915be-6710-4b1d-8be1-207949bcfca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11859
73292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1185973292
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2226957007
Short name T1859
Test name
Test status
Simulation time 182161609 ps
CPU time 0.91 seconds
Started Jun 23 05:16:34 PM PDT 24
Finished Jun 23 05:16:35 PM PDT 24
Peak memory 206004 kb
Host smart-80588e6e-f87f-4b24-8c3f-12290d999642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22269
57007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2226957007
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2248867014
Short name T2045
Test name
Test status
Simulation time 157007073 ps
CPU time 0.77 seconds
Started Jun 23 05:16:23 PM PDT 24
Finished Jun 23 05:16:24 PM PDT 24
Peak memory 206060 kb
Host smart-ee27acd8-8289-42b8-8d71-09107c8bd03b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22488
67014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2248867014
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.118229690
Short name T154
Test name
Test status
Simulation time 8084287346 ps
CPU time 118.92 seconds
Started Jun 23 05:16:25 PM PDT 24
Finished Jun 23 05:18:25 PM PDT 24
Peak memory 206340 kb
Host smart-3d3eda13-dd3e-46ba-b4b1-5f4adc05f094
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=118229690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.118229690
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.1061279045
Short name T717
Test name
Test status
Simulation time 19061626532 ps
CPU time 417.19 seconds
Started Jun 23 05:16:25 PM PDT 24
Finished Jun 23 05:23:23 PM PDT 24
Peak memory 206364 kb
Host smart-2436b107-bd40-4e6f-bee4-dc105d713480
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1061279045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.1061279045
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.3419877975
Short name T973
Test name
Test status
Simulation time 17288015890 ps
CPU time 351.73 seconds
Started Jun 23 05:16:33 PM PDT 24
Finished Jun 23 05:22:26 PM PDT 24
Peak memory 206324 kb
Host smart-3dbab3eb-60c5-4ff4-8314-0736383f9224
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3419877975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.3419877975
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.319392650
Short name T2455
Test name
Test status
Simulation time 192204761 ps
CPU time 0.87 seconds
Started Jun 23 05:16:29 PM PDT 24
Finished Jun 23 05:16:31 PM PDT 24
Peak memory 206064 kb
Host smart-89cd0ae2-e411-4e84-b676-93fd8d982c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31939
2650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.319392650
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.3402083233
Short name T2429
Test name
Test status
Simulation time 192838457 ps
CPU time 0.86 seconds
Started Jun 23 05:16:23 PM PDT 24
Finished Jun 23 05:16:25 PM PDT 24
Peak memory 206112 kb
Host smart-5f5484b5-b75d-4832-bdc5-f5362a3b04cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34020
83233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.3402083233
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.190749029
Short name T1030
Test name
Test status
Simulation time 193450911 ps
CPU time 0.86 seconds
Started Jun 23 05:16:28 PM PDT 24
Finished Jun 23 05:16:30 PM PDT 24
Peak memory 206116 kb
Host smart-f31ba7a0-e179-4902-a88f-0bceeaa373ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19074
9029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.190749029
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.21457864
Short name T1987
Test name
Test status
Simulation time 149906858 ps
CPU time 0.76 seconds
Started Jun 23 05:16:29 PM PDT 24
Finished Jun 23 05:16:31 PM PDT 24
Peak memory 206020 kb
Host smart-359123d4-a695-4687-a496-626b42a4d414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21457
864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.21457864
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2374875363
Short name T869
Test name
Test status
Simulation time 152919495 ps
CPU time 0.76 seconds
Started Jun 23 05:16:31 PM PDT 24
Finished Jun 23 05:16:33 PM PDT 24
Peak memory 206040 kb
Host smart-922020d3-2792-4d74-98dc-2229153cfe5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23748
75363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2374875363
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1320409509
Short name T2359
Test name
Test status
Simulation time 218542640 ps
CPU time 0.98 seconds
Started Jun 23 05:16:18 PM PDT 24
Finished Jun 23 05:16:20 PM PDT 24
Peak memory 206124 kb
Host smart-52e9db29-aa27-4bfa-bed7-5c81c14653b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13204
09509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1320409509
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.833860310
Short name T978
Test name
Test status
Simulation time 3401952495 ps
CPU time 34 seconds
Started Jun 23 05:16:22 PM PDT 24
Finished Jun 23 05:16:56 PM PDT 24
Peak memory 206360 kb
Host smart-a3bfc2c6-b8cd-4b3c-8a22-9bb4dfa6b384
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=833860310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.833860310
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1228992024
Short name T399
Test name
Test status
Simulation time 149719319 ps
CPU time 0.74 seconds
Started Jun 23 05:16:29 PM PDT 24
Finished Jun 23 05:16:30 PM PDT 24
Peak memory 206040 kb
Host smart-1287eace-200f-476e-8a13-9301ecce5aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12289
92024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1228992024
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.1532238270
Short name T1501
Test name
Test status
Simulation time 184947440 ps
CPU time 0.82 seconds
Started Jun 23 05:16:25 PM PDT 24
Finished Jun 23 05:16:26 PM PDT 24
Peak memory 206056 kb
Host smart-aaf8b37a-d2c0-468b-a9b8-85010513bd9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15322
38270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.1532238270
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.2617827845
Short name T2092
Test name
Test status
Simulation time 5822354609 ps
CPU time 44.89 seconds
Started Jun 23 05:16:25 PM PDT 24
Finished Jun 23 05:17:11 PM PDT 24
Peak memory 206360 kb
Host smart-efeb9c9e-8a16-4390-bd8c-989387573205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26178
27845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.2617827845
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.1432543688
Short name T408
Test name
Test status
Simulation time 4049319189 ps
CPU time 4.63 seconds
Started Jun 23 05:16:28 PM PDT 24
Finished Jun 23 05:16:33 PM PDT 24
Peak memory 206368 kb
Host smart-c6b52b72-a620-43fb-a78d-708d0a247c7d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1432543688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.1432543688
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.599600305
Short name T1705
Test name
Test status
Simulation time 13412807685 ps
CPU time 12.79 seconds
Started Jun 23 05:16:29 PM PDT 24
Finished Jun 23 05:16:43 PM PDT 24
Peak memory 206164 kb
Host smart-4064073e-6b3a-440b-98b3-d2d87d40f528
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=599600305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.599600305
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2169662910
Short name T1471
Test name
Test status
Simulation time 23355159705 ps
CPU time 21.31 seconds
Started Jun 23 05:16:30 PM PDT 24
Finished Jun 23 05:16:52 PM PDT 24
Peak memory 206316 kb
Host smart-cb6f7595-4b9b-4aac-b74b-664a2b034947
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2169662910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.2169662910
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1920855358
Short name T2441
Test name
Test status
Simulation time 162411231 ps
CPU time 0.84 seconds
Started Jun 23 05:16:29 PM PDT 24
Finished Jun 23 05:16:31 PM PDT 24
Peak memory 206072 kb
Host smart-81316e96-7d55-41a5-8e1d-29138359468e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19208
55358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1920855358
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.2329814193
Short name T1152
Test name
Test status
Simulation time 152501910 ps
CPU time 0.78 seconds
Started Jun 23 05:16:30 PM PDT 24
Finished Jun 23 05:16:31 PM PDT 24
Peak memory 206072 kb
Host smart-dad7ff85-7125-42ed-91bc-7249745e3ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23298
14193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.2329814193
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.968375283
Short name T2483
Test name
Test status
Simulation time 424500369 ps
CPU time 1.45 seconds
Started Jun 23 05:16:31 PM PDT 24
Finished Jun 23 05:16:33 PM PDT 24
Peak memory 205996 kb
Host smart-8e4da760-2c02-482b-9ff6-2d93480c0fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96837
5283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.968375283
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.1950524074
Short name T1194
Test name
Test status
Simulation time 1172620264 ps
CPU time 2.79 seconds
Started Jun 23 05:16:29 PM PDT 24
Finished Jun 23 05:16:32 PM PDT 24
Peak memory 206292 kb
Host smart-f815e707-e516-4281-a8ab-bad5b7ccc96e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19505
24074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.1950524074
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.1872332724
Short name T156
Test name
Test status
Simulation time 12489460070 ps
CPU time 23.96 seconds
Started Jun 23 05:16:31 PM PDT 24
Finished Jun 23 05:16:55 PM PDT 24
Peak memory 206272 kb
Host smart-8da0e6c5-b74b-4ced-aef4-20e2f6d6cbbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18723
32724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.1872332724
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.2156444036
Short name T318
Test name
Test status
Simulation time 333714576 ps
CPU time 1.21 seconds
Started Jun 23 05:16:33 PM PDT 24
Finished Jun 23 05:16:35 PM PDT 24
Peak memory 206108 kb
Host smart-a4ff8194-e6a8-41d3-85a3-06ae1af680f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21564
44036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.2156444036
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.1135453766
Short name T1069
Test name
Test status
Simulation time 140055391 ps
CPU time 0.74 seconds
Started Jun 23 05:16:29 PM PDT 24
Finished Jun 23 05:16:30 PM PDT 24
Peak memory 206032 kb
Host smart-1a00a86d-6d95-4f7f-94f6-a4c852935f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11354
53766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.1135453766
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.2249802171
Short name T710
Test name
Test status
Simulation time 36191372 ps
CPU time 0.67 seconds
Started Jun 23 05:16:37 PM PDT 24
Finished Jun 23 05:16:38 PM PDT 24
Peak memory 206096 kb
Host smart-eb424cee-b7de-4984-9795-9686e0646839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22498
02171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2249802171
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.2746407530
Short name T599
Test name
Test status
Simulation time 822836799 ps
CPU time 1.94 seconds
Started Jun 23 05:16:31 PM PDT 24
Finished Jun 23 05:16:33 PM PDT 24
Peak memory 206360 kb
Host smart-4d2059ad-2096-406d-810c-876e76ff6c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27464
07530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.2746407530
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2203133961
Short name T879
Test name
Test status
Simulation time 212142840 ps
CPU time 1.16 seconds
Started Jun 23 05:16:33 PM PDT 24
Finished Jun 23 05:16:34 PM PDT 24
Peak memory 206228 kb
Host smart-b66a5bdd-95d4-4774-aa59-5a43190ef53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22031
33961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2203133961
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.105370713
Short name T759
Test name
Test status
Simulation time 180355957 ps
CPU time 0.92 seconds
Started Jun 23 05:16:42 PM PDT 24
Finished Jun 23 05:16:44 PM PDT 24
Peak memory 206124 kb
Host smart-eba57b09-c819-460d-b13c-38c5a63e7757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10537
0713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.105370713
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.2476897467
Short name T2139
Test name
Test status
Simulation time 149636207 ps
CPU time 0.77 seconds
Started Jun 23 05:16:41 PM PDT 24
Finished Jun 23 05:16:43 PM PDT 24
Peak memory 206104 kb
Host smart-efb3b6e1-627e-4329-8296-a6b8b52ff245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24768
97467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.2476897467
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3145445810
Short name T1224
Test name
Test status
Simulation time 273184838 ps
CPU time 0.98 seconds
Started Jun 23 05:16:34 PM PDT 24
Finished Jun 23 05:16:35 PM PDT 24
Peak memory 206108 kb
Host smart-cdbcd37a-0240-46d6-b069-ea698e3565ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31454
45810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3145445810
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.2504116465
Short name T65
Test name
Test status
Simulation time 6297540281 ps
CPU time 169.47 seconds
Started Jun 23 05:16:35 PM PDT 24
Finished Jun 23 05:19:24 PM PDT 24
Peak memory 206368 kb
Host smart-1fb99b9a-a79f-4c36-88c9-56ba8527356c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2504116465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.2504116465
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3162498608
Short name T2287
Test name
Test status
Simulation time 196275635 ps
CPU time 0.87 seconds
Started Jun 23 05:16:37 PM PDT 24
Finished Jun 23 05:16:38 PM PDT 24
Peak memory 206020 kb
Host smart-4a369916-6353-436a-899f-d50b589e7b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31624
98608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3162498608
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.3281713760
Short name T452
Test name
Test status
Simulation time 23270168988 ps
CPU time 20.92 seconds
Started Jun 23 05:16:37 PM PDT 24
Finished Jun 23 05:16:58 PM PDT 24
Peak memory 206164 kb
Host smart-c881c8a6-1420-4ad3-bf2e-e85dedb3eed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32817
13760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.3281713760
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.2079007957
Short name T311
Test name
Test status
Simulation time 3331018593 ps
CPU time 4.34 seconds
Started Jun 23 05:16:34 PM PDT 24
Finished Jun 23 05:16:39 PM PDT 24
Peak memory 206164 kb
Host smart-e74ff2c4-15a8-4d4f-8530-0d05b1bbe743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20790
07957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.2079007957
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.4013067752
Short name T1975
Test name
Test status
Simulation time 10685958777 ps
CPU time 294.09 seconds
Started Jun 23 05:16:33 PM PDT 24
Finished Jun 23 05:21:27 PM PDT 24
Peak memory 206352 kb
Host smart-dc6cc7d5-db14-4b64-9714-74395f142792
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4013067752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.4013067752
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.3026041257
Short name T1789
Test name
Test status
Simulation time 276825734 ps
CPU time 0.99 seconds
Started Jun 23 05:16:42 PM PDT 24
Finished Jun 23 05:16:44 PM PDT 24
Peak memory 206128 kb
Host smart-2d2709ad-4063-4ff5-8cf5-d5b07960d940
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3026041257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.3026041257
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1216395110
Short name T2068
Test name
Test status
Simulation time 231033589 ps
CPU time 0.91 seconds
Started Jun 23 05:16:37 PM PDT 24
Finished Jun 23 05:16:39 PM PDT 24
Peak memory 206132 kb
Host smart-c594a96f-7664-4ce3-9c3c-c1acd6d2eefa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12163
95110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1216395110
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.533713007
Short name T1991
Test name
Test status
Simulation time 5297090015 ps
CPU time 48.33 seconds
Started Jun 23 05:16:34 PM PDT 24
Finished Jun 23 05:17:23 PM PDT 24
Peak memory 206356 kb
Host smart-34008ecf-bac3-4a44-b517-7577ccbcd42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53371
3007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.533713007
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.915063505
Short name T2255
Test name
Test status
Simulation time 7199880633 ps
CPU time 51.44 seconds
Started Jun 23 05:16:36 PM PDT 24
Finished Jun 23 05:17:28 PM PDT 24
Peak memory 206440 kb
Host smart-8a9fd8af-b465-473a-801a-150defe47e4e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=915063505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.915063505
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.1493565240
Short name T2183
Test name
Test status
Simulation time 207905828 ps
CPU time 0.82 seconds
Started Jun 23 05:16:40 PM PDT 24
Finished Jun 23 05:16:41 PM PDT 24
Peak memory 206148 kb
Host smart-585c21f0-7129-4144-a112-248132b374ac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1493565240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.1493565240
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3184076353
Short name T1442
Test name
Test status
Simulation time 178720261 ps
CPU time 0.78 seconds
Started Jun 23 05:16:34 PM PDT 24
Finished Jun 23 05:16:35 PM PDT 24
Peak memory 206048 kb
Host smart-a0caea57-6c83-4374-a272-dbbbcaa872c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31840
76353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3184076353
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.4135540546
Short name T137
Test name
Test status
Simulation time 209716708 ps
CPU time 0.92 seconds
Started Jun 23 05:16:33 PM PDT 24
Finished Jun 23 05:16:35 PM PDT 24
Peak memory 206100 kb
Host smart-2e3d48fe-92fb-491e-9f55-27a81952c89a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41355
40546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.4135540546
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.3516965707
Short name T1630
Test name
Test status
Simulation time 147012646 ps
CPU time 0.78 seconds
Started Jun 23 05:16:33 PM PDT 24
Finished Jun 23 05:16:35 PM PDT 24
Peak memory 206100 kb
Host smart-3ab21e80-cdee-44ed-ab01-535a1d967d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35169
65707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.3516965707
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2318837716
Short name T2487
Test name
Test status
Simulation time 216499749 ps
CPU time 0.82 seconds
Started Jun 23 05:16:33 PM PDT 24
Finished Jun 23 05:16:35 PM PDT 24
Peak memory 206260 kb
Host smart-77fe2e30-df1e-4199-bac2-1b119cfb4094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23188
37716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2318837716
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.140986826
Short name T1389
Test name
Test status
Simulation time 166995024 ps
CPU time 0.84 seconds
Started Jun 23 05:16:33 PM PDT 24
Finished Jun 23 05:16:35 PM PDT 24
Peak memory 206024 kb
Host smart-460a120a-7cc4-4da4-8069-20b0ade39cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14098
6826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.140986826
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.817783004
Short name T1012
Test name
Test status
Simulation time 157225105 ps
CPU time 0.81 seconds
Started Jun 23 05:16:40 PM PDT 24
Finished Jun 23 05:16:41 PM PDT 24
Peak memory 206096 kb
Host smart-a064432e-19ab-4051-9a5d-b100c5e3cff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81778
3004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.817783004
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.949177445
Short name T1270
Test name
Test status
Simulation time 247443423 ps
CPU time 0.98 seconds
Started Jun 23 05:16:39 PM PDT 24
Finished Jun 23 05:16:40 PM PDT 24
Peak memory 206096 kb
Host smart-75ca0689-8da0-420a-bd64-8b43bdd7c1c5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=949177445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.949177445
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3221360034
Short name T185
Test name
Test status
Simulation time 160056770 ps
CPU time 0.8 seconds
Started Jun 23 05:16:40 PM PDT 24
Finished Jun 23 05:16:41 PM PDT 24
Peak memory 206048 kb
Host smart-d49196a6-744e-431c-8502-c68836484c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32213
60034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3221360034
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2913530949
Short name T684
Test name
Test status
Simulation time 66464261 ps
CPU time 0.7 seconds
Started Jun 23 05:16:42 PM PDT 24
Finished Jun 23 05:16:43 PM PDT 24
Peak memory 206076 kb
Host smart-500768b8-f6cc-4f68-8f00-41eacbeaaa8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29135
30949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2913530949
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.1110998698
Short name T2365
Test name
Test status
Simulation time 6463262460 ps
CPU time 14.44 seconds
Started Jun 23 05:16:35 PM PDT 24
Finished Jun 23 05:16:50 PM PDT 24
Peak memory 206364 kb
Host smart-0cbbd062-0390-47d2-911f-befaa09fba2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11109
98698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1110998698
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2392644884
Short name T1943
Test name
Test status
Simulation time 150100425 ps
CPU time 0.8 seconds
Started Jun 23 05:16:36 PM PDT 24
Finished Jun 23 05:16:37 PM PDT 24
Peak memory 206104 kb
Host smart-f8c30378-35ea-4a4e-a0d1-efd7e9e1c927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23926
44884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2392644884
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2803722528
Short name T663
Test name
Test status
Simulation time 217741944 ps
CPU time 0.88 seconds
Started Jun 23 05:16:35 PM PDT 24
Finished Jun 23 05:16:36 PM PDT 24
Peak memory 206156 kb
Host smart-430ca074-a277-48a6-9fc0-9404ca11745c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28037
22528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2803722528
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.4253872514
Short name T1277
Test name
Test status
Simulation time 12104506363 ps
CPU time 108.29 seconds
Started Jun 23 05:16:36 PM PDT 24
Finished Jun 23 05:18:24 PM PDT 24
Peak memory 206380 kb
Host smart-907da7f8-7699-40f5-9543-4fa01b885edb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4253872514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.4253872514
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.3583285424
Short name T1811
Test name
Test status
Simulation time 16808636358 ps
CPU time 121.72 seconds
Started Jun 23 05:16:44 PM PDT 24
Finished Jun 23 05:18:46 PM PDT 24
Peak memory 206400 kb
Host smart-7875f5ab-a681-4676-95c2-93140513c311
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3583285424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3583285424
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1517886555
Short name T2408
Test name
Test status
Simulation time 12044955495 ps
CPU time 233.99 seconds
Started Jun 23 05:16:42 PM PDT 24
Finished Jun 23 05:20:37 PM PDT 24
Peak memory 206392 kb
Host smart-22b27785-b221-471d-830a-9c9703305cb9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1517886555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1517886555
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.3547503719
Short name T468
Test name
Test status
Simulation time 189959486 ps
CPU time 0.83 seconds
Started Jun 23 05:16:40 PM PDT 24
Finished Jun 23 05:16:41 PM PDT 24
Peak memory 206108 kb
Host smart-bfd67d27-189c-4eaf-9c97-809850feb48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35475
03719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.3547503719
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.3037762828
Short name T1814
Test name
Test status
Simulation time 223582341 ps
CPU time 0.87 seconds
Started Jun 23 05:16:40 PM PDT 24
Finished Jun 23 05:16:41 PM PDT 24
Peak memory 206064 kb
Host smart-b898e376-ae57-4ab2-91df-14631e7d876e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30377
62828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.3037762828
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.2116036683
Short name T840
Test name
Test status
Simulation time 211631468 ps
CPU time 0.83 seconds
Started Jun 23 05:16:42 PM PDT 24
Finished Jun 23 05:16:44 PM PDT 24
Peak memory 206100 kb
Host smart-2b91ef27-84aa-45ff-9aa0-9cb00b0e0354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21160
36683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2116036683
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.4048608091
Short name T400
Test name
Test status
Simulation time 151227377 ps
CPU time 0.77 seconds
Started Jun 23 05:16:40 PM PDT 24
Finished Jun 23 05:16:41 PM PDT 24
Peak memory 206096 kb
Host smart-aeaa22ed-1171-42b6-961b-98c0b8129b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40486
08091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.4048608091
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.4169342858
Short name T1103
Test name
Test status
Simulation time 150960527 ps
CPU time 0.81 seconds
Started Jun 23 05:16:41 PM PDT 24
Finished Jun 23 05:16:42 PM PDT 24
Peak memory 206132 kb
Host smart-00dfd14f-097a-4f2a-a8e6-a6333373777e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41693
42858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.4169342858
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2209196887
Short name T1880
Test name
Test status
Simulation time 216551271 ps
CPU time 0.9 seconds
Started Jun 23 05:16:28 PM PDT 24
Finished Jun 23 05:16:29 PM PDT 24
Peak memory 206056 kb
Host smart-c63e9664-4b06-4cab-a62a-fcee11f4608c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22091
96887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2209196887
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.3415316978
Short name T1735
Test name
Test status
Simulation time 7389823657 ps
CPU time 55.52 seconds
Started Jun 23 05:16:46 PM PDT 24
Finished Jun 23 05:17:42 PM PDT 24
Peak memory 206304 kb
Host smart-ebd75990-ab99-477f-bd0c-c347c8c8bfb5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3415316978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.3415316978
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1498601011
Short name T385
Test name
Test status
Simulation time 154240032 ps
CPU time 0.78 seconds
Started Jun 23 05:16:42 PM PDT 24
Finished Jun 23 05:16:43 PM PDT 24
Peak memory 206084 kb
Host smart-3c32541b-7a21-4aa1-bdf2-d2ccf81457c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14986
01011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1498601011
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.480365451
Short name T664
Test name
Test status
Simulation time 165057273 ps
CPU time 0.86 seconds
Started Jun 23 05:16:41 PM PDT 24
Finished Jun 23 05:16:42 PM PDT 24
Peak memory 206060 kb
Host smart-acd8e442-fdab-4a7c-a10e-27f2065a5cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48036
5451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.480365451
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.417217262
Short name T1456
Test name
Test status
Simulation time 4183612922 ps
CPU time 40.14 seconds
Started Jun 23 05:16:42 PM PDT 24
Finished Jun 23 05:17:23 PM PDT 24
Peak memory 206320 kb
Host smart-9b66d3ed-bd09-4d60-9175-df1ecaafaa63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41721
7262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.417217262
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.2371288857
Short name T1229
Test name
Test status
Simulation time 3987963796 ps
CPU time 4.7 seconds
Started Jun 23 05:16:49 PM PDT 24
Finished Jun 23 05:16:54 PM PDT 24
Peak memory 206080 kb
Host smart-4ecd3eba-638c-425b-8cfd-c4c4ffc16114
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2371288857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.2371288857
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.824407896
Short name T1583
Test name
Test status
Simulation time 13390103922 ps
CPU time 11.33 seconds
Started Jun 23 05:16:45 PM PDT 24
Finished Jun 23 05:16:57 PM PDT 24
Peak memory 206344 kb
Host smart-2ef6e742-f641-41e3-9881-3e9aa9e8b39d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=824407896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.824407896
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.2589023302
Short name T2263
Test name
Test status
Simulation time 23329798779 ps
CPU time 22.64 seconds
Started Jun 23 05:16:48 PM PDT 24
Finished Jun 23 05:17:11 PM PDT 24
Peak memory 206376 kb
Host smart-27044f24-0804-424b-917b-4370335dc23f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2589023302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.2589023302
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.650501011
Short name T1579
Test name
Test status
Simulation time 159714366 ps
CPU time 0.8 seconds
Started Jun 23 05:16:45 PM PDT 24
Finished Jun 23 05:16:46 PM PDT 24
Peak memory 206020 kb
Host smart-62059b0e-410c-4035-a5ab-f5c14ee64316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65050
1011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.650501011
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.2555962635
Short name T2209
Test name
Test status
Simulation time 147700774 ps
CPU time 0.77 seconds
Started Jun 23 05:16:48 PM PDT 24
Finished Jun 23 05:16:49 PM PDT 24
Peak memory 206100 kb
Host smart-63c4d40d-c1ae-49dd-944d-315e3470b825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25559
62635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.2555962635
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.2376000429
Short name T1301
Test name
Test status
Simulation time 276931286 ps
CPU time 1.08 seconds
Started Jun 23 05:16:44 PM PDT 24
Finished Jun 23 05:16:45 PM PDT 24
Peak memory 206104 kb
Host smart-2f8a268d-5d00-4753-9a60-31d8b8a9e219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23760
00429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.2376000429
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.282597425
Short name T1536
Test name
Test status
Simulation time 1466674372 ps
CPU time 3.02 seconds
Started Jun 23 05:16:47 PM PDT 24
Finished Jun 23 05:16:50 PM PDT 24
Peak memory 206340 kb
Host smart-d2a8feb0-4ff1-415d-96be-d8d0f8a0f34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28259
7425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.282597425
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.871179182
Short name T1741
Test name
Test status
Simulation time 14755017827 ps
CPU time 31.24 seconds
Started Jun 23 05:16:48 PM PDT 24
Finished Jun 23 05:17:19 PM PDT 24
Peak memory 206380 kb
Host smart-4c03da38-f13f-4f69-bbc9-eaa9c4dab13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87117
9182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.871179182
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.96155537
Short name T824
Test name
Test status
Simulation time 504729982 ps
CPU time 1.35 seconds
Started Jun 23 05:16:45 PM PDT 24
Finished Jun 23 05:16:47 PM PDT 24
Peak memory 206100 kb
Host smart-c09093ad-02a6-45fb-aa72-8d4e0ed97c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96155
537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.96155537
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1662303383
Short name T2060
Test name
Test status
Simulation time 154955564 ps
CPU time 0.81 seconds
Started Jun 23 05:16:46 PM PDT 24
Finished Jun 23 05:16:47 PM PDT 24
Peak memory 206104 kb
Host smart-e8ca085f-ec74-4028-a308-949be3db7323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16623
03383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1662303383
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.497948175
Short name T361
Test name
Test status
Simulation time 64266720 ps
CPU time 0.71 seconds
Started Jun 23 05:16:45 PM PDT 24
Finished Jun 23 05:16:46 PM PDT 24
Peak memory 206056 kb
Host smart-2446bd09-5670-4daf-8fba-5f0f43f669aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49794
8175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.497948175
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.2919871544
Short name T886
Test name
Test status
Simulation time 826298313 ps
CPU time 2.09 seconds
Started Jun 23 05:16:46 PM PDT 24
Finished Jun 23 05:16:49 PM PDT 24
Peak memory 206320 kb
Host smart-233fd63e-dd36-4f52-8087-89725cd3fef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29198
71544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.2919871544
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1336978276
Short name T2234
Test name
Test status
Simulation time 382666853 ps
CPU time 2.47 seconds
Started Jun 23 05:16:47 PM PDT 24
Finished Jun 23 05:16:50 PM PDT 24
Peak memory 206308 kb
Host smart-0ea182f6-a282-4478-b844-23e20d750d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13369
78276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1336978276
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.3072446757
Short name T657
Test name
Test status
Simulation time 183094679 ps
CPU time 0.84 seconds
Started Jun 23 05:17:02 PM PDT 24
Finished Jun 23 05:17:04 PM PDT 24
Peak memory 205988 kb
Host smart-331c8dbe-ec3e-4484-ae74-0251297c84cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30724
46757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.3072446757
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.164868540
Short name T624
Test name
Test status
Simulation time 158900197 ps
CPU time 0.77 seconds
Started Jun 23 05:16:58 PM PDT 24
Finished Jun 23 05:16:59 PM PDT 24
Peak memory 206052 kb
Host smart-376f37ad-4995-4c4a-9aa5-14a308f4f5a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16486
8540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.164868540
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3112465454
Short name T852
Test name
Test status
Simulation time 279067582 ps
CPU time 0.96 seconds
Started Jun 23 05:16:45 PM PDT 24
Finished Jun 23 05:16:47 PM PDT 24
Peak memory 206100 kb
Host smart-c13cbbfd-229c-477e-84d4-32d02a268e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31124
65454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3112465454
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3614047945
Short name T1342
Test name
Test status
Simulation time 184244214 ps
CPU time 0.81 seconds
Started Jun 23 05:16:49 PM PDT 24
Finished Jun 23 05:16:50 PM PDT 24
Peak memory 206020 kb
Host smart-4a575e97-c6c9-43f7-a650-29f5912be056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36140
47945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3614047945
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.1059086433
Short name T1408
Test name
Test status
Simulation time 23282392358 ps
CPU time 25.57 seconds
Started Jun 23 05:16:48 PM PDT 24
Finished Jun 23 05:17:14 PM PDT 24
Peak memory 206088 kb
Host smart-6e0274e1-9c24-44d9-88d0-094116768fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10590
86433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.1059086433
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.585077205
Short name T575
Test name
Test status
Simulation time 3310504875 ps
CPU time 3.98 seconds
Started Jun 23 05:16:52 PM PDT 24
Finished Jun 23 05:16:56 PM PDT 24
Peak memory 206184 kb
Host smart-741c5d5a-c5f2-46f5-9870-55dc4aa62d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58507
7205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.585077205
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.3449457563
Short name T146
Test name
Test status
Simulation time 8712468049 ps
CPU time 242.38 seconds
Started Jun 23 05:16:52 PM PDT 24
Finished Jun 23 05:20:55 PM PDT 24
Peak memory 206352 kb
Host smart-c52ef84b-a40c-4e7f-8ead-d86e6a3dd3be
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3449457563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.3449457563
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.2385152216
Short name T1205
Test name
Test status
Simulation time 252335742 ps
CPU time 0.99 seconds
Started Jun 23 05:17:01 PM PDT 24
Finished Jun 23 05:17:03 PM PDT 24
Peak memory 206076 kb
Host smart-a5731f8d-516f-42c0-9a4d-ea73f3132d84
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2385152216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.2385152216
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3097776358
Short name T309
Test name
Test status
Simulation time 187278536 ps
CPU time 0.82 seconds
Started Jun 23 05:16:50 PM PDT 24
Finished Jun 23 05:16:52 PM PDT 24
Peak memory 206068 kb
Host smart-12ee329c-5188-4430-88d3-af5c358844a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30977
76358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3097776358
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.1334780639
Short name T2347
Test name
Test status
Simulation time 8911927989 ps
CPU time 83.18 seconds
Started Jun 23 05:16:52 PM PDT 24
Finished Jun 23 05:18:15 PM PDT 24
Peak memory 206328 kb
Host smart-5e181f17-f7bf-4594-bbfa-c79ab0510fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13347
80639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.1334780639
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.1660987431
Short name T2271
Test name
Test status
Simulation time 13757428966 ps
CPU time 127.98 seconds
Started Jun 23 05:16:50 PM PDT 24
Finished Jun 23 05:18:59 PM PDT 24
Peak memory 206352 kb
Host smart-18d49a9b-bcc8-4a9a-95bc-2077f510a00f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1660987431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.1660987431
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.1503956896
Short name T1225
Test name
Test status
Simulation time 155597298 ps
CPU time 0.9 seconds
Started Jun 23 05:17:02 PM PDT 24
Finished Jun 23 05:17:03 PM PDT 24
Peak memory 206048 kb
Host smart-250356ae-53ab-458c-8a42-9c22de01fe44
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1503956896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.1503956896
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2854511474
Short name T1852
Test name
Test status
Simulation time 154005060 ps
CPU time 0.77 seconds
Started Jun 23 05:16:51 PM PDT 24
Finished Jun 23 05:16:53 PM PDT 24
Peak memory 206120 kb
Host smart-4edc29d6-355b-40f6-854f-805d36043d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28545
11474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2854511474
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.182795537
Short name T1725
Test name
Test status
Simulation time 161180114 ps
CPU time 0.86 seconds
Started Jun 23 05:16:50 PM PDT 24
Finished Jun 23 05:16:52 PM PDT 24
Peak memory 206288 kb
Host smart-05887058-0a68-4a5b-bce1-2f0863b888b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18279
5537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.182795537
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.4236718153
Short name T90
Test name
Test status
Simulation time 224712094 ps
CPU time 0.83 seconds
Started Jun 23 05:16:51 PM PDT 24
Finished Jun 23 05:16:53 PM PDT 24
Peak memory 206024 kb
Host smart-7ca21ad3-b3b2-465f-91be-f6f57f4cad94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42367
18153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.4236718153
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.196421460
Short name T293
Test name
Test status
Simulation time 172786877 ps
CPU time 0.81 seconds
Started Jun 23 05:16:49 PM PDT 24
Finished Jun 23 05:16:50 PM PDT 24
Peak memory 206112 kb
Host smart-4bc9d45e-8f45-4b39-879a-61083710e928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19642
1460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.196421460
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2926243850
Short name T392
Test name
Test status
Simulation time 187936448 ps
CPU time 0.83 seconds
Started Jun 23 05:16:56 PM PDT 24
Finished Jun 23 05:16:58 PM PDT 24
Peak memory 205996 kb
Host smart-1f644755-a8c5-4c8a-a2d0-92f884338871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29262
43850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2926243850
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.867271484
Short name T2270
Test name
Test status
Simulation time 166184665 ps
CPU time 0.82 seconds
Started Jun 23 05:16:56 PM PDT 24
Finished Jun 23 05:16:58 PM PDT 24
Peak memory 206116 kb
Host smart-30ef2ac8-c9e0-4715-95bf-82de2fa01f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86727
1484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.867271484
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.2843108659
Short name T202
Test name
Test status
Simulation time 241389549 ps
CPU time 0.96 seconds
Started Jun 23 05:16:58 PM PDT 24
Finished Jun 23 05:17:00 PM PDT 24
Peak memory 206084 kb
Host smart-9cd1423c-768e-468c-b98b-aa48ece9e698
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2843108659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.2843108659
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3980544897
Short name T1956
Test name
Test status
Simulation time 151862658 ps
CPU time 0.77 seconds
Started Jun 23 05:16:57 PM PDT 24
Finished Jun 23 05:16:58 PM PDT 24
Peak memory 206048 kb
Host smart-72c05c10-4dc6-46ce-b2f1-89fa44960f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39805
44897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3980544897
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1634687288
Short name T1464
Test name
Test status
Simulation time 91133988 ps
CPU time 0.7 seconds
Started Jun 23 05:16:55 PM PDT 24
Finished Jun 23 05:16:56 PM PDT 24
Peak memory 206116 kb
Host smart-f460a239-2ad6-4aea-b432-bd515dd9ae5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16346
87288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1634687288
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.4154803812
Short name T2214
Test name
Test status
Simulation time 23261026860 ps
CPU time 50.71 seconds
Started Jun 23 05:16:50 PM PDT 24
Finished Jun 23 05:17:42 PM PDT 24
Peak memory 206320 kb
Host smart-9e8e4f4b-59f3-49d0-883e-abd8c8024256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41548
03812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.4154803812
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.312917303
Short name T681
Test name
Test status
Simulation time 185942608 ps
CPU time 0.84 seconds
Started Jun 23 05:16:51 PM PDT 24
Finished Jun 23 05:16:52 PM PDT 24
Peak memory 206100 kb
Host smart-a8e03af6-91ad-4c00-86f4-1aaabc1fe0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31291
7303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.312917303
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1288983388
Short name T20
Test name
Test status
Simulation time 203252416 ps
CPU time 0.88 seconds
Started Jun 23 05:16:57 PM PDT 24
Finished Jun 23 05:16:58 PM PDT 24
Peak memory 206000 kb
Host smart-4187d503-3486-492c-a2bd-50e0e371b3a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12889
83388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1288983388
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.1223030346
Short name T2067
Test name
Test status
Simulation time 14038503534 ps
CPU time 75.99 seconds
Started Jun 23 05:16:56 PM PDT 24
Finished Jun 23 05:18:13 PM PDT 24
Peak memory 206256 kb
Host smart-a04d8245-e58a-4064-b6ae-1f405a9d39ca
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1223030346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.1223030346
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3954159274
Short name T2304
Test name
Test status
Simulation time 19261910797 ps
CPU time 110.22 seconds
Started Jun 23 05:16:54 PM PDT 24
Finished Jun 23 05:18:45 PM PDT 24
Peak memory 206348 kb
Host smart-2f967de0-619c-4ba3-8b68-df6008595db0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3954159274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3954159274
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.496541290
Short name T1700
Test name
Test status
Simulation time 19630087643 ps
CPU time 455.29 seconds
Started Jun 23 05:16:56 PM PDT 24
Finished Jun 23 05:24:32 PM PDT 24
Peak memory 206312 kb
Host smart-5ac93858-36cb-4eb4-9dfb-77ddf48375fa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=496541290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.496541290
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.3878686972
Short name T622
Test name
Test status
Simulation time 239733085 ps
CPU time 0.91 seconds
Started Jun 23 05:17:00 PM PDT 24
Finished Jun 23 05:17:01 PM PDT 24
Peak memory 206028 kb
Host smart-ed1e6b5f-8a9a-4b93-af93-1b30df08f7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38786
86972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.3878686972
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.2387600452
Short name T2174
Test name
Test status
Simulation time 169665124 ps
CPU time 0.82 seconds
Started Jun 23 05:16:58 PM PDT 24
Finished Jun 23 05:16:59 PM PDT 24
Peak memory 206120 kb
Host smart-6ab81836-560a-4af7-9ade-e60eae2892bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23876
00452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.2387600452
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1159362345
Short name T955
Test name
Test status
Simulation time 213486343 ps
CPU time 0.86 seconds
Started Jun 23 05:16:56 PM PDT 24
Finished Jun 23 05:16:58 PM PDT 24
Peak memory 206108 kb
Host smart-ca7461c4-4165-45f6-8c2d-c854878162d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11593
62345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1159362345
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.850601775
Short name T1774
Test name
Test status
Simulation time 167688920 ps
CPU time 0.78 seconds
Started Jun 23 05:16:56 PM PDT 24
Finished Jun 23 05:16:57 PM PDT 24
Peak memory 206052 kb
Host smart-aeff1cd5-7314-4468-bd0e-ec7ecf9e0268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85060
1775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.850601775
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.997466653
Short name T1227
Test name
Test status
Simulation time 163732707 ps
CPU time 0.8 seconds
Started Jun 23 05:16:55 PM PDT 24
Finished Jun 23 05:16:56 PM PDT 24
Peak memory 206060 kb
Host smart-0855e0d1-81f4-47f3-8643-3a2e59373c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99746
6653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.997466653
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2655748589
Short name T1835
Test name
Test status
Simulation time 221977388 ps
CPU time 0.92 seconds
Started Jun 23 05:16:46 PM PDT 24
Finished Jun 23 05:16:48 PM PDT 24
Peak memory 206052 kb
Host smart-86f3be93-4a08-4c65-abe5-59af9a17ec2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26557
48589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2655748589
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.157620181
Short name T1029
Test name
Test status
Simulation time 8228306432 ps
CPU time 76.78 seconds
Started Jun 23 05:16:57 PM PDT 24
Finished Jun 23 05:18:14 PM PDT 24
Peak memory 206428 kb
Host smart-ea78571b-c155-412d-ba63-3bcaa8c1914b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=157620181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.157620181
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.849541583
Short name T330
Test name
Test status
Simulation time 176420187 ps
CPU time 0.81 seconds
Started Jun 23 05:16:58 PM PDT 24
Finished Jun 23 05:16:59 PM PDT 24
Peak memory 206020 kb
Host smart-9c057c1b-892b-4f29-b96b-63b1663852ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84954
1583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.849541583
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3881394795
Short name T662
Test name
Test status
Simulation time 203869515 ps
CPU time 0.8 seconds
Started Jun 23 05:16:59 PM PDT 24
Finished Jun 23 05:17:00 PM PDT 24
Peak memory 205988 kb
Host smart-59e6ca69-1ce2-4dff-a7bf-544de674007d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38813
94795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3881394795
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.2845579655
Short name T1036
Test name
Test status
Simulation time 4056661382 ps
CPU time 42.8 seconds
Started Jun 23 05:16:57 PM PDT 24
Finished Jun 23 05:17:40 PM PDT 24
Peak memory 206368 kb
Host smart-14269f57-a0cb-4780-a0ad-1f5ac6931d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28455
79655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.2845579655
Directory /workspace/9.usbdev_streaming_out/latest
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