Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	121179	1		T1	5		T2	2		T3	2
all_values[1]	121179	1		T1	5		T2	2		T3	2
all_values[2]	121179	1		T1	5		T2	2		T3	2
all_values[3]	121179	1		T1	5		T2	2		T3	2
all_values[4]	121179	1		T1	5		T2	2		T3	2
all_values[5]	121179	1		T1	5		T2	2		T3	2
all_values[6]	121179	1		T1	5		T2	2		T3	2
all_values[7]	121179	1		T1	5		T2	2		T3	2
all_values[8]	121179	1		T1	5		T2	2		T3	2
all_values[9]	121179	1		T1	5		T2	2		T3	2
all_values[10]	121179	1		T1	5		T2	2		T3	2
all_values[11]	121179	1		T1	5		T2	2		T3	2
all_values[12]	121179	1		T1	5		T2	2		T3	2
all_values[13]	121179	1		T1	5		T2	2		T3	2
all_values[14]	121179	1		T1	5		T2	2		T3	2
all_values[15]	121179	1		T1	5		T2	2		T3	2
all_values[16]	121179	1		T1	5		T2	2		T3	2
all_values[17]	121179	1		T1	5		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2173851	1		T1	85		T2	36		T3	36
auto[1]	7371	1		T1	5		T7	2		T19	4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2176433	1		T1	90		T2	36		T3	36
auto[1]	4789	1		T213	60		T214	126		T216	60

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	120213	1		T1	5		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	124	1		T213	1		T214	2		T215	4
all_values[0]	auto[1]	auto[0]	704	1		T19	4		T47	4		T48	3
all_values[0]	auto[1]	auto[1]	138	1		T213	4		T214	5		T215	4
all_values[1]	auto[0]	auto[0]	118805	1		T2	2		T3	2		T27	2
all_values[1]	auto[0]	auto[1]	139	1		T213	4		T214	5		T215	3
all_values[1]	auto[1]	auto[0]	2101	1		T1	5		T7	2		T28	3
all_values[1]	auto[1]	auto[1]	134	1		T214	1		T278	1		T280	5
all_values[2]	auto[0]	auto[0]	120772	1		T1	5		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	121	1		T213	1		T214	5		T216	1
all_values[2]	auto[1]	auto[0]	128	1		T42	2		T43	2		T44	2
all_values[2]	auto[1]	auto[1]	158	1		T213	3		T214	1		T216	4
all_values[3]	auto[0]	auto[0]	119478	1		T1	5		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	129	1		T213	2		T214	6		T216	3
all_values[3]	auto[1]	auto[0]	1448	1		T63	1407		T216	1		T280	3
all_values[3]	auto[1]	auto[1]	124	1		T213	3		T214	2		T216	1
all_values[4]	auto[0]	auto[0]	120884	1		T1	5		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	132	1		T213	3		T214	1		T216	3
all_values[4]	auto[1]	auto[0]	30	1		T64	2		T214	1		T216	2
all_values[4]	auto[1]	auto[1]	133	1		T213	2		T214	6		T215	5
all_values[5]	auto[0]	auto[0]	120887	1		T1	5		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	118	1		T214	3		T215	3		T278	1
all_values[5]	auto[1]	auto[0]	25	1		T213	1		T281	3		T282	1
all_values[5]	auto[1]	auto[1]	149	1		T213	3		T214	5		T216	5
all_values[6]	auto[0]	auto[0]	120888	1		T1	5		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	132	1		T213	3		T214	2		T215	1
all_values[6]	auto[1]	auto[0]	25	1		T213	1		T280	1		T283	1
all_values[6]	auto[1]	auto[1]	134	1		T214	6		T216	5		T215	6
all_values[7]	auto[0]	auto[0]	120887	1		T1	5		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	127	1		T213	3		T214	5		T216	3
all_values[7]	auto[1]	auto[0]	29	1		T50	2		T51	2		T52	2
all_values[7]	auto[1]	auto[1]	136	1		T214	2		T216	2		T215	3
all_values[8]	auto[0]	auto[0]	120873	1		T1	5		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	141	1		T213	4		T214	5		T215	4
all_values[8]	auto[1]	auto[0]	43	1		T56	11		T216	3		T215	1
all_values[8]	auto[1]	auto[1]	122	1		T213	1		T214	2		T215	3
all_values[9]	auto[0]	auto[0]	120857	1		T1	5		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	145	1		T213	4		T214	3		T216	4
all_values[9]	auto[1]	auto[0]	47	1		T21	5		T61	5		T62	5
all_values[9]	auto[1]	auto[1]	130	1		T213	1		T214	4		T215	6
all_values[10]	auto[0]	auto[0]	120885	1		T1	5		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	131	1		T214	2		T216	1		T215	6
all_values[10]	auto[1]	auto[0]	15	1		T213	1		T284	1		T285	4
all_values[10]	auto[1]	auto[1]	148	1		T213	3		T214	5		T216	4
all_values[11]	auto[0]	auto[0]	120781	1		T1	5		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	134	1		T214	4		T216	4		T215	3
all_values[11]	auto[1]	auto[0]	132	1		T71	2		T72	2		T73	2
all_values[11]	auto[1]	auto[1]	132	1		T214	2		T216	1		T215	4
all_values[12]	auto[0]	auto[0]	120883	1		T1	5		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	89	1		T214	1		T215	2		T278	4
all_values[12]	auto[1]	auto[0]	47	1		T75	3		T76	3		T77	3
all_values[12]	auto[1]	auto[1]	160	1		T214	4		T216	5		T215	4
all_values[13]	auto[0]	auto[0]	120894	1		T1	5		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	129	1		T213	3		T214	5		T216	1
all_values[13]	auto[1]	auto[0]	27	1		T213	2		T281	1		T286	2
all_values[13]	auto[1]	auto[1]	129	1		T214	3		T216	4		T215	3
all_values[14]	auto[0]	auto[0]	120894	1		T1	5		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	148	1		T213	3		T214	5		T215	1
all_values[14]	auto[1]	auto[0]	14	1		T214	2		T216	1		T215	1
all_values[14]	auto[1]	auto[1]	123	1		T213	2		T214	1		T215	6
all_values[15]	auto[0]	auto[0]	120889	1		T1	5		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	130	1		T214	4		T280	4		T281	5
all_values[15]	auto[1]	auto[0]	29	1		T216	1		T215	2		T281	1
all_values[15]	auto[1]	auto[1]	131	1		T213	3		T214	3		T215	5
all_values[16]	auto[0]	auto[0]	120863	1		T1	5		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	133	1		T214	3		T216	4		T215	4
all_values[16]	auto[1]	auto[0]	55	1		T67	8		T68	8		T69	8
all_values[16]	auto[1]	auto[1]	128	1		T214	5		T215	3		T278	4
all_values[17]	auto[0]	auto[0]	120885	1		T1	5		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	131	1		T213	1		T214	1		T216	5
all_values[17]	auto[1]	auto[0]	16	1		T57	2		T282	1		T287	1
all_values[17]	auto[1]	auto[1]	147	1		T213	3		T214	7		T215	5