Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	121179	1		T1	5		T2	2		T3	2
all_pins[1]	121179	1		T1	5		T2	2		T3	2
all_pins[2]	121179	1		T1	5		T2	2		T3	2
all_pins[3]	121179	1		T1	5		T2	2		T3	2
all_pins[4]	121179	1		T1	5		T2	2		T3	2
all_pins[5]	121179	1		T1	5		T2	2		T3	2
all_pins[6]	121179	1		T1	5		T2	2		T3	2
all_pins[7]	121179	1		T1	5		T2	2		T3	2
all_pins[8]	121179	1		T1	5		T2	2		T3	2
all_pins[9]	121179	1		T1	5		T2	2		T3	2
all_pins[10]	121179	1		T1	5		T2	2		T3	2
all_pins[11]	121179	1		T1	5		T2	2		T3	2
all_pins[12]	121179	1		T1	5		T2	2		T3	2
all_pins[13]	121179	1		T1	5		T2	2		T3	2
all_pins[14]	121179	1		T1	5		T2	2		T3	2
all_pins[15]	121179	1		T1	5		T2	2		T3	2
all_pins[16]	121179	1		T1	5		T2	2		T3	2
all_pins[17]	121179	1		T1	5		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2178628	1		T1	88		T2	36		T3	36
values[0x1]	2594	1		T1	2		T7	1		T19	1
transitions[0x0=>0x1]	2284	1		T1	2		T7	1		T19	1
transitions[0x1=>0x0]	2301	1		T1	2		T7	1		T19	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	121075	1		T1	5		T2	2		T3	2
all_pins[0]	values[0x1]	104	1		T19	1		T47	1		T288	1
all_pins[0]	transitions[0x0=>0x1]	92	1		T19	1		T47	1		T288	1
all_pins[0]	transitions[0x1=>0x0]	1312	1		T1	2		T7	1		T28	1
all_pins[1]	values[0x0]	119855	1		T1	3		T2	2		T3	2
all_pins[1]	values[0x1]	1324	1		T1	2		T7	1		T28	1
all_pins[1]	transitions[0x0=>0x1]	1310	1		T1	2		T7	1		T28	1
all_pins[1]	transitions[0x1=>0x0]	118	1		T42	1		T43	1		T44	1
all_pins[2]	values[0x0]	121047	1		T1	5		T2	2		T3	2
all_pins[2]	values[0x1]	132	1		T42	1		T43	1		T44	1
all_pins[2]	transitions[0x0=>0x1]	105	1		T42	1		T43	1		T44	1
all_pins[2]	transitions[0x1=>0x0]	36	1		T63	1		T213	2		T214	1
all_pins[3]	values[0x0]	121116	1		T1	5		T2	2		T3	2
all_pins[3]	values[0x1]	63	1		T63	1		T213	2		T214	1
all_pins[3]	transitions[0x0=>0x1]	47	1		T63	1		T213	2		T216	1
all_pins[3]	transitions[0x1=>0x0]	53	1		T64	1		T213	2		T214	1
all_pins[4]	values[0x0]	121110	1		T1	5		T2	2		T3	2
all_pins[4]	values[0x1]	69	1		T64	1		T213	2		T214	2
all_pins[4]	transitions[0x0=>0x1]	60	1		T64	1		T213	2		T214	2
all_pins[4]	transitions[0x1=>0x0]	59	1		T213	2		T216	4		T215	2
all_pins[5]	values[0x0]	121111	1		T1	5		T2	2		T3	2
all_pins[5]	values[0x1]	68	1		T213	2		T216	4		T215	4
all_pins[5]	transitions[0x0=>0x1]	47	1		T213	2		T215	2		T279	2
all_pins[5]	transitions[0x1=>0x0]	38	1		T214	5		T281	1		T279	1
all_pins[6]	values[0x0]	121120	1		T1	5		T2	2		T3	2
all_pins[6]	values[0x1]	59	1		T214	5		T216	4		T215	2
all_pins[6]	transitions[0x0=>0x1]	44	1		T214	5		T216	3		T215	2
all_pins[6]	transitions[0x1=>0x0]	42	1		T50	1		T51	1		T52	1
all_pins[7]	values[0x0]	121122	1		T1	5		T2	2		T3	2
all_pins[7]	values[0x1]	57	1		T50	1		T51	1		T52	1
all_pins[7]	transitions[0x0=>0x1]	45	1		T50	1		T51	1		T52	1
all_pins[7]	transitions[0x1=>0x0]	37	1		T56	1		T213	1		T215	1
all_pins[8]	values[0x0]	121130	1		T1	5		T2	2		T3	2
all_pins[8]	values[0x1]	49	1		T56	1		T213	1		T215	1
all_pins[8]	transitions[0x0=>0x1]	35	1		T56	1		T213	1		T281	2
all_pins[8]	transitions[0x1=>0x0]	66	1		T21	2		T61	2		T62	2
all_pins[9]	values[0x0]	121099	1		T1	5		T2	2		T3	2
all_pins[9]	values[0x1]	80	1		T21	2		T61	2		T62	2
all_pins[9]	transitions[0x0=>0x1]	62	1		T21	2		T61	2		T62	2
all_pins[9]	transitions[0x1=>0x0]	63	1		T213	2		T214	1		T216	3
all_pins[10]	values[0x0]	121098	1		T1	5		T2	2		T3	2
all_pins[10]	values[0x1]	81	1		T213	2		T214	3		T216	3
all_pins[10]	transitions[0x0=>0x1]	59	1		T213	2		T214	3		T216	3
all_pins[10]	transitions[0x1=>0x0]	86	1		T71	1		T72	1		T73	1
all_pins[11]	values[0x0]	121071	1		T1	5		T2	2		T3	2
all_pins[11]	values[0x1]	108	1		T71	1		T72	1		T73	1
all_pins[11]	transitions[0x0=>0x1]	88	1		T71	1		T72	1		T73	1
all_pins[11]	transitions[0x1=>0x0]	51	1		T75	1		T76	1		T77	1
all_pins[12]	values[0x0]	121108	1		T1	5		T2	2		T3	2
all_pins[12]	values[0x1]	71	1		T75	1		T76	1		T77	1
all_pins[12]	transitions[0x0=>0x1]	52	1		T75	1		T76	1		T77	1
all_pins[12]	transitions[0x1=>0x0]	44	1		T214	2		T215	1		T280	1
all_pins[13]	values[0x0]	121116	1		T1	5		T2	2		T3	2
all_pins[13]	values[0x1]	63	1		T214	2		T216	3		T215	1
all_pins[13]	transitions[0x0=>0x1]	52	1		T214	2		T216	3		T280	1
all_pins[13]	transitions[0x1=>0x0]	45	1		T213	1		T214	1		T215	1
all_pins[14]	values[0x0]	121123	1		T1	5		T2	2		T3	2
all_pins[14]	values[0x1]	56	1		T213	1		T214	1		T215	2
all_pins[14]	transitions[0x0=>0x1]	43	1		T213	1		T214	1		T215	2
all_pins[14]	transitions[0x1=>0x0]	54	1		T215	1		T278	3		T280	1
all_pins[15]	values[0x0]	121112	1		T1	5		T2	2		T3	2
all_pins[15]	values[0x1]	67	1		T215	1		T278	4		T280	1
all_pins[15]	transitions[0x0=>0x1]	42	1		T215	1		T278	1		T280	1
all_pins[15]	transitions[0x1=>0x0]	59	1		T67	4		T68	4		T69	4
all_pins[16]	values[0x0]	121095	1		T1	5		T2	2		T3	2
all_pins[16]	values[0x1]	84	1		T67	4		T68	4		T69	4
all_pins[16]	transitions[0x0=>0x1]	70	1		T67	4		T68	4		T69	4
all_pins[16]	transitions[0x1=>0x0]	45	1		T57	1		T213	1		T214	2
all_pins[17]	values[0x0]	121120	1		T1	5		T2	2		T3	2
all_pins[17]	values[0x1]	59	1		T57	1		T213	1		T214	3
all_pins[17]	transitions[0x0=>0x1]	31	1		T57	1		T213	1		T214	2
all_pins[17]	transitions[0x1=>0x0]	93	1		T19	1		T47	1		T288	1