Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.35 97.82 93.79 97.44 73.44 96.21 98.17 96.58


Total test records in report: 2626
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T265 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3119809681 Jun 24 06:06:34 PM PDT 24 Jun 24 06:06:37 PM PDT 24 61349772 ps
T243 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3899199775 Jun 24 06:06:44 PM PDT 24 Jun 24 06:06:48 PM PDT 24 243375442 ps
T290 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3782593406 Jun 24 06:06:40 PM PDT 24 Jun 24 06:06:43 PM PDT 24 46224088 ps
T2523 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.904762987 Jun 24 06:06:32 PM PDT 24 Jun 24 06:06:35 PM PDT 24 58602874 ps
T2524 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3724125777 Jun 24 06:06:32 PM PDT 24 Jun 24 06:06:35 PM PDT 24 75005295 ps
T246 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3443868775 Jun 24 06:06:27 PM PDT 24 Jun 24 06:06:31 PM PDT 24 223714361 ps
T266 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3238465421 Jun 24 06:06:22 PM PDT 24 Jun 24 06:06:24 PM PDT 24 60353328 ps
T2525 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2308413182 Jun 24 06:06:21 PM PDT 24 Jun 24 06:06:27 PM PDT 24 740342495 ps
T287 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.488524350 Jun 24 06:06:40 PM PDT 24 Jun 24 06:06:44 PM PDT 24 59148281 ps
T2526 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4104578211 Jun 24 06:06:31 PM PDT 24 Jun 24 06:06:36 PM PDT 24 245373504 ps
T2527 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.15700551 Jun 24 06:06:27 PM PDT 24 Jun 24 06:06:31 PM PDT 24 102320049 ps
T296 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.585562714 Jun 24 06:06:26 PM PDT 24 Jun 24 06:06:33 PM PDT 24 822095671 ps
T244 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2174857587 Jun 24 06:06:33 PM PDT 24 Jun 24 06:06:37 PM PDT 24 80868323 ps
T2528 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.331713519 Jun 24 06:06:36 PM PDT 24 Jun 24 06:06:39 PM PDT 24 39359749 ps
T284 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2025805695 Jun 24 06:06:46 PM PDT 24 Jun 24 06:06:47 PM PDT 24 45006834 ps
T2529 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1472292355 Jun 24 06:06:18 PM PDT 24 Jun 24 06:06:21 PM PDT 24 77858494 ps
T2530 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3577393485 Jun 24 06:06:42 PM PDT 24 Jun 24 06:06:45 PM PDT 24 63684264 ps
T285 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1825047410 Jun 24 06:06:41 PM PDT 24 Jun 24 06:06:44 PM PDT 24 36251539 ps
T267 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.706153354 Jun 24 06:06:27 PM PDT 24 Jun 24 06:06:30 PM PDT 24 62229576 ps
T2531 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.179140074 Jun 24 06:06:26 PM PDT 24 Jun 24 06:06:29 PM PDT 24 71525440 ps
T268 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2655040618 Jun 24 06:06:35 PM PDT 24 Jun 24 06:06:38 PM PDT 24 56081787 ps
T2532 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3822269808 Jun 24 06:06:23 PM PDT 24 Jun 24 06:06:27 PM PDT 24 245363196 ps
T2533 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3116726263 Jun 24 06:06:25 PM PDT 24 Jun 24 06:06:27 PM PDT 24 60375732 ps
T248 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3225290044 Jun 24 06:06:35 PM PDT 24 Jun 24 06:06:40 PM PDT 24 208157701 ps
T2534 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.4226792324 Jun 24 06:06:32 PM PDT 24 Jun 24 06:06:35 PM PDT 24 41165129 ps
T2535 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2313782808 Jun 24 06:06:31 PM PDT 24 Jun 24 06:06:34 PM PDT 24 76209567 ps
T2536 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1573787532 Jun 24 06:06:36 PM PDT 24 Jun 24 06:06:39 PM PDT 24 38024317 ps
T2537 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.402827978 Jun 24 06:06:23 PM PDT 24 Jun 24 06:06:24 PM PDT 24 78120838 ps
T2538 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3812590781 Jun 24 06:06:21 PM PDT 24 Jun 24 06:06:23 PM PDT 24 55000779 ps
T2539 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.853755907 Jun 24 06:06:29 PM PDT 24 Jun 24 06:06:33 PM PDT 24 203968021 ps
T2540 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4222165043 Jun 24 06:06:31 PM PDT 24 Jun 24 06:06:35 PM PDT 24 219139913 ps
T2541 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4222183982 Jun 24 06:06:26 PM PDT 24 Jun 24 06:06:31 PM PDT 24 94433038 ps
T2542 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.198359575 Jun 24 06:06:30 PM PDT 24 Jun 24 06:06:33 PM PDT 24 48224592 ps
T2543 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.741831700 Jun 24 06:06:30 PM PDT 24 Jun 24 06:06:33 PM PDT 24 73155208 ps
T2544 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3246304463 Jun 24 06:06:23 PM PDT 24 Jun 24 06:06:27 PM PDT 24 77823838 ps
T2545 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1695376820 Jun 24 06:06:33 PM PDT 24 Jun 24 06:06:37 PM PDT 24 63284181 ps
T2546 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3495817163 Jun 24 06:06:40 PM PDT 24 Jun 24 06:06:43 PM PDT 24 58282143 ps
T2547 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3845459742 Jun 24 06:06:22 PM PDT 24 Jun 24 06:06:25 PM PDT 24 123953327 ps
T2548 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2352776376 Jun 24 06:06:24 PM PDT 24 Jun 24 06:06:26 PM PDT 24 44456687 ps
T2549 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2087924029 Jun 24 06:06:31 PM PDT 24 Jun 24 06:06:34 PM PDT 24 49862563 ps
T2550 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1848052334 Jun 24 06:06:26 PM PDT 24 Jun 24 06:06:36 PM PDT 24 642850068 ps
T292 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1816854229 Jun 24 06:06:42 PM PDT 24 Jun 24 06:06:45 PM PDT 24 36123638 ps
T2551 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.25734008 Jun 24 06:06:34 PM PDT 24 Jun 24 06:06:39 PM PDT 24 383838388 ps
T2552 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3486847833 Jun 24 06:06:33 PM PDT 24 Jun 24 06:06:37 PM PDT 24 55254593 ps
T2553 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1680103907 Jun 24 06:06:18 PM PDT 24 Jun 24 06:06:23 PM PDT 24 144482885 ps
T2554 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2891061319 Jun 24 06:06:24 PM PDT 24 Jun 24 06:06:26 PM PDT 24 36514248 ps
T2555 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1719079887 Jun 24 06:06:32 PM PDT 24 Jun 24 06:06:35 PM PDT 24 95727073 ps
T2556 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2213983677 Jun 24 06:06:41 PM PDT 24 Jun 24 06:06:44 PM PDT 24 36966077 ps
T2557 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1000014919 Jun 24 06:06:24 PM PDT 24 Jun 24 06:06:29 PM PDT 24 305598625 ps
T2558 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3617777488 Jun 24 06:06:29 PM PDT 24 Jun 24 06:06:32 PM PDT 24 183881213 ps
T300 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.407864504 Jun 24 06:06:36 PM PDT 24 Jun 24 06:06:41 PM PDT 24 423391744 ps
T301 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.39742829 Jun 24 06:06:38 PM PDT 24 Jun 24 06:06:44 PM PDT 24 805357997 ps
T2559 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3631067586 Jun 24 06:06:30 PM PDT 24 Jun 24 06:06:33 PM PDT 24 62724903 ps
T2560 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.192984332 Jun 24 06:06:34 PM PDT 24 Jun 24 06:06:37 PM PDT 24 58238060 ps
T2561 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.239783029 Jun 24 06:06:33 PM PDT 24 Jun 24 06:06:37 PM PDT 24 159274964 ps
T2562 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2294310430 Jun 24 06:06:39 PM PDT 24 Jun 24 06:06:42 PM PDT 24 37359581 ps
T2563 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2412201556 Jun 24 06:06:28 PM PDT 24 Jun 24 06:06:32 PM PDT 24 180779066 ps
T2564 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2191752875 Jun 24 06:06:29 PM PDT 24 Jun 24 06:06:33 PM PDT 24 240568013 ps
T2565 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2821965353 Jun 24 06:06:41 PM PDT 24 Jun 24 06:06:45 PM PDT 24 43752147 ps
T2566 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2687449175 Jun 24 06:06:35 PM PDT 24 Jun 24 06:06:41 PM PDT 24 300969237 ps
T2567 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3046105755 Jun 24 06:06:25 PM PDT 24 Jun 24 06:06:28 PM PDT 24 119757029 ps
T2568 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.4113905626 Jun 24 06:06:38 PM PDT 24 Jun 24 06:06:40 PM PDT 24 37045415 ps
T2569 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1193535621 Jun 24 06:06:30 PM PDT 24 Jun 24 06:06:33 PM PDT 24 62161662 ps
T2570 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2363926045 Jun 24 06:06:29 PM PDT 24 Jun 24 06:06:33 PM PDT 24 197947711 ps
T2571 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.953576953 Jun 24 06:06:26 PM PDT 24 Jun 24 06:06:29 PM PDT 24 69688189 ps
T2572 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3859328773 Jun 24 06:06:39 PM PDT 24 Jun 24 06:06:43 PM PDT 24 44865949 ps
T2573 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.794131500 Jun 24 06:06:21 PM PDT 24 Jun 24 06:06:23 PM PDT 24 43088246 ps
T2574 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3336970162 Jun 24 06:06:25 PM PDT 24 Jun 24 06:06:30 PM PDT 24 77377995 ps
T2575 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1576060459 Jun 24 06:06:34 PM PDT 24 Jun 24 06:06:37 PM PDT 24 76194023 ps
T2576 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2587343300 Jun 24 06:06:28 PM PDT 24 Jun 24 06:06:32 PM PDT 24 325054137 ps
T2577 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1278882316 Jun 24 06:06:39 PM PDT 24 Jun 24 06:06:44 PM PDT 24 217594740 ps
T2578 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1050978106 Jun 24 06:06:35 PM PDT 24 Jun 24 06:06:38 PM PDT 24 39735117 ps
T297 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1670621351 Jun 24 06:06:32 PM PDT 24 Jun 24 06:06:37 PM PDT 24 422992177 ps
T2579 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3741763863 Jun 24 06:06:30 PM PDT 24 Jun 24 06:06:34 PM PDT 24 179018108 ps
T2580 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.423793814 Jun 24 06:06:34 PM PDT 24 Jun 24 06:06:38 PM PDT 24 263890997 ps
T2581 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3761916721 Jun 24 06:06:28 PM PDT 24 Jun 24 06:06:32 PM PDT 24 209079082 ps
T2582 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3184156743 Jun 24 06:06:36 PM PDT 24 Jun 24 06:06:40 PM PDT 24 87417939 ps
T2583 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2095453368 Jun 24 06:06:20 PM PDT 24 Jun 24 06:06:22 PM PDT 24 62929361 ps
T2584 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4155708371 Jun 24 06:06:23 PM PDT 24 Jun 24 06:06:26 PM PDT 24 103494609 ps
T2585 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2780568117 Jun 24 06:06:15 PM PDT 24 Jun 24 06:06:21 PM PDT 24 260520552 ps
T2586 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3713079952 Jun 24 06:06:30 PM PDT 24 Jun 24 06:06:34 PM PDT 24 99445654 ps
T2587 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.376453282 Jun 24 06:06:42 PM PDT 24 Jun 24 06:06:45 PM PDT 24 124442731 ps
T2588 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.4031163466 Jun 24 06:06:31 PM PDT 24 Jun 24 06:06:33 PM PDT 24 54429769 ps
T2589 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1523339046 Jun 24 06:06:25 PM PDT 24 Jun 24 06:06:28 PM PDT 24 60066286 ps
T2590 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3362585347 Jun 24 06:06:40 PM PDT 24 Jun 24 06:06:43 PM PDT 24 40721788 ps
T295 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3863226408 Jun 24 06:06:34 PM PDT 24 Jun 24 06:06:40 PM PDT 24 229774622 ps
T2591 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1335488534 Jun 24 06:06:34 PM PDT 24 Jun 24 06:06:38 PM PDT 24 94853521 ps
T2592 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2742211688 Jun 24 06:06:30 PM PDT 24 Jun 24 06:06:34 PM PDT 24 247304062 ps
T2593 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3275645499 Jun 24 06:06:23 PM PDT 24 Jun 24 06:06:27 PM PDT 24 105169550 ps
T2594 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3921022833 Jun 24 06:06:34 PM PDT 24 Jun 24 06:06:39 PM PDT 24 133776276 ps
T2595 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2297489475 Jun 24 06:06:32 PM PDT 24 Jun 24 06:06:35 PM PDT 24 47840152 ps
T2596 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3421886599 Jun 24 06:06:32 PM PDT 24 Jun 24 06:06:36 PM PDT 24 414693802 ps
T2597 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3881053281 Jun 24 06:06:27 PM PDT 24 Jun 24 06:06:30 PM PDT 24 79232675 ps
T2598 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1317314179 Jun 24 06:06:31 PM PDT 24 Jun 24 06:06:35 PM PDT 24 467763876 ps
T2599 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1308575716 Jun 24 06:06:26 PM PDT 24 Jun 24 06:06:31 PM PDT 24 99044978 ps
T2600 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4109680935 Jun 24 06:06:39 PM PDT 24 Jun 24 06:06:43 PM PDT 24 136919532 ps
T2601 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2328977080 Jun 24 06:06:42 PM PDT 24 Jun 24 06:06:45 PM PDT 24 45394549 ps
T298 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3196710845 Jun 24 06:06:34 PM PDT 24 Jun 24 06:06:40 PM PDT 24 386398955 ps
T2602 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3286315383 Jun 24 06:06:33 PM PDT 24 Jun 24 06:06:36 PM PDT 24 47072814 ps
T2603 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3417664199 Jun 24 06:06:25 PM PDT 24 Jun 24 06:06:29 PM PDT 24 104133332 ps
T299 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1638813295 Jun 24 06:06:32 PM PDT 24 Jun 24 06:06:39 PM PDT 24 1015625704 ps
T2604 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3846311580 Jun 24 06:06:22 PM PDT 24 Jun 24 06:06:24 PM PDT 24 175170437 ps
T2605 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2428475031 Jun 24 06:06:27 PM PDT 24 Jun 24 06:06:31 PM PDT 24 119715110 ps
T2606 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.331972841 Jun 24 06:06:27 PM PDT 24 Jun 24 06:06:31 PM PDT 24 56115695 ps
T2607 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1353208119 Jun 24 06:06:32 PM PDT 24 Jun 24 06:06:35 PM PDT 24 111996024 ps
T249 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1058794147 Jun 24 06:06:27 PM PDT 24 Jun 24 06:06:34 PM PDT 24 476167529 ps
T2608 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1571372403 Jun 24 06:06:26 PM PDT 24 Jun 24 06:06:31 PM PDT 24 256762388 ps
T302 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1565279648 Jun 24 06:06:35 PM PDT 24 Jun 24 06:06:44 PM PDT 24 919633462 ps
T2609 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.58720619 Jun 24 06:06:23 PM PDT 24 Jun 24 06:06:27 PM PDT 24 301496771 ps
T2610 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3893176312 Jun 24 06:06:24 PM PDT 24 Jun 24 06:06:31 PM PDT 24 1213127185 ps
T2611 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3700593239 Jun 24 06:06:34 PM PDT 24 Jun 24 06:06:40 PM PDT 24 328472163 ps
T2612 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.174294746 Jun 24 06:06:42 PM PDT 24 Jun 24 06:06:45 PM PDT 24 51831846 ps
T2613 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3835568315 Jun 24 06:06:41 PM PDT 24 Jun 24 06:06:44 PM PDT 24 39798766 ps
T2614 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.433049424 Jun 24 06:06:24 PM PDT 24 Jun 24 06:06:35 PM PDT 24 1122507259 ps
T2615 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2133013875 Jun 24 06:06:34 PM PDT 24 Jun 24 06:06:37 PM PDT 24 49650104 ps
T2616 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1961063258 Jun 24 06:06:28 PM PDT 24 Jun 24 06:06:32 PM PDT 24 169343466 ps
T2617 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4123843244 Jun 24 06:06:35 PM PDT 24 Jun 24 06:06:38 PM PDT 24 44876185 ps
T2618 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1086446332 Jun 24 06:06:36 PM PDT 24 Jun 24 06:06:40 PM PDT 24 106027484 ps
T2619 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3899278034 Jun 24 06:06:31 PM PDT 24 Jun 24 06:06:34 PM PDT 24 74374746 ps
T2620 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2330630089 Jun 24 06:06:25 PM PDT 24 Jun 24 06:06:28 PM PDT 24 168661526 ps
T2621 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.136324521 Jun 24 06:06:40 PM PDT 24 Jun 24 06:06:43 PM PDT 24 49245941 ps
T2622 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2971154073 Jun 24 06:06:34 PM PDT 24 Jun 24 06:06:37 PM PDT 24 36640140 ps
T2623 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.22194963 Jun 24 06:06:34 PM PDT 24 Jun 24 06:06:37 PM PDT 24 60025588 ps
T2624 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.844819495 Jun 24 06:06:42 PM PDT 24 Jun 24 06:06:45 PM PDT 24 42550980 ps
T2625 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1082365458 Jun 24 06:06:24 PM PDT 24 Jun 24 06:06:27 PM PDT 24 98491665 ps
T2626 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2132852245 Jun 24 06:06:32 PM PDT 24 Jun 24 06:06:34 PM PDT 24 44598483 ps

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.1326524984
Short name T4
Test name
Test status
Simulation time 10215388311 ps
CPU time 76.22 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:29:25 PM PDT 24
Peak memory 206552 kb
Host smart-6be8f947-3816-48be-ba10-850feaad426d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1326524984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.1326524984
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.548181771
Short name T215
Test name
Test status
Simulation time 45329817 ps
CPU time 0.69 seconds
Started Jun 24 06:06:41 PM PDT 24
Finished Jun 24 06:06:44 PM PDT 24
Peak memory 205776 kb
Host smart-0229b8f0-30f6-49e4-b0cb-247a0712d2b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=548181771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.548181771
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.234925886
Short name T1
Test name
Test status
Simulation time 194435048 ps
CPU time 0.81 seconds
Started Jun 24 05:25:29 PM PDT 24
Finished Jun 24 05:25:34 PM PDT 24
Peak memory 206180 kb
Host smart-dd4ae968-afbe-4413-bbae-2ccb2189262f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23492
5886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.234925886
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3065936865
Short name T8
Test name
Test status
Simulation time 23374920487 ps
CPU time 22.85 seconds
Started Jun 24 05:19:53 PM PDT 24
Finished Jun 24 05:20:17 PM PDT 24
Peak memory 206232 kb
Host smart-312bc0c1-ae94-46a9-aaa7-7b803ae161f3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3065936865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3065936865
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2244284693
Short name T203
Test name
Test status
Simulation time 114332986 ps
CPU time 1.41 seconds
Started Jun 24 06:06:36 PM PDT 24
Finished Jun 24 06:06:40 PM PDT 24
Peak memory 214148 kb
Host smart-d4a99ccc-4295-46c7-98c1-cefda91f4b63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244284693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2244284693
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.3005553973
Short name T70
Test name
Test status
Simulation time 11067770807 ps
CPU time 82.84 seconds
Started Jun 24 05:26:10 PM PDT 24
Finished Jun 24 05:27:34 PM PDT 24
Peak memory 206328 kb
Host smart-0f64800f-be5a-413c-a3b9-0fde1abb5e57
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3005553973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.3005553973
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.3600736247
Short name T319
Test name
Test status
Simulation time 174450777 ps
CPU time 0.81 seconds
Started Jun 24 05:27:17 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206180 kb
Host smart-a0edd150-8cae-40c3-ba3f-991ad0c82c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36007
36247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.3600736247
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.300704107
Short name T103
Test name
Test status
Simulation time 400499237 ps
CPU time 1.23 seconds
Started Jun 24 05:24:41 PM PDT 24
Finished Jun 24 05:24:46 PM PDT 24
Peak memory 205292 kb
Host smart-52c50a86-398a-4422-b86d-061b276412a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30070
4107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.300704107
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.1907143676
Short name T39
Test name
Test status
Simulation time 14374426933 ps
CPU time 291.26 seconds
Started Jun 24 05:21:52 PM PDT 24
Finished Jun 24 05:26:45 PM PDT 24
Peak memory 206328 kb
Host smart-d3e21988-db19-4244-93af-0623f7dc87ad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1907143676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.1907143676
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.294060620
Short name T282
Test name
Test status
Simulation time 54464414 ps
CPU time 0.66 seconds
Started Jun 24 06:06:34 PM PDT 24
Finished Jun 24 06:06:37 PM PDT 24
Peak memory 205976 kb
Host smart-55a0203e-7048-41fe-99d9-1188f90c0104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=294060620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.294060620
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2467623056
Short name T119
Test name
Test status
Simulation time 206693738 ps
CPU time 0.88 seconds
Started Jun 24 05:22:36 PM PDT 24
Finished Jun 24 05:22:39 PM PDT 24
Peak memory 206176 kb
Host smart-a7af4b8a-a755-476d-b3dd-d40e4b49ff6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24676
23056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2467623056
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2555863962
Short name T43
Test name
Test status
Simulation time 139611376 ps
CPU time 0.73 seconds
Started Jun 24 05:22:05 PM PDT 24
Finished Jun 24 05:22:07 PM PDT 24
Peak memory 206172 kb
Host smart-0a0893f0-4d71-4d62-8d5f-f85d7b710e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25558
63962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2555863962
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2247836118
Short name T232
Test name
Test status
Simulation time 733660670 ps
CPU time 4.46 seconds
Started Jun 24 06:06:30 PM PDT 24
Finished Jun 24 06:06:36 PM PDT 24
Peak memory 206100 kb
Host smart-844525db-bed2-4b12-b481-806f951feb28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2247836118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2247836118
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.1031320957
Short name T137
Test name
Test status
Simulation time 218410925 ps
CPU time 0.9 seconds
Started Jun 24 05:20:57 PM PDT 24
Finished Jun 24 05:21:02 PM PDT 24
Peak memory 206128 kb
Host smart-a8672bce-d1fd-4d41-8ed9-fc3d5fa5bf47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10313
20957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1031320957
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.2896261047
Short name T577
Test name
Test status
Simulation time 467514773 ps
CPU time 1.33 seconds
Started Jun 24 05:22:35 PM PDT 24
Finished Jun 24 05:22:37 PM PDT 24
Peak memory 206176 kb
Host smart-d818c22c-1f2a-4ddd-aec5-1463e3b9e95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28962
61047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.2896261047
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.3014700824
Short name T24
Test name
Test status
Simulation time 45750654 ps
CPU time 0.7 seconds
Started Jun 24 05:27:56 PM PDT 24
Finished Jun 24 05:28:00 PM PDT 24
Peak memory 206184 kb
Host smart-84353d52-75e9-4994-9209-6acb25e150fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30147
00824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.3014700824
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1005277328
Short name T200
Test name
Test status
Simulation time 279560752 ps
CPU time 1.19 seconds
Started Jun 24 05:20:07 PM PDT 24
Finished Jun 24 05:20:10 PM PDT 24
Peak memory 223776 kb
Host smart-1c1b9e7d-e4e5-4dc8-84b4-81f8598d48ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1005277328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1005277328
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.3651916176
Short name T79
Test name
Test status
Simulation time 357629282 ps
CPU time 1.03 seconds
Started Jun 24 05:19:57 PM PDT 24
Finished Jun 24 05:20:00 PM PDT 24
Peak memory 206124 kb
Host smart-8126db4a-914c-440a-b3fb-557113ed0ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36519
16176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.3651916176
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.2436964507
Short name T46
Test name
Test status
Simulation time 20178688884 ps
CPU time 18.14 seconds
Started Jun 24 05:19:59 PM PDT 24
Finished Jun 24 05:20:19 PM PDT 24
Peak memory 206236 kb
Host smart-6e3e6d58-dc57-46a2-87ff-f3b4ba047e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24369
64507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.2436964507
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1286908939
Short name T213
Test name
Test status
Simulation time 34953539 ps
CPU time 0.66 seconds
Started Jun 24 06:06:42 PM PDT 24
Finished Jun 24 06:06:45 PM PDT 24
Peak memory 205780 kb
Host smart-3f9b06f2-7aaa-4980-9ead-13a48dbfbcd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1286908939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1286908939
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.3800268591
Short name T109
Test name
Test status
Simulation time 1324734749 ps
CPU time 3.06 seconds
Started Jun 24 05:21:58 PM PDT 24
Finished Jun 24 05:22:02 PM PDT 24
Peak memory 206252 kb
Host smart-d3007d4a-0096-406f-891a-44a2de3993ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38002
68591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.3800268591
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3829303551
Short name T242
Test name
Test status
Simulation time 113161569 ps
CPU time 3.15 seconds
Started Jun 24 06:06:36 PM PDT 24
Finished Jun 24 06:06:41 PM PDT 24
Peak memory 214188 kb
Host smart-a48bdc85-6715-4e49-8550-c109ba705dd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3829303551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3829303551
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1013912961
Short name T206
Test name
Test status
Simulation time 1505445309 ps
CPU time 8.7 seconds
Started Jun 24 06:06:21 PM PDT 24
Finished Jun 24 06:06:31 PM PDT 24
Peak memory 206076 kb
Host smart-255fd64d-fc6c-43c7-aafd-988f677ddd17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1013912961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1013912961
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4139213053
Short name T280
Test name
Test status
Simulation time 50777549 ps
CPU time 0.7 seconds
Started Jun 24 06:06:39 PM PDT 24
Finished Jun 24 06:06:42 PM PDT 24
Peak memory 205792 kb
Host smart-89a63af2-a400-4a22-a61a-e666e310aa41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4139213053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.4139213053
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.2735700082
Short name T73
Test name
Test status
Simulation time 167332882 ps
CPU time 0.76 seconds
Started Jun 24 05:23:40 PM PDT 24
Finished Jun 24 05:23:43 PM PDT 24
Peak memory 206088 kb
Host smart-b18a8f8d-d1bb-4eed-a9be-3eb8e6ff6f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27357
00082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.2735700082
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.586278778
Short name T19
Test name
Test status
Simulation time 174450004 ps
CPU time 0.8 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:33 PM PDT 24
Peak memory 206172 kb
Host smart-a958daa2-a4b4-41cc-9444-15b9b2cbe5ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58627
8778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.586278778
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.3514925809
Short name T15
Test name
Test status
Simulation time 13316848914 ps
CPU time 11.73 seconds
Started Jun 24 05:23:39 PM PDT 24
Finished Jun 24 05:23:52 PM PDT 24
Peak memory 206276 kb
Host smart-7b11a7d3-a31e-40c1-83ce-1747bb3556ef
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3514925809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.3514925809
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3196710845
Short name T298
Test name
Test status
Simulation time 386398955 ps
CPU time 2.64 seconds
Started Jun 24 06:06:34 PM PDT 24
Finished Jun 24 06:06:40 PM PDT 24
Peak memory 206260 kb
Host smart-9c9e4776-fa82-447a-8349-cf8c2b89efb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3196710845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3196710845
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/4.usbdev_device_address.1587907722
Short name T100
Test name
Test status
Simulation time 19949923332 ps
CPU time 37.59 seconds
Started Jun 24 05:20:48 PM PDT 24
Finished Jun 24 05:21:28 PM PDT 24
Peak memory 206368 kb
Host smart-9edd6e27-c03f-48c2-8dd0-b57a81b5d27c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15879
07722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.1587907722
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3065796472
Short name T570
Test name
Test status
Simulation time 151815468 ps
CPU time 0.79 seconds
Started Jun 24 05:22:36 PM PDT 24
Finished Jun 24 05:22:39 PM PDT 24
Peak memory 206176 kb
Host smart-51b152d1-adfa-4072-bada-11ae310eeec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30657
96472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3065796472
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.1573137541
Short name T69
Test name
Test status
Simulation time 588193283 ps
CPU time 1.41 seconds
Started Jun 24 05:20:02 PM PDT 24
Finished Jun 24 05:20:05 PM PDT 24
Peak memory 206172 kb
Host smart-e0da4e57-1583-45ab-b207-57bc814cac21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15731
37541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.1573137541
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.3564052092
Short name T165
Test name
Test status
Simulation time 25560881586 ps
CPU time 618.18 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:31:18 PM PDT 24
Peak memory 206364 kb
Host smart-b0614530-2c64-41f7-b6f9-ddeedcf77c66
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3564052092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.3564052092
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1670621351
Short name T297
Test name
Test status
Simulation time 422992177 ps
CPU time 2.78 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:37 PM PDT 24
Peak memory 206068 kb
Host smart-3b4e758f-3ea8-4fa1-93f4-0f10ce53bd1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1670621351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1670621351
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.2312655288
Short name T792
Test name
Test status
Simulation time 3913616457 ps
CPU time 4.14 seconds
Started Jun 24 05:22:57 PM PDT 24
Finished Jun 24 05:23:02 PM PDT 24
Peak memory 206344 kb
Host smart-ffd7ef9e-cecd-447b-9e12-c0705c02bd44
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2312655288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.2312655288
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.948294708
Short name T56
Test name
Test status
Simulation time 271219309 ps
CPU time 1.05 seconds
Started Jun 24 05:19:57 PM PDT 24
Finished Jun 24 05:19:59 PM PDT 24
Peak memory 206140 kb
Host smart-31cbc06d-f916-41e5-85f5-048ed4de7a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94829
4708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.948294708
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1393339885
Short name T260
Test name
Test status
Simulation time 215543553 ps
CPU time 2.33 seconds
Started Jun 24 06:06:18 PM PDT 24
Finished Jun 24 06:06:22 PM PDT 24
Peak memory 222420 kb
Host smart-77039136-62f9-4f25-8b68-4d2e0a561c1c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1393339885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1393339885
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.4283865294
Short name T87
Test name
Test status
Simulation time 142067477 ps
CPU time 0.74 seconds
Started Jun 24 05:19:52 PM PDT 24
Finished Jun 24 05:19:54 PM PDT 24
Peak memory 206188 kb
Host smart-949a6fc1-4374-45b9-9add-93094e691e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42838
65294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.4283865294
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2352776376
Short name T2548
Test name
Test status
Simulation time 44456687 ps
CPU time 0.67 seconds
Started Jun 24 06:06:24 PM PDT 24
Finished Jun 24 06:06:26 PM PDT 24
Peak memory 205800 kb
Host smart-51d4aff3-ca8d-4b9b-bd40-4438a7fcd7f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2352776376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2352776376
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1565279648
Short name T302
Test name
Test status
Simulation time 919633462 ps
CPU time 5.46 seconds
Started Jun 24 06:06:35 PM PDT 24
Finished Jun 24 06:06:44 PM PDT 24
Peak memory 205988 kb
Host smart-020de746-8138-4c7c-a0c3-f2a7900523ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1565279648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1565279648
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.4231252693
Short name T101
Test name
Test status
Simulation time 34276362271 ps
CPU time 292.51 seconds
Started Jun 24 05:20:17 PM PDT 24
Finished Jun 24 05:25:12 PM PDT 24
Peak memory 206380 kb
Host smart-e134708d-7668-4950-ae2a-8ddbcc6c2af3
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4231252693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.4231252693
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3631067586
Short name T2559
Test name
Test status
Simulation time 62724903 ps
CPU time 1.45 seconds
Started Jun 24 06:06:30 PM PDT 24
Finished Jun 24 06:06:33 PM PDT 24
Peak memory 214240 kb
Host smart-caf48371-a20f-4d84-a8b2-3f1aa728e6ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3631067586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3631067586
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2692061479
Short name T1090
Test name
Test status
Simulation time 1122598630 ps
CPU time 2.36 seconds
Started Jun 24 05:19:48 PM PDT 24
Finished Jun 24 05:19:52 PM PDT 24
Peak memory 206212 kb
Host smart-a48fb77d-103a-4152-b9c3-024285a6284b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26920
61479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2692061479
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.2907901512
Short name T40
Test name
Test status
Simulation time 155291141 ps
CPU time 0.78 seconds
Started Jun 24 05:22:02 PM PDT 24
Finished Jun 24 05:22:04 PM PDT 24
Peak memory 206172 kb
Host smart-b8ef8e20-02a4-4195-8afd-885a3e5918cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29079
01512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.2907901512
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.186658009
Short name T198
Test name
Test status
Simulation time 23367375129 ps
CPU time 24.97 seconds
Started Jun 24 05:20:48 PM PDT 24
Finished Jun 24 05:21:15 PM PDT 24
Peak memory 206144 kb
Host smart-eca9f756-3bc1-45e1-9d3a-db0e6ed28214
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=186658009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.186658009
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3272176997
Short name T386
Test name
Test status
Simulation time 204940501 ps
CPU time 1.32 seconds
Started Jun 24 05:22:01 PM PDT 24
Finished Jun 24 05:22:03 PM PDT 24
Peak memory 206208 kb
Host smart-30734d78-23aa-4cbd-a69f-cbbe372bff08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32721
76997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3272176997
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.2735686085
Short name T90
Test name
Test status
Simulation time 149733163 ps
CPU time 0.78 seconds
Started Jun 24 05:20:39 PM PDT 24
Finished Jun 24 05:20:41 PM PDT 24
Peak memory 206112 kb
Host smart-dce7b3fa-5ef8-471f-b5e0-d30559086f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27356
86085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.2735686085
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.2657385441
Short name T177
Test name
Test status
Simulation time 944410559 ps
CPU time 2.08 seconds
Started Jun 24 05:26:23 PM PDT 24
Finished Jun 24 05:26:26 PM PDT 24
Peak memory 206216 kb
Host smart-ed04ffff-f942-425c-9d18-c8bd642b5e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26573
85441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.2657385441
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.3048990166
Short name T52
Test name
Test status
Simulation time 193743093 ps
CPU time 0.85 seconds
Started Jun 24 05:19:50 PM PDT 24
Finished Jun 24 05:19:52 PM PDT 24
Peak memory 206188 kb
Host smart-42f23dba-8262-4091-aa52-0da9448fd8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30489
90166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3048990166
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.1825572614
Short name T63
Test name
Test status
Simulation time 4172466026 ps
CPU time 9.46 seconds
Started Jun 24 05:19:57 PM PDT 24
Finished Jun 24 05:20:08 PM PDT 24
Peak memory 206320 kb
Host smart-85aeecc7-729d-40a3-9062-0bc065261d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18255
72614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1825572614
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.4057382192
Short name T64
Test name
Test status
Simulation time 185364077 ps
CPU time 0.88 seconds
Started Jun 24 05:19:58 PM PDT 24
Finished Jun 24 05:20:00 PM PDT 24
Peak memory 206172 kb
Host smart-dee67b25-1541-451b-ad0c-442a75ed2eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40573
82192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.4057382192
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.1909611027
Short name T175
Test name
Test status
Simulation time 19380898058 ps
CPU time 455.41 seconds
Started Jun 24 05:19:55 PM PDT 24
Finished Jun 24 05:27:31 PM PDT 24
Peak memory 206388 kb
Host smart-fee5ddf6-8331-472c-8b46-beeeab746e03
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1909611027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.1909611027
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.2449786585
Short name T76
Test name
Test status
Simulation time 170404959 ps
CPU time 0.83 seconds
Started Jun 24 05:20:07 PM PDT 24
Finished Jun 24 05:20:09 PM PDT 24
Peak memory 206176 kb
Host smart-a46f4efb-a48d-4c8c-a7f8-352d6f46a925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24497
86585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.2449786585
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3308007130
Short name T950
Test name
Test status
Simulation time 38987585 ps
CPU time 0.66 seconds
Started Jun 24 05:20:15 PM PDT 24
Finished Jun 24 05:20:18 PM PDT 24
Peak memory 206156 kb
Host smart-6a5463d8-9782-4851-a36a-4d11081f60e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33080
07130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3308007130
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3063038336
Short name T390
Test name
Test status
Simulation time 5243558501 ps
CPU time 51.43 seconds
Started Jun 24 05:22:42 PM PDT 24
Finished Jun 24 05:23:35 PM PDT 24
Peak memory 206256 kb
Host smart-1c74f374-e580-42e4-a8b5-a0484a1e4fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30630
38336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3063038336
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.834912883
Short name T57
Test name
Test status
Simulation time 147469128 ps
CPU time 0.79 seconds
Started Jun 24 05:20:48 PM PDT 24
Finished Jun 24 05:20:52 PM PDT 24
Peak memory 206168 kb
Host smart-0d53c53e-e52f-449b-a3be-d7e9d36f5d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83491
2883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.834912883
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1738914416
Short name T277
Test name
Test status
Simulation time 557169246 ps
CPU time 2.83 seconds
Started Jun 24 06:06:23 PM PDT 24
Finished Jun 24 06:06:27 PM PDT 24
Peak memory 206068 kb
Host smart-34df203d-506c-40ac-94ad-264aadd9729f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1738914416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1738914416
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1058794147
Short name T249
Test name
Test status
Simulation time 476167529 ps
CPU time 3.95 seconds
Started Jun 24 06:06:27 PM PDT 24
Finished Jun 24 06:06:34 PM PDT 24
Peak memory 206096 kb
Host smart-86c54b6c-cd25-4a64-ad47-0b7f20929e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1058794147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1058794147
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3510873950
Short name T122
Test name
Test status
Simulation time 211691550 ps
CPU time 0.88 seconds
Started Jun 24 05:20:02 PM PDT 24
Finished Jun 24 05:20:04 PM PDT 24
Peak memory 205980 kb
Host smart-240ff552-68f7-4893-8c6b-ea3016fb7043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35108
73950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3510873950
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1279339554
Short name T54
Test name
Test status
Simulation time 380066603 ps
CPU time 1.19 seconds
Started Jun 24 05:20:07 PM PDT 24
Finished Jun 24 05:20:09 PM PDT 24
Peak memory 206088 kb
Host smart-fac136d8-573d-467f-b8aa-30750b148347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12793
39554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1279339554
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.835677839
Short name T226
Test name
Test status
Simulation time 8176608055 ps
CPU time 79.35 seconds
Started Jun 24 05:20:13 PM PDT 24
Finished Jun 24 05:21:33 PM PDT 24
Peak memory 206304 kb
Host smart-7e6c1260-7ffa-4ca9-9099-79d04aa597e2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=835677839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.835677839
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.577585109
Short name T1762
Test name
Test status
Simulation time 181260549 ps
CPU time 0.85 seconds
Started Jun 24 05:20:16 PM PDT 24
Finished Jun 24 05:20:19 PM PDT 24
Peak memory 206188 kb
Host smart-3bcdbe56-a5b0-4897-875b-5bc568ec9f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57758
5109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.577585109
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.4258417881
Short name T150
Test name
Test status
Simulation time 213388554 ps
CPU time 0.87 seconds
Started Jun 24 05:22:01 PM PDT 24
Finished Jun 24 05:22:04 PM PDT 24
Peak memory 206176 kb
Host smart-9a80cbe3-203d-49f5-88e9-a1f48e8442c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42584
17881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.4258417881
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.4021158954
Short name T142
Test name
Test status
Simulation time 277211768 ps
CPU time 1.02 seconds
Started Jun 24 05:22:09 PM PDT 24
Finished Jun 24 05:22:12 PM PDT 24
Peak memory 206180 kb
Host smart-eff1b151-bd99-453c-b7f9-e5fc0e26c4a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40211
58954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.4021158954
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.291835449
Short name T140
Test name
Test status
Simulation time 250821123 ps
CPU time 0.91 seconds
Started Jun 24 05:22:19 PM PDT 24
Finished Jun 24 05:22:21 PM PDT 24
Peak memory 206136 kb
Host smart-2e7b9099-e225-4382-b261-73afb7eb9ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29183
5449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.291835449
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2161609308
Short name T2214
Test name
Test status
Simulation time 211536351 ps
CPU time 0.84 seconds
Started Jun 24 05:22:32 PM PDT 24
Finished Jun 24 05:22:34 PM PDT 24
Peak memory 206104 kb
Host smart-a012ad42-e4d1-4416-a89f-940d73df5c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21616
09308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2161609308
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.443996111
Short name T2252
Test name
Test status
Simulation time 10689716003 ps
CPU time 24.7 seconds
Started Jun 24 05:22:39 PM PDT 24
Finished Jun 24 05:23:04 PM PDT 24
Peak memory 206360 kb
Host smart-5239fc44-3e71-45aa-9ce4-8294ed00d586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44399
6111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.443996111
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.523065307
Short name T136
Test name
Test status
Simulation time 197937565 ps
CPU time 0.92 seconds
Started Jun 24 05:22:53 PM PDT 24
Finished Jun 24 05:22:56 PM PDT 24
Peak memory 206176 kb
Host smart-72e34d2a-ed3b-426d-ae24-06944910360f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52306
5307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.523065307
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3851591332
Short name T182
Test name
Test status
Simulation time 6175388769 ps
CPU time 13.84 seconds
Started Jun 24 05:22:47 PM PDT 24
Finished Jun 24 05:23:01 PM PDT 24
Peak memory 206420 kb
Host smart-fc45a267-87ac-4a71-9ed5-53b2111bdf16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38515
91332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3851591332
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.3740467122
Short name T116
Test name
Test status
Simulation time 13308614538 ps
CPU time 94.54 seconds
Started Jun 24 05:23:29 PM PDT 24
Finished Jun 24 05:25:05 PM PDT 24
Peak memory 206368 kb
Host smart-fbf33171-b890-4e48-8977-5f9e22897265
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3740467122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.3740467122
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2032392649
Short name T146
Test name
Test status
Simulation time 215027749 ps
CPU time 0.85 seconds
Started Jun 24 05:23:39 PM PDT 24
Finished Jun 24 05:23:42 PM PDT 24
Peak memory 206068 kb
Host smart-3dbc3424-e1aa-4ac0-b55a-d2bdad17fbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20323
92649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2032392649
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.4054536658
Short name T144
Test name
Test status
Simulation time 175476187 ps
CPU time 0.79 seconds
Started Jun 24 05:23:47 PM PDT 24
Finished Jun 24 05:23:50 PM PDT 24
Peak memory 206416 kb
Host smart-b09bd77e-364b-44cc-a36d-afeee05cd1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40545
36658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.4054536658
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.3259188893
Short name T130
Test name
Test status
Simulation time 209241750 ps
CPU time 0.86 seconds
Started Jun 24 05:24:11 PM PDT 24
Finished Jun 24 05:24:13 PM PDT 24
Peak memory 206152 kb
Host smart-dbdd5d48-10af-4824-bb9a-09422c50beec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32591
88893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3259188893
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.367247341
Short name T149
Test name
Test status
Simulation time 228507615 ps
CPU time 0.9 seconds
Started Jun 24 05:20:41 PM PDT 24
Finished Jun 24 05:20:44 PM PDT 24
Peak memory 206168 kb
Host smart-7aedf517-b3bd-45b2-9805-0deccd264dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36724
7341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.367247341
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1680103907
Short name T2553
Test name
Test status
Simulation time 144482885 ps
CPU time 3.49 seconds
Started Jun 24 06:06:18 PM PDT 24
Finished Jun 24 06:06:23 PM PDT 24
Peak memory 206136 kb
Host smart-026f354a-ae9a-4c0b-b740-7ac9d8e1bc62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1680103907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1680103907
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1472292355
Short name T2529
Test name
Test status
Simulation time 77858494 ps
CPU time 0.85 seconds
Started Jun 24 06:06:18 PM PDT 24
Finished Jun 24 06:06:21 PM PDT 24
Peak memory 205976 kb
Host smart-b4a15361-4b49-4cef-9eba-e8f349f51c11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1472292355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1472292355
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.721309942
Short name T251
Test name
Test status
Simulation time 237708022 ps
CPU time 1.95 seconds
Started Jun 24 06:06:24 PM PDT 24
Finished Jun 24 06:06:28 PM PDT 24
Peak memory 214132 kb
Host smart-84ae6842-c4ac-49f6-9840-df9f587a1d0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721309942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.721309942
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2095453368
Short name T2583
Test name
Test status
Simulation time 62929361 ps
CPU time 0.83 seconds
Started Jun 24 06:06:20 PM PDT 24
Finished Jun 24 06:06:22 PM PDT 24
Peak memory 205872 kb
Host smart-6c497c97-54bc-4bd5-a332-46b89dc5fbea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2095453368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2095453368
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.794131500
Short name T2573
Test name
Test status
Simulation time 43088246 ps
CPU time 0.68 seconds
Started Jun 24 06:06:21 PM PDT 24
Finished Jun 24 06:06:23 PM PDT 24
Peak memory 205780 kb
Host smart-7008cfae-3c1f-4a33-879e-4dfe649c11e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=794131500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.794131500
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2308413182
Short name T2525
Test name
Test status
Simulation time 740342495 ps
CPU time 4.61 seconds
Started Jun 24 06:06:21 PM PDT 24
Finished Jun 24 06:06:27 PM PDT 24
Peak memory 206012 kb
Host smart-de0f652b-7842-443b-9f01-0b652edd0ae5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2308413182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2308413182
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.988543534
Short name T272
Test name
Test status
Simulation time 190623851 ps
CPU time 1.18 seconds
Started Jun 24 06:06:23 PM PDT 24
Finished Jun 24 06:06:26 PM PDT 24
Peak memory 206108 kb
Host smart-e690546f-1543-48bf-bb37-455192c31c22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=988543534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.988543534
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2780568117
Short name T2585
Test name
Test status
Simulation time 260520552 ps
CPU time 3.24 seconds
Started Jun 24 06:06:15 PM PDT 24
Finished Jun 24 06:06:21 PM PDT 24
Peak memory 222060 kb
Host smart-162e73c9-3f3b-470f-b470-b8be803a12a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2780568117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2780568117
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2415438565
Short name T293
Test name
Test status
Simulation time 539512932 ps
CPU time 4.37 seconds
Started Jun 24 06:06:22 PM PDT 24
Finished Jun 24 06:06:27 PM PDT 24
Peak memory 206036 kb
Host smart-25077d60-a568-425b-9e0a-50e2ee7423b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2415438565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2415438565
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2147654922
Short name T258
Test name
Test status
Simulation time 311450730 ps
CPU time 3.6 seconds
Started Jun 24 06:06:24 PM PDT 24
Finished Jun 24 06:06:29 PM PDT 24
Peak memory 205964 kb
Host smart-d26c5fb3-ac83-4d68-9cac-a7857f5a3faf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2147654922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2147654922
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.433049424
Short name T2614
Test name
Test status
Simulation time 1122507259 ps
CPU time 9.64 seconds
Started Jun 24 06:06:24 PM PDT 24
Finished Jun 24 06:06:35 PM PDT 24
Peak memory 206028 kb
Host smart-daf0eaa3-f17f-42a7-845b-0938ff5d70da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=433049424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.433049424
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.953576953
Short name T2571
Test name
Test status
Simulation time 69688189 ps
CPU time 0.82 seconds
Started Jun 24 06:06:26 PM PDT 24
Finished Jun 24 06:06:29 PM PDT 24
Peak memory 205852 kb
Host smart-bac51eae-8b1f-4e42-920d-060f3042a50e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=953576953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.953576953
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4222183982
Short name T2541
Test name
Test status
Simulation time 94433038 ps
CPU time 2.15 seconds
Started Jun 24 06:06:26 PM PDT 24
Finished Jun 24 06:06:31 PM PDT 24
Peak memory 214272 kb
Host smart-aa41ddb8-fec0-4c9a-80d0-df7aef59433f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222183982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.4222183982
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.706153354
Short name T267
Test name
Test status
Simulation time 62229576 ps
CPU time 1.02 seconds
Started Jun 24 06:06:27 PM PDT 24
Finished Jun 24 06:06:30 PM PDT 24
Peak memory 206116 kb
Host smart-a1bf2448-f273-444a-979e-2ee5dfe9a5d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=706153354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.706153354
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2428475031
Short name T2605
Test name
Test status
Simulation time 119715110 ps
CPU time 1.45 seconds
Started Jun 24 06:06:27 PM PDT 24
Finished Jun 24 06:06:31 PM PDT 24
Peak memory 214156 kb
Host smart-13e361b5-653c-4851-bc7e-194702443b2a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2428475031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2428475031
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3275645499
Short name T2593
Test name
Test status
Simulation time 105169550 ps
CPU time 2.37 seconds
Started Jun 24 06:06:23 PM PDT 24
Finished Jun 24 06:06:27 PM PDT 24
Peak memory 205980 kb
Host smart-cc3dd5cd-12a7-421c-879f-22a64fbfdf55
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3275645499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3275645499
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4155708371
Short name T2584
Test name
Test status
Simulation time 103494609 ps
CPU time 1.12 seconds
Started Jun 24 06:06:23 PM PDT 24
Finished Jun 24 06:06:26 PM PDT 24
Peak memory 206028 kb
Host smart-a21e0e40-1e34-4ef2-8fb7-e6ca9b603d47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4155708371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.4155708371
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3899199775
Short name T243
Test name
Test status
Simulation time 243375442 ps
CPU time 2.54 seconds
Started Jun 24 06:06:44 PM PDT 24
Finished Jun 24 06:06:48 PM PDT 24
Peak memory 222188 kb
Host smart-2605949c-2af4-48a0-8ff0-4a23dc0d1fda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3899199775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3899199775
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.219039754
Short name T2522
Test name
Test status
Simulation time 351753809 ps
CPU time 2.51 seconds
Started Jun 24 06:06:24 PM PDT 24
Finished Jun 24 06:06:29 PM PDT 24
Peak memory 206120 kb
Host smart-87e812c5-5efb-4c2e-b082-37e6566a30bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=219039754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.219039754
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2852749989
Short name T236
Test name
Test status
Simulation time 66769756 ps
CPU time 1.71 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:36 PM PDT 24
Peak memory 214212 kb
Host smart-c73502e2-d6e6-45be-9587-72f69c9161ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852749989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2852749989
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2313782808
Short name T2535
Test name
Test status
Simulation time 76209567 ps
CPU time 0.98 seconds
Started Jun 24 06:06:31 PM PDT 24
Finished Jun 24 06:06:34 PM PDT 24
Peak memory 206088 kb
Host smart-26eb7510-0430-4673-bb18-624fda3682f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2313782808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2313782808
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3486847833
Short name T2552
Test name
Test status
Simulation time 55254593 ps
CPU time 0.73 seconds
Started Jun 24 06:06:33 PM PDT 24
Finished Jun 24 06:06:37 PM PDT 24
Peak memory 205780 kb
Host smart-5a5dd140-67da-4389-8edb-897011311598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3486847833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3486847833
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3740855518
Short name T269
Test name
Test status
Simulation time 160063676 ps
CPU time 1.56 seconds
Started Jun 24 06:06:35 PM PDT 24
Finished Jun 24 06:06:39 PM PDT 24
Peak memory 206136 kb
Host smart-5c974c67-7e58-4460-8300-f145b6a43988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3740855518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3740855518
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.741853860
Short name T233
Test name
Test status
Simulation time 84464916 ps
CPU time 1.78 seconds
Started Jun 24 06:06:31 PM PDT 24
Finished Jun 24 06:06:35 PM PDT 24
Peak memory 206072 kb
Host smart-b7a37bcc-5925-4e34-bcb6-75fe4fb19858
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=741853860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.741853860
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.935543685
Short name T227
Test name
Test status
Simulation time 846297466 ps
CPU time 4.87 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:39 PM PDT 24
Peak memory 206180 kb
Host smart-666b765a-0ee9-4152-bc30-c09725dfe153
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=935543685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.935543685
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2253079120
Short name T204
Test name
Test status
Simulation time 133698467 ps
CPU time 1.25 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:35 PM PDT 24
Peak memory 214168 kb
Host smart-8531e70b-6658-4e87-bbd2-2cb8d539fa21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253079120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2253079120
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2297489475
Short name T2595
Test name
Test status
Simulation time 47840152 ps
CPU time 0.83 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:35 PM PDT 24
Peak memory 205968 kb
Host smart-7ddf5cbe-43dd-4cb0-bf62-c63fe7e6cf57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2297489475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2297489475
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2132852245
Short name T2626
Test name
Test status
Simulation time 44598483 ps
CPU time 0.65 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:34 PM PDT 24
Peak memory 205788 kb
Host smart-3a63fdb0-222e-4c5d-894e-008a2dcc2c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2132852245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2132852245
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1657669957
Short name T271
Test name
Test status
Simulation time 152224713 ps
CPU time 1.57 seconds
Started Jun 24 06:06:31 PM PDT 24
Finished Jun 24 06:06:35 PM PDT 24
Peak memory 206088 kb
Host smart-3ac9b59f-6f2d-4ced-8169-c923c4b19ba2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1657669957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.1657669957
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1664434255
Short name T245
Test name
Test status
Simulation time 79881259 ps
CPU time 2.05 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:36 PM PDT 24
Peak memory 221752 kb
Host smart-cd2d7772-a160-471e-83a0-9dc4884b0ab4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1664434255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1664434255
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1317314179
Short name T2598
Test name
Test status
Simulation time 467763876 ps
CPU time 2.63 seconds
Started Jun 24 06:06:31 PM PDT 24
Finished Jun 24 06:06:35 PM PDT 24
Peak memory 206060 kb
Host smart-7c3c4f97-0d95-4bee-ac71-db2922bd6525
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1317314179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1317314179
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1335488534
Short name T2591
Test name
Test status
Simulation time 94853521 ps
CPU time 1.37 seconds
Started Jun 24 06:06:34 PM PDT 24
Finished Jun 24 06:06:38 PM PDT 24
Peak memory 216024 kb
Host smart-65037c34-929d-4319-91ca-ae8e3abc4ac9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335488534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1335488534
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1050978106
Short name T2578
Test name
Test status
Simulation time 39735117 ps
CPU time 0.78 seconds
Started Jun 24 06:06:35 PM PDT 24
Finished Jun 24 06:06:38 PM PDT 24
Peak memory 205780 kb
Host smart-3cf4b60c-e574-4503-9880-2a6ca9b78f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1050978106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1050978106
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2133013875
Short name T2615
Test name
Test status
Simulation time 49650104 ps
CPU time 0.68 seconds
Started Jun 24 06:06:34 PM PDT 24
Finished Jun 24 06:06:37 PM PDT 24
Peak memory 205784 kb
Host smart-c7c099f7-cdaa-4cae-b17a-552a79fc74ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2133013875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2133013875
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.376453282
Short name T2587
Test name
Test status
Simulation time 124442731 ps
CPU time 1.2 seconds
Started Jun 24 06:06:42 PM PDT 24
Finished Jun 24 06:06:45 PM PDT 24
Peak memory 205816 kb
Host smart-1458a3d9-a0bd-4336-ba32-e20b9d8ad622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=376453282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.376453282
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3225290044
Short name T248
Test name
Test status
Simulation time 208157701 ps
CPU time 2.91 seconds
Started Jun 24 06:06:35 PM PDT 24
Finished Jun 24 06:06:40 PM PDT 24
Peak memory 206092 kb
Host smart-d200899c-b6b7-4247-a557-795abef7a51c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3225290044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3225290044
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3863226408
Short name T295
Test name
Test status
Simulation time 229774622 ps
CPU time 2.48 seconds
Started Jun 24 06:06:34 PM PDT 24
Finished Jun 24 06:06:40 PM PDT 24
Peak memory 206064 kb
Host smart-b9bedd5d-82b3-4640-87e3-a96eb818d78e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3863226408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3863226408
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3713079952
Short name T2586
Test name
Test status
Simulation time 99445654 ps
CPU time 2.5 seconds
Started Jun 24 06:06:30 PM PDT 24
Finished Jun 24 06:06:34 PM PDT 24
Peak memory 214192 kb
Host smart-d5b58da2-b979-46a8-ac4f-6e914d35954c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713079952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.3713079952
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3724125777
Short name T2524
Test name
Test status
Simulation time 75005295 ps
CPU time 1.07 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:35 PM PDT 24
Peak memory 206084 kb
Host smart-2def4661-0fa2-40f4-a8cb-8a0618e1804a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3724125777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3724125777
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.4031163466
Short name T2588
Test name
Test status
Simulation time 54429769 ps
CPU time 0.65 seconds
Started Jun 24 06:06:31 PM PDT 24
Finished Jun 24 06:06:33 PM PDT 24
Peak memory 205704 kb
Host smart-de0898e9-1997-4366-bd0c-08109758a2b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4031163466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.4031163466
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1353208119
Short name T2607
Test name
Test status
Simulation time 111996024 ps
CPU time 1.45 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:35 PM PDT 24
Peak memory 206128 kb
Host smart-86efed03-a357-4ef0-9c3a-34e2ea8ba2ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1353208119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1353208119
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3700593239
Short name T2611
Test name
Test status
Simulation time 328472163 ps
CPU time 3.19 seconds
Started Jun 24 06:06:34 PM PDT 24
Finished Jun 24 06:06:40 PM PDT 24
Peak memory 206072 kb
Host smart-c133dc10-056b-4c5f-a731-532d893cffcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3700593239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3700593239
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2742211688
Short name T2592
Test name
Test status
Simulation time 247304062 ps
CPU time 2.04 seconds
Started Jun 24 06:06:30 PM PDT 24
Finished Jun 24 06:06:34 PM PDT 24
Peak memory 214204 kb
Host smart-f59976f2-1469-4114-ab0f-b59628c77eb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742211688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2742211688
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3499432447
Short name T263
Test name
Test status
Simulation time 78489001 ps
CPU time 1.04 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:35 PM PDT 24
Peak memory 205900 kb
Host smart-be3a3f51-66e8-4040-b1c4-4fdfea776cad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3499432447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3499432447
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3899278034
Short name T2619
Test name
Test status
Simulation time 74374746 ps
CPU time 0.7 seconds
Started Jun 24 06:06:31 PM PDT 24
Finished Jun 24 06:06:34 PM PDT 24
Peak memory 205756 kb
Host smart-fbef7fa6-1758-4aaa-9a50-73a220dd3d67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3899278034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3899278034
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3051386835
Short name T207
Test name
Test status
Simulation time 113570884 ps
CPU time 1.54 seconds
Started Jun 24 06:06:35 PM PDT 24
Finished Jun 24 06:06:40 PM PDT 24
Peak memory 206336 kb
Host smart-cee12739-9661-4d7b-8aef-059c3318ddb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3051386835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3051386835
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4220432400
Short name T247
Test name
Test status
Simulation time 73077175 ps
CPU time 1.72 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:36 PM PDT 24
Peak memory 214208 kb
Host smart-151a0ac5-c3bf-4b76-b759-8f1b3771cab2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4220432400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.4220432400
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3421886599
Short name T2596
Test name
Test status
Simulation time 414693802 ps
CPU time 2.62 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:36 PM PDT 24
Peak memory 206056 kb
Host smart-9a006706-d971-4dbd-a9d1-7d9a54cbfeae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3421886599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3421886599
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.239783029
Short name T2561
Test name
Test status
Simulation time 159274964 ps
CPU time 1.72 seconds
Started Jun 24 06:06:33 PM PDT 24
Finished Jun 24 06:06:37 PM PDT 24
Peak memory 214124 kb
Host smart-64ec8b32-1ec6-4034-9b5a-90fbe14ef8c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239783029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.239783029
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1573787532
Short name T2536
Test name
Test status
Simulation time 38024317 ps
CPU time 0.8 seconds
Started Jun 24 06:06:36 PM PDT 24
Finished Jun 24 06:06:39 PM PDT 24
Peak memory 205868 kb
Host smart-56fed0fd-d021-438e-a4b7-361ab316fca1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1573787532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1573787532
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.25734008
Short name T2551
Test name
Test status
Simulation time 383838388 ps
CPU time 2.01 seconds
Started Jun 24 06:06:34 PM PDT 24
Finished Jun 24 06:06:39 PM PDT 24
Peak memory 206056 kb
Host smart-4c673969-17a9-4678-923d-2661c3c86521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=25734008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.25734008
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2687449175
Short name T2566
Test name
Test status
Simulation time 300969237 ps
CPU time 3.5 seconds
Started Jun 24 06:06:35 PM PDT 24
Finished Jun 24 06:06:41 PM PDT 24
Peak memory 214260 kb
Host smart-e447a55e-b362-4357-ad6d-74c38288f15a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2687449175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2687449175
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.407864504
Short name T300
Test name
Test status
Simulation time 423391744 ps
CPU time 3.02 seconds
Started Jun 24 06:06:36 PM PDT 24
Finished Jun 24 06:06:41 PM PDT 24
Peak memory 206092 kb
Host smart-365eb90f-522a-494c-80a6-fa503f0b3323
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=407864504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.407864504
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3184156743
Short name T2582
Test name
Test status
Simulation time 87417939 ps
CPU time 2.12 seconds
Started Jun 24 06:06:36 PM PDT 24
Finished Jun 24 06:06:40 PM PDT 24
Peak memory 214204 kb
Host smart-b409af54-7188-4afc-9b89-fb3ddfe2a0bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184156743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3184156743
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2087924029
Short name T2549
Test name
Test status
Simulation time 49862563 ps
CPU time 0.79 seconds
Started Jun 24 06:06:31 PM PDT 24
Finished Jun 24 06:06:34 PM PDT 24
Peak memory 205936 kb
Host smart-fd0026b6-194e-485e-85d1-1d13e324db8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2087924029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2087924029
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3611880063
Short name T216
Test name
Test status
Simulation time 47830034 ps
CPU time 0.69 seconds
Started Jun 24 06:06:36 PM PDT 24
Finished Jun 24 06:06:39 PM PDT 24
Peak memory 205784 kb
Host smart-35c04b91-80d3-4b47-8171-9af872320294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3611880063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3611880063
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1695376820
Short name T2545
Test name
Test status
Simulation time 63284181 ps
CPU time 1.16 seconds
Started Jun 24 06:06:33 PM PDT 24
Finished Jun 24 06:06:37 PM PDT 24
Peak memory 206032 kb
Host smart-cce9ad89-ebae-4169-a19c-18791ec0fe98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1695376820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1695376820
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2174857587
Short name T244
Test name
Test status
Simulation time 80868323 ps
CPU time 1.68 seconds
Started Jun 24 06:06:33 PM PDT 24
Finished Jun 24 06:06:37 PM PDT 24
Peak memory 214276 kb
Host smart-6ccb3289-38e2-4bea-b4d2-bdbaf4098966
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2174857587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2174857587
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1133815642
Short name T237
Test name
Test status
Simulation time 82278010 ps
CPU time 1.5 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:36 PM PDT 24
Peak memory 214184 kb
Host smart-6324374d-8e6b-4c20-a918-a84d7b495a2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133815642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1133815642
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3119809681
Short name T265
Test name
Test status
Simulation time 61349772 ps
CPU time 0.86 seconds
Started Jun 24 06:06:34 PM PDT 24
Finished Jun 24 06:06:37 PM PDT 24
Peak memory 205964 kb
Host smart-7e833eb4-5ce1-42ee-869e-c5d2d8b84b25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3119809681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3119809681
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3286315383
Short name T2602
Test name
Test status
Simulation time 47072814 ps
CPU time 0.64 seconds
Started Jun 24 06:06:33 PM PDT 24
Finished Jun 24 06:06:36 PM PDT 24
Peak memory 205752 kb
Host smart-ed082b2a-709e-4419-9a10-465bd27c5730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3286315383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3286315383
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1432295654
Short name T208
Test name
Test status
Simulation time 243134855 ps
CPU time 1.49 seconds
Started Jun 24 06:06:31 PM PDT 24
Finished Jun 24 06:06:34 PM PDT 24
Peak memory 206072 kb
Host smart-2ab3bfe6-c0c7-4405-ada8-e7c46784fced
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1432295654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1432295654
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1086446332
Short name T2618
Test name
Test status
Simulation time 106027484 ps
CPU time 1.58 seconds
Started Jun 24 06:06:36 PM PDT 24
Finished Jun 24 06:06:40 PM PDT 24
Peak memory 206016 kb
Host smart-6c437362-b5a4-49e8-b0ae-f37d554a2eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1086446332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1086446332
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3420882152
Short name T228
Test name
Test status
Simulation time 406293854 ps
CPU time 2.77 seconds
Started Jun 24 06:06:35 PM PDT 24
Finished Jun 24 06:06:40 PM PDT 24
Peak memory 206084 kb
Host smart-92e8f3cd-33bd-4ff7-a906-6e1252a94b23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3420882152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3420882152
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2667741743
Short name T235
Test name
Test status
Simulation time 178259484 ps
CPU time 1.32 seconds
Started Jun 24 06:06:38 PM PDT 24
Finished Jun 24 06:06:41 PM PDT 24
Peak memory 214080 kb
Host smart-081930ba-544f-49d9-bbb1-4d915f9b5f43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667741743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2667741743
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3495817163
Short name T2546
Test name
Test status
Simulation time 58282143 ps
CPU time 0.83 seconds
Started Jun 24 06:06:40 PM PDT 24
Finished Jun 24 06:06:43 PM PDT 24
Peak memory 205904 kb
Host smart-018973dc-e157-4b25-867c-c2484b467eae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3495817163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3495817163
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.4226792324
Short name T2534
Test name
Test status
Simulation time 41165129 ps
CPU time 0.68 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:35 PM PDT 24
Peak memory 205752 kb
Host smart-fa853d63-040e-4c8e-8d5a-acdb1351533e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4226792324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.4226792324
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3300227062
Short name T273
Test name
Test status
Simulation time 94682607 ps
CPU time 1.08 seconds
Started Jun 24 06:06:39 PM PDT 24
Finished Jun 24 06:06:43 PM PDT 24
Peak memory 206072 kb
Host smart-a5c61800-1065-489b-8c35-983364e0e33f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3300227062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3300227062
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.39742829
Short name T301
Test name
Test status
Simulation time 805357997 ps
CPU time 4.73 seconds
Started Jun 24 06:06:38 PM PDT 24
Finished Jun 24 06:06:44 PM PDT 24
Peak memory 206120 kb
Host smart-0dc01892-ac02-41e3-b69e-465ed89b007d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=39742829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.39742829
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2655040618
Short name T268
Test name
Test status
Simulation time 56081787 ps
CPU time 0.87 seconds
Started Jun 24 06:06:35 PM PDT 24
Finished Jun 24 06:06:38 PM PDT 24
Peak memory 205768 kb
Host smart-44817a4d-7bce-40c0-b5bf-f8bd97ae9dff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2655040618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2655040618
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.331713519
Short name T2528
Test name
Test status
Simulation time 39359749 ps
CPU time 0.69 seconds
Started Jun 24 06:06:36 PM PDT 24
Finished Jun 24 06:06:39 PM PDT 24
Peak memory 205780 kb
Host smart-51dfdd5e-a8e1-4c4f-b91d-fbff2112a8f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=331713519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.331713519
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.423793814
Short name T2580
Test name
Test status
Simulation time 263890997 ps
CPU time 1.66 seconds
Started Jun 24 06:06:34 PM PDT 24
Finished Jun 24 06:06:38 PM PDT 24
Peak memory 206084 kb
Host smart-f68aa8e7-bb36-45ed-b634-5bfd7c46b01e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=423793814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.423793814
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1278882316
Short name T2577
Test name
Test status
Simulation time 217594740 ps
CPU time 2.43 seconds
Started Jun 24 06:06:39 PM PDT 24
Finished Jun 24 06:06:44 PM PDT 24
Peak memory 221672 kb
Host smart-8a6aba5b-64ab-400f-b918-bde2389804a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1278882316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1278882316
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1000014919
Short name T2557
Test name
Test status
Simulation time 305598625 ps
CPU time 3.59 seconds
Started Jun 24 06:06:24 PM PDT 24
Finished Jun 24 06:06:29 PM PDT 24
Peak memory 206092 kb
Host smart-fe362186-1899-462e-b6c2-7d6d6215450a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1000014919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1000014919
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1844223703
Short name T261
Test name
Test status
Simulation time 195679618 ps
CPU time 3.92 seconds
Started Jun 24 06:06:25 PM PDT 24
Finished Jun 24 06:06:31 PM PDT 24
Peak memory 206060 kb
Host smart-b1d02b35-e376-49d7-8610-f248dc12278c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1844223703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1844223703
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3881053281
Short name T2597
Test name
Test status
Simulation time 79232675 ps
CPU time 0.8 seconds
Started Jun 24 06:06:27 PM PDT 24
Finished Jun 24 06:06:30 PM PDT 24
Peak memory 205880 kb
Host smart-d178401d-7cd8-43e9-b280-d40be66054de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3881053281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3881053281
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2299635332
Short name T205
Test name
Test status
Simulation time 88443261 ps
CPU time 1.27 seconds
Started Jun 24 06:06:26 PM PDT 24
Finished Jun 24 06:06:29 PM PDT 24
Peak memory 214184 kb
Host smart-ad34b712-9ae8-4b6f-abb6-bb722dc5153f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299635332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2299635332
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.179140074
Short name T2531
Test name
Test status
Simulation time 71525440 ps
CPU time 0.83 seconds
Started Jun 24 06:06:26 PM PDT 24
Finished Jun 24 06:06:29 PM PDT 24
Peak memory 205980 kb
Host smart-8ff18ecd-5c17-4da4-9516-5d84df20e5f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=179140074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.179140074
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3694165210
Short name T286
Test name
Test status
Simulation time 41341046 ps
CPU time 0.67 seconds
Started Jun 24 06:06:25 PM PDT 24
Finished Jun 24 06:06:27 PM PDT 24
Peak memory 205792 kb
Host smart-5d02219d-41d9-4b60-b93b-269b32f17faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3694165210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3694165210
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.957657941
Short name T262
Test name
Test status
Simulation time 180912271 ps
CPU time 2.34 seconds
Started Jun 24 06:06:23 PM PDT 24
Finished Jun 24 06:06:26 PM PDT 24
Peak memory 214168 kb
Host smart-d5baee72-1a04-4592-a06b-813ea6fc5363
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=957657941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.957657941
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3845459742
Short name T2547
Test name
Test status
Simulation time 123953327 ps
CPU time 2.43 seconds
Started Jun 24 06:06:22 PM PDT 24
Finished Jun 24 06:06:25 PM PDT 24
Peak memory 205948 kb
Host smart-73a4f19f-de02-4acb-b42d-11aacccc78a1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3845459742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3845459742
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3617777488
Short name T2558
Test name
Test status
Simulation time 183881213 ps
CPU time 1.61 seconds
Started Jun 24 06:06:29 PM PDT 24
Finished Jun 24 06:06:32 PM PDT 24
Peak memory 206064 kb
Host smart-fa04f8c7-eb95-40ba-8285-d87066e1739c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3617777488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3617777488
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.331972841
Short name T2606
Test name
Test status
Simulation time 56115695 ps
CPU time 1.26 seconds
Started Jun 24 06:06:27 PM PDT 24
Finished Jun 24 06:06:31 PM PDT 24
Peak memory 206044 kb
Host smart-a20bfda0-b5a3-4a20-bee8-3bbfa0e15dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=331972841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.331972841
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.192984332
Short name T2560
Test name
Test status
Simulation time 58238060 ps
CPU time 0.69 seconds
Started Jun 24 06:06:34 PM PDT 24
Finished Jun 24 06:06:37 PM PDT 24
Peak memory 205800 kb
Host smart-e09479bc-96a4-48ab-849d-1a8739f4d2fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=192984332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.192984332
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.22194963
Short name T2623
Test name
Test status
Simulation time 60025588 ps
CPU time 0.73 seconds
Started Jun 24 06:06:34 PM PDT 24
Finished Jun 24 06:06:37 PM PDT 24
Peak memory 205776 kb
Host smart-8647bf80-7cb1-42ae-a0e3-a071fc149af6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=22194963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.22194963
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2971154073
Short name T2622
Test name
Test status
Simulation time 36640140 ps
CPU time 0.7 seconds
Started Jun 24 06:06:34 PM PDT 24
Finished Jun 24 06:06:37 PM PDT 24
Peak memory 205780 kb
Host smart-c5c219fb-d26a-4847-a39c-7baf74797829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2971154073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2971154073
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1097986350
Short name T281
Test name
Test status
Simulation time 42602969 ps
CPU time 0.67 seconds
Started Jun 24 06:06:42 PM PDT 24
Finished Jun 24 06:06:45 PM PDT 24
Peak memory 205504 kb
Host smart-9c6b61c4-fe40-4679-8e2f-ca3c51237703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1097986350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1097986350
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3859328773
Short name T2572
Test name
Test status
Simulation time 44865949 ps
CPU time 0.65 seconds
Started Jun 24 06:06:39 PM PDT 24
Finished Jun 24 06:06:43 PM PDT 24
Peak memory 205728 kb
Host smart-a38e09a2-3dda-4128-90d2-4f4875bbefc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3859328773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3859328773
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.858032975
Short name T278
Test name
Test status
Simulation time 82097148 ps
CPU time 0.75 seconds
Started Jun 24 06:06:37 PM PDT 24
Finished Jun 24 06:06:40 PM PDT 24
Peak memory 205804 kb
Host smart-7abc27a4-2dfe-49e3-aad2-5463df65ffb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=858032975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.858032975
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.844819495
Short name T2624
Test name
Test status
Simulation time 42550980 ps
CPU time 0.7 seconds
Started Jun 24 06:06:42 PM PDT 24
Finished Jun 24 06:06:45 PM PDT 24
Peak memory 205572 kb
Host smart-d589a186-3d10-4358-b428-89dd9468acb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=844819495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.844819495
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4123843244
Short name T2617
Test name
Test status
Simulation time 44876185 ps
CPU time 0.75 seconds
Started Jun 24 06:06:35 PM PDT 24
Finished Jun 24 06:06:38 PM PDT 24
Peak memory 205700 kb
Host smart-8ed8a52c-72f8-4876-a2dc-55dae31fd094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4123843244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.4123843244
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2713946351
Short name T279
Test name
Test status
Simulation time 41287152 ps
CPU time 0.66 seconds
Started Jun 24 06:06:35 PM PDT 24
Finished Jun 24 06:06:38 PM PDT 24
Peak memory 205784 kb
Host smart-7b3f8d51-2baf-431d-af78-cc04bf4c38b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2713946351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2713946351
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.174294746
Short name T2612
Test name
Test status
Simulation time 51831846 ps
CPU time 0.71 seconds
Started Jun 24 06:06:42 PM PDT 24
Finished Jun 24 06:06:45 PM PDT 24
Peak memory 205488 kb
Host smart-a8b76f04-bad1-4372-b43b-036beafa9240
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=174294746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.174294746
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2363926045
Short name T2570
Test name
Test status
Simulation time 197947711 ps
CPU time 2.13 seconds
Started Jun 24 06:06:29 PM PDT 24
Finished Jun 24 06:06:33 PM PDT 24
Peak memory 206012 kb
Host smart-5d6299ad-c1f3-40fd-a637-dad09b072715
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2363926045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2363926045
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1848052334
Short name T2550
Test name
Test status
Simulation time 642850068 ps
CPU time 7.45 seconds
Started Jun 24 06:06:26 PM PDT 24
Finished Jun 24 06:06:36 PM PDT 24
Peak memory 206024 kb
Host smart-a0eada14-68e5-4004-92c3-57d9f645c4f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1848052334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1848052334
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1523339046
Short name T2589
Test name
Test status
Simulation time 60066286 ps
CPU time 0.77 seconds
Started Jun 24 06:06:25 PM PDT 24
Finished Jun 24 06:06:28 PM PDT 24
Peak memory 205884 kb
Host smart-728b9514-3d1b-4294-99ed-21136bd394ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1523339046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1523339046
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2330630089
Short name T2620
Test name
Test status
Simulation time 168661526 ps
CPU time 2.06 seconds
Started Jun 24 06:06:25 PM PDT 24
Finished Jun 24 06:06:28 PM PDT 24
Peak memory 214216 kb
Host smart-36131bb5-dd69-47b5-ab58-72ff0aef4921
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330630089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2330630089
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3812590781
Short name T2538
Test name
Test status
Simulation time 55000779 ps
CPU time 0.82 seconds
Started Jun 24 06:06:21 PM PDT 24
Finished Jun 24 06:06:23 PM PDT 24
Peak memory 205964 kb
Host smart-6bc5c8a7-3c32-42e4-9e18-6dbf6d895923
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3812590781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3812590781
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.180226122
Short name T291
Test name
Test status
Simulation time 44740671 ps
CPU time 0.74 seconds
Started Jun 24 06:06:25 PM PDT 24
Finished Jun 24 06:06:28 PM PDT 24
Peak memory 205784 kb
Host smart-8a0df43d-c612-4847-8ee1-05f72a88a33f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=180226122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.180226122
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1082365458
Short name T2625
Test name
Test status
Simulation time 98491665 ps
CPU time 1.44 seconds
Started Jun 24 06:06:24 PM PDT 24
Finished Jun 24 06:06:27 PM PDT 24
Peak memory 214276 kb
Host smart-86b0156d-86d7-4267-8a47-f781896659a1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1082365458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1082365458
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1308575716
Short name T2599
Test name
Test status
Simulation time 99044978 ps
CPU time 2.38 seconds
Started Jun 24 06:06:26 PM PDT 24
Finished Jun 24 06:06:31 PM PDT 24
Peak memory 205992 kb
Host smart-60b512b5-1be1-46e9-80f1-36066d0d53c1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1308575716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1308575716
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3046105755
Short name T2567
Test name
Test status
Simulation time 119757029 ps
CPU time 1.37 seconds
Started Jun 24 06:06:25 PM PDT 24
Finished Jun 24 06:06:28 PM PDT 24
Peak memory 205772 kb
Host smart-4b129f24-e1ea-4929-b6bb-82f570703c40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3046105755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3046105755
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3336970162
Short name T2574
Test name
Test status
Simulation time 77377995 ps
CPU time 2.16 seconds
Started Jun 24 06:06:25 PM PDT 24
Finished Jun 24 06:06:30 PM PDT 24
Peak memory 221780 kb
Host smart-c90d6bc5-c31a-468b-91d5-9b9e7caefcf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3336970162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3336970162
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2213983677
Short name T2556
Test name
Test status
Simulation time 36966077 ps
CPU time 0.69 seconds
Started Jun 24 06:06:41 PM PDT 24
Finished Jun 24 06:06:44 PM PDT 24
Peak memory 205772 kb
Host smart-e820516d-28b2-4c21-8c9f-aaa92baf8cab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2213983677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2213983677
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.219531118
Short name T289
Test name
Test status
Simulation time 57942503 ps
CPU time 0.69 seconds
Started Jun 24 06:06:39 PM PDT 24
Finished Jun 24 06:06:42 PM PDT 24
Peak memory 205776 kb
Host smart-502e977d-b9ba-42da-8a98-c1f2ebdda941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=219531118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.219531118
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3782593406
Short name T290
Test name
Test status
Simulation time 46224088 ps
CPU time 0.68 seconds
Started Jun 24 06:06:40 PM PDT 24
Finished Jun 24 06:06:43 PM PDT 24
Peak memory 205784 kb
Host smart-46274e9a-21d0-49c7-ab42-8b15d47ff19f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3782593406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3782593406
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3577393485
Short name T2530
Test name
Test status
Simulation time 63684264 ps
CPU time 0.68 seconds
Started Jun 24 06:06:42 PM PDT 24
Finished Jun 24 06:06:45 PM PDT 24
Peak memory 205784 kb
Host smart-4598d684-9d27-446b-964d-f5b6eed3f395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3577393485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3577393485
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3835568315
Short name T2613
Test name
Test status
Simulation time 39798766 ps
CPU time 0.7 seconds
Started Jun 24 06:06:41 PM PDT 24
Finished Jun 24 06:06:44 PM PDT 24
Peak memory 205756 kb
Host smart-5850b0c3-c4a2-42df-8b33-8449a15324d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3835568315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3835568315
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3362585347
Short name T2590
Test name
Test status
Simulation time 40721788 ps
CPU time 0.67 seconds
Started Jun 24 06:06:40 PM PDT 24
Finished Jun 24 06:06:43 PM PDT 24
Peak memory 205784 kb
Host smart-caf63a4f-c5b6-4a18-a85a-f6f83beb116e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3362585347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3362585347
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.4113905626
Short name T2568
Test name
Test status
Simulation time 37045415 ps
CPU time 0.63 seconds
Started Jun 24 06:06:38 PM PDT 24
Finished Jun 24 06:06:40 PM PDT 24
Peak memory 205776 kb
Host smart-8cdf99c6-d5c2-4bf2-b85c-9a63968c1a80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4113905626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.4113905626
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3246304463
Short name T2544
Test name
Test status
Simulation time 77823838 ps
CPU time 1.97 seconds
Started Jun 24 06:06:23 PM PDT 24
Finished Jun 24 06:06:27 PM PDT 24
Peak memory 206036 kb
Host smart-aaf3c707-6562-4ca6-a3a3-87003ca0beae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3246304463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3246304463
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1222058100
Short name T259
Test name
Test status
Simulation time 787226136 ps
CPU time 4.59 seconds
Started Jun 24 06:06:22 PM PDT 24
Finished Jun 24 06:06:27 PM PDT 24
Peak memory 206052 kb
Host smart-7f3aefb7-e905-4eb0-a27a-33cc7391d078
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1222058100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1222058100
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3846311580
Short name T2604
Test name
Test status
Simulation time 175170437 ps
CPU time 1.02 seconds
Started Jun 24 06:06:22 PM PDT 24
Finished Jun 24 06:06:24 PM PDT 24
Peak memory 205960 kb
Host smart-59b99e66-120e-43d8-8e2e-a4c5537ff4d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3846311580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3846311580
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1571372403
Short name T2608
Test name
Test status
Simulation time 256762388 ps
CPU time 2.57 seconds
Started Jun 24 06:06:26 PM PDT 24
Finished Jun 24 06:06:31 PM PDT 24
Peak memory 214156 kb
Host smart-ccd76786-ea6c-4a31-898e-f5a00ec45795
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571372403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1571372403
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.741831700
Short name T2543
Test name
Test status
Simulation time 73155208 ps
CPU time 0.84 seconds
Started Jun 24 06:06:30 PM PDT 24
Finished Jun 24 06:06:33 PM PDT 24
Peak memory 205972 kb
Host smart-fedd67e9-fd07-4614-87f0-ebed3f8d9980
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=741831700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.741831700
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3116726263
Short name T2533
Test name
Test status
Simulation time 60375732 ps
CPU time 0.72 seconds
Started Jun 24 06:06:25 PM PDT 24
Finished Jun 24 06:06:27 PM PDT 24
Peak memory 205580 kb
Host smart-9d9e5762-60c3-4631-bfa1-cf0b05f8ea48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3116726263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3116726263
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1148150120
Short name T264
Test name
Test status
Simulation time 74148365 ps
CPU time 1.43 seconds
Started Jun 24 06:06:23 PM PDT 24
Finished Jun 24 06:06:26 PM PDT 24
Peak memory 214104 kb
Host smart-9ad7d210-0ee9-401b-ba3f-b053f7c75ac1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1148150120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1148150120
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3417664199
Short name T2603
Test name
Test status
Simulation time 104133332 ps
CPU time 2.34 seconds
Started Jun 24 06:06:25 PM PDT 24
Finished Jun 24 06:06:29 PM PDT 24
Peak memory 205980 kb
Host smart-94883fea-08a8-45c2-abea-d9587a55454d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3417664199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3417664199
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1961063258
Short name T2616
Test name
Test status
Simulation time 169343466 ps
CPU time 1.8 seconds
Started Jun 24 06:06:28 PM PDT 24
Finished Jun 24 06:06:32 PM PDT 24
Peak memory 206060 kb
Host smart-753d4c4b-1a5b-4193-affb-051487ae411b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1961063258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1961063258
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3443868775
Short name T246
Test name
Test status
Simulation time 223714361 ps
CPU time 2.42 seconds
Started Jun 24 06:06:27 PM PDT 24
Finished Jun 24 06:06:31 PM PDT 24
Peak memory 221920 kb
Host smart-34e4ed73-6086-4493-94b6-d7ddab6aee1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3443868775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3443868775
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2025805695
Short name T284
Test name
Test status
Simulation time 45006834 ps
CPU time 0.68 seconds
Started Jun 24 06:06:46 PM PDT 24
Finished Jun 24 06:06:47 PM PDT 24
Peak memory 205776 kb
Host smart-b87a7cfe-ed34-4391-96d4-3e467492b960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2025805695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2025805695
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2821965353
Short name T2565
Test name
Test status
Simulation time 43752147 ps
CPU time 0.68 seconds
Started Jun 24 06:06:41 PM PDT 24
Finished Jun 24 06:06:45 PM PDT 24
Peak memory 205780 kb
Host smart-278bd3c3-5b48-4bcd-adee-8acaf0e5d6b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2821965353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2821965353
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1825047410
Short name T285
Test name
Test status
Simulation time 36251539 ps
CPU time 0.66 seconds
Started Jun 24 06:06:41 PM PDT 24
Finished Jun 24 06:06:44 PM PDT 24
Peak memory 205784 kb
Host smart-47a249a4-b3fa-48de-87bd-7d541ab9b28a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1825047410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1825047410
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1816854229
Short name T292
Test name
Test status
Simulation time 36123638 ps
CPU time 0.67 seconds
Started Jun 24 06:06:42 PM PDT 24
Finished Jun 24 06:06:45 PM PDT 24
Peak memory 205788 kb
Host smart-756e38e5-d49b-4afb-b293-6f77d3a83b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1816854229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1816854229
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2294310430
Short name T2562
Test name
Test status
Simulation time 37359581 ps
CPU time 0.7 seconds
Started Jun 24 06:06:39 PM PDT 24
Finished Jun 24 06:06:42 PM PDT 24
Peak memory 205700 kb
Host smart-7383b822-6362-4a83-90e2-50288b439459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2294310430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2294310430
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2328977080
Short name T2601
Test name
Test status
Simulation time 45394549 ps
CPU time 0.69 seconds
Started Jun 24 06:06:42 PM PDT 24
Finished Jun 24 06:06:45 PM PDT 24
Peak memory 205780 kb
Host smart-b2fec385-0198-477f-aea4-3be710e4435a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2328977080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2328977080
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2190740156
Short name T2521
Test name
Test status
Simulation time 43150803 ps
CPU time 0.65 seconds
Started Jun 24 06:06:44 PM PDT 24
Finished Jun 24 06:06:46 PM PDT 24
Peak memory 205736 kb
Host smart-2f587c10-6330-4f33-9ba0-8ba6f67f2765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2190740156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2190740156
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.488524350
Short name T287
Test name
Test status
Simulation time 59148281 ps
CPU time 0.74 seconds
Started Jun 24 06:06:40 PM PDT 24
Finished Jun 24 06:06:44 PM PDT 24
Peak memory 205800 kb
Host smart-4534498a-111f-42ac-acda-b51a63b44d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=488524350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.488524350
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3528662719
Short name T214
Test name
Test status
Simulation time 47719036 ps
CPU time 0.68 seconds
Started Jun 24 06:06:40 PM PDT 24
Finished Jun 24 06:06:44 PM PDT 24
Peak memory 205804 kb
Host smart-ac7a58b5-2775-4601-b2dd-6e2f6bae401a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3528662719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3528662719
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.136324521
Short name T2621
Test name
Test status
Simulation time 49245941 ps
CPU time 0.76 seconds
Started Jun 24 06:06:40 PM PDT 24
Finished Jun 24 06:06:43 PM PDT 24
Peak memory 205792 kb
Host smart-bc1a5160-d30c-4c06-bb5c-767bbb5775ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=136324521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.136324521
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2412201556
Short name T2563
Test name
Test status
Simulation time 180779066 ps
CPU time 1.72 seconds
Started Jun 24 06:06:28 PM PDT 24
Finished Jun 24 06:06:32 PM PDT 24
Peak memory 214236 kb
Host smart-2747f59f-6a65-4769-b384-8a39c1bc5320
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412201556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2412201556
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1193535621
Short name T2569
Test name
Test status
Simulation time 62161662 ps
CPU time 0.87 seconds
Started Jun 24 06:06:30 PM PDT 24
Finished Jun 24 06:06:33 PM PDT 24
Peak memory 205876 kb
Host smart-3fc36b33-8847-4075-acb7-28ef40e1909f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1193535621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1193535621
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.402827978
Short name T2537
Test name
Test status
Simulation time 78120838 ps
CPU time 0.69 seconds
Started Jun 24 06:06:23 PM PDT 24
Finished Jun 24 06:06:24 PM PDT 24
Peak memory 205808 kb
Host smart-321e2cae-4bc3-447e-a990-d650b23950ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=402827978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.402827978
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2587343300
Short name T2576
Test name
Test status
Simulation time 325054137 ps
CPU time 1.74 seconds
Started Jun 24 06:06:28 PM PDT 24
Finished Jun 24 06:06:32 PM PDT 24
Peak memory 206084 kb
Host smart-b3ed99e8-a4ce-4872-a949-ff0cb5f3fe0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2587343300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2587343300
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.58720619
Short name T2609
Test name
Test status
Simulation time 301496771 ps
CPU time 2.9 seconds
Started Jun 24 06:06:23 PM PDT 24
Finished Jun 24 06:06:27 PM PDT 24
Peak memory 214220 kb
Host smart-d3a82346-b78b-48c0-865b-a8192b57f4ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=58720619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.58720619
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3893176312
Short name T2610
Test name
Test status
Simulation time 1213127185 ps
CPU time 5.36 seconds
Started Jun 24 06:06:24 PM PDT 24
Finished Jun 24 06:06:31 PM PDT 24
Peak memory 206024 kb
Host smart-0c0ff885-c8ad-4c74-bcfa-3fca37d56f8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3893176312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3893176312
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3822269808
Short name T2532
Test name
Test status
Simulation time 245363196 ps
CPU time 1.81 seconds
Started Jun 24 06:06:23 PM PDT 24
Finished Jun 24 06:06:27 PM PDT 24
Peak memory 214140 kb
Host smart-1dfb2737-0ac0-42cb-976b-83cb9db1179c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822269808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3822269808
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3238465421
Short name T266
Test name
Test status
Simulation time 60353328 ps
CPU time 0.9 seconds
Started Jun 24 06:06:22 PM PDT 24
Finished Jun 24 06:06:24 PM PDT 24
Peak memory 205960 kb
Host smart-f81c0ece-0723-4353-8cf2-98c538bf0903
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3238465421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3238465421
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2448073467
Short name T283
Test name
Test status
Simulation time 44525311 ps
CPU time 0.74 seconds
Started Jun 24 06:06:28 PM PDT 24
Finished Jun 24 06:06:31 PM PDT 24
Peak memory 205772 kb
Host smart-8294a779-7f72-4c4b-9ca9-a4c59d7c20f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2448073467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2448073467
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.15700551
Short name T2527
Test name
Test status
Simulation time 102320049 ps
CPU time 1.13 seconds
Started Jun 24 06:06:27 PM PDT 24
Finished Jun 24 06:06:31 PM PDT 24
Peak memory 205972 kb
Host smart-c3d13b8b-8f3a-40fa-8a3b-a45debf82894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=15700551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.15700551
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.585562714
Short name T296
Test name
Test status
Simulation time 822095671 ps
CPU time 4.65 seconds
Started Jun 24 06:06:26 PM PDT 24
Finished Jun 24 06:06:33 PM PDT 24
Peak memory 206072 kb
Host smart-8710c5ac-f5a5-4a5d-9f25-e225b6624bc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=585562714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.585562714
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1478110728
Short name T250
Test name
Test status
Simulation time 77335707 ps
CPU time 1.7 seconds
Started Jun 24 06:06:26 PM PDT 24
Finished Jun 24 06:06:30 PM PDT 24
Peak memory 214204 kb
Host smart-afb2a874-7365-4414-b2ac-b3899981ba73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478110728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1478110728
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2497820081
Short name T270
Test name
Test status
Simulation time 89992608 ps
CPU time 1.05 seconds
Started Jun 24 06:06:25 PM PDT 24
Finished Jun 24 06:06:28 PM PDT 24
Peak memory 206092 kb
Host smart-da222e08-ae15-4c5d-9d3c-3aa8ab90e10f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2497820081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2497820081
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2891061319
Short name T2554
Test name
Test status
Simulation time 36514248 ps
CPU time 0.66 seconds
Started Jun 24 06:06:24 PM PDT 24
Finished Jun 24 06:06:26 PM PDT 24
Peak memory 205680 kb
Host smart-c00ea762-c55d-45a1-8331-a4fdf495dfbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2891061319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2891061319
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3761916721
Short name T2581
Test name
Test status
Simulation time 209079082 ps
CPU time 1.64 seconds
Started Jun 24 06:06:28 PM PDT 24
Finished Jun 24 06:06:32 PM PDT 24
Peak memory 206116 kb
Host smart-51a522bc-92e8-4ac5-bf70-0e01a8041b08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3761916721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3761916721
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2191752875
Short name T2564
Test name
Test status
Simulation time 240568013 ps
CPU time 2.66 seconds
Started Jun 24 06:06:29 PM PDT 24
Finished Jun 24 06:06:33 PM PDT 24
Peak memory 206036 kb
Host smart-e59db3a5-bb10-4871-8895-1f198f8b6444
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2191752875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2191752875
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3347823028
Short name T229
Test name
Test status
Simulation time 557682913 ps
CPU time 2.93 seconds
Started Jun 24 06:06:26 PM PDT 24
Finished Jun 24 06:06:32 PM PDT 24
Peak memory 206056 kb
Host smart-53522154-942f-4275-bf40-802fc1b84ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3347823028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3347823028
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3921022833
Short name T2594
Test name
Test status
Simulation time 133776276 ps
CPU time 2 seconds
Started Jun 24 06:06:34 PM PDT 24
Finished Jun 24 06:06:39 PM PDT 24
Peak memory 214484 kb
Host smart-83a24833-b271-4d06-aa34-673020f9c144
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921022833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.3921022833
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4109680935
Short name T2600
Test name
Test status
Simulation time 136919532 ps
CPU time 0.94 seconds
Started Jun 24 06:06:39 PM PDT 24
Finished Jun 24 06:06:43 PM PDT 24
Peak memory 205908 kb
Host smart-e63ffc3e-b719-4d12-b490-2a10a0adef6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4109680935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.4109680935
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.904762987
Short name T2523
Test name
Test status
Simulation time 58602874 ps
CPU time 0.67 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:35 PM PDT 24
Peak memory 205780 kb
Host smart-93e57bab-b632-4f79-98b8-a1d34827ed6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=904762987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.904762987
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4222165043
Short name T2540
Test name
Test status
Simulation time 219139913 ps
CPU time 1.81 seconds
Started Jun 24 06:06:31 PM PDT 24
Finished Jun 24 06:06:35 PM PDT 24
Peak memory 206052 kb
Host smart-3b6ad04b-ac19-47c0-9e17-b92644f518df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4222165043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.4222165043
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.853755907
Short name T2539
Test name
Test status
Simulation time 203968021 ps
CPU time 2.17 seconds
Started Jun 24 06:06:29 PM PDT 24
Finished Jun 24 06:06:33 PM PDT 24
Peak memory 221960 kb
Host smart-d56aa6ce-2412-44b2-b550-d375b60b9fc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=853755907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.853755907
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1106698789
Short name T294
Test name
Test status
Simulation time 1461650020 ps
CPU time 5.4 seconds
Started Jun 24 06:06:38 PM PDT 24
Finished Jun 24 06:06:46 PM PDT 24
Peak memory 206024 kb
Host smart-0c1dd3f6-0edb-4cef-908b-35e93bdcb459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1106698789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1106698789
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1719079887
Short name T2555
Test name
Test status
Simulation time 95727073 ps
CPU time 1.52 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:35 PM PDT 24
Peak memory 214284 kb
Host smart-d4f8110a-0040-43e2-9933-002ea213518c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719079887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1719079887
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1576060459
Short name T2575
Test name
Test status
Simulation time 76194023 ps
CPU time 1.06 seconds
Started Jun 24 06:06:34 PM PDT 24
Finished Jun 24 06:06:37 PM PDT 24
Peak memory 206080 kb
Host smart-f23e7623-4691-4f3f-a45a-d1d88eaf9f2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1576060459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1576060459
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.198359575
Short name T2542
Test name
Test status
Simulation time 48224592 ps
CPU time 0.65 seconds
Started Jun 24 06:06:30 PM PDT 24
Finished Jun 24 06:06:33 PM PDT 24
Peak memory 205760 kb
Host smart-63660e9d-63cd-4399-aff5-dcc0a3700458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=198359575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.198359575
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3741763863
Short name T2579
Test name
Test status
Simulation time 179018108 ps
CPU time 1.73 seconds
Started Jun 24 06:06:30 PM PDT 24
Finished Jun 24 06:06:34 PM PDT 24
Peak memory 206068 kb
Host smart-a6a555cc-d7ea-46bd-b61c-c184c08cd1dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3741763863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3741763863
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4104578211
Short name T2526
Test name
Test status
Simulation time 245373504 ps
CPU time 2.56 seconds
Started Jun 24 06:06:31 PM PDT 24
Finished Jun 24 06:06:36 PM PDT 24
Peak memory 214320 kb
Host smart-4a8b2c5c-81dd-4fe4-9780-efd3b884273a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4104578211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.4104578211
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1638813295
Short name T299
Test name
Test status
Simulation time 1015625704 ps
CPU time 4.88 seconds
Started Jun 24 06:06:32 PM PDT 24
Finished Jun 24 06:06:39 PM PDT 24
Peak memory 206072 kb
Host smart-06f4a88e-7da2-4caa-97eb-d73d3a60624b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1638813295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1638813295
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.3847529994
Short name T1568
Test name
Test status
Simulation time 3641239042 ps
CPU time 4.21 seconds
Started Jun 24 05:19:48 PM PDT 24
Finished Jun 24 05:19:53 PM PDT 24
Peak memory 206316 kb
Host smart-f12c856c-ff71-4a76-a897-412af6fff142
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3847529994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.3847529994
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.2814067745
Short name T2235
Test name
Test status
Simulation time 13466597029 ps
CPU time 12.99 seconds
Started Jun 24 05:19:50 PM PDT 24
Finished Jun 24 05:20:04 PM PDT 24
Peak memory 206336 kb
Host smart-04923fb1-6f81-4e5e-ba5d-ad41b18b4442
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2814067745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.2814067745
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2477991958
Short name T1908
Test name
Test status
Simulation time 207151803 ps
CPU time 0.87 seconds
Started Jun 24 05:19:48 PM PDT 24
Finished Jun 24 05:19:50 PM PDT 24
Peak memory 206096 kb
Host smart-6c77c1de-8dcd-4b69-9de8-d2431d5d6e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24779
91958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2477991958
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.933963914
Short name T1618
Test name
Test status
Simulation time 169978776 ps
CPU time 0.81 seconds
Started Jun 24 05:19:51 PM PDT 24
Finished Jun 24 05:19:53 PM PDT 24
Peak memory 206192 kb
Host smart-457af803-eef0-4ebf-8616-ce12bb3a8245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93396
3914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.933963914
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.782345111
Short name T1007
Test name
Test status
Simulation time 451550394 ps
CPU time 1.42 seconds
Started Jun 24 05:19:50 PM PDT 24
Finished Jun 24 05:19:52 PM PDT 24
Peak memory 206104 kb
Host smart-a1238f88-b77f-46bd-ae9b-df2cb944c57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78234
5111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.782345111
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_device_address.4285004186
Short name T2320
Test name
Test status
Simulation time 14372361012 ps
CPU time 27.8 seconds
Started Jun 24 05:19:53 PM PDT 24
Finished Jun 24 05:20:22 PM PDT 24
Peak memory 206376 kb
Host smart-d24f6eea-ef4b-4a36-a68e-7965c0d5243c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42850
04186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.4285004186
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.2149219072
Short name T1960
Test name
Test status
Simulation time 403275391 ps
CPU time 1.23 seconds
Started Jun 24 05:19:48 PM PDT 24
Finished Jun 24 05:19:50 PM PDT 24
Peak memory 206168 kb
Host smart-7524c1da-a418-482f-8852-fc861814dd55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21492
19072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.2149219072
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.4290552180
Short name T2401
Test name
Test status
Simulation time 145445673 ps
CPU time 0.76 seconds
Started Jun 24 05:19:50 PM PDT 24
Finished Jun 24 05:19:52 PM PDT 24
Peak memory 206172 kb
Host smart-48a29555-6fc5-4096-9ae2-2ae68d9cae77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42905
52180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.4290552180
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.2402004425
Short name T1743
Test name
Test status
Simulation time 5118176802 ps
CPU time 131.2 seconds
Started Jun 24 05:19:57 PM PDT 24
Finished Jun 24 05:22:09 PM PDT 24
Peak memory 206360 kb
Host smart-a134b24e-34b1-4b72-bc94-fd7b522a62e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24020
04425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.2402004425
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.3038515735
Short name T2337
Test name
Test status
Simulation time 37579338 ps
CPU time 0.64 seconds
Started Jun 24 05:19:50 PM PDT 24
Finished Jun 24 05:19:51 PM PDT 24
Peak memory 206148 kb
Host smart-4eb3ebe0-7059-4c51-9e5c-9249b1ead307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30385
15735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3038515735
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.1089591577
Short name T853
Test name
Test status
Simulation time 961265895 ps
CPU time 2.13 seconds
Started Jun 24 05:19:53 PM PDT 24
Finished Jun 24 05:19:56 PM PDT 24
Peak memory 206176 kb
Host smart-24522ac8-ac7e-4ae6-afe6-632b84e41a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10895
91577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.1089591577
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.234963329
Short name T2162
Test name
Test status
Simulation time 175340764 ps
CPU time 2.1 seconds
Started Jun 24 05:19:51 PM PDT 24
Finished Jun 24 05:19:54 PM PDT 24
Peak memory 206220 kb
Host smart-3e15a4e3-5b9c-499d-93c2-057e6ab1c9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23496
3329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.234963329
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.13800020
Short name T1152
Test name
Test status
Simulation time 181876680 ps
CPU time 0.77 seconds
Started Jun 24 05:20:04 PM PDT 24
Finished Jun 24 05:20:06 PM PDT 24
Peak memory 206144 kb
Host smart-d75676d5-a514-4229-8ceb-74bf708a1624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13800
020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.13800020
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.1211530114
Short name T1375
Test name
Test status
Simulation time 166821600 ps
CPU time 0.8 seconds
Started Jun 24 05:20:13 PM PDT 24
Finished Jun 24 05:20:15 PM PDT 24
Peak memory 206164 kb
Host smart-a4eb904b-8efa-41bd-95b5-a3cfe697a500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12115
30114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.1211530114
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1951162826
Short name T708
Test name
Test status
Simulation time 241249208 ps
CPU time 0.91 seconds
Started Jun 24 05:20:00 PM PDT 24
Finished Jun 24 05:20:02 PM PDT 24
Peak memory 206180 kb
Host smart-65bbee78-1094-4bde-b03b-8b1caa5d99c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19511
62826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1951162826
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1822819620
Short name T308
Test name
Test status
Simulation time 237413811 ps
CPU time 0.96 seconds
Started Jun 24 05:19:58 PM PDT 24
Finished Jun 24 05:20:00 PM PDT 24
Peak memory 206080 kb
Host smart-b4b3683e-6a85-42c9-b0f3-fdb7da55b25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18228
19620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1822819620
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.3898974536
Short name T67
Test name
Test status
Simulation time 491063964 ps
CPU time 1.31 seconds
Started Jun 24 05:19:58 PM PDT 24
Finished Jun 24 05:20:01 PM PDT 24
Peak memory 206168 kb
Host smart-bf559d8d-e8cd-4b90-b7b5-8d9b95579a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38989
74536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.3898974536
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.4049590309
Short name T2520
Test name
Test status
Simulation time 23329568920 ps
CPU time 21.33 seconds
Started Jun 24 05:20:02 PM PDT 24
Finished Jun 24 05:20:24 PM PDT 24
Peak memory 205944 kb
Host smart-26192e82-07cf-42e9-9832-47f6319a31ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40495
90309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.4049590309
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.1696569164
Short name T2112
Test name
Test status
Simulation time 3375592165 ps
CPU time 3.93 seconds
Started Jun 24 05:19:58 PM PDT 24
Finished Jun 24 05:20:04 PM PDT 24
Peak memory 206244 kb
Host smart-770c86a0-ce4b-4776-8185-93e83b61dec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16965
69164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1696569164
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2165070914
Short name T746
Test name
Test status
Simulation time 5464580482 ps
CPU time 39.06 seconds
Started Jun 24 05:19:58 PM PDT 24
Finished Jun 24 05:20:38 PM PDT 24
Peak memory 206356 kb
Host smart-83fe27d6-36d6-4a0b-b822-4f687b58db47
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2165070914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2165070914
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.1947709462
Short name T935
Test name
Test status
Simulation time 235998603 ps
CPU time 0.87 seconds
Started Jun 24 05:20:14 PM PDT 24
Finished Jun 24 05:20:16 PM PDT 24
Peak memory 206120 kb
Host smart-7c205e39-84cc-4c8f-bfc3-f628ae187796
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1947709462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.1947709462
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2639354862
Short name T537
Test name
Test status
Simulation time 192940460 ps
CPU time 0.85 seconds
Started Jun 24 05:19:56 PM PDT 24
Finished Jun 24 05:19:58 PM PDT 24
Peak memory 206188 kb
Host smart-dd641a9e-4c59-470f-8e9c-a70be40b5c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26393
54862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2639354862
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.191691785
Short name T2381
Test name
Test status
Simulation time 9152145043 ps
CPU time 93.03 seconds
Started Jun 24 05:19:58 PM PDT 24
Finished Jun 24 05:21:32 PM PDT 24
Peak memory 206340 kb
Host smart-489e2b3e-c18c-4e8a-b51b-72c7020a6d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19169
1785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.191691785
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.3323544093
Short name T409
Test name
Test status
Simulation time 7086788966 ps
CPU time 202.12 seconds
Started Jun 24 05:19:59 PM PDT 24
Finished Jun 24 05:23:23 PM PDT 24
Peak memory 206408 kb
Host smart-2f2424f4-3454-4a9a-b073-b07fa0f2b817
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3323544093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.3323544093
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1903459945
Short name T2154
Test name
Test status
Simulation time 164162637 ps
CPU time 0.79 seconds
Started Jun 24 05:20:05 PM PDT 24
Finished Jun 24 05:20:07 PM PDT 24
Peak memory 206196 kb
Host smart-a03b4359-6fe7-4282-81aa-8e9fce0312b2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1903459945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1903459945
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2043856095
Short name T585
Test name
Test status
Simulation time 184108930 ps
CPU time 0.83 seconds
Started Jun 24 05:19:57 PM PDT 24
Finished Jun 24 05:19:59 PM PDT 24
Peak memory 206156 kb
Host smart-882bfdfb-cf7e-42f8-ad3b-84da0648c453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20438
56095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2043856095
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1866042240
Short name T68
Test name
Test status
Simulation time 563731834 ps
CPU time 1.49 seconds
Started Jun 24 05:19:59 PM PDT 24
Finished Jun 24 05:20:02 PM PDT 24
Peak memory 206168 kb
Host smart-821d623b-343d-486c-9218-821aab3fee14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18660
42240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1866042240
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3416499454
Short name T1724
Test name
Test status
Simulation time 152418926 ps
CPU time 0.78 seconds
Started Jun 24 05:19:58 PM PDT 24
Finished Jun 24 05:20:00 PM PDT 24
Peak memory 206176 kb
Host smart-fee265ec-2587-4343-9ebd-03617f6e245e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34164
99454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3416499454
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.502784797
Short name T1524
Test name
Test status
Simulation time 197350485 ps
CPU time 0.86 seconds
Started Jun 24 05:19:59 PM PDT 24
Finished Jun 24 05:20:01 PM PDT 24
Peak memory 206188 kb
Host smart-a27a4fb7-33a6-4cd3-8c4b-d17f6ff09ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50278
4797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.502784797
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2706824361
Short name T541
Test name
Test status
Simulation time 152520453 ps
CPU time 0.79 seconds
Started Jun 24 05:19:57 PM PDT 24
Finished Jun 24 05:20:00 PM PDT 24
Peak memory 206096 kb
Host smart-04289e07-fe16-49be-b4f5-016344d017ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27068
24361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2706824361
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.4109900029
Short name T1897
Test name
Test status
Simulation time 148374983 ps
CPU time 0.76 seconds
Started Jun 24 05:20:10 PM PDT 24
Finished Jun 24 05:20:11 PM PDT 24
Peak memory 206168 kb
Host smart-97b870fc-7ee3-4215-975d-87bd2b741418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41099
00029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.4109900029
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1306261579
Short name T2363
Test name
Test status
Simulation time 183665179 ps
CPU time 0.89 seconds
Started Jun 24 05:19:56 PM PDT 24
Finished Jun 24 05:19:58 PM PDT 24
Peak memory 206200 kb
Host smart-d342017c-1efe-4383-9046-192113a98b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13062
61579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1306261579
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.139205759
Short name T1180
Test name
Test status
Simulation time 226648509 ps
CPU time 0.92 seconds
Started Jun 24 05:19:57 PM PDT 24
Finished Jun 24 05:19:59 PM PDT 24
Peak memory 206064 kb
Host smart-e6c5a8c4-39fd-4a0d-aee6-3b67472b6f31
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=139205759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.139205759
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.2551187354
Short name T211
Test name
Test status
Simulation time 225255947 ps
CPU time 0.97 seconds
Started Jun 24 05:19:57 PM PDT 24
Finished Jun 24 05:19:59 PM PDT 24
Peak memory 206152 kb
Host smart-335c2ca2-282b-432a-bb15-81d32e8deabe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25511
87354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.2551187354
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.3674650457
Short name T1702
Test name
Test status
Simulation time 181223616 ps
CPU time 0.89 seconds
Started Jun 24 05:19:58 PM PDT 24
Finished Jun 24 05:20:00 PM PDT 24
Peak memory 206180 kb
Host smart-e0835024-f187-4381-ba65-6263c189694b
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3674650457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.3674650457
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.642893764
Short name T2011
Test name
Test status
Simulation time 258702285 ps
CPU time 0.95 seconds
Started Jun 24 05:20:00 PM PDT 24
Finished Jun 24 05:20:02 PM PDT 24
Peak memory 206132 kb
Host smart-b52e8f83-8e17-4200-a256-e851a655a887
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=642893764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.642893764
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2096184500
Short name T1924
Test name
Test status
Simulation time 139156685 ps
CPU time 0.77 seconds
Started Jun 24 05:19:55 PM PDT 24
Finished Jun 24 05:19:57 PM PDT 24
Peak memory 206192 kb
Host smart-36157bd5-4680-4d8e-a392-b64465d074a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20961
84500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2096184500
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2343682897
Short name T35
Test name
Test status
Simulation time 73230852 ps
CPU time 0.7 seconds
Started Jun 24 05:20:06 PM PDT 24
Finished Jun 24 05:20:08 PM PDT 24
Peak memory 206084 kb
Host smart-e4fa4245-dd28-4682-9568-837cc71a9b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23436
82897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2343682897
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2834066962
Short name T2334
Test name
Test status
Simulation time 15013976743 ps
CPU time 32.56 seconds
Started Jun 24 05:20:02 PM PDT 24
Finished Jun 24 05:20:36 PM PDT 24
Peak memory 206436 kb
Host smart-248e1202-cf8c-4170-8457-ebc0cb66492d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28340
66962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2834066962
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.956902305
Short name T419
Test name
Test status
Simulation time 170235545 ps
CPU time 0.87 seconds
Started Jun 24 05:20:00 PM PDT 24
Finished Jun 24 05:20:02 PM PDT 24
Peak memory 206188 kb
Host smart-27508c03-b71e-4bc5-a743-b5150e2e5000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95690
2305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.956902305
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2852299564
Short name T1620
Test name
Test status
Simulation time 229049482 ps
CPU time 1 seconds
Started Jun 24 05:19:58 PM PDT 24
Finished Jun 24 05:20:01 PM PDT 24
Peak memory 206188 kb
Host smart-e9836c60-e154-40b1-bbe4-b737d324eccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28522
99564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2852299564
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.3801715741
Short name T183
Test name
Test status
Simulation time 20076679007 ps
CPU time 480.02 seconds
Started Jun 24 05:19:58 PM PDT 24
Finished Jun 24 05:28:00 PM PDT 24
Peak memory 206432 kb
Host smart-96b8f845-1607-4bbb-8adb-a26b38e8d3d5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3801715741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.3801715741
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1393307901
Short name T559
Test name
Test status
Simulation time 24963275760 ps
CPU time 582.78 seconds
Started Jun 24 05:19:57 PM PDT 24
Finished Jun 24 05:29:42 PM PDT 24
Peak memory 206436 kb
Host smart-c49e3922-ed05-45a9-828c-4b4537e57272
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1393307901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1393307901
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3168484381
Short name T862
Test name
Test status
Simulation time 226807689 ps
CPU time 0.87 seconds
Started Jun 24 05:20:07 PM PDT 24
Finished Jun 24 05:20:09 PM PDT 24
Peak memory 206172 kb
Host smart-cf1a12dd-3582-4ba4-849a-8619c1dcdd5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31684
84381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3168484381
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.4292265935
Short name T631
Test name
Test status
Simulation time 184375930 ps
CPU time 0.89 seconds
Started Jun 24 05:19:57 PM PDT 24
Finished Jun 24 05:19:59 PM PDT 24
Peak memory 206420 kb
Host smart-997399c5-3826-4b65-ba27-164ca32d59d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42922
65935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.4292265935
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.289647466
Short name T1911
Test name
Test status
Simulation time 173708075 ps
CPU time 0.88 seconds
Started Jun 24 05:19:58 PM PDT 24
Finished Jun 24 05:20:00 PM PDT 24
Peak memory 206172 kb
Host smart-65690220-fa13-4451-a970-75c71a9fc41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28964
7466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.289647466
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3051061626
Short name T310
Test name
Test status
Simulation time 188520651 ps
CPU time 0.79 seconds
Started Jun 24 05:20:11 PM PDT 24
Finished Jun 24 05:20:13 PM PDT 24
Peak memory 206188 kb
Host smart-139b7536-9350-41cc-819b-bef7ab87c7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30510
61626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3051061626
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.956532731
Short name T1899
Test name
Test status
Simulation time 198357304 ps
CPU time 0.82 seconds
Started Jun 24 05:20:08 PM PDT 24
Finished Jun 24 05:20:09 PM PDT 24
Peak memory 206056 kb
Host smart-23dd62a4-dba6-4b65-8661-bebc815b2a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95653
2731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.956532731
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.2739645705
Short name T1100
Test name
Test status
Simulation time 231708741 ps
CPU time 0.92 seconds
Started Jun 24 05:20:07 PM PDT 24
Finished Jun 24 05:20:09 PM PDT 24
Peak memory 206092 kb
Host smart-db4eae61-c5dc-4435-8d92-7f41494653dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27396
45705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2739645705
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.142778186
Short name T1272
Test name
Test status
Simulation time 14332797149 ps
CPU time 409.01 seconds
Started Jun 24 05:20:06 PM PDT 24
Finished Jun 24 05:26:55 PM PDT 24
Peak memory 206388 kb
Host smart-092a20ff-83f7-4ed1-aaa4-f0dfa56ac9c4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=142778186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.142778186
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.956460241
Short name T2357
Test name
Test status
Simulation time 169963229 ps
CPU time 0.83 seconds
Started Jun 24 05:20:12 PM PDT 24
Finished Jun 24 05:20:14 PM PDT 24
Peak memory 206116 kb
Host smart-d9b9dc6a-2578-4c83-a91d-d316909b730c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95646
0241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.956460241
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.488078614
Short name T1852
Test name
Test status
Simulation time 257240648 ps
CPU time 0.96 seconds
Started Jun 24 05:20:10 PM PDT 24
Finished Jun 24 05:20:12 PM PDT 24
Peak memory 206184 kb
Host smart-41a2f523-8b56-4099-85cd-8cb3f5a0e92e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48807
8614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.488078614
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.3015523208
Short name T1935
Test name
Test status
Simulation time 3920100201 ps
CPU time 110.08 seconds
Started Jun 24 05:20:07 PM PDT 24
Finished Jun 24 05:21:58 PM PDT 24
Peak memory 206284 kb
Host smart-d385e743-051e-41f3-92f3-654b77ae4f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30155
23208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.3015523208
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2129096467
Short name T1532
Test name
Test status
Simulation time 18881123536 ps
CPU time 514.69 seconds
Started Jun 24 05:20:06 PM PDT 24
Finished Jun 24 05:28:41 PM PDT 24
Peak memory 206372 kb
Host smart-70bd27bc-1017-4a6b-8c2f-42cc38608a34
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2129096467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2129096467
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.3007829558
Short name T898
Test name
Test status
Simulation time 4170870812 ps
CPU time 5.06 seconds
Started Jun 24 05:20:12 PM PDT 24
Finished Jun 24 05:20:18 PM PDT 24
Peak memory 206256 kb
Host smart-f8565071-8bed-43d7-9e7c-bc865722ab22
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3007829558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.3007829558
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.2618598817
Short name T760
Test name
Test status
Simulation time 13534589244 ps
CPU time 15.71 seconds
Started Jun 24 05:20:14 PM PDT 24
Finished Jun 24 05:20:31 PM PDT 24
Peak memory 206308 kb
Host smart-0f5e60f6-7df0-4c73-b092-6d90b367f322
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2618598817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.2618598817
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.1851652388
Short name T7
Test name
Test status
Simulation time 23326959104 ps
CPU time 22.17 seconds
Started Jun 24 05:20:06 PM PDT 24
Finished Jun 24 05:20:29 PM PDT 24
Peak memory 206252 kb
Host smart-4c7a17c4-4d5d-449e-b049-5038cd2b2a59
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1851652388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.1851652388
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3507390264
Short name T532
Test name
Test status
Simulation time 199590029 ps
CPU time 0.87 seconds
Started Jun 24 05:20:07 PM PDT 24
Finished Jun 24 05:20:09 PM PDT 24
Peak memory 206172 kb
Host smart-48dad2bb-0fc3-4573-867c-9b448d7e8ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35073
90264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3507390264
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.3236722179
Short name T51
Test name
Test status
Simulation time 167477872 ps
CPU time 0.84 seconds
Started Jun 24 05:20:08 PM PDT 24
Finished Jun 24 05:20:09 PM PDT 24
Peak memory 206068 kb
Host smart-e105184c-f89a-4313-8916-b3130f038b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32367
22179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.3236722179
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.1674295970
Short name T62
Test name
Test status
Simulation time 136276138 ps
CPU time 0.8 seconds
Started Jun 24 05:20:07 PM PDT 24
Finished Jun 24 05:20:09 PM PDT 24
Peak memory 206188 kb
Host smart-c4112f1b-7260-4707-ab2d-52eff390026a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16742
95970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.1674295970
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.2842350956
Short name T1438
Test name
Test status
Simulation time 140333909 ps
CPU time 0.78 seconds
Started Jun 24 05:20:14 PM PDT 24
Finished Jun 24 05:20:16 PM PDT 24
Peak memory 206176 kb
Host smart-abba987c-8e47-4167-b289-30c1fbd9fed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28423
50956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2842350956
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.1165513119
Short name T2331
Test name
Test status
Simulation time 213174731 ps
CPU time 0.87 seconds
Started Jun 24 05:20:08 PM PDT 24
Finished Jun 24 05:20:10 PM PDT 24
Peak memory 206172 kb
Host smart-7013cb0c-bb21-41bc-93a2-2baaa76bf53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11655
13119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.1165513119
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.2655707385
Short name T111
Test name
Test status
Simulation time 1279510497 ps
CPU time 3.1 seconds
Started Jun 24 05:20:13 PM PDT 24
Finished Jun 24 05:20:17 PM PDT 24
Peak memory 206200 kb
Host smart-f83dda3b-5a14-4c2b-a6c7-caaba1c94604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26557
07385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.2655707385
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.4173255823
Short name T2267
Test name
Test status
Simulation time 13463031672 ps
CPU time 24.88 seconds
Started Jun 24 05:20:13 PM PDT 24
Finished Jun 24 05:20:38 PM PDT 24
Peak memory 206360 kb
Host smart-c939d32e-16ae-4601-891c-2fd33f706d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41732
55823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.4173255823
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.4152301883
Short name T363
Test name
Test status
Simulation time 423181222 ps
CPU time 1.26 seconds
Started Jun 24 05:20:10 PM PDT 24
Finished Jun 24 05:20:12 PM PDT 24
Peak memory 206076 kb
Host smart-194a9ba1-cc7c-47fb-8638-fc4498f89299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41523
01883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.4152301883
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.4123096560
Short name T1713
Test name
Test status
Simulation time 182977197 ps
CPU time 0.83 seconds
Started Jun 24 05:20:08 PM PDT 24
Finished Jun 24 05:20:10 PM PDT 24
Peak memory 206072 kb
Host smart-ab8c63c0-fdcc-49e8-b1c8-30c69ae1d362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41230
96560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.4123096560
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.1702663160
Short name T1558
Test name
Test status
Simulation time 27879462 ps
CPU time 0.68 seconds
Started Jun 24 05:20:08 PM PDT 24
Finished Jun 24 05:20:10 PM PDT 24
Peak memory 206176 kb
Host smart-5ce4119f-6552-45ab-af2e-e220f9adaa7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17026
63160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1702663160
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.3336537048
Short name T598
Test name
Test status
Simulation time 814771877 ps
CPU time 1.95 seconds
Started Jun 24 05:20:12 PM PDT 24
Finished Jun 24 05:20:15 PM PDT 24
Peak memory 206200 kb
Host smart-f87a2920-77fa-47c2-8bb5-7a976a101a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33365
37048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.3336537048
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.3798944134
Short name T1626
Test name
Test status
Simulation time 302283678 ps
CPU time 1.82 seconds
Started Jun 24 05:20:06 PM PDT 24
Finished Jun 24 05:20:09 PM PDT 24
Peak memory 206244 kb
Host smart-8ab0efd8-c53a-47c6-938e-0c793da79338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37989
44134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.3798944134
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.872922905
Short name T1186
Test name
Test status
Simulation time 172489278 ps
CPU time 0.81 seconds
Started Jun 24 05:20:18 PM PDT 24
Finished Jun 24 05:20:21 PM PDT 24
Peak memory 206116 kb
Host smart-967be17e-d588-4486-afdb-9ba7d9498f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87292
2905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.872922905
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3155160160
Short name T2417
Test name
Test status
Simulation time 138302969 ps
CPU time 0.82 seconds
Started Jun 24 05:20:16 PM PDT 24
Finished Jun 24 05:20:19 PM PDT 24
Peak memory 206188 kb
Host smart-f0d23d99-f779-4e1a-8133-0852909b283e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31551
60160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3155160160
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3272895170
Short name T2414
Test name
Test status
Simulation time 204507988 ps
CPU time 0.86 seconds
Started Jun 24 05:20:05 PM PDT 24
Finished Jun 24 05:20:07 PM PDT 24
Peak memory 206192 kb
Host smart-f8b79799-dd7f-4465-afb3-0ee0baf45d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32728
95170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3272895170
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.1083165934
Short name T1795
Test name
Test status
Simulation time 183877966 ps
CPU time 0.81 seconds
Started Jun 24 05:20:12 PM PDT 24
Finished Jun 24 05:20:14 PM PDT 24
Peak memory 206152 kb
Host smart-a87d4ea7-0afe-4b2a-b246-a3289fb22d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10831
65934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.1083165934
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.2223733150
Short name T1125
Test name
Test status
Simulation time 23310641649 ps
CPU time 21.88 seconds
Started Jun 24 05:20:06 PM PDT 24
Finished Jun 24 05:20:28 PM PDT 24
Peak memory 206140 kb
Host smart-66134f20-4c51-4bb4-b4b3-9489a3b9a5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22237
33150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.2223733150
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1298718279
Short name T472
Test name
Test status
Simulation time 3329482720 ps
CPU time 3.99 seconds
Started Jun 24 05:20:07 PM PDT 24
Finished Jun 24 05:20:12 PM PDT 24
Peak memory 206228 kb
Host smart-e099b9fb-ecec-4658-8bf2-bea7e92f3f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12987
18279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1298718279
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.2276478719
Short name T604
Test name
Test status
Simulation time 9953283213 ps
CPU time 67.42 seconds
Started Jun 24 05:20:16 PM PDT 24
Finished Jun 24 05:21:26 PM PDT 24
Peak memory 206268 kb
Host smart-546a5af5-7769-46c5-924d-dc9476248155
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2276478719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.2276478719
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.277855947
Short name T2029
Test name
Test status
Simulation time 237088019 ps
CPU time 0.92 seconds
Started Jun 24 05:20:17 PM PDT 24
Finished Jun 24 05:20:21 PM PDT 24
Peak memory 206192 kb
Host smart-d78a8419-398b-441a-8891-524f98535bf0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=277855947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.277855947
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2095310108
Short name T1901
Test name
Test status
Simulation time 196847026 ps
CPU time 0.87 seconds
Started Jun 24 05:20:06 PM PDT 24
Finished Jun 24 05:20:08 PM PDT 24
Peak memory 206116 kb
Host smart-52fdf626-c52f-4713-ad7d-7164f3a80db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20953
10108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2095310108
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.3792211083
Short name T1430
Test name
Test status
Simulation time 7846263956 ps
CPU time 76.6 seconds
Started Jun 24 05:20:16 PM PDT 24
Finished Jun 24 05:21:35 PM PDT 24
Peak memory 206376 kb
Host smart-5359e126-57fc-4fda-82ba-6e8c921293ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37922
11083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.3792211083
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.2583418918
Short name T1068
Test name
Test status
Simulation time 3754361092 ps
CPU time 26.06 seconds
Started Jun 24 05:20:17 PM PDT 24
Finished Jun 24 05:20:46 PM PDT 24
Peak memory 206356 kb
Host smart-f269925c-7906-4fa8-b707-ad121053b2c5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2583418918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.2583418918
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.1326368891
Short name T1500
Test name
Test status
Simulation time 154937695 ps
CPU time 0.81 seconds
Started Jun 24 05:20:14 PM PDT 24
Finished Jun 24 05:20:16 PM PDT 24
Peak memory 206192 kb
Host smart-6be53d24-9e40-4d61-b90b-d8b7a4a390af
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1326368891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1326368891
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1871295716
Short name T986
Test name
Test status
Simulation time 164370435 ps
CPU time 0.79 seconds
Started Jun 24 05:20:10 PM PDT 24
Finished Jun 24 05:20:11 PM PDT 24
Peak memory 206184 kb
Host smart-6bff23ab-cd64-45c5-b605-5aea21d40c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18712
95716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1871295716
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.1051970682
Short name T740
Test name
Test status
Simulation time 191700023 ps
CPU time 0.86 seconds
Started Jun 24 05:20:16 PM PDT 24
Finished Jun 24 05:20:20 PM PDT 24
Peak memory 206108 kb
Host smart-b93c1035-30fa-4315-8efb-8d6ebfa61027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10519
70682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1051970682
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.797976128
Short name T350
Test name
Test status
Simulation time 180772281 ps
CPU time 0.82 seconds
Started Jun 24 05:20:16 PM PDT 24
Finished Jun 24 05:20:19 PM PDT 24
Peak memory 206188 kb
Host smart-9e28ed91-1ddc-4ef1-bdd8-0a6e5f6700b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79797
6128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.797976128
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2961025877
Short name T1188
Test name
Test status
Simulation time 191081999 ps
CPU time 0.93 seconds
Started Jun 24 05:20:17 PM PDT 24
Finished Jun 24 05:20:21 PM PDT 24
Peak memory 206168 kb
Host smart-d1e4e589-9cc5-46c8-9570-29904b56aa71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29610
25877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2961025877
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1506442461
Short name T1214
Test name
Test status
Simulation time 147625773 ps
CPU time 0.79 seconds
Started Jun 24 05:20:14 PM PDT 24
Finished Jun 24 05:20:17 PM PDT 24
Peak memory 206172 kb
Host smart-76dba0bc-f5d4-4074-824e-08c291542a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15064
42461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1506442461
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.4256372008
Short name T1398
Test name
Test status
Simulation time 214344443 ps
CPU time 0.96 seconds
Started Jun 24 05:20:17 PM PDT 24
Finished Jun 24 05:20:21 PM PDT 24
Peak memory 206180 kb
Host smart-98237db6-174b-4a24-95c4-d4e3f9387fb1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4256372008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.4256372008
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.864202509
Short name T210
Test name
Test status
Simulation time 222283767 ps
CPU time 0.93 seconds
Started Jun 24 05:20:18 PM PDT 24
Finished Jun 24 05:20:21 PM PDT 24
Peak memory 206148 kb
Host smart-eea78030-5331-4da5-8078-144dbc5c2104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86420
2509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.864202509
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.4039398813
Short name T2476
Test name
Test status
Simulation time 164210186 ps
CPU time 0.77 seconds
Started Jun 24 05:20:17 PM PDT 24
Finished Jun 24 05:20:21 PM PDT 24
Peak memory 206192 kb
Host smart-9e3d1fb4-065d-4d09-8f0c-61289ef53d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40393
98813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.4039398813
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.4213527907
Short name T2069
Test name
Test status
Simulation time 22978620258 ps
CPU time 52.68 seconds
Started Jun 24 05:20:16 PM PDT 24
Finished Jun 24 05:21:11 PM PDT 24
Peak memory 206380 kb
Host smart-982cf749-ebe3-456f-8985-4dc936e556b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42135
27907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.4213527907
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.184539220
Short name T1957
Test name
Test status
Simulation time 186336244 ps
CPU time 0.93 seconds
Started Jun 24 05:20:16 PM PDT 24
Finished Jun 24 05:20:20 PM PDT 24
Peak memory 206184 kb
Host smart-6c858d16-70a0-43d7-b7c6-b7d138267eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18453
9220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.184539220
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3307624835
Short name T1198
Test name
Test status
Simulation time 247494439 ps
CPU time 0.95 seconds
Started Jun 24 05:20:17 PM PDT 24
Finished Jun 24 05:20:21 PM PDT 24
Peak memory 206168 kb
Host smart-739980de-e780-4f9b-87ef-a0a28394e0cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33076
24835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3307624835
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1974094777
Short name T1277
Test name
Test status
Simulation time 7761842140 ps
CPU time 35.23 seconds
Started Jun 24 05:20:18 PM PDT 24
Finished Jun 24 05:20:56 PM PDT 24
Peak memory 206360 kb
Host smart-214c9dcc-de7e-449f-8399-67c820e9b860
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1974094777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1974094777
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.4016987775
Short name T2446
Test name
Test status
Simulation time 7796233326 ps
CPU time 63.16 seconds
Started Jun 24 05:20:18 PM PDT 24
Finished Jun 24 05:21:24 PM PDT 24
Peak memory 206324 kb
Host smart-4ad44aa5-22e1-402b-9db7-193748490770
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4016987775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.4016987775
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.666023037
Short name T1264
Test name
Test status
Simulation time 15266021900 ps
CPU time 337.73 seconds
Started Jun 24 05:20:17 PM PDT 24
Finished Jun 24 05:25:58 PM PDT 24
Peak memory 206316 kb
Host smart-983a63f7-21c8-47cf-81cc-fec9a3f31dbd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=666023037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.666023037
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.779796443
Short name T941
Test name
Test status
Simulation time 200095938 ps
CPU time 0.83 seconds
Started Jun 24 05:20:16 PM PDT 24
Finished Jun 24 05:20:19 PM PDT 24
Peak memory 206168 kb
Host smart-2d986a16-ca32-4e0e-98fc-1411897f25ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77979
6443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.779796443
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.607629515
Short name T475
Test name
Test status
Simulation time 178206334 ps
CPU time 0.83 seconds
Started Jun 24 05:20:15 PM PDT 24
Finished Jun 24 05:20:18 PM PDT 24
Peak memory 206060 kb
Host smart-fc131be2-76dc-4e4f-9287-b28c5d100349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60762
9515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.607629515
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3746410563
Short name T455
Test name
Test status
Simulation time 176458738 ps
CPU time 0.85 seconds
Started Jun 24 05:20:16 PM PDT 24
Finished Jun 24 05:20:20 PM PDT 24
Peak memory 206112 kb
Host smart-cf6c43d7-b75b-4b1f-bad1-9b6de189cad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37464
10563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3746410563
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.3445136891
Short name T2173
Test name
Test status
Simulation time 166271796 ps
CPU time 0.83 seconds
Started Jun 24 05:20:18 PM PDT 24
Finished Jun 24 05:20:21 PM PDT 24
Peak memory 206180 kb
Host smart-1b3bd235-efc9-4971-9292-1f4dbfb2230f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34451
36891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.3445136891
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2749672850
Short name T202
Test name
Test status
Simulation time 400431384 ps
CPU time 1.28 seconds
Started Jun 24 05:20:14 PM PDT 24
Finished Jun 24 05:20:18 PM PDT 24
Peak memory 223808 kb
Host smart-8c5bb46f-f731-4e40-8d1c-549a1bf36047
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2749672850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2749672850
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.2062583138
Short name T53
Test name
Test status
Simulation time 381110694 ps
CPU time 1.12 seconds
Started Jun 24 05:20:17 PM PDT 24
Finished Jun 24 05:20:21 PM PDT 24
Peak memory 206152 kb
Host smart-4b2ea859-276a-46eb-8557-702bbb8705a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20625
83138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.2062583138
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2034689907
Short name T407
Test name
Test status
Simulation time 157867769 ps
CPU time 0.85 seconds
Started Jun 24 05:20:15 PM PDT 24
Finished Jun 24 05:20:18 PM PDT 24
Peak memory 206104 kb
Host smart-4898b6a8-1f17-4f3d-adf9-54e5048008b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20346
89907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2034689907
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2173033784
Short name T2035
Test name
Test status
Simulation time 194279082 ps
CPU time 0.84 seconds
Started Jun 24 05:20:16 PM PDT 24
Finished Jun 24 05:20:19 PM PDT 24
Peak memory 206176 kb
Host smart-f1a8c7ff-97c9-4ab7-99d0-f50096f057bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21730
33784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2173033784
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2452063785
Short name T468
Test name
Test status
Simulation time 282970093 ps
CPU time 1.07 seconds
Started Jun 24 05:20:18 PM PDT 24
Finished Jun 24 05:20:22 PM PDT 24
Peak memory 206092 kb
Host smart-71856a29-5e0b-4199-baf6-35d457798f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24520
63785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2452063785
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.12027054
Short name T2462
Test name
Test status
Simulation time 8948403226 ps
CPU time 64.48 seconds
Started Jun 24 05:20:14 PM PDT 24
Finished Jun 24 05:21:20 PM PDT 24
Peak memory 206404 kb
Host smart-935bd382-fb0b-4696-83c7-08428c765dc8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=12027054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.12027054
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.3823756601
Short name T817
Test name
Test status
Simulation time 196525104 ps
CPU time 0.91 seconds
Started Jun 24 05:20:18 PM PDT 24
Finished Jun 24 05:20:21 PM PDT 24
Peak memory 206172 kb
Host smart-579882a1-28e1-4a86-a098-4a421ed34b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38237
56601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.3823756601
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.522101103
Short name T969
Test name
Test status
Simulation time 209025484 ps
CPU time 0.85 seconds
Started Jun 24 05:20:17 PM PDT 24
Finished Jun 24 05:20:21 PM PDT 24
Peak memory 206160 kb
Host smart-4188353f-e529-4dda-a08b-99ea8ea1d4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52210
1103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.522101103
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.2107194363
Short name T2515
Test name
Test status
Simulation time 8386045075 ps
CPU time 77.95 seconds
Started Jun 24 05:20:15 PM PDT 24
Finished Jun 24 05:21:35 PM PDT 24
Peak memory 206388 kb
Host smart-064a6c05-1121-41a2-ba82-b60a49c9b6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21071
94363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2107194363
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.2170079747
Short name T1421
Test name
Test status
Simulation time 4242332333 ps
CPU time 5.21 seconds
Started Jun 24 05:21:52 PM PDT 24
Finished Jun 24 05:21:58 PM PDT 24
Peak memory 206364 kb
Host smart-399f3eb3-ad81-43e8-acf7-a8119ba86233
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2170079747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.2170079747
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1360363340
Short name T1692
Test name
Test status
Simulation time 13333663326 ps
CPU time 14.95 seconds
Started Jun 24 05:21:54 PM PDT 24
Finished Jun 24 05:22:11 PM PDT 24
Peak memory 206356 kb
Host smart-8cf7c231-8d26-4a16-8bdd-afef0174f5f5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1360363340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1360363340
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.1363130500
Short name T1592
Test name
Test status
Simulation time 23386516240 ps
CPU time 22.84 seconds
Started Jun 24 05:21:55 PM PDT 24
Finished Jun 24 05:22:20 PM PDT 24
Peak memory 206236 kb
Host smart-049e9abb-7976-406e-a3c7-b85524e4c08e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1363130500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.1363130500
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3925108156
Short name T2045
Test name
Test status
Simulation time 238628058 ps
CPU time 0.88 seconds
Started Jun 24 05:21:54 PM PDT 24
Finished Jun 24 05:21:58 PM PDT 24
Peak memory 206060 kb
Host smart-8435079a-9eaf-4fa5-89c6-a9be7bdde16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39251
08156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3925108156
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.1838470728
Short name T1641
Test name
Test status
Simulation time 160321931 ps
CPU time 0.77 seconds
Started Jun 24 05:21:55 PM PDT 24
Finished Jun 24 05:21:58 PM PDT 24
Peak memory 206072 kb
Host smart-585b9f39-1e77-4a3f-9071-9b3cb7e9ca0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18384
70728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.1838470728
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.1384279156
Short name T1462
Test name
Test status
Simulation time 235865267 ps
CPU time 0.96 seconds
Started Jun 24 05:21:54 PM PDT 24
Finished Jun 24 05:21:56 PM PDT 24
Peak memory 206176 kb
Host smart-c8fb0c62-f2b3-4bad-be28-3e581f014a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13842
79156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.1384279156
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_device_address.830265795
Short name T2382
Test name
Test status
Simulation time 9020023061 ps
CPU time 15.99 seconds
Started Jun 24 05:21:54 PM PDT 24
Finished Jun 24 05:22:13 PM PDT 24
Peak memory 206368 kb
Host smart-114e7bc1-82ac-4a2d-ab6e-99b3507ae67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83026
5795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.830265795
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.2025194841
Short name T2268
Test name
Test status
Simulation time 466995317 ps
CPU time 1.47 seconds
Started Jun 24 05:22:02 PM PDT 24
Finished Jun 24 05:22:05 PM PDT 24
Peak memory 206112 kb
Host smart-a6405003-ba58-4867-9fbf-a400475158fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20251
94841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.2025194841
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_enable.590900126
Short name T365
Test name
Test status
Simulation time 28090331 ps
CPU time 0.69 seconds
Started Jun 24 05:22:02 PM PDT 24
Finished Jun 24 05:22:04 PM PDT 24
Peak memory 206164 kb
Host smart-df1657dd-e986-4935-8dd1-5d4ce710f43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59090
0126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.590900126
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2043608544
Short name T1719
Test name
Test status
Simulation time 922944347 ps
CPU time 2.33 seconds
Started Jun 24 05:22:01 PM PDT 24
Finished Jun 24 05:22:05 PM PDT 24
Peak memory 206256 kb
Host smart-24cd690c-6aaf-4feb-99a2-7de70581dbaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20436
08544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2043608544
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.104626706
Short name T1393
Test name
Test status
Simulation time 264572022 ps
CPU time 0.96 seconds
Started Jun 24 05:22:02 PM PDT 24
Finished Jun 24 05:22:04 PM PDT 24
Peak memory 206420 kb
Host smart-b7359ad9-c25a-4da2-b720-3e7ddb259e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10462
6706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.104626706
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.894154802
Short name T2507
Test name
Test status
Simulation time 135991416 ps
CPU time 0.79 seconds
Started Jun 24 05:22:02 PM PDT 24
Finished Jun 24 05:22:04 PM PDT 24
Peak memory 206188 kb
Host smart-1fdba8cb-8d2f-498b-8089-e664038a762d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89415
4802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.894154802
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3629236653
Short name T1257
Test name
Test status
Simulation time 176365452 ps
CPU time 0.83 seconds
Started Jun 24 05:22:08 PM PDT 24
Finished Jun 24 05:22:10 PM PDT 24
Peak memory 206188 kb
Host smart-ff296d1d-ae44-4484-9861-4f1bd3dfad6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36292
36653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3629236653
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.2211968385
Short name T1643
Test name
Test status
Simulation time 7289701350 ps
CPU time 203.89 seconds
Started Jun 24 05:22:02 PM PDT 24
Finished Jun 24 05:25:28 PM PDT 24
Peak memory 206392 kb
Host smart-f491ff8e-fc9b-416c-8835-4fcbdadb9b68
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2211968385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.2211968385
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3907629331
Short name T640
Test name
Test status
Simulation time 221200935 ps
CPU time 0.87 seconds
Started Jun 24 05:22:02 PM PDT 24
Finished Jun 24 05:22:04 PM PDT 24
Peak memory 206192 kb
Host smart-1015d14b-8ffd-4b96-a133-eb7dc6a3071b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39076
29331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3907629331
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.2946288470
Short name T428
Test name
Test status
Simulation time 23340254680 ps
CPU time 25.88 seconds
Started Jun 24 05:22:04 PM PDT 24
Finished Jun 24 05:22:32 PM PDT 24
Peak memory 206244 kb
Host smart-1fb51157-a8d8-4a51-a4b9-9c74ed0d4d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29462
88470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.2946288470
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1862968043
Short name T1877
Test name
Test status
Simulation time 3279302049 ps
CPU time 3.63 seconds
Started Jun 24 05:22:01 PM PDT 24
Finished Jun 24 05:22:06 PM PDT 24
Peak memory 206232 kb
Host smart-c9cb3608-6e79-422b-b8c5-6e423d654006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18629
68043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1862968043
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.179014895
Short name T1784
Test name
Test status
Simulation time 4661419763 ps
CPU time 130.55 seconds
Started Jun 24 05:22:00 PM PDT 24
Finished Jun 24 05:24:11 PM PDT 24
Peak memory 206584 kb
Host smart-f3b3149a-7c53-471a-adfa-43e52a25cfc6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=179014895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.179014895
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.2854463147
Short name T497
Test name
Test status
Simulation time 232474478 ps
CPU time 0.97 seconds
Started Jun 24 05:22:02 PM PDT 24
Finished Jun 24 05:22:05 PM PDT 24
Peak memory 206388 kb
Host smart-19e55006-60b0-4e86-b112-3aa343dedaf7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2854463147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.2854463147
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1140439637
Short name T252
Test name
Test status
Simulation time 197747099 ps
CPU time 0.86 seconds
Started Jun 24 05:22:04 PM PDT 24
Finished Jun 24 05:22:07 PM PDT 24
Peak memory 206164 kb
Host smart-ce5d4415-2ef8-4b8b-b23f-f528e8382164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11404
39637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1140439637
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.2926501752
Short name T2148
Test name
Test status
Simulation time 7191326761 ps
CPU time 52.16 seconds
Started Jun 24 05:22:00 PM PDT 24
Finished Jun 24 05:22:53 PM PDT 24
Peak memory 206328 kb
Host smart-0ebfee8e-1988-4166-8851-4cb6ffa9fef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29265
01752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.2926501752
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.3913641219
Short name T1289
Test name
Test status
Simulation time 9302306805 ps
CPU time 69.53 seconds
Started Jun 24 05:22:04 PM PDT 24
Finished Jun 24 05:23:15 PM PDT 24
Peak memory 206396 kb
Host smart-4ef536f7-e35e-4315-8964-70f6a6577f6b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3913641219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.3913641219
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.2351608280
Short name T421
Test name
Test status
Simulation time 163123535 ps
CPU time 0.8 seconds
Started Jun 24 05:22:01 PM PDT 24
Finished Jun 24 05:22:03 PM PDT 24
Peak memory 206192 kb
Host smart-474caf6b-9521-47c0-a8e8-e9cfbda3256d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2351608280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.2351608280
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2989321220
Short name T1312
Test name
Test status
Simulation time 184629993 ps
CPU time 0.81 seconds
Started Jun 24 05:21:59 PM PDT 24
Finished Jun 24 05:22:00 PM PDT 24
Peak memory 206076 kb
Host smart-f535741b-261b-4612-8220-ae19edca6269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29893
21220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2989321220
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2161380023
Short name T1696
Test name
Test status
Simulation time 179091114 ps
CPU time 0.84 seconds
Started Jun 24 05:22:05 PM PDT 24
Finished Jun 24 05:22:07 PM PDT 24
Peak memory 206192 kb
Host smart-6cd7647e-8019-4401-897f-1240a9615d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21613
80023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2161380023
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1693722960
Short name T2269
Test name
Test status
Simulation time 192393666 ps
CPU time 0.82 seconds
Started Jun 24 05:22:02 PM PDT 24
Finished Jun 24 05:22:05 PM PDT 24
Peak memory 206080 kb
Host smart-ddbb28cd-d62c-47cb-a931-58f844b72e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16937
22960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1693722960
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3002215362
Short name T458
Test name
Test status
Simulation time 212771586 ps
CPU time 0.83 seconds
Started Jun 24 05:22:06 PM PDT 24
Finished Jun 24 05:22:08 PM PDT 24
Peak memory 206192 kb
Host smart-ce7df27d-5763-4bd8-9a42-cde0c5e299df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30022
15362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3002215362
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.2683304935
Short name T1892
Test name
Test status
Simulation time 195076958 ps
CPU time 0.92 seconds
Started Jun 24 05:22:00 PM PDT 24
Finished Jun 24 05:22:02 PM PDT 24
Peak memory 206164 kb
Host smart-cd6000cf-39e9-44b9-91b5-07dc9bec65e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26833
04935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.2683304935
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.712083482
Short name T1450
Test name
Test status
Simulation time 243210410 ps
CPU time 1 seconds
Started Jun 24 05:22:01 PM PDT 24
Finished Jun 24 05:22:03 PM PDT 24
Peak memory 206056 kb
Host smart-582294fb-3e9d-49c9-a41a-2840c68a183f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=712083482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.712083482
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1228215322
Short name T25
Test name
Test status
Simulation time 36699654 ps
CPU time 0.66 seconds
Started Jun 24 05:22:02 PM PDT 24
Finished Jun 24 05:22:05 PM PDT 24
Peak memory 206188 kb
Host smart-039634fc-fe45-42aa-8fa4-e41ea2e2639f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12282
15322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1228215322
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3323486321
Short name T186
Test name
Test status
Simulation time 10388039456 ps
CPU time 25.44 seconds
Started Jun 24 05:22:01 PM PDT 24
Finished Jun 24 05:22:28 PM PDT 24
Peak memory 206376 kb
Host smart-6609eb67-4768-4519-a0fa-355f7a04c619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33234
86321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3323486321
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2782842371
Short name T612
Test name
Test status
Simulation time 153223363 ps
CPU time 0.84 seconds
Started Jun 24 05:22:02 PM PDT 24
Finished Jun 24 05:22:04 PM PDT 24
Peak memory 206180 kb
Host smart-5c576f74-0d9c-45eb-8807-397a9d0b91dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27828
42371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2782842371
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2476407278
Short name T542
Test name
Test status
Simulation time 204291312 ps
CPU time 0.96 seconds
Started Jun 24 05:22:00 PM PDT 24
Finished Jun 24 05:22:02 PM PDT 24
Peak memory 206192 kb
Host smart-456cf5a8-b26e-49bf-abe2-2f689ddaa041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24764
07278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2476407278
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.497569428
Short name T1196
Test name
Test status
Simulation time 164270378 ps
CPU time 0.8 seconds
Started Jun 24 05:22:03 PM PDT 24
Finished Jun 24 05:22:06 PM PDT 24
Peak memory 206196 kb
Host smart-e7aab11a-5a1a-4bc9-875b-61e8180ba89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49756
9428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.497569428
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.1538003537
Short name T2441
Test name
Test status
Simulation time 172273226 ps
CPU time 0.78 seconds
Started Jun 24 05:22:01 PM PDT 24
Finished Jun 24 05:22:04 PM PDT 24
Peak memory 206212 kb
Host smart-72d63609-3b80-45ee-8558-24801ad48e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15380
03537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.1538003537
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3618324964
Short name T2207
Test name
Test status
Simulation time 173399991 ps
CPU time 0.79 seconds
Started Jun 24 05:22:00 PM PDT 24
Finished Jun 24 05:22:02 PM PDT 24
Peak memory 206088 kb
Host smart-a720626c-34ce-4175-9b63-9b54933b5e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36183
24964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3618324964
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3271324167
Short name T649
Test name
Test status
Simulation time 202192602 ps
CPU time 0.78 seconds
Started Jun 24 05:22:01 PM PDT 24
Finished Jun 24 05:22:02 PM PDT 24
Peak memory 206192 kb
Host smart-a1877d39-86ca-4b63-8fdc-7d492b6e3ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32713
24167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3271324167
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.2655449218
Short name T1182
Test name
Test status
Simulation time 150833549 ps
CPU time 0.8 seconds
Started Jun 24 05:22:02 PM PDT 24
Finished Jun 24 05:22:05 PM PDT 24
Peak memory 206056 kb
Host smart-ed9f6e2b-8bd7-48a1-be0a-8959ea07139a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26554
49218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.2655449218
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.4260896494
Short name T736
Test name
Test status
Simulation time 221832990 ps
CPU time 0.86 seconds
Started Jun 24 05:22:05 PM PDT 24
Finished Jun 24 05:22:07 PM PDT 24
Peak memory 206192 kb
Host smart-e2b42dc2-dce6-4495-b97d-8041915a4416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42608
96494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.4260896494
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.4142861829
Short name T561
Test name
Test status
Simulation time 7787680742 ps
CPU time 73.81 seconds
Started Jun 24 05:21:59 PM PDT 24
Finished Jun 24 05:23:13 PM PDT 24
Peak memory 206304 kb
Host smart-14a83914-7bea-4373-b8a8-6ce75f949fb1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4142861829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.4142861829
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.317696014
Short name T856
Test name
Test status
Simulation time 142628103 ps
CPU time 0.79 seconds
Started Jun 24 05:22:01 PM PDT 24
Finished Jun 24 05:22:04 PM PDT 24
Peak memory 206156 kb
Host smart-b95d5c89-ff5e-47de-aa06-a81d028d1cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31769
6014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.317696014
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3523272252
Short name T105
Test name
Test status
Simulation time 144933503 ps
CPU time 0.79 seconds
Started Jun 24 05:22:02 PM PDT 24
Finished Jun 24 05:22:05 PM PDT 24
Peak memory 206192 kb
Host smart-715799fb-571e-4f10-836d-6a1de6273caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35232
72252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3523272252
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.834568154
Short name T2301
Test name
Test status
Simulation time 14704675724 ps
CPU time 138.47 seconds
Started Jun 24 05:21:59 PM PDT 24
Finished Jun 24 05:24:18 PM PDT 24
Peak memory 206316 kb
Host smart-4598687e-087a-4985-abca-62d2ce7cca9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83456
8154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.834568154
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.3633796835
Short name T1302
Test name
Test status
Simulation time 4261199490 ps
CPU time 4.67 seconds
Started Jun 24 05:22:10 PM PDT 24
Finished Jun 24 05:22:16 PM PDT 24
Peak memory 206264 kb
Host smart-ead0a1f2-ca6e-4ddc-86f9-7da12d22239f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3633796835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.3633796835
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.2023293989
Short name T645
Test name
Test status
Simulation time 13384632606 ps
CPU time 15 seconds
Started Jun 24 05:22:07 PM PDT 24
Finished Jun 24 05:22:22 PM PDT 24
Peak memory 206280 kb
Host smart-bf56fda0-c2e1-42be-8313-26225a3f0a86
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2023293989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.2023293989
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.280622917
Short name T1910
Test name
Test status
Simulation time 23344590646 ps
CPU time 23.92 seconds
Started Jun 24 05:22:07 PM PDT 24
Finished Jun 24 05:22:31 PM PDT 24
Peak memory 206128 kb
Host smart-1047a761-7bc0-4018-842d-2cc207f117a1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=280622917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.280622917
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1482416839
Short name T2376
Test name
Test status
Simulation time 159783134 ps
CPU time 0.8 seconds
Started Jun 24 05:22:08 PM PDT 24
Finished Jun 24 05:22:11 PM PDT 24
Peak memory 206140 kb
Host smart-41aebb5f-c362-49c2-90d5-f527a2cc45cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14824
16839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1482416839
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.1061939440
Short name T2365
Test name
Test status
Simulation time 154733850 ps
CPU time 0.8 seconds
Started Jun 24 05:22:11 PM PDT 24
Finished Jun 24 05:22:14 PM PDT 24
Peak memory 206080 kb
Host smart-01a5a236-f4b1-4cbe-b340-352dbeecd813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10619
39440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.1061939440
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.671649630
Short name T1726
Test name
Test status
Simulation time 357552856 ps
CPU time 1.24 seconds
Started Jun 24 05:22:08 PM PDT 24
Finished Jun 24 05:22:11 PM PDT 24
Peak memory 206168 kb
Host smart-e2a7a73a-1758-4f67-90da-7ddbdb980d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67164
9630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.671649630
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.473977152
Short name T2434
Test name
Test status
Simulation time 481251335 ps
CPU time 1.32 seconds
Started Jun 24 05:22:11 PM PDT 24
Finished Jun 24 05:22:16 PM PDT 24
Peak memory 206168 kb
Host smart-a5272e9c-f233-4629-87d6-6052a0c5355a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47397
7152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.473977152
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.873658981
Short name T1128
Test name
Test status
Simulation time 16210988368 ps
CPU time 29.04 seconds
Started Jun 24 05:22:11 PM PDT 24
Finished Jun 24 05:22:43 PM PDT 24
Peak memory 206320 kb
Host smart-17ae359a-89ab-4370-8020-14a1b8263a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87365
8981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.873658981
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.2481348552
Short name T1971
Test name
Test status
Simulation time 457525207 ps
CPU time 1.3 seconds
Started Jun 24 05:22:10 PM PDT 24
Finished Jun 24 05:22:13 PM PDT 24
Peak memory 206168 kb
Host smart-4387a7cd-6a53-4e6e-8482-fc2827b9a5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24813
48552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.2481348552
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.3674790464
Short name T2402
Test name
Test status
Simulation time 160422708 ps
CPU time 0.74 seconds
Started Jun 24 05:22:09 PM PDT 24
Finished Jun 24 05:22:12 PM PDT 24
Peak memory 206072 kb
Host smart-fdeb65d3-2cee-4c14-a181-4539f41c35fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36747
90464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.3674790464
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2516761342
Short name T2231
Test name
Test status
Simulation time 70167948 ps
CPU time 0.68 seconds
Started Jun 24 05:22:09 PM PDT 24
Finished Jun 24 05:22:12 PM PDT 24
Peak memory 206160 kb
Host smart-8804fe01-9872-4213-8f10-9d6ae4cc418f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25167
61342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2516761342
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1130813431
Short name T445
Test name
Test status
Simulation time 872036899 ps
CPU time 2.12 seconds
Started Jun 24 05:22:07 PM PDT 24
Finished Jun 24 05:22:10 PM PDT 24
Peak memory 206292 kb
Host smart-72a3dcdc-c0f6-4b98-a556-608aa1abebd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11308
13431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1130813431
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.620105106
Short name T1209
Test name
Test status
Simulation time 168681182 ps
CPU time 1.69 seconds
Started Jun 24 05:22:12 PM PDT 24
Finished Jun 24 05:22:16 PM PDT 24
Peak memory 206316 kb
Host smart-af2fa416-117a-4978-adc3-cdd9d540a4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62010
5106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.620105106
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2247207428
Short name T2480
Test name
Test status
Simulation time 230363265 ps
CPU time 0.98 seconds
Started Jun 24 05:22:11 PM PDT 24
Finished Jun 24 05:22:15 PM PDT 24
Peak memory 206076 kb
Host smart-c604916e-39d1-4757-b5b7-914e6322991e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22472
07428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2247207428
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.413205421
Short name T1011
Test name
Test status
Simulation time 169864514 ps
CPU time 0.78 seconds
Started Jun 24 05:22:08 PM PDT 24
Finished Jun 24 05:22:10 PM PDT 24
Peak memory 206152 kb
Host smart-c270cd05-47b0-4869-93b2-30c95081a3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41320
5421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.413205421
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2010161330
Short name T1566
Test name
Test status
Simulation time 265097817 ps
CPU time 0.91 seconds
Started Jun 24 05:22:08 PM PDT 24
Finished Jun 24 05:22:09 PM PDT 24
Peak memory 206172 kb
Host smart-2a052ebc-1dcd-4bf9-bf22-fe8e22500a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20101
61330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2010161330
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.4146641052
Short name T1466
Test name
Test status
Simulation time 189648502 ps
CPU time 0.89 seconds
Started Jun 24 05:22:10 PM PDT 24
Finished Jun 24 05:22:13 PM PDT 24
Peak memory 206108 kb
Host smart-affb3e79-fbb0-47cb-97c7-9ea2016fc376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41466
41052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.4146641052
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.2030420092
Short name T945
Test name
Test status
Simulation time 23318195714 ps
CPU time 24.96 seconds
Started Jun 24 05:22:08 PM PDT 24
Finished Jun 24 05:22:33 PM PDT 24
Peak memory 206252 kb
Host smart-37866113-7a87-402c-a1c6-f02ced5ade51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20304
20092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.2030420092
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.2878683622
Short name T222
Test name
Test status
Simulation time 3303701444 ps
CPU time 3.8 seconds
Started Jun 24 05:22:12 PM PDT 24
Finished Jun 24 05:22:18 PM PDT 24
Peak memory 206204 kb
Host smart-12f2875e-01e7-4d0f-a1a1-cb1dcf112410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28786
83622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.2878683622
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.4209113762
Short name T1082
Test name
Test status
Simulation time 5105191039 ps
CPU time 36.61 seconds
Started Jun 24 05:22:08 PM PDT 24
Finished Jun 24 05:22:45 PM PDT 24
Peak memory 206328 kb
Host smart-0ffeba17-5c8e-4074-bd67-b95e0ca7fbbd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4209113762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.4209113762
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.355902485
Short name T1237
Test name
Test status
Simulation time 242235762 ps
CPU time 0.91 seconds
Started Jun 24 05:22:21 PM PDT 24
Finished Jun 24 05:22:23 PM PDT 24
Peak memory 206192 kb
Host smart-5a9032f7-b69d-4cb7-b6c4-e9e38f9fa8b8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=355902485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.355902485
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3530292446
Short name T544
Test name
Test status
Simulation time 201487228 ps
CPU time 0.85 seconds
Started Jun 24 05:22:10 PM PDT 24
Finished Jun 24 05:22:13 PM PDT 24
Peak memory 206360 kb
Host smart-e0466f76-295d-4d38-9269-3a6200559c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35302
92446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3530292446
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.3422211898
Short name T533
Test name
Test status
Simulation time 12560281628 ps
CPU time 346.55 seconds
Started Jun 24 05:22:08 PM PDT 24
Finished Jun 24 05:27:57 PM PDT 24
Peak memory 206360 kb
Host smart-1abc879d-5688-4e3a-a83d-48eda7db95a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34222
11898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.3422211898
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.988207073
Short name T850
Test name
Test status
Simulation time 9849249106 ps
CPU time 69.15 seconds
Started Jun 24 05:22:12 PM PDT 24
Finished Jun 24 05:23:23 PM PDT 24
Peak memory 206416 kb
Host smart-91c5dc58-9db5-48af-a727-af98999d991b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=988207073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.988207073
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.724894208
Short name T836
Test name
Test status
Simulation time 153572742 ps
CPU time 0.81 seconds
Started Jun 24 05:22:13 PM PDT 24
Finished Jun 24 05:22:17 PM PDT 24
Peak memory 206192 kb
Host smart-1f771a77-eee0-42e7-b674-f5bb0c9460a7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=724894208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.724894208
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3652142618
Short name T330
Test name
Test status
Simulation time 150783482 ps
CPU time 0.78 seconds
Started Jun 24 05:22:11 PM PDT 24
Finished Jun 24 05:22:15 PM PDT 24
Peak memory 206176 kb
Host smart-46d25807-3f75-4acd-864b-932680040926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36521
42618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3652142618
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.1156914917
Short name T2248
Test name
Test status
Simulation time 164458748 ps
CPU time 0.82 seconds
Started Jun 24 05:22:11 PM PDT 24
Finished Jun 24 05:22:15 PM PDT 24
Peak memory 206192 kb
Host smart-fd7c3037-02d2-46df-b0b2-10768fb65e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11569
14917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.1156914917
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2046084088
Short name T2236
Test name
Test status
Simulation time 174861689 ps
CPU time 0.82 seconds
Started Jun 24 05:22:06 PM PDT 24
Finished Jun 24 05:22:08 PM PDT 24
Peak memory 206180 kb
Host smart-3653c141-91c4-43a2-9cb1-d7885f570cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20460
84088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2046084088
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2759629379
Short name T886
Test name
Test status
Simulation time 195866533 ps
CPU time 0.81 seconds
Started Jun 24 05:22:14 PM PDT 24
Finished Jun 24 05:22:17 PM PDT 24
Peak memory 206196 kb
Host smart-20de07d5-acc1-469f-b0ac-77e35fded27e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27596
29379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2759629379
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2083576454
Short name T2370
Test name
Test status
Simulation time 154445910 ps
CPU time 0.78 seconds
Started Jun 24 05:22:09 PM PDT 24
Finished Jun 24 05:22:11 PM PDT 24
Peak memory 206136 kb
Host smart-f4faa8f7-1d16-446a-b735-d63996b1e6ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20835
76454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2083576454
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.1520387616
Short name T1328
Test name
Test status
Simulation time 212055473 ps
CPU time 0.97 seconds
Started Jun 24 05:22:12 PM PDT 24
Finished Jun 24 05:22:16 PM PDT 24
Peak memory 206144 kb
Host smart-17202df3-ba90-4533-b0a8-a7e807fac9de
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1520387616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.1520387616
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.50563549
Short name T336
Test name
Test status
Simulation time 185476283 ps
CPU time 0.84 seconds
Started Jun 24 05:22:11 PM PDT 24
Finished Jun 24 05:22:14 PM PDT 24
Peak memory 206060 kb
Host smart-ad357883-3835-42e3-9ef3-fe520b598e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50563
549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.50563549
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1224871434
Short name T569
Test name
Test status
Simulation time 56364122 ps
CPU time 0.7 seconds
Started Jun 24 05:22:13 PM PDT 24
Finished Jun 24 05:22:16 PM PDT 24
Peak memory 206184 kb
Host smart-bbbe5700-1dbb-4a74-94ce-f58ef4b374b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12248
71434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1224871434
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.134810441
Short name T185
Test name
Test status
Simulation time 15471671423 ps
CPU time 36.14 seconds
Started Jun 24 05:22:12 PM PDT 24
Finished Jun 24 05:22:51 PM PDT 24
Peak memory 206388 kb
Host smart-5d117caa-0ff1-4cb2-ad34-4b3f885c22ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13481
0441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.134810441
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1288235197
Short name T1249
Test name
Test status
Simulation time 215983885 ps
CPU time 0.85 seconds
Started Jun 24 05:22:08 PM PDT 24
Finished Jun 24 05:22:10 PM PDT 24
Peak memory 206168 kb
Host smart-f61ae984-e0f4-4cbc-bfa0-58c6843f2aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12882
35197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1288235197
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.781617649
Short name T1805
Test name
Test status
Simulation time 149478191 ps
CPU time 0.81 seconds
Started Jun 24 05:22:11 PM PDT 24
Finished Jun 24 05:22:14 PM PDT 24
Peak memory 206112 kb
Host smart-ee90f369-9bce-4def-b9d9-63d6fff9abb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78161
7649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.781617649
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.4165020362
Short name T1371
Test name
Test status
Simulation time 246167183 ps
CPU time 0.87 seconds
Started Jun 24 05:22:11 PM PDT 24
Finished Jun 24 05:22:14 PM PDT 24
Peak memory 206200 kb
Host smart-47e04079-df56-4a5a-b492-750cd65e8255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41650
20362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.4165020362
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.391230417
Short name T1283
Test name
Test status
Simulation time 178222738 ps
CPU time 0.93 seconds
Started Jun 24 05:22:11 PM PDT 24
Finished Jun 24 05:22:15 PM PDT 24
Peak memory 206096 kb
Host smart-ce1d0875-64c1-4a43-b3b3-857af4819cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39123
0417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.391230417
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1490512814
Short name T1487
Test name
Test status
Simulation time 146994967 ps
CPU time 0.73 seconds
Started Jun 24 05:22:08 PM PDT 24
Finished Jun 24 05:22:10 PM PDT 24
Peak memory 206108 kb
Host smart-ccc7603b-9037-44a1-bfea-56f398f0ff70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14905
12814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1490512814
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1265826301
Short name T1354
Test name
Test status
Simulation time 161059563 ps
CPU time 0.82 seconds
Started Jun 24 05:22:12 PM PDT 24
Finished Jun 24 05:22:16 PM PDT 24
Peak memory 206168 kb
Host smart-d9130dcf-75d7-46da-8a50-15de1b770fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12658
26301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1265826301
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.910803105
Short name T48
Test name
Test status
Simulation time 156553365 ps
CPU time 0.83 seconds
Started Jun 24 05:22:13 PM PDT 24
Finished Jun 24 05:22:17 PM PDT 24
Peak memory 206172 kb
Host smart-43c53701-63be-43f3-901f-3a44f5483ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91080
3105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.910803105
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1388531529
Short name T1361
Test name
Test status
Simulation time 223172176 ps
CPU time 0.93 seconds
Started Jun 24 05:22:24 PM PDT 24
Finished Jun 24 05:22:25 PM PDT 24
Peak memory 206116 kb
Host smart-ab73c213-b6e4-4198-a8b4-262fc768e336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13885
31529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1388531529
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.3597647164
Short name T2258
Test name
Test status
Simulation time 10055384309 ps
CPU time 281.14 seconds
Started Jun 24 05:22:14 PM PDT 24
Finished Jun 24 05:26:57 PM PDT 24
Peak memory 206392 kb
Host smart-8e72ebf3-4ae2-47b2-8725-5be7fcfe98a6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3597647164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.3597647164
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.379149456
Short name T1274
Test name
Test status
Simulation time 172712135 ps
CPU time 0.83 seconds
Started Jun 24 05:22:11 PM PDT 24
Finished Jun 24 05:22:14 PM PDT 24
Peak memory 206096 kb
Host smart-acf0b34a-0313-49a4-ac6c-9a0231d513f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37914
9456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.379149456
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.2377817681
Short name T1687
Test name
Test status
Simulation time 189136868 ps
CPU time 0.88 seconds
Started Jun 24 05:22:09 PM PDT 24
Finished Jun 24 05:22:11 PM PDT 24
Peak memory 206192 kb
Host smart-a6cf29f2-0ec2-4b08-99de-ffe9f89ed3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23778
17681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.2377817681
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.3582463552
Short name T805
Test name
Test status
Simulation time 8096948918 ps
CPU time 222.03 seconds
Started Jun 24 05:22:10 PM PDT 24
Finished Jun 24 05:25:54 PM PDT 24
Peak memory 206312 kb
Host smart-7643c5f5-f8e4-4461-9a95-fc721681ec51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35824
63552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.3582463552
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.2021225475
Short name T951
Test name
Test status
Simulation time 4424748683 ps
CPU time 5.24 seconds
Started Jun 24 05:22:19 PM PDT 24
Finished Jun 24 05:22:25 PM PDT 24
Peak memory 206312 kb
Host smart-cb585197-2ead-45bc-83bf-f2a81fe61acc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2021225475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.2021225475
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.642770680
Short name T1093
Test name
Test status
Simulation time 13388315157 ps
CPU time 12.58 seconds
Started Jun 24 05:22:17 PM PDT 24
Finished Jun 24 05:22:30 PM PDT 24
Peak memory 206260 kb
Host smart-63a80b19-db31-4793-af97-c68fe9b4465f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=642770680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.642770680
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.1227119972
Short name T231
Test name
Test status
Simulation time 23398617113 ps
CPU time 22.92 seconds
Started Jun 24 05:22:18 PM PDT 24
Finished Jun 24 05:22:42 PM PDT 24
Peak memory 206344 kb
Host smart-9bb9c476-3d40-47c3-85a4-099f6989616a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1227119972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.1227119972
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3206519835
Short name T758
Test name
Test status
Simulation time 155828932 ps
CPU time 0.81 seconds
Started Jun 24 05:22:17 PM PDT 24
Finished Jun 24 05:22:19 PM PDT 24
Peak memory 206180 kb
Host smart-ce5187f8-e57b-491a-ae4c-c15549092aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32065
19835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3206519835
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.731996932
Short name T1370
Test name
Test status
Simulation time 185668781 ps
CPU time 0.83 seconds
Started Jun 24 05:22:19 PM PDT 24
Finished Jun 24 05:22:21 PM PDT 24
Peak memory 206424 kb
Host smart-00679076-ae1e-4a75-9f2f-8fe75ab8bbe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73199
6932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.731996932
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.2189737491
Short name T1219
Test name
Test status
Simulation time 539572033 ps
CPU time 1.55 seconds
Started Jun 24 05:22:18 PM PDT 24
Finished Jun 24 05:22:20 PM PDT 24
Peak memory 206192 kb
Host smart-dc2046e7-70d8-4358-90e4-b772ff741a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21897
37491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.2189737491
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.726033227
Short name T172
Test name
Test status
Simulation time 572201708 ps
CPU time 1.46 seconds
Started Jun 24 05:22:21 PM PDT 24
Finished Jun 24 05:22:24 PM PDT 24
Peak memory 206148 kb
Host smart-e15cc55e-2460-430b-9895-ee0b5ca9ca2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72603
3227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.726033227
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.605320907
Short name T1747
Test name
Test status
Simulation time 15086332564 ps
CPU time 27.4 seconds
Started Jun 24 05:22:17 PM PDT 24
Finished Jun 24 05:22:45 PM PDT 24
Peak memory 206376 kb
Host smart-2159b0a6-044e-4b89-b035-6701983e524f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60532
0907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.605320907
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.3127603432
Short name T2072
Test name
Test status
Simulation time 340722065 ps
CPU time 1.12 seconds
Started Jun 24 05:22:20 PM PDT 24
Finished Jun 24 05:22:22 PM PDT 24
Peak memory 206052 kb
Host smart-5b95da07-859c-4273-9805-8c396716078b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31276
03432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.3127603432
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3437251227
Short name T1400
Test name
Test status
Simulation time 160984257 ps
CPU time 0.77 seconds
Started Jun 24 05:22:18 PM PDT 24
Finished Jun 24 05:22:20 PM PDT 24
Peak memory 206072 kb
Host smart-5bb8758f-5527-45ea-bd78-07bdd7574bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34372
51227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3437251227
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.370917530
Short name T1572
Test name
Test status
Simulation time 60437571 ps
CPU time 0.7 seconds
Started Jun 24 05:22:20 PM PDT 24
Finished Jun 24 05:22:22 PM PDT 24
Peak memory 206168 kb
Host smart-d2951fd4-f9ab-4283-856d-55c810d8dee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37091
7530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.370917530
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1800107606
Short name T891
Test name
Test status
Simulation time 828887996 ps
CPU time 2.15 seconds
Started Jun 24 05:22:19 PM PDT 24
Finished Jun 24 05:22:22 PM PDT 24
Peak memory 206228 kb
Host smart-19a65477-b4b0-4fd6-940f-7fd8fd265334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18001
07606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1800107606
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2902913811
Short name T1327
Test name
Test status
Simulation time 266776806 ps
CPU time 1.85 seconds
Started Jun 24 05:22:20 PM PDT 24
Finished Jun 24 05:22:23 PM PDT 24
Peak memory 206148 kb
Host smart-71cc22dd-a6a1-4954-aa37-c0b44943e774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29029
13811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2902913811
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.250165203
Short name T790
Test name
Test status
Simulation time 193136446 ps
CPU time 0.87 seconds
Started Jun 24 05:22:29 PM PDT 24
Finished Jun 24 05:22:31 PM PDT 24
Peak memory 206088 kb
Host smart-0651e0b8-09b3-405a-b946-a1c00d62ba8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25016
5203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.250165203
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3397008878
Short name T2325
Test name
Test status
Simulation time 142387678 ps
CPU time 0.74 seconds
Started Jun 24 05:22:29 PM PDT 24
Finished Jun 24 05:22:32 PM PDT 24
Peak memory 206164 kb
Host smart-7292ebbd-4ba4-4a78-9c16-e003c60ff234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33970
08878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3397008878
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.941070164
Short name T2157
Test name
Test status
Simulation time 211776264 ps
CPU time 0.85 seconds
Started Jun 24 05:22:17 PM PDT 24
Finished Jun 24 05:22:19 PM PDT 24
Peak memory 206172 kb
Host smart-01c1fd32-887b-4b49-858f-c626e0c8c313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94107
0164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.941070164
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.3886190849
Short name T494
Test name
Test status
Simulation time 213285635 ps
CPU time 0.94 seconds
Started Jun 24 05:22:17 PM PDT 24
Finished Jun 24 05:22:19 PM PDT 24
Peak memory 206164 kb
Host smart-57c1a869-340b-4bfa-acb8-e86403bc582a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38861
90849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3886190849
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2808872321
Short name T311
Test name
Test status
Simulation time 23353041823 ps
CPU time 21.92 seconds
Started Jun 24 05:22:19 PM PDT 24
Finished Jun 24 05:22:42 PM PDT 24
Peak memory 206256 kb
Host smart-75332179-e633-4cb4-aea8-8eaa1facbc03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28088
72321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2808872321
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2401506004
Short name T2423
Test name
Test status
Simulation time 3317002097 ps
CPU time 4.11 seconds
Started Jun 24 05:22:16 PM PDT 24
Finished Jun 24 05:22:22 PM PDT 24
Peak memory 206192 kb
Host smart-82130165-b3b2-41f2-a9b9-194355a6178f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24015
06004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2401506004
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.587953280
Short name T2165
Test name
Test status
Simulation time 8834460297 ps
CPU time 84.38 seconds
Started Jun 24 05:22:17 PM PDT 24
Finished Jun 24 05:23:43 PM PDT 24
Peak memory 206284 kb
Host smart-b0f1e4d8-0c34-4eca-beef-f368922aecfe
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=587953280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.587953280
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.3783430952
Short name T653
Test name
Test status
Simulation time 240921199 ps
CPU time 0.92 seconds
Started Jun 24 05:22:26 PM PDT 24
Finished Jun 24 05:22:28 PM PDT 24
Peak memory 206196 kb
Host smart-157eb813-e570-45af-b04e-637bed4472f2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3783430952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.3783430952
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1252631325
Short name T2050
Test name
Test status
Simulation time 224925624 ps
CPU time 0.89 seconds
Started Jun 24 05:22:17 PM PDT 24
Finished Jun 24 05:22:19 PM PDT 24
Peak memory 206160 kb
Host smart-2b178597-dca1-48ef-beb4-abe95601eef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12526
31325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1252631325
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2739281389
Short name T764
Test name
Test status
Simulation time 5360157762 ps
CPU time 37.53 seconds
Started Jun 24 05:22:22 PM PDT 24
Finished Jun 24 05:23:01 PM PDT 24
Peak memory 206536 kb
Host smart-06e62f6f-0a1a-4678-b15a-3579e7407b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27392
81389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2739281389
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1204830925
Short name T2341
Test name
Test status
Simulation time 3061544242 ps
CPU time 81.55 seconds
Started Jun 24 05:22:17 PM PDT 24
Finished Jun 24 05:23:40 PM PDT 24
Peak memory 206396 kb
Host smart-fbbf0bf0-193a-4486-b153-f5a4d0961d97
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1204830925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1204830925
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.676075334
Short name T629
Test name
Test status
Simulation time 191788162 ps
CPU time 0.81 seconds
Started Jun 24 05:22:25 PM PDT 24
Finished Jun 24 05:22:27 PM PDT 24
Peak memory 206096 kb
Host smart-ab1a9314-99dd-4699-8b39-3d7290032f9b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=676075334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.676075334
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1977237186
Short name T446
Test name
Test status
Simulation time 178696706 ps
CPU time 0.78 seconds
Started Jun 24 05:22:18 PM PDT 24
Finished Jun 24 05:22:20 PM PDT 24
Peak memory 206108 kb
Host smart-5bd82b92-00dc-4477-a5ff-9bfc999e98e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19772
37186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1977237186
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.466665105
Short name T33
Test name
Test status
Simulation time 200368582 ps
CPU time 0.82 seconds
Started Jun 24 05:22:27 PM PDT 24
Finished Jun 24 05:22:29 PM PDT 24
Peak memory 206104 kb
Host smart-0280cddb-8961-42bb-ab45-31de47a427a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46666
5105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.466665105
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3330586785
Short name T410
Test name
Test status
Simulation time 185025639 ps
CPU time 0.84 seconds
Started Jun 24 05:22:31 PM PDT 24
Finished Jun 24 05:22:33 PM PDT 24
Peak memory 206168 kb
Host smart-460febdb-b569-406b-8f54-bc6335784c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33305
86785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3330586785
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.596572933
Short name T796
Test name
Test status
Simulation time 189604790 ps
CPU time 0.84 seconds
Started Jun 24 05:22:31 PM PDT 24
Finished Jun 24 05:22:33 PM PDT 24
Peak memory 206076 kb
Host smart-4bf29aae-c16e-4f6d-ade9-5a082ddd21cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59657
2933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.596572933
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1016612827
Short name T2116
Test name
Test status
Simulation time 166869195 ps
CPU time 0.78 seconds
Started Jun 24 05:22:27 PM PDT 24
Finished Jun 24 05:22:29 PM PDT 24
Peak memory 206152 kb
Host smart-f4e668c6-25a0-4420-a79f-2a3364e8bfa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10166
12827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1016612827
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.3209431522
Short name T619
Test name
Test status
Simulation time 254633309 ps
CPU time 1.08 seconds
Started Jun 24 05:22:30 PM PDT 24
Finished Jun 24 05:22:32 PM PDT 24
Peak memory 206060 kb
Host smart-40c3f996-740d-4278-befb-de7d119a38cc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3209431522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.3209431522
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1291414363
Short name T460
Test name
Test status
Simulation time 144139946 ps
CPU time 0.75 seconds
Started Jun 24 05:22:29 PM PDT 24
Finished Jun 24 05:22:32 PM PDT 24
Peak memory 206176 kb
Host smart-9505719c-3fb4-429a-b958-4b91b866fb40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12914
14363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1291414363
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.2470724678
Short name T1679
Test name
Test status
Simulation time 37538187 ps
CPU time 0.72 seconds
Started Jun 24 05:22:28 PM PDT 24
Finished Jun 24 05:22:30 PM PDT 24
Peak memory 206112 kb
Host smart-a72728f1-d7c8-4b0b-bb13-2839ea799376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24707
24678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.2470724678
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1864147530
Short name T2343
Test name
Test status
Simulation time 16744444169 ps
CPU time 38.53 seconds
Started Jun 24 05:22:28 PM PDT 24
Finished Jun 24 05:23:08 PM PDT 24
Peak memory 206424 kb
Host smart-443157b7-b906-45d6-afc7-7bb604fe8a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18641
47530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1864147530
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.387710780
Short name T614
Test name
Test status
Simulation time 148981283 ps
CPU time 0.83 seconds
Started Jun 24 05:22:26 PM PDT 24
Finished Jun 24 05:22:28 PM PDT 24
Peak memory 206160 kb
Host smart-5f675a10-6b05-4b96-a2b7-30890b655429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38771
0780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.387710780
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.353529772
Short name T636
Test name
Test status
Simulation time 283763941 ps
CPU time 0.92 seconds
Started Jun 24 05:22:30 PM PDT 24
Finished Jun 24 05:22:32 PM PDT 24
Peak memory 206164 kb
Host smart-0aef4849-9c47-4d54-8811-87d1313224dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35352
9772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.353529772
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.2200246837
Short name T2259
Test name
Test status
Simulation time 249392011 ps
CPU time 0.88 seconds
Started Jun 24 05:22:25 PM PDT 24
Finished Jun 24 05:22:26 PM PDT 24
Peak memory 206176 kb
Host smart-19f1d500-e0df-4cd5-bdb7-2f14cc763127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22002
46837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.2200246837
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.3355364395
Short name T2017
Test name
Test status
Simulation time 182553833 ps
CPU time 0.87 seconds
Started Jun 24 05:22:25 PM PDT 24
Finished Jun 24 05:22:27 PM PDT 24
Peak memory 206184 kb
Host smart-103fc96e-3bf7-4fd5-9e4a-152d562fbeb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33553
64395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.3355364395
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.2957303897
Short name T876
Test name
Test status
Simulation time 167520852 ps
CPU time 0.78 seconds
Started Jun 24 05:22:27 PM PDT 24
Finished Jun 24 05:22:28 PM PDT 24
Peak memory 206088 kb
Host smart-fd6bde3a-9946-46d1-aa72-dc77256e4b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29573
03897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.2957303897
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.1814862948
Short name T1344
Test name
Test status
Simulation time 149700361 ps
CPU time 0.73 seconds
Started Jun 24 05:22:25 PM PDT 24
Finished Jun 24 05:22:27 PM PDT 24
Peak memory 206160 kb
Host smart-2ef657c1-b940-4392-99b4-ee1cc1d0516e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18148
62948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.1814862948
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.32812835
Short name T660
Test name
Test status
Simulation time 160945786 ps
CPU time 0.8 seconds
Started Jun 24 05:22:28 PM PDT 24
Finished Jun 24 05:22:30 PM PDT 24
Peak memory 206096 kb
Host smart-7dfaedf2-0ddd-46d9-ab48-e89b5c90605e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32812
835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.32812835
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.693449416
Short name T471
Test name
Test status
Simulation time 254677195 ps
CPU time 0.96 seconds
Started Jun 24 05:22:27 PM PDT 24
Finished Jun 24 05:22:29 PM PDT 24
Peak memory 206192 kb
Host smart-fdd75d3e-3800-453e-96e1-4de9131ea0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69344
9416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.693449416
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.1125329724
Short name T2199
Test name
Test status
Simulation time 4278066311 ps
CPU time 29.73 seconds
Started Jun 24 05:22:30 PM PDT 24
Finished Jun 24 05:23:01 PM PDT 24
Peak memory 206192 kb
Host smart-533c3e4e-9f24-4f4a-9c96-526b512e1d55
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1125329724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.1125329724
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3509938875
Short name T1114
Test name
Test status
Simulation time 176684326 ps
CPU time 0.84 seconds
Started Jun 24 05:22:27 PM PDT 24
Finished Jun 24 05:22:28 PM PDT 24
Peak memory 206180 kb
Host smart-86fdf13c-4629-4890-97dc-76ef5ae87718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35099
38875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3509938875
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2943355788
Short name T351
Test name
Test status
Simulation time 192907378 ps
CPU time 0.82 seconds
Started Jun 24 05:22:24 PM PDT 24
Finished Jun 24 05:22:26 PM PDT 24
Peak memory 206172 kb
Host smart-bac4a71a-63b1-427e-b028-52f1bc3b4532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29433
55788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2943355788
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.2576843820
Short name T352
Test name
Test status
Simulation time 4338126471 ps
CPU time 30.06 seconds
Started Jun 24 05:22:27 PM PDT 24
Finished Jun 24 05:22:58 PM PDT 24
Peak memory 206576 kb
Host smart-57082700-927a-4c83-8d44-549967dd07b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25768
43820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.2576843820
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.1068289856
Short name T1551
Test name
Test status
Simulation time 4203404139 ps
CPU time 5.34 seconds
Started Jun 24 05:22:30 PM PDT 24
Finished Jun 24 05:22:37 PM PDT 24
Peak memory 206428 kb
Host smart-386c03eb-67fa-4561-8771-26d8eed2f214
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1068289856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.1068289856
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.1315246971
Short name T807
Test name
Test status
Simulation time 13314081339 ps
CPU time 12.84 seconds
Started Jun 24 05:22:29 PM PDT 24
Finished Jun 24 05:22:43 PM PDT 24
Peak memory 206216 kb
Host smart-1b4aeaeb-54cb-4c79-8631-5ad0459c4f3a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1315246971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.1315246971
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.1655320958
Short name T2033
Test name
Test status
Simulation time 23402074218 ps
CPU time 25.79 seconds
Started Jun 24 05:22:31 PM PDT 24
Finished Jun 24 05:22:58 PM PDT 24
Peak memory 206304 kb
Host smart-7c261824-9617-4acf-ac6a-830fefe7c5df
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1655320958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.1655320958
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.981016249
Short name T507
Test name
Test status
Simulation time 188857427 ps
CPU time 0.86 seconds
Started Jun 24 05:22:27 PM PDT 24
Finished Jun 24 05:22:28 PM PDT 24
Peak memory 206176 kb
Host smart-42ea2095-0fa2-4bf4-9424-6ff44605126c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98101
6249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.981016249
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.332421795
Short name T1492
Test name
Test status
Simulation time 156409773 ps
CPU time 0.83 seconds
Started Jun 24 05:22:27 PM PDT 24
Finished Jun 24 05:22:28 PM PDT 24
Peak memory 206156 kb
Host smart-3786912a-3510-4ded-a6d5-b030b015aca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33242
1795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.332421795
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3065293743
Short name T1437
Test name
Test status
Simulation time 296379348 ps
CPU time 1.05 seconds
Started Jun 24 05:22:30 PM PDT 24
Finished Jun 24 05:22:33 PM PDT 24
Peak memory 206160 kb
Host smart-6bb8a70e-8eb5-480f-a8d8-6b53aad8bd77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30652
93743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3065293743
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2203172401
Short name T516
Test name
Test status
Simulation time 654393601 ps
CPU time 1.74 seconds
Started Jun 24 05:22:29 PM PDT 24
Finished Jun 24 05:22:32 PM PDT 24
Peak memory 206428 kb
Host smart-8a7778ca-04e8-42a8-9ed9-857ddc6c41ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22031
72401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2203172401
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.530637520
Short name T98
Test name
Test status
Simulation time 20972527930 ps
CPU time 37.93 seconds
Started Jun 24 05:22:24 PM PDT 24
Finished Jun 24 05:23:02 PM PDT 24
Peak memory 206636 kb
Host smart-f164eb11-4d2b-4dee-95cc-c662695342f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53063
7520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.530637520
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2133221222
Short name T2234
Test name
Test status
Simulation time 427442867 ps
CPU time 1.29 seconds
Started Jun 24 05:22:29 PM PDT 24
Finished Jun 24 05:22:32 PM PDT 24
Peak memory 206360 kb
Host smart-bfe321a8-2bdc-459d-b8c7-d4a8792a714c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21332
21222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2133221222
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.3862957383
Short name T2109
Test name
Test status
Simulation time 136934499 ps
CPU time 0.78 seconds
Started Jun 24 05:22:27 PM PDT 24
Finished Jun 24 05:22:30 PM PDT 24
Peak memory 206096 kb
Host smart-746bef17-b2ce-4985-b65c-4fb4d78efacd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38629
57383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.3862957383
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.1774941234
Short name T2394
Test name
Test status
Simulation time 38792379 ps
CPU time 0.69 seconds
Started Jun 24 05:22:30 PM PDT 24
Finished Jun 24 05:22:32 PM PDT 24
Peak memory 206172 kb
Host smart-3db7b292-967e-4580-bd4b-ecae0b8d1729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17749
41234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1774941234
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.3182540824
Short name T897
Test name
Test status
Simulation time 828787581 ps
CPU time 2.2 seconds
Started Jun 24 05:22:29 PM PDT 24
Finished Jun 24 05:22:32 PM PDT 24
Peak memory 206184 kb
Host smart-8fd56c11-cb34-4cce-b94f-07c7a645cbd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31825
40824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.3182540824
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1162369496
Short name T1970
Test name
Test status
Simulation time 215845899 ps
CPU time 1.49 seconds
Started Jun 24 05:22:27 PM PDT 24
Finished Jun 24 05:22:29 PM PDT 24
Peak memory 206276 kb
Host smart-dc0436fd-1322-4d05-89df-d60886e15de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11623
69496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1162369496
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1255114787
Short name T326
Test name
Test status
Simulation time 143976623 ps
CPU time 0.78 seconds
Started Jun 24 05:22:34 PM PDT 24
Finished Jun 24 05:22:36 PM PDT 24
Peak memory 206188 kb
Host smart-c803cd4d-103f-443b-9258-44b0357feeee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12551
14787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1255114787
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1774756270
Short name T527
Test name
Test status
Simulation time 199841433 ps
CPU time 0.86 seconds
Started Jun 24 05:22:40 PM PDT 24
Finished Jun 24 05:22:41 PM PDT 24
Peak memory 206192 kb
Host smart-cfafc803-afb8-4f48-b6a1-8ae7586284dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17747
56270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1774756270
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2935929813
Short name T1988
Test name
Test status
Simulation time 220605984 ps
CPU time 0.93 seconds
Started Jun 24 05:22:35 PM PDT 24
Finished Jun 24 05:22:37 PM PDT 24
Peak memory 206092 kb
Host smart-8f0f4c55-e0a0-4510-bff6-7b30163bdfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29359
29813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2935929813
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.3540643873
Short name T1023
Test name
Test status
Simulation time 23325863929 ps
CPU time 27.41 seconds
Started Jun 24 05:22:33 PM PDT 24
Finished Jun 24 05:23:02 PM PDT 24
Peak memory 206172 kb
Host smart-17b5d0c6-3594-4b98-a594-37db4f814e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35406
43873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3540643873
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3140412887
Short name T1133
Test name
Test status
Simulation time 3344115780 ps
CPU time 3.47 seconds
Started Jun 24 05:22:34 PM PDT 24
Finished Jun 24 05:22:38 PM PDT 24
Peak memory 206236 kb
Host smart-56c8998d-6f30-4895-8aaf-dcea147fc6b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31404
12887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3140412887
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.144002228
Short name T2519
Test name
Test status
Simulation time 11296519556 ps
CPU time 312 seconds
Started Jun 24 05:22:37 PM PDT 24
Finished Jun 24 05:27:51 PM PDT 24
Peak memory 206384 kb
Host smart-ff099eda-7820-4527-9c1b-6e674cb8bb17
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=144002228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.144002228
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.1128878231
Short name T1024
Test name
Test status
Simulation time 237750899 ps
CPU time 0.92 seconds
Started Jun 24 05:22:34 PM PDT 24
Finished Jun 24 05:22:36 PM PDT 24
Peak memory 206072 kb
Host smart-259a7d1f-6713-4cb1-81c1-da09029673d6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1128878231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.1128878231
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3004339461
Short name T2150
Test name
Test status
Simulation time 195608747 ps
CPU time 0.83 seconds
Started Jun 24 05:22:36 PM PDT 24
Finished Jun 24 05:22:38 PM PDT 24
Peak memory 206176 kb
Host smart-e40b8cd0-b3ce-4909-ab29-ca8b66b7f5ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30043
39461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3004339461
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.235537986
Short name T510
Test name
Test status
Simulation time 5823815788 ps
CPU time 41.08 seconds
Started Jun 24 05:22:33 PM PDT 24
Finished Jun 24 05:23:15 PM PDT 24
Peak memory 206280 kb
Host smart-a934130b-f7ba-407c-84d0-fb9f32675065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23553
7986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.235537986
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.2862249834
Short name T2371
Test name
Test status
Simulation time 13601711963 ps
CPU time 102.27 seconds
Started Jun 24 05:22:40 PM PDT 24
Finished Jun 24 05:24:23 PM PDT 24
Peak memory 206216 kb
Host smart-389041f2-eba1-468e-8850-c7c060f044ef
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2862249834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.2862249834
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2715706159
Short name T2126
Test name
Test status
Simulation time 147837871 ps
CPU time 0.81 seconds
Started Jun 24 05:22:35 PM PDT 24
Finished Jun 24 05:22:38 PM PDT 24
Peak memory 206404 kb
Host smart-c9dd4055-188f-466d-afd5-621f617b8932
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2715706159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2715706159
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.176606100
Short name T705
Test name
Test status
Simulation time 139983379 ps
CPU time 0.77 seconds
Started Jun 24 05:22:34 PM PDT 24
Finished Jun 24 05:22:36 PM PDT 24
Peak memory 206172 kb
Host smart-8c460471-d4b0-425c-a1fc-2ed78e8af8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17660
6100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.176606100
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.19520489
Short name T2205
Test name
Test status
Simulation time 204804031 ps
CPU time 0.87 seconds
Started Jun 24 05:22:39 PM PDT 24
Finished Jun 24 05:22:41 PM PDT 24
Peak memory 206120 kb
Host smart-14b231fe-c6d7-4ce3-969c-0be1d20e3fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19520
489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.19520489
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1549893685
Short name T833
Test name
Test status
Simulation time 205808561 ps
CPU time 0.94 seconds
Started Jun 24 05:22:35 PM PDT 24
Finished Jun 24 05:22:38 PM PDT 24
Peak memory 206180 kb
Host smart-3d522e83-e0c8-4d7d-9279-df509a7606dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15498
93685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1549893685
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3504857462
Short name T1357
Test name
Test status
Simulation time 169143761 ps
CPU time 0.79 seconds
Started Jun 24 05:22:48 PM PDT 24
Finished Jun 24 05:22:49 PM PDT 24
Peak memory 206188 kb
Host smart-edac6a9a-fbec-47c8-98ff-176c19f0eb95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35048
57462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3504857462
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1705290726
Short name T171
Test name
Test status
Simulation time 146978468 ps
CPU time 0.76 seconds
Started Jun 24 05:22:33 PM PDT 24
Finished Jun 24 05:22:35 PM PDT 24
Peak memory 206132 kb
Host smart-7ce8fe5b-e2c3-4f2a-a37b-ad64313365fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17052
90726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1705290726
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3055519897
Short name T2431
Test name
Test status
Simulation time 225112879 ps
CPU time 0.95 seconds
Started Jun 24 05:22:35 PM PDT 24
Finished Jun 24 05:22:38 PM PDT 24
Peak memory 206172 kb
Host smart-e798df43-0be5-410b-9cca-12d8083a8792
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3055519897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3055519897
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3377483371
Short name T2309
Test name
Test status
Simulation time 173123445 ps
CPU time 0.8 seconds
Started Jun 24 05:22:34 PM PDT 24
Finished Jun 24 05:22:36 PM PDT 24
Peak memory 206160 kb
Host smart-31336706-0029-4647-b60c-bcc2d351b8bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33774
83371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3377483371
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.511462724
Short name T379
Test name
Test status
Simulation time 47694652 ps
CPU time 0.64 seconds
Started Jun 24 05:22:32 PM PDT 24
Finished Jun 24 05:22:34 PM PDT 24
Peak memory 206188 kb
Host smart-0060c703-1e26-4c9a-ab92-69b8a3921f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51146
2724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.511462724
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3320318579
Short name T1463
Test name
Test status
Simulation time 218117397 ps
CPU time 0.86 seconds
Started Jun 24 05:22:35 PM PDT 24
Finished Jun 24 05:22:38 PM PDT 24
Peak memory 206064 kb
Host smart-15ba76b8-e37c-47e3-974e-4fcd701c8349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33203
18579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3320318579
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2433252113
Short name T1900
Test name
Test status
Simulation time 195521753 ps
CPU time 0.84 seconds
Started Jun 24 05:22:33 PM PDT 24
Finished Jun 24 05:22:35 PM PDT 24
Peak memory 206152 kb
Host smart-d2ec1f60-b5a8-42c6-a0c9-4e24a73ed3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24332
52113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2433252113
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.4099826802
Short name T439
Test name
Test status
Simulation time 245427921 ps
CPU time 0.9 seconds
Started Jun 24 05:22:33 PM PDT 24
Finished Jun 24 05:22:35 PM PDT 24
Peak memory 206160 kb
Host smart-1eb3a6cb-05bc-42e5-a7d8-d61e4770ead0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40998
26802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.4099826802
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.332394700
Short name T647
Test name
Test status
Simulation time 179197569 ps
CPU time 0.82 seconds
Started Jun 24 05:22:35 PM PDT 24
Finished Jun 24 05:22:38 PM PDT 24
Peak memory 206168 kb
Host smart-090c0f9a-bc5b-4d09-8b97-48a5c3c0e77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33239
4700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.332394700
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.2357322344
Short name T2323
Test name
Test status
Simulation time 150546648 ps
CPU time 0.82 seconds
Started Jun 24 05:22:35 PM PDT 24
Finished Jun 24 05:22:38 PM PDT 24
Peak memory 206164 kb
Host smart-8869307f-7fe8-4f38-978b-36c179e7b44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23573
22344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.2357322344
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1608078800
Short name T115
Test name
Test status
Simulation time 162348950 ps
CPU time 0.77 seconds
Started Jun 24 05:22:37 PM PDT 24
Finished Jun 24 05:22:40 PM PDT 24
Peak memory 206140 kb
Host smart-325226fd-ab70-4846-8301-823b6b13675a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16080
78800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1608078800
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1652051585
Short name T2241
Test name
Test status
Simulation time 208204702 ps
CPU time 0.82 seconds
Started Jun 24 05:22:41 PM PDT 24
Finished Jun 24 05:22:43 PM PDT 24
Peak memory 206172 kb
Host smart-db12c1d6-d3f3-44bb-a8b6-171bac03835e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16520
51585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1652051585
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.677745726
Short name T49
Test name
Test status
Simulation time 180456726 ps
CPU time 0.86 seconds
Started Jun 24 05:22:34 PM PDT 24
Finished Jun 24 05:22:36 PM PDT 24
Peak memory 206168 kb
Host smart-9aaa61f3-c0c4-4f25-b5fa-20acedb4de3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67774
5726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.677745726
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.3012295710
Short name T1059
Test name
Test status
Simulation time 8939852850 ps
CPU time 76.96 seconds
Started Jun 24 05:22:35 PM PDT 24
Finished Jun 24 05:23:54 PM PDT 24
Peak memory 206380 kb
Host smart-d72c05ba-71dc-4625-a91e-93454bedf05e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3012295710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.3012295710
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2828968577
Short name T2504
Test name
Test status
Simulation time 160644300 ps
CPU time 0.85 seconds
Started Jun 24 05:22:36 PM PDT 24
Finished Jun 24 05:22:39 PM PDT 24
Peak memory 206176 kb
Host smart-3a95babc-92af-4133-b7c0-c8a7f471136d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28289
68577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2828968577
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.487685667
Short name T2377
Test name
Test status
Simulation time 163721310 ps
CPU time 0.82 seconds
Started Jun 24 05:22:35 PM PDT 24
Finished Jun 24 05:22:38 PM PDT 24
Peak memory 206080 kb
Host smart-f50ee744-86a5-47f5-bfbd-ab8990f112fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48768
5667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.487685667
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.827498572
Short name T1367
Test name
Test status
Simulation time 8642938369 ps
CPU time 64.98 seconds
Started Jun 24 05:22:35 PM PDT 24
Finished Jun 24 05:23:42 PM PDT 24
Peak memory 206340 kb
Host smart-3ffa56ef-60c1-4bd7-b3eb-a45e2d28c3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82749
8572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.827498572
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.1967211458
Short name T1560
Test name
Test status
Simulation time 3458317024 ps
CPU time 3.85 seconds
Started Jun 24 05:22:34 PM PDT 24
Finished Jun 24 05:22:39 PM PDT 24
Peak memory 206172 kb
Host smart-6bd93017-3466-47d2-91b7-cc67acecd938
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1967211458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.1967211458
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.65711478
Short name T1997
Test name
Test status
Simulation time 13318296500 ps
CPU time 12.26 seconds
Started Jun 24 05:22:33 PM PDT 24
Finished Jun 24 05:22:46 PM PDT 24
Peak memory 206328 kb
Host smart-33d62dfe-5c45-4068-8472-f591147f15a7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=65711478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.65711478
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.3040808722
Short name T1941
Test name
Test status
Simulation time 23402885593 ps
CPU time 24.82 seconds
Started Jun 24 05:22:36 PM PDT 24
Finished Jun 24 05:23:03 PM PDT 24
Peak memory 206356 kb
Host smart-e04a748d-f82a-4923-85b5-77dc6e8b4b91
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3040808722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.3040808722
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3126183753
Short name T1039
Test name
Test status
Simulation time 156071334 ps
CPU time 0.8 seconds
Started Jun 24 05:22:40 PM PDT 24
Finished Jun 24 05:22:41 PM PDT 24
Peak memory 206056 kb
Host smart-73df2169-0ae8-471d-abe7-646c85bcd0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31261
83753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3126183753
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2216199462
Short name T852
Test name
Test status
Simulation time 1018137884 ps
CPU time 2.3 seconds
Started Jun 24 05:22:35 PM PDT 24
Finished Jun 24 05:22:39 PM PDT 24
Peak memory 206244 kb
Host smart-57a9f6a0-c93b-4429-844d-c03871e2b2a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22161
99462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2216199462
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.1923779317
Short name T923
Test name
Test status
Simulation time 16089445798 ps
CPU time 28.31 seconds
Started Jun 24 05:22:35 PM PDT 24
Finished Jun 24 05:23:06 PM PDT 24
Peak memory 206328 kb
Host smart-e6c11537-8a5b-4921-989a-808f1af4b559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19237
79317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.1923779317
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.3807429446
Short name T437
Test name
Test status
Simulation time 417631659 ps
CPU time 1.22 seconds
Started Jun 24 05:22:35 PM PDT 24
Finished Jun 24 05:22:39 PM PDT 24
Peak memory 206172 kb
Host smart-7cccf70c-ef84-4728-b73a-ba6287bf9ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38074
29446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3807429446
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.1425382374
Short name T1230
Test name
Test status
Simulation time 172586580 ps
CPU time 0.8 seconds
Started Jun 24 05:22:42 PM PDT 24
Finished Jun 24 05:22:43 PM PDT 24
Peak memory 206172 kb
Host smart-6c66ce71-dc39-4e3d-89b9-42ccf7a3a022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14253
82374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.1425382374
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.3648723198
Short name T328
Test name
Test status
Simulation time 46126436 ps
CPU time 0.74 seconds
Started Jun 24 05:22:45 PM PDT 24
Finished Jun 24 05:22:47 PM PDT 24
Peak memory 206168 kb
Host smart-5ff1d4bf-0609-4cae-b8a7-6d110cad0706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36487
23198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3648723198
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.723344996
Short name T323
Test name
Test status
Simulation time 770262375 ps
CPU time 2.15 seconds
Started Jun 24 05:22:42 PM PDT 24
Finished Jun 24 05:22:45 PM PDT 24
Peak memory 206312 kb
Host smart-d11edcbd-3444-49e3-920f-7caf463a54d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72334
4996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.723344996
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1108677932
Short name T2036
Test name
Test status
Simulation time 315582434 ps
CPU time 1.8 seconds
Started Jun 24 05:22:49 PM PDT 24
Finished Jun 24 05:22:53 PM PDT 24
Peak memory 206256 kb
Host smart-06da106a-5c36-47d7-acb5-916bb0d4f98b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11086
77932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1108677932
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.2378590119
Short name T1522
Test name
Test status
Simulation time 210848697 ps
CPU time 0.86 seconds
Started Jun 24 05:22:50 PM PDT 24
Finished Jun 24 05:22:53 PM PDT 24
Peak memory 206160 kb
Host smart-c77a67b3-35c8-4701-a845-80418289d1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23785
90119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2378590119
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.705650181
Short name T453
Test name
Test status
Simulation time 148557324 ps
CPU time 0.72 seconds
Started Jun 24 05:22:52 PM PDT 24
Finished Jun 24 05:22:54 PM PDT 24
Peak memory 206184 kb
Host smart-611a3d26-e471-4008-a522-6e2f4b78b1b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70565
0181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.705650181
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2375625364
Short name T1143
Test name
Test status
Simulation time 218781959 ps
CPU time 0.88 seconds
Started Jun 24 05:22:46 PM PDT 24
Finished Jun 24 05:22:48 PM PDT 24
Peak memory 206192 kb
Host smart-70a9c205-6405-497e-8bc1-bb63ac855423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23756
25364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2375625364
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.633301112
Short name T1624
Test name
Test status
Simulation time 15547074898 ps
CPU time 450.94 seconds
Started Jun 24 05:22:43 PM PDT 24
Finished Jun 24 05:30:16 PM PDT 24
Peak memory 206400 kb
Host smart-0097a476-3ad4-4c84-a15f-8d081ffdd52a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=633301112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.633301112
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.558585871
Short name T2486
Test name
Test status
Simulation time 229619551 ps
CPU time 0.91 seconds
Started Jun 24 05:22:41 PM PDT 24
Finished Jun 24 05:22:43 PM PDT 24
Peak memory 206108 kb
Host smart-04b35f5d-0a67-42ce-bc4f-426512c3d87e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55858
5871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.558585871
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.1861596400
Short name T1731
Test name
Test status
Simulation time 23363133773 ps
CPU time 23.64 seconds
Started Jun 24 05:22:43 PM PDT 24
Finished Jun 24 05:23:08 PM PDT 24
Peak memory 206240 kb
Host smart-e427e29c-8737-4155-97d0-5160af94f1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18615
96400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.1861596400
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1327902331
Short name T2322
Test name
Test status
Simulation time 3282431208 ps
CPU time 3.65 seconds
Started Jun 24 05:22:41 PM PDT 24
Finished Jun 24 05:22:45 PM PDT 24
Peak memory 206128 kb
Host smart-00fba4a5-c0ed-4499-b7fa-29b0be0e68ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13279
02331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1327902331
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.1143181024
Short name T1542
Test name
Test status
Simulation time 13819615502 ps
CPU time 398.17 seconds
Started Jun 24 05:22:41 PM PDT 24
Finished Jun 24 05:29:20 PM PDT 24
Peak memory 206408 kb
Host smart-a6753663-e467-4f04-831f-194448ac3aee
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1143181024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.1143181024
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2248273740
Short name T1117
Test name
Test status
Simulation time 239575022 ps
CPU time 0.94 seconds
Started Jun 24 05:22:53 PM PDT 24
Finished Jun 24 05:22:55 PM PDT 24
Peak memory 206176 kb
Host smart-f2f7dbfb-db81-4ec9-a4d2-1138bb5c512d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2248273740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2248273740
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.4160841428
Short name T1260
Test name
Test status
Simulation time 256428545 ps
CPU time 0.92 seconds
Started Jun 24 05:22:44 PM PDT 24
Finished Jun 24 05:22:46 PM PDT 24
Peak memory 206180 kb
Host smart-e78b5f7b-7f32-4a5a-aa17-59f6eb5d91b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41608
41428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.4160841428
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.1888452957
Short name T2470
Test name
Test status
Simulation time 14051767383 ps
CPU time 378.97 seconds
Started Jun 24 05:22:49 PM PDT 24
Finished Jun 24 05:29:09 PM PDT 24
Peak memory 206380 kb
Host smart-eca40295-dc48-48c9-9974-bdc8aa6c05a3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1888452957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.1888452957
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.1935018028
Short name T2440
Test name
Test status
Simulation time 149947889 ps
CPU time 0.76 seconds
Started Jun 24 05:22:42 PM PDT 24
Finished Jun 24 05:22:44 PM PDT 24
Peak memory 206120 kb
Host smart-dcb61f22-f655-41c7-a858-283f0a146141
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1935018028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.1935018028
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.378484888
Short name T1777
Test name
Test status
Simulation time 178131095 ps
CPU time 0.87 seconds
Started Jun 24 05:22:53 PM PDT 24
Finished Jun 24 05:22:55 PM PDT 24
Peak memory 206188 kb
Host smart-b4cca79c-da79-4edb-8b36-48185c4aac47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37848
4888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.378484888
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.368389582
Short name T1458
Test name
Test status
Simulation time 179690285 ps
CPU time 0.85 seconds
Started Jun 24 05:22:44 PM PDT 24
Finished Jun 24 05:22:46 PM PDT 24
Peak memory 206176 kb
Host smart-c69ee342-4761-4a1b-aecd-d0951fbc5e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36838
9582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.368389582
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.4253432734
Short name T1065
Test name
Test status
Simulation time 170412426 ps
CPU time 0.8 seconds
Started Jun 24 05:22:44 PM PDT 24
Finished Jun 24 05:22:46 PM PDT 24
Peak memory 206048 kb
Host smart-e5907ad8-cba7-4d82-a406-57642e740296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42534
32734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.4253432734
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1907635194
Short name T1564
Test name
Test status
Simulation time 182559953 ps
CPU time 0.8 seconds
Started Jun 24 05:22:40 PM PDT 24
Finished Jun 24 05:22:42 PM PDT 24
Peak memory 206192 kb
Host smart-9a6aa44a-8102-47f5-be3d-c9065e8a18ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19076
35194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1907635194
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.1099656987
Short name T1317
Test name
Test status
Simulation time 150098237 ps
CPU time 0.76 seconds
Started Jun 24 05:22:42 PM PDT 24
Finished Jun 24 05:22:43 PM PDT 24
Peak memory 206176 kb
Host smart-ebfe63c4-e542-4db9-aacf-9982b96eaf69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10996
56987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.1099656987
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.3026056840
Short name T1276
Test name
Test status
Simulation time 212671748 ps
CPU time 0.94 seconds
Started Jun 24 05:22:46 PM PDT 24
Finished Jun 24 05:22:48 PM PDT 24
Peak memory 206176 kb
Host smart-3ce582d9-efe8-444a-a5e5-5d50c673de44
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3026056840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.3026056840
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1945332685
Short name T477
Test name
Test status
Simulation time 142856958 ps
CPU time 0.76 seconds
Started Jun 24 05:22:40 PM PDT 24
Finished Jun 24 05:22:42 PM PDT 24
Peak memory 206076 kb
Host smart-06c2eeca-661d-4479-8397-3d6dcad93829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19453
32685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1945332685
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2565298030
Short name T1216
Test name
Test status
Simulation time 48955104 ps
CPU time 0.67 seconds
Started Jun 24 05:22:41 PM PDT 24
Finished Jun 24 05:22:43 PM PDT 24
Peak memory 206112 kb
Host smart-c0c1d446-ab48-44ca-9e1a-b72b37553343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25652
98030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2565298030
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3084910534
Short name T382
Test name
Test status
Simulation time 210840544 ps
CPU time 0.98 seconds
Started Jun 24 05:22:46 PM PDT 24
Finished Jun 24 05:22:48 PM PDT 24
Peak memory 206176 kb
Host smart-27304571-76d3-44dd-bc9a-fa05791ee6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30849
10534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3084910534
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1054797061
Short name T565
Test name
Test status
Simulation time 236492300 ps
CPU time 0.9 seconds
Started Jun 24 05:22:44 PM PDT 24
Finished Jun 24 05:22:46 PM PDT 24
Peak memory 206072 kb
Host smart-c6082b5f-e0ba-47a0-b29f-b692d84a382f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10547
97061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1054797061
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.2895394693
Short name T915
Test name
Test status
Simulation time 193298416 ps
CPU time 0.84 seconds
Started Jun 24 05:22:47 PM PDT 24
Finished Jun 24 05:22:48 PM PDT 24
Peak memory 206080 kb
Host smart-c145e8fd-24af-4a0a-9e4e-72d7ba830f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28953
94693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.2895394693
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.3994972261
Short name T1319
Test name
Test status
Simulation time 273098358 ps
CPU time 0.9 seconds
Started Jun 24 05:22:41 PM PDT 24
Finished Jun 24 05:22:43 PM PDT 24
Peak memory 206200 kb
Host smart-9f67609e-fd87-4560-87a3-44e0212a4d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39949
72261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.3994972261
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.4032992577
Short name T1131
Test name
Test status
Simulation time 172843840 ps
CPU time 0.8 seconds
Started Jun 24 05:22:46 PM PDT 24
Finished Jun 24 05:22:48 PM PDT 24
Peak memory 206072 kb
Host smart-2f3fbf24-8342-4a84-8819-ef1a6290847e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40329
92577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.4032992577
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1066565052
Short name T416
Test name
Test status
Simulation time 178698330 ps
CPU time 0.83 seconds
Started Jun 24 05:22:49 PM PDT 24
Finished Jun 24 05:22:51 PM PDT 24
Peak memory 206176 kb
Host smart-90e5b192-ca5f-412a-9fdb-cb9987d7a99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10665
65052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1066565052
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3872449825
Short name T1401
Test name
Test status
Simulation time 164405037 ps
CPU time 0.75 seconds
Started Jun 24 05:22:53 PM PDT 24
Finished Jun 24 05:22:55 PM PDT 24
Peak memory 206172 kb
Host smart-96a84c7d-96d9-46f4-aa97-181c848819b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38724
49825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3872449825
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2256722165
Short name T1304
Test name
Test status
Simulation time 187420362 ps
CPU time 0.88 seconds
Started Jun 24 05:22:44 PM PDT 24
Finished Jun 24 05:22:47 PM PDT 24
Peak memory 206192 kb
Host smart-4759eff1-2195-4ef5-86ec-98a1b6b6614f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22567
22165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2256722165
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.198760681
Short name T849
Test name
Test status
Simulation time 7115134074 ps
CPU time 194.32 seconds
Started Jun 24 05:22:49 PM PDT 24
Finished Jun 24 05:26:04 PM PDT 24
Peak memory 206372 kb
Host smart-737a9072-a3f0-4a3b-a0be-9f24516602f4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=198760681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.198760681
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.3591943158
Short name T2013
Test name
Test status
Simulation time 169475281 ps
CPU time 0.79 seconds
Started Jun 24 05:22:44 PM PDT 24
Finished Jun 24 05:22:46 PM PDT 24
Peak memory 206432 kb
Host smart-53fc1423-3ea7-4172-ae93-6b429db3d16c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35919
43158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.3591943158
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3010838330
Short name T639
Test name
Test status
Simulation time 184448885 ps
CPU time 0.81 seconds
Started Jun 24 05:22:51 PM PDT 24
Finished Jun 24 05:22:53 PM PDT 24
Peak memory 206172 kb
Host smart-f8e212cd-dcea-40d1-93af-b43f83140dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30108
38330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3010838330
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.3229521336
Short name T899
Test name
Test status
Simulation time 11445115899 ps
CPU time 316.78 seconds
Started Jun 24 05:22:53 PM PDT 24
Finished Jun 24 05:28:11 PM PDT 24
Peak memory 206388 kb
Host smart-75a83088-398e-4c5c-a42e-ecba760d180c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32295
21336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.3229521336
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.587875639
Short name T1076
Test name
Test status
Simulation time 4425188437 ps
CPU time 5.34 seconds
Started Jun 24 05:22:43 PM PDT 24
Finished Jun 24 05:22:49 PM PDT 24
Peak memory 206576 kb
Host smart-b5843cc3-fde6-47c9-81c5-83a86d53beae
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=587875639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.587875639
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.17056956
Short name T16
Test name
Test status
Simulation time 13356040613 ps
CPU time 12.64 seconds
Started Jun 24 05:22:43 PM PDT 24
Finished Jun 24 05:22:57 PM PDT 24
Peak memory 206164 kb
Host smart-c38b076d-ee57-4d91-b538-4f0c9cb2af3e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=17056956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.17056956
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.3654681717
Short name T2327
Test name
Test status
Simulation time 23406988312 ps
CPU time 22.64 seconds
Started Jun 24 05:22:49 PM PDT 24
Finished Jun 24 05:23:13 PM PDT 24
Peak memory 206228 kb
Host smart-096739ae-8790-45e0-bce3-03dae7c41f7f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3654681717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.3654681717
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.460609446
Short name T912
Test name
Test status
Simulation time 248242566 ps
CPU time 0.86 seconds
Started Jun 24 05:22:44 PM PDT 24
Finished Jun 24 05:22:46 PM PDT 24
Peak memory 206196 kb
Host smart-897ba3e3-7129-4477-b912-d91466997468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46060
9446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.460609446
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.3069416970
Short name T371
Test name
Test status
Simulation time 198052216 ps
CPU time 0.83 seconds
Started Jun 24 05:22:46 PM PDT 24
Finished Jun 24 05:22:48 PM PDT 24
Peak memory 206056 kb
Host smart-e1565831-8db8-4a35-922e-589080d25194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30694
16970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.3069416970
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.3131049925
Short name T2353
Test name
Test status
Simulation time 200493792 ps
CPU time 0.83 seconds
Started Jun 24 05:22:52 PM PDT 24
Finished Jun 24 05:22:54 PM PDT 24
Peak memory 206176 kb
Host smart-2ad73051-4a0d-47e2-83a8-a538b19472a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31310
49925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.3131049925
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.897763883
Short name T1868
Test name
Test status
Simulation time 1365233343 ps
CPU time 2.7 seconds
Started Jun 24 05:22:42 PM PDT 24
Finished Jun 24 05:22:46 PM PDT 24
Peak memory 206228 kb
Host smart-7fb2ed32-1607-400b-ada7-a3c4c860f1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89776
3883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.897763883
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.1297886318
Short name T1760
Test name
Test status
Simulation time 6302716980 ps
CPU time 11.99 seconds
Started Jun 24 05:22:50 PM PDT 24
Finished Jun 24 05:23:03 PM PDT 24
Peak memory 206368 kb
Host smart-215aebbb-9da4-48ea-bac2-69a566bbff80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12978
86318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.1297886318
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.2377018447
Short name T2272
Test name
Test status
Simulation time 464892705 ps
CPU time 1.41 seconds
Started Jun 24 05:22:48 PM PDT 24
Finished Jun 24 05:22:50 PM PDT 24
Peak memory 206160 kb
Host smart-1fa1f6da-fd2d-4606-8a82-deaebcee7b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23770
18447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.2377018447
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.4104688153
Short name T42
Test name
Test status
Simulation time 161533961 ps
CPU time 0.81 seconds
Started Jun 24 05:22:50 PM PDT 24
Finished Jun 24 05:22:52 PM PDT 24
Peak memory 206168 kb
Host smart-96d648f0-5e0a-4678-97db-ad47859c1049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41046
88153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.4104688153
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.3189389535
Short name T2220
Test name
Test status
Simulation time 60054104 ps
CPU time 0.69 seconds
Started Jun 24 05:22:49 PM PDT 24
Finished Jun 24 05:22:51 PM PDT 24
Peak memory 206416 kb
Host smart-9845bfac-8cf6-4110-8e16-53e30d895e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31893
89535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3189389535
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.532347367
Short name T333
Test name
Test status
Simulation time 842248458 ps
CPU time 2.01 seconds
Started Jun 24 05:22:49 PM PDT 24
Finished Jun 24 05:22:52 PM PDT 24
Peak memory 206272 kb
Host smart-5fcc1e46-08fa-43bc-8fff-42fa0d10b3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53234
7367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.532347367
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2143731156
Short name T391
Test name
Test status
Simulation time 246237737 ps
CPU time 1.78 seconds
Started Jun 24 05:22:50 PM PDT 24
Finished Jun 24 05:22:53 PM PDT 24
Peak memory 206248 kb
Host smart-1332384b-3812-41a1-aba6-4aeef235fb2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21437
31156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2143731156
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2590197107
Short name T1278
Test name
Test status
Simulation time 222288736 ps
CPU time 0.9 seconds
Started Jun 24 05:22:48 PM PDT 24
Finished Jun 24 05:22:49 PM PDT 24
Peak memory 206176 kb
Host smart-51b1890e-b325-41ab-9800-7e24d5be9824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25901
97107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2590197107
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1442081055
Short name T1479
Test name
Test status
Simulation time 144906329 ps
CPU time 0.78 seconds
Started Jun 24 05:22:54 PM PDT 24
Finished Jun 24 05:22:56 PM PDT 24
Peak memory 206188 kb
Host smart-da632038-18ce-47a9-88d8-a91c303f7e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14420
81055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1442081055
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.4218205390
Short name T2512
Test name
Test status
Simulation time 235611738 ps
CPU time 1.01 seconds
Started Jun 24 05:22:55 PM PDT 24
Finished Jun 24 05:22:57 PM PDT 24
Peak memory 206192 kb
Host smart-bc781e17-18b7-4cdb-ac57-1ee20f5c6440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42182
05390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.4218205390
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.1246369648
Short name T847
Test name
Test status
Simulation time 9414865891 ps
CPU time 276.41 seconds
Started Jun 24 05:22:49 PM PDT 24
Finished Jun 24 05:27:27 PM PDT 24
Peak memory 206608 kb
Host smart-16d35181-55e1-464b-b5ec-f938d4beb902
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1246369648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.1246369648
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.2114197988
Short name T628
Test name
Test status
Simulation time 183093017 ps
CPU time 0.82 seconds
Started Jun 24 05:22:54 PM PDT 24
Finished Jun 24 05:22:56 PM PDT 24
Peak memory 206084 kb
Host smart-67c7a777-4bc9-48a1-88ee-875fc5695b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21141
97988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.2114197988
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.854162572
Short name T968
Test name
Test status
Simulation time 23323426949 ps
CPU time 29.04 seconds
Started Jun 24 05:22:49 PM PDT 24
Finished Jun 24 05:23:20 PM PDT 24
Peak memory 206264 kb
Host smart-26edb9d8-782f-479e-bd65-f7ba8e3b00dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85416
2572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.854162572
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.971845544
Short name T1353
Test name
Test status
Simulation time 3306306998 ps
CPU time 3.59 seconds
Started Jun 24 05:22:51 PM PDT 24
Finished Jun 24 05:22:56 PM PDT 24
Peak memory 206244 kb
Host smart-fb6be0a7-f8f1-487a-be24-9a6c6ff60d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97184
5544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.971845544
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2287357566
Short name T2145
Test name
Test status
Simulation time 4883733296 ps
CPU time 47.03 seconds
Started Jun 24 05:22:48 PM PDT 24
Finished Jun 24 05:23:36 PM PDT 24
Peak memory 206368 kb
Host smart-0f6a46e0-a1f9-463f-8627-b877780b574f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2287357566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2287357566
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.4069857969
Short name T971
Test name
Test status
Simulation time 260228019 ps
CPU time 1 seconds
Started Jun 24 05:22:59 PM PDT 24
Finished Jun 24 05:23:01 PM PDT 24
Peak memory 206188 kb
Host smart-a96c81f1-332b-4f93-b43e-0e4eb28a419c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4069857969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.4069857969
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1532680871
Short name T385
Test name
Test status
Simulation time 217282723 ps
CPU time 0.88 seconds
Started Jun 24 05:22:53 PM PDT 24
Finished Jun 24 05:22:55 PM PDT 24
Peak memory 206180 kb
Host smart-e156a7e1-eebc-4eca-b2d8-fadc8dc51dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15326
80871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1532680871
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.3601906258
Short name T1612
Test name
Test status
Simulation time 7642814294 ps
CPU time 211.83 seconds
Started Jun 24 05:22:51 PM PDT 24
Finished Jun 24 05:26:25 PM PDT 24
Peak memory 206376 kb
Host smart-9b4eb247-84f7-4d56-9062-39d5507b389e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36019
06258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.3601906258
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.3159806821
Short name T2291
Test name
Test status
Simulation time 7517695741 ps
CPU time 67.78 seconds
Started Jun 24 05:22:51 PM PDT 24
Finished Jun 24 05:24:00 PM PDT 24
Peak memory 206348 kb
Host smart-b0304f28-f7de-4150-9e61-93dbe80240ce
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3159806821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.3159806821
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.3342639060
Short name T2366
Test name
Test status
Simulation time 233782491 ps
CPU time 0.85 seconds
Started Jun 24 05:22:50 PM PDT 24
Finished Jun 24 05:22:52 PM PDT 24
Peak memory 206196 kb
Host smart-2087d317-5180-4c69-a210-328cf71333d8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3342639060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3342639060
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2329448463
Short name T2192
Test name
Test status
Simulation time 147311755 ps
CPU time 0.77 seconds
Started Jun 24 05:22:54 PM PDT 24
Finished Jun 24 05:22:56 PM PDT 24
Peak memory 206176 kb
Host smart-ec7ad7da-cef4-46f9-a722-4fa96a49df8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23294
48463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2329448463
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2828893773
Short name T135
Test name
Test status
Simulation time 191077078 ps
CPU time 0.83 seconds
Started Jun 24 05:22:49 PM PDT 24
Finished Jun 24 05:22:51 PM PDT 24
Peak memory 206172 kb
Host smart-552adb9b-d224-464a-8222-f2731d1efb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28288
93773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2828893773
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.3501094302
Short name T816
Test name
Test status
Simulation time 179413462 ps
CPU time 0.83 seconds
Started Jun 24 05:22:48 PM PDT 24
Finished Jun 24 05:22:50 PM PDT 24
Peak memory 206192 kb
Host smart-4b3dafcc-3766-4558-b0a2-49f0e8b74661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35010
94302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.3501094302
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3976457358
Short name T2041
Test name
Test status
Simulation time 174817245 ps
CPU time 0.81 seconds
Started Jun 24 05:22:51 PM PDT 24
Finished Jun 24 05:22:54 PM PDT 24
Peak memory 206180 kb
Host smart-5af11444-6807-490a-b2f1-f161c8ff528e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39764
57358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3976457358
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2274558337
Short name T2076
Test name
Test status
Simulation time 188381577 ps
CPU time 0.79 seconds
Started Jun 24 05:22:52 PM PDT 24
Finished Jun 24 05:22:54 PM PDT 24
Peak memory 206192 kb
Host smart-1d41d9a9-e477-4412-a9e8-a29cbf8cf0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22745
58337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2274558337
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1459287384
Short name T1460
Test name
Test status
Simulation time 144265160 ps
CPU time 0.79 seconds
Started Jun 24 05:22:50 PM PDT 24
Finished Jun 24 05:22:53 PM PDT 24
Peak memory 206176 kb
Host smart-63064aca-ffb8-4c4a-9743-5ece760a2774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14592
87384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1459287384
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.2997347498
Short name T1585
Test name
Test status
Simulation time 244955646 ps
CPU time 0.97 seconds
Started Jun 24 05:22:49 PM PDT 24
Finished Jun 24 05:22:51 PM PDT 24
Peak memory 206108 kb
Host smart-e42a8467-aa12-48da-9644-6458a4025944
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2997347498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.2997347498
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2603064850
Short name T1232
Test name
Test status
Simulation time 194031861 ps
CPU time 0.77 seconds
Started Jun 24 05:22:53 PM PDT 24
Finished Jun 24 05:22:55 PM PDT 24
Peak memory 206076 kb
Host smart-d7720aa1-600a-4f17-b83d-c5ae64fa398e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26030
64850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2603064850
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3632447246
Short name T1520
Test name
Test status
Simulation time 50572215 ps
CPU time 0.69 seconds
Started Jun 24 05:22:48 PM PDT 24
Finished Jun 24 05:22:50 PM PDT 24
Peak memory 206148 kb
Host smart-61474926-16cf-44ea-bd85-d38ac143bcff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36324
47246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3632447246
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2003651183
Short name T1077
Test name
Test status
Simulation time 12764989316 ps
CPU time 27.71 seconds
Started Jun 24 05:22:50 PM PDT 24
Finished Jun 24 05:23:19 PM PDT 24
Peak memory 206364 kb
Host smart-ff3709d6-0f12-4507-b645-6cb791642e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20036
51183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2003651183
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1960890189
Short name T415
Test name
Test status
Simulation time 206945468 ps
CPU time 0.86 seconds
Started Jun 24 05:22:49 PM PDT 24
Finished Jun 24 05:22:52 PM PDT 24
Peak memory 206156 kb
Host smart-5cba3f44-5f29-4978-88ac-a2e564bd7e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19608
90189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1960890189
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2236854389
Short name T1431
Test name
Test status
Simulation time 269162673 ps
CPU time 0.97 seconds
Started Jun 24 05:22:54 PM PDT 24
Finished Jun 24 05:22:56 PM PDT 24
Peak memory 206192 kb
Host smart-adfefde6-d60e-4b24-bcf3-1e7634f58b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22368
54389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2236854389
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.3942485946
Short name T2049
Test name
Test status
Simulation time 167419089 ps
CPU time 0.81 seconds
Started Jun 24 05:22:54 PM PDT 24
Finished Jun 24 05:22:56 PM PDT 24
Peak memory 206200 kb
Host smart-ad040c79-088c-4352-bafe-19bd70c98ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39424
85946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3942485946
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.401015330
Short name T1441
Test name
Test status
Simulation time 165090422 ps
CPU time 0.82 seconds
Started Jun 24 05:22:52 PM PDT 24
Finished Jun 24 05:22:54 PM PDT 24
Peak memory 206168 kb
Host smart-7bce37a3-ba61-4a9b-8449-d71fc450e2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40101
5330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.401015330
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.4080121662
Short name T1832
Test name
Test status
Simulation time 152017460 ps
CPU time 0.77 seconds
Started Jun 24 05:22:50 PM PDT 24
Finished Jun 24 05:22:52 PM PDT 24
Peak memory 206092 kb
Host smart-0ed43c7b-5e0c-4275-8e56-5a3fb478437f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40801
21662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.4080121662
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.58000122
Short name T158
Test name
Test status
Simulation time 153820941 ps
CPU time 0.78 seconds
Started Jun 24 05:22:51 PM PDT 24
Finished Jun 24 05:22:53 PM PDT 24
Peak memory 206184 kb
Host smart-d8b73aa4-8324-4460-9a4f-58051caff1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58000
122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.58000122
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1056902087
Short name T476
Test name
Test status
Simulation time 151055737 ps
CPU time 0.79 seconds
Started Jun 24 05:22:56 PM PDT 24
Finished Jun 24 05:22:58 PM PDT 24
Peak memory 206168 kb
Host smart-a879a6ae-a720-4fa2-8383-a22b63b645cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10569
02087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1056902087
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3595081558
Short name T1653
Test name
Test status
Simulation time 218810108 ps
CPU time 0.94 seconds
Started Jun 24 05:22:50 PM PDT 24
Finished Jun 24 05:22:52 PM PDT 24
Peak memory 206076 kb
Host smart-cf78e605-4bc6-4130-adbe-4e5bccfef5f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35950
81558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3595081558
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.1163890249
Short name T826
Test name
Test status
Simulation time 5183330002 ps
CPU time 50.55 seconds
Started Jun 24 05:22:50 PM PDT 24
Finished Jun 24 05:23:42 PM PDT 24
Peak memory 206224 kb
Host smart-bbf34a9d-52b5-4adc-bf57-266262f4c6ee
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1163890249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.1163890249
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.2757925318
Short name T1549
Test name
Test status
Simulation time 203667939 ps
CPU time 0.82 seconds
Started Jun 24 05:22:48 PM PDT 24
Finished Jun 24 05:22:50 PM PDT 24
Peak memory 206180 kb
Host smart-1b09ad37-0259-4bb0-b080-e96523e0f93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27579
25318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2757925318
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.1513590363
Short name T1886
Test name
Test status
Simulation time 192136026 ps
CPU time 0.84 seconds
Started Jun 24 05:22:51 PM PDT 24
Finished Jun 24 05:22:53 PM PDT 24
Peak memory 206152 kb
Host smart-45fdb881-f01d-43c1-970d-3cfd34999cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15135
90363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.1513590363
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.1777225132
Short name T1486
Test name
Test status
Simulation time 6868482494 ps
CPU time 51.02 seconds
Started Jun 24 05:22:51 PM PDT 24
Finished Jun 24 05:23:44 PM PDT 24
Peak memory 206388 kb
Host smart-9c77089a-49c9-499e-b192-dca1ffb8afe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17772
25132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.1777225132
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.2801275409
Short name T2137
Test name
Test status
Simulation time 13356815695 ps
CPU time 14.58 seconds
Started Jun 24 05:22:55 PM PDT 24
Finished Jun 24 05:23:11 PM PDT 24
Peak memory 206224 kb
Host smart-cc3fa669-1b36-4794-9e40-2ded69a6fd7c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2801275409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.2801275409
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2094675588
Short name T1507
Test name
Test status
Simulation time 23404956931 ps
CPU time 22.84 seconds
Started Jun 24 05:22:59 PM PDT 24
Finished Jun 24 05:23:23 PM PDT 24
Peak memory 206244 kb
Host smart-ab7fc285-8473-41f1-bd3b-67f81f4ac598
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2094675588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.2094675588
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.547659386
Short name T1170
Test name
Test status
Simulation time 172469534 ps
CPU time 0.77 seconds
Started Jun 24 05:23:05 PM PDT 24
Finished Jun 24 05:23:08 PM PDT 24
Peak memory 206072 kb
Host smart-ea25fa2b-2c57-43e8-b07a-ee75fd7f8ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54765
9386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.547659386
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.3158171658
Short name T18
Test name
Test status
Simulation time 152047449 ps
CPU time 0.82 seconds
Started Jun 24 05:23:02 PM PDT 24
Finished Jun 24 05:23:04 PM PDT 24
Peak memory 206176 kb
Host smart-c2c7c95d-939c-4fe3-bff5-358c330719f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31581
71658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3158171658
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.4201754073
Short name T642
Test name
Test status
Simulation time 204490345 ps
CPU time 0.87 seconds
Started Jun 24 05:22:56 PM PDT 24
Finished Jun 24 05:22:58 PM PDT 24
Peak memory 206172 kb
Host smart-a03b1085-800b-4b3a-bd72-55b8d315a814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42017
54073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.4201754073
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3772352522
Short name T1193
Test name
Test status
Simulation time 1280710962 ps
CPU time 2.96 seconds
Started Jun 24 05:23:00 PM PDT 24
Finished Jun 24 05:23:04 PM PDT 24
Peak memory 206328 kb
Host smart-73254140-339e-4238-8112-ebb2d1dcfbfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37723
52522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3772352522
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.797804703
Short name T1680
Test name
Test status
Simulation time 13035405927 ps
CPU time 24.97 seconds
Started Jun 24 05:23:00 PM PDT 24
Finished Jun 24 05:23:26 PM PDT 24
Peak memory 206368 kb
Host smart-d39cf909-e9c1-4a6a-9679-8721a8e17e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79780
4703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.797804703
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3725607121
Short name T1225
Test name
Test status
Simulation time 447041992 ps
CPU time 1.37 seconds
Started Jun 24 05:23:04 PM PDT 24
Finished Jun 24 05:23:08 PM PDT 24
Peak memory 206076 kb
Host smart-c51e2595-319a-46f3-8bc2-e54579120648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37256
07121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3725607121
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.2687510967
Short name T581
Test name
Test status
Simulation time 150660522 ps
CPU time 0.81 seconds
Started Jun 24 05:22:57 PM PDT 24
Finished Jun 24 05:22:58 PM PDT 24
Peak memory 206104 kb
Host smart-1729511a-5247-480f-be68-1f0c8de94d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26875
10967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.2687510967
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1083942569
Short name T1715
Test name
Test status
Simulation time 38620439 ps
CPU time 0.68 seconds
Started Jun 24 05:23:00 PM PDT 24
Finished Jun 24 05:23:02 PM PDT 24
Peak memory 206168 kb
Host smart-c754778e-350a-4314-8ac7-44b115c392d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10839
42569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1083942569
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.3925766619
Short name T325
Test name
Test status
Simulation time 712795923 ps
CPU time 1.86 seconds
Started Jun 24 05:22:57 PM PDT 24
Finished Jun 24 05:23:00 PM PDT 24
Peak memory 206548 kb
Host smart-abaf54ca-ded1-49b1-836a-cf04e5b99bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39257
66619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.3925766619
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.394679978
Short name T1407
Test name
Test status
Simulation time 362419676 ps
CPU time 2.18 seconds
Started Jun 24 05:23:05 PM PDT 24
Finished Jun 24 05:23:10 PM PDT 24
Peak memory 206164 kb
Host smart-7a1b8ae9-2e8e-4806-a976-22472fae244b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39467
9978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.394679978
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.736411957
Short name T2415
Test name
Test status
Simulation time 201150717 ps
CPU time 0.88 seconds
Started Jun 24 05:23:05 PM PDT 24
Finished Jun 24 05:23:09 PM PDT 24
Peak memory 206096 kb
Host smart-0707518d-e69c-4863-98d0-7dc099540873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73641
1957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.736411957
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.588770461
Short name T860
Test name
Test status
Simulation time 170593423 ps
CPU time 0.79 seconds
Started Jun 24 05:23:06 PM PDT 24
Finished Jun 24 05:23:10 PM PDT 24
Peak memory 206168 kb
Host smart-d2d588e5-de6c-4f21-9cea-c1fae1656791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58877
0461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.588770461
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.3856164490
Short name T1338
Test name
Test status
Simulation time 238618786 ps
CPU time 0.96 seconds
Started Jun 24 05:22:57 PM PDT 24
Finished Jun 24 05:22:59 PM PDT 24
Peak memory 206112 kb
Host smart-d1f4fead-a2da-4b45-a14a-adb1e8f7f875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38561
64490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.3856164490
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.4081978470
Short name T2289
Test name
Test status
Simulation time 182733196 ps
CPU time 0.84 seconds
Started Jun 24 05:22:59 PM PDT 24
Finished Jun 24 05:23:01 PM PDT 24
Peak memory 205932 kb
Host smart-794f670b-6077-4edd-8750-1a807841211e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40819
78470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.4081978470
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.1634349945
Short name T861
Test name
Test status
Simulation time 23290132945 ps
CPU time 24.29 seconds
Started Jun 24 05:23:03 PM PDT 24
Finished Jun 24 05:23:29 PM PDT 24
Peak memory 206256 kb
Host smart-5a1e9ba7-e3de-4cd6-b1ca-e9308582b97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16343
49945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.1634349945
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2028271918
Short name T1380
Test name
Test status
Simulation time 3276836179 ps
CPU time 3.56 seconds
Started Jun 24 05:23:00 PM PDT 24
Finished Jun 24 05:23:04 PM PDT 24
Peak memory 206192 kb
Host smart-c05fc00e-fe0b-4521-a504-ab2ca9705012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20282
71918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2028271918
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.2097833549
Short name T506
Test name
Test status
Simulation time 5072920727 ps
CPU time 147.22 seconds
Started Jun 24 05:23:06 PM PDT 24
Finished Jun 24 05:25:36 PM PDT 24
Peak memory 206396 kb
Host smart-ddca0046-eea8-4e55-bec8-dfd86283094e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2097833549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.2097833549
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.2270780097
Short name T362
Test name
Test status
Simulation time 232373685 ps
CPU time 0.89 seconds
Started Jun 24 05:23:04 PM PDT 24
Finished Jun 24 05:23:07 PM PDT 24
Peak memory 206104 kb
Host smart-14e54b95-bfad-46ec-b045-c772d5b5501f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2270780097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.2270780097
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.55868022
Short name T989
Test name
Test status
Simulation time 188411339 ps
CPU time 0.86 seconds
Started Jun 24 05:22:56 PM PDT 24
Finished Jun 24 05:22:58 PM PDT 24
Peak memory 206116 kb
Host smart-f9344488-9989-4fbc-bde4-961ad7ec5449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55868
022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.55868022
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.1630189085
Short name T603
Test name
Test status
Simulation time 8284461312 ps
CPU time 244.79 seconds
Started Jun 24 05:23:02 PM PDT 24
Finished Jun 24 05:27:08 PM PDT 24
Peak memory 206376 kb
Host smart-20760e55-14f7-47df-9f06-dabe9106a4d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16301
89085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.1630189085
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1807010209
Short name T1425
Test name
Test status
Simulation time 14606640299 ps
CPU time 147.52 seconds
Started Jun 24 05:23:05 PM PDT 24
Finished Jun 24 05:25:35 PM PDT 24
Peak memory 206256 kb
Host smart-014424d8-19fa-46d8-bbe0-3ec6c2943796
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1807010209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1807010209
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.781285278
Short name T793
Test name
Test status
Simulation time 175376986 ps
CPU time 0.85 seconds
Started Jun 24 05:23:05 PM PDT 24
Finished Jun 24 05:23:09 PM PDT 24
Peak memory 206128 kb
Host smart-f7136c3e-be81-4e7f-9de6-4ad93a2c5918
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=781285278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.781285278
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1037398674
Short name T1396
Test name
Test status
Simulation time 176464492 ps
CPU time 0.84 seconds
Started Jun 24 05:23:02 PM PDT 24
Finished Jun 24 05:23:04 PM PDT 24
Peak memory 206176 kb
Host smart-6118bc73-e685-49ce-b1f1-113798c1b415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10373
98674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1037398674
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2565846680
Short name T128
Test name
Test status
Simulation time 184195203 ps
CPU time 0.79 seconds
Started Jun 24 05:23:04 PM PDT 24
Finished Jun 24 05:23:07 PM PDT 24
Peak memory 206076 kb
Host smart-fe2417bc-036b-4636-9f74-540e09d5f15e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25658
46680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2565846680
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.878462292
Short name T751
Test name
Test status
Simulation time 243621464 ps
CPU time 0.88 seconds
Started Jun 24 05:23:05 PM PDT 24
Finished Jun 24 05:23:09 PM PDT 24
Peak memory 206144 kb
Host smart-ed644412-651f-46be-a480-2568f283c5db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87846
2292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.878462292
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3455320136
Short name T473
Test name
Test status
Simulation time 250802467 ps
CPU time 0.91 seconds
Started Jun 24 05:23:03 PM PDT 24
Finished Jun 24 05:23:05 PM PDT 24
Peak memory 206416 kb
Host smart-fc51f8d3-4cb6-4456-a010-961941a4702d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34553
20136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3455320136
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2281419549
Short name T104
Test name
Test status
Simulation time 154335522 ps
CPU time 0.76 seconds
Started Jun 24 05:22:55 PM PDT 24
Finished Jun 24 05:22:57 PM PDT 24
Peak memory 206116 kb
Host smart-a6b82215-8989-4824-92ac-777ce95cbf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22814
19549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2281419549
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.149302850
Short name T2206
Test name
Test status
Simulation time 186631790 ps
CPU time 0.85 seconds
Started Jun 24 05:23:04 PM PDT 24
Finished Jun 24 05:23:07 PM PDT 24
Peak memory 206180 kb
Host smart-3bf9ce9c-6a43-4a75-b061-e4ef12ebc458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14930
2850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.149302850
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.1793912426
Short name T1184
Test name
Test status
Simulation time 190657419 ps
CPU time 0.88 seconds
Started Jun 24 05:22:56 PM PDT 24
Finished Jun 24 05:22:58 PM PDT 24
Peak memory 206164 kb
Host smart-944fea5d-347b-4365-bb03-e895c361bacf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1793912426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.1793912426
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2368482788
Short name T2030
Test name
Test status
Simulation time 139659288 ps
CPU time 0.79 seconds
Started Jun 24 05:23:05 PM PDT 24
Finished Jun 24 05:23:09 PM PDT 24
Peak memory 206072 kb
Host smart-4a7a7a9e-1fe5-4c88-889e-ffcf678a398a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23684
82788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2368482788
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1143783438
Short name T1750
Test name
Test status
Simulation time 45280394 ps
CPU time 0.67 seconds
Started Jun 24 05:23:05 PM PDT 24
Finished Jun 24 05:23:09 PM PDT 24
Peak memory 206184 kb
Host smart-9e3033b3-426e-44d1-8550-7105a716ddc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11437
83438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1143783438
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.570641780
Short name T2290
Test name
Test status
Simulation time 20238221704 ps
CPU time 44.18 seconds
Started Jun 24 05:23:00 PM PDT 24
Finished Jun 24 05:23:45 PM PDT 24
Peak memory 206368 kb
Host smart-bf45d9a4-4925-414f-9ef0-22995fd15c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57064
1780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.570641780
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.1293426588
Short name T697
Test name
Test status
Simulation time 160023355 ps
CPU time 0.81 seconds
Started Jun 24 05:22:59 PM PDT 24
Finished Jun 24 05:23:01 PM PDT 24
Peak memory 205916 kb
Host smart-08ae0e03-0d13-49f9-8957-8f3132215d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12934
26588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1293426588
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.736553863
Short name T2172
Test name
Test status
Simulation time 172785304 ps
CPU time 0.82 seconds
Started Jun 24 05:22:58 PM PDT 24
Finished Jun 24 05:22:59 PM PDT 24
Peak memory 206140 kb
Host smart-24b06f28-e54a-44c1-a85b-93719d25068d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73655
3863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.736553863
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.2344718372
Short name T431
Test name
Test status
Simulation time 204656372 ps
CPU time 0.86 seconds
Started Jun 24 05:23:05 PM PDT 24
Finished Jun 24 05:23:08 PM PDT 24
Peak memory 206100 kb
Host smart-906141c7-47a5-4446-aec6-4bd99426b44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23447
18372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.2344718372
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.3491209420
Short name T721
Test name
Test status
Simulation time 157582293 ps
CPU time 0.87 seconds
Started Jun 24 05:23:00 PM PDT 24
Finished Jun 24 05:23:02 PM PDT 24
Peak memory 206144 kb
Host smart-b74e1e68-2c14-4891-9094-3dc199700bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34912
09420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.3491209420
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.1785814024
Short name T815
Test name
Test status
Simulation time 220397206 ps
CPU time 0.88 seconds
Started Jun 24 05:22:55 PM PDT 24
Finished Jun 24 05:22:57 PM PDT 24
Peak memory 206172 kb
Host smart-2c2fe069-bf0e-448a-afa0-483fa03c36a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17858
14024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.1785814024
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3343284150
Short name T2500
Test name
Test status
Simulation time 196721707 ps
CPU time 0.79 seconds
Started Jun 24 05:23:05 PM PDT 24
Finished Jun 24 05:23:08 PM PDT 24
Peak memory 206080 kb
Host smart-fa15bb0e-8512-4904-b8df-4834ec2ced01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33432
84150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3343284150
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2430197
Short name T2383
Test name
Test status
Simulation time 151243418 ps
CPU time 0.77 seconds
Started Jun 24 05:23:08 PM PDT 24
Finished Jun 24 05:23:11 PM PDT 24
Peak memory 206172 kb
Host smart-5137e1c2-22d5-417a-8288-5f8a6bee6924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24301
97 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2430197
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1084523305
Short name T435
Test name
Test status
Simulation time 249675276 ps
CPU time 0.89 seconds
Started Jun 24 05:23:05 PM PDT 24
Finished Jun 24 05:23:08 PM PDT 24
Peak memory 206088 kb
Host smart-8029e9c7-d08b-45aa-8bda-fcc110303e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10845
23305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1084523305
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.1166421606
Short name T1556
Test name
Test status
Simulation time 7058298009 ps
CPU time 68.91 seconds
Started Jun 24 05:23:03 PM PDT 24
Finished Jun 24 05:24:14 PM PDT 24
Peak memory 206620 kb
Host smart-c847f918-f395-49e7-a4eb-447067b14355
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1166421606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.1166421606
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2701014546
Short name T2257
Test name
Test status
Simulation time 195120537 ps
CPU time 0.83 seconds
Started Jun 24 05:23:04 PM PDT 24
Finished Jun 24 05:23:07 PM PDT 24
Peak memory 206104 kb
Host smart-b86226fe-fa43-47f5-b43f-f6a05be334fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27010
14546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2701014546
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1537119636
Short name T2158
Test name
Test status
Simulation time 187220074 ps
CPU time 0.82 seconds
Started Jun 24 05:23:03 PM PDT 24
Finished Jun 24 05:23:05 PM PDT 24
Peak memory 206188 kb
Host smart-00be4994-ac6b-4090-9e9e-79914d3c72b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15371
19636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1537119636
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2967065206
Short name T2384
Test name
Test status
Simulation time 11798122273 ps
CPU time 83.74 seconds
Started Jun 24 05:23:04 PM PDT 24
Finished Jun 24 05:24:30 PM PDT 24
Peak memory 206384 kb
Host smart-89eaa304-5d5b-44f0-aa90-0e7f3b04ce7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29670
65206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2967065206
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.3003735090
Short name T1060
Test name
Test status
Simulation time 4451068030 ps
CPU time 5.21 seconds
Started Jun 24 05:23:07 PM PDT 24
Finished Jun 24 05:23:15 PM PDT 24
Peak memory 206352 kb
Host smart-0314f2c7-0839-4283-81eb-b315a9092e98
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3003735090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.3003735090
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.1661911476
Short name T576
Test name
Test status
Simulation time 13498150537 ps
CPU time 12.86 seconds
Started Jun 24 05:23:07 PM PDT 24
Finished Jun 24 05:23:23 PM PDT 24
Peak memory 206376 kb
Host smart-398fe2e2-a2ab-40f7-90d8-f77f83ffde1f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1661911476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.1661911476
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.3601692753
Short name T2071
Test name
Test status
Simulation time 23354551216 ps
CPU time 24.47 seconds
Started Jun 24 05:23:03 PM PDT 24
Finished Jun 24 05:23:30 PM PDT 24
Peak memory 206220 kb
Host smart-5d54d39c-2219-4712-a859-844c21f4a53f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3601692753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.3601692753
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.547184428
Short name T2037
Test name
Test status
Simulation time 253608894 ps
CPU time 0.93 seconds
Started Jun 24 05:23:04 PM PDT 24
Finished Jun 24 05:23:07 PM PDT 24
Peak memory 206060 kb
Host smart-46d91a01-80fc-4f99-b9a2-764b05cb24b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54718
4428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.547184428
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1308254171
Short name T440
Test name
Test status
Simulation time 145243729 ps
CPU time 0.79 seconds
Started Jun 24 05:23:05 PM PDT 24
Finished Jun 24 05:23:09 PM PDT 24
Peak memory 206176 kb
Host smart-8728d6cb-c03c-4b7e-9f8a-9297365eb638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13082
54171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1308254171
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.2577271167
Short name T1105
Test name
Test status
Simulation time 205706587 ps
CPU time 0.95 seconds
Started Jun 24 05:23:06 PM PDT 24
Finished Jun 24 05:23:10 PM PDT 24
Peak memory 206164 kb
Host smart-0c99577b-9612-4ea3-8edd-b613b57516a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25772
71167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2577271167
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.3131231035
Short name T2488
Test name
Test status
Simulation time 461514627 ps
CPU time 1.27 seconds
Started Jun 24 05:23:04 PM PDT 24
Finished Jun 24 05:23:07 PM PDT 24
Peak memory 206156 kb
Host smart-703600d1-6da5-431b-97e6-0fc030fc7f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31312
31035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.3131231035
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.2623829472
Short name T1433
Test name
Test status
Simulation time 14529258926 ps
CPU time 27.77 seconds
Started Jun 24 05:23:13 PM PDT 24
Finished Jun 24 05:23:42 PM PDT 24
Peak memory 206316 kb
Host smart-45f9a67e-c112-4b99-885b-f2426cbf5076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26238
29472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.2623829472
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.4074969908
Short name T865
Test name
Test status
Simulation time 514275997 ps
CPU time 1.52 seconds
Started Jun 24 05:23:05 PM PDT 24
Finished Jun 24 05:23:09 PM PDT 24
Peak memory 206140 kb
Host smart-2c81357a-6423-49a3-b8c4-1b6c65b736cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40749
69908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.4074969908
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.234202344
Short name T1200
Test name
Test status
Simulation time 181823695 ps
CPU time 0.77 seconds
Started Jun 24 05:23:07 PM PDT 24
Finished Jun 24 05:23:11 PM PDT 24
Peak memory 206176 kb
Host smart-4cbc3741-d73a-4e80-b063-3e9571c9eaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23420
2344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.234202344
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.1043342687
Short name T2000
Test name
Test status
Simulation time 39620996 ps
CPU time 0.67 seconds
Started Jun 24 05:23:07 PM PDT 24
Finished Jun 24 05:23:11 PM PDT 24
Peak memory 206160 kb
Host smart-a6588dbc-39dc-44e9-94aa-4312a546a1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10433
42687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1043342687
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.2766009264
Short name T1814
Test name
Test status
Simulation time 985776002 ps
CPU time 2.36 seconds
Started Jun 24 05:23:07 PM PDT 24
Finished Jun 24 05:23:12 PM PDT 24
Peak memory 206292 kb
Host smart-f7c09e04-404e-45a8-b295-96ca7777ced0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27660
09264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.2766009264
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1392747143
Short name T1146
Test name
Test status
Simulation time 385511023 ps
CPU time 2.3 seconds
Started Jun 24 05:23:13 PM PDT 24
Finished Jun 24 05:23:17 PM PDT 24
Peak memory 206172 kb
Host smart-cac3f597-e1ae-4e78-8a87-a1134474c626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13927
47143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1392747143
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.3326844202
Short name T118
Test name
Test status
Simulation time 168384682 ps
CPU time 0.81 seconds
Started Jun 24 05:23:15 PM PDT 24
Finished Jun 24 05:23:17 PM PDT 24
Peak memory 206160 kb
Host smart-c3cc737a-44cd-4685-b82a-2f9b9a829357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33268
44202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.3326844202
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3829310
Short name T2390
Test name
Test status
Simulation time 159788444 ps
CPU time 0.78 seconds
Started Jun 24 05:23:16 PM PDT 24
Finished Jun 24 05:23:19 PM PDT 24
Peak memory 206344 kb
Host smart-8ea73559-a979-49ed-92ee-8e37bdee2a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38293
10 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3829310
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.363969733
Short name T320
Test name
Test status
Simulation time 200836909 ps
CPU time 0.86 seconds
Started Jun 24 05:23:14 PM PDT 24
Finished Jun 24 05:23:17 PM PDT 24
Peak memory 206188 kb
Host smart-4d38526d-35c9-434d-a365-d166eadd4e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36396
9733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.363969733
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2618042689
Short name T376
Test name
Test status
Simulation time 229690352 ps
CPU time 0.94 seconds
Started Jun 24 05:23:13 PM PDT 24
Finished Jun 24 05:23:15 PM PDT 24
Peak memory 206116 kb
Host smart-9138e8ca-9e9b-4970-beb5-5358e5a55c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26180
42689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2618042689
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.3758463787
Short name T1864
Test name
Test status
Simulation time 23322762365 ps
CPU time 25.52 seconds
Started Jun 24 05:23:16 PM PDT 24
Finished Jun 24 05:23:44 PM PDT 24
Peak memory 206256 kb
Host smart-b4bf89b6-f758-405a-8439-c3f18d9298b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37584
63787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.3758463787
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2007909152
Short name T1596
Test name
Test status
Simulation time 3292883399 ps
CPU time 4.05 seconds
Started Jun 24 05:23:15 PM PDT 24
Finished Jun 24 05:23:21 PM PDT 24
Peak memory 206216 kb
Host smart-2fc1d0d4-ef37-44aa-90d0-d92d3f1b4366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20079
09152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2007909152
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.2527392710
Short name T2210
Test name
Test status
Simulation time 5507447838 ps
CPU time 51.66 seconds
Started Jun 24 05:23:17 PM PDT 24
Finished Jun 24 05:24:11 PM PDT 24
Peak memory 206248 kb
Host smart-6eccb4f8-a11c-40aa-a21e-610ec1e106c9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2527392710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.2527392710
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.3980949128
Short name T1041
Test name
Test status
Simulation time 255132957 ps
CPU time 0.86 seconds
Started Jun 24 05:23:13 PM PDT 24
Finished Jun 24 05:23:16 PM PDT 24
Peak memory 206148 kb
Host smart-9be113cb-e362-4c54-8eb2-a0bd6c550d43
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3980949128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.3980949128
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1369767895
Short name T1158
Test name
Test status
Simulation time 190528567 ps
CPU time 0.9 seconds
Started Jun 24 05:23:15 PM PDT 24
Finished Jun 24 05:23:17 PM PDT 24
Peak memory 206152 kb
Host smart-6e048179-7e07-4085-9aa2-8085d49a5290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13697
67895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1369767895
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.2712954136
Short name T799
Test name
Test status
Simulation time 4275431749 ps
CPU time 118.98 seconds
Started Jun 24 05:23:15 PM PDT 24
Finished Jun 24 05:25:17 PM PDT 24
Peak memory 206376 kb
Host smart-355f07ee-6485-4fac-b033-330f03855cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27129
54136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.2712954136
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.1304909624
Short name T2113
Test name
Test status
Simulation time 6061648452 ps
CPU time 44.68 seconds
Started Jun 24 05:23:15 PM PDT 24
Finished Jun 24 05:24:01 PM PDT 24
Peak memory 206312 kb
Host smart-17bf12c2-cab8-4e3c-bec5-4f91b805e63d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1304909624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.1304909624
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.2170579926
Short name T606
Test name
Test status
Simulation time 174282108 ps
CPU time 0.81 seconds
Started Jun 24 05:23:14 PM PDT 24
Finished Jun 24 05:23:17 PM PDT 24
Peak memory 206168 kb
Host smart-e0211d82-8824-469a-b6ab-90b2a151acf1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2170579926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.2170579926
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1950057722
Short name T1153
Test name
Test status
Simulation time 166064553 ps
CPU time 0.8 seconds
Started Jun 24 05:23:15 PM PDT 24
Finished Jun 24 05:23:18 PM PDT 24
Peak memory 206060 kb
Host smart-ce56bc9a-bc4d-4726-a72b-afd2c0fbbc0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19500
57722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1950057722
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1748339315
Short name T129
Test name
Test status
Simulation time 235052726 ps
CPU time 0.95 seconds
Started Jun 24 05:23:14 PM PDT 24
Finished Jun 24 05:23:17 PM PDT 24
Peak memory 206060 kb
Host smart-fe30ca61-cf41-4bfd-814d-ee21024d9b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17483
39315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1748339315
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.2876846126
Short name T1581
Test name
Test status
Simulation time 153902370 ps
CPU time 0.8 seconds
Started Jun 24 05:23:13 PM PDT 24
Finished Jun 24 05:23:15 PM PDT 24
Peak memory 206172 kb
Host smart-7c2e30d1-a683-447f-bd9d-27e11dbb5467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28768
46126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2876846126
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3486513153
Short name T1640
Test name
Test status
Simulation time 206342640 ps
CPU time 0.82 seconds
Started Jun 24 05:23:20 PM PDT 24
Finished Jun 24 05:23:22 PM PDT 24
Peak memory 206172 kb
Host smart-968b026e-6d9e-4118-9b88-907b618ae4e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34865
13153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3486513153
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.4225808833
Short name T926
Test name
Test status
Simulation time 167893146 ps
CPU time 0.82 seconds
Started Jun 24 05:23:20 PM PDT 24
Finished Jun 24 05:23:22 PM PDT 24
Peak memory 206164 kb
Host smart-b1ca2492-3466-4833-8698-cb16ac7914fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42258
08833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.4225808833
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1353359591
Short name T1773
Test name
Test status
Simulation time 153828059 ps
CPU time 0.79 seconds
Started Jun 24 05:23:14 PM PDT 24
Finished Jun 24 05:23:17 PM PDT 24
Peak memory 206148 kb
Host smart-95e57a82-4b16-4fc3-afab-d1cb4f1403fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13533
59591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1353359591
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.2614165690
Short name T1818
Test name
Test status
Simulation time 228730818 ps
CPU time 0.93 seconds
Started Jun 24 05:23:16 PM PDT 24
Finished Jun 24 05:23:19 PM PDT 24
Peak memory 206104 kb
Host smart-d31375dc-dc73-43b3-a3b2-3ddee2035db3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2614165690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.2614165690
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1120184491
Short name T2499
Test name
Test status
Simulation time 148950405 ps
CPU time 0.73 seconds
Started Jun 24 05:23:19 PM PDT 24
Finished Jun 24 05:23:20 PM PDT 24
Peak memory 206168 kb
Host smart-6a49621b-89d6-4b2d-b132-a4c80b2fac8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11201
84491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1120184491
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2851232645
Short name T1705
Test name
Test status
Simulation time 56462408 ps
CPU time 0.64 seconds
Started Jun 24 05:23:13 PM PDT 24
Finished Jun 24 05:23:15 PM PDT 24
Peak memory 206100 kb
Host smart-c6d3f1fb-4ee3-459a-aba1-8a70c4a34524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28512
32645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2851232645
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2428379176
Short name T1982
Test name
Test status
Simulation time 9889557136 ps
CPU time 20.86 seconds
Started Jun 24 05:23:20 PM PDT 24
Finished Jun 24 05:23:41 PM PDT 24
Peak memory 206392 kb
Host smart-03774ff2-da0b-4154-9207-d8f00102c13c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24283
79176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2428379176
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.887700651
Short name T1071
Test name
Test status
Simulation time 196017866 ps
CPU time 0.9 seconds
Started Jun 24 05:23:15 PM PDT 24
Finished Jun 24 05:23:17 PM PDT 24
Peak memory 206104 kb
Host smart-30bc30f4-c9c4-497f-9ccf-48c020dd27c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88770
0651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.887700651
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2394072079
Short name T2151
Test name
Test status
Simulation time 231197162 ps
CPU time 0.89 seconds
Started Jun 24 05:23:14 PM PDT 24
Finished Jun 24 05:23:16 PM PDT 24
Peak memory 206192 kb
Host smart-b20138b1-c45e-4768-b89d-93d2ca3901f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23940
72079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2394072079
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1863848874
Short name T1360
Test name
Test status
Simulation time 182931510 ps
CPU time 0.79 seconds
Started Jun 24 05:23:13 PM PDT 24
Finished Jun 24 05:23:15 PM PDT 24
Peak memory 206204 kb
Host smart-8282d38b-c9be-4f46-90a0-2cb5d5becc91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18638
48874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1863848874
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.615228708
Short name T1817
Test name
Test status
Simulation time 144651382 ps
CPU time 0.77 seconds
Started Jun 24 05:23:15 PM PDT 24
Finished Jun 24 05:23:18 PM PDT 24
Peak memory 206176 kb
Host smart-358e1f50-512c-449e-948b-25102b7672b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61522
8708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.615228708
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.3396660700
Short name T866
Test name
Test status
Simulation time 134698790 ps
CPU time 0.77 seconds
Started Jun 24 05:23:15 PM PDT 24
Finished Jun 24 05:23:18 PM PDT 24
Peak memory 206072 kb
Host smart-cf971cc2-d547-48b2-8a0f-084e3ef8fa59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33966
60700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.3396660700
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1733980833
Short name T2007
Test name
Test status
Simulation time 166891920 ps
CPU time 0.78 seconds
Started Jun 24 05:23:14 PM PDT 24
Finished Jun 24 05:23:16 PM PDT 24
Peak memory 206168 kb
Host smart-15f00aad-dd8c-45e1-82bf-9182b61f3aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17339
80833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1733980833
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.782026893
Short name T1966
Test name
Test status
Simulation time 167200572 ps
CPU time 0.78 seconds
Started Jun 24 05:23:16 PM PDT 24
Finished Jun 24 05:23:20 PM PDT 24
Peak memory 206172 kb
Host smart-3f38f7a0-0aa2-41aa-8c7a-a19858ac63ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78202
6893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.782026893
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.887275167
Short name T1606
Test name
Test status
Simulation time 220741139 ps
CPU time 0.95 seconds
Started Jun 24 05:23:16 PM PDT 24
Finished Jun 24 05:23:19 PM PDT 24
Peak memory 206348 kb
Host smart-9d5940cf-67cc-4328-a60f-d7cd0f631ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88727
5167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.887275167
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2035982832
Short name T584
Test name
Test status
Simulation time 11312982476 ps
CPU time 82.82 seconds
Started Jun 24 05:23:17 PM PDT 24
Finished Jun 24 05:24:42 PM PDT 24
Peak memory 206300 kb
Host smart-e2e7d2b9-72f8-4e59-8c6d-06b69841c84e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2035982832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2035982832
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1208583576
Short name T1540
Test name
Test status
Simulation time 153577672 ps
CPU time 0.82 seconds
Started Jun 24 05:23:12 PM PDT 24
Finished Jun 24 05:23:14 PM PDT 24
Peak memory 206180 kb
Host smart-96482b98-fe5c-41c4-bbe6-cd60d2b06014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12085
83576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1208583576
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.3535567098
Short name T1631
Test name
Test status
Simulation time 220455216 ps
CPU time 0.83 seconds
Started Jun 24 05:23:19 PM PDT 24
Finished Jun 24 05:23:21 PM PDT 24
Peak memory 206180 kb
Host smart-b22549f2-7c9c-4f9d-ba8c-cbe0107ae207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35355
67098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.3535567098
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.3947467306
Short name T1250
Test name
Test status
Simulation time 9043481519 ps
CPU time 67.24 seconds
Started Jun 24 05:23:16 PM PDT 24
Finished Jun 24 05:24:26 PM PDT 24
Peak memory 206416 kb
Host smart-67a3cea3-ec18-4b87-bf1d-0cc612636c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39474
67306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.3947467306
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.1803424448
Short name T762
Test name
Test status
Simulation time 3539715143 ps
CPU time 4.11 seconds
Started Jun 24 05:23:15 PM PDT 24
Finished Jun 24 05:23:22 PM PDT 24
Peak memory 206236 kb
Host smart-d1f95b54-f76b-42ab-92b5-5d91fbc627a5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1803424448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.1803424448
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.280803922
Short name T1634
Test name
Test status
Simulation time 13330357039 ps
CPU time 11.71 seconds
Started Jun 24 05:23:12 PM PDT 24
Finished Jun 24 05:23:24 PM PDT 24
Peak memory 206276 kb
Host smart-07fff3de-33ae-42cc-8628-4b902a678bc8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=280803922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.280803922
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.4248440228
Short name T1199
Test name
Test status
Simulation time 23385426060 ps
CPU time 22.04 seconds
Started Jun 24 05:23:14 PM PDT 24
Finished Jun 24 05:23:38 PM PDT 24
Peak memory 206376 kb
Host smart-6f852e00-c489-4b43-a2ed-533f5c75319c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4248440228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.4248440228
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2999338790
Short name T557
Test name
Test status
Simulation time 154005442 ps
CPU time 0.88 seconds
Started Jun 24 05:23:14 PM PDT 24
Finished Jun 24 05:23:17 PM PDT 24
Peak memory 206096 kb
Host smart-c0e93320-22b5-4bd0-aa0f-1ce0b262b1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29993
38790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2999338790
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.3449605910
Short name T995
Test name
Test status
Simulation time 148181211 ps
CPU time 0.82 seconds
Started Jun 24 05:23:13 PM PDT 24
Finished Jun 24 05:23:15 PM PDT 24
Peak memory 206172 kb
Host smart-4e03a386-068e-4ea1-8abd-65e36a766de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34496
05910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.3449605910
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.1694942152
Short name T2250
Test name
Test status
Simulation time 378728663 ps
CPU time 1.23 seconds
Started Jun 24 05:23:14 PM PDT 24
Finished Jun 24 05:23:17 PM PDT 24
Peak memory 206172 kb
Host smart-1b43b447-bca4-426c-a6db-f816445889c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16949
42152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.1694942152
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.834724521
Short name T652
Test name
Test status
Simulation time 343906447 ps
CPU time 1.04 seconds
Started Jun 24 05:23:14 PM PDT 24
Finished Jun 24 05:23:17 PM PDT 24
Peak memory 206148 kb
Host smart-473bf27b-dc83-46a5-9d52-3b7f5e25f29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83472
4521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.834724521
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.726669500
Short name T189
Test name
Test status
Simulation time 6613631706 ps
CPU time 12.05 seconds
Started Jun 24 05:23:14 PM PDT 24
Finished Jun 24 05:23:28 PM PDT 24
Peak memory 206340 kb
Host smart-6c58292d-c714-4081-ac01-02f3e2320aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72666
9500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.726669500
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.3087015394
Short name T530
Test name
Test status
Simulation time 326880062 ps
CPU time 1.12 seconds
Started Jun 24 05:23:15 PM PDT 24
Finished Jun 24 05:23:18 PM PDT 24
Peak memory 206060 kb
Host smart-ebe048fd-3d9b-4f18-bf6e-8069b6c3153d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30870
15394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.3087015394
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3615448528
Short name T1205
Test name
Test status
Simulation time 138673252 ps
CPU time 0.71 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:34 PM PDT 24
Peak memory 206148 kb
Host smart-fbdc3937-43c0-4807-96b2-b475448461ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36154
48528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3615448528
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.2346483188
Short name T893
Test name
Test status
Simulation time 43047380 ps
CPU time 0.7 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:33 PM PDT 24
Peak memory 206168 kb
Host smart-be7c585d-b9ce-400d-8a4e-e54cfd47e20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23464
83188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2346483188
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.1966695820
Short name T610
Test name
Test status
Simulation time 842406343 ps
CPU time 2.07 seconds
Started Jun 24 05:23:23 PM PDT 24
Finished Jun 24 05:23:27 PM PDT 24
Peak memory 206272 kb
Host smart-dd451684-d85e-4d30-b3b9-55e4891feb87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19666
95820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.1966695820
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.431781253
Short name T196
Test name
Test status
Simulation time 172287493 ps
CPU time 1.89 seconds
Started Jun 24 05:23:22 PM PDT 24
Finished Jun 24 05:23:26 PM PDT 24
Peak memory 206284 kb
Host smart-420a856e-91fa-4a8f-bb0e-ca05a2318de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43178
1253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.431781253
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.910752841
Short name T913
Test name
Test status
Simulation time 234310448 ps
CPU time 0.92 seconds
Started Jun 24 05:23:22 PM PDT 24
Finished Jun 24 05:23:23 PM PDT 24
Peak memory 206072 kb
Host smart-94c3defe-21fa-46ae-a747-e01534e18086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91075
2841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.910752841
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1556869793
Short name T2276
Test name
Test status
Simulation time 209578597 ps
CPU time 0.88 seconds
Started Jun 24 05:23:22 PM PDT 24
Finished Jun 24 05:23:24 PM PDT 24
Peak memory 206188 kb
Host smart-38f1e16f-6242-4c6e-b0c6-da5916de1a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15568
69793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1556869793
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3291603818
Short name T2332
Test name
Test status
Simulation time 230587238 ps
CPU time 0.9 seconds
Started Jun 24 05:23:32 PM PDT 24
Finished Jun 24 05:23:36 PM PDT 24
Peak memory 206168 kb
Host smart-89d2a642-42a1-4c98-8308-6e933bc84951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32916
03818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3291603818
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2034193902
Short name T2117
Test name
Test status
Simulation time 244064843 ps
CPU time 0.88 seconds
Started Jun 24 05:23:23 PM PDT 24
Finished Jun 24 05:23:26 PM PDT 24
Peak memory 206180 kb
Host smart-e184e0f4-8d5f-4acf-bd0a-d7da74c98e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20341
93902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2034193902
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1882996836
Short name T38
Test name
Test status
Simulation time 23305621599 ps
CPU time 20.66 seconds
Started Jun 24 05:23:22 PM PDT 24
Finished Jun 24 05:23:45 PM PDT 24
Peak memory 206412 kb
Host smart-2dc33cbb-e5fc-4e86-9b08-50cf5f85fc8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18829
96836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1882996836
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.2317304472
Short name T2106
Test name
Test status
Simulation time 3318660135 ps
CPU time 3.9 seconds
Started Jun 24 05:23:25 PM PDT 24
Finished Jun 24 05:23:31 PM PDT 24
Peak memory 206240 kb
Host smart-e9c86834-b6d3-4e31-8c0d-275a93407cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23173
04472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.2317304472
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.2138046215
Short name T1058
Test name
Test status
Simulation time 5695076428 ps
CPU time 159.12 seconds
Started Jun 24 05:23:24 PM PDT 24
Finished Jun 24 05:26:06 PM PDT 24
Peak memory 206392 kb
Host smart-33de5e38-de1f-45f3-9f44-95b644a37957
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2138046215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.2138046215
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.1991135774
Short name T2314
Test name
Test status
Simulation time 236541214 ps
CPU time 0.94 seconds
Started Jun 24 05:23:23 PM PDT 24
Finished Jun 24 05:23:25 PM PDT 24
Peak memory 206124 kb
Host smart-5247b4e3-e1f0-4b10-af83-fe9191d523a4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1991135774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.1991135774
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.900529549
Short name T1699
Test name
Test status
Simulation time 184938813 ps
CPU time 0.86 seconds
Started Jun 24 05:23:22 PM PDT 24
Finished Jun 24 05:23:23 PM PDT 24
Peak memory 206168 kb
Host smart-9a4217fd-88bb-4000-ac66-600e26c0f3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90052
9549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.900529549
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.3872371183
Short name T1700
Test name
Test status
Simulation time 13644337748 ps
CPU time 369.72 seconds
Started Jun 24 05:23:23 PM PDT 24
Finished Jun 24 05:29:35 PM PDT 24
Peak memory 206372 kb
Host smart-9dfaa218-2d10-4903-9be7-24a829e35cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38723
71183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.3872371183
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.3544504529
Short name T1473
Test name
Test status
Simulation time 5531605014 ps
CPU time 42.09 seconds
Started Jun 24 05:23:23 PM PDT 24
Finished Jun 24 05:24:07 PM PDT 24
Peak memory 206324 kb
Host smart-299372b0-6868-4f17-ba40-662aac4abd63
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3544504529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.3544504529
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.1229723374
Short name T1468
Test name
Test status
Simulation time 158225943 ps
CPU time 0.79 seconds
Started Jun 24 05:23:23 PM PDT 24
Finished Jun 24 05:23:26 PM PDT 24
Peak memory 206196 kb
Host smart-ae226bb5-d49e-442b-b04b-678203f148e7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1229723374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.1229723374
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2525058854
Short name T1079
Test name
Test status
Simulation time 238454424 ps
CPU time 0.82 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:33 PM PDT 24
Peak memory 206156 kb
Host smart-eb3d5c6a-62f5-4dc9-8578-8300bcadc7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25250
58854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2525058854
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.4058866170
Short name T2477
Test name
Test status
Simulation time 211000676 ps
CPU time 0.84 seconds
Started Jun 24 05:23:24 PM PDT 24
Finished Jun 24 05:23:28 PM PDT 24
Peak memory 206168 kb
Host smart-ad2a0293-378e-444f-80eb-9028c8577976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40588
66170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.4058866170
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.3640539963
Short name T929
Test name
Test status
Simulation time 266353658 ps
CPU time 0.93 seconds
Started Jun 24 05:23:22 PM PDT 24
Finished Jun 24 05:23:25 PM PDT 24
Peak memory 206108 kb
Host smart-73642272-b610-4eaf-ad66-bc30094e865f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36405
39963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.3640539963
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.2833189708
Short name T2216
Test name
Test status
Simulation time 211510019 ps
CPU time 0.87 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:32 PM PDT 24
Peak memory 206180 kb
Host smart-129b2f17-2911-473d-89f8-677f81045d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28331
89708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2833189708
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.508239300
Short name T2201
Test name
Test status
Simulation time 227871565 ps
CPU time 0.86 seconds
Started Jun 24 05:23:21 PM PDT 24
Finished Jun 24 05:23:23 PM PDT 24
Peak memory 206176 kb
Host smart-40acd19e-e701-4b11-8ec8-a17a300e2939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50823
9300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.508239300
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.322572454
Short name T2195
Test name
Test status
Simulation time 166251482 ps
CPU time 0.81 seconds
Started Jun 24 05:23:22 PM PDT 24
Finished Jun 24 05:23:25 PM PDT 24
Peak memory 206428 kb
Host smart-8597d96f-a9e6-4a06-bb19-f1f99a8e87aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32257
2454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.322572454
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.2177368467
Short name T1028
Test name
Test status
Simulation time 292669075 ps
CPU time 1.01 seconds
Started Jun 24 05:23:23 PM PDT 24
Finished Jun 24 05:23:26 PM PDT 24
Peak memory 206172 kb
Host smart-68cf085b-0114-4584-bbba-cae4d5657b6f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2177368467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.2177368467
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.1406852591
Short name T595
Test name
Test status
Simulation time 204272595 ps
CPU time 0.77 seconds
Started Jun 24 05:23:21 PM PDT 24
Finished Jun 24 05:23:23 PM PDT 24
Peak memory 206152 kb
Host smart-2d05d4f1-d888-4a5b-8d09-57025502c84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14068
52591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1406852591
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2165128332
Short name T2038
Test name
Test status
Simulation time 39264570 ps
CPU time 0.67 seconds
Started Jun 24 05:23:22 PM PDT 24
Finished Jun 24 05:23:23 PM PDT 24
Peak memory 206104 kb
Host smart-fb53a8bf-8099-4ff0-8f76-4914359d30cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21651
28332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2165128332
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.471989637
Short name T167
Test name
Test status
Simulation time 16430051547 ps
CPU time 38.41 seconds
Started Jun 24 05:23:23 PM PDT 24
Finished Jun 24 05:24:04 PM PDT 24
Peak memory 206436 kb
Host smart-6161b95a-55d5-43ff-a8fe-e7573db601d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47198
9637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.471989637
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.3073961839
Short name T1967
Test name
Test status
Simulation time 176866213 ps
CPU time 0.88 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:32 PM PDT 24
Peak memory 205556 kb
Host smart-3b8cf97e-d293-4ffb-b679-284a26bd863b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30739
61839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.3073961839
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.3179172109
Short name T2292
Test name
Test status
Simulation time 241513247 ps
CPU time 0.89 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:32 PM PDT 24
Peak memory 205488 kb
Host smart-df441d69-b6cd-4812-872f-7fc3081f8dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31791
72109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3179172109
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.512526903
Short name T1992
Test name
Test status
Simulation time 231093807 ps
CPU time 0.95 seconds
Started Jun 24 05:23:22 PM PDT 24
Finished Jun 24 05:23:25 PM PDT 24
Peak memory 206192 kb
Host smart-4ef1dddf-c759-4e13-93a7-44c356638e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51252
6903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.512526903
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.3738630255
Short name T514
Test name
Test status
Simulation time 182612216 ps
CPU time 0.83 seconds
Started Jun 24 05:23:22 PM PDT 24
Finished Jun 24 05:23:25 PM PDT 24
Peak memory 206148 kb
Host smart-452dd9ff-24cc-4fa8-a998-1efc402c32fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37386
30255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.3738630255
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.3749142288
Short name T501
Test name
Test status
Simulation time 160828198 ps
CPU time 0.8 seconds
Started Jun 24 05:23:23 PM PDT 24
Finished Jun 24 05:23:26 PM PDT 24
Peak memory 206192 kb
Host smart-abf83972-644e-452c-818c-2afa09627770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37491
42288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3749142288
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3630973412
Short name T987
Test name
Test status
Simulation time 172366210 ps
CPU time 0.78 seconds
Started Jun 24 05:23:21 PM PDT 24
Finished Jun 24 05:23:23 PM PDT 24
Peak memory 206092 kb
Host smart-a4b6fae6-64ce-4ea2-aa1f-9c3d1cbc1e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36309
73412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3630973412
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1273001141
Short name T1208
Test name
Test status
Simulation time 146837372 ps
CPU time 0.77 seconds
Started Jun 24 05:23:21 PM PDT 24
Finished Jun 24 05:23:22 PM PDT 24
Peak memory 206164 kb
Host smart-a0f38f7c-042a-47d4-a9fd-9b910845264a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12730
01141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1273001141
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.4015870522
Short name T1896
Test name
Test status
Simulation time 257166230 ps
CPU time 0.87 seconds
Started Jun 24 05:23:22 PM PDT 24
Finished Jun 24 05:23:25 PM PDT 24
Peak memory 206140 kb
Host smart-6c8dfd0b-639c-4686-9e44-f01064707d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40158
70522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.4015870522
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.3812109700
Short name T2315
Test name
Test status
Simulation time 4046276658 ps
CPU time 29.36 seconds
Started Jun 24 05:23:22 PM PDT 24
Finished Jun 24 05:23:54 PM PDT 24
Peak memory 206384 kb
Host smart-636ea373-4c87-464e-b396-4e57b87f7f0c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3812109700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.3812109700
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1608984999
Short name T863
Test name
Test status
Simulation time 190249984 ps
CPU time 0.82 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:34 PM PDT 24
Peak memory 206156 kb
Host smart-0256849d-ac97-47f0-ad97-6fd15a721de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16089
84999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1608984999
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.4081232614
Short name T1306
Test name
Test status
Simulation time 214507814 ps
CPU time 0.86 seconds
Started Jun 24 05:23:23 PM PDT 24
Finished Jun 24 05:23:25 PM PDT 24
Peak memory 206160 kb
Host smart-a914a465-cde3-4cfc-ba04-277d6c8ff84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40812
32614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.4081232614
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.3535273009
Short name T2413
Test name
Test status
Simulation time 9188774238 ps
CPU time 62.3 seconds
Started Jun 24 05:23:32 PM PDT 24
Finished Jun 24 05:24:38 PM PDT 24
Peak memory 206364 kb
Host smart-b973d820-101c-4ed7-940d-fb0d9bd4dfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35352
73009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.3535273009
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.650379647
Short name T212
Test name
Test status
Simulation time 3418682190 ps
CPU time 3.69 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:39 PM PDT 24
Peak memory 206444 kb
Host smart-6b0112c5-e5b4-4611-a137-a2cc67a26d80
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=650379647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.650379647
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.2832420312
Short name T1546
Test name
Test status
Simulation time 13413375144 ps
CPU time 14.6 seconds
Started Jun 24 05:23:32 PM PDT 24
Finished Jun 24 05:23:51 PM PDT 24
Peak memory 206244 kb
Host smart-4da4acbc-16cc-4ad2-9239-0163117e2235
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2832420312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.2832420312
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.246115403
Short name T573
Test name
Test status
Simulation time 23392179385 ps
CPU time 24.61 seconds
Started Jun 24 05:23:32 PM PDT 24
Finished Jun 24 05:24:01 PM PDT 24
Peak memory 206260 kb
Host smart-b4957f97-ef09-4e04-b128-06645b77732e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=246115403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.246115403
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.255043628
Short name T447
Test name
Test status
Simulation time 152795009 ps
CPU time 0.78 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:34 PM PDT 24
Peak memory 206076 kb
Host smart-d6eb73f6-feda-4dd6-83b0-47f0bc0c1b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25504
3628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.255043628
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.3563342265
Short name T2105
Test name
Test status
Simulation time 159581040 ps
CPU time 0.76 seconds
Started Jun 24 05:23:28 PM PDT 24
Finished Jun 24 05:23:30 PM PDT 24
Peak memory 206160 kb
Host smart-9bf372a4-fee3-4a73-8a27-bd47edc8b6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35633
42265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.3563342265
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.4287161815
Short name T1465
Test name
Test status
Simulation time 500673411 ps
CPU time 1.54 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:33 PM PDT 24
Peak memory 206180 kb
Host smart-c1cdc498-4f10-4ed1-91ee-6e1061e8b991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42871
61815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.4287161815
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3072229952
Short name T191
Test name
Test status
Simulation time 967275885 ps
CPU time 2.21 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:35 PM PDT 24
Peak memory 206264 kb
Host smart-6c0b537c-4c91-4a0f-9b57-f4aec9ab11fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30722
29952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3072229952
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.2562184059
Short name T82
Test name
Test status
Simulation time 19302400989 ps
CPU time 35.46 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:24:11 PM PDT 24
Peak memory 206336 kb
Host smart-01997f1b-30c3-4978-ad3f-3bf7506a1515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25621
84059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2562184059
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.112113331
Short name T864
Test name
Test status
Simulation time 396007217 ps
CPU time 1.23 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:34 PM PDT 24
Peak memory 206180 kb
Host smart-613801fa-1dd7-4771-93aa-eeb409ebb1e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11211
3331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.112113331
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.1156713965
Short name T1309
Test name
Test status
Simulation time 141799936 ps
CPU time 0.73 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:34 PM PDT 24
Peak memory 206172 kb
Host smart-613fd6d1-ad0a-49a6-8d1e-0732a86c8526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11567
13965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1156713965
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.3995010828
Short name T1846
Test name
Test status
Simulation time 37682447 ps
CPU time 0.66 seconds
Started Jun 24 05:23:32 PM PDT 24
Finished Jun 24 05:23:36 PM PDT 24
Peak memory 206168 kb
Host smart-54a5157f-27d3-4720-a7eb-dd0f0d874cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39950
10828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3995010828
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3722117019
Short name T723
Test name
Test status
Simulation time 1057497831 ps
CPU time 2.33 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:37 PM PDT 24
Peak memory 206304 kb
Host smart-18c1ae69-d21e-4ab4-a957-d686410ba66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37221
17019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3722117019
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2985327169
Short name T1889
Test name
Test status
Simulation time 178506319 ps
CPU time 1.92 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:36 PM PDT 24
Peak memory 206280 kb
Host smart-8a023dc3-3324-47e9-8350-301057425f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29853
27169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2985327169
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.318920011
Short name T947
Test name
Test status
Simulation time 234644674 ps
CPU time 0.85 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:33 PM PDT 24
Peak memory 206104 kb
Host smart-0cd5dbff-905f-48f0-ae1e-a223a1b65f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31892
0011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.318920011
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.188067930
Short name T120
Test name
Test status
Simulation time 170280529 ps
CPU time 0.8 seconds
Started Jun 24 05:23:32 PM PDT 24
Finished Jun 24 05:23:37 PM PDT 24
Peak memory 206148 kb
Host smart-0469bbd5-f13d-49e2-8902-99ccaa6f0178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18806
7930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.188067930
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.405032982
Short name T1933
Test name
Test status
Simulation time 220082495 ps
CPU time 0.92 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:35 PM PDT 24
Peak memory 206188 kb
Host smart-6b72b4b0-eeb7-4997-85b2-608e37dd1a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40503
2982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.405032982
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1091453101
Short name T2347
Test name
Test status
Simulation time 213359989 ps
CPU time 0.86 seconds
Started Jun 24 05:23:35 PM PDT 24
Finished Jun 24 05:23:38 PM PDT 24
Peak memory 206092 kb
Host smart-b365d730-b93b-4582-ac41-0f4e475a2a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10914
53101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1091453101
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.544759646
Short name T546
Test name
Test status
Simulation time 23345764647 ps
CPU time 22.93 seconds
Started Jun 24 05:23:32 PM PDT 24
Finished Jun 24 05:23:59 PM PDT 24
Peak memory 206136 kb
Host smart-7caefe6c-9e08-4a8e-8a79-76adccaa3bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54475
9646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.544759646
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.2989419962
Short name T345
Test name
Test status
Simulation time 3400186779 ps
CPU time 3.6 seconds
Started Jun 24 05:23:34 PM PDT 24
Finished Jun 24 05:23:40 PM PDT 24
Peak memory 206240 kb
Host smart-aeef4813-6dc4-42a7-a094-0bb38a19afb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29894
19962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.2989419962
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.2367062233
Short name T1061
Test name
Test status
Simulation time 9815367248 ps
CPU time 75.58 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:24:50 PM PDT 24
Peak memory 206424 kb
Host smart-07d042e3-4770-4e02-a580-94b04f50b51c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2367062233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.2367062233
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3581031859
Short name T1902
Test name
Test status
Simulation time 240308268 ps
CPU time 0.92 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:36 PM PDT 24
Peak memory 206196 kb
Host smart-2ca6ce1a-2ec9-4852-9c46-797e937d1dbe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3581031859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3581031859
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.2248814720
Short name T1601
Test name
Test status
Simulation time 196034959 ps
CPU time 0.92 seconds
Started Jun 24 05:23:33 PM PDT 24
Finished Jun 24 05:23:37 PM PDT 24
Peak memory 206180 kb
Host smart-a71f6c55-2a62-4828-a04d-06bb96ed7e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22488
14720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2248814720
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.1618179008
Short name T2501
Test name
Test status
Simulation time 4181573676 ps
CPU time 31.09 seconds
Started Jun 24 05:23:32 PM PDT 24
Finished Jun 24 05:24:07 PM PDT 24
Peak memory 206328 kb
Host smart-e57e1197-6918-4a23-8c48-619f1a1e9e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16181
79008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.1618179008
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.2152253281
Short name T1154
Test name
Test status
Simulation time 7211523299 ps
CPU time 53.42 seconds
Started Jun 24 05:23:28 PM PDT 24
Finished Jun 24 05:24:22 PM PDT 24
Peak memory 206248 kb
Host smart-a4c998f9-cd09-40b6-9fb3-c8a29553399e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2152253281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.2152253281
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.3430357010
Short name T1315
Test name
Test status
Simulation time 160035839 ps
CPU time 0.86 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:33 PM PDT 24
Peak memory 206176 kb
Host smart-61a7a3bb-2608-412e-a2d6-bd69643efd1b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3430357010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.3430357010
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3390432035
Short name T2439
Test name
Test status
Simulation time 142371930 ps
CPU time 0.74 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:34 PM PDT 24
Peak memory 206180 kb
Host smart-ebde4c52-65cd-4d76-8777-0aa94cd71c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33904
32035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3390432035
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3372318826
Short name T1424
Test name
Test status
Simulation time 222628525 ps
CPU time 0.93 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:33 PM PDT 24
Peak memory 206060 kb
Host smart-b6cf5e0b-c4a8-47f1-a68d-09ca2875f9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33723
18826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3372318826
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2596118540
Short name T2247
Test name
Test status
Simulation time 210632407 ps
CPU time 0.9 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:36 PM PDT 24
Peak memory 206192 kb
Host smart-5c764d4a-d11e-4942-94e9-68ac735600e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25961
18540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2596118540
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1713704232
Short name T641
Test name
Test status
Simulation time 200166284 ps
CPU time 0.81 seconds
Started Jun 24 05:23:33 PM PDT 24
Finished Jun 24 05:23:37 PM PDT 24
Peak memory 206180 kb
Host smart-d892db15-ab7d-45c7-9cc7-7eb9e95baba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17137
04232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1713704232
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2184255042
Short name T1985
Test name
Test status
Simulation time 146940106 ps
CPU time 0.77 seconds
Started Jun 24 05:23:32 PM PDT 24
Finished Jun 24 05:23:36 PM PDT 24
Peak memory 206188 kb
Host smart-63185a60-c4b3-46b2-8428-7a0b07cd9499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21842
55042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2184255042
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1713166600
Short name T170
Test name
Test status
Simulation time 159892745 ps
CPU time 0.81 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:36 PM PDT 24
Peak memory 206416 kb
Host smart-467d18df-6e42-4a4c-a59c-1ecf7ac58d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17131
66600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1713166600
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.4090224010
Short name T1708
Test name
Test status
Simulation time 248394211 ps
CPU time 0.95 seconds
Started Jun 24 05:23:34 PM PDT 24
Finished Jun 24 05:23:38 PM PDT 24
Peak memory 206172 kb
Host smart-3eebabcb-c16f-412e-a9cf-b6a13bd423f8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4090224010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.4090224010
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1413358986
Short name T2141
Test name
Test status
Simulation time 160775295 ps
CPU time 0.79 seconds
Started Jun 24 05:23:33 PM PDT 24
Finished Jun 24 05:23:37 PM PDT 24
Peak memory 206424 kb
Host smart-6ed174aa-b682-4801-9f13-e732b0974e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14133
58986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1413358986
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1280217824
Short name T2003
Test name
Test status
Simulation time 43131290 ps
CPU time 0.68 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:35 PM PDT 24
Peak memory 206168 kb
Host smart-174c1132-6ca1-45e3-9012-9235540da02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12802
17824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1280217824
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1869736658
Short name T254
Test name
Test status
Simulation time 8532620319 ps
CPU time 18.48 seconds
Started Jun 24 05:23:32 PM PDT 24
Finished Jun 24 05:23:54 PM PDT 24
Peak memory 206440 kb
Host smart-0201c492-981f-4737-8aed-7f35e74587eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18697
36658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1869736658
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2959675779
Short name T618
Test name
Test status
Simulation time 209904064 ps
CPU time 0.89 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:32 PM PDT 24
Peak memory 206168 kb
Host smart-a0796bac-cbe0-4eda-bb9a-664ea51c34ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29596
75779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2959675779
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.886549944
Short name T1054
Test name
Test status
Simulation time 167733357 ps
CPU time 0.79 seconds
Started Jun 24 05:23:33 PM PDT 24
Finished Jun 24 05:23:37 PM PDT 24
Peak memory 206428 kb
Host smart-45d8c7a4-d153-475f-8bb7-d7a95e4b4b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88654
9944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.886549944
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.180020733
Short name T2503
Test name
Test status
Simulation time 179365867 ps
CPU time 0.86 seconds
Started Jun 24 05:23:35 PM PDT 24
Finished Jun 24 05:23:38 PM PDT 24
Peak memory 206076 kb
Host smart-d0ec2e03-e55b-47ca-9ecd-11263728380c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18002
0733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.180020733
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.36818290
Short name T2044
Test name
Test status
Simulation time 140352039 ps
CPU time 0.79 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:35 PM PDT 24
Peak memory 206168 kb
Host smart-a4f73b2c-0cb5-464f-9e36-b27f5aea5c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36818
290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.36818290
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1153093088
Short name T2243
Test name
Test status
Simulation time 200893456 ps
CPU time 0.81 seconds
Started Jun 24 05:23:32 PM PDT 24
Finished Jun 24 05:23:37 PM PDT 24
Peak memory 206144 kb
Host smart-ce85a69f-71a3-4361-90db-eede52e07a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11530
93088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1153093088
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.663109745
Short name T1657
Test name
Test status
Simulation time 160949104 ps
CPU time 0.78 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:23:34 PM PDT 24
Peak memory 206176 kb
Host smart-39727a10-dede-441e-81f4-6840d1fce3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66310
9745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.663109745
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.401093857
Short name T2458
Test name
Test status
Simulation time 257407549 ps
CPU time 1 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:33 PM PDT 24
Peak memory 206192 kb
Host smart-d8cfe2b1-93ac-40b7-93fb-c95328b17eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40109
3857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.401093857
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.2716909307
Short name T1857
Test name
Test status
Simulation time 9028084303 ps
CPU time 64.21 seconds
Started Jun 24 05:23:31 PM PDT 24
Finished Jun 24 05:24:39 PM PDT 24
Peak memory 206356 kb
Host smart-c2dd4132-bc1f-4c67-8208-09889870417d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2716909307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.2716909307
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1923646386
Short name T1119
Test name
Test status
Simulation time 166870303 ps
CPU time 0.78 seconds
Started Jun 24 05:23:29 PM PDT 24
Finished Jun 24 05:23:31 PM PDT 24
Peak memory 206188 kb
Host smart-de08836d-5116-4fa6-a781-ae5810fac0cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19236
46386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1923646386
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.2554370507
Short name T1163
Test name
Test status
Simulation time 185518163 ps
CPU time 0.83 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:23:33 PM PDT 24
Peak memory 206176 kb
Host smart-658748a8-21b5-48ac-891d-2e08ddbe86f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25543
70507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.2554370507
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.255311769
Short name T917
Test name
Test status
Simulation time 7061716546 ps
CPU time 194.78 seconds
Started Jun 24 05:23:30 PM PDT 24
Finished Jun 24 05:26:47 PM PDT 24
Peak memory 206396 kb
Host smart-caa78b27-3160-4e4a-b1e4-b1cf45ad8477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25531
1769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.255311769
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.3877860367
Short name T1562
Test name
Test status
Simulation time 4049162235 ps
CPU time 5.01 seconds
Started Jun 24 05:20:18 PM PDT 24
Finished Jun 24 05:20:25 PM PDT 24
Peak memory 206224 kb
Host smart-38fe0463-b9f5-44db-bc40-907c0930a1bb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3877860367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.3877860367
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.4140461361
Short name T1880
Test name
Test status
Simulation time 13443264068 ps
CPU time 12.93 seconds
Started Jun 24 05:20:17 PM PDT 24
Finished Jun 24 05:20:32 PM PDT 24
Peak memory 206288 kb
Host smart-3176657f-a858-4e5a-a4e4-476a109c7f7b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4140461361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.4140461361
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1847662174
Short name T590
Test name
Test status
Simulation time 23342461918 ps
CPU time 22.66 seconds
Started Jun 24 05:20:21 PM PDT 24
Finished Jun 24 05:20:44 PM PDT 24
Peak memory 206452 kb
Host smart-1947348b-aa47-4b7b-8774-b59c6f6e0317
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1847662174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.1847662174
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.644683193
Short name T1595
Test name
Test status
Simulation time 166365260 ps
CPU time 0.83 seconds
Started Jun 24 05:20:24 PM PDT 24
Finished Jun 24 05:20:26 PM PDT 24
Peak memory 206092 kb
Host smart-4204cf71-2e03-4aad-b6e7-f21e1d32e66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64468
3193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.644683193
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.2493914541
Short name T2428
Test name
Test status
Simulation time 160688794 ps
CPU time 0.79 seconds
Started Jun 24 05:20:25 PM PDT 24
Finished Jun 24 05:20:27 PM PDT 24
Peak memory 206060 kb
Host smart-1d6b735b-2a85-438d-8eb8-80d76be96ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24939
14541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.2493914541
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.1751304359
Short name T21
Test name
Test status
Simulation time 137522080 ps
CPU time 0.76 seconds
Started Jun 24 05:20:23 PM PDT 24
Finished Jun 24 05:20:25 PM PDT 24
Peak memory 206188 kb
Host smart-3246bb0d-74cc-47c9-9705-8bbe0a1837f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17513
04359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.1751304359
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.2203969451
Short name T2312
Test name
Test status
Simulation time 180575332 ps
CPU time 0.85 seconds
Started Jun 24 05:20:26 PM PDT 24
Finished Jun 24 05:20:28 PM PDT 24
Peak memory 206160 kb
Host smart-cae20fc5-365e-43d0-9907-b3b6ebbd9e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22039
69451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.2203969451
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.2133363514
Short name T540
Test name
Test status
Simulation time 397789460 ps
CPU time 1.25 seconds
Started Jun 24 05:20:27 PM PDT 24
Finished Jun 24 05:20:30 PM PDT 24
Peak memory 206112 kb
Host smart-d7d24f7c-a605-4e10-a48e-865b6b347b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21333
63514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.2133363514
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.736134549
Short name T1378
Test name
Test status
Simulation time 349392577 ps
CPU time 1.07 seconds
Started Jun 24 05:20:24 PM PDT 24
Finished Jun 24 05:20:26 PM PDT 24
Peak memory 206156 kb
Host smart-325145a1-eeba-46a9-b9a9-1c213f0c3e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73613
4549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.736134549
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.4135873975
Short name T778
Test name
Test status
Simulation time 20478332508 ps
CPU time 34.22 seconds
Started Jun 24 05:20:24 PM PDT 24
Finished Jun 24 05:21:00 PM PDT 24
Peak memory 206312 kb
Host smart-9903870d-e212-4cd1-886d-c2be5ed0a1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41358
73975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.4135873975
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.2967815766
Short name T1160
Test name
Test status
Simulation time 447569040 ps
CPU time 1.52 seconds
Started Jun 24 05:20:22 PM PDT 24
Finished Jun 24 05:20:25 PM PDT 24
Peak memory 206176 kb
Host smart-27099444-eb34-407e-b2f2-16f9fe9f34f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29678
15766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.2967815766
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.458323942
Short name T810
Test name
Test status
Simulation time 197935368 ps
CPU time 0.8 seconds
Started Jun 24 05:20:24 PM PDT 24
Finished Jun 24 05:20:26 PM PDT 24
Peak memory 206172 kb
Host smart-66009dd2-cdd2-4111-bb43-8a1f2adfca38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45832
3942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.458323942
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.2449973724
Short name T2420
Test name
Test status
Simulation time 45178907 ps
CPU time 0.71 seconds
Started Jun 24 05:20:28 PM PDT 24
Finished Jun 24 05:20:30 PM PDT 24
Peak memory 206168 kb
Host smart-f9396f07-de1c-491d-ab42-b57b0faa6d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24499
73724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2449973724
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1680548355
Short name T695
Test name
Test status
Simulation time 950115979 ps
CPU time 2.12 seconds
Started Jun 24 05:20:23 PM PDT 24
Finished Jun 24 05:20:26 PM PDT 24
Peak memory 206336 kb
Host smart-5cad71b6-cb9a-469f-adf5-130f5cc2d2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16805
48355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1680548355
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.639161942
Short name T1821
Test name
Test status
Simulation time 216998414 ps
CPU time 1.38 seconds
Started Jun 24 05:20:25 PM PDT 24
Finished Jun 24 05:20:27 PM PDT 24
Peak memory 206228 kb
Host smart-923d1e11-4eac-4a0a-9153-221927419a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63916
1942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.639161942
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1899662654
Short name T1543
Test name
Test status
Simulation time 206983224 ps
CPU time 0.9 seconds
Started Jun 24 05:20:30 PM PDT 24
Finished Jun 24 05:20:31 PM PDT 24
Peak memory 206176 kb
Host smart-4fd40409-0756-42ec-9e0e-b146ae5776b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18996
62654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1899662654
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2126627898
Short name T27
Test name
Test status
Simulation time 194564154 ps
CPU time 0.86 seconds
Started Jun 24 05:20:31 PM PDT 24
Finished Jun 24 05:20:32 PM PDT 24
Peak memory 206188 kb
Host smart-fd09af72-98a6-4e45-8442-5ccc8fc40744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21266
27898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2126627898
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1525255828
Short name T821
Test name
Test status
Simulation time 250478874 ps
CPU time 0.87 seconds
Started Jun 24 05:20:27 PM PDT 24
Finished Jun 24 05:20:29 PM PDT 24
Peak memory 206160 kb
Host smart-b2c1e9a7-73ee-49b4-b17f-5fc1b94c8ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15252
55828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1525255828
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.1742896101
Short name T1142
Test name
Test status
Simulation time 10785147867 ps
CPU time 291.87 seconds
Started Jun 24 05:20:22 PM PDT 24
Finished Jun 24 05:25:15 PM PDT 24
Peak memory 206404 kb
Host smart-58797359-61fb-49f5-b1d8-340380ef27b3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1742896101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.1742896101
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.42249431
Short name T539
Test name
Test status
Simulation time 192403551 ps
CPU time 0.86 seconds
Started Jun 24 05:20:23 PM PDT 24
Finished Jun 24 05:20:25 PM PDT 24
Peak memory 206176 kb
Host smart-2e94a64b-7e71-4519-b641-9fc7ee86b26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42249
431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.42249431
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.1199444652
Short name T1874
Test name
Test status
Simulation time 23343979847 ps
CPU time 20.02 seconds
Started Jun 24 05:20:28 PM PDT 24
Finished Jun 24 05:20:49 PM PDT 24
Peak memory 206152 kb
Host smart-ce0e8cbe-8240-472d-b7dc-a67b488ce0be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11994
44652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.1199444652
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3426756216
Short name T979
Test name
Test status
Simulation time 3328798364 ps
CPU time 3.81 seconds
Started Jun 24 05:20:29 PM PDT 24
Finished Jun 24 05:20:33 PM PDT 24
Peak memory 206140 kb
Host smart-73ebb3d4-4d7c-4d0c-aff3-79002b717818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34267
56216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3426756216
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3076786736
Short name T922
Test name
Test status
Simulation time 8559444380 ps
CPU time 58.59 seconds
Started Jun 24 05:20:24 PM PDT 24
Finished Jun 24 05:21:23 PM PDT 24
Peak memory 206408 kb
Host smart-8e9f4479-ead3-4e16-9f03-a07aa9cee7da
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3076786736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3076786736
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.3774039825
Short name T1684
Test name
Test status
Simulation time 261160033 ps
CPU time 0.99 seconds
Started Jun 24 05:20:30 PM PDT 24
Finished Jun 24 05:20:32 PM PDT 24
Peak memory 206196 kb
Host smart-28995e66-2150-414d-b974-3235acf6df7c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3774039825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.3774039825
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2759957874
Short name T1359
Test name
Test status
Simulation time 191607650 ps
CPU time 0.89 seconds
Started Jun 24 05:20:26 PM PDT 24
Finished Jun 24 05:20:28 PM PDT 24
Peak memory 206196 kb
Host smart-9f6301c1-4d26-495a-97aa-d070f2aceb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27599
57874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2759957874
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.2338734212
Short name T2110
Test name
Test status
Simulation time 9258721068 ps
CPU time 79.66 seconds
Started Jun 24 05:20:27 PM PDT 24
Finished Jun 24 05:21:48 PM PDT 24
Peak memory 206236 kb
Host smart-acf6d718-98ad-4782-9933-93bd14f3bea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23387
34212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.2338734212
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1953639234
Short name T1365
Test name
Test status
Simulation time 12931107800 ps
CPU time 92.3 seconds
Started Jun 24 05:20:27 PM PDT 24
Finished Jun 24 05:22:00 PM PDT 24
Peak memory 206324 kb
Host smart-687c4017-3365-49ee-8b4a-136798c31bcb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1953639234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1953639234
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.3748204243
Short name T2204
Test name
Test status
Simulation time 188962529 ps
CPU time 0.79 seconds
Started Jun 24 05:20:34 PM PDT 24
Finished Jun 24 05:20:36 PM PDT 24
Peak memory 206092 kb
Host smart-9bbd2c1f-87a5-4c36-aa7d-446ed95ae3dc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3748204243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.3748204243
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.544549106
Short name T403
Test name
Test status
Simulation time 146112648 ps
CPU time 0.74 seconds
Started Jun 24 05:20:23 PM PDT 24
Finished Jun 24 05:20:24 PM PDT 24
Peak memory 206196 kb
Host smart-6ebe648a-f693-4ca1-8c2b-f14d3e19e1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54454
9106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.544549106
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2918959900
Short name T134
Test name
Test status
Simulation time 239790039 ps
CPU time 0.92 seconds
Started Jun 24 05:20:23 PM PDT 24
Finished Jun 24 05:20:24 PM PDT 24
Peak memory 206172 kb
Host smart-366e578c-34be-41fc-b49c-7c702bb40df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29189
59900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2918959900
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.921165037
Short name T940
Test name
Test status
Simulation time 161536919 ps
CPU time 0.79 seconds
Started Jun 24 05:20:25 PM PDT 24
Finished Jun 24 05:20:27 PM PDT 24
Peak memory 206048 kb
Host smart-c0411431-d365-427c-be45-8e042e41ca59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92116
5037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.921165037
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.442310473
Short name T1882
Test name
Test status
Simulation time 182619719 ps
CPU time 0.86 seconds
Started Jun 24 05:20:26 PM PDT 24
Finished Jun 24 05:20:28 PM PDT 24
Peak memory 206192 kb
Host smart-9c71c312-cd54-405c-8e0b-913ad2fe8d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44231
0473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.442310473
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1728612876
Short name T2138
Test name
Test status
Simulation time 222564453 ps
CPU time 0.9 seconds
Started Jun 24 05:20:28 PM PDT 24
Finished Jun 24 05:20:30 PM PDT 24
Peak memory 206172 kb
Host smart-e2afb9f2-9916-472f-add9-9d56d304b083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17286
12876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1728612876
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1057691574
Short name T178
Test name
Test status
Simulation time 173607910 ps
CPU time 0.87 seconds
Started Jun 24 05:20:32 PM PDT 24
Finished Jun 24 05:20:34 PM PDT 24
Peak memory 206176 kb
Host smart-05d4b123-feed-47fc-a790-ec3b62c01549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10576
91574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1057691574
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.3612274453
Short name T2019
Test name
Test status
Simulation time 192373437 ps
CPU time 0.86 seconds
Started Jun 24 05:20:26 PM PDT 24
Finished Jun 24 05:20:28 PM PDT 24
Peak memory 206180 kb
Host smart-7c8ca3dd-bb8b-4cad-bafc-b8a021c8fd90
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3612274453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.3612274453
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.2839948118
Short name T568
Test name
Test status
Simulation time 238582400 ps
CPU time 0.91 seconds
Started Jun 24 05:20:27 PM PDT 24
Finished Jun 24 05:20:29 PM PDT 24
Peak memory 206176 kb
Host smart-654f2cad-9c42-4f9b-9151-f6bf7c9662d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28399
48118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.2839948118
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2684096335
Short name T787
Test name
Test status
Simulation time 148293589 ps
CPU time 0.75 seconds
Started Jun 24 05:20:24 PM PDT 24
Finished Jun 24 05:20:25 PM PDT 24
Peak memory 206180 kb
Host smart-7a31698f-74cf-4938-a705-80ffcdccc056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26840
96335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2684096335
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2780591945
Short name T1388
Test name
Test status
Simulation time 42305594 ps
CPU time 0.66 seconds
Started Jun 24 05:20:33 PM PDT 24
Finished Jun 24 05:20:35 PM PDT 24
Peak memory 206168 kb
Host smart-97dac3b8-59d1-4101-bae0-e38bef54344d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27805
91945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2780591945
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1705062455
Short name T1428
Test name
Test status
Simulation time 7253791784 ps
CPU time 18.04 seconds
Started Jun 24 05:20:23 PM PDT 24
Finished Jun 24 05:20:42 PM PDT 24
Peak memory 206412 kb
Host smart-98b4826f-d77b-493d-be8f-69d5012c0b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17050
62455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1705062455
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1236202494
Short name T980
Test name
Test status
Simulation time 186942974 ps
CPU time 0.81 seconds
Started Jun 24 05:20:27 PM PDT 24
Finished Jun 24 05:20:29 PM PDT 24
Peak memory 206172 kb
Host smart-4247beed-50a2-4851-839a-de0a7080805d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12362
02494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1236202494
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1444899729
Short name T1126
Test name
Test status
Simulation time 184322657 ps
CPU time 0.87 seconds
Started Jun 24 05:20:27 PM PDT 24
Finished Jun 24 05:20:29 PM PDT 24
Peak memory 206100 kb
Host smart-0f7a7424-6932-4e49-829d-e8d5203ef3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14448
99729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1444899729
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.1696100200
Short name T1055
Test name
Test status
Simulation time 6954593371 ps
CPU time 28.62 seconds
Started Jun 24 05:20:25 PM PDT 24
Finished Jun 24 05:20:55 PM PDT 24
Peak memory 206380 kb
Host smart-cff91605-1f62-4fd6-9ecf-a5a436479cec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1696100200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.1696100200
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.213825210
Short name T187
Test name
Test status
Simulation time 17722115758 ps
CPU time 139.31 seconds
Started Jun 24 05:20:23 PM PDT 24
Finished Jun 24 05:22:42 PM PDT 24
Peak memory 206196 kb
Host smart-2a95f57d-4d75-41da-85e7-317a47bf5daf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=213825210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.213825210
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2034714602
Short name T1962
Test name
Test status
Simulation time 34755359336 ps
CPU time 270.58 seconds
Started Jun 24 05:20:24 PM PDT 24
Finished Jun 24 05:24:56 PM PDT 24
Peak memory 206352 kb
Host smart-0d0d030a-befa-45e6-9274-797712313d94
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2034714602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2034714602
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.1212382069
Short name T737
Test name
Test status
Simulation time 202039414 ps
CPU time 0.85 seconds
Started Jun 24 05:20:34 PM PDT 24
Finished Jun 24 05:20:36 PM PDT 24
Peak memory 206200 kb
Host smart-453085a6-cef1-4317-b187-bd5cd402e039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12123
82069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1212382069
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.3486317981
Short name T1350
Test name
Test status
Simulation time 175231672 ps
CPU time 0.82 seconds
Started Jun 24 05:20:24 PM PDT 24
Finished Jun 24 05:20:26 PM PDT 24
Peak memory 206156 kb
Host smart-822c0570-be24-41c4-9e14-59370280a5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34863
17981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.3486317981
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1894063398
Short name T1251
Test name
Test status
Simulation time 176279038 ps
CPU time 0.87 seconds
Started Jun 24 05:20:27 PM PDT 24
Finished Jun 24 05:20:29 PM PDT 24
Peak memory 206100 kb
Host smart-2a42df60-ba0c-4195-ad01-56c91c2893b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18940
63398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1894063398
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.305302328
Short name T77
Test name
Test status
Simulation time 190750503 ps
CPU time 0.8 seconds
Started Jun 24 05:20:28 PM PDT 24
Finished Jun 24 05:20:30 PM PDT 24
Peak memory 206076 kb
Host smart-03116695-f8b2-4700-8dab-f2a0fa5586ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30530
2328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.305302328
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.50547640
Short name T218
Test name
Test status
Simulation time 486668138 ps
CPU time 1.32 seconds
Started Jun 24 05:20:32 PM PDT 24
Finished Jun 24 05:20:34 PM PDT 24
Peak memory 224884 kb
Host smart-892d7f8e-c569-427d-97e5-4393a1d41a73
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=50547640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.50547640
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.1573780800
Short name T55
Test name
Test status
Simulation time 451093310 ps
CPU time 1.41 seconds
Started Jun 24 05:20:28 PM PDT 24
Finished Jun 24 05:20:30 PM PDT 24
Peak memory 206192 kb
Host smart-b1c413d2-eabe-404c-ad8f-ea9db1cece59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15737
80800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.1573780800
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3870146570
Short name T1373
Test name
Test status
Simulation time 159214026 ps
CPU time 0.79 seconds
Started Jun 24 05:20:31 PM PDT 24
Finished Jun 24 05:20:33 PM PDT 24
Peak memory 206072 kb
Host smart-48ddf5be-3e1e-44e3-8775-45095829b4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38701
46570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3870146570
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2145188146
Short name T2391
Test name
Test status
Simulation time 152465861 ps
CPU time 0.89 seconds
Started Jun 24 05:20:38 PM PDT 24
Finished Jun 24 05:20:41 PM PDT 24
Peak memory 206096 kb
Host smart-5eb6dd6d-eb49-445a-9288-35d991060fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21451
88146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2145188146
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.402489233
Short name T1567
Test name
Test status
Simulation time 196901726 ps
CPU time 0.88 seconds
Started Jun 24 05:20:33 PM PDT 24
Finished Jun 24 05:20:35 PM PDT 24
Peak memory 206172 kb
Host smart-b1a9e24d-6058-4df0-a301-622e7c1f2c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40248
9233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.402489233
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.2624025180
Short name T1824
Test name
Test status
Simulation time 11078639446 ps
CPU time 111.25 seconds
Started Jun 24 05:20:39 PM PDT 24
Finished Jun 24 05:22:31 PM PDT 24
Peak memory 206228 kb
Host smart-5484b9c3-979e-46da-932b-ae364b97cc6f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2624025180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.2624025180
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.194710294
Short name T1288
Test name
Test status
Simulation time 185437457 ps
CPU time 0.85 seconds
Started Jun 24 05:20:33 PM PDT 24
Finished Jun 24 05:20:35 PM PDT 24
Peak memory 206164 kb
Host smart-ed9401ec-ccbf-4618-ae83-a2c85bc3eb74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19471
0294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.194710294
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2377776698
Short name T1794
Test name
Test status
Simulation time 157692491 ps
CPU time 0.87 seconds
Started Jun 24 05:20:36 PM PDT 24
Finished Jun 24 05:20:38 PM PDT 24
Peak memory 206188 kb
Host smart-80d45001-f849-47e3-9c00-91e97cdf645d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23777
76698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2377776698
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.38799965
Short name T1409
Test name
Test status
Simulation time 14020592038 ps
CPU time 135.24 seconds
Started Jun 24 05:20:32 PM PDT 24
Finished Jun 24 05:22:49 PM PDT 24
Peak memory 206292 kb
Host smart-aa888b4d-be1e-4f41-989c-ec4a8fff5c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38799
965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.38799965
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.188011790
Short name T2047
Test name
Test status
Simulation time 27977794503 ps
CPU time 685.82 seconds
Started Jun 24 05:20:32 PM PDT 24
Finished Jun 24 05:32:00 PM PDT 24
Peak memory 206376 kb
Host smart-329676b8-9f6a-4b27-94e2-2adca0aad064
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=188011790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.188011790
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.135212743
Short name T515
Test name
Test status
Simulation time 3821999425 ps
CPU time 4.63 seconds
Started Jun 24 05:23:36 PM PDT 24
Finished Jun 24 05:23:43 PM PDT 24
Peak memory 206264 kb
Host smart-5a17736d-9bbf-4c6b-86c4-a9af00a12d30
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=135212743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.135212743
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1202341923
Short name T1345
Test name
Test status
Simulation time 23392341528 ps
CPU time 22.79 seconds
Started Jun 24 05:23:44 PM PDT 24
Finished Jun 24 05:24:08 PM PDT 24
Peak memory 206240 kb
Host smart-b70f5f62-7ed5-48a6-b948-9de128b4955d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1202341923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.1202341923
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1494347620
Short name T1528
Test name
Test status
Simulation time 176621967 ps
CPU time 0.83 seconds
Started Jun 24 05:23:39 PM PDT 24
Finished Jun 24 05:23:42 PM PDT 24
Peak memory 206060 kb
Host smart-76598594-f123-47e3-95c7-4da031fa9fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14943
47620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1494347620
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.814572809
Short name T1493
Test name
Test status
Simulation time 150436231 ps
CPU time 0.76 seconds
Started Jun 24 05:23:38 PM PDT 24
Finished Jun 24 05:23:40 PM PDT 24
Peak memory 206100 kb
Host smart-1d4957f6-efaf-4948-9cdc-1c9967772651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81457
2809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.814572809
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.3419857441
Short name T1351
Test name
Test status
Simulation time 367848093 ps
CPU time 1.26 seconds
Started Jun 24 05:23:37 PM PDT 24
Finished Jun 24 05:23:40 PM PDT 24
Peak memory 206172 kb
Host smart-b90f5265-67b1-40fd-b648-8a995976e725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34198
57441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.3419857441
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1898797686
Short name T179
Test name
Test status
Simulation time 678182668 ps
CPU time 1.65 seconds
Started Jun 24 05:23:41 PM PDT 24
Finished Jun 24 05:23:45 PM PDT 24
Peak memory 206180 kb
Host smart-ad657b71-3a8f-459b-85b0-1fdff8ed8684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18987
97686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1898797686
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.2267565118
Short name T176
Test name
Test status
Simulation time 16100467900 ps
CPU time 29.7 seconds
Started Jun 24 05:23:39 PM PDT 24
Finished Jun 24 05:24:11 PM PDT 24
Peak memory 206328 kb
Host smart-f0064aaa-d0eb-404d-8aaa-74b2d73e6247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22675
65118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.2267565118
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.3804588088
Short name T1515
Test name
Test status
Simulation time 325459267 ps
CPU time 1.14 seconds
Started Jun 24 05:23:36 PM PDT 24
Finished Jun 24 05:23:39 PM PDT 24
Peak memory 206176 kb
Host smart-657c5b46-5ff5-41d8-aaf3-9d75389c21c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38045
88088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3804588088
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.3530681185
Short name T1118
Test name
Test status
Simulation time 136377782 ps
CPU time 0.8 seconds
Started Jun 24 05:23:41 PM PDT 24
Finished Jun 24 05:23:44 PM PDT 24
Peak memory 206168 kb
Host smart-08b86cda-6d8e-4566-af69-030fa38367ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35306
81185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.3530681185
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.258576279
Short name T881
Test name
Test status
Simulation time 47151871 ps
CPU time 0.73 seconds
Started Jun 24 05:23:38 PM PDT 24
Finished Jun 24 05:23:41 PM PDT 24
Peak memory 206416 kb
Host smart-d3c82b1b-2787-4b6b-8929-35ba8a182ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25857
6279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.258576279
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3103554566
Short name T1034
Test name
Test status
Simulation time 721098511 ps
CPU time 1.86 seconds
Started Jun 24 05:23:39 PM PDT 24
Finished Jun 24 05:23:43 PM PDT 24
Peak memory 206300 kb
Host smart-d15533f9-c1a4-427c-ae81-5bcbcf7aba6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31035
54566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3103554566
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3485685512
Short name T717
Test name
Test status
Simulation time 428882895 ps
CPU time 2.63 seconds
Started Jun 24 05:23:39 PM PDT 24
Finished Jun 24 05:23:43 PM PDT 24
Peak memory 206320 kb
Host smart-fac2f1c9-c9b4-4ce3-883b-55755dddd4e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34856
85512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3485685512
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.799641857
Short name T484
Test name
Test status
Simulation time 202347565 ps
CPU time 0.83 seconds
Started Jun 24 05:23:47 PM PDT 24
Finished Jun 24 05:23:49 PM PDT 24
Peak memory 206352 kb
Host smart-f333f71d-4d9b-4826-993b-b151d8fd0237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79964
1857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.799641857
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3473200602
Short name T924
Test name
Test status
Simulation time 154612857 ps
CPU time 0.74 seconds
Started Jun 24 05:23:49 PM PDT 24
Finished Jun 24 05:23:52 PM PDT 24
Peak memory 206180 kb
Host smart-240273de-a12f-465c-a6b8-7047061ed400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34732
00602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3473200602
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2992418740
Short name T2249
Test name
Test status
Simulation time 198586171 ps
CPU time 0.87 seconds
Started Jun 24 05:23:40 PM PDT 24
Finished Jun 24 05:23:43 PM PDT 24
Peak memory 206168 kb
Host smart-b1dff78d-19d7-4205-9546-cae176122878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29924
18740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2992418740
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.489311390
Short name T2149
Test name
Test status
Simulation time 13108033735 ps
CPU time 368.57 seconds
Started Jun 24 05:23:39 PM PDT 24
Finished Jun 24 05:29:50 PM PDT 24
Peak memory 206384 kb
Host smart-da5f2786-bf00-4f21-bbe7-587f4d39ee6a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=489311390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.489311390
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3230002805
Short name T936
Test name
Test status
Simulation time 227743020 ps
CPU time 0.9 seconds
Started Jun 24 05:23:38 PM PDT 24
Finished Jun 24 05:23:41 PM PDT 24
Peak memory 206184 kb
Host smart-327e78fc-e836-4f98-8b37-35ec4a9ab53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32300
02805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3230002805
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.2696984374
Short name T2164
Test name
Test status
Simulation time 23283797923 ps
CPU time 22.94 seconds
Started Jun 24 05:23:35 PM PDT 24
Finished Jun 24 05:24:01 PM PDT 24
Peak memory 206224 kb
Host smart-a4f9c013-8420-47a0-bb3a-0059a5c6f42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26969
84374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.2696984374
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2790226409
Short name T2255
Test name
Test status
Simulation time 3312509066 ps
CPU time 3.72 seconds
Started Jun 24 05:23:40 PM PDT 24
Finished Jun 24 05:23:46 PM PDT 24
Peak memory 206240 kb
Host smart-94d1b6b7-0ffe-4348-9248-bf71a5e23d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27902
26409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2790226409
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.3951059882
Short name T2146
Test name
Test status
Simulation time 4207459528 ps
CPU time 40.08 seconds
Started Jun 24 05:23:36 PM PDT 24
Finished Jun 24 05:24:18 PM PDT 24
Peak memory 206280 kb
Host smart-f283ee10-4141-47f4-95fc-c5d3de4e4224
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3951059882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.3951059882
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.733089160
Short name T1341
Test name
Test status
Simulation time 256214418 ps
CPU time 0.92 seconds
Started Jun 24 05:23:47 PM PDT 24
Finished Jun 24 05:23:49 PM PDT 24
Peak memory 206156 kb
Host smart-bc372d99-b863-4653-9035-3cd8f227e073
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=733089160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.733089160
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.3940112592
Short name T2324
Test name
Test status
Simulation time 187899437 ps
CPU time 0.86 seconds
Started Jun 24 05:23:38 PM PDT 24
Finished Jun 24 05:23:41 PM PDT 24
Peak memory 206068 kb
Host smart-161d8e8c-75f7-4730-bd41-a2ae98a2ed4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39401
12592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.3940112592
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.185772263
Short name T1080
Test name
Test status
Simulation time 9618813066 ps
CPU time 263.22 seconds
Started Jun 24 05:23:39 PM PDT 24
Finished Jun 24 05:28:04 PM PDT 24
Peak memory 206340 kb
Host smart-fba0d896-824b-452e-a525-37ca21b9166d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18577
2263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.185772263
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.2195510831
Short name T490
Test name
Test status
Simulation time 6696742133 ps
CPU time 49.75 seconds
Started Jun 24 05:23:38 PM PDT 24
Finished Jun 24 05:24:30 PM PDT 24
Peak memory 206360 kb
Host smart-43297172-af91-4bdc-a224-e7f568b55d26
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2195510831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.2195510831
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1303479114
Short name T2125
Test name
Test status
Simulation time 167697032 ps
CPU time 0.81 seconds
Started Jun 24 05:23:47 PM PDT 24
Finished Jun 24 05:23:50 PM PDT 24
Peak memory 206084 kb
Host smart-8c46dd46-c51f-4fda-aaae-372a239e6712
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1303479114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1303479114
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1431588764
Short name T1949
Test name
Test status
Simulation time 150412170 ps
CPU time 0.78 seconds
Started Jun 24 05:23:37 PM PDT 24
Finished Jun 24 05:23:39 PM PDT 24
Peak memory 206180 kb
Host smart-f3dccbff-110a-401e-a53b-71ffe0e6f1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14315
88764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1431588764
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2292793886
Short name T994
Test name
Test status
Simulation time 201545915 ps
CPU time 0.87 seconds
Started Jun 24 05:23:44 PM PDT 24
Finished Jun 24 05:23:46 PM PDT 24
Peak memory 206192 kb
Host smart-f3aec871-c628-46c2-9b8f-7500102c0848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22927
93886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2292793886
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1816008320
Short name T650
Test name
Test status
Simulation time 198648573 ps
CPU time 0.83 seconds
Started Jun 24 05:23:38 PM PDT 24
Finished Jun 24 05:23:41 PM PDT 24
Peak memory 206176 kb
Host smart-9c6e6505-9d6b-4a5b-b3d0-62393e1c6518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18160
08320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1816008320
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.242017987
Short name T869
Test name
Test status
Simulation time 184172280 ps
CPU time 0.85 seconds
Started Jun 24 05:23:37 PM PDT 24
Finished Jun 24 05:23:39 PM PDT 24
Peak memory 206096 kb
Host smart-ffdac678-ec8a-4dd7-a300-1fbf133260f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24201
7987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.242017987
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2566032034
Short name T2514
Test name
Test status
Simulation time 146416391 ps
CPU time 0.79 seconds
Started Jun 24 05:23:40 PM PDT 24
Finished Jun 24 05:23:43 PM PDT 24
Peak memory 206180 kb
Host smart-662cdd0f-d1f3-4bf2-9ad8-10010680b525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25660
32034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2566032034
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.2016915615
Short name T80
Test name
Test status
Simulation time 205237049 ps
CPU time 0.87 seconds
Started Jun 24 05:23:44 PM PDT 24
Finished Jun 24 05:23:46 PM PDT 24
Peak memory 206176 kb
Host smart-cf275416-fa66-402e-b982-4cb181f6af8d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2016915615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.2016915615
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1192133516
Short name T241
Test name
Test status
Simulation time 148879111 ps
CPU time 0.81 seconds
Started Jun 24 05:23:44 PM PDT 24
Finished Jun 24 05:23:46 PM PDT 24
Peak memory 206176 kb
Host smart-755ac5df-9d7f-4410-af4e-a4dc088b6371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11921
33516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1192133516
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3691966849
Short name T2496
Test name
Test status
Simulation time 47959365 ps
CPU time 0.65 seconds
Started Jun 24 05:23:49 PM PDT 24
Finished Jun 24 05:23:52 PM PDT 24
Peak memory 206184 kb
Host smart-f3695093-d804-4c1c-9ff2-e2f19b26a723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36919
66849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3691966849
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3167861513
Short name T1619
Test name
Test status
Simulation time 14525664869 ps
CPU time 30.88 seconds
Started Jun 24 05:23:38 PM PDT 24
Finished Jun 24 05:24:10 PM PDT 24
Peak memory 206256 kb
Host smart-8703c2d6-8102-4ddb-b8e0-72316eedcfe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31678
61513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3167861513
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.388681956
Short name T965
Test name
Test status
Simulation time 176292090 ps
CPU time 0.8 seconds
Started Jun 24 05:23:40 PM PDT 24
Finished Jun 24 05:23:43 PM PDT 24
Peak memory 206076 kb
Host smart-a5c4c95c-366a-4afd-a0ed-0741178dd004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38868
1956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.388681956
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1683920104
Short name T367
Test name
Test status
Simulation time 194574526 ps
CPU time 0.85 seconds
Started Jun 24 05:23:40 PM PDT 24
Finished Jun 24 05:23:43 PM PDT 24
Peak memory 206184 kb
Host smart-09834244-ceb8-46e9-a977-637e6e536818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16839
20104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1683920104
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.187337611
Short name T888
Test name
Test status
Simulation time 171963146 ps
CPU time 0.82 seconds
Started Jun 24 05:23:46 PM PDT 24
Finished Jun 24 05:23:48 PM PDT 24
Peak memory 206196 kb
Host smart-341756a9-5d34-4879-9958-0e89a39d8772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18733
7611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.187337611
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.3936949028
Short name T1942
Test name
Test status
Simulation time 152571604 ps
CPU time 0.78 seconds
Started Jun 24 05:23:38 PM PDT 24
Finished Jun 24 05:23:40 PM PDT 24
Peak memory 206200 kb
Host smart-a03ea690-cfba-4842-9f85-ab7486ed0ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39369
49028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.3936949028
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1217725679
Short name T842
Test name
Test status
Simulation time 156203466 ps
CPU time 0.76 seconds
Started Jun 24 05:23:40 PM PDT 24
Finished Jun 24 05:23:43 PM PDT 24
Peak memory 206148 kb
Host smart-2b45e121-33d7-42fb-a121-8ee4c585c776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12177
25679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1217725679
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1567055070
Short name T358
Test name
Test status
Simulation time 167531168 ps
CPU time 0.78 seconds
Started Jun 24 05:23:39 PM PDT 24
Finished Jun 24 05:23:42 PM PDT 24
Peak memory 206172 kb
Host smart-aea221c1-f5e2-4096-bfb1-25ff035a8080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15670
55070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1567055070
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3784378853
Short name T2021
Test name
Test status
Simulation time 238752914 ps
CPU time 0.92 seconds
Started Jun 24 05:23:39 PM PDT 24
Finished Jun 24 05:23:42 PM PDT 24
Peak memory 206188 kb
Host smart-5dfc346f-c3af-45bf-b2e0-74be3623eea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37843
78853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3784378853
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1150672922
Short name T1693
Test name
Test status
Simulation time 4258975668 ps
CPU time 118.64 seconds
Started Jun 24 05:23:38 PM PDT 24
Finished Jun 24 05:25:38 PM PDT 24
Peak memory 206340 kb
Host smart-fbe78c8b-81d7-47d0-bbe9-ace06d3f9980
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1150672922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1150672922
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.26068606
Short name T2435
Test name
Test status
Simulation time 232698202 ps
CPU time 0.92 seconds
Started Jun 24 05:23:38 PM PDT 24
Finished Jun 24 05:23:40 PM PDT 24
Peak memory 206196 kb
Host smart-897164c4-7a85-4b25-a0da-363e3197797b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26068
606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.26068606
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3211098556
Short name T1575
Test name
Test status
Simulation time 145780823 ps
CPU time 0.77 seconds
Started Jun 24 05:23:39 PM PDT 24
Finished Jun 24 05:23:42 PM PDT 24
Peak memory 206152 kb
Host smart-41ae60e9-b184-43aa-ae9c-c7962443f5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32110
98556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3211098556
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.416240618
Short name T1922
Test name
Test status
Simulation time 4793297551 ps
CPU time 46.24 seconds
Started Jun 24 05:23:41 PM PDT 24
Finished Jun 24 05:24:29 PM PDT 24
Peak memory 206344 kb
Host smart-0a52ba22-330a-428a-9e48-02a9703911d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41624
0618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.416240618
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.1750932076
Short name T1066
Test name
Test status
Simulation time 3482898818 ps
CPU time 4.03 seconds
Started Jun 24 05:23:45 PM PDT 24
Finished Jun 24 05:23:50 PM PDT 24
Peak memory 206240 kb
Host smart-f4898cbb-13ce-4835-ad29-fa5b61b2c06d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1750932076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.1750932076
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.1104899376
Short name T668
Test name
Test status
Simulation time 13388398268 ps
CPU time 14.02 seconds
Started Jun 24 05:23:47 PM PDT 24
Finished Jun 24 05:24:03 PM PDT 24
Peak memory 206348 kb
Host smart-ac4a567c-5b8f-41ec-bbb9-c95d569198d8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1104899376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.1104899376
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2625753413
Short name T2104
Test name
Test status
Simulation time 23494310517 ps
CPU time 22.34 seconds
Started Jun 24 05:23:48 PM PDT 24
Finished Jun 24 05:24:12 PM PDT 24
Peak memory 206236 kb
Host smart-c26672bc-9601-4718-a2d9-e3e614f382eb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2625753413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.2625753413
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2556628742
Short name T1476
Test name
Test status
Simulation time 185496781 ps
CPU time 0.9 seconds
Started Jun 24 05:23:47 PM PDT 24
Finished Jun 24 05:23:49 PM PDT 24
Peak memory 206180 kb
Host smart-ac96d48d-3fdf-4c98-99ec-29e675df8466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25566
28742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2556628742
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.768873632
Short name T1455
Test name
Test status
Simulation time 143360989 ps
CPU time 0.76 seconds
Started Jun 24 05:23:45 PM PDT 24
Finished Jun 24 05:23:47 PM PDT 24
Peak memory 206180 kb
Host smart-5e13c1e0-e738-4732-a037-b922becbe2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76887
3632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.768873632
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.4286802272
Short name T2339
Test name
Test status
Simulation time 612554927 ps
CPU time 1.78 seconds
Started Jun 24 05:23:46 PM PDT 24
Finished Jun 24 05:23:49 PM PDT 24
Peak memory 206248 kb
Host smart-9ea08c82-a921-4afb-9c15-2970b46317eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42868
02272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.4286802272
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3005928793
Short name T194
Test name
Test status
Simulation time 1303658718 ps
CPU time 2.83 seconds
Started Jun 24 05:23:47 PM PDT 24
Finished Jun 24 05:23:51 PM PDT 24
Peak memory 206228 kb
Host smart-3509cd45-d6f6-409d-a97f-3a28df9fd4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30059
28793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3005928793
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.401757579
Short name T1173
Test name
Test status
Simulation time 12407694530 ps
CPU time 22.37 seconds
Started Jun 24 05:23:49 PM PDT 24
Finished Jun 24 05:24:13 PM PDT 24
Peak memory 206328 kb
Host smart-de37249f-8db7-44ac-8779-bbc8489ab92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40175
7579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.401757579
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.2942380802
Short name T1608
Test name
Test status
Simulation time 448619921 ps
CPU time 1.47 seconds
Started Jun 24 05:23:48 PM PDT 24
Finished Jun 24 05:23:52 PM PDT 24
Peak memory 206080 kb
Host smart-ea6eec7c-0f15-4d6f-991c-3e5bab561406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29423
80802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.2942380802
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.562536283
Short name T1872
Test name
Test status
Simulation time 205380690 ps
CPU time 0.8 seconds
Started Jun 24 05:23:52 PM PDT 24
Finished Jun 24 05:23:53 PM PDT 24
Peak memory 206076 kb
Host smart-3b2fa8e7-1f42-4bf7-8ea9-2b7b74b7cbdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56253
6283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.562536283
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.3597508407
Short name T2027
Test name
Test status
Simulation time 38827914 ps
CPU time 0.66 seconds
Started Jun 24 05:23:48 PM PDT 24
Finished Jun 24 05:23:51 PM PDT 24
Peak memory 206048 kb
Host smart-e41099fd-ccfb-4de3-99cf-c39241f7e176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35975
08407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3597508407
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3364202909
Short name T1650
Test name
Test status
Simulation time 918655567 ps
CPU time 2.18 seconds
Started Jun 24 05:23:48 PM PDT 24
Finished Jun 24 05:23:53 PM PDT 24
Peak memory 206260 kb
Host smart-0a333890-be8e-49b7-ad2a-a161bfbbe265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33642
02909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3364202909
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1366372970
Short name T2424
Test name
Test status
Simulation time 338097733 ps
CPU time 2.02 seconds
Started Jun 24 05:23:48 PM PDT 24
Finished Jun 24 05:23:51 PM PDT 24
Peak memory 206480 kb
Host smart-e6cacd67-72ad-4823-9ee3-f56ab1b6a8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13663
72970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1366372970
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.193098413
Short name T1651
Test name
Test status
Simulation time 225155659 ps
CPU time 0.92 seconds
Started Jun 24 05:23:55 PM PDT 24
Finished Jun 24 05:23:58 PM PDT 24
Peak memory 206092 kb
Host smart-d599cbb0-e11d-4f77-9a78-903207e85e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19309
8413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.193098413
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2575117522
Short name T511
Test name
Test status
Simulation time 159665915 ps
CPU time 0.81 seconds
Started Jun 24 05:23:53 PM PDT 24
Finished Jun 24 05:23:55 PM PDT 24
Peak memory 206112 kb
Host smart-5b14863a-caea-45c8-a1ba-3ea56198c298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25751
17522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2575117522
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3767085258
Short name T704
Test name
Test status
Simulation time 204379192 ps
CPU time 0.88 seconds
Started Jun 24 05:23:48 PM PDT 24
Finished Jun 24 05:23:51 PM PDT 24
Peak memory 206192 kb
Host smart-965b87dd-c73a-4af5-912d-1c2f74ea406f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37670
85258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3767085258
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.1963194699
Short name T1995
Test name
Test status
Simulation time 14938256933 ps
CPU time 106.67 seconds
Started Jun 24 05:23:46 PM PDT 24
Finished Jun 24 05:25:34 PM PDT 24
Peak memory 206372 kb
Host smart-d8f2182f-e4b4-4212-a5fd-db5f35ea22f0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1963194699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.1963194699
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3550605617
Short name T2406
Test name
Test status
Simulation time 232907577 ps
CPU time 0.93 seconds
Started Jun 24 05:23:49 PM PDT 24
Finished Jun 24 05:23:52 PM PDT 24
Peak memory 206192 kb
Host smart-0ffe43f0-8f28-42c7-b7ec-a6be4fc19035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35506
05617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3550605617
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.811986231
Short name T353
Test name
Test status
Simulation time 23320359044 ps
CPU time 27.77 seconds
Started Jun 24 05:23:48 PM PDT 24
Finished Jun 24 05:24:18 PM PDT 24
Peak memory 206252 kb
Host smart-820b1dfe-1c2f-4d4b-ba57-9e7eb09d3ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81198
6231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.811986231
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.2374343881
Short name T566
Test name
Test status
Simulation time 3342208881 ps
CPU time 4.17 seconds
Started Jun 24 05:23:47 PM PDT 24
Finished Jun 24 05:23:53 PM PDT 24
Peak memory 206468 kb
Host smart-c4314526-6e73-47d1-a369-f25b6fc75cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23743
43881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.2374343881
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.1323193155
Short name T670
Test name
Test status
Simulation time 4272868014 ps
CPU time 30.22 seconds
Started Jun 24 05:23:46 PM PDT 24
Finished Jun 24 05:24:17 PM PDT 24
Peak memory 206252 kb
Host smart-79c2a8c6-9940-43be-8ef1-7242e5202dd5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1323193155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.1323193155
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.2438548538
Short name T2364
Test name
Test status
Simulation time 242192710 ps
CPU time 0.9 seconds
Started Jun 24 05:23:54 PM PDT 24
Finished Jun 24 05:23:56 PM PDT 24
Peak memory 206196 kb
Host smart-01d8bf8c-504d-46be-a751-e7f9996c6ae9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2438548538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.2438548538
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3225323408
Short name T1739
Test name
Test status
Simulation time 190055210 ps
CPU time 0.84 seconds
Started Jun 24 05:23:48 PM PDT 24
Finished Jun 24 05:23:52 PM PDT 24
Peak memory 206180 kb
Host smart-3857d53e-a8b1-4063-bf2c-90b73b36ebba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32253
23408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3225323408
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.4257348795
Short name T1506
Test name
Test status
Simulation time 5115345996 ps
CPU time 48.35 seconds
Started Jun 24 05:23:51 PM PDT 24
Finished Jun 24 05:24:41 PM PDT 24
Peak memory 206268 kb
Host smart-ae547268-d877-4a42-85b6-b053eb494623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42573
48795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.4257348795
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1504297535
Short name T892
Test name
Test status
Simulation time 10137000736 ps
CPU time 71.08 seconds
Started Jun 24 05:23:48 PM PDT 24
Finished Jun 24 05:25:01 PM PDT 24
Peak memory 206528 kb
Host smart-30ae4e2b-d550-4b86-9796-5cecaef61d58
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1504297535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1504297535
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1181109914
Short name T1940
Test name
Test status
Simulation time 164798348 ps
CPU time 0.82 seconds
Started Jun 24 05:24:06 PM PDT 24
Finished Jun 24 05:24:09 PM PDT 24
Peak memory 206152 kb
Host smart-f8fce968-3ed5-4f58-8fff-461b97a7d745
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1181109914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1181109914
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.433996530
Short name T457
Test name
Test status
Simulation time 151309421 ps
CPU time 0.79 seconds
Started Jun 24 05:23:46 PM PDT 24
Finished Jun 24 05:23:48 PM PDT 24
Peak memory 206076 kb
Host smart-36862b62-ce5e-471a-b7a1-56732e5d29cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43399
6530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.433996530
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.628047915
Short name T482
Test name
Test status
Simulation time 157939549 ps
CPU time 0.77 seconds
Started Jun 24 05:23:46 PM PDT 24
Finished Jun 24 05:23:48 PM PDT 24
Peak memory 206160 kb
Host smart-34534287-4b0d-4221-b469-78fcdbc4d48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62804
7915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.628047915
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.4026402887
Short name T449
Test name
Test status
Simulation time 197317515 ps
CPU time 0.79 seconds
Started Jun 24 05:23:48 PM PDT 24
Finished Jun 24 05:23:51 PM PDT 24
Peak memory 206136 kb
Host smart-3f7cc92f-d79f-47f5-95db-3ce9986f5c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40264
02887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.4026402887
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3310296496
Short name T2367
Test name
Test status
Simulation time 188014234 ps
CPU time 0.84 seconds
Started Jun 24 05:23:47 PM PDT 24
Finished Jun 24 05:23:50 PM PDT 24
Peak memory 206192 kb
Host smart-b129411d-66d6-4744-8588-78e489836eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33102
96496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3310296496
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2036248492
Short name T962
Test name
Test status
Simulation time 145622244 ps
CPU time 0.77 seconds
Started Jun 24 05:23:54 PM PDT 24
Finished Jun 24 05:23:56 PM PDT 24
Peak memory 206064 kb
Host smart-99335654-3c0c-4df3-8484-34212938ea05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20362
48492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2036248492
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.1291163507
Short name T521
Test name
Test status
Simulation time 218466913 ps
CPU time 0.9 seconds
Started Jun 24 05:23:48 PM PDT 24
Finished Jun 24 05:23:51 PM PDT 24
Peak memory 206176 kb
Host smart-1c5a401d-4178-4219-bf1f-1176840843b0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1291163507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.1291163507
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.978568559
Short name T2400
Test name
Test status
Simulation time 150529890 ps
CPU time 0.83 seconds
Started Jun 24 05:23:48 PM PDT 24
Finished Jun 24 05:23:51 PM PDT 24
Peak memory 206092 kb
Host smart-de6a2e0c-8e5b-4d02-a925-86707ffab265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97856
8559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.978568559
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.4052226615
Short name T1177
Test name
Test status
Simulation time 45560116 ps
CPU time 0.66 seconds
Started Jun 24 05:23:56 PM PDT 24
Finished Jun 24 05:23:58 PM PDT 24
Peak memory 206172 kb
Host smart-908bfe6c-c8a2-4eb6-ba12-7cc3d170e826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40522
26615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.4052226615
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.834074946
Short name T81
Test name
Test status
Simulation time 8965601402 ps
CPU time 19.98 seconds
Started Jun 24 05:23:48 PM PDT 24
Finished Jun 24 05:24:10 PM PDT 24
Peak memory 206436 kb
Host smart-a6094746-bdba-4eb3-94b0-506b96affc40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83407
4946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.834074946
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.148536389
Short name T397
Test name
Test status
Simulation time 176225873 ps
CPU time 0.86 seconds
Started Jun 24 05:23:46 PM PDT 24
Finished Jun 24 05:23:48 PM PDT 24
Peak memory 206160 kb
Host smart-69e0a830-3cd1-49b5-a623-f6a76bef7dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14853
6389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.148536389
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3766572680
Short name T1809
Test name
Test status
Simulation time 170594856 ps
CPU time 0.88 seconds
Started Jun 24 05:23:54 PM PDT 24
Finished Jun 24 05:23:56 PM PDT 24
Peak memory 206168 kb
Host smart-62fea54f-019d-498f-989e-789e713bb19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37665
72680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3766572680
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.3488475108
Short name T335
Test name
Test status
Simulation time 187329595 ps
CPU time 0.82 seconds
Started Jun 24 05:23:52 PM PDT 24
Finished Jun 24 05:23:54 PM PDT 24
Peak memory 206196 kb
Host smart-8e8bec5a-629b-4377-a82f-475980d3ace4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34884
75108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.3488475108
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.1210981681
Short name T1774
Test name
Test status
Simulation time 153187396 ps
CPU time 0.78 seconds
Started Jun 24 05:23:56 PM PDT 24
Finished Jun 24 05:23:59 PM PDT 24
Peak memory 206200 kb
Host smart-cd65fa3c-4d33-41ce-8b9d-68e5356aaffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12109
81681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.1210981681
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2262806972
Short name T95
Test name
Test status
Simulation time 193435058 ps
CPU time 0.88 seconds
Started Jun 24 05:23:54 PM PDT 24
Finished Jun 24 05:23:56 PM PDT 24
Peak memory 206188 kb
Host smart-d3cb3391-9643-4b87-b7e0-ff8b724d2530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22628
06972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2262806972
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2748174794
Short name T1031
Test name
Test status
Simulation time 156569983 ps
CPU time 0.77 seconds
Started Jun 24 05:23:57 PM PDT 24
Finished Jun 24 05:23:59 PM PDT 24
Peak memory 206188 kb
Host smart-40df5aac-1038-45b6-ac4e-8750b273b33f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27481
74794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2748174794
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2284392026
Short name T646
Test name
Test status
Simulation time 171680587 ps
CPU time 0.79 seconds
Started Jun 24 05:23:53 PM PDT 24
Finished Jun 24 05:23:55 PM PDT 24
Peak memory 206152 kb
Host smart-4bcdabe2-96d2-4c67-a7be-593387b85be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22843
92026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2284392026
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.329606820
Short name T1202
Test name
Test status
Simulation time 281912050 ps
CPU time 0.95 seconds
Started Jun 24 05:23:53 PM PDT 24
Finished Jun 24 05:23:55 PM PDT 24
Peak memory 206120 kb
Host smart-5f812175-aadf-49da-b9c7-ad98744e0cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32960
6820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.329606820
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.3081037586
Short name T2222
Test name
Test status
Simulation time 10365920882 ps
CPU time 94.81 seconds
Started Jun 24 05:23:56 PM PDT 24
Finished Jun 24 05:25:33 PM PDT 24
Peak memory 206392 kb
Host smart-6edbdc9d-8b55-4db1-ba7a-240205e6c9f9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3081037586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.3081037586
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.339298211
Short name T1793
Test name
Test status
Simulation time 186704780 ps
CPU time 0.82 seconds
Started Jun 24 05:23:59 PM PDT 24
Finished Jun 24 05:24:00 PM PDT 24
Peak memory 206128 kb
Host smart-a71d474a-f423-4dd4-aae8-c66d708fbbaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33929
8211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.339298211
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.699567564
Short name T627
Test name
Test status
Simulation time 178986394 ps
CPU time 0.77 seconds
Started Jun 24 05:23:59 PM PDT 24
Finished Jun 24 05:24:01 PM PDT 24
Peak memory 206020 kb
Host smart-2e3ccf36-f0e9-47ec-a33a-2261f2e3b9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69956
7564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.699567564
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.1884915687
Short name T973
Test name
Test status
Simulation time 6630105263 ps
CPU time 50.65 seconds
Started Jun 24 05:23:54 PM PDT 24
Finished Jun 24 05:24:46 PM PDT 24
Peak memory 206324 kb
Host smart-a592304b-b4ea-4532-bea2-bc1b59e9b236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18849
15687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.1884915687
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.3741220753
Short name T1109
Test name
Test status
Simulation time 4050871179 ps
CPU time 4.66 seconds
Started Jun 24 05:23:54 PM PDT 24
Finished Jun 24 05:24:00 PM PDT 24
Peak memory 206224 kb
Host smart-eef5191a-694c-46c8-9bc9-ca6d12634580
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3741220753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.3741220753
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3497002604
Short name T617
Test name
Test status
Simulation time 13320721107 ps
CPU time 12.33 seconds
Started Jun 24 05:23:56 PM PDT 24
Finished Jun 24 05:24:10 PM PDT 24
Peak memory 206388 kb
Host smart-fe4f3a5d-3aee-450d-b7bf-07642d97c4cb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3497002604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3497002604
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.845891022
Short name T1504
Test name
Test status
Simulation time 23323026788 ps
CPU time 22.99 seconds
Started Jun 24 05:23:55 PM PDT 24
Finished Jun 24 05:24:20 PM PDT 24
Peak memory 206244 kb
Host smart-7b48d351-cf39-4061-a50d-7a812485631d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=845891022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.845891022
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.2349828254
Short name T635
Test name
Test status
Simulation time 208574239 ps
CPU time 0.9 seconds
Started Jun 24 05:23:54 PM PDT 24
Finished Jun 24 05:23:56 PM PDT 24
Peak memory 206100 kb
Host smart-af0765e8-5670-43e5-9850-34ce04cdd54a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23498
28254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2349828254
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.1010651426
Short name T1290
Test name
Test status
Simulation time 148762726 ps
CPU time 0.77 seconds
Started Jun 24 05:23:59 PM PDT 24
Finished Jun 24 05:24:00 PM PDT 24
Peak memory 206124 kb
Host smart-cbc01e92-e1c8-46f8-afd9-984a795efbd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10106
51426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.1010651426
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.3243835401
Short name T113
Test name
Test status
Simulation time 329796562 ps
CPU time 1.16 seconds
Started Jun 24 05:23:54 PM PDT 24
Finished Jun 24 05:23:57 PM PDT 24
Peak memory 206176 kb
Host smart-a5f2a002-c9a2-4165-a45d-e60e021ef216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32438
35401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.3243835401
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.1894070551
Short name T2280
Test name
Test status
Simulation time 542464735 ps
CPU time 1.35 seconds
Started Jun 24 05:23:55 PM PDT 24
Finished Jun 24 05:23:58 PM PDT 24
Peak memory 206092 kb
Host smart-b49c8a7d-1298-471e-a8af-5e62c7980646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18940
70551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.1894070551
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.1068810158
Short name T2189
Test name
Test status
Simulation time 20168288683 ps
CPU time 36.98 seconds
Started Jun 24 05:24:06 PM PDT 24
Finished Jun 24 05:24:45 PM PDT 24
Peak memory 206324 kb
Host smart-b201eb3b-f284-494d-b162-ca3713ed7f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10688
10158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.1068810158
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2588107809
Short name T1502
Test name
Test status
Simulation time 353564878 ps
CPU time 1.17 seconds
Started Jun 24 05:24:06 PM PDT 24
Finished Jun 24 05:24:09 PM PDT 24
Peak memory 206136 kb
Host smart-a9b8466b-7a72-4f12-ad6e-9f9818a6ca27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25881
07809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2588107809
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.2282899097
Short name T811
Test name
Test status
Simulation time 137860038 ps
CPU time 0.77 seconds
Started Jun 24 05:23:53 PM PDT 24
Finished Jun 24 05:23:54 PM PDT 24
Peak memory 206168 kb
Host smart-86645beb-a526-45f3-80c6-4111d104bd9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22828
99097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2282899097
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.3957656079
Short name T734
Test name
Test status
Simulation time 38871130 ps
CPU time 0.63 seconds
Started Jun 24 05:24:05 PM PDT 24
Finished Jun 24 05:24:08 PM PDT 24
Peak memory 206124 kb
Host smart-e20f1517-82e0-49da-a791-6e231ac448dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39576
56079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3957656079
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3573078640
Short name T763
Test name
Test status
Simulation time 780822043 ps
CPU time 2.03 seconds
Started Jun 24 05:23:59 PM PDT 24
Finished Jun 24 05:24:01 PM PDT 24
Peak memory 206292 kb
Host smart-24d1f538-2d9b-4222-850f-8086270c1c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35730
78640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3573078640
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.854622952
Short name T684
Test name
Test status
Simulation time 256339643 ps
CPU time 1.51 seconds
Started Jun 24 05:24:05 PM PDT 24
Finished Jun 24 05:24:08 PM PDT 24
Peak memory 206224 kb
Host smart-38fd9149-bf2e-4f7d-862b-8e095da1c543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85462
2952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.854622952
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1105069427
Short name T814
Test name
Test status
Simulation time 159580926 ps
CPU time 0.8 seconds
Started Jun 24 05:24:00 PM PDT 24
Finished Jun 24 05:24:02 PM PDT 24
Peak memory 206176 kb
Host smart-cde70c84-47d0-460c-99eb-812ffffdefde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11050
69427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1105069427
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2519769989
Short name T1723
Test name
Test status
Simulation time 153484632 ps
CPU time 0.79 seconds
Started Jun 24 05:24:02 PM PDT 24
Finished Jun 24 05:24:05 PM PDT 24
Peak memory 206192 kb
Host smart-40436899-c467-4e40-93b9-059baf31c95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25197
69989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2519769989
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1470949325
Short name T2087
Test name
Test status
Simulation time 226805787 ps
CPU time 0.94 seconds
Started Jun 24 05:23:55 PM PDT 24
Finished Jun 24 05:23:58 PM PDT 24
Peak memory 206116 kb
Host smart-6b0806ca-21bd-479c-a524-be7d7e952949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14709
49325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1470949325
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.2869080072
Short name T741
Test name
Test status
Simulation time 9083935075 ps
CPU time 67.52 seconds
Started Jun 24 05:23:54 PM PDT 24
Finished Jun 24 05:25:02 PM PDT 24
Peak memory 206300 kb
Host smart-2f8d9cf7-b02d-48c3-ad4f-4f85f67ab8ba
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2869080072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.2869080072
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.1879640410
Short name T920
Test name
Test status
Simulation time 207446911 ps
CPU time 0.88 seconds
Started Jun 24 05:23:54 PM PDT 24
Finished Jun 24 05:23:56 PM PDT 24
Peak memory 206176 kb
Host smart-2a3b467f-62d0-45c8-8d7a-8a80bf6cc71e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18796
40410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.1879640410
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.592374058
Short name T443
Test name
Test status
Simulation time 23304497380 ps
CPU time 20.69 seconds
Started Jun 24 05:23:55 PM PDT 24
Finished Jun 24 05:24:18 PM PDT 24
Peak memory 206240 kb
Host smart-b7eff07b-6770-4a8c-864d-e949339c17a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59237
4058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.592374058
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2626440275
Short name T364
Test name
Test status
Simulation time 3265960783 ps
CPU time 3.66 seconds
Started Jun 24 05:23:59 PM PDT 24
Finished Jun 24 05:24:04 PM PDT 24
Peak memory 206192 kb
Host smart-5f2c5f59-4dc0-4927-b874-943d173d847a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26264
40275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2626440275
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.1915267056
Short name T523
Test name
Test status
Simulation time 10615358161 ps
CPU time 99.24 seconds
Started Jun 24 05:23:52 PM PDT 24
Finished Jun 24 05:25:32 PM PDT 24
Peak memory 206424 kb
Host smart-3e9f3bbd-f6ee-4e3e-989b-f4b1f387fcb4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1915267056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.1915267056
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.431876315
Short name T1883
Test name
Test status
Simulation time 242643640 ps
CPU time 0.91 seconds
Started Jun 24 05:24:03 PM PDT 24
Finished Jun 24 05:24:06 PM PDT 24
Peak memory 206076 kb
Host smart-f1879fbb-434d-4e6f-9d8c-a0b5ada696bb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=431876315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.431876315
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1423123012
Short name T1545
Test name
Test status
Simulation time 189342738 ps
CPU time 0.85 seconds
Started Jun 24 05:23:56 PM PDT 24
Finished Jun 24 05:23:58 PM PDT 24
Peak memory 206172 kb
Host smart-6cd11218-ba64-4d54-8b8b-5b39dde104a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14231
23012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1423123012
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.2877628892
Short name T1335
Test name
Test status
Simulation time 9567275892 ps
CPU time 264.67 seconds
Started Jun 24 05:23:59 PM PDT 24
Finished Jun 24 05:28:25 PM PDT 24
Peak memory 206280 kb
Host smart-77cf946e-2308-48d8-8e8f-1b99098894e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28776
28892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.2877628892
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.931927724
Short name T1490
Test name
Test status
Simulation time 4931633584 ps
CPU time 136.83 seconds
Started Jun 24 05:24:06 PM PDT 24
Finished Jun 24 05:26:25 PM PDT 24
Peak memory 206348 kb
Host smart-038c9e21-7ded-4193-b42e-afae560ccb60
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=931927724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.931927724
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.2908080350
Short name T498
Test name
Test status
Simulation time 161975758 ps
CPU time 0.81 seconds
Started Jun 24 05:24:02 PM PDT 24
Finished Jun 24 05:24:05 PM PDT 24
Peak memory 206180 kb
Host smart-7a44f813-405a-4b8e-888b-1534076f4649
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2908080350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.2908080350
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.207368782
Short name T1314
Test name
Test status
Simulation time 147732071 ps
CPU time 0.77 seconds
Started Jun 24 05:24:06 PM PDT 24
Finished Jun 24 05:24:09 PM PDT 24
Peak memory 206152 kb
Host smart-d21283ee-3705-4c03-beb8-2e0d60377062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20736
8782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.207368782
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1308169467
Short name T147
Test name
Test status
Simulation time 201022859 ps
CPU time 0.9 seconds
Started Jun 24 05:23:55 PM PDT 24
Finished Jun 24 05:23:57 PM PDT 24
Peak memory 206104 kb
Host smart-2d0963ee-7988-4edf-8dc8-9a9817b7138e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13081
69467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1308169467
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.694517312
Short name T1084
Test name
Test status
Simulation time 257564904 ps
CPU time 0.93 seconds
Started Jun 24 05:23:54 PM PDT 24
Finished Jun 24 05:23:56 PM PDT 24
Peak memory 206176 kb
Host smart-057b9946-693f-42eb-9dbc-1dd381ec3127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69451
7312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.694517312
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1645246364
Short name T393
Test name
Test status
Simulation time 167461487 ps
CPU time 0.75 seconds
Started Jun 24 05:24:05 PM PDT 24
Finished Jun 24 05:24:08 PM PDT 24
Peak memory 206136 kb
Host smart-442da562-10e8-4326-92e3-0c675de72091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16452
46364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1645246364
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3423586935
Short name T556
Test name
Test status
Simulation time 206301409 ps
CPU time 0.86 seconds
Started Jun 24 05:24:00 PM PDT 24
Finished Jun 24 05:24:02 PM PDT 24
Peak memory 206176 kb
Host smart-8a917329-63b3-4cd7-9dbc-e1da78b96aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34235
86935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3423586935
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3663170086
Short name T2067
Test name
Test status
Simulation time 147695981 ps
CPU time 0.8 seconds
Started Jun 24 05:24:04 PM PDT 24
Finished Jun 24 05:24:06 PM PDT 24
Peak memory 206096 kb
Host smart-70b609a2-ee43-4084-ba1e-e73f1d2b3039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36631
70086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3663170086
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.1130062377
Short name T1858
Test name
Test status
Simulation time 228798994 ps
CPU time 0.94 seconds
Started Jun 24 05:24:01 PM PDT 24
Finished Jun 24 05:24:03 PM PDT 24
Peak memory 206200 kb
Host smart-e222e680-c0be-4ee7-8879-5a0a63fa1ad6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1130062377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1130062377
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3804733279
Short name T1342
Test name
Test status
Simulation time 177892017 ps
CPU time 0.83 seconds
Started Jun 24 05:24:04 PM PDT 24
Finished Jun 24 05:24:06 PM PDT 24
Peak memory 206160 kb
Host smart-deb86c90-283b-4647-bc6d-515b1881435d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38047
33279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3804733279
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.2012715675
Short name T795
Test name
Test status
Simulation time 50402416 ps
CPU time 0.7 seconds
Started Jun 24 05:24:02 PM PDT 24
Finished Jun 24 05:24:04 PM PDT 24
Peak memory 206184 kb
Host smart-20b7cdc7-7199-486f-83e8-fc0ada5168b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20127
15675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2012715675
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.382003979
Short name T193
Test name
Test status
Simulation time 5316168694 ps
CPU time 11.87 seconds
Started Jun 24 05:24:06 PM PDT 24
Finished Jun 24 05:24:20 PM PDT 24
Peak memory 206360 kb
Host smart-e5f052fa-a04e-4be4-bfdd-9bf25356b287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38200
3979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.382003979
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1206525314
Short name T1337
Test name
Test status
Simulation time 185047429 ps
CPU time 0.83 seconds
Started Jun 24 05:24:03 PM PDT 24
Finished Jun 24 05:24:06 PM PDT 24
Peak memory 206152 kb
Host smart-0cd3ab09-2908-4c59-a41a-c1f93b6b8dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12065
25314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1206525314
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2761081035
Short name T2058
Test name
Test status
Simulation time 203519453 ps
CPU time 0.87 seconds
Started Jun 24 05:24:05 PM PDT 24
Finished Jun 24 05:24:07 PM PDT 24
Peak memory 206192 kb
Host smart-98901e52-18e4-4247-87cb-3c9b7dcf4440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27610
81035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2761081035
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.1493661825
Short name T1969
Test name
Test status
Simulation time 269933230 ps
CPU time 1.01 seconds
Started Jun 24 05:24:00 PM PDT 24
Finished Jun 24 05:24:02 PM PDT 24
Peak memory 206168 kb
Host smart-9b47605a-6217-43c7-b493-10fbfdc95e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14936
61825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.1493661825
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.505171341
Short name T2054
Test name
Test status
Simulation time 259830998 ps
CPU time 0.92 seconds
Started Jun 24 05:24:03 PM PDT 24
Finished Jun 24 05:24:06 PM PDT 24
Peak memory 206060 kb
Host smart-c81fdfc0-a72d-4ffb-a817-5dc7f5b3dfb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50517
1341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.505171341
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.3163777680
Short name T1094
Test name
Test status
Simulation time 160042202 ps
CPU time 0.8 seconds
Started Jun 24 05:24:02 PM PDT 24
Finished Jun 24 05:24:03 PM PDT 24
Peak memory 206180 kb
Host smart-bc7c349e-65d5-4c8b-b4c0-f87ff98dfe16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31637
77680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.3163777680
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.4124625918
Short name T1890
Test name
Test status
Simulation time 148189537 ps
CPU time 0.75 seconds
Started Jun 24 05:24:01 PM PDT 24
Finished Jun 24 05:24:03 PM PDT 24
Peak memory 206092 kb
Host smart-b9b70258-59b4-4b6b-a107-01141a8579ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41246
25918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.4124625918
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1494851491
Short name T1389
Test name
Test status
Simulation time 147253547 ps
CPU time 0.79 seconds
Started Jun 24 05:24:04 PM PDT 24
Finished Jun 24 05:24:06 PM PDT 24
Peak memory 206144 kb
Host smart-96017d43-9078-4e91-aa12-0192f441bf62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14948
51491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1494851491
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.4053059810
Short name T2468
Test name
Test status
Simulation time 202291366 ps
CPU time 0.88 seconds
Started Jun 24 05:24:02 PM PDT 24
Finished Jun 24 05:24:04 PM PDT 24
Peak memory 206168 kb
Host smart-34e46631-e08f-4912-83be-47558d3dc1f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40530
59810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.4053059810
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.2265620790
Short name T1040
Test name
Test status
Simulation time 7720434289 ps
CPU time 215.38 seconds
Started Jun 24 05:24:02 PM PDT 24
Finished Jun 24 05:27:40 PM PDT 24
Peak memory 206348 kb
Host smart-9707acd3-7362-4b8a-9436-54a3c6d5ca93
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2265620790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.2265620790
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2405759353
Short name T1948
Test name
Test status
Simulation time 206845999 ps
CPU time 0.84 seconds
Started Jun 24 05:24:03 PM PDT 24
Finished Jun 24 05:24:06 PM PDT 24
Peak memory 206060 kb
Host smart-0e7234b2-4001-4dea-b407-2b259c0965ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24057
59353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2405759353
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.3996029116
Short name T2447
Test name
Test status
Simulation time 232843043 ps
CPU time 0.88 seconds
Started Jun 24 05:24:06 PM PDT 24
Finished Jun 24 05:24:09 PM PDT 24
Peak memory 206192 kb
Host smart-69c66311-55f7-4e28-b6dc-54bb81890872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39960
29116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.3996029116
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.2102566361
Short name T1934
Test name
Test status
Simulation time 7116254324 ps
CPU time 54.91 seconds
Started Jun 24 05:24:04 PM PDT 24
Finished Jun 24 05:25:01 PM PDT 24
Peak memory 206340 kb
Host smart-b785d9df-e338-49c4-b390-ffe29526f2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21025
66361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.2102566361
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.731775672
Short name T832
Test name
Test status
Simulation time 3478559163 ps
CPU time 4.27 seconds
Started Jun 24 05:24:02 PM PDT 24
Finished Jun 24 05:24:08 PM PDT 24
Peak memory 206292 kb
Host smart-14aa701e-ef9a-4054-b078-8ce6e1c860d5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=731775672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.731775672
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.3790057912
Short name T867
Test name
Test status
Simulation time 13328238513 ps
CPU time 12.62 seconds
Started Jun 24 05:24:01 PM PDT 24
Finished Jun 24 05:24:14 PM PDT 24
Peak memory 206472 kb
Host smart-c6f2761e-dc95-4559-90d9-5aa510e19a91
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3790057912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3790057912
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.3619193727
Short name T1867
Test name
Test status
Simulation time 23423345496 ps
CPU time 22.2 seconds
Started Jun 24 05:24:02 PM PDT 24
Finished Jun 24 05:24:26 PM PDT 24
Peak memory 206236 kb
Host smart-07657059-892a-4e19-95a7-e85683bf5873
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3619193727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.3619193727
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3590809847
Short name T1347
Test name
Test status
Simulation time 151553761 ps
CPU time 0.83 seconds
Started Jun 24 05:24:04 PM PDT 24
Finished Jun 24 05:24:06 PM PDT 24
Peak memory 206152 kb
Host smart-b2412a9d-5b2e-40e8-b84a-8e620a75f46f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35908
09847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3590809847
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.3224490130
Short name T1796
Test name
Test status
Simulation time 149084949 ps
CPU time 0.75 seconds
Started Jun 24 05:24:07 PM PDT 24
Finished Jun 24 05:24:10 PM PDT 24
Peak memory 206132 kb
Host smart-d8cec70e-afb6-4a99-9dda-d20772d55edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32244
90130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3224490130
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.2087333590
Short name T487
Test name
Test status
Simulation time 298448220 ps
CPU time 1.1 seconds
Started Jun 24 05:24:01 PM PDT 24
Finished Jun 24 05:24:03 PM PDT 24
Peak memory 206160 kb
Host smart-7e7ea57b-c09a-4a8f-8822-75d1a2b35341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20873
33590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.2087333590
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.587963899
Short name T1256
Test name
Test status
Simulation time 1426498859 ps
CPU time 3.28 seconds
Started Jun 24 05:24:19 PM PDT 24
Finished Jun 24 05:24:23 PM PDT 24
Peak memory 206220 kb
Host smart-ede1779f-220e-4218-a5c3-b03b9879cf13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58796
3899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.587963899
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.1345070531
Short name T99
Test name
Test status
Simulation time 22427026308 ps
CPU time 44.61 seconds
Started Jun 24 05:24:03 PM PDT 24
Finished Jun 24 05:24:50 PM PDT 24
Peak memory 206312 kb
Host smart-8ea2342e-659f-45b7-bf73-77df822d58c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13450
70531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.1345070531
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.1170611586
Short name T959
Test name
Test status
Simulation time 464494451 ps
CPU time 1.41 seconds
Started Jun 24 05:24:02 PM PDT 24
Finished Jun 24 05:24:04 PM PDT 24
Peak memory 206080 kb
Host smart-5ad05258-55d7-4565-9404-b89f8373c15b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11706
11586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.1170611586
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.232001813
Short name T625
Test name
Test status
Simulation time 141111107 ps
CPU time 0.77 seconds
Started Jun 24 05:24:02 PM PDT 24
Finished Jun 24 05:24:05 PM PDT 24
Peak memory 206176 kb
Host smart-d4db0264-cf22-4f2c-8e21-35822858d69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23200
1813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.232001813
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.249478815
Short name T1677
Test name
Test status
Simulation time 39186946 ps
CPU time 0.69 seconds
Started Jun 24 05:24:04 PM PDT 24
Finished Jun 24 05:24:06 PM PDT 24
Peak memory 206108 kb
Host smart-5b9726dd-fa93-4683-865e-25b982f3df1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24947
8815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.249478815
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.2368840673
Short name T2437
Test name
Test status
Simulation time 733923047 ps
CPU time 1.81 seconds
Started Jun 24 05:24:06 PM PDT 24
Finished Jun 24 05:24:10 PM PDT 24
Peak memory 206300 kb
Host smart-3e2d6deb-e31a-4384-9f63-3f0668c5bdc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23688
40673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.2368840673
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3486012718
Short name T2245
Test name
Test status
Simulation time 214170265 ps
CPU time 1.49 seconds
Started Jun 24 05:24:03 PM PDT 24
Finished Jun 24 05:24:07 PM PDT 24
Peak memory 206312 kb
Host smart-38f79e0a-02c4-49db-b29e-5411099bf1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34860
12718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3486012718
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.370784510
Short name T474
Test name
Test status
Simulation time 209467411 ps
CPU time 0.85 seconds
Started Jun 24 05:24:24 PM PDT 24
Finished Jun 24 05:24:28 PM PDT 24
Peak memory 206124 kb
Host smart-f8653609-9bd3-4fc8-a77e-68d2f10dcb5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37078
4510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.370784510
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1357630395
Short name T1561
Test name
Test status
Simulation time 242419999 ps
CPU time 0.87 seconds
Started Jun 24 05:24:11 PM PDT 24
Finished Jun 24 05:24:13 PM PDT 24
Peak memory 206188 kb
Host smart-2d44023a-2037-4040-b72d-2492bdf6a0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13576
30395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1357630395
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.1752881667
Short name T1987
Test name
Test status
Simulation time 172759791 ps
CPU time 0.91 seconds
Started Jun 24 05:24:02 PM PDT 24
Finished Jun 24 05:24:05 PM PDT 24
Peak memory 206076 kb
Host smart-a0fb4df0-cad3-4659-8587-d2e82f5c9610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17528
81667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1752881667
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1878824085
Short name T1399
Test name
Test status
Simulation time 210478553 ps
CPU time 0.86 seconds
Started Jun 24 05:24:02 PM PDT 24
Finished Jun 24 05:24:05 PM PDT 24
Peak memory 206116 kb
Host smart-7e4ee9f6-efbb-4402-af81-b79841ee3922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18788
24085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1878824085
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2393873717
Short name T948
Test name
Test status
Simulation time 23344117022 ps
CPU time 22.28 seconds
Started Jun 24 05:24:08 PM PDT 24
Finished Jun 24 05:24:32 PM PDT 24
Peak memory 206248 kb
Host smart-ecf37440-5e50-481c-a2f8-c37843c99c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23938
73717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2393873717
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3933896804
Short name T535
Test name
Test status
Simulation time 3306114816 ps
CPU time 4.06 seconds
Started Jun 24 05:24:14 PM PDT 24
Finished Jun 24 05:24:19 PM PDT 24
Peak memory 206192 kb
Host smart-92d904cd-4373-4d4e-823f-e13a3bb660bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39338
96804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3933896804
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1241271798
Short name T626
Test name
Test status
Simulation time 14518799623 ps
CPU time 406.76 seconds
Started Jun 24 05:24:11 PM PDT 24
Finished Jun 24 05:30:59 PM PDT 24
Peak memory 206324 kb
Host smart-e27fc47f-7386-4d40-bbcd-84fa4459dfdd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1241271798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1241271798
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.3971139621
Short name T329
Test name
Test status
Simulation time 279258462 ps
CPU time 0.96 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:25 PM PDT 24
Peak memory 206168 kb
Host smart-9917e8d9-78b2-4ee6-ae51-f203d8e26c2d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3971139621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.3971139621
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3191875384
Short name T998
Test name
Test status
Simulation time 210207618 ps
CPU time 0.91 seconds
Started Jun 24 05:24:13 PM PDT 24
Finished Jun 24 05:24:16 PM PDT 24
Peak memory 206180 kb
Host smart-c4456c43-0610-471d-9626-bd60c19f4805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31918
75384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3191875384
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.3455426122
Short name T404
Test name
Test status
Simulation time 12074737219 ps
CPU time 122.3 seconds
Started Jun 24 05:24:12 PM PDT 24
Finished Jun 24 05:26:16 PM PDT 24
Peak memory 206576 kb
Host smart-a084e8ea-9d0b-4e60-bec3-0ddd761c02cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34554
26122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.3455426122
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.1915721341
Short name T1683
Test name
Test status
Simulation time 6857187690 ps
CPU time 189.77 seconds
Started Jun 24 05:24:15 PM PDT 24
Finished Jun 24 05:27:26 PM PDT 24
Peak memory 206324 kb
Host smart-52c078e8-80b0-4497-9fc6-6de1b643ad36
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1915721341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.1915721341
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.2032911409
Short name T1086
Test name
Test status
Simulation time 223591966 ps
CPU time 0.79 seconds
Started Jun 24 05:24:21 PM PDT 24
Finished Jun 24 05:24:22 PM PDT 24
Peak memory 206120 kb
Host smart-8690c2f5-181b-4fba-8eda-1c60bcf03f2f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2032911409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.2032911409
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1493015359
Short name T1544
Test name
Test status
Simulation time 154022457 ps
CPU time 0.83 seconds
Started Jun 24 05:24:12 PM PDT 24
Finished Jun 24 05:24:14 PM PDT 24
Peak memory 206180 kb
Host smart-5e23f0dc-13cd-4e65-a467-6bd5ff0a5c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14930
15359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1493015359
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.995735234
Short name T2046
Test name
Test status
Simulation time 172842111 ps
CPU time 0.85 seconds
Started Jun 24 05:24:15 PM PDT 24
Finished Jun 24 05:24:17 PM PDT 24
Peak memory 206072 kb
Host smart-54659f80-547f-4df6-9798-8ef5080534a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99573
5234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.995735234
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3479629331
Short name T1915
Test name
Test status
Simulation time 206828284 ps
CPU time 0.94 seconds
Started Jun 24 05:24:08 PM PDT 24
Finished Jun 24 05:24:10 PM PDT 24
Peak memory 206172 kb
Host smart-60534e58-8271-4332-a394-65e5b1e9fa87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34796
29331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3479629331
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3864735987
Short name T1879
Test name
Test status
Simulation time 179737859 ps
CPU time 0.83 seconds
Started Jun 24 05:24:12 PM PDT 24
Finished Jun 24 05:24:15 PM PDT 24
Peak memory 206104 kb
Host smart-b5a1f64f-e88b-4476-97af-9d6bc4e5d377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38647
35987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3864735987
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.4091319716
Short name T162
Test name
Test status
Simulation time 154690469 ps
CPU time 0.82 seconds
Started Jun 24 05:24:11 PM PDT 24
Finished Jun 24 05:24:12 PM PDT 24
Peak memory 206176 kb
Host smart-2f75b6aa-ea4b-41e8-85b7-255c76ef77cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40913
19716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.4091319716
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1805291888
Short name T343
Test name
Test status
Simulation time 235855734 ps
CPU time 0.96 seconds
Started Jun 24 05:24:12 PM PDT 24
Finished Jun 24 05:24:15 PM PDT 24
Peak memory 206136 kb
Host smart-32e64eaa-c955-4a9f-94bd-50b03f82165c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1805291888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1805291888
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.2524080920
Short name T96
Test name
Test status
Simulation time 141453916 ps
CPU time 0.76 seconds
Started Jun 24 05:24:09 PM PDT 24
Finished Jun 24 05:24:11 PM PDT 24
Peak memory 206152 kb
Host smart-df690625-3b45-4d0a-9964-c2b88399418b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25240
80920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.2524080920
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1705392480
Short name T36
Test name
Test status
Simulation time 85976350 ps
CPU time 0.69 seconds
Started Jun 24 05:24:13 PM PDT 24
Finished Jun 24 05:24:16 PM PDT 24
Peak memory 206196 kb
Host smart-7a2cc83b-91fd-4644-820a-c281b47719c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17053
92480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1705392480
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3402566329
Short name T2098
Test name
Test status
Simulation time 5476866052 ps
CPU time 12.64 seconds
Started Jun 24 05:24:12 PM PDT 24
Finished Jun 24 05:24:26 PM PDT 24
Peak memory 206448 kb
Host smart-457a996f-7205-4b35-a79a-43ec05d83762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34025
66329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3402566329
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.942233400
Short name T288
Test name
Test status
Simulation time 221897820 ps
CPU time 0.85 seconds
Started Jun 24 05:24:14 PM PDT 24
Finished Jun 24 05:24:16 PM PDT 24
Peak memory 206120 kb
Host smart-b95c6b19-aaea-4f87-b739-3808aeab68ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94223
3400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.942233400
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1806474095
Short name T1323
Test name
Test status
Simulation time 187812397 ps
CPU time 0.86 seconds
Started Jun 24 05:24:14 PM PDT 24
Finished Jun 24 05:24:17 PM PDT 24
Peak memory 206160 kb
Host smart-4efe37ae-7383-4c04-b80b-8b60b27f86e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18064
74095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1806474095
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.2561335041
Short name T31
Test name
Test status
Simulation time 225068532 ps
CPU time 0.92 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:26 PM PDT 24
Peak memory 206200 kb
Host smart-8a99d4fb-cafe-45fb-8a04-d639621a4414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25613
35041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.2561335041
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.3883442395
Short name T2085
Test name
Test status
Simulation time 200941148 ps
CPU time 0.86 seconds
Started Jun 24 05:24:11 PM PDT 24
Finished Jun 24 05:24:13 PM PDT 24
Peak memory 206184 kb
Host smart-dda1703b-844a-4662-90ce-7092ecdca774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38834
42395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.3883442395
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2206126231
Short name T622
Test name
Test status
Simulation time 140534690 ps
CPU time 0.74 seconds
Started Jun 24 05:24:09 PM PDT 24
Finished Jun 24 05:24:11 PM PDT 24
Peak memory 206140 kb
Host smart-ac47926f-25d4-4dfd-83ab-95ca9b9549e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22061
26231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2206126231
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.3682763170
Short name T2270
Test name
Test status
Simulation time 149890112 ps
CPU time 0.8 seconds
Started Jun 24 05:24:14 PM PDT 24
Finished Jun 24 05:24:16 PM PDT 24
Peak memory 206112 kb
Host smart-f5fa3257-a180-4cc3-b741-8702cb522d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36827
63170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.3682763170
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2788361278
Short name T1803
Test name
Test status
Simulation time 141816929 ps
CPU time 0.76 seconds
Started Jun 24 05:24:15 PM PDT 24
Finished Jun 24 05:24:17 PM PDT 24
Peak memory 206172 kb
Host smart-7ca60ae7-f0bb-443e-970c-a45c7ea6007a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27883
61278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2788361278
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.2816665334
Short name T1672
Test name
Test status
Simulation time 205140449 ps
CPU time 0.87 seconds
Started Jun 24 05:24:09 PM PDT 24
Finished Jun 24 05:24:11 PM PDT 24
Peak memory 206092 kb
Host smart-e68a1a37-26af-4580-92b1-7dbd4db899be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28166
65334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2816665334
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.1547452034
Short name T1440
Test name
Test status
Simulation time 4396437826 ps
CPU time 119.29 seconds
Started Jun 24 05:24:09 PM PDT 24
Finished Jun 24 05:26:09 PM PDT 24
Peak memory 206392 kb
Host smart-c6644574-eeab-4ff5-a866-888a46e87b6a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1547452034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.1547452034
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.1848240521
Short name T2397
Test name
Test status
Simulation time 158599252 ps
CPU time 0.78 seconds
Started Jun 24 05:24:10 PM PDT 24
Finished Jun 24 05:24:11 PM PDT 24
Peak memory 206176 kb
Host smart-20a10a51-faed-4f89-a163-31d242fe3f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18482
40521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.1848240521
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3532326299
Short name T1042
Test name
Test status
Simulation time 153766893 ps
CPU time 0.86 seconds
Started Jun 24 05:24:12 PM PDT 24
Finished Jun 24 05:24:15 PM PDT 24
Peak memory 206188 kb
Host smart-1c7cc6c7-293d-4d73-837f-7384391e0c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35323
26299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3532326299
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.3839183591
Short name T2153
Test name
Test status
Simulation time 11292046730 ps
CPU time 111.05 seconds
Started Jun 24 05:24:10 PM PDT 24
Finished Jun 24 05:26:02 PM PDT 24
Peak memory 206336 kb
Host smart-5c5a2cb1-fa5a-4169-949a-a1f755ca0e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38391
83591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.3839183591
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.4056011538
Short name T2404
Test name
Test status
Simulation time 3407926859 ps
CPU time 4.14 seconds
Started Jun 24 05:24:24 PM PDT 24
Finished Jun 24 05:24:31 PM PDT 24
Peak memory 206236 kb
Host smart-339bc8df-0488-4ccb-b933-afe793e6952a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4056011538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.4056011538
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2605630011
Short name T14
Test name
Test status
Simulation time 13362718430 ps
CPU time 15.92 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:40 PM PDT 24
Peak memory 206240 kb
Host smart-4dd6619f-9b29-4a76-86da-033d0929ec32
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2605630011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2605630011
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.3086169481
Short name T1494
Test name
Test status
Simulation time 23437541158 ps
CPU time 22.65 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:48 PM PDT 24
Peak memory 206220 kb
Host smart-a845d40d-e6d1-453a-9326-04c0257ae19c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3086169481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.3086169481
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1627095872
Short name T2147
Test name
Test status
Simulation time 153011002 ps
CPU time 0.78 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:25 PM PDT 24
Peak memory 206056 kb
Host smart-4ecb84bd-d532-4666-b6f5-2836aaaacacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16270
95872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1627095872
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.453522511
Short name T1955
Test name
Test status
Simulation time 140045667 ps
CPU time 0.75 seconds
Started Jun 24 05:24:24 PM PDT 24
Finished Jun 24 05:24:28 PM PDT 24
Peak memory 206156 kb
Host smart-a6aca7c8-8e21-4f99-afb9-10e91831dd31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45352
2511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.453522511
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.410856436
Short name T2015
Test name
Test status
Simulation time 377663143 ps
CPU time 1.22 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:26 PM PDT 24
Peak memory 206096 kb
Host smart-e7c16514-f1fd-46d3-9719-30b58e431e4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41085
6436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.410856436
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.436547053
Short name T1366
Test name
Test status
Simulation time 1279379499 ps
CPU time 2.71 seconds
Started Jun 24 05:24:23 PM PDT 24
Finished Jun 24 05:24:29 PM PDT 24
Peak memory 206280 kb
Host smart-ce09a091-61d1-4865-b3b6-e2af87d6e0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43654
7053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.436547053
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.565038895
Short name T2143
Test name
Test status
Simulation time 20594968515 ps
CPU time 37.47 seconds
Started Jun 24 05:24:21 PM PDT 24
Finished Jun 24 05:25:00 PM PDT 24
Peak memory 206400 kb
Host smart-5e3a3a31-1079-4d04-9664-2edf321418ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56503
8895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.565038895
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.3532810943
Short name T1383
Test name
Test status
Simulation time 332184312 ps
CPU time 1.26 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:25 PM PDT 24
Peak memory 206160 kb
Host smart-00b832fd-1bda-4d58-9636-6cae24be0275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35328
10943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.3532810943
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.4226189459
Short name T555
Test name
Test status
Simulation time 164008720 ps
CPU time 0.76 seconds
Started Jun 24 05:24:26 PM PDT 24
Finished Jun 24 05:24:29 PM PDT 24
Peak memory 206168 kb
Host smart-c83a47a8-3939-4f7d-b543-b9e48e9e21bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42261
89459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.4226189459
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.340976086
Short name T1586
Test name
Test status
Simulation time 34932121 ps
CPU time 0.68 seconds
Started Jun 24 05:24:27 PM PDT 24
Finished Jun 24 05:24:30 PM PDT 24
Peak memory 206168 kb
Host smart-7c458db1-4776-4963-9706-e9b7d9b81a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34097
6086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.340976086
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.1861368
Short name T677
Test name
Test status
Simulation time 783044458 ps
CPU time 1.91 seconds
Started Jun 24 05:24:24 PM PDT 24
Finished Jun 24 05:24:29 PM PDT 24
Peak memory 206224 kb
Host smart-112cc54f-76b5-4b79-b75a-06a8c0856231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18613
68 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1861368
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.301362009
Short name T656
Test name
Test status
Simulation time 278687172 ps
CPU time 1.7 seconds
Started Jun 24 05:24:20 PM PDT 24
Finished Jun 24 05:24:23 PM PDT 24
Peak memory 206336 kb
Host smart-cc56bcbb-b8df-4822-a5e2-24237ce6e3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30136
2009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.301362009
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.3395555194
Short name T1669
Test name
Test status
Simulation time 235866965 ps
CPU time 0.9 seconds
Started Jun 24 05:24:20 PM PDT 24
Finished Jun 24 05:24:22 PM PDT 24
Peak memory 206076 kb
Host smart-1e16ef8d-40ed-47b0-a0a0-046788ee0c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33955
55194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.3395555194
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2776173143
Short name T2511
Test name
Test status
Simulation time 142587839 ps
CPU time 0.78 seconds
Started Jun 24 05:24:26 PM PDT 24
Finished Jun 24 05:24:29 PM PDT 24
Peak memory 206140 kb
Host smart-766b6658-7c8e-44f5-a3ac-adfe18cfc1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27761
73143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2776173143
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.2518040494
Short name T2506
Test name
Test status
Simulation time 209513000 ps
CPU time 0.91 seconds
Started Jun 24 05:24:20 PM PDT 24
Finished Jun 24 05:24:22 PM PDT 24
Peak memory 206412 kb
Host smart-c37dc508-3ac0-440d-87e1-2a650dcd1cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25180
40494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.2518040494
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.1368409691
Short name T1938
Test name
Test status
Simulation time 195584847 ps
CPU time 0.93 seconds
Started Jun 24 05:24:24 PM PDT 24
Finished Jun 24 05:24:28 PM PDT 24
Peak memory 206148 kb
Host smart-38b02d61-8b09-4e96-a3d5-eaba94211874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13684
09691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.1368409691
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.406708570
Short name T2473
Test name
Test status
Simulation time 23330069783 ps
CPU time 20.47 seconds
Started Jun 24 05:24:31 PM PDT 24
Finished Jun 24 05:24:54 PM PDT 24
Peak memory 206248 kb
Host smart-83548f55-b9df-4ee2-93b8-d5b59ef83c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40670
8570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.406708570
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2890155577
Short name T321
Test name
Test status
Simulation time 3341567006 ps
CPU time 4.5 seconds
Started Jun 24 05:24:23 PM PDT 24
Finished Jun 24 05:24:30 PM PDT 24
Peak memory 206160 kb
Host smart-064ace37-8486-4f29-8449-1c01e6d28ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28901
55577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2890155577
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.3697049249
Short name T1120
Test name
Test status
Simulation time 4283259902 ps
CPU time 124.1 seconds
Started Jun 24 05:24:21 PM PDT 24
Finished Jun 24 05:26:27 PM PDT 24
Peak memory 206396 kb
Host smart-2d904ae0-5f2c-468d-ab12-3ac1071258fc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3697049249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.3697049249
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.2325182851
Short name T387
Test name
Test status
Simulation time 251508431 ps
CPU time 0.93 seconds
Started Jun 24 05:24:23 PM PDT 24
Finished Jun 24 05:24:27 PM PDT 24
Peak memory 206196 kb
Host smart-bbfd69d1-19d7-42e2-be0a-2d0404ec740f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2325182851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.2325182851
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.4187999768
Short name T432
Test name
Test status
Simulation time 247976945 ps
CPU time 1.01 seconds
Started Jun 24 05:24:21 PM PDT 24
Finished Jun 24 05:24:24 PM PDT 24
Peak memory 206152 kb
Host smart-93db2912-b127-4593-9390-470915196e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41879
99768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.4187999768
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.1130810389
Short name T1334
Test name
Test status
Simulation time 6386560215 ps
CPU time 172.56 seconds
Started Jun 24 05:24:25 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206380 kb
Host smart-206ae597-24ba-484f-94b5-86ca8503dfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11308
10389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.1130810389
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.2232633750
Short name T156
Test name
Test status
Simulation time 3115809102 ps
CPU time 28.89 seconds
Started Jun 24 05:24:21 PM PDT 24
Finished Jun 24 05:24:52 PM PDT 24
Peak memory 206356 kb
Host smart-c4a438d3-fc42-4af1-a177-cc3a54ac0462
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2232633750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.2232633750
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.1142378278
Short name T2118
Test name
Test status
Simulation time 163647283 ps
CPU time 0.81 seconds
Started Jun 24 05:24:23 PM PDT 24
Finished Jun 24 05:24:27 PM PDT 24
Peak memory 206196 kb
Host smart-e2f8acc3-c147-4918-b340-520d71735355
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1142378278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.1142378278
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.359717968
Short name T1954
Test name
Test status
Simulation time 156116678 ps
CPU time 0.82 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:24 PM PDT 24
Peak memory 206192 kb
Host smart-490ba5d9-41b4-48da-a820-ffee0048f2d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35971
7968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.359717968
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3094189719
Short name T125
Test name
Test status
Simulation time 199157052 ps
CPU time 0.85 seconds
Started Jun 24 05:24:23 PM PDT 24
Finished Jun 24 05:24:26 PM PDT 24
Peak memory 206176 kb
Host smart-d5efc66e-7166-42af-b610-c9d040869fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30941
89719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3094189719
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2192530959
Short name T1286
Test name
Test status
Simulation time 143711433 ps
CPU time 0.78 seconds
Started Jun 24 05:24:24 PM PDT 24
Finished Jun 24 05:24:28 PM PDT 24
Peak memory 206192 kb
Host smart-db0a5e8c-8fd8-4ae2-8a09-a9b52943b39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21925
30959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2192530959
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3228081019
Short name T2056
Test name
Test status
Simulation time 156434706 ps
CPU time 0.78 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:25 PM PDT 24
Peak memory 206156 kb
Host smart-11329e0b-a7fa-47d8-875b-f5c99a8db039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32280
81019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3228081019
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2738104483
Short name T1946
Test name
Test status
Simulation time 156122638 ps
CPU time 0.78 seconds
Started Jun 24 05:24:28 PM PDT 24
Finished Jun 24 05:24:31 PM PDT 24
Peak memory 206092 kb
Host smart-e8484e44-c85f-4878-8649-9df3b186d9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27381
04483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2738104483
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3108018672
Short name T1828
Test name
Test status
Simulation time 153266700 ps
CPU time 0.87 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:26 PM PDT 24
Peak memory 206096 kb
Host smart-ea770686-e82b-457f-94e8-2b6fa6f6f7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31080
18672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3108018672
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.2681029820
Short name T1268
Test name
Test status
Simulation time 217867089 ps
CPU time 0.89 seconds
Started Jun 24 05:24:24 PM PDT 24
Finished Jun 24 05:24:28 PM PDT 24
Peak memory 206088 kb
Host smart-aa2f2e03-d59b-45b2-a1fa-f0febecb0b21
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2681029820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.2681029820
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.1438789251
Short name T1589
Test name
Test status
Simulation time 170463990 ps
CPU time 0.8 seconds
Started Jun 24 05:24:37 PM PDT 24
Finished Jun 24 05:24:42 PM PDT 24
Peak memory 206176 kb
Host smart-e1789b9f-52a7-4d9e-afb1-54a76863b54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14387
89251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.1438789251
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.727812395
Short name T1406
Test name
Test status
Simulation time 85828941 ps
CPU time 0.7 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:25 PM PDT 24
Peak memory 206188 kb
Host smart-d8bc7c04-76b8-4513-89b6-afc05d20c840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72781
2395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.727812395
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3005050044
Short name T823
Test name
Test status
Simulation time 19189576269 ps
CPU time 44.49 seconds
Started Jun 24 05:24:24 PM PDT 24
Finished Jun 24 05:25:12 PM PDT 24
Peak memory 206372 kb
Host smart-2ad927c3-f5bc-49fa-b2d7-110ef4805bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30050
50044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3005050044
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2163833058
Short name T1298
Test name
Test status
Simulation time 172681154 ps
CPU time 0.83 seconds
Started Jun 24 05:24:25 PM PDT 24
Finished Jun 24 05:24:28 PM PDT 24
Peak memory 206072 kb
Host smart-84a877b8-e13e-4c07-a03a-0bb5a78edad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21638
33058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2163833058
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.734492178
Short name T2191
Test name
Test status
Simulation time 240033121 ps
CPU time 0.88 seconds
Started Jun 24 05:24:21 PM PDT 24
Finished Jun 24 05:24:22 PM PDT 24
Peak memory 206172 kb
Host smart-859c3ca0-48de-4864-80c0-29d0071d7a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73449
2178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.734492178
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.3166319635
Short name T1099
Test name
Test status
Simulation time 200920428 ps
CPU time 0.84 seconds
Started Jun 24 05:24:23 PM PDT 24
Finished Jun 24 05:24:26 PM PDT 24
Peak memory 206200 kb
Host smart-df279bee-df31-4c38-861c-9869a84ae816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31663
19635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.3166319635
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.2416782607
Short name T1527
Test name
Test status
Simulation time 214462130 ps
CPU time 0.85 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:26 PM PDT 24
Peak memory 206200 kb
Host smart-4b64edc2-8dc1-42ca-aec6-aecefaa90f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24167
82607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.2416782607
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.86367650
Short name T1749
Test name
Test status
Simulation time 174365314 ps
CPU time 0.8 seconds
Started Jun 24 05:24:28 PM PDT 24
Finished Jun 24 05:24:31 PM PDT 24
Peak memory 206068 kb
Host smart-1a5b54cc-535c-42ef-afe2-a0caeb8fa7e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86367
650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.86367650
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1774824262
Short name T1898
Test name
Test status
Simulation time 155553878 ps
CPU time 0.8 seconds
Started Jun 24 05:24:23 PM PDT 24
Finished Jun 24 05:24:27 PM PDT 24
Peak memory 206184 kb
Host smart-1b833f1f-70b7-4e63-ae8e-52b167970b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17748
24262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1774824262
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3053128316
Short name T858
Test name
Test status
Simulation time 161996588 ps
CPU time 0.76 seconds
Started Jun 24 05:24:24 PM PDT 24
Finished Jun 24 05:24:28 PM PDT 24
Peak memory 206176 kb
Host smart-6d8b1d22-8f1b-45e2-a8cf-cd9ba19e16a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30531
28316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3053128316
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3759139802
Short name T2304
Test name
Test status
Simulation time 229893908 ps
CPU time 0.96 seconds
Started Jun 24 05:24:25 PM PDT 24
Finished Jun 24 05:24:28 PM PDT 24
Peak memory 206060 kb
Host smart-31017106-bb22-47bb-9e15-20a53c80ad1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37591
39802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3759139802
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.3663935236
Short name T873
Test name
Test status
Simulation time 9903531068 ps
CPU time 93.62 seconds
Started Jun 24 05:24:23 PM PDT 24
Finished Jun 24 05:26:00 PM PDT 24
Peak memory 206304 kb
Host smart-738eb983-e7d6-4074-95a1-1213a09b18aa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3663935236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.3663935236
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.596848471
Short name T1226
Test name
Test status
Simulation time 204241161 ps
CPU time 0.85 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:26 PM PDT 24
Peak memory 206176 kb
Host smart-a55f3dad-26c2-4b68-aeeb-465c2e55d10d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59684
8471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.596848471
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.3430333546
Short name T1652
Test name
Test status
Simulation time 169748971 ps
CPU time 0.82 seconds
Started Jun 24 05:24:23 PM PDT 24
Finished Jun 24 05:24:26 PM PDT 24
Peak memory 206184 kb
Host smart-c8d04cb6-7c78-4116-a279-db319aa80596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34303
33546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.3430333546
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.3473967302
Short name T413
Test name
Test status
Simulation time 4348200411 ps
CPU time 32.68 seconds
Started Jun 24 05:24:28 PM PDT 24
Finished Jun 24 05:25:03 PM PDT 24
Peak memory 206304 kb
Host smart-670b4f8e-5eb2-40fb-8a2d-c1dca37ae060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34739
67302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.3473967302
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.4052084282
Short name T2465
Test name
Test status
Simulation time 4017853976 ps
CPU time 5.32 seconds
Started Jun 24 05:24:24 PM PDT 24
Finished Jun 24 05:24:32 PM PDT 24
Peak memory 206352 kb
Host smart-ea2076a2-597b-4935-9ddc-8c634110b148
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4052084282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.4052084282
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.4258395104
Short name T1167
Test name
Test status
Simulation time 13421610095 ps
CPU time 11.99 seconds
Started Jun 24 05:24:23 PM PDT 24
Finished Jun 24 05:24:37 PM PDT 24
Peak memory 206164 kb
Host smart-541142be-a246-4edb-897a-dc4823514884
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4258395104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.4258395104
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.51247259
Short name T1983
Test name
Test status
Simulation time 23332857047 ps
CPU time 22.86 seconds
Started Jun 24 05:24:24 PM PDT 24
Finished Jun 24 05:24:50 PM PDT 24
Peak memory 206204 kb
Host smart-c8185880-5739-4cce-963a-324bcd523fea
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=51247259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.51247259
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.702674170
Short name T1253
Test name
Test status
Simulation time 188591961 ps
CPU time 0.83 seconds
Started Jun 24 05:24:28 PM PDT 24
Finished Jun 24 05:24:30 PM PDT 24
Peak memory 206088 kb
Host smart-24f9dd6e-e997-4e87-87f6-4d67655eacc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70267
4170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.702674170
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.272011058
Short name T1454
Test name
Test status
Simulation time 153225798 ps
CPU time 0.79 seconds
Started Jun 24 05:24:23 PM PDT 24
Finished Jun 24 05:24:27 PM PDT 24
Peak memory 206176 kb
Host smart-4d8cc7d6-95ed-4681-a21c-9056e0a9ef40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27201
1058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.272011058
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.2903563523
Short name T1172
Test name
Test status
Simulation time 473376580 ps
CPU time 1.5 seconds
Started Jun 24 05:24:25 PM PDT 24
Finished Jun 24 05:24:29 PM PDT 24
Peak memory 206176 kb
Host smart-35ff7683-9126-4ca4-a9fb-574af0947669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29035
63523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.2903563523
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.4281402752
Short name T30
Test name
Test status
Simulation time 356584615 ps
CPU time 1.09 seconds
Started Jun 24 05:24:25 PM PDT 24
Finished Jun 24 05:24:29 PM PDT 24
Peak memory 206100 kb
Host smart-981203b7-d01a-4c8f-9757-509fe328900d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42814
02752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.4281402752
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.3698095085
Short name T991
Test name
Test status
Simulation time 20273069635 ps
CPU time 44.8 seconds
Started Jun 24 05:24:39 PM PDT 24
Finished Jun 24 05:25:27 PM PDT 24
Peak memory 206320 kb
Host smart-e67badaa-f7ab-43ed-826a-32e938e61d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36980
95085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.3698095085
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.3228532776
Short name T469
Test name
Test status
Simulation time 473367200 ps
CPU time 1.27 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:25 PM PDT 24
Peak memory 206184 kb
Host smart-29590951-58af-45f5-bc71-0c0ad72124b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32285
32776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.3228532776
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.4175986189
Short name T2218
Test name
Test status
Simulation time 139261760 ps
CPU time 0.76 seconds
Started Jun 24 05:24:25 PM PDT 24
Finished Jun 24 05:24:28 PM PDT 24
Peak memory 206168 kb
Host smart-0f82075b-cd60-43fb-8e13-94d2c8ecabc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41759
86189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.4175986189
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.1980534621
Short name T1316
Test name
Test status
Simulation time 53717564 ps
CPU time 0.69 seconds
Started Jun 24 05:24:20 PM PDT 24
Finished Jun 24 05:24:22 PM PDT 24
Peak memory 206160 kb
Host smart-e36b5d28-3f96-4acc-8f0a-aceaa5cf20cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19805
34621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1980534621
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.2201364049
Short name T463
Test name
Test status
Simulation time 865426925 ps
CPU time 2.11 seconds
Started Jun 24 05:24:22 PM PDT 24
Finished Jun 24 05:24:27 PM PDT 24
Peak memory 206312 kb
Host smart-925ace85-c4a6-49f2-b878-8c4d958ad957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22013
64049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.2201364049
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1948870689
Short name T2274
Test name
Test status
Simulation time 316858904 ps
CPU time 1.94 seconds
Started Jun 24 05:24:32 PM PDT 24
Finished Jun 24 05:24:36 PM PDT 24
Peak memory 206540 kb
Host smart-9078a9fe-4a6a-4ff5-aba9-1867c8bc6c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19488
70689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1948870689
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.1998345260
Short name T804
Test name
Test status
Simulation time 214349258 ps
CPU time 0.91 seconds
Started Jun 24 05:24:33 PM PDT 24
Finished Jun 24 05:24:37 PM PDT 24
Peak memory 206076 kb
Host smart-d00776dc-3e4a-4af4-991f-6c771e9367de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19983
45260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.1998345260
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1170168407
Short name T121
Test name
Test status
Simulation time 148965805 ps
CPU time 0.82 seconds
Started Jun 24 05:24:34 PM PDT 24
Finished Jun 24 05:24:37 PM PDT 24
Peak memory 206188 kb
Host smart-31f348a5-7b8e-40ac-867e-d7c661b0c057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11701
68407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1170168407
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2724584349
Short name T378
Test name
Test status
Simulation time 167212899 ps
CPU time 0.86 seconds
Started Jun 24 05:24:35 PM PDT 24
Finished Jun 24 05:24:40 PM PDT 24
Peak memory 206188 kb
Host smart-eaf3b638-a4ad-4811-b0e1-48ea42ad8f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27245
84349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2724584349
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.3542113099
Short name T587
Test name
Test status
Simulation time 5294773035 ps
CPU time 48.39 seconds
Started Jun 24 05:24:34 PM PDT 24
Finished Jun 24 05:25:26 PM PDT 24
Peak memory 206536 kb
Host smart-1859c743-d7ad-4dfd-a990-80c4fb0a847d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3542113099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.3542113099
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.588930535
Short name T1016
Test name
Test status
Simulation time 233216292 ps
CPU time 0.92 seconds
Started Jun 24 05:24:33 PM PDT 24
Finished Jun 24 05:24:37 PM PDT 24
Peak memory 206108 kb
Host smart-9e264541-99af-4a2d-a188-e81aa6b269e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58893
0535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.588930535
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.2658501765
Short name T2253
Test name
Test status
Simulation time 23309852910 ps
CPU time 29.39 seconds
Started Jun 24 05:24:34 PM PDT 24
Finished Jun 24 05:25:07 PM PDT 24
Peak memory 206492 kb
Host smart-dc880860-bd08-40c7-9204-a57bc107e967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26585
01765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.2658501765
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.3890751716
Short name T1770
Test name
Test status
Simulation time 3319953976 ps
CPU time 3.6 seconds
Started Jun 24 05:24:34 PM PDT 24
Finished Jun 24 05:24:40 PM PDT 24
Peak memory 206220 kb
Host smart-fae24508-dfe3-4b29-a457-621381524263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38907
51716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.3890751716
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.624342666
Short name T601
Test name
Test status
Simulation time 8454708428 ps
CPU time 59.21 seconds
Started Jun 24 05:24:29 PM PDT 24
Finished Jun 24 05:25:31 PM PDT 24
Peak memory 206348 kb
Host smart-e9108b31-f553-42c6-a3e2-c4bc31461837
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=624342666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.624342666
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.3164276044
Short name T689
Test name
Test status
Simulation time 236751176 ps
CPU time 0.94 seconds
Started Jun 24 05:24:32 PM PDT 24
Finished Jun 24 05:24:35 PM PDT 24
Peak memory 206096 kb
Host smart-7e642f2c-baee-4a1a-b8c7-506f6cf46cec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3164276044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.3164276044
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.989919507
Short name T1688
Test name
Test status
Simulation time 237110790 ps
CPU time 0.89 seconds
Started Jun 24 05:24:35 PM PDT 24
Finished Jun 24 05:24:39 PM PDT 24
Peak memory 206196 kb
Host smart-e498e372-c58b-466c-baf9-969529506613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98991
9507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.989919507
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2642059807
Short name T883
Test name
Test status
Simulation time 7404066046 ps
CPU time 68.96 seconds
Started Jun 24 05:24:36 PM PDT 24
Finished Jun 24 05:25:49 PM PDT 24
Peak memory 206308 kb
Host smart-e8ccfd70-698c-4601-bd3d-e613225e14d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26420
59807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2642059807
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.441052466
Short name T1645
Test name
Test status
Simulation time 9960865339 ps
CPU time 93.79 seconds
Started Jun 24 05:24:33 PM PDT 24
Finished Jun 24 05:26:09 PM PDT 24
Peak memory 206624 kb
Host smart-38807d8c-56b2-4866-9612-61f2c5d8349f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=441052466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.441052466
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.219610573
Short name T738
Test name
Test status
Simulation time 160139511 ps
CPU time 0.79 seconds
Started Jun 24 05:24:37 PM PDT 24
Finished Jun 24 05:24:42 PM PDT 24
Peak memory 206196 kb
Host smart-1ec66027-68cd-41b8-b8c0-b1bea3e66199
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=219610573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.219610573
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2315705889
Short name T1666
Test name
Test status
Simulation time 146213140 ps
CPU time 0.79 seconds
Started Jun 24 05:24:30 PM PDT 24
Finished Jun 24 05:24:33 PM PDT 24
Peak memory 206176 kb
Host smart-5f878451-c76b-46ca-a33a-84e568b86eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23157
05889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2315705889
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.3190306176
Short name T1930
Test name
Test status
Simulation time 206560379 ps
CPU time 0.91 seconds
Started Jun 24 05:24:29 PM PDT 24
Finished Jun 24 05:24:33 PM PDT 24
Peak memory 206180 kb
Host smart-8916170a-33f7-4697-a1ef-b4a6cee5684e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31903
06176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3190306176
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.3061924811
Short name T1550
Test name
Test status
Simulation time 141305242 ps
CPU time 0.8 seconds
Started Jun 24 05:24:30 PM PDT 24
Finished Jun 24 05:24:33 PM PDT 24
Peak memory 206076 kb
Host smart-b6634d78-a44f-4807-9347-da921c1b41cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30619
24811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.3061924811
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.936556830
Short name T1270
Test name
Test status
Simulation time 176468859 ps
CPU time 0.8 seconds
Started Jun 24 05:24:30 PM PDT 24
Finished Jun 24 05:24:33 PM PDT 24
Peak memory 206176 kb
Host smart-352d90a6-7379-42da-a6a9-611e2182d5ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93655
6830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.936556830
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3194229833
Short name T589
Test name
Test status
Simulation time 194868248 ps
CPU time 0.82 seconds
Started Jun 24 05:24:34 PM PDT 24
Finished Jun 24 05:24:38 PM PDT 24
Peak memory 206120 kb
Host smart-d69348bb-12d5-40cb-995f-f0471dd819ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31942
29833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3194229833
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.347906633
Short name T184
Test name
Test status
Simulation time 150785811 ps
CPU time 0.82 seconds
Started Jun 24 05:24:35 PM PDT 24
Finished Jun 24 05:24:39 PM PDT 24
Peak memory 206180 kb
Host smart-1acbe146-2b46-480e-9347-35659e5e1cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34790
6633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.347906633
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.394225944
Short name T500
Test name
Test status
Simulation time 228889861 ps
CPU time 0.94 seconds
Started Jun 24 05:24:30 PM PDT 24
Finished Jun 24 05:24:34 PM PDT 24
Peak memory 206180 kb
Host smart-c85d0a4a-42bc-474c-ae2a-021a9f173c8f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=394225944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.394225944
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1689935165
Short name T1395
Test name
Test status
Simulation time 138467819 ps
CPU time 0.75 seconds
Started Jun 24 05:24:28 PM PDT 24
Finished Jun 24 05:24:31 PM PDT 24
Peak memory 206096 kb
Host smart-482ae9af-ae94-4292-97d4-0df402d9e9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16899
35165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1689935165
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1197957958
Short name T1714
Test name
Test status
Simulation time 55237619 ps
CPU time 0.67 seconds
Started Jun 24 05:24:28 PM PDT 24
Finished Jun 24 05:24:31 PM PDT 24
Peak memory 206096 kb
Host smart-b86bd38a-b63e-4dea-a0bb-8aa058e49281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11979
57958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1197957958
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3115542692
Short name T1921
Test name
Test status
Simulation time 9124481757 ps
CPU time 22.15 seconds
Started Jun 24 05:24:32 PM PDT 24
Finished Jun 24 05:24:57 PM PDT 24
Peak memory 206364 kb
Host smart-ebec75cd-335c-4e25-a572-9dbe5d15c500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31155
42692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3115542692
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.3203195227
Short name T666
Test name
Test status
Simulation time 151238785 ps
CPU time 0.81 seconds
Started Jun 24 05:24:32 PM PDT 24
Finished Jun 24 05:24:35 PM PDT 24
Peak memory 206136 kb
Host smart-5445b7f5-c7b7-4688-8f8b-23089966d525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32031
95227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.3203195227
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2380373718
Short name T727
Test name
Test status
Simulation time 200446101 ps
CPU time 0.88 seconds
Started Jun 24 05:24:33 PM PDT 24
Finished Jun 24 05:24:37 PM PDT 24
Peak memory 206188 kb
Host smart-2e29fb6f-875e-4e46-9cb1-a52e5c420c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23803
73718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2380373718
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.2565739230
Short name T2352
Test name
Test status
Simulation time 239726696 ps
CPU time 1 seconds
Started Jun 24 05:24:32 PM PDT 24
Finished Jun 24 05:24:36 PM PDT 24
Peak memory 206200 kb
Host smart-cc8309b9-fae3-48b5-bca7-f3ee4b4b95ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25657
39230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.2565739230
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.692519331
Short name T658
Test name
Test status
Simulation time 241905476 ps
CPU time 0.93 seconds
Started Jun 24 05:24:31 PM PDT 24
Finished Jun 24 05:24:34 PM PDT 24
Peak memory 206052 kb
Host smart-6b6baae0-2bc2-437d-8e9c-31f795cb39c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69251
9331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.692519331
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.3868188016
Short name T1238
Test name
Test status
Simulation time 149687339 ps
CPU time 0.77 seconds
Started Jun 24 05:24:31 PM PDT 24
Finished Jun 24 05:24:35 PM PDT 24
Peak memory 206408 kb
Host smart-42becb74-365f-4488-8c67-2ebbc7f645ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38681
88016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3868188016
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.688354600
Short name T2510
Test name
Test status
Simulation time 186000744 ps
CPU time 0.82 seconds
Started Jun 24 05:24:30 PM PDT 24
Finished Jun 24 05:24:33 PM PDT 24
Peak memory 206188 kb
Host smart-62be1687-7b03-4294-96eb-484a7ec1cc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68835
4600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.688354600
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.4074914975
Short name T735
Test name
Test status
Simulation time 160671577 ps
CPU time 0.75 seconds
Started Jun 24 05:24:34 PM PDT 24
Finished Jun 24 05:24:38 PM PDT 24
Peak memory 206148 kb
Host smart-811ab748-bd2c-4408-ae24-af7f9d689f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40749
14975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.4074914975
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2411495816
Short name T356
Test name
Test status
Simulation time 224675743 ps
CPU time 0.91 seconds
Started Jun 24 05:24:30 PM PDT 24
Finished Jun 24 05:24:34 PM PDT 24
Peak memory 206192 kb
Host smart-36d3840c-669d-4ca3-b9b5-ad32342d76ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24114
95816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2411495816
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.711643977
Short name T654
Test name
Test status
Simulation time 4696351518 ps
CPU time 127.13 seconds
Started Jun 24 05:24:34 PM PDT 24
Finished Jun 24 05:26:44 PM PDT 24
Peak memory 206376 kb
Host smart-4b036fb7-10a5-41e8-9e59-b463dab5176c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=711643977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.711643977
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.461192580
Short name T671
Test name
Test status
Simulation time 249748388 ps
CPU time 0.95 seconds
Started Jun 24 05:24:30 PM PDT 24
Finished Jun 24 05:24:33 PM PDT 24
Peak memory 206172 kb
Host smart-b333aa8b-990e-4fd3-baad-52990345bed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46119
2580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.461192580
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2923956442
Short name T1835
Test name
Test status
Simulation time 181480304 ps
CPU time 0.84 seconds
Started Jun 24 05:24:34 PM PDT 24
Finished Jun 24 05:24:38 PM PDT 24
Peak memory 206116 kb
Host smart-838a79fa-daba-4f69-bdc8-c87c32ef6710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29239
56442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2923956442
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.1918873742
Short name T1741
Test name
Test status
Simulation time 14706892412 ps
CPU time 144.25 seconds
Started Jun 24 05:24:32 PM PDT 24
Finished Jun 24 05:26:59 PM PDT 24
Peak memory 206568 kb
Host smart-e29a1363-0bbc-48b2-92c0-3e4f2cb515a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19188
73742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.1918873742
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2390412978
Short name T2194
Test name
Test status
Simulation time 3421361353 ps
CPU time 4.05 seconds
Started Jun 24 05:24:32 PM PDT 24
Finished Jun 24 05:24:39 PM PDT 24
Peak memory 206240 kb
Host smart-1cff640a-74cd-451c-98a2-218bac7e0080
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2390412978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.2390412978
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.1717710901
Short name T2263
Test name
Test status
Simulation time 13387919368 ps
CPU time 15.88 seconds
Started Jun 24 05:24:37 PM PDT 24
Finished Jun 24 05:24:57 PM PDT 24
Peak memory 206244 kb
Host smart-587c7990-7264-49ef-bac0-e787fe2bdca1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1717710901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.1717710901
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.2125442135
Short name T1976
Test name
Test status
Simulation time 23357993986 ps
CPU time 22.1 seconds
Started Jun 24 05:24:34 PM PDT 24
Finished Jun 24 05:24:59 PM PDT 24
Peak memory 206292 kb
Host smart-ed119507-bfac-49c2-9597-806023f63cc2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2125442135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.2125442135
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3867857423
Short name T605
Test name
Test status
Simulation time 211493269 ps
CPU time 0.84 seconds
Started Jun 24 05:24:32 PM PDT 24
Finished Jun 24 05:24:35 PM PDT 24
Peak memory 206180 kb
Host smart-45576d91-532a-4008-9629-082f5b99f8d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38678
57423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3867857423
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.963688420
Short name T2180
Test name
Test status
Simulation time 161685282 ps
CPU time 0.8 seconds
Started Jun 24 05:24:37 PM PDT 24
Finished Jun 24 05:24:41 PM PDT 24
Peak memory 206176 kb
Host smart-0cb614a6-316c-406b-8cad-c54e862ae4e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96368
8420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.963688420
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.2558214624
Short name T716
Test name
Test status
Simulation time 405475615 ps
CPU time 1.33 seconds
Started Jun 24 05:24:32 PM PDT 24
Finished Jun 24 05:24:35 PM PDT 24
Peak memory 206176 kb
Host smart-cf60cbb4-f9f9-4eae-a1f6-da91ee7bead8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25582
14624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.2558214624
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.2569351521
Short name T58
Test name
Test status
Simulation time 580176329 ps
CPU time 1.57 seconds
Started Jun 24 05:24:35 PM PDT 24
Finished Jun 24 05:24:40 PM PDT 24
Peak memory 206172 kb
Host smart-aef2b8b6-4c06-479d-ad92-070faee54f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25693
51521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.2569351521
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.483597092
Short name T2213
Test name
Test status
Simulation time 18922157469 ps
CPU time 33.03 seconds
Started Jun 24 05:24:35 PM PDT 24
Finished Jun 24 05:25:11 PM PDT 24
Peak memory 206248 kb
Host smart-26699789-4833-41b0-a57a-ef33522da567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48359
7092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.483597092
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.1891233888
Short name T1392
Test name
Test status
Simulation time 428780302 ps
CPU time 1.35 seconds
Started Jun 24 05:24:37 PM PDT 24
Finished Jun 24 05:24:42 PM PDT 24
Peak memory 206180 kb
Host smart-3f8deb63-0b22-41fb-b4e2-d4d6b06034ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18912
33888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1891233888
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2216725316
Short name T748
Test name
Test status
Simulation time 139732754 ps
CPU time 0.75 seconds
Started Jun 24 05:24:33 PM PDT 24
Finished Jun 24 05:24:36 PM PDT 24
Peak memory 206164 kb
Host smart-d67efde2-d6ef-4e15-a74b-a8b3dfd066a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22167
25316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2216725316
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.2696929287
Short name T830
Test name
Test status
Simulation time 58806125 ps
CPU time 0.71 seconds
Started Jun 24 05:24:32 PM PDT 24
Finished Jun 24 05:24:35 PM PDT 24
Peak memory 206164 kb
Host smart-7be99bab-182b-410f-a9c0-a8a9e0a45344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26969
29287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2696929287
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2157182099
Short name T1695
Test name
Test status
Simulation time 903362432 ps
CPU time 2.21 seconds
Started Jun 24 05:24:35 PM PDT 24
Finished Jun 24 05:24:41 PM PDT 24
Peak memory 206252 kb
Host smart-e2c900de-d0a9-453a-aeea-4b2444066a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21571
82099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2157182099
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2912011425
Short name T1509
Test name
Test status
Simulation time 251046835 ps
CPU time 1.35 seconds
Started Jun 24 05:24:32 PM PDT 24
Finished Jun 24 05:24:36 PM PDT 24
Peak memory 206200 kb
Host smart-1a4ecec8-ba1d-484c-bb0a-004a0f108b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29120
11425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2912011425
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3374500168
Short name T1843
Test name
Test status
Simulation time 250195724 ps
CPU time 0.98 seconds
Started Jun 24 05:24:42 PM PDT 24
Finished Jun 24 05:24:47 PM PDT 24
Peak memory 206064 kb
Host smart-2f167d13-89b1-46d3-a231-a9b26211c7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33745
00168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3374500168
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.329229364
Short name T766
Test name
Test status
Simulation time 172936373 ps
CPU time 0.8 seconds
Started Jun 24 05:24:43 PM PDT 24
Finished Jun 24 05:24:48 PM PDT 24
Peak memory 206072 kb
Host smart-daab5ed4-8b1b-4caf-bf15-bbb8c7a14f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32922
9364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.329229364
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2721453825
Short name T828
Test name
Test status
Simulation time 210569622 ps
CPU time 0.87 seconds
Started Jun 24 05:24:35 PM PDT 24
Finished Jun 24 05:24:40 PM PDT 24
Peak memory 206192 kb
Host smart-ff77f82f-b700-4289-94ab-db04514c47ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27214
53825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2721453825
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.469657845
Short name T2455
Test name
Test status
Simulation time 7913276635 ps
CPU time 58.09 seconds
Started Jun 24 05:24:35 PM PDT 24
Finished Jun 24 05:25:37 PM PDT 24
Peak memory 206348 kb
Host smart-2f3bc6ac-9865-48e1-8b21-1e9523da232a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=469657845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.469657845
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3458836048
Short name T1352
Test name
Test status
Simulation time 250505946 ps
CPU time 0.95 seconds
Started Jun 24 05:24:35 PM PDT 24
Finished Jun 24 05:24:39 PM PDT 24
Peak memory 206192 kb
Host smart-c7aa1141-9aee-4dd4-9564-d1a95dfb538d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34588
36048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3458836048
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3518230808
Short name T2185
Test name
Test status
Simulation time 23318165586 ps
CPU time 21.9 seconds
Started Jun 24 05:24:33 PM PDT 24
Finished Jun 24 05:24:57 PM PDT 24
Peak memory 206156 kb
Host smart-cb1f4bb4-edb7-47be-a6b8-edef5e26564e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35182
30808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3518230808
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2181054025
Short name T955
Test name
Test status
Simulation time 3300401781 ps
CPU time 3.71 seconds
Started Jun 24 05:24:36 PM PDT 24
Finished Jun 24 05:24:43 PM PDT 24
Peak memory 206240 kb
Host smart-bc88d415-89a6-4a43-a675-c62b098ea4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21810
54025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2181054025
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1385492779
Short name T1052
Test name
Test status
Simulation time 14920563185 ps
CPU time 131.95 seconds
Started Jun 24 05:24:46 PM PDT 24
Finished Jun 24 05:27:02 PM PDT 24
Peak memory 206256 kb
Host smart-2d234c89-a8ac-4a72-844a-ad755f81d408
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1385492779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1385492779
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.1259220615
Short name T2467
Test name
Test status
Simulation time 237014898 ps
CPU time 0.88 seconds
Started Jun 24 05:24:41 PM PDT 24
Finished Jun 24 05:24:46 PM PDT 24
Peak memory 205424 kb
Host smart-2b0e7f85-b9ab-49df-9b7a-9b1d70260ba2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1259220615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.1259220615
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.305305439
Short name T1958
Test name
Test status
Simulation time 229745986 ps
CPU time 0.92 seconds
Started Jun 24 05:24:37 PM PDT 24
Finished Jun 24 05:24:42 PM PDT 24
Peak memory 206196 kb
Host smart-7dc53ef6-8508-4c96-adc8-0c1a57c25651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30530
5439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.305305439
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.1677272405
Short name T1063
Test name
Test status
Simulation time 12892657741 ps
CPU time 121.62 seconds
Started Jun 24 05:24:36 PM PDT 24
Finished Jun 24 05:26:41 PM PDT 24
Peak memory 206216 kb
Host smart-bd0baae7-4886-4103-9a18-bb70110278bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16772
72405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.1677272405
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.2293842891
Short name T687
Test name
Test status
Simulation time 3479847751 ps
CPU time 25.38 seconds
Started Jun 24 05:24:35 PM PDT 24
Finished Jun 24 05:25:04 PM PDT 24
Peak memory 206416 kb
Host smart-8379cb94-55d8-4c66-a9a8-ce1caac1ffd7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2293842891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.2293842891
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.4168903101
Short name T831
Test name
Test status
Simulation time 156111125 ps
CPU time 0.78 seconds
Started Jun 24 05:24:42 PM PDT 24
Finished Jun 24 05:24:47 PM PDT 24
Peak memory 206084 kb
Host smart-f93cbe54-69ad-49cd-8cbf-ea8a9592bc2e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4168903101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.4168903101
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1306050403
Short name T1815
Test name
Test status
Simulation time 148272409 ps
CPU time 0.76 seconds
Started Jun 24 05:24:36 PM PDT 24
Finished Jun 24 05:24:40 PM PDT 24
Peak memory 206180 kb
Host smart-bcbcec51-a579-4d4c-9739-a558982f3119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13060
50403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1306050403
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2474948684
Short name T139
Test name
Test status
Simulation time 205946833 ps
CPU time 0.85 seconds
Started Jun 24 05:24:38 PM PDT 24
Finished Jun 24 05:24:43 PM PDT 24
Peak memory 206160 kb
Host smart-dd1e96d5-302b-43bc-af64-e7e42aa7a089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24749
48684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2474948684
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.3410848755
Short name T1269
Test name
Test status
Simulation time 153731820 ps
CPU time 0.78 seconds
Started Jun 24 05:24:41 PM PDT 24
Finished Jun 24 05:24:46 PM PDT 24
Peak memory 206140 kb
Host smart-be1ac160-29d1-4087-8927-e93fbf3034bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34108
48755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3410848755
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.474038405
Short name T253
Test name
Test status
Simulation time 173487771 ps
CPU time 0.8 seconds
Started Jun 24 05:24:40 PM PDT 24
Finished Jun 24 05:24:44 PM PDT 24
Peak memory 206168 kb
Host smart-c537eabb-251c-405e-85b4-d416856d37dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47403
8405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.474038405
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.471512786
Short name T316
Test name
Test status
Simulation time 210728954 ps
CPU time 0.86 seconds
Started Jun 24 05:24:44 PM PDT 24
Finished Jun 24 05:24:50 PM PDT 24
Peak memory 206340 kb
Host smart-e6cb3a21-4eb6-467f-aeca-2b30f7d9d4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47151
2786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.471512786
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.4014495532
Short name T89
Test name
Test status
Simulation time 159862686 ps
CPU time 0.79 seconds
Started Jun 24 05:24:40 PM PDT 24
Finished Jun 24 05:24:45 PM PDT 24
Peak memory 206152 kb
Host smart-69372b89-8180-45e7-8f5b-578a26f6d4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40144
95532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.4014495532
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1751643115
Short name T1800
Test name
Test status
Simulation time 213497568 ps
CPU time 0.87 seconds
Started Jun 24 05:24:44 PM PDT 24
Finished Jun 24 05:24:50 PM PDT 24
Peak memory 206356 kb
Host smart-f5c9e67e-cba7-48c5-b37c-0018b85e48fb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1751643115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1751643115
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.833499217
Short name T309
Test name
Test status
Simulation time 183192547 ps
CPU time 0.82 seconds
Started Jun 24 05:24:39 PM PDT 24
Finished Jun 24 05:24:44 PM PDT 24
Peak memory 206072 kb
Host smart-8acb54db-7bca-4a56-a3bc-8238dac0e3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83349
9217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.833499217
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3319396833
Short name T536
Test name
Test status
Simulation time 90991573 ps
CPU time 0.74 seconds
Started Jun 24 05:24:39 PM PDT 24
Finished Jun 24 05:24:44 PM PDT 24
Peak memory 206144 kb
Host smart-a30f2024-f5e1-4d43-ae80-f95e398a46db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33193
96833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3319396833
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.4191217791
Short name T256
Test name
Test status
Simulation time 7166115174 ps
CPU time 15.33 seconds
Started Jun 24 05:24:41 PM PDT 24
Finished Jun 24 05:25:00 PM PDT 24
Peak memory 206320 kb
Host smart-0b91ab6a-ce79-4617-940c-698dee8ae755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41912
17791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.4191217791
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.871006543
Short name T2152
Test name
Test status
Simulation time 175972227 ps
CPU time 0.87 seconds
Started Jun 24 05:24:40 PM PDT 24
Finished Jun 24 05:24:45 PM PDT 24
Peak memory 206176 kb
Host smart-4df7ca59-02ee-47eb-85a6-0c1671ab5dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87100
6543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.871006543
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.854086086
Short name T1630
Test name
Test status
Simulation time 228691029 ps
CPU time 0.92 seconds
Started Jun 24 05:24:40 PM PDT 24
Finished Jun 24 05:24:45 PM PDT 24
Peak memory 206160 kb
Host smart-8b6ede82-d8ca-4032-afef-ad72b23f4b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85408
6086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.854086086
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.1191791089
Short name T479
Test name
Test status
Simulation time 283626095 ps
CPU time 1.02 seconds
Started Jun 24 05:24:41 PM PDT 24
Finished Jun 24 05:24:45 PM PDT 24
Peak memory 206200 kb
Host smart-ac7acf40-3953-4b48-b458-3b04ea4cda25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11917
91089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.1191791089
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.1056358251
Short name T709
Test name
Test status
Simulation time 196911964 ps
CPU time 0.84 seconds
Started Jun 24 05:24:43 PM PDT 24
Finished Jun 24 05:24:48 PM PDT 24
Peak memory 206192 kb
Host smart-cd92b932-7ef4-453a-b47c-b24a4df9b3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10563
58251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.1056358251
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1656543835
Short name T1386
Test name
Test status
Simulation time 140686661 ps
CPU time 0.77 seconds
Started Jun 24 05:24:42 PM PDT 24
Finished Jun 24 05:24:47 PM PDT 24
Peak memory 206088 kb
Host smart-3144f0de-956e-4f17-980b-f40fa8087926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16565
43835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1656543835
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.733704392
Short name T837
Test name
Test status
Simulation time 158016896 ps
CPU time 0.77 seconds
Started Jun 24 05:24:40 PM PDT 24
Finished Jun 24 05:24:45 PM PDT 24
Peak memory 206196 kb
Host smart-b36a3966-691b-484c-b26e-93c8f7254952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73370
4392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.733704392
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2610224819
Short name T534
Test name
Test status
Simulation time 188752402 ps
CPU time 0.81 seconds
Started Jun 24 05:24:40 PM PDT 24
Finished Jun 24 05:24:45 PM PDT 24
Peak memory 206096 kb
Host smart-34a28a58-4caf-4992-92da-8962446fd1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26102
24819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2610224819
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1260264590
Short name T1496
Test name
Test status
Simulation time 250471584 ps
CPU time 0.91 seconds
Started Jun 24 05:24:40 PM PDT 24
Finished Jun 24 05:24:45 PM PDT 24
Peak memory 206176 kb
Host smart-cafd7b03-e7b8-49fd-91db-aa921042d301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12602
64590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1260264590
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.1277641810
Short name T756
Test name
Test status
Simulation time 9046832592 ps
CPU time 62.57 seconds
Started Jun 24 05:24:42 PM PDT 24
Finished Jun 24 05:25:49 PM PDT 24
Peak memory 206300 kb
Host smart-b4c0ba59-6d54-4d7f-8ce5-5edaedb56fef
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1277641810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.1277641810
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.3222566678
Short name T2031
Test name
Test status
Simulation time 180572821 ps
CPU time 0.79 seconds
Started Jun 24 05:24:37 PM PDT 24
Finished Jun 24 05:24:42 PM PDT 24
Peak memory 206104 kb
Host smart-390081a3-f112-451e-8d98-d3dad62f0250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32225
66678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.3222566678
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2138058704
Short name T29
Test name
Test status
Simulation time 173387358 ps
CPU time 0.81 seconds
Started Jun 24 05:24:38 PM PDT 24
Finished Jun 24 05:24:43 PM PDT 24
Peak memory 206188 kb
Host smart-1d6ca073-9f4a-44a2-bd0c-398365555c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21380
58704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2138058704
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.19248726
Short name T2369
Test name
Test status
Simulation time 4592805743 ps
CPU time 121.38 seconds
Started Jun 24 05:24:38 PM PDT 24
Finished Jun 24 05:26:43 PM PDT 24
Peak memory 206364 kb
Host smart-c1709d47-7292-4dac-a2d0-8bd4d478861f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19248
726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.19248726
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.3412728538
Short name T1799
Test name
Test status
Simulation time 4248413272 ps
CPU time 4.92 seconds
Started Jun 24 05:24:38 PM PDT 24
Finished Jun 24 05:24:47 PM PDT 24
Peak memory 206164 kb
Host smart-c0fc9850-f3c9-4fb5-9689-6badfceda159
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3412728538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.3412728538
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2023819244
Short name T1467
Test name
Test status
Simulation time 13332792865 ps
CPU time 15.53 seconds
Started Jun 24 05:24:43 PM PDT 24
Finished Jun 24 05:25:03 PM PDT 24
Peak memory 206552 kb
Host smart-f3da9ddf-69ef-4173-ad55-96bc5d883c48
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2023819244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2023819244
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.832197003
Short name T599
Test name
Test status
Simulation time 23369962637 ps
CPU time 23.25 seconds
Started Jun 24 05:24:41 PM PDT 24
Finished Jun 24 05:25:08 PM PDT 24
Peak memory 206316 kb
Host smart-8d55d125-794e-49b5-bf69-1d1181a2e953
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=832197003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.832197003
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1722416268
Short name T161
Test name
Test status
Simulation time 168040806 ps
CPU time 0.81 seconds
Started Jun 24 05:24:40 PM PDT 24
Finished Jun 24 05:24:45 PM PDT 24
Peak memory 206176 kb
Host smart-6ef37d3c-cd0e-4b1f-b7e3-efac61b2b503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17224
16268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1722416268
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.4292175098
Short name T834
Test name
Test status
Simulation time 151389350 ps
CPU time 0.74 seconds
Started Jun 24 05:24:43 PM PDT 24
Finished Jun 24 05:24:49 PM PDT 24
Peak memory 206344 kb
Host smart-b7f7653b-d276-4705-9bca-635d32d5f650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42921
75098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.4292175098
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2794045160
Short name T114
Test name
Test status
Simulation time 343375315 ps
CPU time 1.15 seconds
Started Jun 24 05:24:39 PM PDT 24
Finished Jun 24 05:24:44 PM PDT 24
Peak memory 206104 kb
Host smart-b73cdb33-4633-4e6a-9025-9181c0dc8ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27940
45160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2794045160
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3524071739
Short name T1157
Test name
Test status
Simulation time 858308656 ps
CPU time 2.04 seconds
Started Jun 24 05:24:43 PM PDT 24
Finished Jun 24 05:24:49 PM PDT 24
Peak memory 206128 kb
Host smart-02062ec4-2661-4801-8d49-fcb293fc966c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35240
71739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3524071739
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.3438583533
Short name T774
Test name
Test status
Simulation time 18083039450 ps
CPU time 34.68 seconds
Started Jun 24 05:24:39 PM PDT 24
Finished Jun 24 05:25:17 PM PDT 24
Peak memory 206388 kb
Host smart-15a477b7-2f35-4ab8-889f-914c61263a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34385
83533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.3438583533
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.384057640
Short name T1020
Test name
Test status
Simulation time 156057844 ps
CPU time 0.87 seconds
Started Jun 24 05:24:39 PM PDT 24
Finished Jun 24 05:24:44 PM PDT 24
Peak memory 206100 kb
Host smart-5c5c5f68-9b33-4d2b-a4eb-4b7068c796c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38405
7640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.384057640
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.3287980431
Short name T1707
Test name
Test status
Simulation time 41201408 ps
CPU time 0.68 seconds
Started Jun 24 05:24:47 PM PDT 24
Finished Jun 24 05:24:52 PM PDT 24
Peak memory 206088 kb
Host smart-bcd3d40f-a096-42f5-b306-53b17fa2d27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32879
80431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3287980431
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.1399620336
Short name T1443
Test name
Test status
Simulation time 799988011 ps
CPU time 1.91 seconds
Started Jun 24 05:24:51 PM PDT 24
Finished Jun 24 05:24:59 PM PDT 24
Peak memory 206256 kb
Host smart-e401f98b-3ef8-4b3e-9596-9a0154d86120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13996
20336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.1399620336
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.4138841999
Short name T23
Test name
Test status
Simulation time 322556162 ps
CPU time 1.87 seconds
Started Jun 24 05:24:48 PM PDT 24
Finished Jun 24 05:24:54 PM PDT 24
Peak memory 206220 kb
Host smart-5a31c379-8748-4d15-93d9-31e5fbe2f375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41388
41999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.4138841999
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.3598040259
Short name T2066
Test name
Test status
Simulation time 189091140 ps
CPU time 0.87 seconds
Started Jun 24 05:24:47 PM PDT 24
Finished Jun 24 05:24:52 PM PDT 24
Peak memory 206160 kb
Host smart-74cd8430-4db5-41ad-bc87-4f8502280abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35980
40259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3598040259
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.86594596
Short name T1917
Test name
Test status
Simulation time 147381272 ps
CPU time 0.77 seconds
Started Jun 24 05:24:49 PM PDT 24
Finished Jun 24 05:24:55 PM PDT 24
Peak memory 206188 kb
Host smart-0ddece36-8351-4fa9-ac6a-338344b27967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86594
596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.86594596
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2635598207
Short name T691
Test name
Test status
Simulation time 227653942 ps
CPU time 0.91 seconds
Started Jun 24 05:24:57 PM PDT 24
Finished Jun 24 05:25:05 PM PDT 24
Peak memory 206148 kb
Host smart-1ab26400-a444-42e6-a227-d88a263bda93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26355
98207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2635598207
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.2040096124
Short name T234
Test name
Test status
Simulation time 5140145055 ps
CPU time 48.67 seconds
Started Jun 24 05:24:52 PM PDT 24
Finished Jun 24 05:25:46 PM PDT 24
Peak memory 206188 kb
Host smart-1aa35017-b205-4742-9029-a53c1d20ac93
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2040096124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.2040096124
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.668803828
Short name T1379
Test name
Test status
Simulation time 163864784 ps
CPU time 0.89 seconds
Started Jun 24 05:24:49 PM PDT 24
Finished Jun 24 05:24:54 PM PDT 24
Peak memory 206076 kb
Host smart-24ec8b6f-6d4b-49cb-846b-21686e6886fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66880
3828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.668803828
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.3778200463
Short name T1758
Test name
Test status
Simulation time 23312631830 ps
CPU time 27.48 seconds
Started Jun 24 05:24:57 PM PDT 24
Finished Jun 24 05:25:31 PM PDT 24
Peak memory 206208 kb
Host smart-c692942c-0b22-4166-99be-87d1469a37a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37782
00463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.3778200463
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.1209762840
Short name T874
Test name
Test status
Simulation time 3324353957 ps
CPU time 4.62 seconds
Started Jun 24 05:24:46 PM PDT 24
Finished Jun 24 05:24:55 PM PDT 24
Peak memory 206164 kb
Host smart-66638565-d7ba-4652-bd5f-41fb69e72024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12097
62840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1209762840
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.2321647243
Short name T88
Test name
Test status
Simulation time 11465218113 ps
CPU time 316.02 seconds
Started Jun 24 05:24:50 PM PDT 24
Finished Jun 24 05:30:10 PM PDT 24
Peak memory 206316 kb
Host smart-90d48c20-cd9d-475b-b51e-ac128d76aed8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2321647243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.2321647243
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.1762653795
Short name T2097
Test name
Test status
Simulation time 342873725 ps
CPU time 0.97 seconds
Started Jun 24 05:24:57 PM PDT 24
Finished Jun 24 05:25:05 PM PDT 24
Peak memory 206152 kb
Host smart-f9cd6e5e-7b87-48be-8089-fe57ed6324b1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1762653795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.1762653795
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2872519997
Short name T2064
Test name
Test status
Simulation time 182256732 ps
CPU time 0.89 seconds
Started Jun 24 05:24:46 PM PDT 24
Finished Jun 24 05:24:51 PM PDT 24
Peak memory 206180 kb
Host smart-46c41466-6d95-47d4-848f-f4ad7d639437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28725
19997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2872519997
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.1634855248
Short name T1372
Test name
Test status
Simulation time 13722980735 ps
CPU time 94.56 seconds
Started Jun 24 05:24:49 PM PDT 24
Finished Jun 24 05:26:28 PM PDT 24
Peak memory 206280 kb
Host smart-f8bc1fc7-e13e-4d3c-a033-b3fa91ed059b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16348
55248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.1634855248
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.3407621273
Short name T683
Test name
Test status
Simulation time 4900916493 ps
CPU time 46.81 seconds
Started Jun 24 05:24:50 PM PDT 24
Finished Jun 24 05:25:42 PM PDT 24
Peak memory 206424 kb
Host smart-5d1dd3b6-43f1-4ce9-8c40-1815f02585d3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3407621273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.3407621273
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.1595541034
Short name T707
Test name
Test status
Simulation time 163534553 ps
CPU time 0.81 seconds
Started Jun 24 05:24:51 PM PDT 24
Finished Jun 24 05:24:57 PM PDT 24
Peak memory 206176 kb
Host smart-4d6d9e83-d1fd-41e6-8daa-11a8a6c69a75
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1595541034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.1595541034
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3864826312
Short name T2086
Test name
Test status
Simulation time 141174329 ps
CPU time 0.82 seconds
Started Jun 24 05:24:47 PM PDT 24
Finished Jun 24 05:24:53 PM PDT 24
Peak memory 206148 kb
Host smart-7f7280db-03a3-48af-bb75-5f9cc6216da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38648
26312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3864826312
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.638728101
Short name T141
Test name
Test status
Simulation time 222490692 ps
CPU time 0.94 seconds
Started Jun 24 05:24:49 PM PDT 24
Finished Jun 24 05:24:54 PM PDT 24
Peak memory 205868 kb
Host smart-2883a06c-2355-4685-abb8-a049cfa2e59b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63872
8101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.638728101
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.2486116855
Short name T2161
Test name
Test status
Simulation time 204807051 ps
CPU time 0.97 seconds
Started Jun 24 05:24:48 PM PDT 24
Finished Jun 24 05:24:53 PM PDT 24
Peak memory 206172 kb
Host smart-d27f21c7-f89a-4113-9c57-e7f86a89be12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24861
16855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.2486116855
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1412703654
Short name T307
Test name
Test status
Simulation time 170264237 ps
CPU time 0.83 seconds
Started Jun 24 05:24:47 PM PDT 24
Finished Jun 24 05:24:52 PM PDT 24
Peak memory 206172 kb
Host smart-5ca97883-e9be-4c89-82e4-7ccbb324c0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14127
03654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1412703654
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1905179298
Short name T2459
Test name
Test status
Simulation time 179337933 ps
CPU time 0.82 seconds
Started Jun 24 05:24:48 PM PDT 24
Finished Jun 24 05:24:53 PM PDT 24
Peak memory 206192 kb
Host smart-2951fa18-d97d-4d6a-9536-8ca44667b623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19051
79298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1905179298
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3955023935
Short name T188
Test name
Test status
Simulation time 195814635 ps
CPU time 0.85 seconds
Started Jun 24 05:24:49 PM PDT 24
Finished Jun 24 05:24:54 PM PDT 24
Peak memory 206064 kb
Host smart-421fd00f-3f7f-4e79-bf64-347e556f3016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39550
23935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3955023935
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2552301349
Short name T1541
Test name
Test status
Simulation time 250191711 ps
CPU time 1.01 seconds
Started Jun 24 05:24:51 PM PDT 24
Finished Jun 24 05:24:57 PM PDT 24
Peak memory 206160 kb
Host smart-b2ff0262-c70c-41ce-82bd-9f8be906e7c5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2552301349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2552301349
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.64442946
Short name T483
Test name
Test status
Simulation time 147974306 ps
CPU time 0.8 seconds
Started Jun 24 05:24:50 PM PDT 24
Finished Jun 24 05:24:55 PM PDT 24
Peak memory 206188 kb
Host smart-a512078e-0d42-4d4a-8479-54adfeb2883b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64442
946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.64442946
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.1145396565
Short name T558
Test name
Test status
Simulation time 44426681 ps
CPU time 0.7 seconds
Started Jun 24 05:24:46 PM PDT 24
Finished Jun 24 05:24:51 PM PDT 24
Peak memory 206188 kb
Host smart-44c6663a-998c-4dd6-a0f5-015a72f304c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11453
96565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1145396565
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3172374195
Short name T1482
Test name
Test status
Simulation time 16447341183 ps
CPU time 33.9 seconds
Started Jun 24 05:24:47 PM PDT 24
Finished Jun 24 05:25:26 PM PDT 24
Peak memory 206512 kb
Host smart-636eae28-46d5-421f-ae6c-20279aa208ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31723
74195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3172374195
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2514984335
Short name T743
Test name
Test status
Simulation time 229117587 ps
CPU time 0.86 seconds
Started Jun 24 05:24:57 PM PDT 24
Finished Jun 24 05:25:04 PM PDT 24
Peak memory 206092 kb
Host smart-c87d1374-b8a5-41b1-81d3-342aa6e94bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25149
84335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2514984335
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.376422949
Short name T1178
Test name
Test status
Simulation time 183001705 ps
CPU time 0.87 seconds
Started Jun 24 05:24:57 PM PDT 24
Finished Jun 24 05:25:04 PM PDT 24
Peak memory 206136 kb
Host smart-5129868b-efaf-4c1e-bd06-6470ecf0840f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37642
2949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.376422949
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.1802767233
Short name T547
Test name
Test status
Simulation time 257883311 ps
CPU time 0.93 seconds
Started Jun 24 05:24:51 PM PDT 24
Finished Jun 24 05:24:57 PM PDT 24
Peak memory 206076 kb
Host smart-a8921dac-3b3a-42e3-82cd-fd3952af1f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18027
67233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.1802767233
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.215311204
Short name T2326
Test name
Test status
Simulation time 179770614 ps
CPU time 0.84 seconds
Started Jun 24 05:24:49 PM PDT 24
Finished Jun 24 05:24:54 PM PDT 24
Peak memory 206148 kb
Host smart-d93a7026-c423-4654-9a3a-fe839a4de72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21531
1204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.215311204
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.2273591390
Short name T2256
Test name
Test status
Simulation time 153987029 ps
CPU time 0.77 seconds
Started Jun 24 05:24:48 PM PDT 24
Finished Jun 24 05:24:54 PM PDT 24
Peak memory 206188 kb
Host smart-89013e9c-def2-4532-b98e-62251767036f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22735
91390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.2273591390
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.2935811434
Short name T1116
Test name
Test status
Simulation time 150123670 ps
CPU time 0.74 seconds
Started Jun 24 05:24:50 PM PDT 24
Finished Jun 24 05:24:55 PM PDT 24
Peak memory 206176 kb
Host smart-6e4083d6-618c-44d2-841b-8f90e4d8c4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29358
11434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.2935811434
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1952114144
Short name T613
Test name
Test status
Simulation time 150853733 ps
CPU time 0.8 seconds
Started Jun 24 05:24:48 PM PDT 24
Finished Jun 24 05:24:53 PM PDT 24
Peak memory 206172 kb
Host smart-b0661ea6-60d2-4c72-8622-79dcf7a902c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19521
14144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1952114144
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.485802442
Short name T1598
Test name
Test status
Simulation time 206535395 ps
CPU time 0.9 seconds
Started Jun 24 05:24:47 PM PDT 24
Finished Jun 24 05:24:52 PM PDT 24
Peak memory 206192 kb
Host smart-38c2140e-0dc5-47a2-b806-726737d6725e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48580
2442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.485802442
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.2013634599
Short name T2273
Test name
Test status
Simulation time 10619878334 ps
CPU time 74.89 seconds
Started Jun 24 05:24:50 PM PDT 24
Finished Jun 24 05:26:09 PM PDT 24
Peak memory 206284 kb
Host smart-a239bdfb-7823-4161-a241-b90d0b11bef4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2013634599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2013634599
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.87912296
Short name T2237
Test name
Test status
Simulation time 158079143 ps
CPU time 0.79 seconds
Started Jun 24 05:24:53 PM PDT 24
Finished Jun 24 05:25:00 PM PDT 24
Peak memory 206196 kb
Host smart-f45f871e-54c1-49ca-a2ac-b96c5d32b4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87912
296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.87912296
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2832667142
Short name T1660
Test name
Test status
Simulation time 226819895 ps
CPU time 0.84 seconds
Started Jun 24 05:24:47 PM PDT 24
Finished Jun 24 05:24:52 PM PDT 24
Peak memory 206184 kb
Host smart-4cc0a234-a3b2-4c06-8660-8fc463a5a44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28326
67142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2832667142
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.4239373427
Short name T745
Test name
Test status
Simulation time 11712150462 ps
CPU time 324.92 seconds
Started Jun 24 05:24:46 PM PDT 24
Finished Jun 24 05:30:15 PM PDT 24
Peak memory 206288 kb
Host smart-e557fa91-3189-4601-83fc-b0d87596fb9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42393
73427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.4239373427
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.512970154
Short name T1822
Test name
Test status
Simulation time 4296753424 ps
CPU time 5.09 seconds
Started Jun 24 05:24:48 PM PDT 24
Finished Jun 24 05:24:58 PM PDT 24
Peak memory 206316 kb
Host smart-758d0ca4-78b4-4c9a-a47c-48ee22817d9d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=512970154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.512970154
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.2321998611
Short name T1136
Test name
Test status
Simulation time 13355434911 ps
CPU time 11.74 seconds
Started Jun 24 05:24:50 PM PDT 24
Finished Jun 24 05:25:07 PM PDT 24
Peak memory 206288 kb
Host smart-fb6f4f1f-9dc9-4570-8182-4d6300d89937
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2321998611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.2321998611
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.1225035280
Short name T230
Test name
Test status
Simulation time 23340467572 ps
CPU time 21.57 seconds
Started Jun 24 05:24:51 PM PDT 24
Finished Jun 24 05:25:18 PM PDT 24
Peak memory 206340 kb
Host smart-8d8f9518-5768-4fab-9248-116817c3a505
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1225035280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.1225035280
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2219020822
Short name T714
Test name
Test status
Simulation time 161016014 ps
CPU time 0.77 seconds
Started Jun 24 05:24:49 PM PDT 24
Finished Jun 24 05:24:54 PM PDT 24
Peak memory 206180 kb
Host smart-ca478d61-3506-4d0d-8fa0-d612dfbfac62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22190
20822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2219020822
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.202724647
Short name T1582
Test name
Test status
Simulation time 175592749 ps
CPU time 0.8 seconds
Started Jun 24 05:24:51 PM PDT 24
Finished Jun 24 05:24:58 PM PDT 24
Peak memory 206168 kb
Host smart-c2b76136-16e9-4fed-ae6b-fe617260848b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20272
4647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.202724647
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.3905846978
Short name T775
Test name
Test status
Simulation time 236255620 ps
CPU time 0.87 seconds
Started Jun 24 05:24:53 PM PDT 24
Finished Jun 24 05:25:00 PM PDT 24
Peak memory 206152 kb
Host smart-64210f16-5066-4684-87cc-f83ae1f1551d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39058
46978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.3905846978
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.4041107336
Short name T1807
Test name
Test status
Simulation time 318046091 ps
CPU time 1.02 seconds
Started Jun 24 05:24:56 PM PDT 24
Finished Jun 24 05:25:03 PM PDT 24
Peak memory 206172 kb
Host smart-108f5831-d8ad-4a0a-ad82-ba12f2f804e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40411
07336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.4041107336
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.1056606814
Short name T1245
Test name
Test status
Simulation time 5977063404 ps
CPU time 12.05 seconds
Started Jun 24 05:24:52 PM PDT 24
Finished Jun 24 05:25:09 PM PDT 24
Peak memory 206380 kb
Host smart-7e4990f3-35c0-4418-bab7-b2fe3d0a5623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10566
06814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.1056606814
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.714230574
Short name T1772
Test name
Test status
Simulation time 477386150 ps
CPU time 1.31 seconds
Started Jun 24 05:24:49 PM PDT 24
Finished Jun 24 05:24:55 PM PDT 24
Peak memory 206152 kb
Host smart-c18a7278-0fad-4a94-b07e-ca8ea740daf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71423
0574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.714230574
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.512240948
Short name T1964
Test name
Test status
Simulation time 141528803 ps
CPU time 0.75 seconds
Started Jun 24 05:24:53 PM PDT 24
Finished Jun 24 05:25:00 PM PDT 24
Peak memory 206164 kb
Host smart-52bbd293-1ee6-4506-be98-e1328fe4021c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51224
0948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.512240948
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3902186033
Short name T2396
Test name
Test status
Simulation time 83194462 ps
CPU time 0.69 seconds
Started Jun 24 05:24:49 PM PDT 24
Finished Jun 24 05:24:55 PM PDT 24
Peak memory 206100 kb
Host smart-6c74f12c-e889-4ec4-85e3-1a7e3c38aae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39021
86033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3902186033
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1165544498
Short name T1240
Test name
Test status
Simulation time 783122968 ps
CPU time 2.12 seconds
Started Jun 24 05:24:53 PM PDT 24
Finished Jun 24 05:25:01 PM PDT 24
Peak memory 206272 kb
Host smart-775981ec-354a-4793-8419-4689c9a8be5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11655
44498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1165544498
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2110765258
Short name T1014
Test name
Test status
Simulation time 327664152 ps
CPU time 2.02 seconds
Started Jun 24 05:24:51 PM PDT 24
Finished Jun 24 05:24:58 PM PDT 24
Peak memory 206152 kb
Host smart-f3ddbf97-da57-4e60-82c1-7da2721e5938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21107
65258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2110765258
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.3408367065
Short name T464
Test name
Test status
Simulation time 185549812 ps
CPU time 0.88 seconds
Started Jun 24 05:24:56 PM PDT 24
Finished Jun 24 05:25:04 PM PDT 24
Peak memory 206176 kb
Host smart-1e26e4e3-d36b-45d1-b106-5a73032dbcd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34083
67065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3408367065
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.964602132
Short name T433
Test name
Test status
Simulation time 139534632 ps
CPU time 0.76 seconds
Started Jun 24 05:24:56 PM PDT 24
Finished Jun 24 05:25:04 PM PDT 24
Peak memory 206424 kb
Host smart-1131593f-7fa5-4ebb-ba1c-1f970729fe42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96460
2132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.964602132
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.1439177482
Short name T422
Test name
Test status
Simulation time 171882426 ps
CPU time 0.78 seconds
Started Jun 24 05:24:46 PM PDT 24
Finished Jun 24 05:24:51 PM PDT 24
Peak memory 206164 kb
Host smart-7995159f-bb6c-4813-81de-196c625886e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14391
77482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.1439177482
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2121359658
Short name T1005
Test name
Test status
Simulation time 201950863 ps
CPU time 0.85 seconds
Started Jun 24 05:24:56 PM PDT 24
Finished Jun 24 05:25:03 PM PDT 24
Peak memory 206108 kb
Host smart-7b33852f-0788-46c9-be58-81554eaa4bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21213
59658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2121359658
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.1370231808
Short name T851
Test name
Test status
Simulation time 23321146344 ps
CPU time 21.77 seconds
Started Jun 24 05:24:54 PM PDT 24
Finished Jun 24 05:25:22 PM PDT 24
Peak memory 206260 kb
Host smart-9e33703e-5a96-486b-8885-816bc31d0ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13702
31808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.1370231808
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.2469384844
Short name T1408
Test name
Test status
Simulation time 3294151892 ps
CPU time 3.88 seconds
Started Jun 24 05:24:54 PM PDT 24
Finished Jun 24 05:25:04 PM PDT 24
Peak memory 206240 kb
Host smart-8e0a08b2-b682-446c-9390-41731aa2b176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24693
84844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.2469384844
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2509601206
Short name T1207
Test name
Test status
Simulation time 3939356399 ps
CPU time 38.09 seconds
Started Jun 24 05:24:58 PM PDT 24
Finished Jun 24 05:25:42 PM PDT 24
Peak memory 206252 kb
Host smart-5c23c879-7ce3-4f7a-a122-25b7529d53e3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2509601206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2509601206
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.3994742727
Short name T493
Test name
Test status
Simulation time 243708393 ps
CPU time 0.94 seconds
Started Jun 24 05:25:05 PM PDT 24
Finished Jun 24 05:25:08 PM PDT 24
Peak memory 206196 kb
Host smart-11ac245d-dd81-447c-a7b1-886707a20156
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3994742727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.3994742727
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1126964388
Short name T2302
Test name
Test status
Simulation time 235893735 ps
CPU time 0.94 seconds
Started Jun 24 05:24:56 PM PDT 24
Finished Jun 24 05:25:03 PM PDT 24
Peak memory 206132 kb
Host smart-8e9ef437-9e3e-4c0c-b785-a085e135bfde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11269
64388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1126964388
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.3035319659
Short name T1841
Test name
Test status
Simulation time 8203131838 ps
CPU time 57.29 seconds
Started Jun 24 05:24:53 PM PDT 24
Finished Jun 24 05:25:56 PM PDT 24
Peak memory 206376 kb
Host smart-6dcf5750-36b9-45d6-a294-b8da8e76cd5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30353
19659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.3035319659
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.552517119
Short name T586
Test name
Test status
Simulation time 13577101846 ps
CPU time 392.85 seconds
Started Jun 24 05:24:56 PM PDT 24
Finished Jun 24 05:31:35 PM PDT 24
Peak memory 206384 kb
Host smart-306eeda6-200a-4a33-907a-77631adc4ae8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=552517119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.552517119
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.1597236351
Short name T221
Test name
Test status
Simulation time 175414253 ps
CPU time 0.9 seconds
Started Jun 24 05:24:56 PM PDT 24
Finished Jun 24 05:25:04 PM PDT 24
Peak memory 206096 kb
Host smart-17520409-1581-4432-891c-e547a8ddf53c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1597236351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.1597236351
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.434512059
Short name T1349
Test name
Test status
Simulation time 143924918 ps
CPU time 0.75 seconds
Started Jun 24 05:24:56 PM PDT 24
Finished Jun 24 05:25:03 PM PDT 24
Peak memory 206432 kb
Host smart-865fdce9-5aea-4184-9dcd-eb5a9b944874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43451
2059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.434512059
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.954225053
Short name T2395
Test name
Test status
Simulation time 234394523 ps
CPU time 0.9 seconds
Started Jun 24 05:24:53 PM PDT 24
Finished Jun 24 05:25:00 PM PDT 24
Peak memory 206140 kb
Host smart-45c82092-a275-44fe-b801-632205c61f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95422
5053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.954225053
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.3594390651
Short name T1213
Test name
Test status
Simulation time 241239841 ps
CPU time 0.87 seconds
Started Jun 24 05:24:54 PM PDT 24
Finished Jun 24 05:25:01 PM PDT 24
Peak memory 206164 kb
Host smart-ccf392df-dcb1-4ab0-8652-4c5ce41f7245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35943
90651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3594390651
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.4100554368
Short name T2348
Test name
Test status
Simulation time 204730092 ps
CPU time 0.85 seconds
Started Jun 24 05:24:57 PM PDT 24
Finished Jun 24 05:25:04 PM PDT 24
Peak memory 206176 kb
Host smart-066d3c4e-bfe5-4a5e-b2c3-4013e25d3391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41005
54368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.4100554368
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.4068018731
Short name T949
Test name
Test status
Simulation time 193366967 ps
CPU time 0.86 seconds
Started Jun 24 05:24:55 PM PDT 24
Finished Jun 24 05:25:01 PM PDT 24
Peak memory 206412 kb
Host smart-f71f32be-c7c2-4e82-bfa7-5d13336cb280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40680
18731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.4068018731
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3319882788
Short name T2497
Test name
Test status
Simulation time 155794951 ps
CPU time 0.77 seconds
Started Jun 24 05:24:54 PM PDT 24
Finished Jun 24 05:25:01 PM PDT 24
Peak memory 206180 kb
Host smart-8124f0d5-42e4-4be7-9101-082dfe4e2924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33198
82788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3319882788
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.723785088
Short name T2346
Test name
Test status
Simulation time 232463093 ps
CPU time 0.99 seconds
Started Jun 24 05:24:57 PM PDT 24
Finished Jun 24 05:25:04 PM PDT 24
Peak memory 206180 kb
Host smart-73d24a3f-d0d4-4b8c-bf28-0e09324b053f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=723785088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.723785088
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1296693302
Short name T712
Test name
Test status
Simulation time 143943472 ps
CPU time 0.74 seconds
Started Jun 24 05:24:55 PM PDT 24
Finished Jun 24 05:25:01 PM PDT 24
Peak memory 206160 kb
Host smart-e3e97de3-6896-407f-9e72-abbbd01f1dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12966
93302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1296693302
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.4026897031
Short name T2010
Test name
Test status
Simulation time 54329968 ps
CPU time 0.66 seconds
Started Jun 24 05:24:54 PM PDT 24
Finished Jun 24 05:25:00 PM PDT 24
Peak memory 206164 kb
Host smart-76d741ff-a683-45aa-9c0c-1daa8e2a30e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40268
97031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.4026897031
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2749458457
Short name T1418
Test name
Test status
Simulation time 7394798596 ps
CPU time 15.96 seconds
Started Jun 24 05:24:55 PM PDT 24
Finished Jun 24 05:25:16 PM PDT 24
Peak memory 206284 kb
Host smart-94bdb225-3fb1-47a8-b683-bf42a915c893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27494
58457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2749458457
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3527771978
Short name T749
Test name
Test status
Simulation time 193144672 ps
CPU time 0.93 seconds
Started Jun 24 05:24:58 PM PDT 24
Finished Jun 24 05:25:05 PM PDT 24
Peak memory 206176 kb
Host smart-e99688b0-16e6-42c4-922f-7e2e4f327f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35277
71978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3527771978
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.570726753
Short name T1166
Test name
Test status
Simulation time 229433392 ps
CPU time 0.95 seconds
Started Jun 24 05:24:56 PM PDT 24
Finished Jun 24 05:25:03 PM PDT 24
Peak memory 206188 kb
Host smart-8ac2545f-e85f-4c5f-a7ed-6e941d080406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57072
6753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.570726753
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.1413294748
Short name T713
Test name
Test status
Simulation time 227979521 ps
CPU time 0.92 seconds
Started Jun 24 05:24:56 PM PDT 24
Finished Jun 24 05:25:03 PM PDT 24
Peak memory 206104 kb
Host smart-4ecea57d-96ce-42d8-9d07-241e347c92c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14132
94748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.1413294748
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.2002942868
Short name T85
Test name
Test status
Simulation time 167000897 ps
CPU time 0.84 seconds
Started Jun 24 05:24:56 PM PDT 24
Finished Jun 24 05:25:03 PM PDT 24
Peak memory 206196 kb
Host smart-6f9e7638-8994-4e6e-b7ba-b23596eb3528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20029
42868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.2002942868
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.526177128
Short name T1374
Test name
Test status
Simulation time 183454957 ps
CPU time 0.82 seconds
Started Jun 24 05:24:54 PM PDT 24
Finished Jun 24 05:25:01 PM PDT 24
Peak memory 206152 kb
Host smart-0abeb69a-980d-46e0-93f4-0ebabc4f8d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52617
7128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.526177128
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.3937691090
Short name T2474
Test name
Test status
Simulation time 203601858 ps
CPU time 0.83 seconds
Started Jun 24 05:24:54 PM PDT 24
Finished Jun 24 05:25:01 PM PDT 24
Peak memory 206084 kb
Host smart-22e36409-c42d-4020-aaef-b54bea3c3596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39376
91090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.3937691090
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3347923107
Short name T752
Test name
Test status
Simulation time 158228979 ps
CPU time 0.79 seconds
Started Jun 24 05:24:54 PM PDT 24
Finished Jun 24 05:25:01 PM PDT 24
Peak memory 206168 kb
Host smart-42da1954-abe5-4e13-a347-08c668c15c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33479
23107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3347923107
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.1310945667
Short name T434
Test name
Test status
Simulation time 201679399 ps
CPU time 1.01 seconds
Started Jun 24 05:24:54 PM PDT 24
Finished Jun 24 05:25:01 PM PDT 24
Peak memory 206144 kb
Host smart-529e76fd-477e-46e5-97ee-03c6e576684d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13109
45667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1310945667
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.4147583045
Short name T86
Test name
Test status
Simulation time 5838418368 ps
CPU time 159.83 seconds
Started Jun 24 05:24:54 PM PDT 24
Finished Jun 24 05:27:39 PM PDT 24
Peak memory 206424 kb
Host smart-bb5630d9-4107-4e79-bcfd-8f160b9fb2a4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4147583045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.4147583045
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2419072962
Short name T1035
Test name
Test status
Simulation time 187125500 ps
CPU time 0.84 seconds
Started Jun 24 05:24:57 PM PDT 24
Finished Jun 24 05:25:04 PM PDT 24
Peak memory 206076 kb
Host smart-bbcd4620-9f0d-4593-85c5-d1eb7a7064ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24190
72962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2419072962
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.3732659279
Short name T481
Test name
Test status
Simulation time 168922798 ps
CPU time 0.84 seconds
Started Jun 24 05:24:56 PM PDT 24
Finished Jun 24 05:25:03 PM PDT 24
Peak memory 206124 kb
Host smart-43aab83d-5bf8-403b-87ab-87bc2ee169d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37326
59279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.3732659279
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3543361905
Short name T344
Test name
Test status
Simulation time 8860219632 ps
CPU time 90.96 seconds
Started Jun 24 05:24:56 PM PDT 24
Finished Jun 24 05:26:33 PM PDT 24
Peak memory 206344 kb
Host smart-e358cd41-45d0-45f6-b076-3ed20166df6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35433
61905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3543361905
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.365614674
Short name T2443
Test name
Test status
Simulation time 3680812760 ps
CPU time 4.89 seconds
Started Jun 24 05:25:03 PM PDT 24
Finished Jun 24 05:25:12 PM PDT 24
Peak memory 206256 kb
Host smart-6c393e6c-c7b2-4618-b514-6fea15e47fef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=365614674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.365614674
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.1666184984
Short name T2240
Test name
Test status
Simulation time 13368667723 ps
CPU time 11.3 seconds
Started Jun 24 05:25:06 PM PDT 24
Finished Jun 24 05:25:20 PM PDT 24
Peak memory 206292 kb
Host smart-4104290d-aa4e-4733-b685-857e915a3b02
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1666184984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.1666184984
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.671394584
Short name T1003
Test name
Test status
Simulation time 23520773197 ps
CPU time 23.48 seconds
Started Jun 24 05:25:07 PM PDT 24
Finished Jun 24 05:25:32 PM PDT 24
Peak memory 206292 kb
Host smart-4dc3c34e-f91d-4e6a-8fd3-8b0e20cf2105
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=671394584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.671394584
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.369930117
Short name T1844
Test name
Test status
Simulation time 156570492 ps
CPU time 0.85 seconds
Started Jun 24 05:25:06 PM PDT 24
Finished Jun 24 05:25:10 PM PDT 24
Peak memory 206176 kb
Host smart-ad0344ea-eec7-4b82-8f57-fda1fe9bdf33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36993
0117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.369930117
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.1457777680
Short name T1484
Test name
Test status
Simulation time 144884615 ps
CPU time 0.76 seconds
Started Jun 24 05:25:03 PM PDT 24
Finished Jun 24 05:25:07 PM PDT 24
Peak memory 206172 kb
Host smart-181e3a62-4f6b-4a08-9ec6-00c1790e78d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14577
77680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.1457777680
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3237402453
Short name T1499
Test name
Test status
Simulation time 416736528 ps
CPU time 1.28 seconds
Started Jun 24 05:25:03 PM PDT 24
Finished Jun 24 05:25:08 PM PDT 24
Peak memory 206124 kb
Host smart-c32158ce-58e0-49e8-99e7-64e289d8d10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32374
02453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3237402453
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.3637257222
Short name T168
Test name
Test status
Simulation time 1141087528 ps
CPU time 2.49 seconds
Started Jun 24 05:25:03 PM PDT 24
Finished Jun 24 05:25:09 PM PDT 24
Peak memory 206216 kb
Host smart-94bf4c26-ade4-41ab-bdb5-93119e7979d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36372
57222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3637257222
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.1242184523
Short name T1110
Test name
Test status
Simulation time 10255597113 ps
CPU time 19.13 seconds
Started Jun 24 05:25:04 PM PDT 24
Finished Jun 24 05:25:26 PM PDT 24
Peak memory 206276 kb
Host smart-b9a56689-3e88-4748-94d2-329f5ac441d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12421
84523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.1242184523
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.331197858
Short name T854
Test name
Test status
Simulation time 490174490 ps
CPU time 1.39 seconds
Started Jun 24 05:25:04 PM PDT 24
Finished Jun 24 05:25:09 PM PDT 24
Peak memory 206180 kb
Host smart-e92b8a65-820b-4355-a945-fa77cb8fb750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33119
7858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.331197858
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.941364971
Short name T2088
Test name
Test status
Simulation time 152244639 ps
CPU time 0.74 seconds
Started Jun 24 05:25:03 PM PDT 24
Finished Jun 24 05:25:07 PM PDT 24
Peak memory 206152 kb
Host smart-9713215c-009b-48d8-9139-55001de79197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94136
4971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.941364971
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1261899275
Short name T1521
Test name
Test status
Simulation time 61097223 ps
CPU time 0.71 seconds
Started Jun 24 05:25:05 PM PDT 24
Finished Jun 24 05:25:09 PM PDT 24
Peak memory 206172 kb
Host smart-d7fac81e-0f52-448d-91b4-2e5a30cec3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12618
99275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1261899275
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3265449020
Short name T383
Test name
Test status
Simulation time 938851430 ps
CPU time 2.27 seconds
Started Jun 24 05:25:06 PM PDT 24
Finished Jun 24 05:25:10 PM PDT 24
Peak memory 206152 kb
Host smart-8213a5d9-211f-468c-a6be-2dfd451fb710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32654
49020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3265449020
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3030732188
Short name T1787
Test name
Test status
Simulation time 184314557 ps
CPU time 1.75 seconds
Started Jun 24 05:25:04 PM PDT 24
Finished Jun 24 05:25:09 PM PDT 24
Peak memory 206244 kb
Host smart-ba74e882-b876-44d1-8c36-e8babda2d9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30307
32188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3030732188
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.148923903
Short name T2130
Test name
Test status
Simulation time 319789604 ps
CPU time 1.04 seconds
Started Jun 24 05:25:12 PM PDT 24
Finished Jun 24 05:25:15 PM PDT 24
Peak memory 206172 kb
Host smart-500d90af-af8e-4b6d-ad01-ae4714c10651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14892
3903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.148923903
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2970681622
Short name T502
Test name
Test status
Simulation time 155533911 ps
CPU time 0.78 seconds
Started Jun 24 05:25:14 PM PDT 24
Finished Jun 24 05:25:16 PM PDT 24
Peak memory 206188 kb
Host smart-99c82f10-d610-4221-b3c5-41a393b4d257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29706
81622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2970681622
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3109593040
Short name T1446
Test name
Test status
Simulation time 203624473 ps
CPU time 0.86 seconds
Started Jun 24 05:25:04 PM PDT 24
Finished Jun 24 05:25:08 PM PDT 24
Peak memory 206120 kb
Host smart-c501907e-ea70-4113-8a25-c1a5ba2447d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31095
93040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3109593040
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.689915316
Short name T1046
Test name
Test status
Simulation time 187822013 ps
CPU time 0.79 seconds
Started Jun 24 05:25:04 PM PDT 24
Finished Jun 24 05:25:08 PM PDT 24
Peak memory 206188 kb
Host smart-c643427b-344e-4639-a91d-ae5106b427d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68991
5316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.689915316
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.2015283295
Short name T1523
Test name
Test status
Simulation time 23281945750 ps
CPU time 22.48 seconds
Started Jun 24 05:25:04 PM PDT 24
Finished Jun 24 05:25:29 PM PDT 24
Peak memory 206476 kb
Host smart-155ddf24-00c7-44ef-b936-2e89c8088afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20152
83295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.2015283295
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.1899574295
Short name T1927
Test name
Test status
Simulation time 3317275337 ps
CPU time 3.64 seconds
Started Jun 24 05:25:06 PM PDT 24
Finished Jun 24 05:25:12 PM PDT 24
Peak memory 206220 kb
Host smart-dff5c873-0ad9-4ad6-8eb9-2e616a10f2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18995
74295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1899574295
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.2444833731
Short name T1862
Test name
Test status
Simulation time 13984135001 ps
CPU time 100.33 seconds
Started Jun 24 05:25:05 PM PDT 24
Finished Jun 24 05:26:48 PM PDT 24
Peak memory 206396 kb
Host smart-c9661c4e-6d5f-41b8-ac46-6c17fe9328e5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2444833731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.2444833731
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.443426423
Short name T1501
Test name
Test status
Simulation time 279907920 ps
CPU time 1.03 seconds
Started Jun 24 05:25:16 PM PDT 24
Finished Jun 24 05:25:18 PM PDT 24
Peak memory 206196 kb
Host smart-6e375815-448b-482c-8b2e-50bdc45d9572
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=443426423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.443426423
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.819613544
Short name T2457
Test name
Test status
Simulation time 203152125 ps
CPU time 0.86 seconds
Started Jun 24 05:25:05 PM PDT 24
Finished Jun 24 05:25:08 PM PDT 24
Peak memory 206168 kb
Host smart-4f27f99d-6f0c-402f-aa75-96a6e93816f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81961
3544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.819613544
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.2460665908
Short name T972
Test name
Test status
Simulation time 10637637969 ps
CPU time 71.49 seconds
Started Jun 24 05:25:02 PM PDT 24
Finished Jun 24 05:26:18 PM PDT 24
Peak memory 206368 kb
Host smart-60e427d1-b326-4d09-9c16-b8ea3575ed27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24606
65908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.2460665908
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.191885336
Short name T1254
Test name
Test status
Simulation time 8036961365 ps
CPU time 73.98 seconds
Started Jun 24 05:25:19 PM PDT 24
Finished Jun 24 05:26:36 PM PDT 24
Peak memory 206340 kb
Host smart-11e62878-cbb4-44a1-a558-065a5b6fe0aa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=191885336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.191885336
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.668700773
Short name T1244
Test name
Test status
Simulation time 169309521 ps
CPU time 0.9 seconds
Started Jun 24 05:25:15 PM PDT 24
Finished Jun 24 05:25:18 PM PDT 24
Peak memory 206196 kb
Host smart-3860681f-b407-40b1-a22d-4d9ebba8d376
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=668700773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.668700773
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2487871385
Short name T1780
Test name
Test status
Simulation time 149842190 ps
CPU time 0.85 seconds
Started Jun 24 05:25:04 PM PDT 24
Finished Jun 24 05:25:08 PM PDT 24
Peak memory 206176 kb
Host smart-21aa76f7-2146-4ca3-a95d-bc8145e88c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24878
71385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2487871385
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.289232993
Short name T126
Test name
Test status
Simulation time 191677141 ps
CPU time 0.84 seconds
Started Jun 24 05:25:06 PM PDT 24
Finished Jun 24 05:25:09 PM PDT 24
Peak memory 206076 kb
Host smart-d24352a9-8a87-48e2-af0b-2978feb662c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28923
2993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.289232993
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.2999851504
Short name T1986
Test name
Test status
Simulation time 171601938 ps
CPU time 0.83 seconds
Started Jun 24 05:25:06 PM PDT 24
Finished Jun 24 05:25:09 PM PDT 24
Peak memory 206160 kb
Host smart-ac7d230b-a54f-4e36-865d-92dea3af61f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29998
51504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2999851504
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3876312405
Short name T1149
Test name
Test status
Simulation time 179171201 ps
CPU time 0.87 seconds
Started Jun 24 05:25:05 PM PDT 24
Finished Jun 24 05:25:08 PM PDT 24
Peak memory 206056 kb
Host smart-825f6810-e62c-4d1a-b903-8dbb133712bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38763
12405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3876312405
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3618617908
Short name T1027
Test name
Test status
Simulation time 195282098 ps
CPU time 0.84 seconds
Started Jun 24 05:25:04 PM PDT 24
Finished Jun 24 05:25:08 PM PDT 24
Peak memory 206192 kb
Host smart-527ef587-7904-468d-ba6f-fc0b5eae0278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36186
17908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3618617908
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2857660891
Short name T1945
Test name
Test status
Simulation time 157623193 ps
CPU time 0.78 seconds
Started Jun 24 05:25:11 PM PDT 24
Finished Jun 24 05:25:13 PM PDT 24
Peak memory 206168 kb
Host smart-e137f486-f19d-478d-9b3c-8f1b147a0eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28576
60891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2857660891
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.265155733
Short name T2168
Test name
Test status
Simulation time 239393258 ps
CPU time 1.01 seconds
Started Jun 24 05:25:17 PM PDT 24
Finished Jun 24 05:25:20 PM PDT 24
Peak memory 206176 kb
Host smart-4527d52f-cdb8-468a-9727-df259f610939
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=265155733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.265155733
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2565236358
Short name T2159
Test name
Test status
Simulation time 144667329 ps
CPU time 0.76 seconds
Started Jun 24 05:25:11 PM PDT 24
Finished Jun 24 05:25:13 PM PDT 24
Peak memory 206148 kb
Host smart-cd82a2e7-87d1-4e83-98ef-a2479f0e776c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25652
36358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2565236358
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1162354293
Short name T1685
Test name
Test status
Simulation time 47132928 ps
CPU time 0.65 seconds
Started Jun 24 05:25:15 PM PDT 24
Finished Jun 24 05:25:17 PM PDT 24
Peak memory 206140 kb
Host smart-6518ff62-7205-49d2-bed7-746e02a227d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11623
54293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1162354293
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.384067463
Short name T1489
Test name
Test status
Simulation time 10921613311 ps
CPU time 24.8 seconds
Started Jun 24 05:25:11 PM PDT 24
Finished Jun 24 05:25:37 PM PDT 24
Peak memory 206352 kb
Host smart-4f00fa57-b12b-4523-a2b2-43f5df060204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38406
7463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.384067463
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.3884502783
Short name T355
Test name
Test status
Simulation time 170179222 ps
CPU time 0.81 seconds
Started Jun 24 05:25:16 PM PDT 24
Finished Jun 24 05:25:19 PM PDT 24
Peak memory 206132 kb
Host smart-f85e0bb1-e976-46fc-a3dc-3d5b1bb62e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38845
02783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3884502783
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1404675665
Short name T359
Test name
Test status
Simulation time 219849938 ps
CPU time 0.89 seconds
Started Jun 24 05:25:13 PM PDT 24
Finished Jun 24 05:25:15 PM PDT 24
Peak memory 206104 kb
Host smart-43655b86-4001-4dbe-8003-f368dcef4b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14046
75665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1404675665
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2751352196
Short name T673
Test name
Test status
Simulation time 215692190 ps
CPU time 0.91 seconds
Started Jun 24 05:25:15 PM PDT 24
Finished Jun 24 05:25:17 PM PDT 24
Peak memory 205512 kb
Host smart-f2da9d3a-74d5-4fcd-b8bc-63d28ee4d38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27513
52196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2751352196
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1081036005
Short name T2059
Test name
Test status
Simulation time 236534370 ps
CPU time 0.94 seconds
Started Jun 24 05:25:10 PM PDT 24
Finished Jun 24 05:25:12 PM PDT 24
Peak memory 206196 kb
Host smart-67732d4c-ebf5-4846-afb0-ce7aba9c0ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10810
36005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1081036005
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.4276913583
Short name T930
Test name
Test status
Simulation time 192562419 ps
CPU time 0.81 seconds
Started Jun 24 05:25:20 PM PDT 24
Finished Jun 24 05:25:25 PM PDT 24
Peak memory 206192 kb
Host smart-eb337164-7c05-4e1a-b8ae-056ecd1ff422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42769
13583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.4276913583
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.768182695
Short name T1147
Test name
Test status
Simulation time 163305356 ps
CPU time 0.8 seconds
Started Jun 24 05:25:12 PM PDT 24
Finished Jun 24 05:25:14 PM PDT 24
Peak memory 206076 kb
Host smart-15d345a9-fb92-434a-951e-823f12bffcb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76818
2695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.768182695
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.616228119
Short name T485
Test name
Test status
Simulation time 163328763 ps
CPU time 0.78 seconds
Started Jun 24 05:25:11 PM PDT 24
Finished Jun 24 05:25:13 PM PDT 24
Peak memory 206172 kb
Host smart-babc9512-f5f3-4f35-a4ca-a05f9f41a558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61622
8119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.616228119
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.4287661564
Short name T2170
Test name
Test status
Simulation time 262798952 ps
CPU time 0.94 seconds
Started Jun 24 05:25:12 PM PDT 24
Finished Jun 24 05:25:15 PM PDT 24
Peak memory 206120 kb
Host smart-854b62c3-f8b0-4370-ac75-862c8f9915f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42876
61564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.4287661564
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.2541002840
Short name T2091
Test name
Test status
Simulation time 14292277834 ps
CPU time 395.58 seconds
Started Jun 24 05:25:14 PM PDT 24
Finished Jun 24 05:31:51 PM PDT 24
Peak memory 206344 kb
Host smart-38736b49-ede3-4b8f-8744-8553bae6d116
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2541002840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.2541002840
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.88886728
Short name T1047
Test name
Test status
Simulation time 209624671 ps
CPU time 0.8 seconds
Started Jun 24 05:25:12 PM PDT 24
Finished Jun 24 05:25:14 PM PDT 24
Peak memory 206412 kb
Host smart-d900c084-e4d3-4aac-a12a-53bc210d5846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88886
728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.88886728
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2204038398
Short name T1597
Test name
Test status
Simulation time 219445273 ps
CPU time 0.88 seconds
Started Jun 24 05:25:11 PM PDT 24
Finished Jun 24 05:25:13 PM PDT 24
Peak memory 206116 kb
Host smart-372bbd23-ebfd-4dfb-a964-54a2ec0d9674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22040
38398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2204038398
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.4192561995
Short name T1736
Test name
Test status
Simulation time 15757698286 ps
CPU time 110.41 seconds
Started Jun 24 05:25:13 PM PDT 24
Finished Jun 24 05:27:05 PM PDT 24
Peak memory 206368 kb
Host smart-eb04fa37-0838-48a7-9bd3-362fd9060383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41925
61995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.4192561995
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.463540770
Short name T548
Test name
Test status
Simulation time 3782339817 ps
CPU time 4.53 seconds
Started Jun 24 05:20:32 PM PDT 24
Finished Jun 24 05:20:39 PM PDT 24
Peak memory 206232 kb
Host smart-663cdd1c-f2c6-4d5b-a759-24d58f175d03
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=463540770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.463540770
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.1392305359
Short name T1002
Test name
Test status
Simulation time 13367139666 ps
CPU time 12.52 seconds
Started Jun 24 05:20:34 PM PDT 24
Finished Jun 24 05:20:48 PM PDT 24
Peak memory 206316 kb
Host smart-13a87e5a-d4e5-4f7e-bf0e-4ecdb104638e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1392305359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1392305359
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.2756879631
Short name T10
Test name
Test status
Simulation time 23337822460 ps
CPU time 21.45 seconds
Started Jun 24 05:20:35 PM PDT 24
Finished Jun 24 05:20:57 PM PDT 24
Peak memory 206244 kb
Host smart-531adb7e-3a40-4702-8a2a-c936af81b578
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2756879631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.2756879631
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2317327771
Short name T2230
Test name
Test status
Simulation time 202700347 ps
CPU time 0.87 seconds
Started Jun 24 05:20:32 PM PDT 24
Finished Jun 24 05:20:35 PM PDT 24
Peak memory 206160 kb
Host smart-5ad0a276-69e3-42fb-b9a2-78f4e9695a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23173
27771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2317327771
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.4071938753
Short name T50
Test name
Test status
Simulation time 187935562 ps
CPU time 0.84 seconds
Started Jun 24 05:20:31 PM PDT 24
Finished Jun 24 05:20:32 PM PDT 24
Peak memory 206116 kb
Host smart-c8181f95-4e62-4d5e-b305-a3a26b02ad96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40719
38753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.4071938753
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.4004486453
Short name T2190
Test name
Test status
Simulation time 161750133 ps
CPU time 0.77 seconds
Started Jun 24 05:20:35 PM PDT 24
Finished Jun 24 05:20:36 PM PDT 24
Peak memory 206188 kb
Host smart-6f0fa94b-485f-4c8c-a184-8b168afb65b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40044
86453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.4004486453
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.3817326077
Short name T1176
Test name
Test status
Simulation time 211655760 ps
CPU time 0.9 seconds
Started Jun 24 05:20:32 PM PDT 24
Finished Jun 24 05:20:33 PM PDT 24
Peak memory 206176 kb
Host smart-1fef7670-66bf-454e-8cde-f4bae491b111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38173
26077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.3817326077
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1103089390
Short name T2198
Test name
Test status
Simulation time 903876723 ps
CPU time 2.11 seconds
Started Jun 24 05:20:37 PM PDT 24
Finished Jun 24 05:20:39 PM PDT 24
Peak memory 206148 kb
Host smart-4396f46c-b874-481c-8580-bc7f74ba27c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11030
89390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1103089390
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.1579677726
Short name T911
Test name
Test status
Simulation time 17700369704 ps
CPU time 33.85 seconds
Started Jun 24 05:20:32 PM PDT 24
Finished Jun 24 05:21:08 PM PDT 24
Peak memory 206344 kb
Host smart-be8c3e8a-51a9-4eae-aab8-71997bd67ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15796
77726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.1579677726
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.2041059666
Short name T1069
Test name
Test status
Simulation time 369255877 ps
CPU time 1.17 seconds
Started Jun 24 05:20:37 PM PDT 24
Finished Jun 24 05:20:39 PM PDT 24
Peak memory 206176 kb
Host smart-6c0d5fa3-fb0d-4d68-a091-4b8048794c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20410
59666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.2041059666
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.517113668
Short name T2498
Test name
Test status
Simulation time 143210323 ps
CPU time 0.74 seconds
Started Jun 24 05:20:32 PM PDT 24
Finished Jun 24 05:20:34 PM PDT 24
Peak memory 206196 kb
Host smart-418ee0c4-4d92-4827-98ee-40cb31df4cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51711
3668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.517113668
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.4070051947
Short name T827
Test name
Test status
Simulation time 53772566 ps
CPU time 0.68 seconds
Started Jun 24 05:20:32 PM PDT 24
Finished Jun 24 05:20:34 PM PDT 24
Peak memory 206168 kb
Host smart-7e14b37f-eee9-43b1-b24c-0128bcad4c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40700
51947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.4070051947
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.2578217996
Short name T2445
Test name
Test status
Simulation time 938538336 ps
CPU time 2.03 seconds
Started Jun 24 05:20:33 PM PDT 24
Finished Jun 24 05:20:37 PM PDT 24
Peak memory 206256 kb
Host smart-a244f94f-6fa9-41bb-a0f7-9ced8ca43f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25782
17996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.2578217996
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.434637409
Short name T1778
Test name
Test status
Simulation time 324456220 ps
CPU time 1.65 seconds
Started Jun 24 05:20:33 PM PDT 24
Finished Jun 24 05:20:36 PM PDT 24
Peak memory 206296 kb
Host smart-ff03886d-8998-41c9-8f26-66b84997c58e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43463
7409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.434637409
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.3963382503
Short name T1235
Test name
Test status
Simulation time 184271726 ps
CPU time 0.81 seconds
Started Jun 24 05:20:40 PM PDT 24
Finished Jun 24 05:20:42 PM PDT 24
Peak memory 206140 kb
Host smart-c11ff350-254c-4f55-9906-ee60b8000d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39633
82503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.3963382503
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2721773991
Short name T1613
Test name
Test status
Simulation time 138191006 ps
CPU time 0.77 seconds
Started Jun 24 05:20:39 PM PDT 24
Finished Jun 24 05:20:42 PM PDT 24
Peak memory 206172 kb
Host smart-a6bb79b8-a6b7-46ea-b5f2-74fe4ae8d3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27217
73991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2721773991
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3524684508
Short name T1812
Test name
Test status
Simulation time 209360159 ps
CPU time 0.92 seconds
Started Jun 24 05:20:32 PM PDT 24
Finished Jun 24 05:20:34 PM PDT 24
Peak memory 206428 kb
Host smart-7a446a22-4333-4222-bb2e-afb82d382a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35246
84508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3524684508
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1031755314
Short name T1919
Test name
Test status
Simulation time 213068355 ps
CPU time 0.86 seconds
Started Jun 24 05:20:32 PM PDT 24
Finished Jun 24 05:20:34 PM PDT 24
Peak memory 206188 kb
Host smart-feab4c32-315c-422e-afd7-f52a041ac5c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10317
55314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1031755314
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.3944667875
Short name T2262
Test name
Test status
Simulation time 23341148433 ps
CPU time 21.96 seconds
Started Jun 24 05:20:32 PM PDT 24
Finished Jun 24 05:20:56 PM PDT 24
Peak memory 206176 kb
Host smart-0aa3dc3b-4230-466f-9e36-4bc443efbd23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39446
67875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.3944667875
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2673468188
Short name T1644
Test name
Test status
Simulation time 3340600896 ps
CPU time 4.1 seconds
Started Jun 24 05:20:37 PM PDT 24
Finished Jun 24 05:20:42 PM PDT 24
Peak memory 206236 kb
Host smart-88c41b10-a20b-4e69-915b-6ca36ce78038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26734
68188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2673468188
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.1702580806
Short name T1470
Test name
Test status
Simulation time 9554084237 ps
CPU time 265.2 seconds
Started Jun 24 05:20:39 PM PDT 24
Finished Jun 24 05:25:06 PM PDT 24
Peak memory 206396 kb
Host smart-b164eb31-0a80-4eec-a8fd-8aba4ac51c5b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1702580806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.1702580806
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.1156250016
Short name T846
Test name
Test status
Simulation time 243105304 ps
CPU time 0.97 seconds
Started Jun 24 05:20:42 PM PDT 24
Finished Jun 24 05:20:45 PM PDT 24
Peak memory 206188 kb
Host smart-a0f0e6be-4be7-4e4e-b93b-a6bbfabab137
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1156250016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.1156250016
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.855113864
Short name T871
Test name
Test status
Simulation time 186159755 ps
CPU time 0.86 seconds
Started Jun 24 05:20:33 PM PDT 24
Finished Jun 24 05:20:35 PM PDT 24
Peak memory 206432 kb
Host smart-112b0160-942e-4a28-9f19-f2030997203c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85511
3864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.855113864
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.933596494
Short name T1073
Test name
Test status
Simulation time 9267282361 ps
CPU time 65.87 seconds
Started Jun 24 05:20:33 PM PDT 24
Finished Jun 24 05:21:40 PM PDT 24
Peak memory 206292 kb
Host smart-4c46e02b-6dc0-4875-963e-3661c4277fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93359
6494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.933596494
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.3612690834
Short name T1547
Test name
Test status
Simulation time 3967609275 ps
CPU time 38.48 seconds
Started Jun 24 05:20:36 PM PDT 24
Finished Jun 24 05:21:15 PM PDT 24
Peak memory 206232 kb
Host smart-55bb0750-aa45-4646-9762-cddeec2f3121
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3612690834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.3612690834
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.70352875
Short name T1860
Test name
Test status
Simulation time 151389946 ps
CPU time 0.78 seconds
Started Jun 24 05:20:42 PM PDT 24
Finished Jun 24 05:20:45 PM PDT 24
Peak memory 206172 kb
Host smart-1fabee1f-a1ce-4096-9f12-7ea2f178c107
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=70352875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.70352875
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3431256867
Short name T999
Test name
Test status
Simulation time 196973691 ps
CPU time 0.82 seconds
Started Jun 24 05:20:32 PM PDT 24
Finished Jun 24 05:20:35 PM PDT 24
Peak memory 206096 kb
Host smart-7ab7d93f-f7b3-4dd7-a456-9d93d1fd7891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34312
56867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3431256867
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3904710828
Short name T2197
Test name
Test status
Simulation time 164176626 ps
CPU time 0.84 seconds
Started Jun 24 05:20:37 PM PDT 24
Finished Jun 24 05:20:39 PM PDT 24
Peak memory 206052 kb
Host smart-11ffecfc-7b68-401f-bde0-26657bc9ee1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39047
10828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3904710828
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2791460434
Short name T1165
Test name
Test status
Simulation time 155324937 ps
CPU time 0.77 seconds
Started Jun 24 05:20:38 PM PDT 24
Finished Jun 24 05:20:41 PM PDT 24
Peak memory 206172 kb
Host smart-93f25a0a-5de8-4085-b718-0fbf83225476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27914
60434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2791460434
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2326912664
Short name T916
Test name
Test status
Simulation time 159702333 ps
CPU time 0.8 seconds
Started Jun 24 05:20:36 PM PDT 24
Finished Jun 24 05:20:38 PM PDT 24
Peak memory 206408 kb
Host smart-0afdf32e-679d-4d28-b59a-74aae8394a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23269
12664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2326912664
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1437481669
Short name T2094
Test name
Test status
Simulation time 145333652 ps
CPU time 0.81 seconds
Started Jun 24 05:20:48 PM PDT 24
Finished Jun 24 05:20:51 PM PDT 24
Peak memory 206172 kb
Host smart-de88e022-9bfc-40be-8876-44efac033db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14374
81669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1437481669
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.2679281247
Short name T1505
Test name
Test status
Simulation time 228479060 ps
CPU time 0.92 seconds
Started Jun 24 05:20:39 PM PDT 24
Finished Jun 24 05:20:42 PM PDT 24
Peak memory 206184 kb
Host smart-44d7ecf1-a69b-446a-b20c-378b53f85411
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2679281247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.2679281247
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.2307439718
Short name T1931
Test name
Test status
Simulation time 228267451 ps
CPU time 0.98 seconds
Started Jun 24 05:20:41 PM PDT 24
Finished Jun 24 05:20:44 PM PDT 24
Peak memory 206172 kb
Host smart-82bb85b1-44e7-4ca7-a041-eeabdafdfcb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23074
39718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.2307439718
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.1697762033
Short name T1085
Test name
Test status
Simulation time 143083203 ps
CPU time 0.79 seconds
Started Jun 24 05:20:39 PM PDT 24
Finished Jun 24 05:20:42 PM PDT 24
Peak memory 206188 kb
Host smart-de4d5cc0-e2c6-45f4-bd8f-0bd1fd0c1d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16977
62033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.1697762033
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2286310128
Short name T1656
Test name
Test status
Simulation time 39625171 ps
CPU time 0.66 seconds
Started Jun 24 05:20:41 PM PDT 24
Finished Jun 24 05:20:44 PM PDT 24
Peak memory 206136 kb
Host smart-809bf8bd-3a8d-4bfb-9e42-2115cb777e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22863
10128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2286310128
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1050560935
Short name T1138
Test name
Test status
Simulation time 22671091745 ps
CPU time 50.52 seconds
Started Jun 24 05:20:42 PM PDT 24
Finished Jun 24 05:21:34 PM PDT 24
Peak memory 206336 kb
Host smart-16168cf9-ff54-4324-9444-a7af96b4f5af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10505
60935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1050560935
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.744310644
Short name T488
Test name
Test status
Simulation time 200682861 ps
CPU time 0.87 seconds
Started Jun 24 05:20:40 PM PDT 24
Finished Jun 24 05:20:43 PM PDT 24
Peak memory 206188 kb
Host smart-59cada0b-6f11-4583-93f8-f9935ffb81ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74431
0644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.744310644
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3913870889
Short name T803
Test name
Test status
Simulation time 224072704 ps
CPU time 0.92 seconds
Started Jun 24 05:20:41 PM PDT 24
Finished Jun 24 05:20:44 PM PDT 24
Peak memory 206184 kb
Host smart-c5e6778f-9629-4262-bbd7-ffb9e0cd5894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39138
70889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3913870889
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.920207456
Short name T1635
Test name
Test status
Simulation time 17489674829 ps
CPU time 153.17 seconds
Started Jun 24 05:20:41 PM PDT 24
Finished Jun 24 05:23:17 PM PDT 24
Peak memory 206432 kb
Host smart-7c9e9e37-1f4f-4f41-83e4-3f0ab2a2d82f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=920207456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.920207456
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.836648237
Short name T1434
Test name
Test status
Simulation time 9082666773 ps
CPU time 168.72 seconds
Started Jun 24 05:20:42 PM PDT 24
Finished Jun 24 05:23:33 PM PDT 24
Peak memory 206384 kb
Host smart-0981ce80-0a72-497c-bdb4-7b89297c2e73
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=836648237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.836648237
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2458808859
Short name T953
Test name
Test status
Simulation time 17308851984 ps
CPU time 130.93 seconds
Started Jun 24 05:20:41 PM PDT 24
Finished Jun 24 05:22:54 PM PDT 24
Peak memory 206336 kb
Host smart-f00cf394-191f-4ee4-99a8-8c9297fb63cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2458808859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2458808859
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.3507740266
Short name T2380
Test name
Test status
Simulation time 240661261 ps
CPU time 0.9 seconds
Started Jun 24 05:20:41 PM PDT 24
Finished Jun 24 05:20:44 PM PDT 24
Peak memory 206120 kb
Host smart-e7e91b66-84e6-439f-8d40-3a46a312a75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35077
40266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.3507740266
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.1785313145
Short name T1894
Test name
Test status
Simulation time 193977548 ps
CPU time 0.83 seconds
Started Jun 24 05:20:38 PM PDT 24
Finished Jun 24 05:20:39 PM PDT 24
Peak memory 206096 kb
Host smart-ddafaf2b-bd40-46f0-9038-6cc3529e30e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17853
13145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.1785313145
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1967235574
Short name T1382
Test name
Test status
Simulation time 178514631 ps
CPU time 0.84 seconds
Started Jun 24 05:20:40 PM PDT 24
Finished Jun 24 05:20:42 PM PDT 24
Peak memory 206180 kb
Host smart-2f7ff553-bc53-4c03-b638-5f63146646af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19672
35574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1967235574
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.852524101
Short name T932
Test name
Test status
Simulation time 222420532 ps
CPU time 0.82 seconds
Started Jun 24 05:20:42 PM PDT 24
Finished Jun 24 05:20:45 PM PDT 24
Peak memory 206164 kb
Host smart-544b9bc2-5a58-45a1-ad60-0c83c8825d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85252
4101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.852524101
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1287507573
Short name T217
Test name
Test status
Simulation time 651164494 ps
CPU time 1.42 seconds
Started Jun 24 05:20:48 PM PDT 24
Finished Jun 24 05:20:51 PM PDT 24
Peak memory 223820 kb
Host smart-bfc0980d-0d57-4263-be0a-99c9f91e6ea7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1287507573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1287507573
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.1604478331
Short name T1710
Test name
Test status
Simulation time 385281795 ps
CPU time 1.2 seconds
Started Jun 24 05:20:40 PM PDT 24
Finished Jun 24 05:20:43 PM PDT 24
Peak memory 206164 kb
Host smart-ba6eb3a6-4a9d-4a34-8354-7413e65bbc9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16044
78331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.1604478331
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.2493839367
Short name T499
Test name
Test status
Simulation time 149906270 ps
CPU time 0.82 seconds
Started Jun 24 05:20:48 PM PDT 24
Finished Jun 24 05:20:51 PM PDT 24
Peak memory 206180 kb
Host smart-c77867d7-712c-480f-b72e-b57666e74d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24938
39367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.2493839367
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.732261124
Short name T600
Test name
Test status
Simulation time 156928627 ps
CPU time 0.81 seconds
Started Jun 24 05:20:39 PM PDT 24
Finished Jun 24 05:20:41 PM PDT 24
Peak memory 206176 kb
Host smart-ffb19afb-5b44-4d31-9941-a501cae70e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73226
1124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.732261124
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2569037023
Short name T1057
Test name
Test status
Simulation time 201608885 ps
CPU time 0.93 seconds
Started Jun 24 05:20:39 PM PDT 24
Finished Jun 24 05:20:42 PM PDT 24
Peak memory 206428 kb
Host smart-68993763-338f-438d-bd0c-7ca90fff0cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25690
37023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2569037023
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.4058291424
Short name T2313
Test name
Test status
Simulation time 10090706621 ps
CPU time 69.91 seconds
Started Jun 24 05:20:48 PM PDT 24
Finished Jun 24 05:22:00 PM PDT 24
Peak memory 206400 kb
Host smart-109033c1-f388-42ef-b1c7-d36b1bdccd9f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4058291424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.4058291424
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3862214357
Short name T868
Test name
Test status
Simulation time 181223978 ps
CPU time 0.82 seconds
Started Jun 24 05:20:48 PM PDT 24
Finished Jun 24 05:20:51 PM PDT 24
Peak memory 205092 kb
Host smart-d2b52309-b2a4-4f44-ae4f-342ed721b79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38622
14357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3862214357
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2874885970
Short name T2427
Test name
Test status
Simulation time 181941872 ps
CPU time 0.84 seconds
Started Jun 24 05:20:40 PM PDT 24
Finished Jun 24 05:20:43 PM PDT 24
Peak memory 206116 kb
Host smart-fc4184d6-2b90-452d-a8a2-4c2498295f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28748
85970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2874885970
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2822995496
Short name T538
Test name
Test status
Simulation time 10061671512 ps
CPU time 72.98 seconds
Started Jun 24 05:20:40 PM PDT 24
Finished Jun 24 05:21:54 PM PDT 24
Peak memory 206308 kb
Host smart-6d205631-4b72-4469-bef1-366fe6b72d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28229
95496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2822995496
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.2469826617
Short name T1891
Test name
Test status
Simulation time 23744151594 ps
CPU time 189.62 seconds
Started Jun 24 05:20:48 PM PDT 24
Finished Jun 24 05:24:00 PM PDT 24
Peak memory 205540 kb
Host smart-c7e3deb6-9308-4718-87cf-1905b55551fe
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2469826617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.2469826617
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.2329132951
Short name T943
Test name
Test status
Simulation time 4372625137 ps
CPU time 4.68 seconds
Started Jun 24 05:25:13 PM PDT 24
Finished Jun 24 05:25:20 PM PDT 24
Peak memory 206304 kb
Host smart-0efea801-b24f-41e6-8198-5199ea5ad983
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2329132951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.2329132951
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.1714768634
Short name T1553
Test name
Test status
Simulation time 13391147850 ps
CPU time 12.92 seconds
Started Jun 24 05:25:14 PM PDT 24
Finished Jun 24 05:25:29 PM PDT 24
Peak memory 206244 kb
Host smart-319b3355-7f69-4aa9-b1b9-8bf491cdcc48
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1714768634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.1714768634
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.1430664868
Short name T996
Test name
Test status
Simulation time 23367818686 ps
CPU time 24.85 seconds
Started Jun 24 05:25:11 PM PDT 24
Finished Jun 24 05:25:37 PM PDT 24
Peak memory 206244 kb
Host smart-ee54c202-01bb-4556-bd8d-e0b1b61d5887
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1430664868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.1430664868
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.764821863
Short name T1583
Test name
Test status
Simulation time 151279464 ps
CPU time 0.78 seconds
Started Jun 24 05:25:13 PM PDT 24
Finished Jun 24 05:25:15 PM PDT 24
Peak memory 206176 kb
Host smart-36758e8d-3b05-45f7-9e7f-2f76f03445bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76482
1863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.764821863
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.319885451
Short name T2133
Test name
Test status
Simulation time 147780118 ps
CPU time 0.79 seconds
Started Jun 24 05:25:12 PM PDT 24
Finished Jun 24 05:25:14 PM PDT 24
Peak memory 206080 kb
Host smart-96ac2d86-f534-4e5c-bcae-465bfecf39da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31988
5451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.319885451
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.1157015359
Short name T2219
Test name
Test status
Simulation time 144281234 ps
CPU time 0.78 seconds
Started Jun 24 05:25:13 PM PDT 24
Finished Jun 24 05:25:15 PM PDT 24
Peak memory 206172 kb
Host smart-9245b4fe-b701-41db-bd84-4c271b4ba211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11570
15359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.1157015359
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.1128098053
Short name T1766
Test name
Test status
Simulation time 1007788250 ps
CPU time 2.23 seconds
Started Jun 24 05:25:19 PM PDT 24
Finished Jun 24 05:25:23 PM PDT 24
Peak memory 206328 kb
Host smart-2b0e2fdb-971b-494a-a20f-5e9cb3931374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11280
98053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.1128098053
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.1596474158
Short name T1722
Test name
Test status
Simulation time 8805533264 ps
CPU time 17.57 seconds
Started Jun 24 05:25:13 PM PDT 24
Finished Jun 24 05:25:32 PM PDT 24
Peak memory 206328 kb
Host smart-d7a253a7-757f-48b1-811d-461170184724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15964
74158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.1596474158
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.19591457
Short name T2451
Test name
Test status
Simulation time 514386873 ps
CPU time 1.57 seconds
Started Jun 24 05:25:18 PM PDT 24
Finished Jun 24 05:25:21 PM PDT 24
Peak memory 206180 kb
Host smart-2d433e2a-7502-484c-a1ae-ccb62263a5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19591
457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.19591457
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.2052179395
Short name T1030
Test name
Test status
Simulation time 134114271 ps
CPU time 0.77 seconds
Started Jun 24 05:25:15 PM PDT 24
Finished Jun 24 05:25:18 PM PDT 24
Peak memory 206168 kb
Host smart-a1c5c77a-80d5-4436-a6d4-87d66964b7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20521
79395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2052179395
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.1449313938
Short name T882
Test name
Test status
Simulation time 43120625 ps
CPU time 0.67 seconds
Started Jun 24 05:25:11 PM PDT 24
Finished Jun 24 05:25:13 PM PDT 24
Peak memory 206168 kb
Host smart-b789aba8-facc-426f-a8d6-25bcec1b009d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14493
13938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1449313938
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.2568853302
Short name T919
Test name
Test status
Simulation time 794020081 ps
CPU time 1.88 seconds
Started Jun 24 05:25:13 PM PDT 24
Finished Jun 24 05:25:17 PM PDT 24
Peak memory 206188 kb
Host smart-ebe6a3da-77de-44f4-8666-35162c0e0c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25688
53302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.2568853302
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.497956538
Short name T560
Test name
Test status
Simulation time 201012092 ps
CPU time 1.99 seconds
Started Jun 24 05:25:16 PM PDT 24
Finished Jun 24 05:25:20 PM PDT 24
Peak memory 206260 kb
Host smart-e4e5b0e5-cd7e-48e0-a8ea-1ef8d732ab85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49795
6538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.497956538
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3784629310
Short name T2202
Test name
Test status
Simulation time 173259914 ps
CPU time 0.81 seconds
Started Jun 24 05:25:17 PM PDT 24
Finished Jun 24 05:25:20 PM PDT 24
Peak memory 206176 kb
Host smart-832029dc-bc7a-4069-8d06-2ebb73b472cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37846
29310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3784629310
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1599313547
Short name T809
Test name
Test status
Simulation time 219388538 ps
CPU time 0.81 seconds
Started Jun 24 05:25:22 PM PDT 24
Finished Jun 24 05:25:26 PM PDT 24
Peak memory 206152 kb
Host smart-1e56cc73-b801-43a2-bc46-3cee6054f9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15993
13547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1599313547
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2427216007
Short name T1478
Test name
Test status
Simulation time 218198315 ps
CPU time 0.88 seconds
Started Jun 24 05:25:10 PM PDT 24
Finished Jun 24 05:25:12 PM PDT 24
Peak memory 206116 kb
Host smart-e0931c06-b4d1-42c2-87d6-9bd721c0a2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24272
16007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2427216007
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.4107378909
Short name T928
Test name
Test status
Simulation time 11828058943 ps
CPU time 312.12 seconds
Started Jun 24 05:25:20 PM PDT 24
Finished Jun 24 05:30:36 PM PDT 24
Peak memory 206396 kb
Host smart-ee1d732d-c644-4670-ae19-9c69261fb5ff
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4107378909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.4107378909
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1166975994
Short name T580
Test name
Test status
Simulation time 220584130 ps
CPU time 0.88 seconds
Started Jun 24 05:25:16 PM PDT 24
Finished Jun 24 05:25:19 PM PDT 24
Peak memory 206152 kb
Host smart-6a11e298-f79a-45ba-bfb2-9f183ee563f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11669
75994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1166975994
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.4255222128
Short name T2483
Test name
Test status
Simulation time 23327756071 ps
CPU time 23.44 seconds
Started Jun 24 05:25:15 PM PDT 24
Finished Jun 24 05:25:40 PM PDT 24
Peak memory 205532 kb
Host smart-c2ac5180-6860-4a3f-858d-b4ce73ea07fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42552
22128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.4255222128
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.1672401983
Short name T526
Test name
Test status
Simulation time 3316973318 ps
CPU time 3.64 seconds
Started Jun 24 05:25:17 PM PDT 24
Finished Jun 24 05:25:22 PM PDT 24
Peak memory 206240 kb
Host smart-206852b8-322b-4464-b274-c968c890403d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16724
01983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.1672401983
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.3866947893
Short name T672
Test name
Test status
Simulation time 10268344426 ps
CPU time 72.34 seconds
Started Jun 24 05:25:12 PM PDT 24
Finished Jun 24 05:26:26 PM PDT 24
Peak memory 206336 kb
Host smart-a3aa9231-60da-4fd0-a970-13319c7dbe58
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3866947893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.3866947893
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.3633140388
Short name T643
Test name
Test status
Simulation time 247906424 ps
CPU time 0.95 seconds
Started Jun 24 05:25:22 PM PDT 24
Finished Jun 24 05:25:26 PM PDT 24
Peak memory 206196 kb
Host smart-d0585c26-8cc9-4552-b40b-650ddfbde27b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3633140388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.3633140388
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2384706384
Short name T1831
Test name
Test status
Simulation time 250799822 ps
CPU time 0.91 seconds
Started Jun 24 05:25:20 PM PDT 24
Finished Jun 24 05:25:25 PM PDT 24
Peak memory 206156 kb
Host smart-3543b121-a5ec-4b5b-8cf1-6ddb342e82f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23847
06384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2384706384
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.2236067926
Short name T1711
Test name
Test status
Simulation time 4799842984 ps
CPU time 45.89 seconds
Started Jun 24 05:25:15 PM PDT 24
Finished Jun 24 05:26:03 PM PDT 24
Peak memory 206376 kb
Host smart-8d168bf0-de14-4e28-a76e-8a377eec251a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22360
67926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.2236067926
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.3305028320
Short name T1144
Test name
Test status
Simulation time 11969722943 ps
CPU time 84.19 seconds
Started Jun 24 05:25:14 PM PDT 24
Finished Jun 24 05:26:40 PM PDT 24
Peak memory 206396 kb
Host smart-cf2cf5b7-c55e-4cd3-b935-2d696ef6fd93
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3305028320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.3305028320
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.844649098
Short name T2282
Test name
Test status
Simulation time 154105521 ps
CPU time 0.78 seconds
Started Jun 24 05:25:20 PM PDT 24
Finished Jun 24 05:25:23 PM PDT 24
Peak memory 206196 kb
Host smart-48320659-9b29-4eaf-8e1a-d76805574520
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=844649098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.844649098
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2234909670
Short name T1614
Test name
Test status
Simulation time 148805061 ps
CPU time 0.76 seconds
Started Jun 24 05:25:10 PM PDT 24
Finished Jun 24 05:25:11 PM PDT 24
Peak memory 206100 kb
Host smart-d417a701-783e-4208-a7a1-3f2c0a099580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22349
09670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2234909670
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1438148593
Short name T2226
Test name
Test status
Simulation time 273506196 ps
CPU time 0.99 seconds
Started Jun 24 05:25:19 PM PDT 24
Finished Jun 24 05:25:22 PM PDT 24
Peak memory 206180 kb
Host smart-d42c83d7-2e0a-436b-8f99-12213e38c01f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14381
48593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1438148593
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3861957922
Short name T2075
Test name
Test status
Simulation time 175749477 ps
CPU time 0.84 seconds
Started Jun 24 05:25:16 PM PDT 24
Finished Jun 24 05:25:19 PM PDT 24
Peak memory 206188 kb
Host smart-64c0443e-ff62-4656-aeab-5a9ca1df6164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38619
57922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3861957922
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.12726843
Short name T933
Test name
Test status
Simulation time 159417154 ps
CPU time 0.81 seconds
Started Jun 24 05:25:14 PM PDT 24
Finished Jun 24 05:25:16 PM PDT 24
Peak memory 206088 kb
Host smart-ab3d1a87-ec8c-4cee-ae30-6cc0015ae095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12726
843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.12726843
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2497443385
Short name T1451
Test name
Test status
Simulation time 161127862 ps
CPU time 0.78 seconds
Started Jun 24 05:25:14 PM PDT 24
Finished Jun 24 05:25:16 PM PDT 24
Peak memory 206092 kb
Host smart-0b97ba94-5a27-4ace-97f2-da02edcf8918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24974
43385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2497443385
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.4026191961
Short name T1127
Test name
Test status
Simulation time 155638539 ps
CPU time 0.78 seconds
Started Jun 24 05:25:21 PM PDT 24
Finished Jun 24 05:25:25 PM PDT 24
Peak memory 206176 kb
Host smart-1b54c1f3-4fcf-46bc-8a8e-67537d418494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40261
91961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.4026191961
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.696294469
Short name T442
Test name
Test status
Simulation time 217127127 ps
CPU time 0.88 seconds
Started Jun 24 05:25:14 PM PDT 24
Finished Jun 24 05:25:16 PM PDT 24
Peak memory 206072 kb
Host smart-edb8ddf3-4ebf-4832-82f1-10c2cd1df1ee
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=696294469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.696294469
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1109736503
Short name T342
Test name
Test status
Simulation time 134048912 ps
CPU time 0.75 seconds
Started Jun 24 05:25:13 PM PDT 24
Finished Jun 24 05:25:16 PM PDT 24
Peak memory 206176 kb
Host smart-dd23f01d-9510-42c7-a23d-2eb1f41daf4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11097
36503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1109736503
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.202709066
Short name T1215
Test name
Test status
Simulation time 36280590 ps
CPU time 0.67 seconds
Started Jun 24 05:25:22 PM PDT 24
Finished Jun 24 05:25:26 PM PDT 24
Peak memory 206184 kb
Host smart-1e569f6d-2a59-4a03-b113-91c0e8637c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20270
9066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.202709066
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3029165337
Short name T1961
Test name
Test status
Simulation time 22517155528 ps
CPU time 45.36 seconds
Started Jun 24 05:25:13 PM PDT 24
Finished Jun 24 05:26:01 PM PDT 24
Peak memory 206400 kb
Host smart-0aeb87f1-d24c-4623-af80-2d3cc7e4f7ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30291
65337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3029165337
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3048148725
Short name T1192
Test name
Test status
Simulation time 150886691 ps
CPU time 0.76 seconds
Started Jun 24 05:25:14 PM PDT 24
Finished Jun 24 05:25:16 PM PDT 24
Peak memory 206176 kb
Host smart-2a9c3783-5768-4844-940e-17e1ce501d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30481
48725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3048148725
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.4117200148
Short name T1064
Test name
Test status
Simulation time 243856233 ps
CPU time 0.91 seconds
Started Jun 24 05:25:11 PM PDT 24
Finished Jun 24 05:25:13 PM PDT 24
Peak memory 206152 kb
Host smart-20de8ce4-8a36-4466-b5f2-77db42f190f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41172
00148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.4117200148
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.1903278643
Short name T1218
Test name
Test status
Simulation time 242058656 ps
CPU time 0.88 seconds
Started Jun 24 05:25:18 PM PDT 24
Finished Jun 24 05:25:21 PM PDT 24
Peak memory 206192 kb
Host smart-60c326b4-75b3-462f-ba63-30cebc66ed35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19032
78643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.1903278643
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.4153720296
Short name T452
Test name
Test status
Simulation time 193594933 ps
CPU time 0.86 seconds
Started Jun 24 05:25:14 PM PDT 24
Finished Jun 24 05:25:17 PM PDT 24
Peak memory 206152 kb
Host smart-9bc1126c-5a47-4995-b554-3b68f34d4b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41537
20296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.4153720296
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.1143807442
Short name T725
Test name
Test status
Simulation time 141082792 ps
CPU time 0.77 seconds
Started Jun 24 05:25:14 PM PDT 24
Finished Jun 24 05:25:16 PM PDT 24
Peak memory 206108 kb
Host smart-91913e84-e82b-45a0-abff-576c8e7d4a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11438
07442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.1143807442
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1706947546
Short name T1448
Test name
Test status
Simulation time 166400198 ps
CPU time 0.79 seconds
Started Jun 24 05:25:18 PM PDT 24
Finished Jun 24 05:25:21 PM PDT 24
Peak memory 206092 kb
Host smart-9a00191d-d055-4691-9a9e-774db1294572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17069
47546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1706947546
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3138997613
Short name T341
Test name
Test status
Simulation time 180395974 ps
CPU time 0.79 seconds
Started Jun 24 05:25:21 PM PDT 24
Finished Jun 24 05:25:25 PM PDT 24
Peak memory 206168 kb
Host smart-7e418c7a-7bd1-4b86-aa48-502f83964331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31389
97613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3138997613
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3695896361
Short name T2260
Test name
Test status
Simulation time 242970788 ps
CPU time 0.97 seconds
Started Jun 24 05:25:12 PM PDT 24
Finished Jun 24 05:25:14 PM PDT 24
Peak memory 206192 kb
Host smart-6ba8cecb-eeb5-4831-af07-6d7634036600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36958
96361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3695896361
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.987403339
Short name T1171
Test name
Test status
Simulation time 8252456820 ps
CPU time 60.5 seconds
Started Jun 24 05:25:10 PM PDT 24
Finished Jun 24 05:26:11 PM PDT 24
Peak memory 206400 kb
Host smart-fef7c455-b1f5-4514-9db8-826c78ebde4f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=987403339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.987403339
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.426858936
Short name T1159
Test name
Test status
Simulation time 252833580 ps
CPU time 0.91 seconds
Started Jun 24 05:25:21 PM PDT 24
Finished Jun 24 05:25:26 PM PDT 24
Peak memory 206176 kb
Host smart-8a699286-db83-4493-aa98-78d3bf209381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42685
8936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.426858936
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.616275955
Short name T946
Test name
Test status
Simulation time 182489019 ps
CPU time 0.82 seconds
Started Jun 24 05:25:14 PM PDT 24
Finished Jun 24 05:25:16 PM PDT 24
Peak memory 206192 kb
Host smart-084196a7-55d0-4403-8cb0-481ac8f581d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61627
5955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.616275955
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.2036903230
Short name T1951
Test name
Test status
Simulation time 14290274247 ps
CPU time 130.94 seconds
Started Jun 24 05:25:18 PM PDT 24
Finished Jun 24 05:27:31 PM PDT 24
Peak memory 206384 kb
Host smart-d1282643-b693-4654-bde9-5e1170810996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20369
03230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.2036903230
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.4257045506
Short name T2392
Test name
Test status
Simulation time 3496312261 ps
CPU time 4.16 seconds
Started Jun 24 05:25:21 PM PDT 24
Finished Jun 24 05:25:29 PM PDT 24
Peak memory 206240 kb
Host smart-41239a0f-845b-4bf4-8d56-d6d3130ec271
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4257045506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.4257045506
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.270622746
Short name T1295
Test name
Test status
Simulation time 13368767427 ps
CPU time 14.84 seconds
Started Jun 24 05:25:16 PM PDT 24
Finished Jun 24 05:25:32 PM PDT 24
Peak memory 206172 kb
Host smart-167f20c7-6984-48a7-8d46-aae157b1035a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=270622746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.270622746
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.4164523037
Short name T1671
Test name
Test status
Simulation time 23339294270 ps
CPU time 27.24 seconds
Started Jun 24 05:25:21 PM PDT 24
Finished Jun 24 05:25:52 PM PDT 24
Peak memory 206164 kb
Host smart-dd5bd298-7cbb-49fa-81d5-846fc53bdb1d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4164523037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.4164523037
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3179100246
Short name T157
Test name
Test status
Simulation time 147238397 ps
CPU time 0.83 seconds
Started Jun 24 05:25:19 PM PDT 24
Finished Jun 24 05:25:21 PM PDT 24
Peak memory 206412 kb
Host smart-2afdefbd-ea47-4d5b-b746-f1acac8333d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31791
00246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3179100246
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.3570522059
Short name T1491
Test name
Test status
Simulation time 180011533 ps
CPU time 0.8 seconds
Started Jun 24 05:25:20 PM PDT 24
Finished Jun 24 05:25:24 PM PDT 24
Peak memory 206160 kb
Host smart-376776c7-3a09-4ab1-bdb0-cafe8cb1b1aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35705
22059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.3570522059
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.2544923441
Short name T1682
Test name
Test status
Simulation time 390713656 ps
CPU time 1.38 seconds
Started Jun 24 05:25:18 PM PDT 24
Finished Jun 24 05:25:22 PM PDT 24
Peak memory 206172 kb
Host smart-0aa53310-07b2-4574-9dbf-6190f1c0c09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25449
23441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.2544923441
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.239580856
Short name T1029
Test name
Test status
Simulation time 906236350 ps
CPU time 2.08 seconds
Started Jun 24 05:25:19 PM PDT 24
Finished Jun 24 05:25:23 PM PDT 24
Peak memory 206132 kb
Host smart-b049bd40-21ba-454a-a3ff-a2afef5b9f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23958
0856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.239580856
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.1496238057
Short name T1195
Test name
Test status
Simulation time 17264390093 ps
CPU time 31.55 seconds
Started Jun 24 05:25:20 PM PDT 24
Finished Jun 24 05:25:55 PM PDT 24
Peak memory 206316 kb
Host smart-be4aedcb-3183-45b0-80cf-fb2a9697f22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14962
38057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.1496238057
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.2364723764
Short name T997
Test name
Test status
Simulation time 390266886 ps
CPU time 1.28 seconds
Started Jun 24 05:25:21 PM PDT 24
Finished Jun 24 05:25:25 PM PDT 24
Peak memory 206060 kb
Host smart-6300a0b2-62b2-414b-a4e6-34a0941b88c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23647
23764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.2364723764
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.1473917799
Short name T2310
Test name
Test status
Simulation time 197972066 ps
CPU time 0.78 seconds
Started Jun 24 05:25:24 PM PDT 24
Finished Jun 24 05:25:28 PM PDT 24
Peak memory 206096 kb
Host smart-11e2ac26-180d-49bf-b262-760e85d5770b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14739
17799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.1473917799
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.1881520862
Short name T1036
Test name
Test status
Simulation time 44908372 ps
CPU time 0.66 seconds
Started Jun 24 05:25:19 PM PDT 24
Finished Jun 24 05:25:23 PM PDT 24
Peak memory 206168 kb
Host smart-c54fefa1-cd4a-4291-b965-40a6eb8bbcf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18815
20862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1881520862
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3690362640
Short name T1754
Test name
Test status
Simulation time 884161181 ps
CPU time 2.06 seconds
Started Jun 24 05:25:20 PM PDT 24
Finished Jun 24 05:25:25 PM PDT 24
Peak memory 206284 kb
Host smart-e18f15c0-1f85-47f0-995b-bd8ee1d77645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36903
62640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3690362640
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.150902439
Short name T870
Test name
Test status
Simulation time 159644808 ps
CPU time 1.26 seconds
Started Jun 24 05:25:20 PM PDT 24
Finished Jun 24 05:25:24 PM PDT 24
Peak memory 206156 kb
Host smart-8c21f4d9-c844-4e31-b27b-3f8ca14ce3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15090
2439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.150902439
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.4109547312
Short name T1526
Test name
Test status
Simulation time 170511532 ps
CPU time 0.82 seconds
Started Jun 24 05:25:28 PM PDT 24
Finished Jun 24 05:25:32 PM PDT 24
Peak memory 206068 kb
Host smart-3510d823-de27-417e-ac78-2aa3f94a3323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41095
47312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.4109547312
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.804601213
Short name T1617
Test name
Test status
Simulation time 134821780 ps
CPU time 0.73 seconds
Started Jun 24 05:25:28 PM PDT 24
Finished Jun 24 05:25:33 PM PDT 24
Peak memory 206160 kb
Host smart-fe282d44-2b53-4565-8fdc-041c6167b256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80460
1213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.804601213
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2549202712
Short name T694
Test name
Test status
Simulation time 184927236 ps
CPU time 0.85 seconds
Started Jun 24 05:25:21 PM PDT 24
Finished Jun 24 05:25:25 PM PDT 24
Peak memory 206192 kb
Host smart-bc769f1a-1925-4d25-abf5-d240a52aa3a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25492
02712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2549202712
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.210805354
Short name T102
Test name
Test status
Simulation time 15229997157 ps
CPU time 142.97 seconds
Started Jun 24 05:25:21 PM PDT 24
Finished Jun 24 05:27:48 PM PDT 24
Peak memory 206300 kb
Host smart-b46b06db-c568-48df-a47e-0c76a942a137
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=210805354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.210805354
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.2023838129
Short name T1006
Test name
Test status
Simulation time 204650371 ps
CPU time 0.94 seconds
Started Jun 24 05:25:21 PM PDT 24
Finished Jun 24 05:25:25 PM PDT 24
Peak memory 206092 kb
Host smart-3318f1bf-52d7-4cae-b873-eac1f4b49690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20238
38129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.2023838129
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.2219289469
Short name T1610
Test name
Test status
Simulation time 23294009854 ps
CPU time 22.22 seconds
Started Jun 24 05:25:21 PM PDT 24
Finished Jun 24 05:25:47 PM PDT 24
Peak memory 206248 kb
Host smart-7b1b27b9-f2a7-4955-a90f-f91b931994a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22192
89469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.2219289469
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2423388524
Short name T578
Test name
Test status
Simulation time 3302155097 ps
CPU time 4.3 seconds
Started Jun 24 05:25:22 PM PDT 24
Finished Jun 24 05:25:29 PM PDT 24
Peak memory 206228 kb
Host smart-ae744982-9ae8-4077-a088-bd5f8ff8af60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24233
88524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2423388524
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.2191606352
Short name T698
Test name
Test status
Simulation time 10205676795 ps
CPU time 75.79 seconds
Started Jun 24 05:25:21 PM PDT 24
Finished Jun 24 05:26:40 PM PDT 24
Peak memory 206312 kb
Host smart-60ade107-6e90-4e1b-b59a-29827d1d8c81
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2191606352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.2191606352
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.707060327
Short name T669
Test name
Test status
Simulation time 246639434 ps
CPU time 0.99 seconds
Started Jun 24 05:25:27 PM PDT 24
Finished Jun 24 05:25:31 PM PDT 24
Peak memory 206196 kb
Host smart-91ce5e80-7917-4d56-9432-09e7bd0baa2a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=707060327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.707060327
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1223111802
Short name T1937
Test name
Test status
Simulation time 198094310 ps
CPU time 0.89 seconds
Started Jun 24 05:25:22 PM PDT 24
Finished Jun 24 05:25:27 PM PDT 24
Peak memory 206104 kb
Host smart-8d85d596-d271-4ab1-8903-84c1187f9f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12231
11802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1223111802
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.598056466
Short name T465
Test name
Test status
Simulation time 4418222622 ps
CPU time 33.37 seconds
Started Jun 24 05:25:23 PM PDT 24
Finished Jun 24 05:25:59 PM PDT 24
Peak memory 206300 kb
Host smart-ed916195-f54f-4a1a-be0f-10f752f1862b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59805
6466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.598056466
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.4000775240
Short name T728
Test name
Test status
Simulation time 8587888484 ps
CPU time 85.51 seconds
Started Jun 24 05:25:22 PM PDT 24
Finished Jun 24 05:26:51 PM PDT 24
Peak memory 206356 kb
Host smart-3fc33ed3-22a0-4b7e-8ab8-756c943079e5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4000775240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.4000775240
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.3008628567
Short name T1845
Test name
Test status
Simulation time 210231388 ps
CPU time 0.82 seconds
Started Jun 24 05:25:28 PM PDT 24
Finished Jun 24 05:25:33 PM PDT 24
Peak memory 206144 kb
Host smart-0e8d57bf-b08a-4cae-a5a5-78e3e203da6d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3008628567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3008628567
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.69104984
Short name T17
Test name
Test status
Simulation time 169862521 ps
CPU time 0.8 seconds
Started Jun 24 05:25:23 PM PDT 24
Finished Jun 24 05:25:27 PM PDT 24
Peak memory 206088 kb
Host smart-d6d8ec16-e92d-47f0-a397-1f8c782e731a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69104
984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.69104984
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.927376003
Short name T152
Test name
Test status
Simulation time 217538967 ps
CPU time 0.89 seconds
Started Jun 24 05:25:22 PM PDT 24
Finished Jun 24 05:25:26 PM PDT 24
Peak memory 206172 kb
Host smart-7c4a9e01-3d1a-4baa-bd78-1d24ada4f918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92737
6003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.927376003
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3371999440
Short name T2012
Test name
Test status
Simulation time 206790329 ps
CPU time 0.81 seconds
Started Jun 24 05:25:23 PM PDT 24
Finished Jun 24 05:25:27 PM PDT 24
Peak memory 206188 kb
Host smart-5e83d7f6-888a-4676-b58e-a644618a11eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33719
99440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3371999440
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.422606457
Short name T2271
Test name
Test status
Simulation time 183110248 ps
CPU time 0.9 seconds
Started Jun 24 05:25:23 PM PDT 24
Finished Jun 24 05:25:27 PM PDT 24
Peak memory 206176 kb
Host smart-1da8b6c9-1f6b-4a89-9c83-5671ba30a300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42260
6457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.422606457
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.402730378
Short name T1510
Test name
Test status
Simulation time 224808123 ps
CPU time 0.83 seconds
Started Jun 24 05:25:22 PM PDT 24
Finished Jun 24 05:25:27 PM PDT 24
Peak memory 206172 kb
Host smart-9cdd1cd2-a2c2-40e8-b40c-08289b08321a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40273
0378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.402730378
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.207373810
Short name T686
Test name
Test status
Simulation time 152162452 ps
CPU time 0.79 seconds
Started Jun 24 05:25:30 PM PDT 24
Finished Jun 24 05:25:34 PM PDT 24
Peak memory 206172 kb
Host smart-4558ccb2-245c-4ae7-8e20-22492046f35b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20737
3810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.207373810
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.191728536
Short name T1420
Test name
Test status
Simulation time 196261990 ps
CPU time 0.88 seconds
Started Jun 24 05:25:23 PM PDT 24
Finished Jun 24 05:25:27 PM PDT 24
Peak memory 206176 kb
Host smart-410f7387-3e21-4e0d-bd93-b62d135663c4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=191728536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.191728536
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1192173651
Short name T2184
Test name
Test status
Simulation time 138676707 ps
CPU time 0.76 seconds
Started Jun 24 05:25:21 PM PDT 24
Finished Jun 24 05:25:25 PM PDT 24
Peak memory 206156 kb
Host smart-9bd7c13a-1388-4e62-8269-68f1f50d2ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11921
73651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1192173651
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.349197739
Short name T1355
Test name
Test status
Simulation time 57956339 ps
CPU time 0.72 seconds
Started Jun 24 05:25:28 PM PDT 24
Finished Jun 24 05:25:33 PM PDT 24
Peak memory 206084 kb
Host smart-0d4b5444-7b3d-4886-b503-5c048a8c533d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34919
7739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.349197739
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1357808678
Short name T2108
Test name
Test status
Simulation time 18168842713 ps
CPU time 36.85 seconds
Started Jun 24 05:25:26 PM PDT 24
Finished Jun 24 05:26:06 PM PDT 24
Peak memory 206296 kb
Host smart-409738d5-465d-40e9-8912-f6782ce50234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13578
08678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1357808678
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2186762291
Short name T1221
Test name
Test status
Simulation time 168237347 ps
CPU time 0.82 seconds
Started Jun 24 05:25:26 PM PDT 24
Finished Jun 24 05:25:30 PM PDT 24
Peak memory 206096 kb
Host smart-aa2b2c44-21c2-4324-9dd4-bacd39aa3f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21867
62291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2186762291
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.802177613
Short name T2286
Test name
Test status
Simulation time 274767935 ps
CPU time 0.91 seconds
Started Jun 24 05:25:28 PM PDT 24
Finished Jun 24 05:25:33 PM PDT 24
Peak memory 206112 kb
Host smart-2e4880a6-d177-48d1-ae67-df1b96dfe08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80217
7613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.802177613
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.3156411652
Short name T462
Test name
Test status
Simulation time 204382692 ps
CPU time 0.85 seconds
Started Jun 24 05:25:32 PM PDT 24
Finished Jun 24 05:25:36 PM PDT 24
Peak memory 206200 kb
Host smart-47dd6c37-2e9a-4ec4-83bd-10368af9650a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31564
11652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.3156411652
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3889905226
Short name T1775
Test name
Test status
Simulation time 188856461 ps
CPU time 0.82 seconds
Started Jun 24 05:25:29 PM PDT 24
Finished Jun 24 05:25:33 PM PDT 24
Peak memory 206176 kb
Host smart-0b880d8e-9598-4308-9b3c-d6d42c2d743b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38899
05226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3889905226
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2130879497
Short name T1175
Test name
Test status
Simulation time 164235528 ps
CPU time 0.79 seconds
Started Jun 24 05:25:26 PM PDT 24
Finished Jun 24 05:25:30 PM PDT 24
Peak memory 206116 kb
Host smart-9b5e7e54-172b-43ca-9b0c-8e16d3d59f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21308
79497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2130879497
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.990954169
Short name T1279
Test name
Test status
Simulation time 156833914 ps
CPU time 0.77 seconds
Started Jun 24 05:25:31 PM PDT 24
Finished Jun 24 05:25:35 PM PDT 24
Peak memory 206264 kb
Host smart-8e7163ec-4f74-4393-bbc6-1f7833833190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99095
4169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.990954169
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3953491385
Short name T722
Test name
Test status
Simulation time 147677177 ps
CPU time 0.74 seconds
Started Jun 24 05:25:31 PM PDT 24
Finished Jun 24 05:25:36 PM PDT 24
Peak memory 206172 kb
Host smart-f5c66189-6170-4023-9b8d-b1d3cdd129e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39534
91385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3953491385
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.55106098
Short name T1594
Test name
Test status
Simulation time 216888262 ps
CPU time 1.03 seconds
Started Jun 24 05:25:26 PM PDT 24
Finished Jun 24 05:25:29 PM PDT 24
Peak memory 206124 kb
Host smart-f45f1bc4-f411-4edb-a8e6-5e5012120ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55106
098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.55106098
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.1254261674
Short name T2410
Test name
Test status
Simulation time 10926646845 ps
CPU time 300.26 seconds
Started Jun 24 05:25:26 PM PDT 24
Finished Jun 24 05:30:29 PM PDT 24
Peak memory 206368 kb
Host smart-114a81d1-b5d2-4dd1-b596-1c6f395c405a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1254261674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.1254261674
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.742402949
Short name T543
Test name
Test status
Simulation time 151545730 ps
CPU time 0.8 seconds
Started Jun 24 05:25:26 PM PDT 24
Finished Jun 24 05:25:30 PM PDT 24
Peak memory 206100 kb
Host smart-b423ba20-143d-44c3-b5d8-d2df8db819ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74240
2949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.742402949
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.534695848
Short name T1548
Test name
Test status
Simulation time 169740436 ps
CPU time 0.78 seconds
Started Jun 24 05:25:28 PM PDT 24
Finished Jun 24 05:25:31 PM PDT 24
Peak memory 206188 kb
Host smart-e75e4839-f839-48a8-992c-ff02337bc5a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53469
5848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.534695848
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1494897957
Short name T337
Test name
Test status
Simulation time 14087979629 ps
CPU time 139.03 seconds
Started Jun 24 05:25:27 PM PDT 24
Finished Jun 24 05:27:49 PM PDT 24
Peak memory 206336 kb
Host smart-1c05837d-2a37-47d1-9988-d2e1d1863e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14948
97957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1494897957
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.1270800099
Short name T1905
Test name
Test status
Simulation time 4379657102 ps
CPU time 4.89 seconds
Started Jun 24 05:25:34 PM PDT 24
Finished Jun 24 05:25:41 PM PDT 24
Peak memory 206240 kb
Host smart-71887d6c-2c3e-46c2-9e9d-510920374ade
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1270800099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.1270800099
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3161618666
Short name T2193
Test name
Test status
Simulation time 13447050897 ps
CPU time 14.65 seconds
Started Jun 24 05:25:30 PM PDT 24
Finished Jun 24 05:25:48 PM PDT 24
Peak memory 206232 kb
Host smart-97a526a6-6793-47c6-91c3-2aa6233f56c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3161618666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3161618666
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.983193349
Short name T2084
Test name
Test status
Simulation time 23354529925 ps
CPU time 28.55 seconds
Started Jun 24 05:25:27 PM PDT 24
Finished Jun 24 05:25:59 PM PDT 24
Peak memory 206244 kb
Host smart-7d222e14-2837-4338-9ea6-4f3eead635d7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=983193349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.983193349
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2825713626
Short name T1517
Test name
Test status
Simulation time 167355955 ps
CPU time 0.82 seconds
Started Jun 24 05:25:27 PM PDT 24
Finished Jun 24 05:25:31 PM PDT 24
Peak memory 206180 kb
Host smart-098049f4-b601-4612-aefa-942dc2e79ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28257
13626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2825713626
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.3669468411
Short name T394
Test name
Test status
Simulation time 147141145 ps
CPU time 0.78 seconds
Started Jun 24 05:25:28 PM PDT 24
Finished Jun 24 05:25:32 PM PDT 24
Peak memory 206136 kb
Host smart-2affe270-f96b-44a9-9040-5581dd62f3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36694
68411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.3669468411
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.127759227
Short name T744
Test name
Test status
Simulation time 343766855 ps
CPU time 1.12 seconds
Started Jun 24 05:25:27 PM PDT 24
Finished Jun 24 05:25:31 PM PDT 24
Peak memory 206172 kb
Host smart-b2b31a37-dc2b-4401-9ef0-d392a58f7cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12775
9227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.127759227
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1989895317
Short name T190
Test name
Test status
Simulation time 957788137 ps
CPU time 2.32 seconds
Started Jun 24 05:25:27 PM PDT 24
Finished Jun 24 05:25:33 PM PDT 24
Peak memory 206304 kb
Host smart-4b3131ce-3f40-4b79-98d7-193543728535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19898
95317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1989895317
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.1505860590
Short name T1307
Test name
Test status
Simulation time 17049668880 ps
CPU time 29.02 seconds
Started Jun 24 05:25:31 PM PDT 24
Finished Jun 24 05:26:04 PM PDT 24
Peak memory 206276 kb
Host smart-f6cf1cf2-1ffd-47da-88dc-eebe1e7af9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15058
60590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.1505860590
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.3565496106
Short name T2387
Test name
Test status
Simulation time 392941503 ps
CPU time 1.42 seconds
Started Jun 24 05:25:27 PM PDT 24
Finished Jun 24 05:25:32 PM PDT 24
Peak memory 206060 kb
Host smart-f0441f41-212e-43e8-a16f-2f689e21ca94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35654
96106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.3565496106
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.374524744
Short name T1511
Test name
Test status
Simulation time 141440361 ps
CPU time 0.74 seconds
Started Jun 24 05:25:28 PM PDT 24
Finished Jun 24 05:25:33 PM PDT 24
Peak memory 206128 kb
Host smart-0905e868-897f-485f-886b-f24137588f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37452
4744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.374524744
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2217884362
Short name T2471
Test name
Test status
Simulation time 36367326 ps
CPU time 0.65 seconds
Started Jun 24 05:25:31 PM PDT 24
Finished Jun 24 05:25:35 PM PDT 24
Peak memory 206172 kb
Host smart-8ef13eb8-f116-4a3d-a6d6-b5dca89b7cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22178
84362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2217884362
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.544387419
Short name T1043
Test name
Test status
Simulation time 962706413 ps
CPU time 2.21 seconds
Started Jun 24 05:25:29 PM PDT 24
Finished Jun 24 05:25:35 PM PDT 24
Peak memory 206176 kb
Host smart-3b476370-57aa-45d2-a140-c7bd0474baec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54438
7419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.544387419
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1475093688
Short name T1121
Test name
Test status
Simulation time 161121494 ps
CPU time 1.43 seconds
Started Jun 24 05:25:29 PM PDT 24
Finished Jun 24 05:25:34 PM PDT 24
Peak memory 206148 kb
Host smart-6e07ce44-3cc7-4582-8943-292d7aad236d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14750
93688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1475093688
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.1919005854
Short name T1083
Test name
Test status
Simulation time 157245047 ps
CPU time 0.81 seconds
Started Jun 24 05:25:37 PM PDT 24
Finished Jun 24 05:25:40 PM PDT 24
Peak memory 206176 kb
Host smart-4e68c4d7-9708-4756-b962-2ab747b61250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19190
05854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1919005854
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3138667862
Short name T2057
Test name
Test status
Simulation time 134203685 ps
CPU time 0.84 seconds
Started Jun 24 05:25:37 PM PDT 24
Finished Jun 24 05:25:40 PM PDT 24
Peak memory 206184 kb
Host smart-03b243af-cf88-4389-9e37-366210bc0277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31386
67862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3138667862
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.3786113343
Short name T1537
Test name
Test status
Simulation time 7383505984 ps
CPU time 54.6 seconds
Started Jun 24 05:25:27 PM PDT 24
Finished Jun 24 05:26:25 PM PDT 24
Peak memory 206376 kb
Host smart-8afcddc1-d152-4ca3-87da-68e1194f8642
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3786113343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.3786113343
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2130943492
Short name T2163
Test name
Test status
Simulation time 181519875 ps
CPU time 0.82 seconds
Started Jun 24 05:25:31 PM PDT 24
Finished Jun 24 05:25:35 PM PDT 24
Peak memory 206148 kb
Host smart-efe580c8-d713-4422-aa98-47bd0f8a8aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21309
43492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2130943492
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.4268985344
Short name T1368
Test name
Test status
Simulation time 23335175388 ps
CPU time 22.02 seconds
Started Jun 24 05:25:30 PM PDT 24
Finished Jun 24 05:25:56 PM PDT 24
Peak memory 206144 kb
Host smart-23dabd1f-43fd-472e-bd67-fbc2fd56d1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42689
85344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.4268985344
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3440823640
Short name T2080
Test name
Test status
Simulation time 3302781748 ps
CPU time 3.62 seconds
Started Jun 24 05:25:25 PM PDT 24
Finished Jun 24 05:25:32 PM PDT 24
Peak memory 206240 kb
Host smart-812fa54a-7a5d-457a-b574-8d528c830c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34408
23640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3440823640
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.2287152573
Short name T921
Test name
Test status
Simulation time 14385118717 ps
CPU time 412 seconds
Started Jun 24 05:25:34 PM PDT 24
Finished Jun 24 05:32:29 PM PDT 24
Peak memory 206316 kb
Host smart-6fb49e68-4c8a-4108-803f-a529f02834c3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2287152573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.2287152573
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.2152129700
Short name T1637
Test name
Test status
Simulation time 237534281 ps
CPU time 0.94 seconds
Started Jun 24 05:25:35 PM PDT 24
Finished Jun 24 05:25:38 PM PDT 24
Peak memory 206196 kb
Host smart-9d02925e-4a6f-4623-a5c6-1fd43093a042
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2152129700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.2152129700
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1337170809
Short name T1187
Test name
Test status
Simulation time 203121327 ps
CPU time 0.88 seconds
Started Jun 24 05:25:30 PM PDT 24
Finished Jun 24 05:25:34 PM PDT 24
Peak memory 206104 kb
Host smart-09db28ae-c697-4943-a6f5-4930da68c3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13371
70809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1337170809
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.1222602917
Short name T885
Test name
Test status
Simulation time 3625031653 ps
CPU time 101.17 seconds
Started Jun 24 05:25:36 PM PDT 24
Finished Jun 24 05:27:19 PM PDT 24
Peak memory 206336 kb
Host smart-939a5c66-9fdf-4d0b-8ac7-201825069698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12226
02917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.1222602917
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.1840848153
Short name T918
Test name
Test status
Simulation time 4380784963 ps
CPU time 42.92 seconds
Started Jun 24 05:25:35 PM PDT 24
Finished Jun 24 05:26:21 PM PDT 24
Peak memory 206396 kb
Host smart-38c68d77-c033-4e25-b94d-f8e79a4607c4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1840848153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.1840848153
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.1861438355
Short name T1472
Test name
Test status
Simulation time 155443596 ps
CPU time 0.83 seconds
Started Jun 24 05:25:38 PM PDT 24
Finished Jun 24 05:25:41 PM PDT 24
Peak memory 206188 kb
Host smart-7038e0c3-f83c-4b28-9b0c-bb4661b4fbce
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1861438355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.1861438355
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2109336653
Short name T2385
Test name
Test status
Simulation time 147193403 ps
CPU time 0.76 seconds
Started Jun 24 05:25:26 PM PDT 24
Finished Jun 24 05:25:29 PM PDT 24
Peak memory 206180 kb
Host smart-314dc1fd-2ca0-4032-982e-35a45a35879e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21093
36653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2109336653
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2722774223
Short name T132
Test name
Test status
Simulation time 212888900 ps
CPU time 0.86 seconds
Started Jun 24 05:25:36 PM PDT 24
Finished Jun 24 05:25:39 PM PDT 24
Peak memory 206144 kb
Host smart-7586a74a-6461-4a6f-8b6c-a06f267d431e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27227
74223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2722774223
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.3068239197
Short name T2482
Test name
Test status
Simulation time 151217039 ps
CPU time 0.81 seconds
Started Jun 24 05:25:36 PM PDT 24
Finished Jun 24 05:25:40 PM PDT 24
Peak memory 206068 kb
Host smart-88110f25-1a10-4898-9e29-568c3ce79e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30682
39197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3068239197
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.70298705
Short name T754
Test name
Test status
Simulation time 202427341 ps
CPU time 0.85 seconds
Started Jun 24 05:25:34 PM PDT 24
Finished Jun 24 05:25:38 PM PDT 24
Peak memory 206168 kb
Host smart-42d7f822-fae8-4efc-9d66-d50308214e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70298
705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.70298705
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.4118022445
Short name T65
Test name
Test status
Simulation time 161887194 ps
CPU time 0.77 seconds
Started Jun 24 05:25:36 PM PDT 24
Finished Jun 24 05:25:39 PM PDT 24
Peak memory 206196 kb
Host smart-bb02ba73-a16d-4aae-8008-e2545353eadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41180
22445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.4118022445
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3038321440
Short name T1419
Test name
Test status
Simulation time 168112516 ps
CPU time 0.79 seconds
Started Jun 24 05:25:37 PM PDT 24
Finished Jun 24 05:25:40 PM PDT 24
Peak memory 206068 kb
Host smart-908162d2-72d5-4ab4-aa7d-2f93d9e43384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30383
21440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3038321440
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.4112769821
Short name T2287
Test name
Test status
Simulation time 224836330 ps
CPU time 0.89 seconds
Started Jun 24 05:25:35 PM PDT 24
Finished Jun 24 05:25:38 PM PDT 24
Peak memory 206076 kb
Host smart-05c9d821-439b-4d15-a504-2628fd4503b3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4112769821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.4112769821
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.1934126345
Short name T2409
Test name
Test status
Simulation time 153170106 ps
CPU time 0.79 seconds
Started Jun 24 05:25:36 PM PDT 24
Finished Jun 24 05:25:39 PM PDT 24
Peak memory 206172 kb
Host smart-20c60840-3264-40b0-b4a1-d64aed63ef0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19341
26345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.1934126345
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.532627431
Short name T657
Test name
Test status
Simulation time 36202176 ps
CPU time 0.66 seconds
Started Jun 24 05:25:35 PM PDT 24
Finished Jun 24 05:25:37 PM PDT 24
Peak memory 206184 kb
Host smart-fddb156f-13e6-4070-baae-30809dcbde93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53262
7431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.532627431
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1776686107
Short name T275
Test name
Test status
Simulation time 15321657527 ps
CPU time 33.92 seconds
Started Jun 24 05:25:42 PM PDT 24
Finished Jun 24 05:26:17 PM PDT 24
Peak memory 206368 kb
Host smart-311308fc-d335-4962-9977-79007b79845e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17766
86107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1776686107
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3470529142
Short name T2403
Test name
Test status
Simulation time 189125868 ps
CPU time 0.83 seconds
Started Jun 24 05:25:42 PM PDT 24
Finished Jun 24 05:25:44 PM PDT 24
Peak memory 206172 kb
Host smart-a571403e-34ff-452a-b2ea-c1701db61f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34705
29142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3470529142
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.1573938254
Short name T1308
Test name
Test status
Simulation time 162727317 ps
CPU time 0.83 seconds
Started Jun 24 05:25:37 PM PDT 24
Finished Jun 24 05:25:40 PM PDT 24
Peak memory 206176 kb
Host smart-d6d92c73-1486-42ef-8b6c-7b08b61c8e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15739
38254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1573938254
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.4260609088
Short name T1950
Test name
Test status
Simulation time 168744346 ps
CPU time 0.79 seconds
Started Jun 24 05:25:37 PM PDT 24
Finished Jun 24 05:25:40 PM PDT 24
Peak memory 206176 kb
Host smart-4d1e8b17-76b1-4e79-917c-bfae946f8513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42606
09088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.4260609088
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.2768062801
Short name T791
Test name
Test status
Simulation time 182979403 ps
CPU time 0.85 seconds
Started Jun 24 05:25:37 PM PDT 24
Finished Jun 24 05:25:40 PM PDT 24
Peak memory 206080 kb
Host smart-9fa95c46-6cfe-4cbb-bddb-59e6a6489a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27680
62801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.2768062801
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.724605226
Short name T492
Test name
Test status
Simulation time 163244512 ps
CPU time 0.77 seconds
Started Jun 24 05:25:38 PM PDT 24
Finished Jun 24 05:25:41 PM PDT 24
Peak memory 206172 kb
Host smart-ba9b377f-ffa4-4c8e-abf1-279154ade77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72460
5226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.724605226
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1426010738
Short name T2139
Test name
Test status
Simulation time 175824017 ps
CPU time 0.82 seconds
Started Jun 24 05:25:36 PM PDT 24
Finished Jun 24 05:25:40 PM PDT 24
Peak memory 206192 kb
Host smart-785eb66a-2042-48e7-901f-6e9f2101c7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14260
10738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1426010738
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.74499718
Short name T1920
Test name
Test status
Simulation time 199901446 ps
CPU time 0.84 seconds
Started Jun 24 05:25:38 PM PDT 24
Finished Jun 24 05:25:41 PM PDT 24
Peak memory 206148 kb
Host smart-5d11db9b-1e7e-4a4a-b4c6-d97cdb5427b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74499
718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.74499718
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3532793716
Short name T1427
Test name
Test status
Simulation time 235093044 ps
CPU time 0.86 seconds
Started Jun 24 05:25:36 PM PDT 24
Finished Jun 24 05:25:39 PM PDT 24
Peak memory 206192 kb
Host smart-4f70723f-d657-4062-8e31-c55a92745a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35327
93716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3532793716
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.3862285731
Short name T444
Test name
Test status
Simulation time 10492370591 ps
CPU time 103.96 seconds
Started Jun 24 05:25:36 PM PDT 24
Finished Jun 24 05:27:22 PM PDT 24
Peak memory 206328 kb
Host smart-6c075387-7232-47a4-af6b-db54f8791849
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3862285731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.3862285731
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3626434365
Short name T2175
Test name
Test status
Simulation time 183286525 ps
CPU time 0.82 seconds
Started Jun 24 05:25:36 PM PDT 24
Finished Jun 24 05:25:39 PM PDT 24
Peak memory 206180 kb
Host smart-d6ed4b8e-575e-46f7-9c3a-5960cde93dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36264
34365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3626434365
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.4276779293
Short name T2311
Test name
Test status
Simulation time 162510620 ps
CPU time 0.8 seconds
Started Jun 24 05:25:37 PM PDT 24
Finished Jun 24 05:25:40 PM PDT 24
Peak memory 206176 kb
Host smart-f7c33b78-3651-40c6-b0fe-586014f4638b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42767
79293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.4276779293
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.4247093956
Short name T562
Test name
Test status
Simulation time 9307916543 ps
CPU time 267.43 seconds
Started Jun 24 05:25:36 PM PDT 24
Finished Jun 24 05:30:05 PM PDT 24
Peak memory 206384 kb
Host smart-c706a85e-7b4b-4469-83c3-234bf0dcb41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42470
93956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.4247093956
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.2063053166
Short name T1503
Test name
Test status
Simulation time 4326556853 ps
CPU time 4.93 seconds
Started Jun 24 05:25:37 PM PDT 24
Finished Jun 24 05:25:44 PM PDT 24
Peak memory 206232 kb
Host smart-84ba4f3a-c72e-4943-8c83-a41b5a7d4b60
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2063053166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.2063053166
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.37451226
Short name T772
Test name
Test status
Simulation time 13410846176 ps
CPU time 11.65 seconds
Started Jun 24 05:25:38 PM PDT 24
Finished Jun 24 05:25:52 PM PDT 24
Peak memory 206372 kb
Host smart-aaa64613-6528-49d1-93b5-c1df6e04b5d4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=37451226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.37451226
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.870905361
Short name T887
Test name
Test status
Simulation time 23346429354 ps
CPU time 25.28 seconds
Started Jun 24 05:25:37 PM PDT 24
Finished Jun 24 05:26:05 PM PDT 24
Peak memory 206232 kb
Host smart-665f9c86-4769-40a5-8358-81a361e1e8ab
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=870905361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.870905361
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1406761501
Short name T1956
Test name
Test status
Simulation time 236629077 ps
CPU time 0.95 seconds
Started Jun 24 05:25:37 PM PDT 24
Finished Jun 24 05:25:41 PM PDT 24
Peak memory 206152 kb
Host smart-850e6e76-c4d1-4d2e-9086-3807b43821fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14067
61501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1406761501
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2226361769
Short name T1963
Test name
Test status
Simulation time 149015727 ps
CPU time 0.79 seconds
Started Jun 24 05:25:34 PM PDT 24
Finished Jun 24 05:25:37 PM PDT 24
Peak memory 206108 kb
Host smart-b80e5105-4346-43df-83c4-d973acbeef9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22263
61769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2226361769
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.1636205004
Short name T110
Test name
Test status
Simulation time 347464714 ps
CPU time 1.18 seconds
Started Jun 24 05:25:43 PM PDT 24
Finished Jun 24 05:25:46 PM PDT 24
Peak memory 206168 kb
Host smart-4bcfb1d5-a523-4d8f-bfd5-2b9ad43ec773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16362
05004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.1636205004
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.1927410331
Short name T1895
Test name
Test status
Simulation time 300066248 ps
CPU time 1.01 seconds
Started Jun 24 05:25:37 PM PDT 24
Finished Jun 24 05:25:40 PM PDT 24
Peak memory 206172 kb
Host smart-c000f30a-b53b-407e-b5aa-5da264559a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19274
10331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1927410331
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.3319885419
Short name T2002
Test name
Test status
Simulation time 15770664128 ps
CPU time 26.52 seconds
Started Jun 24 05:25:40 PM PDT 24
Finished Jun 24 05:26:08 PM PDT 24
Peak memory 206476 kb
Host smart-93ab4754-571c-4d58-b687-b56c226e4722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33198
85419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.3319885419
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.3713066111
Short name T1590
Test name
Test status
Simulation time 494914372 ps
CPU time 1.32 seconds
Started Jun 24 05:25:40 PM PDT 24
Finished Jun 24 05:25:43 PM PDT 24
Peak memory 206360 kb
Host smart-c12b2484-1f21-4c31-a4d9-d9e360bfef83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37130
66111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.3713066111
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2306458272
Short name T1410
Test name
Test status
Simulation time 153630852 ps
CPU time 0.83 seconds
Started Jun 24 05:25:36 PM PDT 24
Finished Jun 24 05:25:40 PM PDT 24
Peak memory 206056 kb
Host smart-20e01dab-652e-457d-b591-5143ff1589ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23064
58272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2306458272
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.794774237
Short name T903
Test name
Test status
Simulation time 31364229 ps
CPU time 0.67 seconds
Started Jun 24 05:25:43 PM PDT 24
Finished Jun 24 05:25:45 PM PDT 24
Peak memory 206160 kb
Host smart-d0dbf42b-cc1c-44fd-a6a3-cf6ab614355b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79477
4237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.794774237
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.2570588256
Short name T1776
Test name
Test status
Simulation time 936168078 ps
CPU time 2.02 seconds
Started Jun 24 05:25:38 PM PDT 24
Finished Jun 24 05:25:42 PM PDT 24
Peak memory 206304 kb
Host smart-8ca6db5c-a1df-4fc8-b465-2a4f13a7c4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25705
88256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2570588256
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3847778508
Short name T2317
Test name
Test status
Simulation time 196034007 ps
CPU time 2.41 seconds
Started Jun 24 05:25:44 PM PDT 24
Finished Jun 24 05:25:48 PM PDT 24
Peak memory 206192 kb
Host smart-a77f8f8b-3509-4f38-aa94-ab54ca7f656a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38477
78508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3847778508
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3364663753
Short name T2203
Test name
Test status
Simulation time 194438693 ps
CPU time 0.86 seconds
Started Jun 24 05:25:46 PM PDT 24
Finished Jun 24 05:25:48 PM PDT 24
Peak memory 206176 kb
Host smart-017e5daa-800d-4c04-8a5f-3a953dd6a3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33646
63753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3364663753
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1610844488
Short name T1838
Test name
Test status
Simulation time 148093947 ps
CPU time 0.77 seconds
Started Jun 24 05:25:45 PM PDT 24
Finished Jun 24 05:25:47 PM PDT 24
Peak memory 206428 kb
Host smart-678f20ef-63de-407c-b8f3-db2f51db111b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16108
44488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1610844488
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1323307265
Short name T2495
Test name
Test status
Simulation time 210867455 ps
CPU time 0.9 seconds
Started Jun 24 05:25:46 PM PDT 24
Finished Jun 24 05:25:49 PM PDT 24
Peak memory 206176 kb
Host smart-df7f1e97-5c74-426b-bd18-9b1c674ddef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13233
07265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1323307265
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2044874867
Short name T2014
Test name
Test status
Simulation time 222086761 ps
CPU time 0.86 seconds
Started Jun 24 05:25:43 PM PDT 24
Finished Jun 24 05:25:46 PM PDT 24
Peak memory 206168 kb
Host smart-8af4b971-0923-4f5f-b78a-bbfe9cb695fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20448
74867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2044874867
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.1966710297
Short name T1385
Test name
Test status
Simulation time 23293190844 ps
CPU time 22.37 seconds
Started Jun 24 05:25:48 PM PDT 24
Finished Jun 24 05:26:13 PM PDT 24
Peak memory 206200 kb
Host smart-949ed556-1d1b-404e-a002-754cd1fc620f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19667
10297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.1966710297
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3675266420
Short name T1457
Test name
Test status
Simulation time 3302150655 ps
CPU time 3.7 seconds
Started Jun 24 05:25:43 PM PDT 24
Finished Jun 24 05:25:49 PM PDT 24
Peak memory 206228 kb
Host smart-69310b6a-c8f7-41ee-81f5-cc1c2f198a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36752
66420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3675266420
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.637138748
Short name T2509
Test name
Test status
Simulation time 5391392446 ps
CPU time 146.61 seconds
Started Jun 24 05:25:42 PM PDT 24
Finished Jun 24 05:28:10 PM PDT 24
Peak memory 206396 kb
Host smart-79b123e2-f670-48b6-8dee-d815f8636c76
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=637138748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.637138748
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.553624648
Short name T2303
Test name
Test status
Simulation time 289235457 ps
CPU time 0.94 seconds
Started Jun 24 05:25:47 PM PDT 24
Finished Jun 24 05:25:50 PM PDT 24
Peak memory 206352 kb
Host smart-72f6dfe3-8ff9-4769-a29e-75370c82fe7c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=553624648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.553624648
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1157689262
Short name T1325
Test name
Test status
Simulation time 188783686 ps
CPU time 0.82 seconds
Started Jun 24 05:25:44 PM PDT 24
Finished Jun 24 05:25:47 PM PDT 24
Peak memory 206172 kb
Host smart-2618d4a7-6508-4e33-b43b-7051695f8373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11576
89262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1157689262
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1302115292
Short name T1785
Test name
Test status
Simulation time 10669799400 ps
CPU time 77.88 seconds
Started Jun 24 05:25:45 PM PDT 24
Finished Jun 24 05:27:04 PM PDT 24
Peak memory 206320 kb
Host smart-01b6b5c0-2533-40f4-bd3f-ab8cbcdb2d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13021
15292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1302115292
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.3326296411
Short name T2082
Test name
Test status
Simulation time 7875741068 ps
CPU time 76.71 seconds
Started Jun 24 05:25:44 PM PDT 24
Finished Jun 24 05:27:02 PM PDT 24
Peak memory 206548 kb
Host smart-c375aeab-ae66-4685-b1ad-624be708168a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3326296411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.3326296411
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2523353610
Short name T306
Test name
Test status
Simulation time 185161430 ps
CPU time 0.94 seconds
Started Jun 24 05:25:46 PM PDT 24
Finished Jun 24 05:25:49 PM PDT 24
Peak memory 206196 kb
Host smart-a5ae96c4-77c5-4d37-8f49-8bc6021503bb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2523353610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2523353610
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.532956948
Short name T424
Test name
Test status
Simulation time 182186986 ps
CPU time 0.88 seconds
Started Jun 24 05:25:44 PM PDT 24
Finished Jun 24 05:25:46 PM PDT 24
Peak memory 206196 kb
Host smart-a2b63148-178f-440f-a0d1-5528066ec453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53295
6948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.532956948
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3050996922
Short name T148
Test name
Test status
Simulation time 251060300 ps
CPU time 0.93 seconds
Started Jun 24 05:25:46 PM PDT 24
Finished Jun 24 05:25:48 PM PDT 24
Peak memory 206080 kb
Host smart-b6a3ce78-d98a-4572-bf19-e903e4fd62be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30509
96922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3050996922
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.198346093
Short name T1436
Test name
Test status
Simulation time 200090405 ps
CPU time 0.91 seconds
Started Jun 24 05:25:43 PM PDT 24
Finished Jun 24 05:25:45 PM PDT 24
Peak memory 206072 kb
Host smart-572ad1dc-fd53-4094-880a-c08cb4e2899a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19834
6093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.198346093
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2598048141
Short name T2489
Test name
Test status
Simulation time 156106911 ps
CPU time 0.8 seconds
Started Jun 24 05:25:43 PM PDT 24
Finished Jun 24 05:25:45 PM PDT 24
Peak memory 206152 kb
Host smart-df7567ea-ba76-4692-976e-c251c15f654f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25980
48141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2598048141
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3708967453
Short name T1642
Test name
Test status
Simulation time 152854062 ps
CPU time 0.77 seconds
Started Jun 24 05:25:48 PM PDT 24
Finished Jun 24 05:25:51 PM PDT 24
Peak memory 206144 kb
Host smart-496f596a-6a4b-4cd4-9af4-29d326078729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37089
67453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3708967453
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1644046072
Short name T180
Test name
Test status
Simulation time 181530727 ps
CPU time 0.92 seconds
Started Jun 24 05:25:45 PM PDT 24
Finished Jun 24 05:25:47 PM PDT 24
Peak memory 206100 kb
Host smart-4996078d-1499-407d-95c5-2eb2b364e05b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16440
46072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1644046072
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.3347403473
Short name T1248
Test name
Test status
Simulation time 199662072 ps
CPU time 0.89 seconds
Started Jun 24 05:25:45 PM PDT 24
Finished Jun 24 05:25:48 PM PDT 24
Peak memory 206176 kb
Host smart-f30cf941-1874-4eda-b2fe-b1f455fc42ae
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3347403473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.3347403473
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.2539094970
Short name T1813
Test name
Test status
Simulation time 149655927 ps
CPU time 0.76 seconds
Started Jun 24 05:25:47 PM PDT 24
Finished Jun 24 05:25:50 PM PDT 24
Peak memory 206168 kb
Host smart-b85010fe-5d89-4495-b7c8-31a722e256d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25390
94970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.2539094970
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.4074974851
Short name T2438
Test name
Test status
Simulation time 35236322 ps
CPU time 0.65 seconds
Started Jun 24 05:25:47 PM PDT 24
Finished Jun 24 05:25:50 PM PDT 24
Peak memory 206168 kb
Host smart-22e14cfe-3bb1-4f2e-9195-5eab623a44cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40749
74851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.4074974851
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1007111372
Short name T2174
Test name
Test status
Simulation time 19677737651 ps
CPU time 41.23 seconds
Started Jun 24 05:25:48 PM PDT 24
Finished Jun 24 05:26:31 PM PDT 24
Peak memory 206400 kb
Host smart-525da659-546c-484a-9aa5-b219d741426c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10071
11372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1007111372
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2436684407
Short name T1234
Test name
Test status
Simulation time 179492571 ps
CPU time 0.89 seconds
Started Jun 24 05:25:49 PM PDT 24
Finished Jun 24 05:25:51 PM PDT 24
Peak memory 206132 kb
Host smart-2ef7e7c6-614c-4a43-bda9-e6a5218c9cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24366
84407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2436684407
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1716948878
Short name T314
Test name
Test status
Simulation time 163477883 ps
CPU time 0.79 seconds
Started Jun 24 05:25:43 PM PDT 24
Finished Jun 24 05:25:45 PM PDT 24
Peak memory 206164 kb
Host smart-87310bbc-d8c4-413f-9af3-18ef1b16a4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17169
48878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1716948878
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.2409339014
Short name T2028
Test name
Test status
Simulation time 244669284 ps
CPU time 0.9 seconds
Started Jun 24 05:25:46 PM PDT 24
Finished Jun 24 05:25:49 PM PDT 24
Peak memory 206172 kb
Host smart-81b7a8aa-b7fb-41a2-8732-10b030828fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24093
39014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.2409339014
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.1834841030
Short name T1701
Test name
Test status
Simulation time 188094727 ps
CPU time 0.8 seconds
Started Jun 24 05:25:49 PM PDT 24
Finished Jun 24 05:25:51 PM PDT 24
Peak memory 206104 kb
Host smart-b3ce43d3-876f-467d-b5dd-421f97734eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18348
41030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.1834841030
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.2178955964
Short name T1461
Test name
Test status
Simulation time 147007030 ps
CPU time 0.75 seconds
Started Jun 24 05:25:44 PM PDT 24
Finished Jun 24 05:25:47 PM PDT 24
Peak memory 206064 kb
Host smart-87d576a2-1f59-45e6-8b1e-c5a7d2e19db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21789
55964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.2178955964
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.86220129
Short name T84
Test name
Test status
Simulation time 180108628 ps
CPU time 0.84 seconds
Started Jun 24 05:25:49 PM PDT 24
Finished Jun 24 05:25:51 PM PDT 24
Peak memory 206148 kb
Host smart-374c5891-20fe-466f-9133-0e8bf4db2ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86220
129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.86220129
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3581409513
Short name T2460
Test name
Test status
Simulation time 154516219 ps
CPU time 0.81 seconds
Started Jun 24 05:25:45 PM PDT 24
Finished Jun 24 05:25:47 PM PDT 24
Peak memory 206072 kb
Host smart-890f5390-5d10-4f8a-b534-fb88a0099307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35814
09513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3581409513
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3028155101
Short name T2244
Test name
Test status
Simulation time 221093868 ps
CPU time 0.94 seconds
Started Jun 24 05:25:43 PM PDT 24
Finished Jun 24 05:25:45 PM PDT 24
Peak memory 206116 kb
Host smart-3cf97cba-3f20-4e46-8f46-c3cb7680c26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30281
55101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3028155101
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.1052251173
Short name T1638
Test name
Test status
Simulation time 12823498350 ps
CPU time 116.51 seconds
Started Jun 24 05:25:46 PM PDT 24
Finished Jun 24 05:27:45 PM PDT 24
Peak memory 206208 kb
Host smart-11d91dea-c6e5-4984-9464-fd355e020885
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1052251173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1052251173
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.3793777433
Short name T2136
Test name
Test status
Simulation time 236147718 ps
CPU time 0.88 seconds
Started Jun 24 05:25:48 PM PDT 24
Finished Jun 24 05:25:51 PM PDT 24
Peak memory 206360 kb
Host smart-74366458-9c78-4981-9d69-455985641374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37937
77433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.3793777433
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.592318873
Short name T2456
Test name
Test status
Simulation time 185104239 ps
CPU time 0.82 seconds
Started Jun 24 05:25:43 PM PDT 24
Finished Jun 24 05:25:45 PM PDT 24
Peak memory 206172 kb
Host smart-ca2768f7-3671-49bc-af9e-3699097c3974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59231
8873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.592318873
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3953448343
Short name T1863
Test name
Test status
Simulation time 8152268770 ps
CPU time 228.55 seconds
Started Jun 24 05:25:47 PM PDT 24
Finished Jun 24 05:29:38 PM PDT 24
Peak memory 206312 kb
Host smart-2cf4e1ba-5ee7-4642-9fb1-58ae4f2f6b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39534
48343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3953448343
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.3546348811
Short name T12
Test name
Test status
Simulation time 4371661180 ps
CPU time 5.29 seconds
Started Jun 24 05:25:48 PM PDT 24
Finished Jun 24 05:25:55 PM PDT 24
Peak memory 206240 kb
Host smart-0a64b779-7f79-4b58-8cfb-73e8c4225052
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3546348811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.3546348811
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.974149407
Short name T2283
Test name
Test status
Simulation time 13410721702 ps
CPU time 12.29 seconds
Started Jun 24 05:25:47 PM PDT 24
Finished Jun 24 05:26:01 PM PDT 24
Peak memory 206388 kb
Host smart-72667c0b-3f28-40ef-b52a-185f687ddc59
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=974149407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.974149407
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.2534244410
Short name T1000
Test name
Test status
Simulation time 23390955058 ps
CPU time 22.58 seconds
Started Jun 24 05:25:45 PM PDT 24
Finished Jun 24 05:26:09 PM PDT 24
Peak memory 206196 kb
Host smart-749d5ae5-51b3-45f6-a3b6-4d504a2f1bce
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2534244410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.2534244410
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3201155202
Short name T1698
Test name
Test status
Simulation time 187572127 ps
CPU time 0.85 seconds
Started Jun 24 05:25:45 PM PDT 24
Finished Jun 24 05:25:47 PM PDT 24
Peak memory 206428 kb
Host smart-6d1909e3-0b4c-4191-bba5-26ed207c1cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32011
55202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3201155202
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.590941174
Short name T664
Test name
Test status
Simulation time 149064942 ps
CPU time 0.78 seconds
Started Jun 24 05:25:44 PM PDT 24
Finished Jun 24 05:25:46 PM PDT 24
Peak memory 206164 kb
Host smart-fb1163b0-0568-45e2-89db-ae65c30bcfb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59094
1174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.590941174
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.1248981392
Short name T1096
Test name
Test status
Simulation time 400306019 ps
CPU time 1.33 seconds
Started Jun 24 05:25:47 PM PDT 24
Finished Jun 24 05:25:50 PM PDT 24
Peak memory 206168 kb
Host smart-8b3f57ec-a97a-4e1c-94c0-e280469f5047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12489
81392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.1248981392
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1935404994
Short name T173
Test name
Test status
Simulation time 841246276 ps
CPU time 2 seconds
Started Jun 24 05:25:45 PM PDT 24
Finished Jun 24 05:25:49 PM PDT 24
Peak memory 206224 kb
Host smart-3a8db81c-ae9a-41f1-b24a-d400409ab2f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19354
04994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1935404994
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.3298946443
Short name T1204
Test name
Test status
Simulation time 14471182837 ps
CPU time 27.07 seconds
Started Jun 24 05:25:47 PM PDT 24
Finished Jun 24 05:26:17 PM PDT 24
Peak memory 206344 kb
Host smart-6b21ab05-6b69-4497-8f8c-471952f51cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32989
46443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.3298946443
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.3980112524
Short name T2408
Test name
Test status
Simulation time 357471257 ps
CPU time 1.15 seconds
Started Jun 24 05:25:43 PM PDT 24
Finished Jun 24 05:25:46 PM PDT 24
Peak memory 206176 kb
Host smart-aaaa3a46-54e9-4d01-8af7-720008e00c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39801
12524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.3980112524
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.10347529
Short name T1414
Test name
Test status
Simulation time 156485037 ps
CPU time 0.86 seconds
Started Jun 24 05:25:44 PM PDT 24
Finished Jun 24 05:25:46 PM PDT 24
Peak memory 206172 kb
Host smart-6922a036-8416-49b6-a486-618aeccb442e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10347
529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.10347529
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.3904792935
Short name T240
Test name
Test status
Simulation time 55156903 ps
CPU time 0.7 seconds
Started Jun 24 05:25:45 PM PDT 24
Finished Jun 24 05:25:48 PM PDT 24
Peak memory 206068 kb
Host smart-4089eac8-ee2f-46ab-9011-90b7e3e507c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39047
92935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3904792935
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.3653171668
Short name T1056
Test name
Test status
Simulation time 831875064 ps
CPU time 2.05 seconds
Started Jun 24 05:25:45 PM PDT 24
Finished Jun 24 05:25:49 PM PDT 24
Peak memory 206208 kb
Host smart-b395d259-85fe-4c4b-842e-2bb3449e3995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36531
71668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.3653171668
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1590443166
Short name T1674
Test name
Test status
Simulation time 242405221 ps
CPU time 2.35 seconds
Started Jun 24 05:25:45 PM PDT 24
Finished Jun 24 05:25:49 PM PDT 24
Peak memory 206348 kb
Host smart-88ad403b-000e-4b76-b986-e3ec06675133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15904
43166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1590443166
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3941841589
Short name T1840
Test name
Test status
Simulation time 221433310 ps
CPU time 0.85 seconds
Started Jun 24 05:25:53 PM PDT 24
Finished Jun 24 05:25:56 PM PDT 24
Peak memory 206096 kb
Host smart-ee182adb-5b61-40a7-b085-e4525e67262a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39418
41589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3941841589
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3496568106
Short name T2305
Test name
Test status
Simulation time 148331858 ps
CPU time 0.75 seconds
Started Jun 24 05:25:55 PM PDT 24
Finished Jun 24 05:25:58 PM PDT 24
Peak memory 206084 kb
Host smart-9abfb5aa-fadd-4266-bb39-d3e107bc3fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34965
68106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3496568106
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.586075035
Short name T224
Test name
Test status
Simulation time 181773862 ps
CPU time 0.83 seconds
Started Jun 24 05:25:55 PM PDT 24
Finished Jun 24 05:25:59 PM PDT 24
Peak memory 206084 kb
Host smart-1fd0cb63-83c8-4d22-aca8-a481ad6bb123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58607
5035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.586075035
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.639461560
Short name T963
Test name
Test status
Simulation time 11619320159 ps
CPU time 112.03 seconds
Started Jun 24 05:25:52 PM PDT 24
Finished Jun 24 05:27:46 PM PDT 24
Peak memory 206564 kb
Host smart-b185bb9c-333c-4f79-b330-e1334d568529
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=639461560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.639461560
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.165614726
Short name T1081
Test name
Test status
Simulation time 194304279 ps
CPU time 0.86 seconds
Started Jun 24 05:25:56 PM PDT 24
Finished Jun 24 05:26:00 PM PDT 24
Peak memory 206136 kb
Host smart-8e3792fc-f8a2-4255-ae1b-85afce62eb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16561
4726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.165614726
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.3766252859
Short name T937
Test name
Test status
Simulation time 23329591103 ps
CPU time 25.57 seconds
Started Jun 24 05:25:56 PM PDT 24
Finished Jun 24 05:26:24 PM PDT 24
Peak memory 206204 kb
Host smart-84faf3d6-6157-439f-a80e-05eaa9df9379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37662
52859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.3766252859
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.2644647092
Short name T1067
Test name
Test status
Simulation time 3330910172 ps
CPU time 3.72 seconds
Started Jun 24 05:25:54 PM PDT 24
Finished Jun 24 05:26:00 PM PDT 24
Peak memory 206240 kb
Host smart-a0102b96-2c09-4066-a5ad-76f52f48fb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26446
47092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2644647092
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2784186222
Short name T2096
Test name
Test status
Simulation time 9126253426 ps
CPU time 86.01 seconds
Started Jun 24 05:25:50 PM PDT 24
Finished Jun 24 05:27:17 PM PDT 24
Peak memory 206324 kb
Host smart-e47847fa-385e-45a1-94fa-371d6ca70b4d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2784186222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2784186222
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.4005150864
Short name T615
Test name
Test status
Simulation time 241783803 ps
CPU time 0.85 seconds
Started Jun 24 05:25:53 PM PDT 24
Finished Jun 24 05:25:55 PM PDT 24
Peak memory 206188 kb
Host smart-cfa4bf50-620b-49b9-9e37-bd3ec8dcf567
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4005150864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.4005150864
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2210382338
Short name T374
Test name
Test status
Simulation time 221954122 ps
CPU time 0.91 seconds
Started Jun 24 05:25:53 PM PDT 24
Finished Jun 24 05:25:56 PM PDT 24
Peak memory 206164 kb
Host smart-c1e8c2d6-33e3-405c-84ed-ca6656faff36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22103
82338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2210382338
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.2800053196
Short name T2484
Test name
Test status
Simulation time 7184515271 ps
CPU time 204.56 seconds
Started Jun 24 05:25:52 PM PDT 24
Finished Jun 24 05:29:19 PM PDT 24
Peak memory 206372 kb
Host smart-c47a48b5-5c4a-4024-8d4f-3972381d7d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28000
53196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.2800053196
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.1428115834
Short name T324
Test name
Test status
Simulation time 14514378394 ps
CPU time 139.5 seconds
Started Jun 24 05:25:53 PM PDT 24
Finished Jun 24 05:28:14 PM PDT 24
Peak memory 206356 kb
Host smart-fc7b19c3-f072-4b16-bfce-deff27d41cf8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1428115834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.1428115834
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.3201950547
Short name T509
Test name
Test status
Simulation time 180244642 ps
CPU time 0.77 seconds
Started Jun 24 05:25:52 PM PDT 24
Finished Jun 24 05:25:54 PM PDT 24
Peak memory 206180 kb
Host smart-57d5e469-5543-48d4-9310-d551d1af92e1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3201950547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.3201950547
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3962582634
Short name T2124
Test name
Test status
Simulation time 150864619 ps
CPU time 0.81 seconds
Started Jun 24 05:25:51 PM PDT 24
Finished Jun 24 05:25:53 PM PDT 24
Peak memory 206064 kb
Host smart-2b942ad3-12c3-4070-abfa-4318e2918142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39625
82634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3962582634
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.207486532
Short name T133
Test name
Test status
Simulation time 188981724 ps
CPU time 0.84 seconds
Started Jun 24 05:25:52 PM PDT 24
Finished Jun 24 05:25:54 PM PDT 24
Peak memory 206100 kb
Host smart-4b562622-7449-419f-930e-9a30c382f020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20748
6532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.207486532
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3774282616
Short name T83
Test name
Test status
Simulation time 209607315 ps
CPU time 0.84 seconds
Started Jun 24 05:25:55 PM PDT 24
Finished Jun 24 05:25:59 PM PDT 24
Peak memory 206144 kb
Host smart-dc6dd13a-a53b-4fcb-aa9c-fb2fbbc3c9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37742
82616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3774282616
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.978353094
Short name T2448
Test name
Test status
Simulation time 157361561 ps
CPU time 0.77 seconds
Started Jun 24 05:25:54 PM PDT 24
Finished Jun 24 05:25:58 PM PDT 24
Peak memory 206072 kb
Host smart-e9f9e73e-1a81-4373-9de0-3feb0a247bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97835
3094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.978353094
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.4024338802
Short name T1833
Test name
Test status
Simulation time 176515297 ps
CPU time 0.83 seconds
Started Jun 24 05:25:52 PM PDT 24
Finished Jun 24 05:25:54 PM PDT 24
Peak memory 206116 kb
Host smart-249dc892-bd8f-456b-ab6e-52e05a275502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40243
38802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.4024338802
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.989328114
Short name T978
Test name
Test status
Simulation time 147948266 ps
CPU time 0.78 seconds
Started Jun 24 05:25:55 PM PDT 24
Finished Jun 24 05:25:59 PM PDT 24
Peak memory 206148 kb
Host smart-ecd15572-9491-4f1e-b635-fead0f5197df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98932
8114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.989328114
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.488923657
Short name T1870
Test name
Test status
Simulation time 191981214 ps
CPU time 0.89 seconds
Started Jun 24 05:25:55 PM PDT 24
Finished Jun 24 05:25:59 PM PDT 24
Peak memory 206156 kb
Host smart-7e14bd61-2ef5-4d00-8064-b4b619912bea
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=488923657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.488923657
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2442547779
Short name T2025
Test name
Test status
Simulation time 145441296 ps
CPU time 0.78 seconds
Started Jun 24 05:25:51 PM PDT 24
Finished Jun 24 05:25:52 PM PDT 24
Peak memory 206176 kb
Host smart-78523dff-4c1c-4798-b02c-7c71007c726f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24425
47779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2442547779
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2614863071
Short name T1296
Test name
Test status
Simulation time 42124081 ps
CPU time 0.65 seconds
Started Jun 24 05:25:49 PM PDT 24
Finished Jun 24 05:25:51 PM PDT 24
Peak memory 206184 kb
Host smart-bdf3223c-4c7a-4d2a-990f-b4a53f397285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26148
63071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2614863071
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1360258891
Short name T93
Test name
Test status
Simulation time 15431952001 ps
CPU time 33.22 seconds
Started Jun 24 05:25:52 PM PDT 24
Finished Jun 24 05:26:26 PM PDT 24
Peak memory 206368 kb
Host smart-839eb8c5-2164-456f-8c8c-3435a0a215cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13602
58891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1360258891
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.4113745569
Short name T347
Test name
Test status
Simulation time 203454127 ps
CPU time 0.85 seconds
Started Jun 24 05:25:55 PM PDT 24
Finished Jun 24 05:25:59 PM PDT 24
Peak memory 206148 kb
Host smart-dde3d469-d1ea-46ed-99ed-89be62eda9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41137
45569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.4113745569
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1592498749
Short name T675
Test name
Test status
Simulation time 228752446 ps
CPU time 0.85 seconds
Started Jun 24 05:25:53 PM PDT 24
Finished Jun 24 05:25:56 PM PDT 24
Peak memory 206112 kb
Host smart-c9a33240-ad3a-4227-a46c-ef0a6a2fac17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15924
98749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1592498749
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.1123510837
Short name T2422
Test name
Test status
Simulation time 242023456 ps
CPU time 0.94 seconds
Started Jun 24 05:25:53 PM PDT 24
Finished Jun 24 05:25:56 PM PDT 24
Peak memory 206200 kb
Host smart-f6faf3dd-91f2-4328-ab41-6228a92056cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11235
10837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.1123510837
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.496765088
Short name T2492
Test name
Test status
Simulation time 164543194 ps
CPU time 0.82 seconds
Started Jun 24 05:25:51 PM PDT 24
Finished Jun 24 05:25:53 PM PDT 24
Peak memory 206176 kb
Host smart-add89cf2-575e-4df0-b64d-c01cf6d0eae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49676
5088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.496765088
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.198725660
Short name T1820
Test name
Test status
Simulation time 186995928 ps
CPU time 0.84 seconds
Started Jun 24 05:25:54 PM PDT 24
Finished Jun 24 05:25:58 PM PDT 24
Peak memory 206180 kb
Host smart-5d01e68d-6618-494a-a694-1cc11641d6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19872
5660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.198725660
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.200326708
Short name T1853
Test name
Test status
Simulation time 155614282 ps
CPU time 0.81 seconds
Started Jun 24 05:25:52 PM PDT 24
Finished Jun 24 05:25:55 PM PDT 24
Peak memory 206184 kb
Host smart-8540d0e8-b9c0-441f-b5c4-bd0cf61f4135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20032
6708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.200326708
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1889491528
Short name T1281
Test name
Test status
Simulation time 149168468 ps
CPU time 0.77 seconds
Started Jun 24 05:25:54 PM PDT 24
Finished Jun 24 05:25:58 PM PDT 24
Peak memory 206052 kb
Host smart-5c086c15-a24c-4f6c-b30b-914e70bda14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18894
91528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1889491528
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1984626362
Short name T1273
Test name
Test status
Simulation time 248585592 ps
CPU time 0.93 seconds
Started Jun 24 05:25:53 PM PDT 24
Finished Jun 24 05:25:56 PM PDT 24
Peak memory 206184 kb
Host smart-e4b71bb9-e036-48ae-8623-05b4ecce0201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19846
26362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1984626362
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.1355019156
Short name T966
Test name
Test status
Simulation time 10844316508 ps
CPU time 305.69 seconds
Started Jun 24 05:25:52 PM PDT 24
Finished Jun 24 05:31:00 PM PDT 24
Peak memory 206392 kb
Host smart-9f71dc33-3776-4fd7-88b3-06d73a503b6b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1355019156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.1355019156
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2387894021
Short name T1808
Test name
Test status
Simulation time 198421445 ps
CPU time 0.83 seconds
Started Jun 24 05:25:52 PM PDT 24
Finished Jun 24 05:25:54 PM PDT 24
Peak memory 206436 kb
Host smart-ead40c0d-9c7b-4910-94ee-1c03b7809a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23878
94021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2387894021
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1960121473
Short name T1837
Test name
Test status
Simulation time 232135534 ps
CPU time 0.85 seconds
Started Jun 24 05:25:51 PM PDT 24
Finished Jun 24 05:25:54 PM PDT 24
Peak memory 206168 kb
Host smart-a69793ec-e280-4410-ac36-4e6d49621e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19601
21473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1960121473
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.716466889
Short name T1417
Test name
Test status
Simulation time 4279657950 ps
CPU time 41.83 seconds
Started Jun 24 05:25:51 PM PDT 24
Finished Jun 24 05:26:34 PM PDT 24
Peak memory 206352 kb
Host smart-8271d1ad-d01b-40b2-a151-fed3f2cb3a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71646
6889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.716466889
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.307607840
Short name T2100
Test name
Test status
Simulation time 3605134622 ps
CPU time 4.12 seconds
Started Jun 24 05:25:54 PM PDT 24
Finished Jun 24 05:26:00 PM PDT 24
Peak memory 206244 kb
Host smart-a4f6c0d2-2569-4335-a342-b3b88e61ed75
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=307607840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.307607840
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2994069064
Short name T620
Test name
Test status
Simulation time 13342806699 ps
CPU time 15.93 seconds
Started Jun 24 05:25:51 PM PDT 24
Finished Jun 24 05:26:08 PM PDT 24
Peak memory 206244 kb
Host smart-e7b31663-a4c7-4e0c-83b6-a667cf68ea29
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2994069064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2994069064
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.2137375127
Short name T1432
Test name
Test status
Simulation time 23362867206 ps
CPU time 22.29 seconds
Started Jun 24 05:25:52 PM PDT 24
Finished Jun 24 05:26:17 PM PDT 24
Peak memory 206224 kb
Host smart-fe16441d-06c6-4ea9-82a0-48369c300cd8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2137375127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.2137375127
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.970900649
Short name T2518
Test name
Test status
Simulation time 166442343 ps
CPU time 0.83 seconds
Started Jun 24 05:25:54 PM PDT 24
Finished Jun 24 05:25:58 PM PDT 24
Peak memory 206152 kb
Host smart-8267dd26-3377-4d73-ac48-ce1b7bf813c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97090
0649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.970900649
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.57834802
Short name T1664
Test name
Test status
Simulation time 140462390 ps
CPU time 0.72 seconds
Started Jun 24 05:25:53 PM PDT 24
Finished Jun 24 05:25:56 PM PDT 24
Peak memory 206196 kb
Host smart-e978c044-1259-49b7-a87d-8b0c08144ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57834
802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.57834802
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.334711021
Short name T112
Test name
Test status
Simulation time 524494419 ps
CPU time 1.56 seconds
Started Jun 24 05:25:52 PM PDT 24
Finished Jun 24 05:25:56 PM PDT 24
Peak memory 206240 kb
Host smart-74cd83f0-f1b9-470d-8014-71d69c059867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33471
1021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.334711021
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.3008438149
Short name T1953
Test name
Test status
Simulation time 1219343560 ps
CPU time 2.62 seconds
Started Jun 24 05:25:56 PM PDT 24
Finished Jun 24 05:26:01 PM PDT 24
Peak memory 206240 kb
Host smart-07608f0b-f8b0-45ed-8873-5434ec9684fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30084
38149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.3008438149
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.4205739946
Short name T1343
Test name
Test status
Simulation time 8050474287 ps
CPU time 14.91 seconds
Started Jun 24 05:25:53 PM PDT 24
Finished Jun 24 05:26:10 PM PDT 24
Peak memory 206408 kb
Host smart-c32f50a8-3bc9-489e-b84c-5d84e313baa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42057
39946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.4205739946
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.1851367759
Short name T1893
Test name
Test status
Simulation time 358384906 ps
CPU time 1.13 seconds
Started Jun 24 05:25:55 PM PDT 24
Finished Jun 24 05:25:59 PM PDT 24
Peak memory 206180 kb
Host smart-cf5d48ce-4428-499b-87ca-99266b40daaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18513
67759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.1851367759
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.3472656208
Short name T1801
Test name
Test status
Simulation time 183166240 ps
CPU time 0.81 seconds
Started Jun 24 05:25:52 PM PDT 24
Finished Jun 24 05:25:55 PM PDT 24
Peak memory 206144 kb
Host smart-f5ab3375-5a85-4bf8-95fa-8fd6b7c93a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34726
56208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.3472656208
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.41385551
Short name T1445
Test name
Test status
Simulation time 46832508 ps
CPU time 0.67 seconds
Started Jun 24 05:25:54 PM PDT 24
Finished Jun 24 05:25:57 PM PDT 24
Peak memory 206084 kb
Host smart-af3273a9-975e-45ae-a31a-cfbe3e47f717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41385
551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.41385551
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.1384895850
Short name T1730
Test name
Test status
Simulation time 910925458 ps
CPU time 2.28 seconds
Started Jun 24 05:25:55 PM PDT 24
Finished Jun 24 05:26:00 PM PDT 24
Peak memory 206292 kb
Host smart-9148881a-6c5e-4682-9335-aab0b66a5b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13848
95850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.1384895850
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3386583445
Short name T1181
Test name
Test status
Simulation time 342601020 ps
CPU time 2.03 seconds
Started Jun 24 05:25:54 PM PDT 24
Finished Jun 24 05:25:59 PM PDT 24
Peak memory 206272 kb
Host smart-8907c9d6-4fc4-4967-b569-2e6ce829b035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33865
83445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3386583445
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3353144303
Short name T2224
Test name
Test status
Simulation time 268582526 ps
CPU time 0.95 seconds
Started Jun 24 05:26:00 PM PDT 24
Finished Jun 24 05:26:03 PM PDT 24
Peak memory 206172 kb
Host smart-5c9c18ba-9a40-4bf0-ba19-f32a1fbb5f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33531
44303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3353144303
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.413498793
Short name T663
Test name
Test status
Simulation time 155318759 ps
CPU time 0.86 seconds
Started Jun 24 05:26:01 PM PDT 24
Finished Jun 24 05:26:03 PM PDT 24
Peak memory 206196 kb
Host smart-77792c82-ab6e-42a0-9b65-3fc553caf5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41349
8793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.413498793
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.416129580
Short name T767
Test name
Test status
Simulation time 282634443 ps
CPU time 0.92 seconds
Started Jun 24 05:25:54 PM PDT 24
Finished Jun 24 05:25:58 PM PDT 24
Peak memory 206188 kb
Host smart-eb0e6dd0-e556-4ca9-993c-5054314d8a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41612
9580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.416129580
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1773539268
Short name T2212
Test name
Test status
Simulation time 217727426 ps
CPU time 0.91 seconds
Started Jun 24 05:26:01 PM PDT 24
Finished Jun 24 05:26:04 PM PDT 24
Peak memory 206176 kb
Host smart-878e0343-219e-4937-8482-444bfb307d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17735
39268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1773539268
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.2368537039
Short name T2306
Test name
Test status
Simulation time 23359866719 ps
CPU time 23.22 seconds
Started Jun 24 05:26:01 PM PDT 24
Finished Jun 24 05:26:27 PM PDT 24
Peak memory 206256 kb
Host smart-974ab87a-c3af-4618-992b-49ed03ca74fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23685
37039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.2368537039
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.59534539
Short name T1959
Test name
Test status
Simulation time 3314317407 ps
CPU time 3.61 seconds
Started Jun 24 05:26:00 PM PDT 24
Finished Jun 24 05:26:05 PM PDT 24
Peak memory 206244 kb
Host smart-f8c0c13f-8329-4add-8d39-80688eaddacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59534
539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.59534539
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.3412341292
Short name T2354
Test name
Test status
Simulation time 9985324838 ps
CPU time 95.06 seconds
Started Jun 24 05:26:01 PM PDT 24
Finished Jun 24 05:27:38 PM PDT 24
Peak memory 206340 kb
Host smart-79569f93-5386-4764-a18a-07729efacc71
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3412341292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3412341292
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.1545227724
Short name T1580
Test name
Test status
Simulation time 307647210 ps
CPU time 1.1 seconds
Started Jun 24 05:26:01 PM PDT 24
Finished Jun 24 05:26:05 PM PDT 24
Peak memory 206196 kb
Host smart-a77f9595-5263-4ccd-ad21-d2be63cf62e5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1545227724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.1545227724
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3585035880
Short name T2453
Test name
Test status
Simulation time 202016152 ps
CPU time 0.88 seconds
Started Jun 24 05:26:00 PM PDT 24
Finished Jun 24 05:26:03 PM PDT 24
Peak memory 206104 kb
Host smart-7dde70b1-e45b-477d-828a-b3f26748c122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35850
35880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3585035880
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.4125092293
Short name T1786
Test name
Test status
Simulation time 4254548796 ps
CPU time 117.99 seconds
Started Jun 24 05:26:02 PM PDT 24
Finished Jun 24 05:28:02 PM PDT 24
Peak memory 206304 kb
Host smart-51faeea2-2177-4726-b7d8-02753c36eb98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41250
92293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.4125092293
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2141796319
Short name T981
Test name
Test status
Simulation time 3958783423 ps
CPU time 111.17 seconds
Started Jun 24 05:26:01 PM PDT 24
Finished Jun 24 05:27:55 PM PDT 24
Peak memory 206292 kb
Host smart-bc95d1df-fed8-41ca-86ff-a5f755f22d15
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2141796319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2141796319
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.1960086116
Short name T621
Test name
Test status
Simulation time 184616550 ps
CPU time 0.82 seconds
Started Jun 24 05:26:00 PM PDT 24
Finished Jun 24 05:26:02 PM PDT 24
Peak memory 206192 kb
Host smart-8f6b2b9c-a403-43c1-9c04-5d5e3c4a5ce0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1960086116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.1960086116
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.411760138
Short name T1321
Test name
Test status
Simulation time 176893751 ps
CPU time 0.81 seconds
Started Jun 24 05:25:59 PM PDT 24
Finished Jun 24 05:26:01 PM PDT 24
Peak memory 206120 kb
Host smart-b9bbb139-ef0c-4a4e-82c0-2f8992e652ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41176
0138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.411760138
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.534568777
Short name T145
Test name
Test status
Simulation time 283042600 ps
CPU time 0.93 seconds
Started Jun 24 05:26:02 PM PDT 24
Finished Jun 24 05:26:05 PM PDT 24
Peak memory 206160 kb
Host smart-4138f9d4-04b5-4a6a-b32d-1d8c25269026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53456
8777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.534568777
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.3185794508
Short name T2070
Test name
Test status
Simulation time 188436422 ps
CPU time 0.92 seconds
Started Jun 24 05:26:02 PM PDT 24
Finished Jun 24 05:26:05 PM PDT 24
Peak memory 206116 kb
Host smart-2b0635dc-582f-4d24-a0ae-547d74efe529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31857
94508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3185794508
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3272279136
Short name T1569
Test name
Test status
Simulation time 188861934 ps
CPU time 0.8 seconds
Started Jun 24 05:26:02 PM PDT 24
Finished Jun 24 05:26:06 PM PDT 24
Peak memory 206176 kb
Host smart-c8d30775-9f06-49bb-b81e-d0f9f257e9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32722
79136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3272279136
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.4184196378
Short name T651
Test name
Test status
Simulation time 176280078 ps
CPU time 0.81 seconds
Started Jun 24 05:26:02 PM PDT 24
Finished Jun 24 05:26:06 PM PDT 24
Peak memory 206188 kb
Host smart-82f24e2b-6a2e-47ba-9579-c8e8684bd532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41841
96378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.4184196378
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.931518750
Short name T2006
Test name
Test status
Simulation time 208488186 ps
CPU time 0.84 seconds
Started Jun 24 05:26:00 PM PDT 24
Finished Jun 24 05:26:02 PM PDT 24
Peak memory 206176 kb
Host smart-8b01cdf3-a913-4dff-b674-f02b0a6ea7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93151
8750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.931518750
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.489951750
Short name T1402
Test name
Test status
Simulation time 271126803 ps
CPU time 1.01 seconds
Started Jun 24 05:26:01 PM PDT 24
Finished Jun 24 05:26:03 PM PDT 24
Peak memory 206188 kb
Host smart-bb5f4638-831b-42b9-95da-acd146ac88d4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=489951750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.489951750
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1493577800
Short name T22
Test name
Test status
Simulation time 158444576 ps
CPU time 0.8 seconds
Started Jun 24 05:26:01 PM PDT 24
Finished Jun 24 05:26:05 PM PDT 24
Peak memory 206136 kb
Host smart-3da7898d-2604-4033-b05b-fb94f2ff987e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14935
77800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1493577800
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1538742821
Short name T223
Test name
Test status
Simulation time 56118874 ps
CPU time 0.65 seconds
Started Jun 24 05:26:00 PM PDT 24
Finished Jun 24 05:26:03 PM PDT 24
Peak memory 206108 kb
Host smart-07ce5168-2a1e-4152-aeda-1c104d42f724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15387
42821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1538742821
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.2629380909
Short name T567
Test name
Test status
Simulation time 11738724043 ps
CPU time 25.82 seconds
Started Jun 24 05:26:01 PM PDT 24
Finished Jun 24 05:26:29 PM PDT 24
Peak memory 206364 kb
Host smart-4d5b00cd-cbe7-4076-a16f-a3e0f56715a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26293
80909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.2629380909
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.593439827
Short name T592
Test name
Test status
Simulation time 165321573 ps
CPU time 0.85 seconds
Started Jun 24 05:25:59 PM PDT 24
Finished Jun 24 05:26:01 PM PDT 24
Peak memory 206180 kb
Host smart-520d5479-27a7-42d5-9122-47ee77cdd969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59343
9827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.593439827
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.191109026
Short name T2494
Test name
Test status
Simulation time 231418706 ps
CPU time 0.88 seconds
Started Jun 24 05:26:00 PM PDT 24
Finished Jun 24 05:26:02 PM PDT 24
Peak memory 206408 kb
Host smart-5289d715-2e30-43ef-92d5-827ce8685a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19110
9026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.191109026
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.172433346
Short name T2060
Test name
Test status
Simulation time 283248706 ps
CPU time 0.93 seconds
Started Jun 24 05:26:02 PM PDT 24
Finished Jun 24 05:26:05 PM PDT 24
Peak memory 206188 kb
Host smart-45e69220-0914-4291-bd75-a13f8e5a5fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17243
3346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.172433346
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.3084809597
Short name T1751
Test name
Test status
Simulation time 168074804 ps
CPU time 0.84 seconds
Started Jun 24 05:26:03 PM PDT 24
Finished Jun 24 05:26:06 PM PDT 24
Peak memory 206096 kb
Host smart-0e0a0a2c-f0b4-4383-8972-50a06ed3ff99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30848
09597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3084809597
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.1956461049
Short name T1981
Test name
Test status
Simulation time 137542252 ps
CPU time 0.82 seconds
Started Jun 24 05:26:01 PM PDT 24
Finished Jun 24 05:26:04 PM PDT 24
Peak memory 206172 kb
Host smart-05450f34-3d0e-487b-ac45-202417c4c297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19564
61049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.1956461049
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.3634916530
Short name T988
Test name
Test status
Simulation time 152653424 ps
CPU time 0.82 seconds
Started Jun 24 05:26:03 PM PDT 24
Finished Jun 24 05:26:06 PM PDT 24
Peak memory 206148 kb
Host smart-901b5b12-c746-4b6c-a94d-b1769a341945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36349
16530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3634916530
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2748974007
Short name T2361
Test name
Test status
Simulation time 160954433 ps
CPU time 0.79 seconds
Started Jun 24 05:26:02 PM PDT 24
Finished Jun 24 05:26:06 PM PDT 24
Peak memory 206172 kb
Host smart-95e3b9f3-c6cf-4d83-abf2-17d07a94a9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27489
74007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2748974007
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2808192616
Short name T1018
Test name
Test status
Simulation time 192877410 ps
CPU time 0.88 seconds
Started Jun 24 05:26:03 PM PDT 24
Finished Jun 24 05:26:06 PM PDT 24
Peak memory 206148 kb
Host smart-080667ed-ce11-4fc9-812e-3332ad24e032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28081
92616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2808192616
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.1798695749
Short name T1292
Test name
Test status
Simulation time 5230597849 ps
CPU time 37.43 seconds
Started Jun 24 05:25:59 PM PDT 24
Finished Jun 24 05:26:38 PM PDT 24
Peak memory 206344 kb
Host smart-f57827e7-5c18-45e8-86aa-6b51468b755c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1798695749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.1798695749
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3402679128
Short name T1394
Test name
Test status
Simulation time 190931181 ps
CPU time 0.81 seconds
Started Jun 24 05:26:02 PM PDT 24
Finished Jun 24 05:26:05 PM PDT 24
Peak memory 206164 kb
Host smart-b8c3bee3-2c01-4b78-9df8-a83761e095de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34026
79128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3402679128
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.99197058
Short name T1854
Test name
Test status
Simulation time 193592061 ps
CPU time 0.88 seconds
Started Jun 24 05:26:01 PM PDT 24
Finished Jun 24 05:26:05 PM PDT 24
Peak memory 206192 kb
Host smart-c1b03025-aaf6-4ece-afcc-da49580f5dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99197
058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.99197058
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.535902510
Short name T459
Test name
Test status
Simulation time 7974332797 ps
CPU time 80.1 seconds
Started Jun 24 05:26:01 PM PDT 24
Finished Jun 24 05:27:23 PM PDT 24
Peak memory 206348 kb
Host smart-af612274-0b91-4ec8-a5d0-c5f738421ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53590
2510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.535902510
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.3295415414
Short name T662
Test name
Test status
Simulation time 4161158257 ps
CPU time 4.53 seconds
Started Jun 24 05:26:03 PM PDT 24
Finished Jun 24 05:26:10 PM PDT 24
Peak memory 206136 kb
Host smart-00c914ce-2173-48bf-b6b5-500de6f1cfb4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3295415414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.3295415414
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.691162155
Short name T2166
Test name
Test status
Simulation time 13425694504 ps
CPU time 14.95 seconds
Started Jun 24 05:26:03 PM PDT 24
Finished Jun 24 05:26:20 PM PDT 24
Peak memory 206296 kb
Host smart-205a87ff-96d0-4908-9557-75fc5ea2af59
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=691162155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.691162155
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.2641393233
Short name T2227
Test name
Test status
Simulation time 23486756196 ps
CPU time 22.8 seconds
Started Jun 24 05:25:59 PM PDT 24
Finished Jun 24 05:26:24 PM PDT 24
Peak memory 206380 kb
Host smart-1a47eb9e-399a-4987-8ca1-5c3cfaacd9c9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2641393233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.2641393233
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1818656513
Short name T332
Test name
Test status
Simulation time 190923850 ps
CPU time 0.89 seconds
Started Jun 24 05:26:01 PM PDT 24
Finished Jun 24 05:26:05 PM PDT 24
Peak memory 206140 kb
Host smart-1af4c3be-dad6-4aeb-a2e9-f686a471c5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18186
56513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1818656513
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.2644466855
Short name T884
Test name
Test status
Simulation time 146288457 ps
CPU time 0.79 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:15 PM PDT 24
Peak memory 206100 kb
Host smart-742aacc8-38ac-4fb0-937e-927ed244ed7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26444
66855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.2644466855
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.408665724
Short name T2298
Test name
Test status
Simulation time 270666419 ps
CPU time 1.05 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:14 PM PDT 24
Peak memory 206128 kb
Host smart-6024d9f9-6b5f-40ac-b66b-aa2a95fe4219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40866
5724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.408665724
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1682134861
Short name T1263
Test name
Test status
Simulation time 495258361 ps
CPU time 1.52 seconds
Started Jun 24 05:26:12 PM PDT 24
Finished Jun 24 05:26:16 PM PDT 24
Peak memory 206164 kb
Host smart-a3648183-5649-42f4-8503-a8a1a2c642b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16821
34861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1682134861
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.3702085747
Short name T97
Test name
Test status
Simulation time 12623156356 ps
CPU time 28.37 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:42 PM PDT 24
Peak memory 206560 kb
Host smart-88ca9dbd-5152-44ac-8cc3-bcc4843bfbf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37020
85747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.3702085747
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.2718319175
Short name T1439
Test name
Test status
Simulation time 404510736 ps
CPU time 1.42 seconds
Started Jun 24 05:26:18 PM PDT 24
Finished Jun 24 05:26:21 PM PDT 24
Peak memory 206176 kb
Host smart-bdebd8bf-eb54-4887-a5e6-7ce1ea714fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27183
19175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.2718319175
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.285985761
Short name T1477
Test name
Test status
Simulation time 133413895 ps
CPU time 0.75 seconds
Started Jun 24 05:26:09 PM PDT 24
Finished Jun 24 05:26:11 PM PDT 24
Peak memory 206176 kb
Host smart-3f0e2cbe-a125-4920-90cf-8fd7defc63c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28598
5761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.285985761
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3759325063
Short name T1423
Test name
Test status
Simulation time 40415044 ps
CPU time 0.68 seconds
Started Jun 24 05:26:12 PM PDT 24
Finished Jun 24 05:26:15 PM PDT 24
Peak memory 205568 kb
Host smart-0c215c0f-6f8a-447a-8859-775c1e39b487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37593
25063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3759325063
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2390976659
Short name T2053
Test name
Test status
Simulation time 776455733 ps
CPU time 1.88 seconds
Started Jun 24 05:26:09 PM PDT 24
Finished Jun 24 05:26:12 PM PDT 24
Peak memory 206176 kb
Host smart-ed8f07c2-f805-4681-9bdb-c701bdf0b1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23909
76659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2390976659
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2546040008
Short name T1929
Test name
Test status
Simulation time 254836175 ps
CPU time 1.88 seconds
Started Jun 24 05:26:14 PM PDT 24
Finished Jun 24 05:26:18 PM PDT 24
Peak memory 206240 kb
Host smart-4b6f0b25-0afe-46a9-b010-f9af9df37c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25460
40008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2546040008
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.2593794207
Short name T117
Test name
Test status
Simulation time 232799062 ps
CPU time 0.91 seconds
Started Jun 24 05:26:12 PM PDT 24
Finished Jun 24 05:26:15 PM PDT 24
Peak memory 206172 kb
Host smart-d4c82609-3307-469f-ac67-d1162c02896c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25937
94207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.2593794207
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.4197431427
Short name T1305
Test name
Test status
Simulation time 155594154 ps
CPU time 0.82 seconds
Started Jun 24 05:26:13 PM PDT 24
Finished Jun 24 05:26:16 PM PDT 24
Peak memory 206148 kb
Host smart-c4de710b-b23f-4953-bcc4-e78c1d561e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41974
31427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.4197431427
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.526844921
Short name T2114
Test name
Test status
Simulation time 154769318 ps
CPU time 0.87 seconds
Started Jun 24 05:26:19 PM PDT 24
Finished Jun 24 05:26:21 PM PDT 24
Peak memory 206184 kb
Host smart-f8979479-a0e2-4b21-8476-cca95adcab6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52684
4921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.526844921
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.3475408781
Short name T2155
Test name
Test status
Simulation time 191844639 ps
CPU time 0.83 seconds
Started Jun 24 05:26:09 PM PDT 24
Finished Jun 24 05:26:11 PM PDT 24
Peak memory 206064 kb
Host smart-794f2ae7-251f-4bce-ae7f-4f61c6437882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34754
08781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.3475408781
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.3290655654
Short name T2490
Test name
Test status
Simulation time 23316649440 ps
CPU time 20.43 seconds
Started Jun 24 05:26:10 PM PDT 24
Finished Jun 24 05:26:31 PM PDT 24
Peak memory 206188 kb
Host smart-abaea093-94f2-4cec-a4de-297213ad6494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32906
55654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.3290655654
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.3177626273
Short name T2386
Test name
Test status
Simulation time 3280382084 ps
CPU time 4.32 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:18 PM PDT 24
Peak memory 206240 kb
Host smart-9dde1f37-96dd-47b3-92b2-fba9fcf38c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31776
26273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3177626273
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.389421149
Short name T504
Test name
Test status
Simulation time 3941633701 ps
CPU time 116.71 seconds
Started Jun 24 05:26:12 PM PDT 24
Finished Jun 24 05:28:11 PM PDT 24
Peak memory 206396 kb
Host smart-d81832c2-615c-478f-bffd-5df075347777
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=389421149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.389421149
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.1583640951
Short name T313
Test name
Test status
Simulation time 240956643 ps
CPU time 0.98 seconds
Started Jun 24 05:26:09 PM PDT 24
Finished Jun 24 05:26:11 PM PDT 24
Peak memory 206172 kb
Host smart-7ddd93a7-1d1c-4b0b-a65b-3ee6afa4a0ae
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1583640951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.1583640951
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.582172420
Short name T1130
Test name
Test status
Simulation time 201084239 ps
CPU time 0.88 seconds
Started Jun 24 05:26:09 PM PDT 24
Finished Jun 24 05:26:11 PM PDT 24
Peak memory 206416 kb
Host smart-988beec9-eda7-417f-8270-dea7b9963188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58217
2420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.582172420
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.1711438768
Short name T1728
Test name
Test status
Simulation time 9825151466 ps
CPU time 97.19 seconds
Started Jun 24 05:26:12 PM PDT 24
Finished Jun 24 05:27:52 PM PDT 24
Peak memory 206328 kb
Host smart-afc8d009-910d-480b-9e99-2900cc1ac61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17114
38768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.1711438768
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.4294718384
Short name T2478
Test name
Test status
Simulation time 5977101628 ps
CPU time 44.19 seconds
Started Jun 24 05:26:13 PM PDT 24
Finished Jun 24 05:26:59 PM PDT 24
Peak memory 206292 kb
Host smart-f202d578-bbf9-4d67-9f14-20a53ff64f15
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4294718384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.4294718384
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.2168750141
Short name T2242
Test name
Test status
Simulation time 215835955 ps
CPU time 0.86 seconds
Started Jun 24 05:26:12 PM PDT 24
Finished Jun 24 05:26:16 PM PDT 24
Peak memory 206196 kb
Host smart-5959eaeb-99ef-4b21-979a-c360bfd833a6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2168750141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.2168750141
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.229141431
Short name T1332
Test name
Test status
Simulation time 141085615 ps
CPU time 0.88 seconds
Started Jun 24 05:26:16 PM PDT 24
Finished Jun 24 05:26:18 PM PDT 24
Peak memory 206152 kb
Host smart-aadbc9cc-0b6c-410d-9753-50c40a4378e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22914
1431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.229141431
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.987669882
Short name T127
Test name
Test status
Simulation time 241625124 ps
CPU time 0.92 seconds
Started Jun 24 05:26:12 PM PDT 24
Finished Jun 24 05:26:16 PM PDT 24
Peak memory 206100 kb
Host smart-59af7b01-b822-4735-8ef9-dc3877e3da83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98766
9882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.987669882
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3904690106
Short name T699
Test name
Test status
Simulation time 218976813 ps
CPU time 0.87 seconds
Started Jun 24 05:26:10 PM PDT 24
Finished Jun 24 05:26:12 PM PDT 24
Peak memory 206192 kb
Host smart-7894424d-1e71-4af9-9ea6-c0ed6c733613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39046
90106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3904690106
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1357528747
Short name T2229
Test name
Test status
Simulation time 171241410 ps
CPU time 0.82 seconds
Started Jun 24 05:26:12 PM PDT 24
Finished Jun 24 05:26:16 PM PDT 24
Peak memory 206180 kb
Host smart-d94147e4-d6c5-455e-b3a4-970302d3c841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13575
28747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1357528747
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3835616871
Short name T1168
Test name
Test status
Simulation time 168714404 ps
CPU time 0.82 seconds
Started Jun 24 05:26:10 PM PDT 24
Finished Jun 24 05:26:13 PM PDT 24
Peak memory 206196 kb
Host smart-04bb5ae0-9a21-4725-939a-be4e80536b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38356
16871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3835616871
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2654564702
Short name T1655
Test name
Test status
Simulation time 153986318 ps
CPU time 0.81 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:14 PM PDT 24
Peak memory 206176 kb
Host smart-c77ea594-31c3-4689-a2b5-4548e34d08ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26545
64702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2654564702
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.13259023
Short name T1999
Test name
Test status
Simulation time 227980982 ps
CPU time 0.97 seconds
Started Jun 24 05:26:12 PM PDT 24
Finished Jun 24 05:26:16 PM PDT 24
Peak memory 205440 kb
Host smart-d50ac84a-b185-480a-a35f-6ce8c1e2f093
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=13259023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.13259023
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.2690018541
Short name T1678
Test name
Test status
Simulation time 144379052 ps
CPU time 0.75 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:14 PM PDT 24
Peak memory 206172 kb
Host smart-8397f853-547d-457c-9d01-8772d1617f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26900
18541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.2690018541
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.4235030408
Short name T37
Test name
Test status
Simulation time 30692534 ps
CPU time 0.68 seconds
Started Jun 24 05:26:12 PM PDT 24
Finished Jun 24 05:26:15 PM PDT 24
Peak memory 206188 kb
Host smart-83db6cef-a251-4f06-8606-c9b9fb559e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42350
30408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.4235030408
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.402605789
Short name T276
Test name
Test status
Simulation time 6565844332 ps
CPU time 17.12 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:30 PM PDT 24
Peak memory 206372 kb
Host smart-6f8768d3-87f3-4f75-86ab-e2b96dabc1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40260
5789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.402605789
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2000519211
Short name T519
Test name
Test status
Simulation time 217308510 ps
CPU time 0.86 seconds
Started Jun 24 05:26:10 PM PDT 24
Finished Jun 24 05:26:12 PM PDT 24
Peak memory 206072 kb
Host smart-63af6707-2c0c-44ac-ba9c-45b1085161a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20005
19211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2000519211
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.2068134246
Short name T28
Test name
Test status
Simulation time 171323849 ps
CPU time 0.8 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:15 PM PDT 24
Peak memory 206192 kb
Host smart-b9c617c0-d15d-4afe-87e3-49e4cbebc9c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20681
34246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2068134246
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.841778984
Short name T1313
Test name
Test status
Simulation time 253517989 ps
CPU time 0.93 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:15 PM PDT 24
Peak memory 206112 kb
Host smart-90da0fed-ddcc-4934-88d0-f103dace0a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84177
8984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.841778984
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.2313372933
Short name T1925
Test name
Test status
Simulation time 248516392 ps
CPU time 0.91 seconds
Started Jun 24 05:26:10 PM PDT 24
Finished Jun 24 05:26:12 PM PDT 24
Peak memory 206164 kb
Host smart-fb483501-7f06-4bb9-b1f9-9a1f57687c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23133
72933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.2313372933
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2431752509
Short name T765
Test name
Test status
Simulation time 151972821 ps
CPU time 0.81 seconds
Started Jun 24 05:26:13 PM PDT 24
Finished Jun 24 05:26:16 PM PDT 24
Peak memory 206344 kb
Host smart-56120645-a57a-42cd-ba73-7babb2293a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24317
52509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2431752509
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1856341044
Short name T2461
Test name
Test status
Simulation time 162642104 ps
CPU time 0.78 seconds
Started Jun 24 05:26:18 PM PDT 24
Finished Jun 24 05:26:21 PM PDT 24
Peak memory 206180 kb
Host smart-3d4f3719-fb5d-4214-8abd-247c59000014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18563
41044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1856341044
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1474062848
Short name T1148
Test name
Test status
Simulation time 152236992 ps
CPU time 0.78 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:14 PM PDT 24
Peak memory 206152 kb
Host smart-96598f29-b25a-4a80-ac48-0e8f92aa7058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14740
62848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1474062848
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.659166177
Short name T1102
Test name
Test status
Simulation time 219791148 ps
CPU time 0.91 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:14 PM PDT 24
Peak memory 206192 kb
Host smart-b3f4b113-6b33-4b4f-b5e6-1bce96237324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65916
6177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.659166177
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.2039842840
Short name T2061
Test name
Test status
Simulation time 5804263934 ps
CPU time 164.43 seconds
Started Jun 24 05:26:09 PM PDT 24
Finished Jun 24 05:28:54 PM PDT 24
Peak memory 206396 kb
Host smart-3bb4ffc2-c529-4185-bfda-5ac56b69b5a4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2039842840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2039842840
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.2888629555
Short name T909
Test name
Test status
Simulation time 162885235 ps
CPU time 0.76 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:14 PM PDT 24
Peak memory 206180 kb
Host smart-29dc2382-ee18-43c6-853f-766d346095c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28886
29555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.2888629555
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3237254039
Short name T1767
Test name
Test status
Simulation time 175633208 ps
CPU time 0.83 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:13 PM PDT 24
Peak memory 206192 kb
Host smart-ae92f84e-d507-4cab-8726-d33eb1bff6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32372
54039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3237254039
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.168766554
Short name T777
Test name
Test status
Simulation time 14529188149 ps
CPU time 401.24 seconds
Started Jun 24 05:26:12 PM PDT 24
Finished Jun 24 05:32:56 PM PDT 24
Peak memory 206372 kb
Host smart-a3ea7d6b-e5c3-4e53-aaa5-702db98a2328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16876
6554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.168766554
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3456343909
Short name T895
Test name
Test status
Simulation time 3957469389 ps
CPU time 4.39 seconds
Started Jun 24 05:26:19 PM PDT 24
Finished Jun 24 05:26:25 PM PDT 24
Peak memory 206372 kb
Host smart-d09a31aa-5c61-4fbf-8fa1-b25269c07015
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3456343909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.3456343909
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.2293409629
Short name T2481
Test name
Test status
Simulation time 13522442009 ps
CPU time 13.48 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:26 PM PDT 24
Peak memory 206316 kb
Host smart-9026433c-f84e-4aed-ae89-40e509a67915
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2293409629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.2293409629
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.2636734383
Short name T1282
Test name
Test status
Simulation time 23370134875 ps
CPU time 22.77 seconds
Started Jun 24 05:26:12 PM PDT 24
Finished Jun 24 05:26:37 PM PDT 24
Peak memory 206356 kb
Host smart-c94d18fc-ddda-4e65-8290-2cd7df4417d7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2636734383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.2636734383
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.525791065
Short name T384
Test name
Test status
Simulation time 142419408 ps
CPU time 0.77 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:14 PM PDT 24
Peak memory 206172 kb
Host smart-15ad6038-b450-4aa2-97f2-010c8952a164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52579
1065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.525791065
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.3096327077
Short name T60
Test name
Test status
Simulation time 186275350 ps
CPU time 0.81 seconds
Started Jun 24 05:26:18 PM PDT 24
Finished Jun 24 05:26:21 PM PDT 24
Peak memory 206176 kb
Host smart-add4c3fc-4fa0-4e08-a345-bc5dc7a442c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30963
27077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.3096327077
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.3651357324
Short name T1139
Test name
Test status
Simulation time 461381922 ps
CPU time 1.45 seconds
Started Jun 24 05:26:18 PM PDT 24
Finished Jun 24 05:26:21 PM PDT 24
Peak memory 206260 kb
Host smart-ea274029-b73d-4d5d-9521-ad0d56b9764e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36513
57324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.3651357324
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.354107509
Short name T2074
Test name
Test status
Simulation time 1500263184 ps
CPU time 3.04 seconds
Started Jun 24 05:26:11 PM PDT 24
Finished Jun 24 05:26:17 PM PDT 24
Peak memory 206276 kb
Host smart-f7cdc123-dd2d-423b-a64b-f06d2941140d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35410
7509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.354107509
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.3004741367
Short name T1639
Test name
Test status
Simulation time 9201857611 ps
CPU time 16.38 seconds
Started Jun 24 05:26:33 PM PDT 24
Finished Jun 24 05:26:53 PM PDT 24
Peak memory 206524 kb
Host smart-e30a4828-c050-40cb-b145-d86358005aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30047
41367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.3004741367
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.2823120767
Short name T441
Test name
Test status
Simulation time 475384936 ps
CPU time 1.58 seconds
Started Jun 24 05:26:26 PM PDT 24
Finished Jun 24 05:26:29 PM PDT 24
Peak memory 206104 kb
Host smart-98161df9-57cd-4be0-b7f7-2b3e9e9d2dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28231
20767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.2823120767
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.37220847
Short name T1519
Test name
Test status
Simulation time 160884250 ps
CPU time 0.75 seconds
Started Jun 24 05:26:28 PM PDT 24
Finished Jun 24 05:26:32 PM PDT 24
Peak memory 206196 kb
Host smart-0e57fe5b-706c-44a7-92c4-2c5b7b961059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37220
847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.37220847
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.102672277
Short name T1387
Test name
Test status
Simulation time 40712074 ps
CPU time 0.65 seconds
Started Jun 24 05:26:28 PM PDT 24
Finished Jun 24 05:26:31 PM PDT 24
Peak memory 206148 kb
Host smart-ffecd752-36d1-4e66-b27b-1598bc5d4ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10267
2277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.102672277
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.745240902
Short name T2188
Test name
Test status
Simulation time 863879107 ps
CPU time 2.04 seconds
Started Jun 24 05:26:28 PM PDT 24
Finished Jun 24 05:26:33 PM PDT 24
Peak memory 206296 kb
Host smart-fab0f556-ba3b-4cc0-bfea-56beefc0a32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74524
0902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.745240902
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1252845796
Short name T1836
Test name
Test status
Simulation time 286323966 ps
CPU time 1.91 seconds
Started Jun 24 05:26:27 PM PDT 24
Finished Jun 24 05:26:31 PM PDT 24
Peak memory 206300 kb
Host smart-7800232f-40a3-467d-af5d-06af0b94e51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12528
45796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1252845796
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2225808547
Short name T1737
Test name
Test status
Simulation time 172763353 ps
CPU time 0.85 seconds
Started Jun 24 05:26:25 PM PDT 24
Finished Jun 24 05:26:28 PM PDT 24
Peak memory 206152 kb
Host smart-a8e2cb31-22f9-4144-b2a7-809ba3251fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22258
08547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2225808547
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.783554907
Short name T2293
Test name
Test status
Simulation time 152594135 ps
CPU time 0.8 seconds
Started Jun 24 05:26:26 PM PDT 24
Finished Jun 24 05:26:29 PM PDT 24
Peak memory 206188 kb
Host smart-cd3b4c15-8f69-4dea-b7a2-87da673c3a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78355
4907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.783554907
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3671093808
Short name T1322
Test name
Test status
Simulation time 177173192 ps
CPU time 0.88 seconds
Started Jun 24 05:26:27 PM PDT 24
Finished Jun 24 05:26:30 PM PDT 24
Peak memory 206420 kb
Host smart-2f79fccc-853c-4437-9e3e-cb355da34989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36710
93808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3671093808
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.983726425
Short name T1074
Test name
Test status
Simulation time 196494537 ps
CPU time 0.8 seconds
Started Jun 24 05:26:22 PM PDT 24
Finished Jun 24 05:26:23 PM PDT 24
Peak memory 206164 kb
Host smart-3a99679c-58ad-4938-bec6-e1b6c3546547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98372
6425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.983726425
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.301041288
Short name T2020
Test name
Test status
Simulation time 23400644891 ps
CPU time 22.47 seconds
Started Jun 24 05:26:15 PM PDT 24
Finished Jun 24 05:26:39 PM PDT 24
Peak memory 206248 kb
Host smart-b46818ef-169d-49ac-a0af-91c58a92e90f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30104
1288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.301041288
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.2042126753
Short name T451
Test name
Test status
Simulation time 3331021722 ps
CPU time 4.55 seconds
Started Jun 24 05:26:23 PM PDT 24
Finished Jun 24 05:26:29 PM PDT 24
Peak memory 206240 kb
Host smart-4015484d-ea0e-4fb9-89ea-fedd9569f012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20421
26753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.2042126753
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3670055960
Short name T693
Test name
Test status
Simulation time 13086911450 ps
CPU time 95.48 seconds
Started Jun 24 05:26:26 PM PDT 24
Finished Jun 24 05:28:04 PM PDT 24
Peak memory 206604 kb
Host smart-67ed6e18-962c-4f42-b229-8d557987d4e9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3670055960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3670055960
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.1991798326
Short name T593
Test name
Test status
Simulation time 240777795 ps
CPU time 0.9 seconds
Started Jun 24 05:26:29 PM PDT 24
Finished Jun 24 05:26:34 PM PDT 24
Peak memory 206088 kb
Host smart-9d7208b1-aa8f-40a6-921a-01568edbb027
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1991798326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.1991798326
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1803293422
Short name T2277
Test name
Test status
Simulation time 191340747 ps
CPU time 0.87 seconds
Started Jun 24 05:26:24 PM PDT 24
Finished Jun 24 05:26:26 PM PDT 24
Peak memory 206180 kb
Host smart-9218d479-74fd-4cca-8875-ad8e81810ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18032
93422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1803293422
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.2086676052
Short name T1869
Test name
Test status
Simulation time 11010998741 ps
CPU time 105.33 seconds
Started Jun 24 05:26:25 PM PDT 24
Finished Jun 24 05:28:12 PM PDT 24
Peak memory 206220 kb
Host smart-9f13f84d-1023-4a6c-b413-d90ff1268d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20866
76052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.2086676052
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.348624806
Short name T1848
Test name
Test status
Simulation time 2948574295 ps
CPU time 83.81 seconds
Started Jun 24 05:26:26 PM PDT 24
Finished Jun 24 05:27:53 PM PDT 24
Peak memory 206388 kb
Host smart-b695e989-ace4-4df1-8260-6a6dfb0a1ffb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=348624806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.348624806
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.2110383950
Short name T724
Test name
Test status
Simulation time 149563198 ps
CPU time 0.78 seconds
Started Jun 24 05:26:26 PM PDT 24
Finished Jun 24 05:26:29 PM PDT 24
Peak memory 206080 kb
Host smart-d9044d66-9ce0-4351-b5c5-7bf095ec4938
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2110383950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.2110383950
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.4232245202
Short name T1391
Test name
Test status
Simulation time 159800409 ps
CPU time 0.8 seconds
Started Jun 24 05:26:24 PM PDT 24
Finished Jun 24 05:26:26 PM PDT 24
Peak memory 206180 kb
Host smart-c69cd7c1-eccd-4ea2-abbb-328d31765463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42322
45202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.4232245202
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.4216715796
Short name T151
Test name
Test status
Simulation time 191555565 ps
CPU time 0.87 seconds
Started Jun 24 05:26:28 PM PDT 24
Finished Jun 24 05:26:32 PM PDT 24
Peak memory 205952 kb
Host smart-8eea0a60-5e23-4c18-8fa6-ee05d7205038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42167
15796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.4216715796
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.2243463770
Short name T939
Test name
Test status
Simulation time 184015185 ps
CPU time 0.86 seconds
Started Jun 24 05:26:29 PM PDT 24
Finished Jun 24 05:26:33 PM PDT 24
Peak memory 206092 kb
Host smart-ba0c6cc5-c05d-4a1e-8948-6a6f2010431b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22434
63770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.2243463770
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3821053974
Short name T944
Test name
Test status
Simulation time 160869774 ps
CPU time 0.83 seconds
Started Jun 24 05:26:27 PM PDT 24
Finished Jun 24 05:26:31 PM PDT 24
Peak memory 206140 kb
Host smart-363216f4-af09-423a-bf22-d27a62db244c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38210
53974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3821053974
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2044303490
Short name T1275
Test name
Test status
Simulation time 174497360 ps
CPU time 0.83 seconds
Started Jun 24 05:26:27 PM PDT 24
Finished Jun 24 05:26:31 PM PDT 24
Peak memory 206116 kb
Host smart-adc513cb-2c06-45dc-8edf-bd297290b153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20443
03490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2044303490
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1625967634
Short name T1884
Test name
Test status
Simulation time 157857639 ps
CPU time 0.8 seconds
Started Jun 24 05:26:24 PM PDT 24
Finished Jun 24 05:26:26 PM PDT 24
Peak memory 206152 kb
Host smart-bcee5e7c-f066-42f3-863d-5a4086603ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16259
67634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1625967634
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.4067732118
Short name T348
Test name
Test status
Simulation time 261680979 ps
CPU time 0.98 seconds
Started Jun 24 05:26:27 PM PDT 24
Finished Jun 24 05:26:31 PM PDT 24
Peak memory 206100 kb
Host smart-0170ea64-6dab-4fde-9112-9964afa27ac7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4067732118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.4067732118
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.1688006800
Short name T1706
Test name
Test status
Simulation time 160442539 ps
CPU time 0.8 seconds
Started Jun 24 05:26:29 PM PDT 24
Finished Jun 24 05:26:33 PM PDT 24
Peak memory 206072 kb
Host smart-fe3da053-22d2-408c-883e-ea428170d732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16880
06800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.1688006800
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1583227847
Short name T1297
Test name
Test status
Simulation time 48685917 ps
CPU time 0.7 seconds
Started Jun 24 05:26:27 PM PDT 24
Finished Jun 24 05:26:31 PM PDT 24
Peak memory 206144 kb
Host smart-b5f01837-a6d9-42eb-89a4-d80450f76635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15832
27847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1583227847
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.327093407
Short name T163
Test name
Test status
Simulation time 20252475736 ps
CPU time 42.76 seconds
Started Jun 24 05:26:25 PM PDT 24
Finished Jun 24 05:27:10 PM PDT 24
Peak memory 206348 kb
Host smart-e336e2c2-90ae-43b6-b94b-520e46ace68d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32709
3407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.327093407
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.294108586
Short name T1452
Test name
Test status
Simulation time 196471735 ps
CPU time 0.88 seconds
Started Jun 24 05:26:25 PM PDT 24
Finished Jun 24 05:26:27 PM PDT 24
Peak memory 206104 kb
Host smart-1a342da8-8a09-4739-998a-4c021b4d0d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29410
8586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.294108586
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1140940546
Short name T1429
Test name
Test status
Simulation time 244854842 ps
CPU time 0.92 seconds
Started Jun 24 05:26:22 PM PDT 24
Finished Jun 24 05:26:24 PM PDT 24
Peak memory 206188 kb
Host smart-ea171df0-81ac-4be0-90eb-6e5b4068915d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11409
40546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1140940546
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2249486030
Short name T1627
Test name
Test status
Simulation time 230248237 ps
CPU time 0.86 seconds
Started Jun 24 05:26:25 PM PDT 24
Finished Jun 24 05:26:28 PM PDT 24
Peak memory 206184 kb
Host smart-edc65ea5-8bdf-4df6-b163-75e3ed7613a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22494
86030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2249486030
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.2353114976
Short name T1329
Test name
Test status
Simulation time 166042138 ps
CPU time 0.79 seconds
Started Jun 24 05:26:25 PM PDT 24
Finished Jun 24 05:26:27 PM PDT 24
Peak memory 206204 kb
Host smart-85329370-e4d3-4b94-93dd-7dd8f17d792d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23531
14976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.2353114976
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3337561378
Short name T1978
Test name
Test status
Simulation time 148352646 ps
CPU time 0.78 seconds
Started Jun 24 05:26:25 PM PDT 24
Finished Jun 24 05:26:27 PM PDT 24
Peak memory 206188 kb
Host smart-df8fad0d-7b24-4b68-88e2-c391668823d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33375
61378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3337561378
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2707331589
Short name T782
Test name
Test status
Simulation time 146494377 ps
CPU time 0.75 seconds
Started Jun 24 05:26:17 PM PDT 24
Finished Jun 24 05:26:19 PM PDT 24
Peak memory 206184 kb
Host smart-089395fc-57f9-49f1-b79d-69dede6fb749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27073
31589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2707331589
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1879465221
Short name T340
Test name
Test status
Simulation time 189567078 ps
CPU time 0.82 seconds
Started Jun 24 05:26:25 PM PDT 24
Finished Jun 24 05:26:28 PM PDT 24
Peak memory 206068 kb
Host smart-16a416cc-36a9-42bd-9e71-b8c5e98bbb9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18794
65221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1879465221
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.593373817
Short name T1019
Test name
Test status
Simulation time 315398638 ps
CPU time 0.96 seconds
Started Jun 24 05:26:31 PM PDT 24
Finished Jun 24 05:26:36 PM PDT 24
Peak memory 206128 kb
Host smart-2b115563-71ed-4bbd-ba8d-3232bdfa0889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59337
3817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.593373817
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.77807378
Short name T1449
Test name
Test status
Simulation time 11340033339 ps
CPU time 324.51 seconds
Started Jun 24 05:26:32 PM PDT 24
Finished Jun 24 05:32:01 PM PDT 24
Peak memory 206584 kb
Host smart-9d8ffe5f-c367-4085-918d-d4b6e0a900e7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=77807378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.77807378
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1847750597
Short name T2464
Test name
Test status
Simulation time 200102428 ps
CPU time 0.84 seconds
Started Jun 24 05:26:28 PM PDT 24
Finished Jun 24 05:26:32 PM PDT 24
Peak memory 206172 kb
Host smart-06e565ea-2093-4243-a248-cd8f666c9c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18477
50597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1847750597
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.4244454598
Short name T1804
Test name
Test status
Simulation time 167326505 ps
CPU time 0.8 seconds
Started Jun 24 05:26:31 PM PDT 24
Finished Jun 24 05:26:36 PM PDT 24
Peak memory 206128 kb
Host smart-b8cd1433-a1b9-47ee-83c5-96ffaa6789d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42444
54598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.4244454598
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.2061023234
Short name T1422
Test name
Test status
Simulation time 3975427810 ps
CPU time 34.51 seconds
Started Jun 24 05:26:24 PM PDT 24
Finished Jun 24 05:27:00 PM PDT 24
Peak memory 206268 kb
Host smart-96f9abbe-fddb-4ae9-93ba-3fcab03f095d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20610
23234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2061023234
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.3626262117
Short name T1038
Test name
Test status
Simulation time 3688237944 ps
CPU time 4.55 seconds
Started Jun 24 05:26:28 PM PDT 24
Finished Jun 24 05:26:36 PM PDT 24
Peak memory 206232 kb
Host smart-27e7ddb3-75bb-4056-95f8-b59c512e5347
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3626262117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.3626262117
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.2888219957
Short name T934
Test name
Test status
Simulation time 13353509389 ps
CPU time 13.51 seconds
Started Jun 24 05:26:27 PM PDT 24
Finished Jun 24 05:26:44 PM PDT 24
Peak memory 206240 kb
Host smart-46cacfba-98b5-43fe-8879-29df1270b0ee
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2888219957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.2888219957
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.3323250621
Short name T845
Test name
Test status
Simulation time 23426129792 ps
CPU time 21.02 seconds
Started Jun 24 05:26:26 PM PDT 24
Finished Jun 24 05:26:49 PM PDT 24
Peak memory 206364 kb
Host smart-48325960-4440-427f-a006-fa0465f3cbbe
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3323250621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.3323250621
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.4041858630
Short name T906
Test name
Test status
Simulation time 225147134 ps
CPU time 0.9 seconds
Started Jun 24 05:26:29 PM PDT 24
Finished Jun 24 05:26:33 PM PDT 24
Peak memory 206160 kb
Host smart-f05e9744-1e71-4ac5-a735-e397412c8fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40418
58630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.4041858630
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.2240728192
Short name T2368
Test name
Test status
Simulation time 178237293 ps
CPU time 0.79 seconds
Started Jun 24 05:26:26 PM PDT 24
Finished Jun 24 05:26:29 PM PDT 24
Peak memory 206108 kb
Host smart-96524ef4-302c-44f8-9619-bb6f19bb5b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22407
28192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2240728192
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.17847302
Short name T1026
Test name
Test status
Simulation time 200235494 ps
CPU time 0.8 seconds
Started Jun 24 05:26:28 PM PDT 24
Finished Jun 24 05:26:32 PM PDT 24
Peak memory 206168 kb
Host smart-a4d75184-4495-4796-bc3e-02ac46b48a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17847
302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.17847302
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3303056642
Short name T2103
Test name
Test status
Simulation time 14063761851 ps
CPU time 28.31 seconds
Started Jun 24 05:26:25 PM PDT 24
Finished Jun 24 05:26:56 PM PDT 24
Peak memory 206264 kb
Host smart-136f15e9-14ad-48d7-ae3e-99b9a99b58d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33030
56642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3303056642
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.477870403
Short name T1906
Test name
Test status
Simulation time 451120967 ps
CPU time 1.39 seconds
Started Jun 24 05:26:25 PM PDT 24
Finished Jun 24 05:26:28 PM PDT 24
Peak memory 206180 kb
Host smart-6b805193-ccc5-4b04-afcd-5bbb87058905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47787
0403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.477870403
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.2068816398
Short name T985
Test name
Test status
Simulation time 146325411 ps
CPU time 0.78 seconds
Started Jun 24 05:26:23 PM PDT 24
Finished Jun 24 05:26:25 PM PDT 24
Peak memory 206136 kb
Host smart-8bd6bc33-7409-4693-a56f-4801cc424b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20688
16398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.2068816398
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.2470725406
Short name T1469
Test name
Test status
Simulation time 32308206 ps
CPU time 0.67 seconds
Started Jun 24 05:26:26 PM PDT 24
Finished Jun 24 05:26:30 PM PDT 24
Peak memory 206168 kb
Host smart-e2fc6e1b-97a8-4920-8333-d9963296bcf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24707
25406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2470725406
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3385936146
Short name T155
Test name
Test status
Simulation time 846343542 ps
CPU time 2 seconds
Started Jun 24 05:26:28 PM PDT 24
Finished Jun 24 05:26:33 PM PDT 24
Peak memory 206240 kb
Host smart-64bca69c-d406-4e6b-83eb-9923e0dc6ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33859
36146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3385936146
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3836952434
Short name T931
Test name
Test status
Simulation time 373446595 ps
CPU time 2.31 seconds
Started Jun 24 05:26:29 PM PDT 24
Finished Jun 24 05:26:35 PM PDT 24
Peak memory 206252 kb
Host smart-e3583633-bc44-4444-89b3-d0ccd0f3b8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38369
52434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3836952434
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.641788040
Short name T1191
Test name
Test status
Simulation time 188877282 ps
CPU time 0.84 seconds
Started Jun 24 05:26:28 PM PDT 24
Finished Jun 24 05:26:33 PM PDT 24
Peak memory 206092 kb
Host smart-1ea6c7a7-dbd3-4a63-ad00-e8325e2439b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64178
8040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.641788040
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1640487788
Short name T2127
Test name
Test status
Simulation time 141994607 ps
CPU time 0.74 seconds
Started Jun 24 05:26:34 PM PDT 24
Finished Jun 24 05:26:38 PM PDT 24
Peak memory 206076 kb
Host smart-313d409c-5e64-44d8-a1d8-82201380415e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16404
87788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1640487788
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2826647217
Short name T942
Test name
Test status
Simulation time 172860098 ps
CPU time 0.85 seconds
Started Jun 24 05:26:28 PM PDT 24
Finished Jun 24 05:26:32 PM PDT 24
Peak memory 206004 kb
Host smart-16c0dfeb-2384-4690-9561-9f1173af4e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28266
47217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2826647217
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.3201750470
Short name T1839
Test name
Test status
Simulation time 16174200753 ps
CPU time 107.33 seconds
Started Jun 24 05:26:32 PM PDT 24
Finished Jun 24 05:28:23 PM PDT 24
Peak memory 206500 kb
Host smart-c033ea82-e952-4258-93fe-4e8464c0c490
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3201750470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.3201750470
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.1488516230
Short name T2078
Test name
Test status
Simulation time 203826289 ps
CPU time 0.95 seconds
Started Jun 24 05:26:26 PM PDT 24
Finished Jun 24 05:26:29 PM PDT 24
Peak memory 206172 kb
Host smart-0bcbb245-8d34-47a0-b604-5f3bde192c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14885
16230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.1488516230
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1852268193
Short name T1300
Test name
Test status
Simulation time 23288355593 ps
CPU time 21.72 seconds
Started Jun 24 05:26:24 PM PDT 24
Finished Jun 24 05:26:47 PM PDT 24
Peak memory 206256 kb
Host smart-f38bacaf-5c87-4f83-8d88-b1825cfb2419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18522
68193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1852268193
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.2921664011
Short name T879
Test name
Test status
Simulation time 3320034248 ps
CPU time 4.2 seconds
Started Jun 24 05:26:25 PM PDT 24
Finished Jun 24 05:26:31 PM PDT 24
Peak memory 206240 kb
Host smart-6a6c582e-4ee9-40e7-88e2-ef6f56dbad6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29216
64011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.2921664011
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2128656283
Short name T1861
Test name
Test status
Simulation time 8154278388 ps
CPU time 74.16 seconds
Started Jun 24 05:26:29 PM PDT 24
Finished Jun 24 05:27:47 PM PDT 24
Peak memory 206328 kb
Host smart-3ddfc7cf-2bf7-4bb5-a9fe-7f4e55453373
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2128656283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.2128656283
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.1303430175
Short name T1037
Test name
Test status
Simulation time 244556679 ps
CPU time 0.92 seconds
Started Jun 24 05:26:32 PM PDT 24
Finished Jun 24 05:26:36 PM PDT 24
Peak memory 206140 kb
Host smart-767ade8c-5b4c-4ea6-be96-b2eb217e5ec5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1303430175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.1303430175
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.2352763620
Short name T1974
Test name
Test status
Simulation time 210442389 ps
CPU time 0.93 seconds
Started Jun 24 05:26:29 PM PDT 24
Finished Jun 24 05:26:33 PM PDT 24
Peak memory 206172 kb
Host smart-3f0dcfa6-c0ff-4474-9e8c-b9cc85d0319b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23527
63620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.2352763620
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.3341098669
Short name T1456
Test name
Test status
Simulation time 3034685100 ps
CPU time 82.91 seconds
Started Jun 24 05:26:31 PM PDT 24
Finished Jun 24 05:27:58 PM PDT 24
Peak memory 206376 kb
Host smart-5dba0a0f-0d5c-4df2-9baa-c824383da772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33410
98669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.3341098669
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1263001373
Short name T2134
Test name
Test status
Simulation time 14702166865 ps
CPU time 103.35 seconds
Started Jun 24 05:26:30 PM PDT 24
Finished Jun 24 05:28:17 PM PDT 24
Peak memory 206248 kb
Host smart-bd5a5a76-18b2-42d4-9c3f-5564eaed3c76
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1263001373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1263001373
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1820841166
Short name T2181
Test name
Test status
Simulation time 208781449 ps
CPU time 0.83 seconds
Started Jun 24 05:26:31 PM PDT 24
Finished Jun 24 05:26:36 PM PDT 24
Peak memory 206196 kb
Host smart-7cc944ed-d572-43ff-a914-e04697532804
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1820841166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1820841166
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3187909206
Short name T733
Test name
Test status
Simulation time 151508710 ps
CPU time 0.78 seconds
Started Jun 24 05:26:32 PM PDT 24
Finished Jun 24 05:26:36 PM PDT 24
Peak memory 206176 kb
Host smart-9b76facb-28ef-43b6-a04b-5eb112adffa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31879
09206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3187909206
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3152823262
Short name T2121
Test name
Test status
Simulation time 205392016 ps
CPU time 0.83 seconds
Started Jun 24 05:26:31 PM PDT 24
Finished Jun 24 05:26:36 PM PDT 24
Peak memory 206104 kb
Host smart-bca20773-2f0e-42d6-92ba-11a7e0d53889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31528
23262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3152823262
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1826436120
Short name T1447
Test name
Test status
Simulation time 188134373 ps
CPU time 0.85 seconds
Started Jun 24 05:26:34 PM PDT 24
Finished Jun 24 05:26:38 PM PDT 24
Peak memory 206360 kb
Host smart-ee7ec6ef-e0ac-412d-ad99-c0163536d143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18264
36120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1826436120
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2609550452
Short name T927
Test name
Test status
Simulation time 189757611 ps
CPU time 0.85 seconds
Started Jun 24 05:26:32 PM PDT 24
Finished Jun 24 05:26:37 PM PDT 24
Peak memory 206104 kb
Host smart-5e417dc5-4f51-4f84-a4dd-4902a3ddc4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26095
50452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2609550452
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2972933000
Short name T1926
Test name
Test status
Simulation time 175338084 ps
CPU time 0.87 seconds
Started Jun 24 05:26:32 PM PDT 24
Finished Jun 24 05:26:36 PM PDT 24
Peak memory 206196 kb
Host smart-05cc9eba-7c08-463b-a460-aa6271043998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29729
33000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2972933000
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2074542945
Short name T1887
Test name
Test status
Simulation time 161109353 ps
CPU time 0.78 seconds
Started Jun 24 05:26:33 PM PDT 24
Finished Jun 24 05:26:38 PM PDT 24
Peak memory 206360 kb
Host smart-1b5ccc50-71a9-4fe8-93ee-b895ea73f8bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20745
42945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2074542945
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.4080372947
Short name T1135
Test name
Test status
Simulation time 227934640 ps
CPU time 0.93 seconds
Started Jun 24 05:26:31 PM PDT 24
Finished Jun 24 05:26:36 PM PDT 24
Peak memory 206204 kb
Host smart-cd2aefcb-2fed-4682-a676-7ef6cf898660
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4080372947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.4080372947
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.660866071
Short name T1790
Test name
Test status
Simulation time 170370240 ps
CPU time 0.77 seconds
Started Jun 24 05:26:33 PM PDT 24
Finished Jun 24 05:26:37 PM PDT 24
Peak memory 205804 kb
Host smart-80c75c9d-f151-4beb-ad91-6c331fe5621f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66086
6071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.660866071
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2362131964
Short name T1859
Test name
Test status
Simulation time 96812786 ps
CPU time 0.7 seconds
Started Jun 24 05:26:30 PM PDT 24
Finished Jun 24 05:26:34 PM PDT 24
Peak memory 206172 kb
Host smart-21d65c03-7445-408d-847b-5cd3aa2730b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23621
31964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2362131964
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1151795893
Short name T1972
Test name
Test status
Simulation time 9998941242 ps
CPU time 22.5 seconds
Started Jun 24 05:26:33 PM PDT 24
Finished Jun 24 05:26:59 PM PDT 24
Peak memory 206308 kb
Host smart-765e4d52-187e-4bb2-b2c4-d89d2d73e4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11517
95893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1151795893
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.654566590
Short name T47
Test name
Test status
Simulation time 194299080 ps
CPU time 0.85 seconds
Started Jun 24 05:26:29 PM PDT 24
Finished Jun 24 05:26:34 PM PDT 24
Peak memory 206056 kb
Host smart-7fc6025b-b04a-48e6-90ea-f0a794173cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65456
6590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.654566590
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1390428584
Short name T2372
Test name
Test status
Simulation time 210113824 ps
CPU time 0.93 seconds
Started Jun 24 05:26:33 PM PDT 24
Finished Jun 24 05:26:38 PM PDT 24
Peak memory 206116 kb
Host smart-1139e48e-bafd-4ec6-ba2c-e4b5eeca67f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13904
28584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1390428584
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.3638498534
Short name T901
Test name
Test status
Simulation time 177812671 ps
CPU time 0.82 seconds
Started Jun 24 05:26:33 PM PDT 24
Finished Jun 24 05:26:38 PM PDT 24
Peak memory 206156 kb
Host smart-636f2bca-ea26-469f-a799-ec6fb89b7ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36384
98534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.3638498534
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3978846646
Short name T638
Test name
Test status
Simulation time 175677790 ps
CPU time 0.9 seconds
Started Jun 24 05:26:30 PM PDT 24
Finished Jun 24 05:26:35 PM PDT 24
Peak memory 206184 kb
Host smart-bbfe2a7a-4f31-413d-a3a0-632da396b5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39788
46646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3978846646
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1816368051
Short name T2178
Test name
Test status
Simulation time 187721015 ps
CPU time 0.83 seconds
Started Jun 24 05:26:33 PM PDT 24
Finished Jun 24 05:26:38 PM PDT 24
Peak memory 206188 kb
Host smart-0e59f793-0128-4429-af3b-addc03491710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18163
68051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1816368051
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1264571371
Short name T427
Test name
Test status
Simulation time 190909814 ps
CPU time 0.79 seconds
Started Jun 24 05:26:33 PM PDT 24
Finished Jun 24 05:26:37 PM PDT 24
Peak memory 206132 kb
Host smart-e1f4395a-f8f1-4d26-8560-f04bbc93a0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12645
71371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1264571371
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3225853721
Short name T611
Test name
Test status
Simulation time 148216599 ps
CPU time 0.76 seconds
Started Jun 24 05:26:31 PM PDT 24
Finished Jun 24 05:26:35 PM PDT 24
Peak memory 206104 kb
Host smart-bdf26330-f3e3-46b6-b966-e8a1963d6bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32258
53721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3225853721
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1839513188
Short name T2266
Test name
Test status
Simulation time 193697480 ps
CPU time 0.88 seconds
Started Jun 24 05:26:30 PM PDT 24
Finished Jun 24 05:26:35 PM PDT 24
Peak memory 206144 kb
Host smart-e4102063-67f1-4a47-a116-ccf162cc333f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18395
13188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1839513188
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.3159635295
Short name T2513
Test name
Test status
Simulation time 3712682237 ps
CPU time 103.5 seconds
Started Jun 24 05:26:33 PM PDT 24
Finished Jun 24 05:28:20 PM PDT 24
Peak memory 206280 kb
Host smart-b19dd6e4-afd3-49c2-91e7-6b7177d28e86
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3159635295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.3159635295
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2869657412
Short name T2265
Test name
Test status
Simulation time 169692611 ps
CPU time 0.79 seconds
Started Jun 24 05:26:32 PM PDT 24
Finished Jun 24 05:26:37 PM PDT 24
Peak memory 206068 kb
Host smart-4cd30ac6-a3f2-4a24-947e-6c5fbc66527d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28696
57412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2869657412
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.3580463396
Short name T1403
Test name
Test status
Simulation time 144564028 ps
CPU time 0.76 seconds
Started Jun 24 05:26:31 PM PDT 24
Finished Jun 24 05:26:36 PM PDT 24
Peak memory 206112 kb
Host smart-1b40df5e-53d3-4ba1-87b9-838068b9d45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35804
63396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3580463396
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.176340039
Short name T1980
Test name
Test status
Simulation time 7902535698 ps
CPU time 216 seconds
Started Jun 24 05:26:32 PM PDT 24
Finished Jun 24 05:30:11 PM PDT 24
Peak memory 206388 kb
Host smart-bee64bad-7a51-4692-90e2-d638a8bb2ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17634
0039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.176340039
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1002496187
Short name T2398
Test name
Test status
Simulation time 4116093101 ps
CPU time 5.18 seconds
Started Jun 24 05:26:32 PM PDT 24
Finished Jun 24 05:26:40 PM PDT 24
Peak memory 206224 kb
Host smart-669ffda4-dff0-4b55-807a-7c066df78a1e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1002496187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.1002496187
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.3887534395
Short name T904
Test name
Test status
Simulation time 13399912971 ps
CPU time 12.51 seconds
Started Jun 24 05:26:31 PM PDT 24
Finished Jun 24 05:26:47 PM PDT 24
Peak memory 206244 kb
Host smart-780377ca-0c10-4a66-9209-77ca7828b754
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3887534395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.3887534395
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.4091079514
Short name T974
Test name
Test status
Simulation time 23318286165 ps
CPU time 27.99 seconds
Started Jun 24 05:26:29 PM PDT 24
Finished Jun 24 05:27:01 PM PDT 24
Peak memory 206240 kb
Host smart-b245b27d-c934-408a-a46a-31309b3a48a3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4091079514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.4091079514
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2619393032
Short name T820
Test name
Test status
Simulation time 160410710 ps
CPU time 0.77 seconds
Started Jun 24 05:26:33 PM PDT 24
Finished Jun 24 05:26:38 PM PDT 24
Peak memory 206104 kb
Host smart-bba6c48c-b5ad-437f-9da2-fc6c6ced6094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26193
93032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2619393032
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.2538467593
Short name T1783
Test name
Test status
Simulation time 145432599 ps
CPU time 0.79 seconds
Started Jun 24 05:26:31 PM PDT 24
Finished Jun 24 05:26:36 PM PDT 24
Peak memory 206176 kb
Host smart-aac36e76-bd90-4e1c-b100-61af78aee389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25384
67593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.2538467593
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.2203311082
Short name T529
Test name
Test status
Simulation time 177787357 ps
CPU time 0.8 seconds
Started Jun 24 05:26:30 PM PDT 24
Finished Jun 24 05:26:35 PM PDT 24
Peak memory 206128 kb
Host smart-83697049-b16c-4c5e-bfce-dcf9efbefcf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22033
11082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.2203311082
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.843738395
Short name T1169
Test name
Test status
Simulation time 794495119 ps
CPU time 2.1 seconds
Started Jun 24 05:26:32 PM PDT 24
Finished Jun 24 05:26:38 PM PDT 24
Peak memory 206284 kb
Host smart-43adc263-064b-40a8-8f71-60462cb65b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84373
8395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.843738395
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.1957784625
Short name T674
Test name
Test status
Simulation time 15528407585 ps
CPU time 31.88 seconds
Started Jun 24 05:26:32 PM PDT 24
Finished Jun 24 05:27:07 PM PDT 24
Peak memory 206328 kb
Host smart-74dfa25a-03cf-4374-b02b-0291a79184b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19577
84625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.1957784625
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.4085745775
Short name T2092
Test name
Test status
Simulation time 510072875 ps
CPU time 1.4 seconds
Started Jun 24 05:26:31 PM PDT 24
Finished Jun 24 05:26:36 PM PDT 24
Peak memory 206176 kb
Host smart-fbed8d38-351d-4d93-9ff0-283f0aab46b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40857
45775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.4085745775
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3404796772
Short name T2407
Test name
Test status
Simulation time 194908649 ps
CPU time 0.83 seconds
Started Jun 24 05:26:34 PM PDT 24
Finished Jun 24 05:26:38 PM PDT 24
Peak memory 206172 kb
Host smart-e9d5708d-55c2-41c6-b25d-28e650e096b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34047
96772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3404796772
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.1141809955
Short name T1326
Test name
Test status
Simulation time 73220575 ps
CPU time 0.66 seconds
Started Jun 24 05:26:31 PM PDT 24
Finished Jun 24 05:26:35 PM PDT 24
Peak memory 206152 kb
Host smart-6fc6b341-0675-4b19-af85-80e17e589f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11418
09955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1141809955
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.4014990535
Short name T1262
Test name
Test status
Simulation time 968546179 ps
CPU time 2.35 seconds
Started Jun 24 05:26:29 PM PDT 24
Finished Jun 24 05:26:35 PM PDT 24
Peak memory 206132 kb
Host smart-1accba6f-ab3f-48b5-9b6f-69ff93265683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40149
90535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.4014990535
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.2498066059
Short name T2411
Test name
Test status
Simulation time 199357230 ps
CPU time 1.4 seconds
Started Jun 24 05:26:30 PM PDT 24
Finished Jun 24 05:26:35 PM PDT 24
Peak memory 206244 kb
Host smart-db6a514e-357a-4395-9b06-ba6dd4478eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24980
66059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2498066059
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2381816292
Short name T1830
Test name
Test status
Simulation time 185883100 ps
CPU time 0.82 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:26:47 PM PDT 24
Peak memory 206176 kb
Host smart-78899250-827d-4be1-8f0b-1bd2b50fd637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23818
16292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2381816292
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.32918438
Short name T399
Test name
Test status
Simulation time 145014555 ps
CPU time 0.77 seconds
Started Jun 24 05:26:41 PM PDT 24
Finished Jun 24 05:26:44 PM PDT 24
Peak memory 206192 kb
Host smart-c554e8b8-df3a-439c-98f9-77258008ffbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32918
438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.32918438
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2525788350
Short name T395
Test name
Test status
Simulation time 222626746 ps
CPU time 0.92 seconds
Started Jun 24 05:26:33 PM PDT 24
Finished Jun 24 05:26:37 PM PDT 24
Peak memory 206184 kb
Host smart-07fe08aa-7661-4235-9f5b-aa7d63455cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25257
88350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2525788350
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.3155547176
Short name T389
Test name
Test status
Simulation time 194390388 ps
CPU time 0.92 seconds
Started Jun 24 05:26:43 PM PDT 24
Finished Jun 24 05:26:46 PM PDT 24
Peak memory 206196 kb
Host smart-70aa6669-0c21-458a-8458-fe13bb3d2084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31555
47176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.3155547176
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.585722387
Short name T470
Test name
Test status
Simulation time 23316993732 ps
CPU time 21.8 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:27:08 PM PDT 24
Peak memory 206176 kb
Host smart-18e455a6-6b37-47cb-aa17-9dc003a06a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58572
2387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.585722387
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.2744676733
Short name T896
Test name
Test status
Simulation time 3309484862 ps
CPU time 3.72 seconds
Started Jun 24 05:26:42 PM PDT 24
Finished Jun 24 05:26:48 PM PDT 24
Peak memory 206240 kb
Host smart-e3b49180-abb3-4e8e-801f-2f5f18a5efd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27446
76733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.2744676733
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.3513681300
Short name T1873
Test name
Test status
Simulation time 4545866921 ps
CPU time 33.73 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206396 kb
Host smart-601806b5-8d85-40d8-a5a1-972b5346a2a9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3513681300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.3513681300
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.766495988
Short name T1032
Test name
Test status
Simulation time 309772944 ps
CPU time 1.02 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:26:47 PM PDT 24
Peak memory 206180 kb
Host smart-8df1be8b-c2f6-409a-8505-8f4a83ae134c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=766495988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.766495988
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2031621870
Short name T331
Test name
Test status
Simulation time 181407082 ps
CPU time 0.85 seconds
Started Jun 24 05:26:42 PM PDT 24
Finished Jun 24 05:26:45 PM PDT 24
Peak memory 206108 kb
Host smart-e2d980c9-34c2-4008-b552-7b4935036a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20316
21870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2031621870
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.3903000676
Short name T1442
Test name
Test status
Simulation time 9142384591 ps
CPU time 260.86 seconds
Started Jun 24 05:26:43 PM PDT 24
Finished Jun 24 05:31:06 PM PDT 24
Peak memory 206624 kb
Host smart-29ae9362-907c-4cfc-9536-c8303144df41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39030
00676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.3903000676
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.2572738239
Short name T1185
Test name
Test status
Simulation time 11764366791 ps
CPU time 327.93 seconds
Started Jun 24 05:26:42 PM PDT 24
Finished Jun 24 05:32:12 PM PDT 24
Peak memory 206396 kb
Host smart-c678e7f5-9e05-4075-9fb6-524c054ec075
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2572738239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.2572738239
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.3956388547
Short name T1570
Test name
Test status
Simulation time 168560884 ps
CPU time 0.8 seconds
Started Jun 24 05:26:41 PM PDT 24
Finished Jun 24 05:26:43 PM PDT 24
Peak memory 206188 kb
Host smart-6d681fd8-3f44-41df-82a9-32dbfa808685
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3956388547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.3956388547
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3061300166
Short name T952
Test name
Test status
Simulation time 151227536 ps
CPU time 0.78 seconds
Started Jun 24 05:26:40 PM PDT 24
Finished Jun 24 05:26:43 PM PDT 24
Peak memory 206408 kb
Host smart-65b444ec-c4c1-4ae8-8d2a-5ae042567354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30613
00166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3061300166
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1501660999
Short name T143
Test name
Test status
Simulation time 197778672 ps
CPU time 0.81 seconds
Started Jun 24 05:26:40 PM PDT 24
Finished Jun 24 05:26:42 PM PDT 24
Peak memory 206064 kb
Host smart-ae7ee45f-3163-4e3b-97a4-20ffec32f267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15016
60999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1501660999
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1371608072
Short name T1603
Test name
Test status
Simulation time 150180193 ps
CPU time 0.83 seconds
Started Jun 24 05:26:43 PM PDT 24
Finished Jun 24 05:26:46 PM PDT 24
Peak memory 206116 kb
Host smart-90d078a1-fc54-485a-9797-204e1eb35d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13716
08072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1371608072
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.3897385628
Short name T2228
Test name
Test status
Simulation time 172828102 ps
CPU time 0.81 seconds
Started Jun 24 05:26:45 PM PDT 24
Finished Jun 24 05:26:48 PM PDT 24
Peak memory 206156 kb
Host smart-a0214497-4979-4070-aa8b-c924c9d716db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38973
85628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.3897385628
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.432798261
Short name T571
Test name
Test status
Simulation time 189313506 ps
CPU time 0.86 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:26:47 PM PDT 24
Peak memory 206168 kb
Host smart-bf396186-89ff-46c0-b5f4-c52943fa9901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43279
8261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.432798261
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.599968314
Short name T1849
Test name
Test status
Simulation time 144826144 ps
CPU time 0.79 seconds
Started Jun 24 05:26:43 PM PDT 24
Finished Jun 24 05:26:46 PM PDT 24
Peak memory 206104 kb
Host smart-82a05549-b295-4a48-94a6-56e0871317f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59996
8314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.599968314
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.3415846658
Short name T2239
Test name
Test status
Simulation time 236299600 ps
CPU time 0.98 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:26:47 PM PDT 24
Peak memory 206096 kb
Host smart-e6364d6e-ca47-472d-a206-5efcf55d3e3f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3415846658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3415846658
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1372593223
Short name T1788
Test name
Test status
Simulation time 144218742 ps
CPU time 0.76 seconds
Started Jun 24 05:26:42 PM PDT 24
Finished Jun 24 05:26:45 PM PDT 24
Peak memory 206188 kb
Host smart-cb3c16aa-3166-4b5d-8d01-6ba6ed1943ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13725
93223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1372593223
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.2286956207
Short name T1763
Test name
Test status
Simulation time 37523203 ps
CPU time 0.67 seconds
Started Jun 24 05:26:41 PM PDT 24
Finished Jun 24 05:26:44 PM PDT 24
Peak memory 206176 kb
Host smart-4cf4269e-9415-44ad-990d-e09a01b54cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22869
56207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.2286956207
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.751377180
Short name T2393
Test name
Test status
Simulation time 5881866590 ps
CPU time 15.43 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:27:02 PM PDT 24
Peak memory 206348 kb
Host smart-635d33e6-c371-47c5-8975-0d7ab16e1c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75137
7180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.751377180
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.3418496110
Short name T2308
Test name
Test status
Simulation time 196171302 ps
CPU time 0.81 seconds
Started Jun 24 05:26:45 PM PDT 24
Finished Jun 24 05:26:48 PM PDT 24
Peak memory 206148 kb
Host smart-775bedae-d0ea-4800-b886-654a19284ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34184
96110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.3418496110
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1991525177
Short name T1190
Test name
Test status
Simulation time 255316721 ps
CPU time 1.01 seconds
Started Jun 24 05:26:42 PM PDT 24
Finished Jun 24 05:26:45 PM PDT 24
Peak memory 206192 kb
Host smart-2f8b00be-f1cd-40d3-8ede-2298b6aa05f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19915
25177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1991525177
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.3762643430
Short name T2144
Test name
Test status
Simulation time 211970111 ps
CPU time 0.87 seconds
Started Jun 24 05:26:48 PM PDT 24
Finished Jun 24 05:26:50 PM PDT 24
Peak memory 205696 kb
Host smart-0872ff82-197c-44fa-8a4b-66ed42e9ba0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37626
43430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.3762643430
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.1296867297
Short name T1416
Test name
Test status
Simulation time 190204298 ps
CPU time 0.89 seconds
Started Jun 24 05:26:48 PM PDT 24
Finished Jun 24 05:26:50 PM PDT 24
Peak memory 206184 kb
Host smart-336f2d78-7a4b-4966-9a12-1aca90e2bbd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12968
67297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.1296867297
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.4064946292
Short name T486
Test name
Test status
Simulation time 191629001 ps
CPU time 0.81 seconds
Started Jun 24 05:26:41 PM PDT 24
Finished Jun 24 05:26:43 PM PDT 24
Peak memory 206192 kb
Host smart-25d470a2-ce21-4010-99fe-8d6d4f8ca59b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40649
46292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.4064946292
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1898621612
Short name T1001
Test name
Test status
Simulation time 157742317 ps
CPU time 0.75 seconds
Started Jun 24 05:26:42 PM PDT 24
Finished Jun 24 05:26:45 PM PDT 24
Peak memory 206168 kb
Host smart-bb3fe8d2-511c-412b-9f70-fd6a39f70bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18986
21612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1898621612
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.92395685
Short name T2405
Test name
Test status
Simulation time 160323465 ps
CPU time 0.76 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:26:47 PM PDT 24
Peak memory 206096 kb
Host smart-3a51185c-7582-4ce0-afd4-9c30ecf014a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92395
685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.92395685
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.4104120744
Short name T690
Test name
Test status
Simulation time 199902689 ps
CPU time 0.89 seconds
Started Jun 24 05:26:43 PM PDT 24
Finished Jun 24 05:26:46 PM PDT 24
Peak memory 206092 kb
Host smart-c067871b-b039-4b0e-9cae-7bd465b837f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41041
20744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.4104120744
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.3617272050
Short name T1649
Test name
Test status
Simulation time 8332532690 ps
CPU time 237.4 seconds
Started Jun 24 05:26:41 PM PDT 24
Finished Jun 24 05:30:40 PM PDT 24
Peak memory 206372 kb
Host smart-214088c5-413f-495c-aa33-ea49d41bc8dd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3617272050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.3617272050
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1699114480
Short name T1625
Test name
Test status
Simulation time 187083927 ps
CPU time 0.84 seconds
Started Jun 24 05:26:43 PM PDT 24
Finished Jun 24 05:26:46 PM PDT 24
Peak memory 206080 kb
Host smart-182ae6d0-3b94-449c-943f-ff7df76f6e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16991
14480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1699114480
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.729114603
Short name T1636
Test name
Test status
Simulation time 185384139 ps
CPU time 0.83 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:26:47 PM PDT 24
Peak memory 206092 kb
Host smart-2b5c5b48-91b6-44d8-af82-57dfc98b1e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72911
4603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.729114603
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.1846594736
Short name T1735
Test name
Test status
Simulation time 7872220963 ps
CPU time 58 seconds
Started Jun 24 05:26:43 PM PDT 24
Finished Jun 24 05:27:43 PM PDT 24
Peak memory 206252 kb
Host smart-ca7402b3-5104-4e43-b7b3-be75aa7501a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18465
94736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.1846594736
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.3228960932
Short name T2502
Test name
Test status
Simulation time 4080819608 ps
CPU time 4.84 seconds
Started Jun 24 05:20:48 PM PDT 24
Finished Jun 24 05:20:55 PM PDT 24
Peak memory 206424 kb
Host smart-da3aed63-b5d5-4b41-99b7-4b8b136b84f0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3228960932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.3228960932
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.3382381921
Short name T975
Test name
Test status
Simulation time 13330789148 ps
CPU time 13.85 seconds
Started Jun 24 05:20:47 PM PDT 24
Finished Jun 24 05:21:03 PM PDT 24
Peak memory 206228 kb
Host smart-3f5eca82-2dc3-4334-8735-f69fa90e0aa4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3382381921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.3382381921
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3060995127
Short name T2142
Test name
Test status
Simulation time 163353514 ps
CPU time 0.8 seconds
Started Jun 24 05:20:54 PM PDT 24
Finished Jun 24 05:20:58 PM PDT 24
Peak memory 206152 kb
Host smart-133b7b2c-f8a6-4148-a59e-e59fa8af4af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30609
95127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3060995127
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.1520182463
Short name T61
Test name
Test status
Simulation time 155222330 ps
CPU time 0.83 seconds
Started Jun 24 05:20:46 PM PDT 24
Finished Jun 24 05:20:48 PM PDT 24
Peak memory 206088 kb
Host smart-b1ac2f57-70ec-4a4c-a094-07ab4a93092e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15201
82463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.1520182463
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.2118029023
Short name T78
Test name
Test status
Simulation time 217464991 ps
CPU time 0.9 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:21:00 PM PDT 24
Peak memory 206176 kb
Host smart-0ce9ba23-af6a-457b-9576-2984870de0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21180
29023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.2118029023
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.156220889
Short name T524
Test name
Test status
Simulation time 251085886 ps
CPU time 0.98 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:20:59 PM PDT 24
Peak memory 206180 kb
Host smart-02e31951-1981-40e6-8bdb-4b35290bdf0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15622
0889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.156220889
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.691274375
Short name T1518
Test name
Test status
Simulation time 910463609 ps
CPU time 2.07 seconds
Started Jun 24 05:20:47 PM PDT 24
Finished Jun 24 05:20:50 PM PDT 24
Peak memory 206176 kb
Host smart-d8fc7ad6-15cc-408f-832e-8c04ea67c8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69127
4375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.691274375
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.2135419334
Short name T2032
Test name
Test status
Simulation time 518634955 ps
CPU time 1.51 seconds
Started Jun 24 05:20:49 PM PDT 24
Finished Jun 24 05:20:53 PM PDT 24
Peak memory 206168 kb
Host smart-bf93d441-1fcf-4524-b0ae-e1a36e95708d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21354
19334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.2135419334
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2360648132
Short name T1781
Test name
Test status
Simulation time 137353467 ps
CPU time 0.73 seconds
Started Jun 24 05:20:54 PM PDT 24
Finished Jun 24 05:20:56 PM PDT 24
Peak memory 206148 kb
Host smart-b75989c4-daa0-4625-b711-9aebcc114072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23606
48132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2360648132
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.2740239453
Short name T238
Test name
Test status
Simulation time 72301378 ps
CPU time 0.69 seconds
Started Jun 24 05:20:47 PM PDT 24
Finished Jun 24 05:20:50 PM PDT 24
Peak memory 206092 kb
Host smart-b378f082-78be-48be-a865-8b45daedaa60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27402
39453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2740239453
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.4177136628
Short name T1823
Test name
Test status
Simulation time 865204364 ps
CPU time 2.18 seconds
Started Jun 24 05:20:49 PM PDT 24
Finished Jun 24 05:20:53 PM PDT 24
Peak memory 206296 kb
Host smart-097535a9-69cf-414b-a205-7794736cb25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41771
36628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.4177136628
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.973377241
Short name T2319
Test name
Test status
Simulation time 318651185 ps
CPU time 2.35 seconds
Started Jun 24 05:20:48 PM PDT 24
Finished Jun 24 05:20:52 PM PDT 24
Peak memory 206272 kb
Host smart-93f92daa-a5d7-463a-8f7e-39fb6d260645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97337
7241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.973377241
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3325532514
Short name T2426
Test name
Test status
Simulation time 191254895 ps
CPU time 0.91 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:21:00 PM PDT 24
Peak memory 206100 kb
Host smart-8a089c45-a6ff-4799-a654-feaa9d05d97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33255
32514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3325532514
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.791720569
Short name T681
Test name
Test status
Simulation time 146696902 ps
CPU time 0.77 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:21:00 PM PDT 24
Peak memory 206132 kb
Host smart-c83a3a26-99a8-4ecf-9cc8-770f4350d693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79172
0569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.791720569
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3535198670
Short name T907
Test name
Test status
Simulation time 214821044 ps
CPU time 0.87 seconds
Started Jun 24 05:20:54 PM PDT 24
Finished Jun 24 05:20:56 PM PDT 24
Peak memory 206168 kb
Host smart-d8f3b8f0-0366-45af-9bbb-0cba8dd38de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35351
98670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3535198670
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3388108178
Short name T1875
Test name
Test status
Simulation time 226463296 ps
CPU time 0.87 seconds
Started Jun 24 05:20:49 PM PDT 24
Finished Jun 24 05:20:52 PM PDT 24
Peak memory 206176 kb
Host smart-11199424-7f38-4cba-a2a0-aebdcc49e755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33881
08178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3388108178
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.4170511130
Short name T632
Test name
Test status
Simulation time 23359820874 ps
CPU time 21.2 seconds
Started Jun 24 05:20:47 PM PDT 24
Finished Jun 24 05:21:09 PM PDT 24
Peak memory 206248 kb
Host smart-d9c2d569-237f-4f6e-84d2-2a2a39a0923b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41705
11130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.4170511130
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.1284437438
Short name T1255
Test name
Test status
Simulation time 3339403629 ps
CPU time 4.02 seconds
Started Jun 24 05:20:50 PM PDT 24
Finished Jun 24 05:20:56 PM PDT 24
Peak memory 206236 kb
Host smart-65b7a387-d541-4013-ac68-e17da800faec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12844
37438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.1284437438
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.879006068
Short name T1495
Test name
Test status
Simulation time 5014543603 ps
CPU time 48.26 seconds
Started Jun 24 05:20:53 PM PDT 24
Finished Jun 24 05:21:43 PM PDT 24
Peak memory 206328 kb
Host smart-2a04f191-add7-4d52-9399-56691b375df7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=879006068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.879006068
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.2398111721
Short name T1694
Test name
Test status
Simulation time 237851943 ps
CPU time 0.92 seconds
Started Jun 24 05:20:58 PM PDT 24
Finished Jun 24 05:21:03 PM PDT 24
Peak memory 206180 kb
Host smart-bfe7e78c-24fe-4160-83d1-f2fa986564bb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2398111721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.2398111721
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3723229886
Short name T1134
Test name
Test status
Simulation time 199387224 ps
CPU time 0.88 seconds
Started Jun 24 05:20:48 PM PDT 24
Finished Jun 24 05:20:51 PM PDT 24
Peak memory 206196 kb
Host smart-fa22baff-ef23-431d-be40-d18dd95be3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37232
29886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3723229886
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.2425555729
Short name T1668
Test name
Test status
Simulation time 9083893932 ps
CPU time 86.56 seconds
Started Jun 24 05:20:49 PM PDT 24
Finished Jun 24 05:22:18 PM PDT 24
Peak memory 206320 kb
Host smart-c2c38f23-08b8-4a3c-adaf-41b99f00b508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24255
55729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.2425555729
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.151005145
Short name T771
Test name
Test status
Simulation time 10039659169 ps
CPU time 294.89 seconds
Started Jun 24 05:20:47 PM PDT 24
Finished Jun 24 05:25:43 PM PDT 24
Peak memory 206396 kb
Host smart-599eaa00-0a5d-4174-9b67-cbaefc22b398
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=151005145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.151005145
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.168347064
Short name T430
Test name
Test status
Simulation time 189003909 ps
CPU time 0.86 seconds
Started Jun 24 05:20:56 PM PDT 24
Finished Jun 24 05:21:02 PM PDT 24
Peak memory 206192 kb
Host smart-aa0bd941-4273-459c-9f9f-f8c9829cbaa7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=168347064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.168347064
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1197447321
Short name T2295
Test name
Test status
Simulation time 197636865 ps
CPU time 0.84 seconds
Started Jun 24 05:20:49 PM PDT 24
Finished Jun 24 05:20:52 PM PDT 24
Peak memory 206152 kb
Host smart-17603680-240d-4781-8c7d-9f8c247144b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11974
47321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1197447321
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.1316297284
Short name T1916
Test name
Test status
Simulation time 166727842 ps
CPU time 0.89 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:21:01 PM PDT 24
Peak memory 206096 kb
Host smart-0ae663b2-a78f-4977-aefa-a5550e356fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13162
97284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1316297284
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.92197856
Short name T106
Test name
Test status
Simulation time 169913616 ps
CPU time 0.9 seconds
Started Jun 24 05:20:56 PM PDT 24
Finished Jun 24 05:21:02 PM PDT 24
Peak memory 206188 kb
Host smart-bd5c8f04-486d-462c-9766-98f0c56ae369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92197
856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.92197856
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.828986980
Short name T1975
Test name
Test status
Simulation time 139757646 ps
CPU time 0.77 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:21:00 PM PDT 24
Peak memory 206172 kb
Host smart-077a1abd-44a8-4115-9f64-c7c5f9d38309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82898
6980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.828986980
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1369260772
Short name T166
Test name
Test status
Simulation time 215092373 ps
CPU time 0.81 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:21:00 PM PDT 24
Peak memory 206096 kb
Host smart-918abee1-8db1-4f87-8ebd-5f9a813403e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13692
60772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1369260772
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.2512260291
Short name T1053
Test name
Test status
Simulation time 188816949 ps
CPU time 0.87 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:20:59 PM PDT 24
Peak memory 206180 kb
Host smart-c49d6f7d-e675-4090-aa57-bca7adcfe818
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2512260291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.2512260291
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.4243652870
Short name T209
Test name
Test status
Simulation time 221381911 ps
CPU time 0.96 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:20:59 PM PDT 24
Peak memory 206132 kb
Host smart-face2218-9f96-4d78-8de4-e518c12fb791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42436
52870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.4243652870
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.4228540456
Short name T1771
Test name
Test status
Simulation time 157033502 ps
CPU time 0.82 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:21:00 PM PDT 24
Peak memory 206092 kb
Host smart-3b88dff7-418b-4561-893a-f7985a1e64d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42285
40456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.4228540456
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3466478934
Short name T1013
Test name
Test status
Simulation time 44672353 ps
CPU time 0.7 seconds
Started Jun 24 05:20:56 PM PDT 24
Finished Jun 24 05:21:02 PM PDT 24
Peak memory 206168 kb
Host smart-f0d078ba-de8e-43b8-ba82-6ef24d7269ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34664
78934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3466478934
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3343455464
Short name T1563
Test name
Test status
Simulation time 9381736828 ps
CPU time 19.53 seconds
Started Jun 24 05:20:57 PM PDT 24
Finished Jun 24 05:21:21 PM PDT 24
Peak memory 206380 kb
Host smart-69a71b0d-75f1-4d94-9f61-713378309fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33434
55464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3343455464
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.4038816491
Short name T1224
Test name
Test status
Simulation time 203379389 ps
CPU time 0.9 seconds
Started Jun 24 05:20:57 PM PDT 24
Finished Jun 24 05:21:03 PM PDT 24
Peak memory 206156 kb
Host smart-840976da-c6e5-46db-853e-1f436ad26e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40388
16491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.4038816491
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1550204103
Short name T2328
Test name
Test status
Simulation time 210586790 ps
CPU time 0.88 seconds
Started Jun 24 05:20:56 PM PDT 24
Finished Jun 24 05:21:02 PM PDT 24
Peak memory 206092 kb
Host smart-0982ccdf-3b4d-49e4-b37e-01c2362a5306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15502
04103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1550204103
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.391476869
Short name T174
Test name
Test status
Simulation time 8246150390 ps
CPU time 62.38 seconds
Started Jun 24 05:20:56 PM PDT 24
Finished Jun 24 05:22:03 PM PDT 24
Peak memory 206360 kb
Host smart-9261a596-a1f1-4e5e-bcb5-7d5e5b55d20d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=391476869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.391476869
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2068087723
Short name T1615
Test name
Test status
Simulation time 29865457896 ps
CPU time 771.36 seconds
Started Jun 24 05:20:57 PM PDT 24
Finished Jun 24 05:33:53 PM PDT 24
Peak memory 206404 kb
Host smart-e517e7f6-9043-45aa-8617-b6e6c2422ed8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2068087723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2068087723
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.54082555
Short name T800
Test name
Test status
Simulation time 226757262 ps
CPU time 0.91 seconds
Started Jun 24 05:20:59 PM PDT 24
Finished Jun 24 05:21:04 PM PDT 24
Peak memory 206064 kb
Host smart-68c0f2bf-e354-431b-854f-76ac3e40b69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54082
555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.54082555
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.192059014
Short name T2412
Test name
Test status
Simulation time 165382868 ps
CPU time 0.81 seconds
Started Jun 24 05:20:56 PM PDT 24
Finished Jun 24 05:21:02 PM PDT 24
Peak memory 206172 kb
Host smart-e7e316f2-5093-4f75-a50c-393103d1e6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19205
9014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.192059014
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.804401731
Short name T779
Test name
Test status
Simulation time 157301334 ps
CPU time 0.79 seconds
Started Jun 24 05:20:56 PM PDT 24
Finished Jun 24 05:21:01 PM PDT 24
Peak memory 206180 kb
Host smart-4f312f62-2b3f-440d-99ff-460638a28bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80440
1731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.804401731
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.3862476307
Short name T75
Test name
Test status
Simulation time 242997359 ps
CPU time 0.87 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:21:00 PM PDT 24
Peak memory 206180 kb
Host smart-a96c8bde-ec62-4ca8-8d60-58e716dc6a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38624
76307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.3862476307
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1560228908
Short name T201
Test name
Test status
Simulation time 2595781360 ps
CPU time 3.16 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:21:03 PM PDT 24
Peak memory 224996 kb
Host smart-3f151e4f-08fe-4d9b-8293-c26f0d6982b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1560228908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1560228908
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.4119323500
Short name T1727
Test name
Test status
Simulation time 456839423 ps
CPU time 1.32 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:21:00 PM PDT 24
Peak memory 206188 kb
Host smart-e49c4b9f-69ff-4346-86ce-ba940d3f8f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41193
23500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.4119323500
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3709317077
Short name T2251
Test name
Test status
Simulation time 174038769 ps
CPU time 0.78 seconds
Started Jun 24 05:20:56 PM PDT 24
Finished Jun 24 05:21:01 PM PDT 24
Peak memory 206196 kb
Host smart-3f11c470-b712-45da-bfca-9069f2f41a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37093
17077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3709317077
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2995918839
Short name T703
Test name
Test status
Simulation time 178751987 ps
CPU time 0.84 seconds
Started Jun 24 05:20:59 PM PDT 24
Finished Jun 24 05:21:04 PM PDT 24
Peak memory 206060 kb
Host smart-4b2696d6-7a7a-4e84-839c-206376f012bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29959
18839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2995918839
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.566056060
Short name T839
Test name
Test status
Simulation time 219985010 ps
CPU time 1.06 seconds
Started Jun 24 05:20:57 PM PDT 24
Finished Jun 24 05:21:02 PM PDT 24
Peak memory 206180 kb
Host smart-a97b023c-cb15-4c8d-abc7-f7611711369a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56605
6060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.566056060
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.4039760511
Short name T2307
Test name
Test status
Simulation time 9412502344 ps
CPU time 272.46 seconds
Started Jun 24 05:20:54 PM PDT 24
Finished Jun 24 05:25:28 PM PDT 24
Peak memory 206396 kb
Host smart-3219d77d-becb-43cd-97a7-67169992eb3b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4039760511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.4039760511
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.2302436256
Short name T1717
Test name
Test status
Simulation time 235574765 ps
CPU time 0.93 seconds
Started Jun 24 05:20:55 PM PDT 24
Finished Jun 24 05:21:00 PM PDT 24
Peak memory 206176 kb
Host smart-bb7c37fc-8298-468d-a0b1-c828f9c7d019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23024
36256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.2302436256
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3798960201
Short name T412
Test name
Test status
Simulation time 193717548 ps
CPU time 0.87 seconds
Started Jun 24 05:20:56 PM PDT 24
Finished Jun 24 05:21:01 PM PDT 24
Peak memory 206116 kb
Host smart-5c748ce3-d97c-4bc2-8c66-17f744a85390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37989
60201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3798960201
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.3469028736
Short name T1320
Test name
Test status
Simulation time 4451170306 ps
CPU time 43.5 seconds
Started Jun 24 05:20:57 PM PDT 24
Finished Jun 24 05:21:45 PM PDT 24
Peak memory 206336 kb
Host smart-cbfb7c01-9d96-44ad-95dc-37b152d61e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34690
28736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.3469028736
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.1169553140
Short name T2516
Test name
Test status
Simulation time 14748982802 ps
CPU time 87.68 seconds
Started Jun 24 05:20:58 PM PDT 24
Finished Jun 24 05:22:30 PM PDT 24
Peak memory 206320 kb
Host smart-9271931c-d2ac-4fa0-8663-90da257e3b6a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1169553140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.1169553140
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.3031452343
Short name T1611
Test name
Test status
Simulation time 3463792168 ps
CPU time 4.1 seconds
Started Jun 24 05:26:41 PM PDT 24
Finished Jun 24 05:26:46 PM PDT 24
Peak memory 206240 kb
Host smart-e73b1328-1bc4-4c5c-8003-b2543e7c03da
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3031452343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.3031452343
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.3704877408
Short name T575
Test name
Test status
Simulation time 13343494657 ps
CPU time 13.03 seconds
Started Jun 24 05:26:43 PM PDT 24
Finished Jun 24 05:26:58 PM PDT 24
Peak memory 206280 kb
Host smart-0243f8c1-73ec-4aaa-a579-a512e170c09b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3704877408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.3704877408
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.1201475676
Short name T1150
Test name
Test status
Simulation time 23319254383 ps
CPU time 29.84 seconds
Started Jun 24 05:26:42 PM PDT 24
Finished Jun 24 05:27:14 PM PDT 24
Peak memory 206244 kb
Host smart-7bba417b-87b8-4476-8713-1524ad21d6bc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1201475676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.1201475676
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1676372295
Short name T1885
Test name
Test status
Simulation time 155523410 ps
CPU time 0.8 seconds
Started Jun 24 05:26:42 PM PDT 24
Finished Jun 24 05:26:45 PM PDT 24
Peak memory 206180 kb
Host smart-57a661c6-ff3c-4f6d-9fdf-dad119a7c42b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16763
72295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1676372295
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.3837370441
Short name T678
Test name
Test status
Simulation time 155537860 ps
CPU time 0.76 seconds
Started Jun 24 05:26:42 PM PDT 24
Finished Jun 24 05:26:44 PM PDT 24
Peak memory 206176 kb
Host smart-62559bf9-78d5-47e3-a720-478793e9c7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38373
70441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.3837370441
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.4079118011
Short name T1881
Test name
Test status
Simulation time 231841145 ps
CPU time 0.94 seconds
Started Jun 24 05:26:42 PM PDT 24
Finished Jun 24 05:26:45 PM PDT 24
Peak memory 206152 kb
Host smart-dc0ee3ef-6e34-4630-84f2-2729f213546c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40791
18011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.4079118011
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.682120388
Short name T1072
Test name
Test status
Simulation time 1028604470 ps
CPU time 2.65 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:26:49 PM PDT 24
Peak memory 206176 kb
Host smart-61c7f0cb-f47b-43a8-b34b-05768c5795ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68212
0388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.682120388
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.818232135
Short name T1555
Test name
Test status
Simulation time 9818481986 ps
CPU time 21.02 seconds
Started Jun 24 05:26:42 PM PDT 24
Finished Jun 24 05:27:06 PM PDT 24
Peak memory 206352 kb
Host smart-bdc5d698-cd1a-440d-bf4c-01f0b744b909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81823
2135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.818232135
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.3993177051
Short name T564
Test name
Test status
Simulation time 463687739 ps
CPU time 1.32 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:26:48 PM PDT 24
Peak memory 206080 kb
Host smart-f20309f9-1578-48ad-9888-0372c8f81fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39931
77051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.3993177051
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.2415678775
Short name T1222
Test name
Test status
Simulation time 172678784 ps
CPU time 0.8 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:26:47 PM PDT 24
Peak memory 206164 kb
Host smart-3313c6e6-45cd-4f94-9067-dac485f916a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24156
78775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.2415678775
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.472125081
Short name T1904
Test name
Test status
Simulation time 71915344 ps
CPU time 0.71 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:26:47 PM PDT 24
Peak memory 206156 kb
Host smart-c189a1ec-a16c-4f01-a15e-0d215c0b4688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47212
5081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.472125081
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.4052870794
Short name T2079
Test name
Test status
Simulation time 882810168 ps
CPU time 2.19 seconds
Started Jun 24 05:26:43 PM PDT 24
Finished Jun 24 05:26:48 PM PDT 24
Peak memory 206192 kb
Host smart-4400fe1f-59d9-4d85-aa25-6fb0e0a04f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40528
70794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.4052870794
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2723798159
Short name T1646
Test name
Test status
Simulation time 387203703 ps
CPU time 2.33 seconds
Started Jun 24 05:26:41 PM PDT 24
Finished Jun 24 05:26:45 PM PDT 24
Peak memory 206244 kb
Host smart-1b0eb8b3-4e8d-4bab-a1c5-c9fd23b8f3a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27237
98159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2723798159
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1135159298
Short name T1356
Test name
Test status
Simulation time 184576176 ps
CPU time 0.88 seconds
Started Jun 24 05:26:55 PM PDT 24
Finished Jun 24 05:26:59 PM PDT 24
Peak memory 206172 kb
Host smart-b1c09ca1-bfd5-4b7c-a9b2-e7d8c294eb02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11351
59298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1135159298
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1814235583
Short name T496
Test name
Test status
Simulation time 136635031 ps
CPU time 0.75 seconds
Started Jun 24 05:26:51 PM PDT 24
Finished Jun 24 05:26:52 PM PDT 24
Peak memory 206192 kb
Host smart-50164746-8bcc-4ba0-8353-4ccb7b187920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18142
35583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1814235583
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1831635010
Short name T692
Test name
Test status
Simulation time 202488906 ps
CPU time 0.86 seconds
Started Jun 24 05:26:48 PM PDT 24
Finished Jun 24 05:26:50 PM PDT 24
Peak memory 205920 kb
Host smart-b77471aa-bc6f-41bd-9f61-88ca427871fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18316
35010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1831635010
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.1280565168
Short name T1994
Test name
Test status
Simulation time 248603289 ps
CPU time 0.88 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:26:47 PM PDT 24
Peak memory 206180 kb
Host smart-0a416890-cd16-40b1-aab8-75c0e3dbf33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12805
65168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1280565168
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.1195628685
Short name T1764
Test name
Test status
Simulation time 23343561419 ps
CPU time 22 seconds
Started Jun 24 05:26:41 PM PDT 24
Finished Jun 24 05:27:05 PM PDT 24
Peak memory 206228 kb
Host smart-87678e9c-bd96-4a50-bd11-d8c75358936c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11956
28685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.1195628685
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.229739083
Short name T1132
Test name
Test status
Simulation time 3285164005 ps
CPU time 3.63 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:26:50 PM PDT 24
Peak memory 206220 kb
Host smart-5c2eca24-8d50-4d81-94d7-d2652742b459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22973
9083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.229739083
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2593970546
Short name T1206
Test name
Test status
Simulation time 13649466696 ps
CPU time 398.98 seconds
Started Jun 24 05:26:41 PM PDT 24
Finished Jun 24 05:33:22 PM PDT 24
Peak memory 206396 kb
Host smart-ce1759a0-5223-4f94-a2f3-c27529ff61e1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2593970546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2593970546
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2641098380
Short name T1513
Test name
Test status
Simulation time 261545467 ps
CPU time 1.02 seconds
Started Jun 24 05:26:57 PM PDT 24
Finished Jun 24 05:27:01 PM PDT 24
Peak memory 206144 kb
Host smart-b2c7b141-c815-4920-82f4-6c4ee48e3ee5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2641098380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2641098380
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2646556402
Short name T2009
Test name
Test status
Simulation time 194601941 ps
CPU time 0.85 seconds
Started Jun 24 05:26:48 PM PDT 24
Finished Jun 24 05:26:50 PM PDT 24
Peak memory 206164 kb
Host smart-65723bec-3702-41e4-be43-1f63b88b0aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26465
56402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2646556402
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1144846203
Short name T5
Test name
Test status
Simulation time 7453385557 ps
CPU time 218.48 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:30:25 PM PDT 24
Peak memory 206296 kb
Host smart-3a3b2dd0-6721-44ef-be55-439d5a00b76b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11448
46203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1144846203
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.2550283519
Short name T1362
Test name
Test status
Simulation time 9553822825 ps
CPU time 270.7 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:31:17 PM PDT 24
Peak memory 206384 kb
Host smart-e0560ed9-367f-4052-a152-4d92acc518b2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2550283519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.2550283519
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3228020688
Short name T274
Test name
Test status
Simulation time 168878876 ps
CPU time 0.79 seconds
Started Jun 24 05:26:58 PM PDT 24
Finished Jun 24 05:27:02 PM PDT 24
Peak memory 206172 kb
Host smart-d4b2ecb6-f5a2-480c-a1e2-fddb5ea9f749
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3228020688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3228020688
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3506698937
Short name T2430
Test name
Test status
Simulation time 201086293 ps
CPU time 0.83 seconds
Started Jun 24 05:26:41 PM PDT 24
Finished Jun 24 05:26:43 PM PDT 24
Peak memory 206152 kb
Host smart-425e8690-26de-4876-bf0e-4ed53925a4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35066
98937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3506698937
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2826450885
Short name T1977
Test name
Test status
Simulation time 189177829 ps
CPU time 0.85 seconds
Started Jun 24 05:26:44 PM PDT 24
Finished Jun 24 05:26:47 PM PDT 24
Peak memory 206160 kb
Host smart-72a91126-179b-4533-8286-910a50371b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28264
50885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2826450885
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1916570344
Short name T594
Test name
Test status
Simulation time 222645076 ps
CPU time 0.87 seconds
Started Jun 24 05:26:42 PM PDT 24
Finished Jun 24 05:26:45 PM PDT 24
Peak memory 206168 kb
Host smart-09677ef2-5be9-40a7-b997-39e535aa1c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19165
70344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1916570344
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2713752030
Short name T1229
Test name
Test status
Simulation time 153131705 ps
CPU time 0.76 seconds
Started Jun 24 05:26:54 PM PDT 24
Finished Jun 24 05:26:58 PM PDT 24
Peak memory 206180 kb
Host smart-f237fb87-0a7a-43f9-b06e-4cc55e6a7053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27137
52030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2713752030
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3886079081
Short name T1530
Test name
Test status
Simulation time 185802041 ps
CPU time 0.97 seconds
Started Jun 24 05:26:53 PM PDT 24
Finished Jun 24 05:26:56 PM PDT 24
Peak memory 206156 kb
Host smart-b772ea98-3459-458b-b924-7a9bb49a50fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38860
79081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3886079081
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3872399773
Short name T729
Test name
Test status
Simulation time 164901220 ps
CPU time 0.91 seconds
Started Jun 24 05:26:56 PM PDT 24
Finished Jun 24 05:27:00 PM PDT 24
Peak memory 206168 kb
Host smart-63535844-e3d2-4643-aef8-5b3c97e22402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38723
99773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3872399773
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.1078176501
Short name T1015
Test name
Test status
Simulation time 217067658 ps
CPU time 1.04 seconds
Started Jun 24 05:26:52 PM PDT 24
Finished Jun 24 05:26:54 PM PDT 24
Peak memory 206060 kb
Host smart-7e561f86-be0b-486a-86bc-e7df85f6fe08
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1078176501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.1078176501
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.1032469927
Short name T757
Test name
Test status
Simulation time 146809104 ps
CPU time 0.75 seconds
Started Jun 24 05:26:53 PM PDT 24
Finished Jun 24 05:26:56 PM PDT 24
Peak memory 206408 kb
Host smart-81385046-8435-4a2f-ad51-68d74d11cf8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10324
69927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.1032469927
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1981722176
Short name T1475
Test name
Test status
Simulation time 56409540 ps
CPU time 0.68 seconds
Started Jun 24 05:26:52 PM PDT 24
Finished Jun 24 05:26:54 PM PDT 24
Peak memory 206184 kb
Host smart-7f9b4085-cb1d-49f8-9bee-73b19f4fcf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19817
22176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1981722176
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.977650000
Short name T1156
Test name
Test status
Simulation time 20466303683 ps
CPU time 44.69 seconds
Started Jun 24 05:26:55 PM PDT 24
Finished Jun 24 05:27:42 PM PDT 24
Peak memory 206412 kb
Host smart-dafc3697-4806-425c-867d-2b15b154ebfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97765
0000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.977650000
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.3096314494
Short name T711
Test name
Test status
Simulation time 197994671 ps
CPU time 0.88 seconds
Started Jun 24 05:26:52 PM PDT 24
Finished Jun 24 05:26:54 PM PDT 24
Peak memory 206172 kb
Host smart-736908d6-5fc2-49c2-ba6c-9a4490379fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30963
14494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3096314494
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2313684868
Short name T32
Test name
Test status
Simulation time 156833968 ps
CPU time 0.83 seconds
Started Jun 24 05:26:59 PM PDT 24
Finished Jun 24 05:27:03 PM PDT 24
Peak memory 206072 kb
Host smart-494bb62c-970d-46b9-9a4e-67b99a1a9158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23136
84868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2313684868
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.409032828
Short name T1932
Test name
Test status
Simulation time 185125504 ps
CPU time 0.81 seconds
Started Jun 24 05:26:56 PM PDT 24
Finished Jun 24 05:27:00 PM PDT 24
Peak memory 206196 kb
Host smart-be39ff60-8b4b-4987-a4ca-16f46015df90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40903
2828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.409032828
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1734027130
Short name T1534
Test name
Test status
Simulation time 262640529 ps
CPU time 0.99 seconds
Started Jun 24 05:26:54 PM PDT 24
Finished Jun 24 05:26:57 PM PDT 24
Peak memory 206124 kb
Host smart-145df5c3-7ef1-488d-892b-5d1d65cca39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17340
27130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1734027130
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.4213764496
Short name T1676
Test name
Test status
Simulation time 177103085 ps
CPU time 0.77 seconds
Started Jun 24 05:26:54 PM PDT 24
Finished Jun 24 05:26:56 PM PDT 24
Peak memory 206188 kb
Host smart-55b12700-5547-45ff-871b-528ae1595f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42137
64496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.4213764496
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.851274309
Short name T1223
Test name
Test status
Simulation time 178563535 ps
CPU time 0.82 seconds
Started Jun 24 05:26:55 PM PDT 24
Finished Jun 24 05:26:59 PM PDT 24
Peak memory 206168 kb
Host smart-807964f2-a61c-43ee-a62e-4f31604e317c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85127
4309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.851274309
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.4143278061
Short name T2340
Test name
Test status
Simulation time 153329761 ps
CPU time 0.79 seconds
Started Jun 24 05:26:51 PM PDT 24
Finished Jun 24 05:26:53 PM PDT 24
Peak memory 206172 kb
Host smart-38a0f909-5a3b-4d2a-ab18-aca38d6f3acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41432
78061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.4143278061
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.120551620
Short name T1991
Test name
Test status
Simulation time 285235102 ps
CPU time 1.01 seconds
Started Jun 24 05:26:56 PM PDT 24
Finished Jun 24 05:27:00 PM PDT 24
Peak memory 206148 kb
Host smart-a583fe33-71aa-4248-b1ea-d8da7ad93908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12055
1620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.120551620
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.3625105568
Short name T2052
Test name
Test status
Simulation time 10947597188 ps
CPU time 102.26 seconds
Started Jun 24 05:26:54 PM PDT 24
Finished Jun 24 05:28:38 PM PDT 24
Peak memory 206392 kb
Host smart-cdfad69c-cdd5-4336-8c50-f15cf6ca65bc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3625105568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.3625105568
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2566531836
Short name T2450
Test name
Test status
Simulation time 180234893 ps
CPU time 0.82 seconds
Started Jun 24 05:26:54 PM PDT 24
Finished Jun 24 05:26:58 PM PDT 24
Peak memory 206156 kb
Host smart-0ea121bc-5303-4f99-93a8-dbaffce08f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25665
31836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2566531836
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.3035261531
Short name T786
Test name
Test status
Simulation time 219719315 ps
CPU time 0.87 seconds
Started Jun 24 05:26:58 PM PDT 24
Finished Jun 24 05:27:01 PM PDT 24
Peak memory 206176 kb
Host smart-f0e8c2ad-f8b2-4f62-895e-482284e179e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30352
61531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.3035261531
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.2104517150
Short name T2300
Test name
Test status
Simulation time 5738930132 ps
CPU time 55.93 seconds
Started Jun 24 05:26:53 PM PDT 24
Finished Jun 24 05:27:51 PM PDT 24
Peak memory 206652 kb
Host smart-0b3db7ad-950b-4357-a742-a76ee87b6276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21045
17150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.2104517150
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.958009057
Short name T1474
Test name
Test status
Simulation time 3953851816 ps
CPU time 5.69 seconds
Started Jun 24 05:26:58 PM PDT 24
Finished Jun 24 05:27:07 PM PDT 24
Peak memory 206264 kb
Host smart-22380e96-08d8-47b8-94a1-1ec7b7ec3f35
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=958009057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.958009057
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.756245701
Short name T679
Test name
Test status
Simulation time 13339563781 ps
CPU time 13.26 seconds
Started Jun 24 05:26:56 PM PDT 24
Finished Jun 24 05:27:13 PM PDT 24
Peak memory 206324 kb
Host smart-60c33236-dbcd-422b-b93a-b6153a30a81a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=756245701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.756245701
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2574793495
Short name T2254
Test name
Test status
Simulation time 23326180139 ps
CPU time 22.26 seconds
Started Jun 24 05:26:58 PM PDT 24
Finished Jun 24 05:27:24 PM PDT 24
Peak memory 206376 kb
Host smart-03970a8b-f4e0-4278-b708-cec4b315f49f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2574793495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.2574793495
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.4209706555
Short name T633
Test name
Test status
Simulation time 152854532 ps
CPU time 0.82 seconds
Started Jun 24 05:26:58 PM PDT 24
Finished Jun 24 05:27:02 PM PDT 24
Peak memory 206128 kb
Host smart-2718d407-9c1b-4100-b708-4d5471e3984b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42097
06555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.4209706555
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.4055885293
Short name T1667
Test name
Test status
Simulation time 156102790 ps
CPU time 0.81 seconds
Started Jun 24 05:26:53 PM PDT 24
Finished Jun 24 05:26:56 PM PDT 24
Peak memory 206408 kb
Host smart-2149baba-2bee-44f0-a64a-7f28d8d64b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40558
85293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.4055885293
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.231617090
Short name T976
Test name
Test status
Simulation time 534481814 ps
CPU time 1.55 seconds
Started Jun 24 05:27:00 PM PDT 24
Finished Jun 24 05:27:04 PM PDT 24
Peak memory 206236 kb
Host smart-6742c80f-92c1-4047-82e0-68c83cfccbc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23161
7090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.231617090
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.3999146095
Short name T1140
Test name
Test status
Simulation time 628065021 ps
CPU time 1.61 seconds
Started Jun 24 05:26:53 PM PDT 24
Finished Jun 24 05:26:56 PM PDT 24
Peak memory 206176 kb
Host smart-d8a461ee-5518-438f-9ebe-7a702e0d9b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39991
46095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.3999146095
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.1190147106
Short name T2316
Test name
Test status
Simulation time 12325651666 ps
CPU time 23.1 seconds
Started Jun 24 05:26:58 PM PDT 24
Finished Jun 24 05:27:23 PM PDT 24
Peak memory 206300 kb
Host smart-a2c2bc05-898c-42f9-bef4-2b997e715585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11901
47106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.1190147106
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.3703328843
Short name T448
Test name
Test status
Simulation time 371652703 ps
CPU time 1.3 seconds
Started Jun 24 05:26:56 PM PDT 24
Finished Jun 24 05:27:00 PM PDT 24
Peak memory 206160 kb
Host smart-f5c4554d-a49f-46bc-8bc4-87342e747ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37033
28843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.3703328843
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.175611329
Short name T2008
Test name
Test status
Simulation time 141078270 ps
CPU time 0.8 seconds
Started Jun 24 05:26:53 PM PDT 24
Finished Jun 24 05:26:56 PM PDT 24
Peak memory 206344 kb
Host smart-8fb9e368-449c-4da6-b250-ca6127f8b9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17561
1329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.175611329
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3490439181
Short name T1944
Test name
Test status
Simulation time 40607303 ps
CPU time 0.66 seconds
Started Jun 24 05:26:54 PM PDT 24
Finished Jun 24 05:26:57 PM PDT 24
Peak memory 206168 kb
Host smart-48e8446e-e9e8-49a6-9055-aa084b31f449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34904
39181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3490439181
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.3293379126
Short name T346
Test name
Test status
Simulation time 950928545 ps
CPU time 2.27 seconds
Started Jun 24 05:26:53 PM PDT 24
Finished Jun 24 05:26:57 PM PDT 24
Peak memory 206252 kb
Host smart-27678df0-56fd-487f-a7f0-c3797a87c7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32933
79126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3293379126
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2710522946
Short name T1827
Test name
Test status
Simulation time 179167061 ps
CPU time 1.87 seconds
Started Jun 24 05:26:55 PM PDT 24
Finished Jun 24 05:27:00 PM PDT 24
Peak memory 206276 kb
Host smart-763f24b0-f662-4fd1-b756-4107a9f070d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27105
22946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2710522946
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3660252750
Short name T655
Test name
Test status
Simulation time 218701063 ps
CPU time 0.92 seconds
Started Jun 24 05:27:12 PM PDT 24
Finished Jun 24 05:27:15 PM PDT 24
Peak memory 206148 kb
Host smart-4411c06f-7ad9-450c-a5a4-cb27d67c6498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36602
52750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3660252750
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1249546919
Short name T1284
Test name
Test status
Simulation time 138870842 ps
CPU time 0.76 seconds
Started Jun 24 05:27:01 PM PDT 24
Finished Jun 24 05:27:04 PM PDT 24
Peak memory 206068 kb
Host smart-f29d5229-80a8-4b7f-8887-a57e2e0f63db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12495
46919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1249546919
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2173733580
Short name T1293
Test name
Test status
Simulation time 185756543 ps
CPU time 0.86 seconds
Started Jun 24 05:26:59 PM PDT 24
Finished Jun 24 05:27:03 PM PDT 24
Peak memory 206176 kb
Host smart-5a2f6001-5dbf-43e2-92bb-cdd42d6203b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21737
33580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2173733580
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.1296855244
Short name T108
Test name
Test status
Simulation time 215737338 ps
CPU time 0.84 seconds
Started Jun 24 05:26:53 PM PDT 24
Finished Jun 24 05:26:56 PM PDT 24
Peak memory 206116 kb
Host smart-4f6eccd2-24dd-492c-bf2e-742c6e60aec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12968
55244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.1296855244
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.3006000835
Short name T2023
Test name
Test status
Simulation time 23304503693 ps
CPU time 22.67 seconds
Started Jun 24 05:26:52 PM PDT 24
Finished Jun 24 05:27:16 PM PDT 24
Peak memory 206256 kb
Host smart-c7437dad-f826-4757-9a01-6edba4e6de63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30060
00835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3006000835
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2627004426
Short name T715
Test name
Test status
Simulation time 3293813584 ps
CPU time 4.08 seconds
Started Jun 24 05:26:56 PM PDT 24
Finished Jun 24 05:27:03 PM PDT 24
Peak memory 206156 kb
Host smart-95b5cb30-3276-45d6-a0b6-8b2db61c0cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26270
04426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2627004426
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.2821849702
Short name T1565
Test name
Test status
Simulation time 10496575247 ps
CPU time 293.01 seconds
Started Jun 24 05:26:54 PM PDT 24
Finished Jun 24 05:31:49 PM PDT 24
Peak memory 206396 kb
Host smart-6a7e233a-2460-4b12-8c58-4d639a0cbc8c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2821849702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.2821849702
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.3096212626
Short name T312
Test name
Test status
Simulation time 239706309 ps
CPU time 0.93 seconds
Started Jun 24 05:27:02 PM PDT 24
Finished Jun 24 05:27:05 PM PDT 24
Peak memory 206096 kb
Host smart-5e542d64-cbbe-4857-ac14-40e5e2992533
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3096212626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.3096212626
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.912565726
Short name T1267
Test name
Test status
Simulation time 237434225 ps
CPU time 0.95 seconds
Started Jun 24 05:26:52 PM PDT 24
Finished Jun 24 05:26:54 PM PDT 24
Peak memory 206120 kb
Host smart-d3c9215e-4920-4b58-bdae-1b245a305f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91256
5726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.912565726
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.261525768
Short name T1746
Test name
Test status
Simulation time 9442145352 ps
CPU time 272.14 seconds
Started Jun 24 05:26:55 PM PDT 24
Finished Jun 24 05:31:29 PM PDT 24
Peak memory 206360 kb
Host smart-b716fc57-0b67-4011-bc19-ed9bf801cdf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26152
5768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.261525768
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.3197604534
Short name T495
Test name
Test status
Simulation time 8619751521 ps
CPU time 84.06 seconds
Started Jun 24 05:26:56 PM PDT 24
Finished Jun 24 05:28:23 PM PDT 24
Peak memory 206344 kb
Host smart-a10005ae-7ecd-4e86-9ed5-b82427f22a59
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3197604534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.3197604534
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.2223382630
Short name T1113
Test name
Test status
Simulation time 161360971 ps
CPU time 0.81 seconds
Started Jun 24 05:27:08 PM PDT 24
Finished Jun 24 05:27:10 PM PDT 24
Peak memory 206180 kb
Host smart-5f7b1693-ea56-4e36-b52b-80eb61dbd613
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2223382630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.2223382630
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2876062986
Short name T769
Test name
Test status
Simulation time 173811563 ps
CPU time 0.84 seconds
Started Jun 24 05:26:54 PM PDT 24
Finished Jun 24 05:26:58 PM PDT 24
Peak memory 206136 kb
Host smart-8a028cff-23e3-473d-9bcd-a7984fe8aab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28760
62986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2876062986
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1208932818
Short name T2505
Test name
Test status
Simulation time 235624912 ps
CPU time 0.87 seconds
Started Jun 24 05:26:53 PM PDT 24
Finished Jun 24 05:26:55 PM PDT 24
Peak memory 206140 kb
Host smart-a5cc8df3-7ac7-4a5c-8df7-db2a78306faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12089
32818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1208932818
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1377121144
Short name T388
Test name
Test status
Simulation time 224762638 ps
CPU time 0.88 seconds
Started Jun 24 05:26:54 PM PDT 24
Finished Jun 24 05:26:57 PM PDT 24
Peak memory 206184 kb
Host smart-2e18ce42-4a8a-416a-8b33-c3cd76747411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13771
21144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1377121144
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2553689028
Short name T1346
Test name
Test status
Simulation time 208146561 ps
CPU time 0.82 seconds
Started Jun 24 05:26:53 PM PDT 24
Finished Jun 24 05:26:56 PM PDT 24
Peak memory 206132 kb
Host smart-6edb4431-12f0-438a-9581-f7aa791333dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25536
89028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2553689028
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2729507555
Short name T322
Test name
Test status
Simulation time 168893764 ps
CPU time 0.81 seconds
Started Jun 24 05:26:55 PM PDT 24
Finished Jun 24 05:26:59 PM PDT 24
Peak memory 206148 kb
Host smart-82f0207d-d047-41ba-b552-a9611bd44083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27295
07555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2729507555
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2345413943
Short name T1825
Test name
Test status
Simulation time 189696429 ps
CPU time 0.85 seconds
Started Jun 24 05:26:58 PM PDT 24
Finished Jun 24 05:27:02 PM PDT 24
Peak memory 206060 kb
Host smart-76310f99-04f9-40e3-8748-0fc630862647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23454
13943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2345413943
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.1745811181
Short name T2182
Test name
Test status
Simulation time 197330290 ps
CPU time 0.94 seconds
Started Jun 24 05:26:54 PM PDT 24
Finished Jun 24 05:26:57 PM PDT 24
Peak memory 206176 kb
Host smart-b551add4-cb6d-458a-b638-06f6f9a8def9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1745811181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.1745811181
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3397973039
Short name T1662
Test name
Test status
Simulation time 178273366 ps
CPU time 0.78 seconds
Started Jun 24 05:26:54 PM PDT 24
Finished Jun 24 05:26:57 PM PDT 24
Peak memory 206176 kb
Host smart-ae1da8c0-baf2-4583-addc-7853a6f69bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33979
73039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3397973039
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2446648397
Short name T961
Test name
Test status
Simulation time 48042691 ps
CPU time 0.69 seconds
Started Jun 24 05:27:04 PM PDT 24
Finished Jun 24 05:27:06 PM PDT 24
Peak memory 206344 kb
Host smart-9266c12b-1ba0-4e5d-ac66-ff947c418aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24466
48397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2446648397
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.2570360220
Short name T94
Test name
Test status
Simulation time 13369797219 ps
CPU time 34.57 seconds
Started Jun 24 05:26:58 PM PDT 24
Finished Jun 24 05:27:36 PM PDT 24
Peak memory 206404 kb
Host smart-3c0a4c8d-a13e-4095-a630-7c46b4ae582b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25703
60220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2570360220
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.881422290
Short name T682
Test name
Test status
Simulation time 178833784 ps
CPU time 0.84 seconds
Started Jun 24 05:26:55 PM PDT 24
Finished Jun 24 05:26:59 PM PDT 24
Peak memory 206180 kb
Host smart-fb4eb374-3742-4864-a1ce-1173384d214b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88142
2290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.881422290
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2621336013
Short name T2444
Test name
Test status
Simulation time 197371325 ps
CPU time 0.94 seconds
Started Jun 24 05:26:56 PM PDT 24
Finished Jun 24 05:27:00 PM PDT 24
Peak memory 206184 kb
Host smart-dfd145f2-e3b7-494d-a041-13d8bb010643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26213
36013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2621336013
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.1399152009
Short name T454
Test name
Test status
Simulation time 209020013 ps
CPU time 0.85 seconds
Started Jun 24 05:27:02 PM PDT 24
Finished Jun 24 05:27:05 PM PDT 24
Peak memory 206200 kb
Host smart-07829011-bdb9-45de-adeb-8dd5930e827d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13991
52009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.1399152009
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.2625145650
Short name T1744
Test name
Test status
Simulation time 162906050 ps
CPU time 0.83 seconds
Started Jun 24 05:26:55 PM PDT 24
Finished Jun 24 05:26:59 PM PDT 24
Peak memory 206116 kb
Host smart-c44784c7-d6c1-42ce-8c7f-4b3c44eebedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26251
45650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.2625145650
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1753747575
Short name T2517
Test name
Test status
Simulation time 144533117 ps
CPU time 0.76 seconds
Started Jun 24 05:26:58 PM PDT 24
Finished Jun 24 05:27:02 PM PDT 24
Peak memory 206140 kb
Host smart-785a4ec9-5213-4b4c-8f3c-4dbf247fc5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17537
47575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1753747575
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.285656815
Short name T1721
Test name
Test status
Simulation time 152132030 ps
CPU time 0.83 seconds
Started Jun 24 05:26:58 PM PDT 24
Finished Jun 24 05:27:02 PM PDT 24
Peak memory 205716 kb
Host smart-402e527d-41db-4d90-a686-72217aac7021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28565
6815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.285656815
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.1607252261
Short name T1984
Test name
Test status
Simulation time 190873454 ps
CPU time 0.86 seconds
Started Jun 24 05:26:58 PM PDT 24
Finished Jun 24 05:27:02 PM PDT 24
Peak memory 205620 kb
Host smart-1d6cb7df-e296-4565-a79e-3e73b05c8d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16072
52261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.1607252261
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2988455619
Short name T1725
Test name
Test status
Simulation time 212578986 ps
CPU time 1.01 seconds
Started Jun 24 05:26:55 PM PDT 24
Finished Jun 24 05:26:59 PM PDT 24
Peak memory 206116 kb
Host smart-b825cff7-20cc-4fc1-b98a-78f2c8791784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29884
55619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2988455619
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3541257518
Short name T1103
Test name
Test status
Simulation time 7276943232 ps
CPU time 52.1 seconds
Started Jun 24 05:26:59 PM PDT 24
Finished Jun 24 05:27:54 PM PDT 24
Peak memory 206224 kb
Host smart-e275c37b-2ec0-4ca2-9d49-48451551865a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3541257518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3541257518
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.979951212
Short name T154
Test name
Test status
Simulation time 184789222 ps
CPU time 0.81 seconds
Started Jun 24 05:26:58 PM PDT 24
Finished Jun 24 05:27:01 PM PDT 24
Peak memory 206176 kb
Host smart-e535f3ad-fc3f-4308-9376-77733a536805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97995
1212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.979951212
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.299110487
Short name T794
Test name
Test status
Simulation time 185657397 ps
CPU time 0.83 seconds
Started Jun 24 05:26:59 PM PDT 24
Finished Jun 24 05:27:03 PM PDT 24
Peak memory 206072 kb
Host smart-7f04c9b4-9566-4970-8c39-b417b48ac71e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29911
0487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.299110487
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.3443385649
Short name T1733
Test name
Test status
Simulation time 11833777346 ps
CPU time 325.57 seconds
Started Jun 24 05:26:59 PM PDT 24
Finished Jun 24 05:32:27 PM PDT 24
Peak memory 206268 kb
Host smart-e6fc8c8a-a1da-4431-8e2f-5333dc3c2ab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34433
85649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.3443385649
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.1739811436
Short name T1009
Test name
Test status
Simulation time 3615743598 ps
CPU time 4.12 seconds
Started Jun 24 05:27:04 PM PDT 24
Finished Jun 24 05:27:10 PM PDT 24
Peak memory 206236 kb
Host smart-9b89b662-cb7b-404a-853f-ada2a6bfd67f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1739811436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.1739811436
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.1449386879
Short name T1952
Test name
Test status
Simulation time 13308532226 ps
CPU time 12.69 seconds
Started Jun 24 05:27:07 PM PDT 24
Finished Jun 24 05:27:21 PM PDT 24
Peak memory 206200 kb
Host smart-da0ebbe4-21c0-445d-ba9c-d6f5667be427
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1449386879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.1449386879
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.375509087
Short name T13
Test name
Test status
Simulation time 23336260364 ps
CPU time 22.45 seconds
Started Jun 24 05:27:12 PM PDT 24
Finished Jun 24 05:27:37 PM PDT 24
Peak memory 206292 kb
Host smart-70a65b17-1b6b-40bd-a6c9-35a615d012d7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=375509087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.375509087
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2609865367
Short name T1622
Test name
Test status
Simulation time 162721687 ps
CPU time 0.8 seconds
Started Jun 24 05:27:04 PM PDT 24
Finished Jun 24 05:27:07 PM PDT 24
Peak memory 206180 kb
Host smart-09e08bd4-5047-4e6f-8321-2e5c6aec04af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26098
65367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2609865367
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.1886600545
Short name T925
Test name
Test status
Simulation time 153396943 ps
CPU time 0.78 seconds
Started Jun 24 05:27:07 PM PDT 24
Finished Jun 24 05:27:08 PM PDT 24
Peak memory 206144 kb
Host smart-9092a44f-e866-4534-9128-04e1ad7af3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18866
00545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.1886600545
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.3312976748
Short name T1647
Test name
Test status
Simulation time 561934701 ps
CPU time 1.63 seconds
Started Jun 24 05:27:05 PM PDT 24
Finished Jun 24 05:27:08 PM PDT 24
Peak memory 206308 kb
Host smart-8e5d35ff-9160-496a-9a97-a7aaa780170f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33129
76748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.3312976748
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1484474246
Short name T2436
Test name
Test status
Simulation time 307532005 ps
CPU time 1.04 seconds
Started Jun 24 05:27:03 PM PDT 24
Finished Jun 24 05:27:06 PM PDT 24
Peak memory 206420 kb
Host smart-3fdb5668-45b9-4378-bb92-b73240ef1e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14844
74246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1484474246
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.870520825
Short name T2055
Test name
Test status
Simulation time 12984959856 ps
CPU time 21.81 seconds
Started Jun 24 05:27:07 PM PDT 24
Finished Jun 24 05:27:30 PM PDT 24
Peak memory 206348 kb
Host smart-44625f70-1cff-43ab-a1b5-22889815a241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87052
0825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.870520825
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.4255471751
Short name T2209
Test name
Test status
Simulation time 375164132 ps
CPU time 1.13 seconds
Started Jun 24 05:27:07 PM PDT 24
Finished Jun 24 05:27:09 PM PDT 24
Peak memory 206152 kb
Host smart-9fe13c53-3854-440b-977d-928d4c4c2b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42554
71751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.4255471751
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3953482705
Short name T1155
Test name
Test status
Simulation time 221930793 ps
CPU time 0.8 seconds
Started Jun 24 05:27:04 PM PDT 24
Finished Jun 24 05:27:07 PM PDT 24
Peak memory 206172 kb
Host smart-b5f99b6e-9760-40c4-8bb2-3cc268b67fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39534
82705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3953482705
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.3468718252
Short name T467
Test name
Test status
Simulation time 37147986 ps
CPU time 0.68 seconds
Started Jun 24 05:27:04 PM PDT 24
Finished Jun 24 05:27:06 PM PDT 24
Peak memory 206168 kb
Host smart-612ff7ad-80fe-4a62-b42a-6e7cf631e1b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34687
18252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.3468718252
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.1532061007
Short name T1411
Test name
Test status
Simulation time 875786803 ps
CPU time 2.08 seconds
Started Jun 24 05:27:05 PM PDT 24
Finished Jun 24 05:27:09 PM PDT 24
Peak memory 206236 kb
Host smart-f44105d7-8df8-4470-829c-a6d18595ad01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15320
61007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.1532061007
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3887712166
Short name T1012
Test name
Test status
Simulation time 237230011 ps
CPU time 1.36 seconds
Started Jun 24 05:27:03 PM PDT 24
Finished Jun 24 05:27:07 PM PDT 24
Peak memory 206196 kb
Host smart-cbfeb068-d06f-4e19-9e48-eb0b2940a46d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38877
12166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3887712166
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.841038785
Short name T2034
Test name
Test status
Simulation time 239799085 ps
CPU time 0.94 seconds
Started Jun 24 05:27:16 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206148 kb
Host smart-e8dd8d91-c1f4-499a-8298-d026512590d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84103
8785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.841038785
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1964278042
Short name T719
Test name
Test status
Simulation time 164617808 ps
CPU time 0.82 seconds
Started Jun 24 05:27:15 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206168 kb
Host smart-047f9fba-c5bf-42bc-9f60-c7e14589fc8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19642
78042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1964278042
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.267292943
Short name T1538
Test name
Test status
Simulation time 283257859 ps
CPU time 0.92 seconds
Started Jun 24 05:27:03 PM PDT 24
Finished Jun 24 05:27:06 PM PDT 24
Peak memory 206168 kb
Host smart-ef150e52-1bf6-42e1-961c-99bbef7e22ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26729
2943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.267292943
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3523970977
Short name T731
Test name
Test status
Simulation time 251218272 ps
CPU time 0.97 seconds
Started Jun 24 05:27:05 PM PDT 24
Finished Jun 24 05:27:08 PM PDT 24
Peak memory 206192 kb
Host smart-40a70e28-0fe4-4b14-92af-56c56636695f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35239
70977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3523970977
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1609676198
Short name T2275
Test name
Test status
Simulation time 23338437579 ps
CPU time 21.36 seconds
Started Jun 24 05:27:04 PM PDT 24
Finished Jun 24 05:27:27 PM PDT 24
Peak memory 206244 kb
Host smart-f03d40b3-a2e4-4eab-a721-ed116ceb298a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16096
76198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1609676198
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.4030607132
Short name T583
Test name
Test status
Simulation time 3297377306 ps
CPU time 3.84 seconds
Started Jun 24 05:27:03 PM PDT 24
Finished Jun 24 05:27:09 PM PDT 24
Peak memory 206240 kb
Host smart-32e977d4-a905-48c2-85cc-ac0ce654117c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40306
07132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.4030607132
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.2240047155
Short name T1989
Test name
Test status
Simulation time 12263346614 ps
CPU time 122.62 seconds
Started Jun 24 05:27:02 PM PDT 24
Finished Jun 24 05:29:07 PM PDT 24
Peak memory 206396 kb
Host smart-5e89b320-a287-4935-99fe-5854b20cc0bd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2240047155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.2240047155
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.1951184103
Short name T739
Test name
Test status
Simulation time 271710184 ps
CPU time 0.95 seconds
Started Jun 24 05:27:16 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206144 kb
Host smart-693ad06f-c59b-4bc3-99e5-e1de0067d0dc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1951184103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.1951184103
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3008372191
Short name T1141
Test name
Test status
Simulation time 203298481 ps
CPU time 0.88 seconds
Started Jun 24 05:27:04 PM PDT 24
Finished Jun 24 05:27:07 PM PDT 24
Peak memory 206172 kb
Host smart-15b2ceff-b3bd-4a91-a071-083011ecc8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30083
72191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3008372191
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.1609510882
Short name T2186
Test name
Test status
Simulation time 4671204555 ps
CPU time 131.64 seconds
Started Jun 24 05:27:12 PM PDT 24
Finished Jun 24 05:29:26 PM PDT 24
Peak memory 206128 kb
Host smart-ed772a46-cc1c-4576-ad14-5335368b8b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16095
10882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.1609510882
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3104235839
Short name T1008
Test name
Test status
Simulation time 3255849026 ps
CPU time 91.2 seconds
Started Jun 24 05:27:12 PM PDT 24
Finished Jun 24 05:28:45 PM PDT 24
Peak memory 206396 kb
Host smart-41656e80-acae-45c3-9db7-331bb4514906
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3104235839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3104235839
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.560541582
Short name T1573
Test name
Test status
Simulation time 163542538 ps
CPU time 0.78 seconds
Started Jun 24 05:27:12 PM PDT 24
Finished Jun 24 05:27:15 PM PDT 24
Peak memory 206192 kb
Host smart-118d8314-2bd4-4c1d-9d89-ce582c861800
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=560541582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.560541582
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.824790832
Short name T984
Test name
Test status
Simulation time 182355161 ps
CPU time 0.82 seconds
Started Jun 24 05:27:03 PM PDT 24
Finished Jun 24 05:27:06 PM PDT 24
Peak memory 206196 kb
Host smart-98115ef8-d1f3-48f7-a41f-4e073868b2a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82479
0832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.824790832
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3369866474
Short name T131
Test name
Test status
Simulation time 243001488 ps
CPU time 0.89 seconds
Started Jun 24 05:27:11 PM PDT 24
Finished Jun 24 05:27:13 PM PDT 24
Peak memory 206180 kb
Host smart-7900d50e-8a7e-4a54-86e8-deead08d204e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33698
66474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3369866474
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.3232065895
Short name T20
Test name
Test status
Simulation time 245866890 ps
CPU time 0.85 seconds
Started Jun 24 05:27:07 PM PDT 24
Finished Jun 24 05:27:09 PM PDT 24
Peak memory 206164 kb
Host smart-edbc18cd-eead-41ac-bbd5-87fcc7e6692d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32320
65895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.3232065895
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2354655117
Short name T334
Test name
Test status
Simulation time 179159943 ps
CPU time 0.83 seconds
Started Jun 24 05:27:02 PM PDT 24
Finished Jun 24 05:27:05 PM PDT 24
Peak memory 206184 kb
Host smart-63e9664d-f303-405e-9a0d-a10f464399e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23546
55117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2354655117
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1402332005
Short name T1340
Test name
Test status
Simulation time 165682928 ps
CPU time 0.78 seconds
Started Jun 24 05:27:05 PM PDT 24
Finished Jun 24 05:27:08 PM PDT 24
Peak memory 206176 kb
Host smart-fc21b48d-5169-45fe-bb42-408ca8bc0be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14023
32005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1402332005
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2860321136
Short name T1280
Test name
Test status
Simulation time 158854552 ps
CPU time 0.79 seconds
Started Jun 24 05:27:14 PM PDT 24
Finished Jun 24 05:27:19 PM PDT 24
Peak memory 206176 kb
Host smart-16cc0cd1-d535-4a17-ab93-a4f446ac9767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28603
21136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2860321136
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.4150239882
Short name T1939
Test name
Test status
Simulation time 220157325 ps
CPU time 0.95 seconds
Started Jun 24 05:27:02 PM PDT 24
Finished Jun 24 05:27:05 PM PDT 24
Peak memory 206176 kb
Host smart-901933e1-e48d-4835-a19a-f83dbee07b79
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4150239882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.4150239882
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1393069191
Short name T665
Test name
Test status
Simulation time 142503331 ps
CPU time 0.73 seconds
Started Jun 24 05:27:06 PM PDT 24
Finished Jun 24 05:27:08 PM PDT 24
Peak memory 206148 kb
Host smart-94cc5700-9992-4791-b2c9-a311562b7689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13930
69191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1393069191
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2434710169
Short name T2238
Test name
Test status
Simulation time 56258719 ps
CPU time 0.7 seconds
Started Jun 24 05:27:16 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206164 kb
Host smart-3715ac75-9611-42cf-b9f4-d6607c3d8c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24347
10169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2434710169
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.228185504
Short name T2081
Test name
Test status
Simulation time 8637129822 ps
CPU time 18.18 seconds
Started Jun 24 05:27:01 PM PDT 24
Finished Jun 24 05:27:22 PM PDT 24
Peak memory 206384 kb
Host smart-24109538-cb80-4f16-968b-986c34972629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22818
5504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.228185504
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2066921109
Short name T2429
Test name
Test status
Simulation time 186880636 ps
CPU time 0.85 seconds
Started Jun 24 05:27:07 PM PDT 24
Finished Jun 24 05:27:10 PM PDT 24
Peak memory 206176 kb
Host smart-062f401b-dd5c-4bc1-9338-e4112c1eb71f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20669
21109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2066921109
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.764495854
Short name T1137
Test name
Test status
Simulation time 236742666 ps
CPU time 0.92 seconds
Started Jun 24 05:27:08 PM PDT 24
Finished Jun 24 05:27:10 PM PDT 24
Peak memory 206188 kb
Host smart-c0cf6db4-d5c0-4b37-8ea5-c5ef4c6ced7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76449
5854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.764495854
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.745484259
Short name T1453
Test name
Test status
Simulation time 177279721 ps
CPU time 0.84 seconds
Started Jun 24 05:27:14 PM PDT 24
Finished Jun 24 05:27:18 PM PDT 24
Peak memory 206192 kb
Host smart-4a6ef9a1-8152-4c7f-a882-b01234b5ac9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74548
4259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.745484259
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.114508256
Short name T1265
Test name
Test status
Simulation time 175803247 ps
CPU time 0.87 seconds
Started Jun 24 05:27:03 PM PDT 24
Finished Jun 24 05:27:06 PM PDT 24
Peak memory 206128 kb
Host smart-29b74d5a-e94e-44cb-9dc0-7e6709ce958a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11450
8256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.114508256
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1187733267
Short name T1659
Test name
Test status
Simulation time 179092788 ps
CPU time 0.8 seconds
Started Jun 24 05:27:07 PM PDT 24
Finished Jun 24 05:27:10 PM PDT 24
Peak memory 206168 kb
Host smart-190abe58-513f-44f4-acf3-b730f7cc02cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11877
33267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1187733267
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.1589802164
Short name T1842
Test name
Test status
Simulation time 175336446 ps
CPU time 0.79 seconds
Started Jun 24 05:27:11 PM PDT 24
Finished Jun 24 05:27:14 PM PDT 24
Peak memory 206164 kb
Host smart-9ca7085b-6d8e-476d-bf23-3926fbc1508f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15898
02164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.1589802164
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3823577311
Short name T890
Test name
Test status
Simulation time 151707007 ps
CPU time 0.85 seconds
Started Jun 24 05:27:16 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206172 kb
Host smart-309d697d-597b-429f-aa41-51852b8ad0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38235
77311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3823577311
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2545757328
Short name T159
Test name
Test status
Simulation time 213323720 ps
CPU time 0.98 seconds
Started Jun 24 05:27:12 PM PDT 24
Finished Jun 24 05:27:15 PM PDT 24
Peak memory 206192 kb
Host smart-bac15539-1946-4ae3-8b74-8c465c3b41f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25457
57328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2545757328
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.593864977
Short name T1426
Test name
Test status
Simulation time 11104256167 ps
CPU time 79.6 seconds
Started Jun 24 05:27:12 PM PDT 24
Finished Jun 24 05:28:34 PM PDT 24
Peak memory 205952 kb
Host smart-fc406f2e-1624-457c-bf43-d06ebc1392f4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=593864977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.593864977
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.377930319
Short name T153
Test name
Test status
Simulation time 171292752 ps
CPU time 0.82 seconds
Started Jun 24 05:27:15 PM PDT 24
Finished Jun 24 05:27:19 PM PDT 24
Peak memory 206156 kb
Host smart-5ee4388d-a260-4414-a14f-5d4281905e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37793
0319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.377930319
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.45940993
Short name T1571
Test name
Test status
Simulation time 154843703 ps
CPU time 0.79 seconds
Started Jun 24 05:27:07 PM PDT 24
Finished Jun 24 05:27:10 PM PDT 24
Peak memory 206164 kb
Host smart-97072ce6-dec9-40f3-b5af-7884447dfbb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45940
993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.45940993
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2039412630
Short name T607
Test name
Test status
Simulation time 4323735235 ps
CPU time 28.91 seconds
Started Jun 24 05:27:14 PM PDT 24
Finished Jun 24 05:27:47 PM PDT 24
Peak memory 206400 kb
Host smart-dcc6424b-4899-4448-816b-52dd9eb030f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20394
12630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2039412630
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.1449212974
Short name T701
Test name
Test status
Simulation time 3562191869 ps
CPU time 3.94 seconds
Started Jun 24 05:27:14 PM PDT 24
Finished Jun 24 05:27:22 PM PDT 24
Peak memory 206240 kb
Host smart-71cae784-c26f-4f84-9fad-dc97909a6ce1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1449212974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.1449212974
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.3425956946
Short name T1022
Test name
Test status
Simulation time 13375505605 ps
CPU time 11.82 seconds
Started Jun 24 05:27:11 PM PDT 24
Finished Jun 24 05:27:23 PM PDT 24
Peak memory 206292 kb
Host smart-fa20c155-ec6c-4841-9a85-bbbf669fc24a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3425956946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.3425956946
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.4111020243
Short name T1554
Test name
Test status
Simulation time 23314478005 ps
CPU time 23.18 seconds
Started Jun 24 05:27:14 PM PDT 24
Finished Jun 24 05:27:41 PM PDT 24
Peak memory 206248 kb
Host smart-9eeece33-afef-4912-8da0-1be65fd18513
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4111020243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.4111020243
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2986075507
Short name T1673
Test name
Test status
Simulation time 157579656 ps
CPU time 0.85 seconds
Started Jun 24 05:27:14 PM PDT 24
Finished Jun 24 05:27:19 PM PDT 24
Peak memory 206184 kb
Host smart-9489ffe3-9ef3-46ce-a231-7c5903d6e845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29860
75507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2986075507
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.1680897275
Short name T2333
Test name
Test status
Simulation time 184829072 ps
CPU time 0.8 seconds
Started Jun 24 05:27:12 PM PDT 24
Finished Jun 24 05:27:16 PM PDT 24
Peak memory 206424 kb
Host smart-a20abfef-b877-4141-b4e7-70c4ccf1919c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16808
97275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.1680897275
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.3419851686
Short name T788
Test name
Test status
Simulation time 436347863 ps
CPU time 1.36 seconds
Started Jun 24 05:27:13 PM PDT 24
Finished Jun 24 05:27:19 PM PDT 24
Peak memory 206108 kb
Host smart-e5a3037b-ebdb-4337-9e6c-fc8c184bfa5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34198
51686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.3419851686
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.930468855
Short name T1855
Test name
Test status
Simulation time 1230176204 ps
CPU time 2.65 seconds
Started Jun 24 05:27:13 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206276 kb
Host smart-7fcbab28-ab56-4eac-8f24-67b0d79c3209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93046
8855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.930468855
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.2514104857
Short name T1303
Test name
Test status
Simulation time 15039477676 ps
CPU time 28.01 seconds
Started Jun 24 05:27:15 PM PDT 24
Finished Jun 24 05:27:46 PM PDT 24
Peak memory 206416 kb
Host smart-d7034a8c-cb65-42a7-a321-c5394b35a320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25141
04857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.2514104857
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.4292239253
Short name T1681
Test name
Test status
Simulation time 363928875 ps
CPU time 1.18 seconds
Started Jun 24 05:27:17 PM PDT 24
Finished Jun 24 05:27:21 PM PDT 24
Peak memory 206132 kb
Host smart-09a58bfa-d062-4b72-acce-f7fa9f8649c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42922
39253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.4292239253
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.1947053206
Short name T2001
Test name
Test status
Simulation time 200023240 ps
CPU time 0.8 seconds
Started Jun 24 05:27:16 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206144 kb
Host smart-00245fe0-2b07-43ff-934e-ed7f5f2646f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19470
53206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.1947053206
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3418843553
Short name T2083
Test name
Test status
Simulation time 60654078 ps
CPU time 0.65 seconds
Started Jun 24 05:27:15 PM PDT 24
Finished Jun 24 05:27:19 PM PDT 24
Peak memory 206168 kb
Host smart-9fcdf732-e0f3-43b9-9258-ee22ea317edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34188
43553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3418843553
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.203469498
Short name T1227
Test name
Test status
Simulation time 872718664 ps
CPU time 2.16 seconds
Started Jun 24 05:27:17 PM PDT 24
Finished Jun 24 05:27:22 PM PDT 24
Peak memory 206212 kb
Host smart-1b1408cf-1018-4a97-b891-5326de38d9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20346
9498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.203469498
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3361738189
Short name T1179
Test name
Test status
Simulation time 155674851 ps
CPU time 1.3 seconds
Started Jun 24 05:27:17 PM PDT 24
Finished Jun 24 05:27:21 PM PDT 24
Peak memory 206196 kb
Host smart-cb9ffd66-6306-4719-8544-a338c1fc5c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33617
38189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3361738189
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.358614207
Short name T582
Test name
Test status
Simulation time 269122061 ps
CPU time 0.94 seconds
Started Jun 24 05:27:14 PM PDT 24
Finished Jun 24 05:27:18 PM PDT 24
Peak memory 206168 kb
Host smart-49570958-7de3-49b4-8f37-d714cc2fe037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35861
4207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.358614207
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2868161486
Short name T2119
Test name
Test status
Simulation time 217798789 ps
CPU time 0.82 seconds
Started Jun 24 05:27:13 PM PDT 24
Finished Jun 24 05:27:16 PM PDT 24
Peak memory 206192 kb
Host smart-b628f151-ea10-404c-a858-077146b58cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28681
61486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2868161486
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1285993848
Short name T2418
Test name
Test status
Simulation time 228978954 ps
CPU time 0.92 seconds
Started Jun 24 05:27:16 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206172 kb
Host smart-7b2a052b-f3fa-43e5-ade6-b368ee3e7aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12859
93848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1285993848
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.1046042052
Short name T2217
Test name
Test status
Simulation time 205479630 ps
CPU time 0.85 seconds
Started Jun 24 05:27:16 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206192 kb
Host smart-fae9dd46-f927-4314-86ca-821f4766a9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10460
42052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.1046042052
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.200188738
Short name T841
Test name
Test status
Simulation time 23319263232 ps
CPU time 20.93 seconds
Started Jun 24 05:27:16 PM PDT 24
Finished Jun 24 05:27:40 PM PDT 24
Peak memory 206248 kb
Host smart-723fdc54-46a3-485f-8af6-27339f321d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20018
8738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.200188738
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1652920762
Short name T2350
Test name
Test status
Simulation time 3335114774 ps
CPU time 3.58 seconds
Started Jun 24 05:27:14 PM PDT 24
Finished Jun 24 05:27:21 PM PDT 24
Peak memory 206224 kb
Host smart-d3a7e7cd-5710-431a-bab0-065d7a6e18ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16529
20762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1652920762
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.58374535
Short name T761
Test name
Test status
Simulation time 7603147901 ps
CPU time 213.22 seconds
Started Jun 24 05:27:12 PM PDT 24
Finished Jun 24 05:30:49 PM PDT 24
Peak memory 206384 kb
Host smart-62054d76-d52c-4834-9d1d-2c55a8220951
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=58374535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.58374535
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.3619689185
Short name T1162
Test name
Test status
Simulation time 247023303 ps
CPU time 1 seconds
Started Jun 24 05:27:20 PM PDT 24
Finished Jun 24 05:27:22 PM PDT 24
Peak memory 206388 kb
Host smart-cf3592bc-981d-407c-8385-eecca3392726
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3619689185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.3619689185
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2705558368
Short name T305
Test name
Test status
Simulation time 187055209 ps
CPU time 0.93 seconds
Started Jun 24 05:27:14 PM PDT 24
Finished Jun 24 05:27:18 PM PDT 24
Peak memory 206112 kb
Host smart-fb62da31-dea4-4c84-af51-0f6e6c1fef39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27055
58368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2705558368
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.2589748160
Short name T2016
Test name
Test status
Simulation time 9061877298 ps
CPU time 66.16 seconds
Started Jun 24 05:27:16 PM PDT 24
Finished Jun 24 05:28:25 PM PDT 24
Peak memory 206396 kb
Host smart-4d910e04-b510-43de-8087-496d8c4ef135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25897
48160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.2589748160
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.1138648179
Short name T732
Test name
Test status
Simulation time 7479372227 ps
CPU time 54.7 seconds
Started Jun 24 05:27:12 PM PDT 24
Finished Jun 24 05:28:10 PM PDT 24
Peak memory 206376 kb
Host smart-f0fdd5b9-095a-4caf-9e96-215a42ef35c9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1138648179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.1138648179
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.3532942036
Short name T838
Test name
Test status
Simulation time 157679146 ps
CPU time 0.78 seconds
Started Jun 24 05:27:27 PM PDT 24
Finished Jun 24 05:27:30 PM PDT 24
Peak memory 206152 kb
Host smart-545db85c-9dd1-4636-bc1d-7b58f48f9810
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3532942036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.3532942036
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1942708681
Short name T755
Test name
Test status
Simulation time 156085492 ps
CPU time 0.77 seconds
Started Jun 24 05:27:16 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206076 kb
Host smart-4c78aa9e-c2a3-4711-897e-2222289c3739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19427
08681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1942708681
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.572637250
Short name T2115
Test name
Test status
Simulation time 199138521 ps
CPU time 0.86 seconds
Started Jun 24 05:27:15 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206076 kb
Host smart-335486b6-2d2f-4492-aa7b-c55535b7ef39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57263
7250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.572637250
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2020622725
Short name T1217
Test name
Test status
Simulation time 196286160 ps
CPU time 0.83 seconds
Started Jun 24 05:27:12 PM PDT 24
Finished Jun 24 05:27:16 PM PDT 24
Peak memory 206180 kb
Host smart-6994fb8b-fbc1-4338-ae12-573e5920c3c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20206
22725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2020622725
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.4026249600
Short name T1369
Test name
Test status
Simulation time 170720720 ps
CPU time 0.84 seconds
Started Jun 24 05:27:15 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206096 kb
Host smart-4b5e0734-d520-4c54-982b-f7f7ed46dc42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40262
49600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.4026249600
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3384314485
Short name T2039
Test name
Test status
Simulation time 155608385 ps
CPU time 0.83 seconds
Started Jun 24 05:27:16 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206128 kb
Host smart-86b9a1e5-a7c8-4794-9e35-ad838b67f238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33843
14485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3384314485
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3193068016
Short name T436
Test name
Test status
Simulation time 242700910 ps
CPU time 0.96 seconds
Started Jun 24 05:27:14 PM PDT 24
Finished Jun 24 05:27:18 PM PDT 24
Peak memory 206104 kb
Host smart-33c64963-7927-4cd5-ac54-0d1c75820c0b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3193068016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3193068016
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3103360739
Short name T381
Test name
Test status
Simulation time 148008294 ps
CPU time 0.75 seconds
Started Jun 24 05:27:13 PM PDT 24
Finished Jun 24 05:27:16 PM PDT 24
Peak memory 206176 kb
Host smart-2eb20c5a-3bac-4cee-8786-b848ebdeaab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31033
60739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3103360739
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.4149325154
Short name T1287
Test name
Test status
Simulation time 47861433 ps
CPU time 0.67 seconds
Started Jun 24 05:27:14 PM PDT 24
Finished Jun 24 05:27:18 PM PDT 24
Peak memory 206184 kb
Host smart-626b79af-6095-4a98-9288-a2bcca1e8a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41493
25154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.4149325154
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2550356525
Short name T255
Test name
Test status
Simulation time 19606663185 ps
CPU time 42.16 seconds
Started Jun 24 05:27:16 PM PDT 24
Finished Jun 24 05:28:01 PM PDT 24
Peak memory 206372 kb
Host smart-78f56dc8-52d3-4461-a69b-9b8d16663e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25503
56525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2550356525
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3725559724
Short name T518
Test name
Test status
Simulation time 161593258 ps
CPU time 0.85 seconds
Started Jun 24 05:27:13 PM PDT 24
Finished Jun 24 05:27:17 PM PDT 24
Peak memory 206092 kb
Host smart-09f6f2fd-e5e8-4c49-af12-e0b3caacd32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37255
59724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3725559724
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3489784130
Short name T802
Test name
Test status
Simulation time 209252589 ps
CPU time 0.92 seconds
Started Jun 24 05:27:17 PM PDT 24
Finished Jun 24 05:27:21 PM PDT 24
Peak memory 206092 kb
Host smart-5000535d-bcce-4435-9238-0bc88026ba16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34897
84130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3489784130
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.4135526011
Short name T696
Test name
Test status
Simulation time 189943180 ps
CPU time 0.84 seconds
Started Jun 24 05:27:23 PM PDT 24
Finished Jun 24 05:27:26 PM PDT 24
Peak memory 206212 kb
Host smart-fb9d9c80-6ccb-48c1-844a-2c4b2369bb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41355
26011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.4135526011
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2316722480
Short name T1529
Test name
Test status
Simulation time 192173346 ps
CPU time 0.83 seconds
Started Jun 24 05:27:11 PM PDT 24
Finished Jun 24 05:27:14 PM PDT 24
Peak memory 206096 kb
Host smart-17602a78-b448-4038-87bb-af304c40e4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23167
22480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2316722480
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.2891153811
Short name T2179
Test name
Test status
Simulation time 145787861 ps
CPU time 0.78 seconds
Started Jun 24 05:27:13 PM PDT 24
Finished Jun 24 05:27:16 PM PDT 24
Peak memory 206188 kb
Host smart-ec674997-289e-4646-8be0-966e548072fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28911
53811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.2891153811
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1758942257
Short name T1104
Test name
Test status
Simulation time 146780269 ps
CPU time 0.74 seconds
Started Jun 24 05:27:15 PM PDT 24
Finished Jun 24 05:27:20 PM PDT 24
Peak memory 206168 kb
Host smart-e309adda-20e6-4b7c-b2d3-cedd05a2b460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17589
42257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1758942257
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.109276424
Short name T648
Test name
Test status
Simulation time 148401732 ps
CPU time 0.78 seconds
Started Jun 24 05:27:14 PM PDT 24
Finished Jun 24 05:27:18 PM PDT 24
Peak memory 206096 kb
Host smart-3f17be9d-66bb-48ff-b54e-0b57f859815a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10927
6424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.109276424
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1489547364
Short name T2167
Test name
Test status
Simulation time 248646199 ps
CPU time 0.96 seconds
Started Jun 24 05:27:13 PM PDT 24
Finished Jun 24 05:27:17 PM PDT 24
Peak memory 206092 kb
Host smart-cf17189a-c66e-4f80-988a-0d2277dc5518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14895
47364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1489547364
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.2086639892
Short name T438
Test name
Test status
Simulation time 5966033197 ps
CPU time 56.96 seconds
Started Jun 24 05:27:13 PM PDT 24
Finished Jun 24 05:28:13 PM PDT 24
Peak memory 206392 kb
Host smart-d9e0cbd6-4a11-401d-84b0-6953029ce25d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2086639892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.2086639892
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1333575381
Short name T1607
Test name
Test status
Simulation time 158130362 ps
CPU time 0.79 seconds
Started Jun 24 05:27:17 PM PDT 24
Finished Jun 24 05:27:21 PM PDT 24
Peak memory 206116 kb
Host smart-d0a56b26-01a0-4c7f-9685-284f1f670439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13335
75381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1333575381
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2036765745
Short name T608
Test name
Test status
Simulation time 163217336 ps
CPU time 0.85 seconds
Started Jun 24 05:27:12 PM PDT 24
Finished Jun 24 05:27:15 PM PDT 24
Peak memory 206076 kb
Host smart-43780887-383c-457a-a06f-35d8f91cc1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20367
65745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2036765745
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.355114494
Short name T742
Test name
Test status
Simulation time 14590023420 ps
CPU time 426.88 seconds
Started Jun 24 05:27:12 PM PDT 24
Finished Jun 24 05:34:21 PM PDT 24
Peak memory 206388 kb
Host smart-54905bda-c121-4f08-9584-0c0b554dd7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35511
4494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.355114494
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2692151938
Short name T1998
Test name
Test status
Simulation time 4380210906 ps
CPU time 4.77 seconds
Started Jun 24 05:27:23 PM PDT 24
Finished Jun 24 05:27:29 PM PDT 24
Peak memory 206332 kb
Host smart-2d82bbd6-c35a-46fa-b715-42abba5bee77
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2692151938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.2692151938
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.3532437868
Short name T1174
Test name
Test status
Simulation time 13370650016 ps
CPU time 12.43 seconds
Started Jun 24 05:27:26 PM PDT 24
Finished Jun 24 05:27:40 PM PDT 24
Peak memory 206112 kb
Host smart-75824f37-2a67-4f40-b385-b8c8aa19a1c3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3532437868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.3532437868
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.30186750
Short name T1033
Test name
Test status
Simulation time 23401462695 ps
CPU time 23.15 seconds
Started Jun 24 05:27:25 PM PDT 24
Finished Jun 24 05:27:50 PM PDT 24
Peak memory 206244 kb
Host smart-748cbc2b-8078-45ab-9491-de14bd84ccb2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=30186750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.30186750
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.946938297
Short name T2463
Test name
Test status
Simulation time 188527127 ps
CPU time 0.93 seconds
Started Jun 24 05:27:21 PM PDT 24
Finished Jun 24 05:27:24 PM PDT 24
Peak memory 206176 kb
Host smart-cd9c73ea-a859-4cc0-9aea-912576390bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94693
8297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.946938297
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1170949598
Short name T1508
Test name
Test status
Simulation time 172183978 ps
CPU time 0.84 seconds
Started Jun 24 05:27:27 PM PDT 24
Finished Jun 24 05:27:30 PM PDT 24
Peak memory 206176 kb
Host smart-4d972e24-1f7e-4d1a-bc44-a1303f209e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11709
49598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1170949598
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.1511973112
Short name T2095
Test name
Test status
Simulation time 231985159 ps
CPU time 0.98 seconds
Started Jun 24 05:27:22 PM PDT 24
Finished Jun 24 05:27:25 PM PDT 24
Peak memory 206176 kb
Host smart-75ed49ef-2154-405b-8bd3-fbd543bde293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15119
73112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.1511973112
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2476061695
Short name T829
Test name
Test status
Simulation time 499097541 ps
CPU time 1.4 seconds
Started Jun 24 05:27:22 PM PDT 24
Finished Jun 24 05:27:24 PM PDT 24
Peak memory 206136 kb
Host smart-4d2f2c00-f17a-4afc-80c7-335c6a3920cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24760
61695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2476061695
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.1514897419
Short name T1665
Test name
Test status
Simulation time 16537550275 ps
CPU time 30.24 seconds
Started Jun 24 05:27:24 PM PDT 24
Finished Jun 24 05:27:56 PM PDT 24
Peak memory 206328 kb
Host smart-7666990b-bcb1-4fda-beac-774fc7deff72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15148
97419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1514897419
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.21983480
Short name T525
Test name
Test status
Simulation time 486376452 ps
CPU time 1.33 seconds
Started Jun 24 05:27:24 PM PDT 24
Finished Jun 24 05:27:27 PM PDT 24
Peak memory 206068 kb
Host smart-4b8ed6c9-979a-4086-9a4d-bc9a19a20563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21983
480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.21983480
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3816157076
Short name T377
Test name
Test status
Simulation time 135641616 ps
CPU time 0.76 seconds
Started Jun 24 05:27:29 PM PDT 24
Finished Jun 24 05:27:31 PM PDT 24
Peak memory 206052 kb
Host smart-a906cbe0-babe-4b87-bc9e-79fc7c6db8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38161
57076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3816157076
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.1188036020
Short name T1377
Test name
Test status
Simulation time 65417684 ps
CPU time 0.71 seconds
Started Jun 24 05:27:29 PM PDT 24
Finished Jun 24 05:27:31 PM PDT 24
Peak memory 206036 kb
Host smart-61c90625-669c-419a-8b74-868eb18f21f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11880
36020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1188036020
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1140472086
Short name T1609
Test name
Test status
Simulation time 726932646 ps
CPU time 1.93 seconds
Started Jun 24 05:27:23 PM PDT 24
Finished Jun 24 05:27:26 PM PDT 24
Peak memory 206308 kb
Host smart-ae316295-6958-4222-a9ad-57d04aac638a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11404
72086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1140472086
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2552330501
Short name T1720
Test name
Test status
Simulation time 269231459 ps
CPU time 2.03 seconds
Started Jun 24 05:27:24 PM PDT 24
Finished Jun 24 05:27:27 PM PDT 24
Peak memory 206340 kb
Host smart-cf30efc8-e4b1-4da6-a13f-b743e2137798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25523
30501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2552330501
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.1488219265
Short name T1689
Test name
Test status
Simulation time 180730690 ps
CPU time 0.84 seconds
Started Jun 24 05:27:23 PM PDT 24
Finished Jun 24 05:27:25 PM PDT 24
Peak memory 206060 kb
Host smart-a6c619ac-a856-45b0-835d-f93b311ea82f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14882
19265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.1488219265
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.1978777000
Short name T450
Test name
Test status
Simulation time 135981516 ps
CPU time 0.75 seconds
Started Jun 24 05:27:22 PM PDT 24
Finished Jun 24 05:27:24 PM PDT 24
Peak memory 206188 kb
Host smart-c557afe4-6922-46e1-a2ed-2ec7c28fae1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19787
77000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1978777000
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3081021709
Short name T304
Test name
Test status
Simulation time 203596929 ps
CPU time 0.87 seconds
Started Jun 24 05:27:26 PM PDT 24
Finished Jun 24 05:27:28 PM PDT 24
Peak memory 206104 kb
Host smart-f6e65822-6fe7-4973-860c-44f92865bc69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30810
21709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3081021709
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.3403153412
Short name T491
Test name
Test status
Simulation time 16617653993 ps
CPU time 458.89 seconds
Started Jun 24 05:27:26 PM PDT 24
Finished Jun 24 05:35:07 PM PDT 24
Peak memory 206396 kb
Host smart-ba75b947-3dd8-4517-94c4-b41146a3e909
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3403153412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.3403153412
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1720370404
Short name T406
Test name
Test status
Simulation time 170165433 ps
CPU time 0.79 seconds
Started Jun 24 05:27:23 PM PDT 24
Finished Jun 24 05:27:25 PM PDT 24
Peak memory 206184 kb
Host smart-38374118-82cd-4a9f-80e3-0669dc4433b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17203
70404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1720370404
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.2339123195
Short name T1197
Test name
Test status
Simulation time 23435061684 ps
CPU time 23.05 seconds
Started Jun 24 05:27:24 PM PDT 24
Finished Jun 24 05:27:49 PM PDT 24
Peak memory 206176 kb
Host smart-7784b4ca-d472-4ce1-952d-5c832fe7edfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23391
23195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.2339123195
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2811356880
Short name T2102
Test name
Test status
Simulation time 3302538132 ps
CPU time 3.86 seconds
Started Jun 24 05:27:26 PM PDT 24
Finished Jun 24 05:27:32 PM PDT 24
Peak memory 206164 kb
Host smart-53f7019f-70a5-4a64-8310-37afc34579d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28113
56880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2811356880
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1354404566
Short name T1856
Test name
Test status
Simulation time 10980272735 ps
CPU time 81.66 seconds
Started Jun 24 05:27:24 PM PDT 24
Finished Jun 24 05:28:47 PM PDT 24
Peak memory 206584 kb
Host smart-ba0e3273-331e-4a26-b73e-054e8da28bcb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1354404566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1354404566
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.3050826150
Short name T480
Test name
Test status
Simulation time 284966045 ps
CPU time 0.95 seconds
Started Jun 24 05:27:26 PM PDT 24
Finished Jun 24 05:27:28 PM PDT 24
Peak memory 205976 kb
Host smart-dd3093fe-f8b5-447b-a988-44d1ac29999c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3050826150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.3050826150
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1631542765
Short name T1691
Test name
Test status
Simulation time 190363201 ps
CPU time 0.87 seconds
Started Jun 24 05:27:23 PM PDT 24
Finished Jun 24 05:27:25 PM PDT 24
Peak memory 206180 kb
Host smart-6b9b30c3-f1e1-424a-ab71-770cba969235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16315
42765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1631542765
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.4151785538
Short name T1768
Test name
Test status
Simulation time 11565480376 ps
CPU time 311.24 seconds
Started Jun 24 05:27:25 PM PDT 24
Finished Jun 24 05:32:38 PM PDT 24
Peak memory 206360 kb
Host smart-dc6dfc1b-3559-4c94-8dbb-e5e70c53e735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41517
85538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.4151785538
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.1192838704
Short name T1241
Test name
Test status
Simulation time 11350491890 ps
CPU time 331.55 seconds
Started Jun 24 05:27:22 PM PDT 24
Finished Jun 24 05:32:54 PM PDT 24
Peak memory 206392 kb
Host smart-e0246414-ddd0-40f8-83c7-96bbc4fa1679
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1192838704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.1192838704
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.717572925
Short name T1923
Test name
Test status
Simulation time 154126147 ps
CPU time 0.83 seconds
Started Jun 24 05:27:27 PM PDT 24
Finished Jun 24 05:27:30 PM PDT 24
Peak memory 206172 kb
Host smart-05dc945e-a0c7-481e-95af-5587ed848593
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=717572925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.717572925
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.151824983
Short name T624
Test name
Test status
Simulation time 209013348 ps
CPU time 0.81 seconds
Started Jun 24 05:27:28 PM PDT 24
Finished Jun 24 05:27:30 PM PDT 24
Peak memory 206188 kb
Host smart-3580e878-19bc-4bd1-bf30-89d361c93ce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15182
4983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.151824983
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2917521475
Short name T124
Test name
Test status
Simulation time 209377551 ps
CPU time 0.87 seconds
Started Jun 24 05:27:24 PM PDT 24
Finished Jun 24 05:27:27 PM PDT 24
Peak memory 206064 kb
Host smart-877e0bf2-f748-45c2-80d9-c4542627f39c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29175
21475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2917521475
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.870090605
Short name T2171
Test name
Test status
Simulation time 201641474 ps
CPU time 0.84 seconds
Started Jun 24 05:27:27 PM PDT 24
Finished Jun 24 05:27:30 PM PDT 24
Peak memory 206168 kb
Host smart-75875226-6f2c-4997-9642-7bdc27915adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87009
0605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.870090605
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2405014467
Short name T417
Test name
Test status
Simulation time 153883884 ps
CPU time 0.76 seconds
Started Jun 24 05:27:23 PM PDT 24
Finished Jun 24 05:27:25 PM PDT 24
Peak memory 206172 kb
Host smart-d8e12d5a-07b5-42e5-b4cb-db66c6be3769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24050
14467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2405014467
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1703542776
Short name T2491
Test name
Test status
Simulation time 203457197 ps
CPU time 0.78 seconds
Started Jun 24 05:27:26 PM PDT 24
Finished Jun 24 05:27:28 PM PDT 24
Peak memory 206192 kb
Host smart-a5aa6135-db08-4c2d-bb18-68c30973d8f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17035
42776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1703542776
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3271704114
Short name T824
Test name
Test status
Simulation time 147172038 ps
CPU time 0.77 seconds
Started Jun 24 05:27:24 PM PDT 24
Finished Jun 24 05:27:26 PM PDT 24
Peak memory 206180 kb
Host smart-947d1805-e907-44f2-862b-e8ad828c4844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32717
04114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3271704114
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.3995435909
Short name T2026
Test name
Test status
Simulation time 210107662 ps
CPU time 0.87 seconds
Started Jun 24 05:27:21 PM PDT 24
Finished Jun 24 05:27:23 PM PDT 24
Peak memory 206096 kb
Host smart-f438e24c-7f8a-447d-823f-69067d5b87f6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3995435909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.3995435909
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.29520525
Short name T812
Test name
Test status
Simulation time 168704907 ps
CPU time 0.78 seconds
Started Jun 24 05:27:27 PM PDT 24
Finished Jun 24 05:27:29 PM PDT 24
Peak memory 206168 kb
Host smart-7ac85b23-9c6a-498a-9bb4-0516e197aa81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29520
525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.29520525
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.30893265
Short name T1498
Test name
Test status
Simulation time 40502014 ps
CPU time 0.63 seconds
Started Jun 24 05:27:26 PM PDT 24
Finished Jun 24 05:27:28 PM PDT 24
Peak memory 206188 kb
Host smart-67a277d1-9f61-4d9a-8858-ad5498cd75c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30893
265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.30893265
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3070556370
Short name T2169
Test name
Test status
Simulation time 20943492815 ps
CPU time 45.05 seconds
Started Jun 24 05:27:23 PM PDT 24
Finished Jun 24 05:28:09 PM PDT 24
Peak memory 206444 kb
Host smart-bc340ddf-9a90-4b70-81f8-21fe26003f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30705
56370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3070556370
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2665621144
Short name T872
Test name
Test status
Simulation time 190218853 ps
CPU time 0.92 seconds
Started Jun 24 05:27:25 PM PDT 24
Finished Jun 24 05:27:27 PM PDT 24
Peak memory 206064 kb
Host smart-da9b07d4-ac13-4536-afd2-85c986ae304c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26656
21144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2665621144
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3913019935
Short name T956
Test name
Test status
Simulation time 169574280 ps
CPU time 0.81 seconds
Started Jun 24 05:27:27 PM PDT 24
Finished Jun 24 05:27:30 PM PDT 24
Peak memory 206168 kb
Host smart-f46599f2-7e22-44cb-bb65-c112054d9a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39130
19935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3913019935
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.3164661058
Short name T553
Test name
Test status
Simulation time 260823849 ps
CPU time 0.9 seconds
Started Jun 24 05:27:26 PM PDT 24
Finished Jun 24 05:27:28 PM PDT 24
Peak memory 206136 kb
Host smart-495ac840-9696-4b91-ac51-a4b408501ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31646
61058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.3164661058
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.167764747
Short name T825
Test name
Test status
Simulation time 176971795 ps
CPU time 0.87 seconds
Started Jun 24 05:27:23 PM PDT 24
Finished Jun 24 05:27:26 PM PDT 24
Peak memory 206184 kb
Host smart-d15d549d-8032-4e69-8314-6301db67bc11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16776
4747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.167764747
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.236939104
Short name T2211
Test name
Test status
Simulation time 170992856 ps
CPU time 0.79 seconds
Started Jun 24 05:27:25 PM PDT 24
Finished Jun 24 05:27:28 PM PDT 24
Peak memory 206176 kb
Host smart-1b6730e9-66f1-418f-8ee5-51688ddf4bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23693
9104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.236939104
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.1093054429
Short name T993
Test name
Test status
Simulation time 164474036 ps
CPU time 0.76 seconds
Started Jun 24 05:27:21 PM PDT 24
Finished Jun 24 05:27:23 PM PDT 24
Peak memory 206192 kb
Host smart-dc933cb9-c1db-44bb-ab07-ce9dc5a743c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10930
54429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.1093054429
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3442066631
Short name T1444
Test name
Test status
Simulation time 196687154 ps
CPU time 0.78 seconds
Started Jun 24 05:27:24 PM PDT 24
Finished Jun 24 05:27:26 PM PDT 24
Peak memory 206124 kb
Host smart-53cb04a1-fe51-40fc-8149-dc48cc296e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34420
66631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3442066631
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1382267645
Short name T1947
Test name
Test status
Simulation time 261748328 ps
CPU time 1.04 seconds
Started Jun 24 05:27:26 PM PDT 24
Finished Jun 24 05:27:29 PM PDT 24
Peak memory 206116 kb
Host smart-70252dbf-a2f3-4f74-8c52-8ec789915f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13822
67645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1382267645
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.1791568743
Short name T902
Test name
Test status
Simulation time 11824990764 ps
CPU time 338.79 seconds
Started Jun 24 05:27:22 PM PDT 24
Finished Jun 24 05:33:02 PM PDT 24
Peak memory 206360 kb
Host smart-59f0dd54-323d-4e9b-8e9a-e1376649f080
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1791568743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.1791568743
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3011817230
Short name T1623
Test name
Test status
Simulation time 168407009 ps
CPU time 0.82 seconds
Started Jun 24 05:27:27 PM PDT 24
Finished Jun 24 05:27:29 PM PDT 24
Peak memory 205672 kb
Host smart-4cadc9c2-5f75-442b-8d19-3ce26a421223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30118
17230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3011817230
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1428365030
Short name T1124
Test name
Test status
Simulation time 177629028 ps
CPU time 0.79 seconds
Started Jun 24 05:27:25 PM PDT 24
Finished Jun 24 05:27:27 PM PDT 24
Peak memory 206120 kb
Host smart-bc0d1b7c-6cd8-444e-8c9f-036e48f7f2a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14283
65030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1428365030
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.950532954
Short name T2099
Test name
Test status
Simulation time 10193915739 ps
CPU time 77.02 seconds
Started Jun 24 05:27:21 PM PDT 24
Finished Jun 24 05:28:40 PM PDT 24
Peak memory 206400 kb
Host smart-90cd2f4c-7c36-4499-b1b3-324ff87fd1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95053
2954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.950532954
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.3414066341
Short name T1826
Test name
Test status
Simulation time 4162280296 ps
CPU time 5.2 seconds
Started Jun 24 05:27:27 PM PDT 24
Finished Jun 24 05:27:34 PM PDT 24
Peak memory 206216 kb
Host smart-7ff3a8bd-9473-44ff-8c09-41b63ccbcea4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3414066341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.3414066341
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.1869569849
Short name T659
Test name
Test status
Simulation time 13437284248 ps
CPU time 11.8 seconds
Started Jun 24 05:27:23 PM PDT 24
Finished Jun 24 05:27:37 PM PDT 24
Peak memory 206300 kb
Host smart-9ed6dbd7-c5d5-4ba6-a033-5a4257b0d15d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1869569849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.1869569849
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.2771648618
Short name T768
Test name
Test status
Simulation time 23418594693 ps
CPU time 25.08 seconds
Started Jun 24 05:27:27 PM PDT 24
Finished Jun 24 05:27:54 PM PDT 24
Peak memory 205844 kb
Host smart-97d4c85a-bde3-4e80-8a71-b200f8ae30a1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2771648618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.2771648618
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.4107504920
Short name T1755
Test name
Test status
Simulation time 175168378 ps
CPU time 0.87 seconds
Started Jun 24 05:27:23 PM PDT 24
Finished Jun 24 05:27:26 PM PDT 24
Peak memory 206192 kb
Host smart-fb0fffdf-4f46-449f-99d5-944252aa6189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41075
04920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.4107504920
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.3127929106
Short name T1761
Test name
Test status
Simulation time 145075348 ps
CPU time 0.79 seconds
Started Jun 24 05:27:23 PM PDT 24
Finished Jun 24 05:27:26 PM PDT 24
Peak memory 206160 kb
Host smart-8e0a1c0e-d161-4f36-9986-f59251b11a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31279
29106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.3127929106
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.4012363556
Short name T2077
Test name
Test status
Simulation time 238107491 ps
CPU time 0.9 seconds
Started Jun 24 05:27:28 PM PDT 24
Finished Jun 24 05:27:30 PM PDT 24
Peak memory 206172 kb
Host smart-db51ceca-106a-4502-b7f9-89c3ea2c82ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40123
63556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.4012363556
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3772963435
Short name T408
Test name
Test status
Simulation time 762266707 ps
CPU time 1.81 seconds
Started Jun 24 05:27:24 PM PDT 24
Finished Jun 24 05:27:28 PM PDT 24
Peak memory 206356 kb
Host smart-197a18ab-cab1-4618-9a33-f21b4b164ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37729
63435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3772963435
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.2682264777
Short name T2449
Test name
Test status
Simulation time 18882536350 ps
CPU time 36.09 seconds
Started Jun 24 05:27:27 PM PDT 24
Finished Jun 24 05:28:05 PM PDT 24
Peak memory 206336 kb
Host smart-4a7c102f-8d4f-4720-b70a-a3a9e7318dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26822
64777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.2682264777
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.1403932852
Short name T2335
Test name
Test status
Simulation time 388569715 ps
CPU time 1.27 seconds
Started Jun 24 05:27:24 PM PDT 24
Finished Jun 24 05:27:27 PM PDT 24
Peak memory 206156 kb
Host smart-3c3b4263-2906-4587-8ed1-1422411dbd02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14039
32852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.1403932852
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.1281803253
Short name T1189
Test name
Test status
Simulation time 204947286 ps
CPU time 0.81 seconds
Started Jun 24 05:27:26 PM PDT 24
Finished Jun 24 05:27:29 PM PDT 24
Peak memory 206096 kb
Host smart-35a9a9ba-ce14-42de-ab1d-bc7fc790a75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12818
03253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.1281803253
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.3930438472
Short name T1912
Test name
Test status
Simulation time 36513574 ps
CPU time 0.64 seconds
Started Jun 24 05:27:35 PM PDT 24
Finished Jun 24 05:27:38 PM PDT 24
Peak memory 206108 kb
Host smart-a340690e-1e74-49c0-a9fc-f5480a3e4a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39304
38472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3930438472
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3997190432
Short name T2065
Test name
Test status
Simulation time 846811534 ps
CPU time 1.97 seconds
Started Jun 24 05:27:32 PM PDT 24
Finished Jun 24 05:27:34 PM PDT 24
Peak memory 206248 kb
Host smart-447c0fb6-e7a9-4711-832a-f8f631968f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39971
90432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3997190432
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1992271076
Short name T1658
Test name
Test status
Simulation time 411812922 ps
CPU time 2.53 seconds
Started Jun 24 05:27:33 PM PDT 24
Finished Jun 24 05:27:37 PM PDT 24
Peak memory 206324 kb
Host smart-3c479578-090c-49da-9452-10afa70a8c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19922
71076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1992271076
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.4183372163
Short name T914
Test name
Test status
Simulation time 179172092 ps
CPU time 0.86 seconds
Started Jun 24 05:27:36 PM PDT 24
Finished Jun 24 05:27:39 PM PDT 24
Peak memory 206176 kb
Host smart-2829ffa6-94af-4337-aaa1-7d27c335f8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41833
72163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.4183372163
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3229762699
Short name T1850
Test name
Test status
Simulation time 145898836 ps
CPU time 0.73 seconds
Started Jun 24 05:27:33 PM PDT 24
Finished Jun 24 05:27:36 PM PDT 24
Peak memory 206188 kb
Host smart-705f143e-7ce0-47a9-a699-a4c53bc9ece8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32297
62699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3229762699
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.661609647
Short name T1829
Test name
Test status
Simulation time 285888433 ps
CPU time 1 seconds
Started Jun 24 05:27:33 PM PDT 24
Finished Jun 24 05:27:35 PM PDT 24
Peak memory 206188 kb
Host smart-bccccb35-75e7-4d24-9918-a789550bfc6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66160
9647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.661609647
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.3496089995
Short name T107
Test name
Test status
Simulation time 9138102223 ps
CPU time 69.74 seconds
Started Jun 24 05:27:33 PM PDT 24
Finished Jun 24 05:28:43 PM PDT 24
Peak memory 206356 kb
Host smart-7392a082-e4a9-4da8-8f1b-44e52c5702f7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3496089995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.3496089995
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.3229633366
Short name T644
Test name
Test status
Simulation time 176624437 ps
CPU time 0.88 seconds
Started Jun 24 05:27:34 PM PDT 24
Finished Jun 24 05:27:37 PM PDT 24
Peak memory 206192 kb
Host smart-0d58ca8c-5894-409a-a985-2a9efb31a44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32296
33366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.3229633366
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.830976947
Short name T798
Test name
Test status
Simulation time 23276771565 ps
CPU time 23.64 seconds
Started Jun 24 05:27:33 PM PDT 24
Finished Jun 24 05:27:58 PM PDT 24
Peak memory 206148 kb
Host smart-f7656605-a3ba-4691-9e7a-e01c74ff1fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83097
6947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.830976947
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.2720572270
Short name T1358
Test name
Test status
Simulation time 3345479336 ps
CPU time 3.74 seconds
Started Jun 24 05:27:31 PM PDT 24
Finished Jun 24 05:27:36 PM PDT 24
Peak memory 206160 kb
Host smart-f8bd4fb7-9334-4e45-957b-742f5021e11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27205
72270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2720572270
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.1223506023
Short name T877
Test name
Test status
Simulation time 11311711186 ps
CPU time 315.69 seconds
Started Jun 24 05:27:33 PM PDT 24
Finished Jun 24 05:32:51 PM PDT 24
Peak memory 206388 kb
Host smart-77409975-6213-4bcb-86b6-62804726d7a7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1223506023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.1223506023
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.226209037
Short name T554
Test name
Test status
Simulation time 257920816 ps
CPU time 0.92 seconds
Started Jun 24 05:27:33 PM PDT 24
Finished Jun 24 05:27:36 PM PDT 24
Peak memory 206196 kb
Host smart-ed5bc58e-ca8f-44e2-a4e5-d4efa8c8a162
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=226209037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.226209037
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.517959392
Short name T1299
Test name
Test status
Simulation time 235230595 ps
CPU time 0.9 seconds
Started Jun 24 05:27:35 PM PDT 24
Finished Jun 24 05:27:38 PM PDT 24
Peak memory 206180 kb
Host smart-7b3c50f6-cd5e-4620-9793-7ca4b8ba8644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51795
9392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.517959392
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.618928745
Short name T1363
Test name
Test status
Simulation time 4730255457 ps
CPU time 133.56 seconds
Started Jun 24 05:27:31 PM PDT 24
Finished Jun 24 05:29:46 PM PDT 24
Peak memory 206300 kb
Host smart-288a0300-0339-49a0-bb56-779da329a10a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61892
8745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.618928745
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.750594783
Short name T2200
Test name
Test status
Simulation time 10062037182 ps
CPU time 90.73 seconds
Started Jun 24 05:27:36 PM PDT 24
Finished Jun 24 05:29:09 PM PDT 24
Peak memory 206352 kb
Host smart-39419cbc-9b1e-4208-9d85-11a695f6741f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=750594783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.750594783
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.2253404070
Short name T1261
Test name
Test status
Simulation time 150146440 ps
CPU time 0.79 seconds
Started Jun 24 05:27:34 PM PDT 24
Finished Jun 24 05:27:38 PM PDT 24
Peak memory 206192 kb
Host smart-74c31d09-449b-4acc-ba88-fa29bf60f6f1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2253404070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.2253404070
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1558366478
Short name T338
Test name
Test status
Simulation time 146697819 ps
CPU time 0.81 seconds
Started Jun 24 05:27:32 PM PDT 24
Finished Jun 24 05:27:33 PM PDT 24
Peak memory 206192 kb
Host smart-3146fad6-11df-4886-ada1-d4cdbf21837c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15583
66478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1558366478
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.4071185068
Short name T1979
Test name
Test status
Simulation time 177047773 ps
CPU time 0.81 seconds
Started Jun 24 05:27:34 PM PDT 24
Finished Jun 24 05:27:37 PM PDT 24
Peak memory 206176 kb
Host smart-f6b846ee-8a05-491a-8553-e04a33d79321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40711
85068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.4071185068
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.3939375701
Short name T1348
Test name
Test status
Simulation time 181678755 ps
CPU time 0.88 seconds
Started Jun 24 05:27:37 PM PDT 24
Finished Jun 24 05:27:40 PM PDT 24
Peak memory 206116 kb
Host smart-1856934a-6d3c-4e67-b085-342cb2fc78f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39393
75701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.3939375701
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.3970061433
Short name T1878
Test name
Test status
Simulation time 180798235 ps
CPU time 0.83 seconds
Started Jun 24 05:27:32 PM PDT 24
Finished Jun 24 05:27:34 PM PDT 24
Peak memory 206176 kb
Host smart-71a31a96-6ae9-4ee0-8712-35c1314bf2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39700
61433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.3970061433
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.86671592
Short name T456
Test name
Test status
Simulation time 243555229 ps
CPU time 0.88 seconds
Started Jun 24 05:27:32 PM PDT 24
Finished Jun 24 05:27:33 PM PDT 24
Peak memory 206128 kb
Host smart-24fa385a-e22a-4d36-bbe2-607dbb29bc3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86671
592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.86671592
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1272790309
Short name T1791
Test name
Test status
Simulation time 145092634 ps
CPU time 0.8 seconds
Started Jun 24 05:27:35 PM PDT 24
Finished Jun 24 05:27:39 PM PDT 24
Peak memory 206172 kb
Host smart-36a661b1-1dc8-47b4-b169-f75bf938aeeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12727
90309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1272790309
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.600215230
Short name T1819
Test name
Test status
Simulation time 248121835 ps
CPU time 1.04 seconds
Started Jun 24 05:27:34 PM PDT 24
Finished Jun 24 05:27:37 PM PDT 24
Peak memory 206028 kb
Host smart-1c8bcbbc-a35c-42b0-a69a-6c0ac7b1878a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=600215230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.600215230
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.498260534
Short name T303
Test name
Test status
Simulation time 140770268 ps
CPU time 0.78 seconds
Started Jun 24 05:27:36 PM PDT 24
Finished Jun 24 05:27:39 PM PDT 24
Peak memory 206192 kb
Host smart-1ec93af2-157f-4381-8310-743688180c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49826
0534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.498260534
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3626112295
Short name T759
Test name
Test status
Simulation time 28125677 ps
CPU time 0.65 seconds
Started Jun 24 05:27:37 PM PDT 24
Finished Jun 24 05:27:40 PM PDT 24
Peak memory 206096 kb
Host smart-82f25c58-3cdf-4191-bd11-144c91ca81f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36261
12295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3626112295
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.147869747
Short name T2128
Test name
Test status
Simulation time 19168806269 ps
CPU time 41.82 seconds
Started Jun 24 05:27:33 PM PDT 24
Finished Jun 24 05:28:17 PM PDT 24
Peak memory 206232 kb
Host smart-8d737ed9-8f81-4a6e-ad65-577174360972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14786
9747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.147869747
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.518160292
Short name T1748
Test name
Test status
Simulation time 192370626 ps
CPU time 0.84 seconds
Started Jun 24 05:27:35 PM PDT 24
Finished Jun 24 05:27:39 PM PDT 24
Peak memory 206156 kb
Host smart-5b6edd00-7f5a-420b-8d22-f22220eda6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51816
0292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.518160292
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1582252375
Short name T954
Test name
Test status
Simulation time 202039206 ps
CPU time 0.84 seconds
Started Jun 24 05:27:34 PM PDT 24
Finished Jun 24 05:27:36 PM PDT 24
Peak memory 206180 kb
Host smart-a06f8fc2-fcd6-425f-9c5f-967c80a928f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15822
52375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1582252375
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.3331672828
Short name T1301
Test name
Test status
Simulation time 198622942 ps
CPU time 0.85 seconds
Started Jun 24 05:27:33 PM PDT 24
Finished Jun 24 05:27:35 PM PDT 24
Peak memory 206200 kb
Host smart-ddc519f4-e703-498f-8cd3-33b4b634f720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33316
72828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3331672828
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.732393061
Short name T784
Test name
Test status
Simulation time 182880040 ps
CPU time 0.79 seconds
Started Jun 24 05:27:31 PM PDT 24
Finished Jun 24 05:27:33 PM PDT 24
Peak memory 206172 kb
Host smart-6b4333d5-5d06-4891-b01e-6f1303f174a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73239
3061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.732393061
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.4113953346
Short name T2375
Test name
Test status
Simulation time 139814447 ps
CPU time 0.74 seconds
Started Jun 24 05:27:35 PM PDT 24
Finished Jun 24 05:27:38 PM PDT 24
Peak memory 206172 kb
Host smart-b3d1db89-f9dd-4cf0-965f-783aa424d4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41139
53346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.4113953346
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1595484290
Short name T938
Test name
Test status
Simulation time 153519661 ps
CPU time 0.77 seconds
Started Jun 24 05:27:36 PM PDT 24
Finished Jun 24 05:27:39 PM PDT 24
Peak memory 206188 kb
Host smart-0949dc9f-392c-4322-828a-6eb9aa427869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15954
84290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1595484290
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1564079819
Short name T1336
Test name
Test status
Simulation time 156293244 ps
CPU time 0.78 seconds
Started Jun 24 05:27:32 PM PDT 24
Finished Jun 24 05:27:33 PM PDT 24
Peak memory 206176 kb
Host smart-0bfed237-2b63-47f8-84e4-8902c8e0fade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15640
79819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1564079819
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2042275555
Short name T967
Test name
Test status
Simulation time 196767815 ps
CPU time 0.84 seconds
Started Jun 24 05:27:33 PM PDT 24
Finished Jun 24 05:27:35 PM PDT 24
Peak memory 206192 kb
Host smart-6504faa4-f6f6-4ff0-a411-56a8523743be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20422
75555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2042275555
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3676400507
Short name T2281
Test name
Test status
Simulation time 7706860784 ps
CPU time 54.97 seconds
Started Jun 24 05:27:35 PM PDT 24
Finished Jun 24 05:28:32 PM PDT 24
Peak memory 206392 kb
Host smart-f25db3d7-4e99-4041-b014-f3fbf463b14d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3676400507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3676400507
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3075716329
Short name T1390
Test name
Test status
Simulation time 171146847 ps
CPU time 0.8 seconds
Started Jun 24 05:27:33 PM PDT 24
Finished Jun 24 05:27:35 PM PDT 24
Peak memory 206104 kb
Host smart-c4f021b9-fd27-4e81-9710-215bf6715fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30757
16329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3075716329
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.3585658555
Short name T349
Test name
Test status
Simulation time 190509188 ps
CPU time 0.83 seconds
Started Jun 24 05:27:34 PM PDT 24
Finished Jun 24 05:27:37 PM PDT 24
Peak memory 206020 kb
Host smart-222c3996-09a5-4eaf-a87c-81ec4cfa3c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35856
58555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.3585658555
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1020201777
Short name T2388
Test name
Test status
Simulation time 6193914398 ps
CPU time 62.52 seconds
Started Jun 24 05:27:33 PM PDT 24
Finished Jun 24 05:28:37 PM PDT 24
Peak memory 206232 kb
Host smart-0734dc59-589e-4868-b400-35317e503a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10202
01777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1020201777
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.1286863924
Short name T1231
Test name
Test status
Simulation time 3756041421 ps
CPU time 4.67 seconds
Started Jun 24 05:27:36 PM PDT 24
Finished Jun 24 05:27:43 PM PDT 24
Peak memory 206372 kb
Host smart-f5a1179f-339d-4031-b232-91d6263b2b54
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1286863924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.1286863924
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1548019073
Short name T2389
Test name
Test status
Simulation time 13562170589 ps
CPU time 15.41 seconds
Started Jun 24 05:27:34 PM PDT 24
Finished Jun 24 05:27:52 PM PDT 24
Peak memory 206352 kb
Host smart-67b8e729-1dc0-40f4-a54b-28a2b49a310a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1548019073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1548019073
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3773046275
Short name T1779
Test name
Test status
Simulation time 23316808537 ps
CPU time 25.81 seconds
Started Jun 24 05:27:34 PM PDT 24
Finished Jun 24 05:28:02 PM PDT 24
Peak memory 206216 kb
Host smart-30fecac6-6706-4d25-b966-dcfbb372ef8e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3773046275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.3773046275
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.702225844
Short name T2279
Test name
Test status
Simulation time 155012423 ps
CPU time 0.78 seconds
Started Jun 24 05:27:36 PM PDT 24
Finished Jun 24 05:27:39 PM PDT 24
Peak memory 206168 kb
Host smart-592c440d-8327-4da7-8256-6f67221e5517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70222
5844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.702225844
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.1755434532
Short name T2043
Test name
Test status
Simulation time 180767055 ps
CPU time 0.78 seconds
Started Jun 24 05:27:37 PM PDT 24
Finished Jun 24 05:27:40 PM PDT 24
Peak memory 206088 kb
Host smart-2663db79-e8ff-4d6e-b9dd-1e7021988240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17554
34532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.1755434532
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3759064005
Short name T2296
Test name
Test status
Simulation time 234478177 ps
CPU time 0.95 seconds
Started Jun 24 05:27:34 PM PDT 24
Finished Jun 24 05:27:37 PM PDT 24
Peak memory 206076 kb
Host smart-b4a4bcfe-53d3-4fe9-89fa-7fa435ec7676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37590
64005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3759064005
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1010805531
Short name T551
Test name
Test status
Simulation time 527575975 ps
CPU time 1.33 seconds
Started Jun 24 05:27:34 PM PDT 24
Finished Jun 24 05:27:38 PM PDT 24
Peak memory 206168 kb
Host smart-f9d9973a-d13a-4002-b5a3-7207ee40da49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10108
05531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1010805531
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.733254476
Short name T1740
Test name
Test status
Simulation time 21526305058 ps
CPU time 39.66 seconds
Started Jun 24 05:27:33 PM PDT 24
Finished Jun 24 05:28:14 PM PDT 24
Peak memory 206368 kb
Host smart-f028adba-a85d-47c1-9b78-89804cd1433e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73325
4476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.733254476
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.2922008643
Short name T1485
Test name
Test status
Simulation time 454179101 ps
CPU time 1.3 seconds
Started Jun 24 05:27:34 PM PDT 24
Finished Jun 24 05:27:37 PM PDT 24
Peak memory 206164 kb
Host smart-d3f47c07-c29b-4aae-9e6f-889eb546f234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29220
08643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.2922008643
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.2673114424
Short name T1769
Test name
Test status
Simulation time 143851623 ps
CPU time 0.78 seconds
Started Jun 24 05:27:34 PM PDT 24
Finished Jun 24 05:27:37 PM PDT 24
Peak memory 206096 kb
Host smart-71764a49-7810-4f40-a7d1-da687ab67cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26731
14424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.2673114424
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.3231468558
Short name T2297
Test name
Test status
Simulation time 107424535 ps
CPU time 0.71 seconds
Started Jun 24 05:27:32 PM PDT 24
Finished Jun 24 05:27:34 PM PDT 24
Peak memory 206096 kb
Host smart-5e66d9f9-ac38-4499-ad5b-e957f19a840e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32314
68558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3231468558
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.2396545106
Short name T1577
Test name
Test status
Simulation time 748513896 ps
CPU time 1.91 seconds
Started Jun 24 05:27:34 PM PDT 24
Finished Jun 24 05:27:38 PM PDT 24
Peak memory 206236 kb
Host smart-a4d32af0-ad03-44e8-aed1-73cd2895a3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23965
45106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.2396545106
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.151405129
Short name T197
Test name
Test status
Simulation time 240768207 ps
CPU time 1.45 seconds
Started Jun 24 05:27:35 PM PDT 24
Finished Jun 24 05:27:38 PM PDT 24
Peak memory 206308 kb
Host smart-b08fef62-7751-456d-8c1c-926021ac9e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15140
5129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.151405129
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.2443884842
Short name T2135
Test name
Test status
Simulation time 213075099 ps
CPU time 0.9 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:27:52 PM PDT 24
Peak memory 206176 kb
Host smart-f69be46c-1462-47ae-9814-cdfffee5b3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24438
84842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.2443884842
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1552789489
Short name T1324
Test name
Test status
Simulation time 144562405 ps
CPU time 0.77 seconds
Started Jun 24 05:27:46 PM PDT 24
Finished Jun 24 05:27:50 PM PDT 24
Peak memory 206180 kb
Host smart-2bfea00a-5d1c-43eb-82dc-faa41f3359fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15527
89489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1552789489
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2258814364
Short name T2421
Test name
Test status
Simulation time 259593553 ps
CPU time 0.91 seconds
Started Jun 24 05:27:45 PM PDT 24
Finished Jun 24 05:27:48 PM PDT 24
Peak memory 206192 kb
Host smart-bfc84d44-09c0-488e-bebe-ab568c76d145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22588
14364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2258814364
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.600721309
Short name T2299
Test name
Test status
Simulation time 10625098939 ps
CPU time 318.38 seconds
Started Jun 24 05:27:43 PM PDT 24
Finished Jun 24 05:33:03 PM PDT 24
Peak memory 206296 kb
Host smart-b25ec5e0-80fc-41ea-ba21-2297a4bb12de
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=600721309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.600721309
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2041831358
Short name T1405
Test name
Test status
Simulation time 232089805 ps
CPU time 0.88 seconds
Started Jun 24 05:27:45 PM PDT 24
Finished Jun 24 05:27:49 PM PDT 24
Peak memory 206192 kb
Host smart-92425543-4832-4e24-8bb6-3d57c05d7895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20418
31358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2041831358
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.955567671
Short name T1968
Test name
Test status
Simulation time 23314682571 ps
CPU time 29.64 seconds
Started Jun 24 05:27:45 PM PDT 24
Finished Jun 24 05:28:18 PM PDT 24
Peak memory 206244 kb
Host smart-e8dc6609-6f6b-4d33-a8e1-9e49b088232f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95556
7671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.955567671
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2172282097
Short name T2373
Test name
Test status
Simulation time 3286661001 ps
CPU time 3.77 seconds
Started Jun 24 05:27:45 PM PDT 24
Finished Jun 24 05:27:51 PM PDT 24
Peak memory 206172 kb
Host smart-5ec762ac-13fb-4bb4-a361-aa526cb502da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21722
82097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2172282097
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.1630177390
Short name T461
Test name
Test status
Simulation time 10555819865 ps
CPU time 286.5 seconds
Started Jun 24 05:27:44 PM PDT 24
Finished Jun 24 05:32:33 PM PDT 24
Peak memory 206380 kb
Host smart-41ea2717-a2e8-4de4-9958-6b9d0ddad7f5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1630177390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.1630177390
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3919552200
Short name T574
Test name
Test status
Simulation time 251248407 ps
CPU time 0.95 seconds
Started Jun 24 05:27:50 PM PDT 24
Finished Jun 24 05:27:55 PM PDT 24
Peak memory 205532 kb
Host smart-a1d7ea07-9219-4e92-9b3b-879974f33f33
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3919552200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3919552200
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2947984775
Short name T1247
Test name
Test status
Simulation time 206770773 ps
CPU time 0.89 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:27:52 PM PDT 24
Peak memory 206172 kb
Host smart-5a29f507-8df6-4ef0-82cc-96237405d313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29479
84775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2947984775
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.1818655889
Short name T781
Test name
Test status
Simulation time 8134467245 ps
CPU time 203.2 seconds
Started Jun 24 05:27:44 PM PDT 24
Finished Jun 24 05:31:09 PM PDT 24
Peak memory 206304 kb
Host smart-bf5c6850-fd31-4d7c-bb5a-648a24afab1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18186
55889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.1818655889
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.3543168817
Short name T2048
Test name
Test status
Simulation time 5420631964 ps
CPU time 37.94 seconds
Started Jun 24 05:27:46 PM PDT 24
Finished Jun 24 05:28:28 PM PDT 24
Peak memory 206316 kb
Host smart-0f035d71-70f2-49de-8ce4-ef7f9cc6f83a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3543168817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.3543168817
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.675040842
Short name T1871
Test name
Test status
Simulation time 164314436 ps
CPU time 0.81 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:27:52 PM PDT 24
Peak memory 206192 kb
Host smart-9e9bc719-3475-414e-b9a9-c9cf6192cb74
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=675040842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.675040842
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3602950386
Short name T317
Test name
Test status
Simulation time 173120370 ps
CPU time 0.78 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:27:52 PM PDT 24
Peak memory 206356 kb
Host smart-cf9cf149-a35e-4b00-94d1-b45a291287f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36029
50386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3602950386
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.4253337343
Short name T1591
Test name
Test status
Simulation time 175827473 ps
CPU time 0.79 seconds
Started Jun 24 05:27:43 PM PDT 24
Finished Jun 24 05:27:46 PM PDT 24
Peak memory 206156 kb
Host smart-24d536de-c691-421b-89c3-e5edc2261b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42533
37343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.4253337343
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.1504752872
Short name T1661
Test name
Test status
Simulation time 193405776 ps
CPU time 0.95 seconds
Started Jun 24 05:27:42 PM PDT 24
Finished Jun 24 05:27:44 PM PDT 24
Peak memory 206192 kb
Host smart-63dc88bb-1ad5-4fc8-9530-3dc90ae11324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15047
52872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.1504752872
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2562097900
Short name T1151
Test name
Test status
Simulation time 201152027 ps
CPU time 0.85 seconds
Started Jun 24 05:27:43 PM PDT 24
Finished Jun 24 05:27:46 PM PDT 24
Peak memory 206184 kb
Host smart-94a1c315-77df-4b24-862d-3176e3d738c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25620
97900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2562097900
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1748658478
Short name T2225
Test name
Test status
Simulation time 150465751 ps
CPU time 0.78 seconds
Started Jun 24 05:27:42 PM PDT 24
Finished Jun 24 05:27:43 PM PDT 24
Peak memory 206196 kb
Host smart-ebbb6e9e-eef7-4251-a3fc-fb1e158f19e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17486
58478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1748658478
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1158761315
Short name T2176
Test name
Test status
Simulation time 156636409 ps
CPU time 0.83 seconds
Started Jun 24 05:27:46 PM PDT 24
Finished Jun 24 05:27:51 PM PDT 24
Peak memory 206144 kb
Host smart-9ec356ed-9e99-42e4-b99c-6e97d7067058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11587
61315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1158761315
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.1900610623
Short name T2416
Test name
Test status
Simulation time 226724164 ps
CPU time 0.91 seconds
Started Jun 24 05:27:46 PM PDT 24
Finished Jun 24 05:27:50 PM PDT 24
Peak memory 206152 kb
Host smart-06923134-7af2-45bf-8650-8d8f6f2df433
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1900610623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.1900610623
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3743236858
Short name T1017
Test name
Test status
Simulation time 162347950 ps
CPU time 0.76 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:27:52 PM PDT 24
Peak memory 206152 kb
Host smart-2e1f7bfa-f2cc-4fd5-aa44-46c65ba3e990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37432
36858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3743236858
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2513782209
Short name T26
Test name
Test status
Simulation time 35559057 ps
CPU time 0.7 seconds
Started Jun 24 05:27:43 PM PDT 24
Finished Jun 24 05:27:45 PM PDT 24
Peak memory 206188 kb
Host smart-d2543c7d-333b-4e8f-b36c-106ea10e42fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25137
82209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2513782209
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1045851451
Short name T1092
Test name
Test status
Simulation time 12701332131 ps
CPU time 30.08 seconds
Started Jun 24 05:27:43 PM PDT 24
Finished Jun 24 05:28:15 PM PDT 24
Peak memory 206360 kb
Host smart-4fcb1972-32d1-4d8a-bf90-8e14bc0016e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10458
51451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1045851451
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1620360289
Short name T370
Test name
Test status
Simulation time 217560347 ps
CPU time 1.06 seconds
Started Jun 24 05:27:45 PM PDT 24
Finished Jun 24 05:27:49 PM PDT 24
Peak memory 206172 kb
Host smart-b6571846-cd01-41e9-937d-8870228dd008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16203
60289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1620360289
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.4276941955
Short name T1078
Test name
Test status
Simulation time 168619352 ps
CPU time 0.82 seconds
Started Jun 24 05:27:44 PM PDT 24
Finished Jun 24 05:27:47 PM PDT 24
Peak memory 206064 kb
Host smart-db53c45c-c268-4c07-a61b-8fb9746b2bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42769
41955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.4276941955
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.1414970765
Short name T1584
Test name
Test status
Simulation time 218881957 ps
CPU time 0.89 seconds
Started Jun 24 05:27:50 PM PDT 24
Finished Jun 24 05:27:55 PM PDT 24
Peak memory 205616 kb
Host smart-54d12189-e89e-41e5-a011-ad48cc619e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14149
70765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.1414970765
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.608815738
Short name T813
Test name
Test status
Simulation time 184978546 ps
CPU time 0.83 seconds
Started Jun 24 05:27:45 PM PDT 24
Finished Jun 24 05:27:48 PM PDT 24
Peak memory 206108 kb
Host smart-02122857-53b0-4a3f-a5dd-73d56c2588ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60881
5738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.608815738
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.1339699951
Short name T878
Test name
Test status
Simulation time 249389380 ps
CPU time 0.96 seconds
Started Jun 24 05:27:48 PM PDT 24
Finished Jun 24 05:27:53 PM PDT 24
Peak memory 206180 kb
Host smart-0cb1e70f-ece1-4a53-93f3-96a43a83e460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13396
99951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.1339699951
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2413737822
Short name T545
Test name
Test status
Simulation time 157815392 ps
CPU time 0.8 seconds
Started Jun 24 05:27:43 PM PDT 24
Finished Jun 24 05:27:46 PM PDT 24
Peak memory 206184 kb
Host smart-b0624272-f416-4e40-a409-134a19cc85bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24137
37822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2413737822
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2774459823
Short name T797
Test name
Test status
Simulation time 166072724 ps
CPU time 0.79 seconds
Started Jun 24 05:27:46 PM PDT 24
Finished Jun 24 05:27:50 PM PDT 24
Peak memory 206168 kb
Host smart-ae3174db-786c-4516-9234-a371c17b4ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27744
59823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2774459823
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.254483629
Short name T1108
Test name
Test status
Simulation time 234612738 ps
CPU time 0.94 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:27:52 PM PDT 24
Peak memory 206056 kb
Host smart-2e0f3240-75dc-4f30-a307-90d324067ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25448
3629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.254483629
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.816603402
Short name T1588
Test name
Test status
Simulation time 4619260593 ps
CPU time 45.28 seconds
Started Jun 24 05:27:45 PM PDT 24
Finished Jun 24 05:28:34 PM PDT 24
Peak memory 206580 kb
Host smart-1cf2c8a5-5d7e-4dbe-9e64-118bff446c13
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=816603402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.816603402
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2239636607
Short name T843
Test name
Test status
Simulation time 158966813 ps
CPU time 0.8 seconds
Started Jun 24 05:27:45 PM PDT 24
Finished Jun 24 05:27:47 PM PDT 24
Peak memory 206156 kb
Host smart-c6905737-5058-4222-bf46-3d4b4e4c0f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22396
36607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2239636607
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.3921917097
Short name T1907
Test name
Test status
Simulation time 200518852 ps
CPU time 0.81 seconds
Started Jun 24 05:27:44 PM PDT 24
Finished Jun 24 05:27:46 PM PDT 24
Peak memory 206192 kb
Host smart-97681a87-f358-4e2b-a981-2feb6733393a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39219
17097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.3921917097
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.3798774249
Short name T361
Test name
Test status
Simulation time 5059877208 ps
CPU time 46.15 seconds
Started Jun 24 05:27:43 PM PDT 24
Finished Jun 24 05:28:32 PM PDT 24
Peak memory 206352 kb
Host smart-07baf996-7fff-4b97-a622-b9b942fe67c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37987
74249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.3798774249
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.3196875615
Short name T1716
Test name
Test status
Simulation time 4123747023 ps
CPU time 4.81 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:27:55 PM PDT 24
Peak memory 206244 kb
Host smart-a03c9787-0e41-43ea-8612-45ee53d5e1e7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3196875615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.3196875615
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.2226372262
Short name T2288
Test name
Test status
Simulation time 13342674070 ps
CPU time 12.28 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:28:03 PM PDT 24
Peak memory 206316 kb
Host smart-4bac807b-ee82-401d-9890-c14be1b73ba7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2226372262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.2226372262
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.3750553822
Short name T1376
Test name
Test status
Simulation time 23418362649 ps
CPU time 22.37 seconds
Started Jun 24 05:27:48 PM PDT 24
Finished Jun 24 05:28:14 PM PDT 24
Peak memory 206096 kb
Host smart-c8ab3acd-6a6c-4d3d-91bb-cbdc70da8abf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3750553822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.3750553822
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2765144264
Short name T1210
Test name
Test status
Simulation time 205055249 ps
CPU time 0.85 seconds
Started Jun 24 05:27:46 PM PDT 24
Finished Jun 24 05:27:50 PM PDT 24
Peak memory 206100 kb
Host smart-17973f76-ad0d-409f-992c-94e7f7954d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27651
44264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2765144264
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2998181355
Short name T630
Test name
Test status
Simulation time 149071806 ps
CPU time 0.79 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:27:52 PM PDT 24
Peak memory 206368 kb
Host smart-f0863037-24cb-482f-ad4d-d7f5987be3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29981
81355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2998181355
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.3419802322
Short name T2101
Test name
Test status
Simulation time 483290978 ps
CPU time 1.54 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:27:53 PM PDT 24
Peak memory 206412 kb
Host smart-7978045a-f3cc-41a6-a2a7-f62a98e0bbaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34198
02322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.3419802322
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3948949764
Short name T2215
Test name
Test status
Simulation time 1015290317 ps
CPU time 2.62 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:27:53 PM PDT 24
Peak memory 206332 kb
Host smart-00198720-0a16-4cbc-b66f-1d0d8c6b302b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39489
49764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3948949764
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.3627559578
Short name T1201
Test name
Test status
Simulation time 10094298563 ps
CPU time 20.97 seconds
Started Jun 24 05:27:50 PM PDT 24
Finished Jun 24 05:28:15 PM PDT 24
Peak memory 206244 kb
Host smart-f7d20411-c9ae-45d2-b842-0a29e4672a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36275
59578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.3627559578
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.1943868333
Short name T2233
Test name
Test status
Simulation time 453751460 ps
CPU time 1.31 seconds
Started Jun 24 05:27:46 PM PDT 24
Finished Jun 24 05:27:51 PM PDT 24
Peak memory 206416 kb
Host smart-4c6827ab-bc3f-48f8-ac61-b9af4b10a15e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19438
68333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1943868333
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.3366414129
Short name T2264
Test name
Test status
Simulation time 137019721 ps
CPU time 0.76 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:27:52 PM PDT 24
Peak memory 206176 kb
Host smart-688d2267-8c91-467c-bff0-e88f17baa8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33664
14129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3366414129
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.232863411
Short name T1025
Test name
Test status
Simulation time 38009436 ps
CPU time 0.67 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:27:52 PM PDT 24
Peak memory 206164 kb
Host smart-bcf241ac-8d93-4ed8-9cca-7b6f1350ec21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23286
3411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.232863411
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1433798195
Short name T2123
Test name
Test status
Simulation time 837661037 ps
CPU time 2.21 seconds
Started Jun 24 05:27:50 PM PDT 24
Finished Jun 24 05:27:56 PM PDT 24
Peak memory 206176 kb
Host smart-de5e5d76-165f-4db6-9f31-003f6e408942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14337
98195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1433798195
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3550180633
Short name T1459
Test name
Test status
Simulation time 219269130 ps
CPU time 1.57 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:27:53 PM PDT 24
Peak memory 206432 kb
Host smart-bcf48193-fcfb-4ad7-8b2a-92bc640bb231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35501
80633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3550180633
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.4100556808
Short name T2221
Test name
Test status
Simulation time 253471086 ps
CPU time 1.02 seconds
Started Jun 24 05:27:56 PM PDT 24
Finished Jun 24 05:28:00 PM PDT 24
Peak memory 206176 kb
Host smart-8a3c4307-54ea-4abc-b113-1ce9488ce227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41005
56808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.4100556808
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1824809160
Short name T958
Test name
Test status
Simulation time 172089059 ps
CPU time 0.77 seconds
Started Jun 24 05:27:54 PM PDT 24
Finished Jun 24 05:27:58 PM PDT 24
Peak memory 206160 kb
Host smart-a105fdaf-0a16-4056-b18e-0078c5ad3d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18248
09160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1824809160
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.58280275
Short name T2285
Test name
Test status
Simulation time 204910499 ps
CPU time 0.9 seconds
Started Jun 24 05:27:47 PM PDT 24
Finished Jun 24 05:27:52 PM PDT 24
Peak memory 206176 kb
Host smart-5fe017e4-3034-476d-896b-789a88a0cab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58280
275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.58280275
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.2828727363
Short name T661
Test name
Test status
Simulation time 203030467 ps
CPU time 0.86 seconds
Started Jun 24 05:27:48 PM PDT 24
Finished Jun 24 05:27:53 PM PDT 24
Peak memory 206064 kb
Host smart-c5b04f23-ce3d-4d04-969f-6e35c2bafbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28287
27363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.2828727363
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.4071173346
Short name T339
Test name
Test status
Simulation time 23309397516 ps
CPU time 20.3 seconds
Started Jun 24 05:27:48 PM PDT 24
Finished Jun 24 05:28:12 PM PDT 24
Peak memory 206128 kb
Host smart-3041534a-e764-4e2b-8f01-4ab1c0976ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40711
73346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.4071173346
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.2865464006
Short name T1559
Test name
Test status
Simulation time 3325004618 ps
CPU time 3.95 seconds
Started Jun 24 05:27:45 PM PDT 24
Finished Jun 24 05:27:51 PM PDT 24
Peak memory 206236 kb
Host smart-70e75054-0e9f-4dfa-a1a2-c21360333400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28654
64006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2865464006
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2385992520
Short name T1654
Test name
Test status
Simulation time 7542928092 ps
CPU time 73.96 seconds
Started Jun 24 05:27:46 PM PDT 24
Finished Jun 24 05:29:04 PM PDT 24
Peak memory 206356 kb
Host smart-6b1593c5-10ea-4696-94eb-1bd3d6dd94f4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2385992520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2385992520
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.1387402704
Short name T1106
Test name
Test status
Simulation time 232191030 ps
CPU time 0.87 seconds
Started Jun 24 05:27:53 PM PDT 24
Finished Jun 24 05:27:57 PM PDT 24
Peak memory 206164 kb
Host smart-1f397cd3-6f15-4c0f-8c15-0debe20e9c0f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1387402704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.1387402704
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.94854008
Short name T1318
Test name
Test status
Simulation time 203259213 ps
CPU time 0.9 seconds
Started Jun 24 05:27:46 PM PDT 24
Finished Jun 24 05:27:51 PM PDT 24
Peak memory 206156 kb
Host smart-b698979b-e50f-4f6c-9352-1d7e99302d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94854
008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.94854008
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.434943303
Short name T2208
Test name
Test status
Simulation time 3940643500 ps
CPU time 106.66 seconds
Started Jun 24 05:27:45 PM PDT 24
Finished Jun 24 05:29:36 PM PDT 24
Peak memory 206376 kb
Host smart-709ce3c7-8d6a-4429-abec-5ff57322f128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43494
3303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.434943303
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.538088237
Short name T710
Test name
Test status
Simulation time 3515229802 ps
CPU time 32.9 seconds
Started Jun 24 05:27:48 PM PDT 24
Finished Jun 24 05:28:25 PM PDT 24
Peak memory 206368 kb
Host smart-757f6ba5-30bb-4568-b222-2791e5fd2115
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=538088237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.538088237
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.782106928
Short name T368
Test name
Test status
Simulation time 147675959 ps
CPU time 0.8 seconds
Started Jun 24 05:27:58 PM PDT 24
Finished Jun 24 05:28:02 PM PDT 24
Peak memory 206148 kb
Host smart-8b6af071-da50-42e2-b5b2-d29ec7c55e3e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=782106928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.782106928
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3488860413
Short name T822
Test name
Test status
Simulation time 170137806 ps
CPU time 0.83 seconds
Started Jun 24 05:27:45 PM PDT 24
Finished Jun 24 05:27:49 PM PDT 24
Peak memory 206424 kb
Host smart-d58cd98a-2f26-4d67-be30-357fb6878e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34888
60413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3488860413
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.3936911920
Short name T2089
Test name
Test status
Simulation time 153653664 ps
CPU time 0.78 seconds
Started Jun 24 05:27:49 PM PDT 24
Finished Jun 24 05:27:54 PM PDT 24
Peak memory 206056 kb
Host smart-c8350b3b-876c-44dc-8fb7-783b7833195f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39369
11920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.3936911920
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.462217711
Short name T2107
Test name
Test status
Simulation time 185336436 ps
CPU time 0.84 seconds
Started Jun 24 05:28:00 PM PDT 24
Finished Jun 24 05:28:03 PM PDT 24
Peak memory 206144 kb
Host smart-8a580e42-2379-4973-bef3-613a59d644ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46221
7711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.462217711
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3050484070
Short name T425
Test name
Test status
Simulation time 207087303 ps
CPU time 0.82 seconds
Started Jun 24 05:27:56 PM PDT 24
Finished Jun 24 05:28:01 PM PDT 24
Peak memory 206080 kb
Host smart-d72b3a8b-18b3-462f-aa4d-76b63d82bb4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30504
84070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3050484070
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1509463399
Short name T66
Test name
Test status
Simulation time 158856285 ps
CPU time 0.76 seconds
Started Jun 24 05:27:54 PM PDT 24
Finished Jun 24 05:27:58 PM PDT 24
Peak memory 206076 kb
Host smart-26b9e07c-a9b8-4e5b-8619-5108d8617d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15094
63399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1509463399
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2869953734
Short name T855
Test name
Test status
Simulation time 176070260 ps
CPU time 0.73 seconds
Started Jun 24 05:27:56 PM PDT 24
Finished Jun 24 05:28:00 PM PDT 24
Peak memory 206136 kb
Host smart-f62270e3-d149-4e8d-b195-a89b5f9808ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28699
53734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2869953734
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.1987878423
Short name T720
Test name
Test status
Simulation time 191608602 ps
CPU time 0.89 seconds
Started Jun 24 05:27:56 PM PDT 24
Finished Jun 24 05:28:01 PM PDT 24
Peak memory 206360 kb
Host smart-592df963-c37e-4891-b558-224ed0b9518c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1987878423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.1987878423
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.246562646
Short name T1876
Test name
Test status
Simulation time 175062751 ps
CPU time 0.79 seconds
Started Jun 24 05:27:55 PM PDT 24
Finished Jun 24 05:27:59 PM PDT 24
Peak memory 206144 kb
Host smart-fff7b05c-cefd-4349-b664-856f5b81b4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24656
2646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.246562646
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1467224574
Short name T1464
Test name
Test status
Simulation time 16214335426 ps
CPU time 35.45 seconds
Started Jun 24 05:27:53 PM PDT 24
Finished Jun 24 05:28:31 PM PDT 24
Peak memory 206372 kb
Host smart-3d84440b-2ce9-4d2b-9df2-66ad28cb5ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14672
24574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1467224574
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.4145540850
Short name T990
Test name
Test status
Simulation time 162630736 ps
CPU time 0.81 seconds
Started Jun 24 05:27:54 PM PDT 24
Finished Jun 24 05:27:57 PM PDT 24
Peak memory 206176 kb
Host smart-177ce819-5e97-49c7-8432-1755033fbd85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41455
40850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.4145540850
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.168361050
Short name T1798
Test name
Test status
Simulation time 272865147 ps
CPU time 1.01 seconds
Started Jun 24 05:27:58 PM PDT 24
Finished Jun 24 05:28:02 PM PDT 24
Peak memory 206188 kb
Host smart-71a7e1dd-8c37-46bc-8870-6a0b1627831c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16836
1050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.168361050
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.2883532084
Short name T2160
Test name
Test status
Simulation time 224047902 ps
CPU time 0.83 seconds
Started Jun 24 05:27:58 PM PDT 24
Finished Jun 24 05:28:02 PM PDT 24
Peak memory 206148 kb
Host smart-fea18f47-e091-44ca-9f1a-10ca153b7a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28835
32084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.2883532084
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1178678582
Short name T2508
Test name
Test status
Simulation time 203977061 ps
CPU time 0.88 seconds
Started Jun 24 05:27:55 PM PDT 24
Finished Jun 24 05:28:00 PM PDT 24
Peak memory 206200 kb
Host smart-81c50353-89a5-450c-9f29-751a22deb920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11786
78582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1178678582
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.434027771
Short name T2232
Test name
Test status
Simulation time 150036667 ps
CPU time 0.75 seconds
Started Jun 24 05:28:00 PM PDT 24
Finished Jun 24 05:28:03 PM PDT 24
Peak memory 206160 kb
Host smart-eb5be79e-ade3-4fb7-bab9-92846f746a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43402
7771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.434027771
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.2223459404
Short name T1194
Test name
Test status
Simulation time 163323479 ps
CPU time 0.81 seconds
Started Jun 24 05:27:56 PM PDT 24
Finished Jun 24 05:28:00 PM PDT 24
Peak memory 206192 kb
Host smart-20e63edc-898f-4b78-aebb-852f316eadaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22234
59404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2223459404
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2550503263
Short name T1718
Test name
Test status
Simulation time 170312621 ps
CPU time 0.81 seconds
Started Jun 24 05:27:58 PM PDT 24
Finished Jun 24 05:28:02 PM PDT 24
Peak memory 206124 kb
Host smart-54c25e4e-7b4b-4152-acb1-7ae09e6e252f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25505
03263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2550503263
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.4035395980
Short name T418
Test name
Test status
Simulation time 200490260 ps
CPU time 0.9 seconds
Started Jun 24 05:27:59 PM PDT 24
Finished Jun 24 05:28:03 PM PDT 24
Peak memory 206176 kb
Host smart-c77ef6cd-f46a-4858-be2e-5ec6ece5fef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40353
95980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.4035395980
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.39122205
Short name T160
Test name
Test status
Simulation time 5926143790 ps
CPU time 160.85 seconds
Started Jun 24 05:27:59 PM PDT 24
Finished Jun 24 05:30:43 PM PDT 24
Peak memory 206380 kb
Host smart-ace931dd-ac0a-4714-a40d-01b3bd9ec067
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=39122205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.39122205
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3068601232
Short name T889
Test name
Test status
Simulation time 184011052 ps
CPU time 0.88 seconds
Started Jun 24 05:27:55 PM PDT 24
Finished Jun 24 05:27:59 PM PDT 24
Peak memory 206172 kb
Host smart-678c0e1e-d44e-4e47-83b4-f7ee66df7371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30686
01232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3068601232
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.1499057813
Short name T318
Test name
Test status
Simulation time 178515921 ps
CPU time 0.79 seconds
Started Jun 24 05:27:55 PM PDT 24
Finished Jun 24 05:27:59 PM PDT 24
Peak memory 206192 kb
Host smart-6527d41d-b3c8-44b1-a9b3-0e982f5121d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14990
57813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1499057813
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.711195690
Short name T508
Test name
Test status
Simulation time 14127560814 ps
CPU time 410.23 seconds
Started Jun 24 05:27:54 PM PDT 24
Finished Jun 24 05:34:47 PM PDT 24
Peak memory 206288 kb
Host smart-41335ed0-9dd3-4f80-a7cc-12495ca5a151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71119
5690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.711195690
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.3099935345
Short name T1228
Test name
Test status
Simulation time 3686021927 ps
CPU time 4.67 seconds
Started Jun 24 05:27:55 PM PDT 24
Finished Jun 24 05:28:02 PM PDT 24
Peak memory 206228 kb
Host smart-9425533c-339c-416c-93f5-d7962d7dbd67
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3099935345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.3099935345
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.1164586326
Short name T1599
Test name
Test status
Simulation time 13406175573 ps
CPU time 12.04 seconds
Started Jun 24 05:27:56 PM PDT 24
Finished Jun 24 05:28:11 PM PDT 24
Peak memory 206244 kb
Host smart-153f6978-758c-4e92-baf3-c5fec4b0bf63
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1164586326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.1164586326
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.76542624
Short name T9
Test name
Test status
Simulation time 23363658603 ps
CPU time 22.65 seconds
Started Jun 24 05:27:56 PM PDT 24
Finished Jun 24 05:28:21 PM PDT 24
Peak memory 206268 kb
Host smart-c001760c-55eb-4796-bd21-888d9ca765c4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=76542624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.76542624
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.61901281
Short name T1600
Test name
Test status
Simulation time 159891445 ps
CPU time 0.77 seconds
Started Jun 24 05:27:55 PM PDT 24
Finished Jun 24 05:27:59 PM PDT 24
Peak memory 206188 kb
Host smart-0128d244-331e-470f-b4a3-4c29bdb93545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61901
281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.61901281
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.4068190811
Short name T1732
Test name
Test status
Simulation time 154825930 ps
CPU time 0.73 seconds
Started Jun 24 05:27:53 PM PDT 24
Finished Jun 24 05:27:57 PM PDT 24
Peak memory 206076 kb
Host smart-d5df0013-68d8-4cf0-9627-6c3a2aa89264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40681
90811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.4068190811
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.3942827948
Short name T2090
Test name
Test status
Simulation time 451891023 ps
CPU time 1.37 seconds
Started Jun 24 05:27:59 PM PDT 24
Finished Jun 24 05:28:03 PM PDT 24
Peak memory 206172 kb
Host smart-4e1339f7-96e7-4a28-9a58-04e87e7d4a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39428
27948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.3942827948
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.43855360
Short name T1996
Test name
Test status
Simulation time 1524848056 ps
CPU time 3.25 seconds
Started Jun 24 05:27:56 PM PDT 24
Finished Jun 24 05:28:03 PM PDT 24
Peak memory 206172 kb
Host smart-4046cd74-d47c-4f30-888e-488004fbd197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43855
360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.43855360
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.168961505
Short name T844
Test name
Test status
Simulation time 18337229658 ps
CPU time 33.64 seconds
Started Jun 24 05:27:56 PM PDT 24
Finished Jun 24 05:28:33 PM PDT 24
Peak memory 206276 kb
Host smart-aaadb129-2c6a-4ce3-8ad6-e10e2dc055e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16896
1505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.168961505
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.799055272
Short name T357
Test name
Test status
Simulation time 498939199 ps
CPU time 1.48 seconds
Started Jun 24 05:27:54 PM PDT 24
Finished Jun 24 05:27:58 PM PDT 24
Peak memory 206176 kb
Host smart-94d044e5-7089-4cf8-ba56-eb1ff04341ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79905
5272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.799055272
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.660894971
Short name T1488
Test name
Test status
Simulation time 152089764 ps
CPU time 0.77 seconds
Started Jun 24 05:27:54 PM PDT 24
Finished Jun 24 05:27:57 PM PDT 24
Peak memory 206176 kb
Host smart-3cea8de9-cb16-41ba-8561-723b058d3746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66089
4971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.660894971
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.160494073
Short name T522
Test name
Test status
Simulation time 91895642 ps
CPU time 0.71 seconds
Started Jun 24 05:27:58 PM PDT 24
Finished Jun 24 05:28:02 PM PDT 24
Peak memory 206124 kb
Host smart-96a6bda5-f3a2-4aac-b79d-43650bcf87ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16049
4073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.160494073
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.687776074
Short name T982
Test name
Test status
Simulation time 842185981 ps
CPU time 2.02 seconds
Started Jun 24 05:27:57 PM PDT 24
Finished Jun 24 05:28:02 PM PDT 24
Peak memory 206296 kb
Host smart-75de3c93-86e9-49a2-bb8d-dee19c0c2deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68777
6074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.687776074
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3154712911
Short name T219
Test name
Test status
Simulation time 308451787 ps
CPU time 2.24 seconds
Started Jun 24 05:27:57 PM PDT 24
Finished Jun 24 05:28:03 PM PDT 24
Peak memory 206180 kb
Host smart-e615d2ee-4af5-446f-8d76-66d3e43d1ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31547
12911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3154712911
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.1255184532
Short name T2140
Test name
Test status
Simulation time 199688880 ps
CPU time 0.85 seconds
Started Jun 24 05:28:09 PM PDT 24
Finished Jun 24 05:28:15 PM PDT 24
Peak memory 206148 kb
Host smart-322d02d6-4e93-45ba-bd1b-a6124f417ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12551
84532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.1255184532
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1364819410
Short name T1294
Test name
Test status
Simulation time 151045958 ps
CPU time 0.78 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:28:11 PM PDT 24
Peak memory 206192 kb
Host smart-99df2730-4b7a-46a2-8b24-03daa066ee88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13648
19410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1364819410
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3084201787
Short name T1129
Test name
Test status
Simulation time 229330813 ps
CPU time 1.01 seconds
Started Jun 24 05:27:56 PM PDT 24
Finished Jun 24 05:28:01 PM PDT 24
Peak memory 206192 kb
Host smart-4bfdfa0c-ec04-41e8-b02f-dbf73db15f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30842
01787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3084201787
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.2650744007
Short name T1339
Test name
Test status
Simulation time 282292066 ps
CPU time 1.02 seconds
Started Jun 24 05:27:56 PM PDT 24
Finished Jun 24 05:28:00 PM PDT 24
Peak memory 206192 kb
Host smart-67cf59e0-4cd6-41a6-9d0e-18622cc75271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26507
44007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2650744007
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.2465793330
Short name T478
Test name
Test status
Simulation time 23369271491 ps
CPU time 20.15 seconds
Started Jun 24 05:27:55 PM PDT 24
Finished Jun 24 05:28:18 PM PDT 24
Peak memory 206252 kb
Host smart-38cf0d83-8dac-449b-8746-4e73409459fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24657
93330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.2465793330
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.2303547893
Short name T780
Test name
Test status
Simulation time 3273027613 ps
CPU time 4.09 seconds
Started Jun 24 05:27:57 PM PDT 24
Finished Jun 24 05:28:04 PM PDT 24
Peak memory 206196 kb
Host smart-0277d184-f3ed-4062-948e-f51dedbf9f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23035
47893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.2303547893
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2141849273
Short name T1435
Test name
Test status
Simulation time 15134253023 ps
CPU time 396.87 seconds
Started Jun 24 05:27:56 PM PDT 24
Finished Jun 24 05:34:36 PM PDT 24
Peak memory 206356 kb
Host smart-ff813e87-f3c2-4a67-b9b4-23954f8c9b90
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2141849273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2141849273
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.1197880209
Short name T616
Test name
Test status
Simulation time 242013791 ps
CPU time 0.89 seconds
Started Jun 24 05:28:08 PM PDT 24
Finished Jun 24 05:28:14 PM PDT 24
Peak memory 206108 kb
Host smart-f80f133e-32f1-47b6-89b9-fa09af12fee8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1197880209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.1197880209
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3110704112
Short name T1753
Test name
Test status
Simulation time 188718322 ps
CPU time 0.86 seconds
Started Jun 24 05:27:55 PM PDT 24
Finished Jun 24 05:27:59 PM PDT 24
Peak memory 206180 kb
Host smart-4458af28-4e0f-4408-81ae-f33ac5dc6cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31107
04112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3110704112
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.3541989445
Short name T1044
Test name
Test status
Simulation time 9547263506 ps
CPU time 63.59 seconds
Started Jun 24 05:27:57 PM PDT 24
Finished Jun 24 05:29:04 PM PDT 24
Peak memory 206284 kb
Host smart-6d331cc6-f65e-4144-9d8b-887f7e5bdc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35419
89445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.3541989445
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.2074061896
Short name T6
Test name
Test status
Simulation time 8229911773 ps
CPU time 64.91 seconds
Started Jun 24 05:28:00 PM PDT 24
Finished Jun 24 05:29:07 PM PDT 24
Peak memory 206360 kb
Host smart-d656accc-58d0-4ec0-820c-423839f5ff14
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2074061896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.2074061896
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.943327287
Short name T875
Test name
Test status
Simulation time 157509974 ps
CPU time 0.78 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:28:12 PM PDT 24
Peak memory 206120 kb
Host smart-9c286a09-ae03-48b6-8b26-7ad9cd1bfa84
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=943327287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.943327287
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1350257615
Short name T1734
Test name
Test status
Simulation time 151667983 ps
CPU time 0.77 seconds
Started Jun 24 05:27:54 PM PDT 24
Finished Jun 24 05:27:58 PM PDT 24
Peak memory 206152 kb
Host smart-e89fa8a4-7d7a-4dbe-965d-dfd7772ff0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13502
57615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1350257615
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.582099674
Short name T1266
Test name
Test status
Simulation time 209800293 ps
CPU time 0.85 seconds
Started Jun 24 05:28:00 PM PDT 24
Finished Jun 24 05:28:03 PM PDT 24
Peak memory 206168 kb
Host smart-2303d679-ab31-489d-923b-342c4d987b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58209
9674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.582099674
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.108404682
Short name T1865
Test name
Test status
Simulation time 185032294 ps
CPU time 0.86 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:28:10 PM PDT 24
Peak memory 206164 kb
Host smart-637c500b-9a41-46c8-8748-aac73fcf7c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10840
4682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.108404682
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.2689894524
Short name T1331
Test name
Test status
Simulation time 198841601 ps
CPU time 0.91 seconds
Started Jun 24 05:28:09 PM PDT 24
Finished Jun 24 05:28:16 PM PDT 24
Peak memory 206156 kb
Host smart-f5bc0bcc-a8bc-4952-bdd1-77b18ce5368d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26898
94524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2689894524
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2830021305
Short name T1918
Test name
Test status
Simulation time 172131564 ps
CPU time 0.77 seconds
Started Jun 24 05:28:05 PM PDT 24
Finished Jun 24 05:28:07 PM PDT 24
Peak memory 206192 kb
Host smart-c3963124-4a83-4311-9c5c-34d5fc1e4097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28300
21305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2830021305
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1045964228
Short name T2131
Test name
Test status
Simulation time 148647136 ps
CPU time 0.78 seconds
Started Jun 24 05:28:04 PM PDT 24
Finished Jun 24 05:28:06 PM PDT 24
Peak memory 206412 kb
Host smart-31626827-895b-422a-b66f-22015d599410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10459
64228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1045964228
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.290994665
Short name T588
Test name
Test status
Simulation time 246579042 ps
CPU time 1 seconds
Started Jun 24 05:28:05 PM PDT 24
Finished Jun 24 05:28:07 PM PDT 24
Peak memory 206100 kb
Host smart-ed39a87d-19e5-404d-b512-f4f5dc1f7257
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=290994665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.290994665
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.890664081
Short name T2
Test name
Test status
Simulation time 148371002 ps
CPU time 0.77 seconds
Started Jun 24 05:28:04 PM PDT 24
Finished Jun 24 05:28:06 PM PDT 24
Peak memory 206192 kb
Host smart-c4955233-a80f-4f8c-a2b8-56bef87469af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89066
4081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.890664081
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2957438910
Short name T970
Test name
Test status
Simulation time 58845029 ps
CPU time 0.72 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:28:12 PM PDT 24
Peak memory 206156 kb
Host smart-36cad391-ac8c-4591-ae09-89341d8f9134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29574
38910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2957438910
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3675399879
Short name T1161
Test name
Test status
Simulation time 22160666272 ps
CPU time 48.44 seconds
Started Jun 24 05:28:05 PM PDT 24
Finished Jun 24 05:28:55 PM PDT 24
Peak memory 206316 kb
Host smart-884666d9-c6e2-48ee-b37f-059d37fab64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36753
99879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3675399879
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3265854387
Short name T718
Test name
Test status
Simulation time 187071935 ps
CPU time 0.82 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:28:09 PM PDT 24
Peak memory 206164 kb
Host smart-d577c484-6e56-4ee1-b4f3-9d3b2b158625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32658
54387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3265854387
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2794738484
Short name T1712
Test name
Test status
Simulation time 196421793 ps
CPU time 0.87 seconds
Started Jun 24 05:28:05 PM PDT 24
Finished Jun 24 05:28:08 PM PDT 24
Peak memory 206180 kb
Host smart-b088cab8-01f1-4760-810e-adc1ee5fb7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27947
38484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2794738484
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.336713529
Short name T2359
Test name
Test status
Simulation time 195416161 ps
CPU time 0.88 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:28:12 PM PDT 24
Peak memory 206168 kb
Host smart-8840ee69-2c03-46e6-bd17-26e30566360a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33671
3529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.336713529
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.2317520334
Short name T964
Test name
Test status
Simulation time 170798183 ps
CPU time 0.85 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:28:09 PM PDT 24
Peak memory 206132 kb
Host smart-77577f63-fb5a-471e-bf4c-ee86e6b6a656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23175
20334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.2317520334
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.3288630264
Short name T1738
Test name
Test status
Simulation time 160792062 ps
CPU time 0.79 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:28:10 PM PDT 24
Peak memory 206188 kb
Host smart-e5f05ac8-1cc8-456c-b1aa-82df74dc2830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32886
30264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.3288630264
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3805765023
Short name T1888
Test name
Test status
Simulation time 160919652 ps
CPU time 0.84 seconds
Started Jun 24 05:28:08 PM PDT 24
Finished Jun 24 05:28:14 PM PDT 24
Peak memory 206148 kb
Host smart-1cd39300-7add-4bd7-8365-727479645527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38057
65023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3805765023
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1211717638
Short name T2479
Test name
Test status
Simulation time 168839083 ps
CPU time 0.78 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:28:09 PM PDT 24
Peak memory 206172 kb
Host smart-6d1661e2-4063-4759-8cb2-b160a9564880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12117
17638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1211717638
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1130563327
Short name T1415
Test name
Test status
Simulation time 208339372 ps
CPU time 0.94 seconds
Started Jun 24 05:28:08 PM PDT 24
Finished Jun 24 05:28:14 PM PDT 24
Peak memory 206192 kb
Host smart-85e6cc12-dea3-405c-aac2-1a9546aa013b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11305
63327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1130563327
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.572848236
Short name T2156
Test name
Test status
Simulation time 4432824285 ps
CPU time 42.49 seconds
Started Jun 24 05:28:04 PM PDT 24
Finished Jun 24 05:28:48 PM PDT 24
Peak memory 206208 kb
Host smart-f9021b35-95d9-46ae-9d66-595c8cd3141d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=572848236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.572848236
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3534364434
Short name T910
Test name
Test status
Simulation time 165688400 ps
CPU time 0.78 seconds
Started Jun 24 05:28:05 PM PDT 24
Finished Jun 24 05:28:08 PM PDT 24
Peak memory 206176 kb
Host smart-2f658919-428b-4195-8bbb-1b0c73089722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35343
64434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3534364434
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.543542459
Short name T1866
Test name
Test status
Simulation time 178071596 ps
CPU time 0.86 seconds
Started Jun 24 05:28:05 PM PDT 24
Finished Jun 24 05:28:08 PM PDT 24
Peak memory 206176 kb
Host smart-405a9674-6e68-4e6c-a9c2-110c9da3f1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54354
2459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.543542459
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.1742230783
Short name T637
Test name
Test status
Simulation time 9198653618 ps
CPU time 68.98 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:29:21 PM PDT 24
Peak memory 206392 kb
Host smart-92f4fd6a-1f73-4c02-a15f-720641b77456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17422
30783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.1742230783
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.2841328143
Short name T11
Test name
Test status
Simulation time 3896227345 ps
CPU time 4.29 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:28:13 PM PDT 24
Peak memory 206216 kb
Host smart-bb6cd436-1531-49dd-bf59-377ccf1f57e2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2841328143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.2841328143
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.406286051
Short name T2349
Test name
Test status
Simulation time 13348247592 ps
CPU time 13.26 seconds
Started Jun 24 05:28:09 PM PDT 24
Finished Jun 24 05:28:28 PM PDT 24
Peak memory 206220 kb
Host smart-37f00832-e4dc-43f7-804a-05ecee2d69f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=406286051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.406286051
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1079956587
Short name T680
Test name
Test status
Simulation time 23301105258 ps
CPU time 26.32 seconds
Started Jun 24 05:28:05 PM PDT 24
Finished Jun 24 05:28:32 PM PDT 24
Peak memory 206240 kb
Host smart-c6c8e621-2ae7-46a2-9829-040d33118114
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1079956587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.1079956587
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3296985135
Short name T552
Test name
Test status
Simulation time 203387049 ps
CPU time 0.82 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:28:10 PM PDT 24
Peak memory 206192 kb
Host smart-f34310b5-6f68-41c5-86a8-3b96780ef945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32969
85135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3296985135
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.1649749060
Short name T2419
Test name
Test status
Simulation time 140773523 ps
CPU time 0.82 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:28:09 PM PDT 24
Peak memory 205996 kb
Host smart-f3a0e9cd-e58a-4684-bab0-8ad39a633f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16497
49060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.1649749060
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.1930987828
Short name T2336
Test name
Test status
Simulation time 335720579 ps
CPU time 1.18 seconds
Started Jun 24 05:28:04 PM PDT 24
Finished Jun 24 05:28:07 PM PDT 24
Peak memory 206148 kb
Host smart-5d25e01e-3fd9-491b-ac44-677d8e5ec816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19309
87828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.1930987828
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3056918635
Short name T1075
Test name
Test status
Simulation time 499344032 ps
CPU time 1.25 seconds
Started Jun 24 05:28:08 PM PDT 24
Finished Jun 24 05:28:15 PM PDT 24
Peak memory 206128 kb
Host smart-c4a283dd-ce91-4611-9cb7-38bfc3937b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30569
18635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3056918635
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.3118353700
Short name T1087
Test name
Test status
Simulation time 13720808554 ps
CPU time 28.14 seconds
Started Jun 24 05:28:04 PM PDT 24
Finished Jun 24 05:28:33 PM PDT 24
Peak memory 206336 kb
Host smart-179ae4ee-2063-45f9-8ece-012e4c37b645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31183
53700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.3118353700
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.381466960
Short name T1048
Test name
Test status
Simulation time 438134651 ps
CPU time 1.24 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:28:10 PM PDT 24
Peak memory 206172 kb
Host smart-ff269531-50f3-4716-9c1e-bbed3a37eb95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38146
6960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.381466960
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.2068007413
Short name T401
Test name
Test status
Simulation time 166022689 ps
CPU time 0.8 seconds
Started Jun 24 05:28:03 PM PDT 24
Finished Jun 24 05:28:05 PM PDT 24
Peak memory 206156 kb
Host smart-5cbc31dc-7ae0-4c3e-a0ab-0c0b3b080338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20680
07413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.2068007413
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2659487686
Short name T1481
Test name
Test status
Simulation time 41311954 ps
CPU time 0.67 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:28:12 PM PDT 24
Peak memory 206172 kb
Host smart-09fa4575-e477-47aa-a7a5-c56ac85f0ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26594
87686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2659487686
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3020606192
Short name T1993
Test name
Test status
Simulation time 748844947 ps
CPU time 1.95 seconds
Started Jun 24 05:28:05 PM PDT 24
Finished Jun 24 05:28:08 PM PDT 24
Peak memory 206248 kb
Host smart-63ef4b9c-a151-4356-88a6-18e5f6650368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30206
06192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3020606192
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1028325551
Short name T2330
Test name
Test status
Simulation time 214446597 ps
CPU time 1.67 seconds
Started Jun 24 05:28:05 PM PDT 24
Finished Jun 24 05:28:08 PM PDT 24
Peak memory 206348 kb
Host smart-f63ebcc9-b32e-4197-b3b6-d5a4c858d4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10283
25551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1028325551
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.553202524
Short name T750
Test name
Test status
Simulation time 203482685 ps
CPU time 0.88 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:28:11 PM PDT 24
Peak memory 206060 kb
Host smart-7da2e98a-4957-4ae1-9728-28c5b03fe1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55320
2524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.553202524
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.4213732685
Short name T2469
Test name
Test status
Simulation time 141747485 ps
CPU time 0.74 seconds
Started Jun 24 05:28:08 PM PDT 24
Finished Jun 24 05:28:14 PM PDT 24
Peak memory 206076 kb
Host smart-c4f303ab-f4ec-44a8-9d79-6f41b48375b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42137
32685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.4213732685
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.69666128
Short name T685
Test name
Test status
Simulation time 259040799 ps
CPU time 0.95 seconds
Started Jun 24 05:28:05 PM PDT 24
Finished Jun 24 05:28:08 PM PDT 24
Peak memory 206192 kb
Host smart-0de823c9-1db5-42b4-9c68-51dc9dc07662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69666
128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.69666128
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.3329879635
Short name T225
Test name
Test status
Simulation time 7116630433 ps
CPU time 50.33 seconds
Started Jun 24 05:28:09 PM PDT 24
Finished Jun 24 05:29:05 PM PDT 24
Peak memory 206372 kb
Host smart-ebde84e6-19d1-4ecd-a919-d0abc395e2b4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3329879635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.3329879635
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.2686857855
Short name T676
Test name
Test status
Simulation time 238587135 ps
CPU time 0.91 seconds
Started Jun 24 05:28:09 PM PDT 24
Finished Jun 24 05:28:15 PM PDT 24
Peak memory 206164 kb
Host smart-f1ab4a41-f9af-4ac5-baf9-c05db3ea14a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26868
57855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.2686857855
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.1022915472
Short name T398
Test name
Test status
Simulation time 23287950254 ps
CPU time 29.08 seconds
Started Jun 24 05:28:08 PM PDT 24
Finished Jun 24 05:28:42 PM PDT 24
Peak memory 206256 kb
Host smart-79c533c1-25bd-447c-895f-fc7e18d84752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10229
15472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.1022915472
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3403781183
Short name T1576
Test name
Test status
Simulation time 3315232302 ps
CPU time 3.78 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:28:14 PM PDT 24
Peak memory 206192 kb
Host smart-8bb5e0cc-d0c6-4a5a-9947-2695e5033dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34037
81183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3403781183
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.2612352041
Short name T579
Test name
Test status
Simulation time 9749522915 ps
CPU time 282.66 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:32:53 PM PDT 24
Peak memory 206360 kb
Host smart-79ad31a2-4eb0-4f35-b434-a2d8d3a70d25
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2612352041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.2612352041
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.3497030205
Short name T373
Test name
Test status
Simulation time 242379451 ps
CPU time 0.91 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:28:13 PM PDT 24
Peak memory 206188 kb
Host smart-8449ea08-7fc3-489c-8f50-fb9c16eab634
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3497030205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.3497030205
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3092633782
Short name T1745
Test name
Test status
Simulation time 192548193 ps
CPU time 0.85 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:28:09 PM PDT 24
Peak memory 206112 kb
Host smart-3104b67d-b952-4236-afe1-f47540981cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30926
33782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3092633782
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.965334253
Short name T572
Test name
Test status
Simulation time 4908281041 ps
CPU time 36.85 seconds
Started Jun 24 05:28:04 PM PDT 24
Finished Jun 24 05:28:42 PM PDT 24
Peak memory 206624 kb
Host smart-e58566ab-3592-46ae-9c57-d50414a17462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96533
4253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.965334253
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.177185744
Short name T1246
Test name
Test status
Simulation time 8102257936 ps
CPU time 61.23 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:29:11 PM PDT 24
Peak memory 206364 kb
Host smart-2d5eac4a-9e0c-4b01-bdab-91e0d97d515b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=177185744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.177185744
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1903629243
Short name T1628
Test name
Test status
Simulation time 152627874 ps
CPU time 0.78 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:28:11 PM PDT 24
Peak memory 206124 kb
Host smart-083b6714-b3e2-4a0d-a1a0-fcdc091a94c8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1903629243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1903629243
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1509603011
Short name T1602
Test name
Test status
Simulation time 152613770 ps
CPU time 0.76 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:28:09 PM PDT 24
Peak memory 206128 kb
Host smart-6264e5ad-1a3c-4bec-917a-e26ba716a1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15096
03011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1509603011
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.3371429547
Short name T1759
Test name
Test status
Simulation time 192814232 ps
CPU time 0.81 seconds
Started Jun 24 05:28:05 PM PDT 24
Finished Jun 24 05:28:08 PM PDT 24
Peak memory 206176 kb
Host smart-6612b217-cc31-49e6-ac7e-c1e83655ba17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33714
29547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.3371429547
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.4261071068
Short name T2379
Test name
Test status
Simulation time 183988157 ps
CPU time 0.8 seconds
Started Jun 24 05:28:04 PM PDT 24
Finished Jun 24 05:28:05 PM PDT 24
Peak memory 206192 kb
Host smart-a028ec47-4bc1-4c07-ba62-e3cdc1ee9d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42610
71068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.4261071068
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1456418284
Short name T420
Test name
Test status
Simulation time 161474133 ps
CPU time 0.84 seconds
Started Jun 24 05:28:08 PM PDT 24
Finished Jun 24 05:28:14 PM PDT 24
Peak memory 206064 kb
Host smart-a26ff7bc-dfee-450c-8f7b-fe7d91eb51b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14564
18284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1456418284
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3629310044
Short name T396
Test name
Test status
Simulation time 178807664 ps
CPU time 0.77 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:28:12 PM PDT 24
Peak memory 206172 kb
Host smart-a7583293-3993-41eb-aca9-e1f46987520c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36293
10044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3629310044
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1904197316
Short name T667
Test name
Test status
Simulation time 154385185 ps
CPU time 0.8 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:28:12 PM PDT 24
Peak memory 206176 kb
Host smart-1565a321-25a1-4235-8097-9d2582141bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19041
97316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1904197316
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.3262580808
Short name T1834
Test name
Test status
Simulation time 202954356 ps
CPU time 0.95 seconds
Started Jun 24 05:28:09 PM PDT 24
Finished Jun 24 05:28:15 PM PDT 24
Peak memory 206084 kb
Host smart-03a1425f-4e03-4ed2-afa4-2573652f8569
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3262580808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.3262580808
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.482220370
Short name T1514
Test name
Test status
Simulation time 143192961 ps
CPU time 0.75 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:28:09 PM PDT 24
Peak memory 206052 kb
Host smart-f196ed62-731c-4697-8d56-7d836d32a1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48222
0370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.482220370
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.240301138
Short name T1765
Test name
Test status
Simulation time 31621073 ps
CPU time 0.71 seconds
Started Jun 24 05:28:09 PM PDT 24
Finished Jun 24 05:28:16 PM PDT 24
Peak memory 206180 kb
Host smart-4cc359b3-aaab-43d5-a9c7-5fb333853bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24030
1138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.240301138
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.3570441749
Short name T91
Test name
Test status
Simulation time 11034605138 ps
CPU time 23.92 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:28:33 PM PDT 24
Peak memory 206396 kb
Host smart-618199f9-21e1-40cc-b7ff-f3284841deff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35704
41749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3570441749
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.757680597
Short name T1051
Test name
Test status
Simulation time 253690696 ps
CPU time 0.96 seconds
Started Jun 24 05:28:08 PM PDT 24
Finished Jun 24 05:28:13 PM PDT 24
Peak memory 206180 kb
Host smart-043d8e94-1241-43ca-8046-fbffe7a954b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75768
0597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.757680597
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.451760501
Short name T1604
Test name
Test status
Simulation time 237515770 ps
CPU time 1.01 seconds
Started Jun 24 05:28:08 PM PDT 24
Finished Jun 24 05:28:15 PM PDT 24
Peak memory 206112 kb
Host smart-a04306be-8bd4-4b0d-9e66-8a1b1876e692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45176
0501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.451760501
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.964127253
Short name T423
Test name
Test status
Simulation time 203784528 ps
CPU time 0.9 seconds
Started Jun 24 05:28:08 PM PDT 24
Finished Jun 24 05:28:14 PM PDT 24
Peak memory 206188 kb
Host smart-d9d14d23-21ef-44df-8054-3185faa8dbbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96412
7253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.964127253
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.1817144874
Short name T2294
Test name
Test status
Simulation time 195299723 ps
CPU time 0.81 seconds
Started Jun 24 05:28:06 PM PDT 24
Finished Jun 24 05:28:10 PM PDT 24
Peak memory 206208 kb
Host smart-d3204809-8ac3-4b72-bb0a-ce7d2ff583cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18171
44874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.1817144874
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3248571196
Short name T1242
Test name
Test status
Simulation time 142640194 ps
CPU time 0.75 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:28:12 PM PDT 24
Peak memory 206072 kb
Host smart-4bf1842b-1445-4b5f-82e0-7a725bff37de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32485
71196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3248571196
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1701537260
Short name T2374
Test name
Test status
Simulation time 152052859 ps
CPU time 0.8 seconds
Started Jun 24 05:28:08 PM PDT 24
Finished Jun 24 05:28:14 PM PDT 24
Peak memory 206104 kb
Host smart-a210e0c4-66a6-454e-83e4-29d1b668766d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17015
37260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1701537260
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.61735459
Short name T2022
Test name
Test status
Simulation time 198667464 ps
CPU time 0.81 seconds
Started Jun 24 05:28:08 PM PDT 24
Finished Jun 24 05:28:14 PM PDT 24
Peak memory 206164 kb
Host smart-527b27f5-9fcd-4942-9a7c-25df1860625d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61735
459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.61735459
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.563944787
Short name T1483
Test name
Test status
Simulation time 231304731 ps
CPU time 0.94 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:28:13 PM PDT 24
Peak memory 206076 kb
Host smart-d2b7d878-07e3-4b8d-b749-5aa6a2492ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56394
4787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.563944787
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1669697172
Short name T2004
Test name
Test status
Simulation time 208311629 ps
CPU time 0.89 seconds
Started Jun 24 05:28:09 PM PDT 24
Finished Jun 24 05:28:15 PM PDT 24
Peak memory 206152 kb
Host smart-ebf3277b-2117-4732-832a-a1c027a052c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16696
97172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1669697172
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1093086912
Short name T1220
Test name
Test status
Simulation time 171192352 ps
CPU time 0.82 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:28:11 PM PDT 24
Peak memory 206188 kb
Host smart-fc16018a-4cd3-4c0e-9023-5a778ac2b507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10930
86912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1093086912
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.999050633
Short name T1212
Test name
Test status
Simulation time 9407592720 ps
CPU time 87.21 seconds
Started Jun 24 05:28:07 PM PDT 24
Finished Jun 24 05:29:37 PM PDT 24
Peak memory 206324 kb
Host smart-8201e28d-109e-4c06-9e87-04db0345e9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99905
0633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.999050633
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.2513055490
Short name T1663
Test name
Test status
Simulation time 3994576838 ps
CPU time 5.54 seconds
Started Jun 24 05:20:58 PM PDT 24
Finished Jun 24 05:21:08 PM PDT 24
Peak memory 206260 kb
Host smart-5c85467a-fd84-4c83-bdc5-c9673caec02f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2513055490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.2513055490
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3018477344
Short name T1557
Test name
Test status
Simulation time 13340071684 ps
CPU time 14.63 seconds
Started Jun 24 05:20:58 PM PDT 24
Finished Jun 24 05:21:17 PM PDT 24
Peak memory 206232 kb
Host smart-0ee1dfed-05a7-4616-824f-4cbe7fabcb58
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3018477344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3018477344
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.967737025
Short name T835
Test name
Test status
Simulation time 23378085371 ps
CPU time 26.63 seconds
Started Jun 24 05:20:59 PM PDT 24
Finished Jun 24 05:21:30 PM PDT 24
Peak memory 206264 kb
Host smart-f08d7506-6712-4218-b9f1-75ba5db24978
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=967737025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.967737025
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.3467822858
Short name T2005
Test name
Test status
Simulation time 166232325 ps
CPU time 0.83 seconds
Started Jun 24 05:20:57 PM PDT 24
Finished Jun 24 05:21:03 PM PDT 24
Peak memory 206168 kb
Host smart-733beb88-e082-4674-98a6-72916ec6559f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34678
22858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3467822858
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.954423232
Short name T1049
Test name
Test status
Simulation time 173167691 ps
CPU time 0.88 seconds
Started Jun 24 05:21:03 PM PDT 24
Finished Jun 24 05:21:06 PM PDT 24
Peak memory 206072 kb
Host smart-9e3c913d-be96-4bce-b7a4-cc6946f9813b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95442
3232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.954423232
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.2744598619
Short name T1095
Test name
Test status
Simulation time 205945380 ps
CPU time 0.9 seconds
Started Jun 24 05:21:06 PM PDT 24
Finished Jun 24 05:21:09 PM PDT 24
Peak memory 206176 kb
Host smart-eada90a2-1a11-4602-8b9f-b5345e036bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27445
98619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.2744598619
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.708437701
Short name T1112
Test name
Test status
Simulation time 361908573 ps
CPU time 1.15 seconds
Started Jun 24 05:21:04 PM PDT 24
Finished Jun 24 05:21:08 PM PDT 24
Peak memory 206100 kb
Host smart-8e73f3d9-0ba7-409c-8b68-a5d36082207e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70843
7701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.708437701
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.2513566495
Short name T1729
Test name
Test status
Simulation time 14855889982 ps
CPU time 27.34 seconds
Started Jun 24 05:21:05 PM PDT 24
Finished Jun 24 05:21:35 PM PDT 24
Peak memory 206320 kb
Host smart-2a926a4b-8ffc-4f55-8f67-601169fffd03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25135
66495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.2513566495
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.962721084
Short name T375
Test name
Test status
Simulation time 431822915 ps
CPU time 1.35 seconds
Started Jun 24 05:21:03 PM PDT 24
Finished Jun 24 05:21:06 PM PDT 24
Peak memory 206180 kb
Host smart-7e1e538c-0975-4d60-9043-3a3fd604ca92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96272
1084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.962721084
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.3761309711
Short name T1236
Test name
Test status
Simulation time 138317750 ps
CPU time 0.73 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:17 PM PDT 24
Peak memory 206172 kb
Host smart-16f4c46f-73c2-4c98-b4bc-1b92849b8272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37613
09711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3761309711
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2211780278
Short name T1497
Test name
Test status
Simulation time 59466919 ps
CPU time 0.68 seconds
Started Jun 24 05:21:07 PM PDT 24
Finished Jun 24 05:21:10 PM PDT 24
Peak memory 206168 kb
Host smart-d5eb43d4-ed54-47dc-b904-ce602bfc59ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22117
80278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2211780278
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.2778300584
Short name T2122
Test name
Test status
Simulation time 786518102 ps
CPU time 2.17 seconds
Started Jun 24 05:21:03 PM PDT 24
Finished Jun 24 05:21:07 PM PDT 24
Peak memory 206288 kb
Host smart-b8ae3fc8-f9fe-4b1c-b0bb-da4f6afd4bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27783
00584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.2778300584
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1021136689
Short name T1115
Test name
Test status
Simulation time 292662725 ps
CPU time 2.16 seconds
Started Jun 24 05:21:04 PM PDT 24
Finished Jun 24 05:21:08 PM PDT 24
Peak memory 206320 kb
Host smart-9ceab327-9970-4b73-9b3f-3b852f3a8b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10211
36689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1021136689
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3916261616
Short name T1089
Test name
Test status
Simulation time 177810757 ps
CPU time 0.85 seconds
Started Jun 24 05:21:05 PM PDT 24
Finished Jun 24 05:21:08 PM PDT 24
Peak memory 206172 kb
Host smart-ee6853c0-b4b6-49d6-88c0-ec822d997c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39162
61616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3916261616
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.892877847
Short name T1928
Test name
Test status
Simulation time 168518567 ps
CPU time 0.84 seconds
Started Jun 24 05:21:07 PM PDT 24
Finished Jun 24 05:21:10 PM PDT 24
Peak memory 205604 kb
Host smart-0a3feaec-f3a4-4046-b2e6-691705f32849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89287
7847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.892877847
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1672210488
Short name T2433
Test name
Test status
Simulation time 169663750 ps
CPU time 0.86 seconds
Started Jun 24 05:21:05 PM PDT 24
Finished Jun 24 05:21:08 PM PDT 24
Peak memory 206192 kb
Host smart-8e4d0ced-19dd-4db9-bd8a-c22954d05434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16722
10488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1672210488
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.3905725050
Short name T1480
Test name
Test status
Simulation time 241175690 ps
CPU time 0.92 seconds
Started Jun 24 05:21:07 PM PDT 24
Finished Jun 24 05:21:10 PM PDT 24
Peak memory 206192 kb
Host smart-0ba300ba-c4d0-40c8-8617-6557acdeb8fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39057
25050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.3905725050
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.3297099757
Short name T1914
Test name
Test status
Simulation time 23325072070 ps
CPU time 22.77 seconds
Started Jun 24 05:21:04 PM PDT 24
Finished Jun 24 05:21:29 PM PDT 24
Peak memory 206216 kb
Host smart-734ec1cd-0b50-46c0-bfb3-57f435b2c23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32970
99757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.3297099757
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.233517117
Short name T706
Test name
Test status
Simulation time 3283198911 ps
CPU time 3.42 seconds
Started Jun 24 05:21:05 PM PDT 24
Finished Jun 24 05:21:11 PM PDT 24
Peak memory 206256 kb
Host smart-f4f5e114-f590-4b05-a554-79ff62502f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23351
7117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.233517117
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.3657881894
Short name T1535
Test name
Test status
Simulation time 5333626408 ps
CPU time 145.97 seconds
Started Jun 24 05:21:01 PM PDT 24
Finished Jun 24 05:23:30 PM PDT 24
Peak memory 206396 kb
Host smart-bc29b705-94f6-4ed8-8b30-069dcb602722
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3657881894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.3657881894
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.3284138517
Short name T2068
Test name
Test status
Simulation time 237774032 ps
CPU time 0.96 seconds
Started Jun 24 05:21:14 PM PDT 24
Finished Jun 24 05:21:18 PM PDT 24
Peak memory 206160 kb
Host smart-56e786c6-3e46-420a-b61f-a85adf9067da
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3284138517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.3284138517
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.408561675
Short name T327
Test name
Test status
Simulation time 191851555 ps
CPU time 0.83 seconds
Started Jun 24 05:21:04 PM PDT 24
Finished Jun 24 05:21:07 PM PDT 24
Peak memory 206076 kb
Host smart-14634451-2d12-48e6-9433-aff5f630d713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40856
1675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.408561675
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.366732777
Short name T1062
Test name
Test status
Simulation time 5273871453 ps
CPU time 35.2 seconds
Started Jun 24 05:21:12 PM PDT 24
Finished Jun 24 05:21:49 PM PDT 24
Peak memory 206344 kb
Host smart-57961459-095f-49f7-88a0-155fb1f90d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36673
2777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.366732777
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.4053180222
Short name T2360
Test name
Test status
Simulation time 10684237969 ps
CPU time 303.77 seconds
Started Jun 24 05:21:08 PM PDT 24
Finished Jun 24 05:26:14 PM PDT 24
Peak memory 206388 kb
Host smart-0e8e56e1-762d-4097-ad3d-fa64e84bf40a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4053180222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.4053180222
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.35926960
Short name T528
Test name
Test status
Simulation time 159470277 ps
CPU time 0.89 seconds
Started Jun 24 05:21:14 PM PDT 24
Finished Jun 24 05:21:18 PM PDT 24
Peak memory 206064 kb
Host smart-c1ba0b93-a157-43e6-9e28-49d55d36ecad
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=35926960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.35926960
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1867002890
Short name T2454
Test name
Test status
Simulation time 156076847 ps
CPU time 0.78 seconds
Started Jun 24 05:21:07 PM PDT 24
Finished Jun 24 05:21:10 PM PDT 24
Peak memory 205656 kb
Host smart-d358985d-398d-4aff-83b8-b74b9d44fa73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18670
02890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1867002890
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1905232681
Short name T1811
Test name
Test status
Simulation time 205271146 ps
CPU time 0.83 seconds
Started Jun 24 05:21:08 PM PDT 24
Finished Jun 24 05:21:10 PM PDT 24
Peak memory 206168 kb
Host smart-dec6d292-783f-4804-8020-3fa725e05c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19052
32681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1905232681
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.537502927
Short name T466
Test name
Test status
Simulation time 188298836 ps
CPU time 0.79 seconds
Started Jun 24 05:21:06 PM PDT 24
Finished Jun 24 05:21:09 PM PDT 24
Peak memory 206172 kb
Host smart-baf3a51a-002c-4976-8c8a-62a88c443f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53750
2927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.537502927
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3918434213
Short name T2261
Test name
Test status
Simulation time 157590080 ps
CPU time 0.76 seconds
Started Jun 24 05:21:01 PM PDT 24
Finished Jun 24 05:21:05 PM PDT 24
Peak memory 206188 kb
Host smart-c49691e4-7dc2-432e-a6b1-28c07ebb222a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39184
34213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3918434213
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2617327141
Short name T597
Test name
Test status
Simulation time 166249004 ps
CPU time 0.76 seconds
Started Jun 24 05:21:12 PM PDT 24
Finished Jun 24 05:21:14 PM PDT 24
Peak memory 206168 kb
Host smart-b7c90ed3-5447-40d0-a649-2c96f0450add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26173
27141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2617327141
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3734160555
Short name T195
Test name
Test status
Simulation time 194163064 ps
CPU time 0.86 seconds
Started Jun 24 05:21:05 PM PDT 24
Finished Jun 24 05:21:08 PM PDT 24
Peak memory 206156 kb
Host smart-dd08440b-23bb-4cb4-b707-10a65dbfa886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37341
60555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3734160555
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2440617723
Short name T2338
Test name
Test status
Simulation time 210712783 ps
CPU time 0.91 seconds
Started Jun 24 05:21:08 PM PDT 24
Finished Jun 24 05:21:11 PM PDT 24
Peak memory 206176 kb
Host smart-16d5f291-32da-4d78-a407-ea7f9f04597f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2440617723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2440617723
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.1495360629
Short name T2475
Test name
Test status
Simulation time 201604530 ps
CPU time 0.84 seconds
Started Jun 24 05:21:05 PM PDT 24
Finished Jun 24 05:21:08 PM PDT 24
Peak memory 206092 kb
Host smart-94d586f7-e487-4e75-881a-a088f8a1e9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14953
60629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1495360629
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.480035631
Short name T1384
Test name
Test status
Simulation time 54721640 ps
CPU time 0.71 seconds
Started Jun 24 05:21:07 PM PDT 24
Finished Jun 24 05:21:10 PM PDT 24
Peak memory 206184 kb
Host smart-6fd2080b-fb28-4377-a5a7-57d14669bc1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48003
5631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.480035631
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2576795740
Short name T257
Test name
Test status
Simulation time 7509334426 ps
CPU time 16.96 seconds
Started Jun 24 05:21:06 PM PDT 24
Finished Jun 24 05:21:25 PM PDT 24
Peak memory 206332 kb
Host smart-77e720cf-257b-4be2-b7ef-eb1b039d0c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25767
95740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2576795740
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.781426998
Short name T1471
Test name
Test status
Simulation time 162926364 ps
CPU time 0.81 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:16 PM PDT 24
Peak memory 206188 kb
Host smart-0705f4aa-1b6d-4eee-be41-3faae478067a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78142
6998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.781426998
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1414127668
Short name T220
Test name
Test status
Simulation time 213178086 ps
CPU time 0.83 seconds
Started Jun 24 05:21:12 PM PDT 24
Finished Jun 24 05:21:15 PM PDT 24
Peak memory 206192 kb
Host smart-481ca3fe-30ce-4a7f-bacc-68d20aae8592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14141
27668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1414127668
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.1851340682
Short name T426
Test name
Test status
Simulation time 15418433209 ps
CPU time 112.9 seconds
Started Jun 24 05:21:05 PM PDT 24
Finished Jun 24 05:23:00 PM PDT 24
Peak memory 206356 kb
Host smart-5f4046d5-2fa0-4bdc-8fb0-b5f7fa117761
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1851340682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1851340682
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.3761071724
Short name T192
Test name
Test status
Simulation time 11375772842 ps
CPU time 102.45 seconds
Started Jun 24 05:21:04 PM PDT 24
Finished Jun 24 05:22:49 PM PDT 24
Peak memory 206300 kb
Host smart-72cb3d9a-f92c-4c99-a729-d9f6e0758ae8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3761071724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.3761071724
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.2279609809
Short name T2342
Test name
Test status
Simulation time 41878410792 ps
CPU time 280.37 seconds
Started Jun 24 05:21:04 PM PDT 24
Finished Jun 24 05:25:46 PM PDT 24
Peak memory 206360 kb
Host smart-b7ee6a6b-775d-485c-a892-8452708d0d3b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2279609809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.2279609809
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.1649076067
Short name T1616
Test name
Test status
Simulation time 244106124 ps
CPU time 0.93 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:16 PM PDT 24
Peak memory 206200 kb
Host smart-83d69164-3662-4364-860d-148f03232622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16490
76067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.1649076067
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1800224811
Short name T1686
Test name
Test status
Simulation time 197910463 ps
CPU time 0.81 seconds
Started Jun 24 05:21:06 PM PDT 24
Finished Jun 24 05:21:09 PM PDT 24
Peak memory 206160 kb
Host smart-db128438-df8e-492e-bd55-fc34a4ecd7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18002
24811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1800224811
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.487733640
Short name T2321
Test name
Test status
Simulation time 144461477 ps
CPU time 0.77 seconds
Started Jun 24 05:21:04 PM PDT 24
Finished Jun 24 05:21:07 PM PDT 24
Peak memory 206176 kb
Host smart-b8343f6b-f9c8-4a66-994b-2d80a1d53de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48773
3640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.487733640
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1196535295
Short name T634
Test name
Test status
Simulation time 208171153 ps
CPU time 0.78 seconds
Started Jun 24 05:21:06 PM PDT 24
Finished Jun 24 05:21:09 PM PDT 24
Peak memory 206184 kb
Host smart-f022dbc5-2734-412b-b498-54862d1de363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11965
35295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1196535295
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3061414992
Short name T1703
Test name
Test status
Simulation time 153152244 ps
CPU time 0.79 seconds
Started Jun 24 05:21:06 PM PDT 24
Finished Jun 24 05:21:09 PM PDT 24
Peak memory 206168 kb
Host smart-ae1911d5-c13b-4eea-b19c-f08a68e7a7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30614
14992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3061414992
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.602509983
Short name T2132
Test name
Test status
Simulation time 217646146 ps
CPU time 0.88 seconds
Started Jun 24 05:21:03 PM PDT 24
Finished Jun 24 05:21:06 PM PDT 24
Peak memory 206168 kb
Host smart-034074a5-28f5-4939-b8fb-5657384987e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60250
9983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.602509983
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.3595420458
Short name T1091
Test name
Test status
Simulation time 10490006446 ps
CPU time 103.55 seconds
Started Jun 24 05:21:08 PM PDT 24
Finished Jun 24 05:22:54 PM PDT 24
Peak memory 206300 kb
Host smart-cbb84975-a432-4e1f-ac82-fb7067b771e0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3595420458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.3595420458
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.4279461554
Short name T513
Test name
Test status
Simulation time 186048835 ps
CPU time 0.8 seconds
Started Jun 24 05:21:04 PM PDT 24
Finished Jun 24 05:21:07 PM PDT 24
Peak memory 206172 kb
Host smart-44486400-4eb8-414c-8d17-5d13637fa85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42794
61554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.4279461554
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3746947771
Short name T1050
Test name
Test status
Simulation time 186605062 ps
CPU time 0.79 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:17 PM PDT 24
Peak memory 206192 kb
Host smart-8eb19ab5-1c59-4cd4-a947-e63983a43956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37469
47771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3746947771
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.769891742
Short name T1333
Test name
Test status
Simulation time 9809367953 ps
CPU time 97.87 seconds
Started Jun 24 05:21:06 PM PDT 24
Finished Jun 24 05:22:46 PM PDT 24
Peak memory 206340 kb
Host smart-577dae7f-88e6-4fda-83bc-465aefcd6b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76989
1742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.769891742
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3632423228
Short name T2425
Test name
Test status
Simulation time 4061139913 ps
CPU time 5.72 seconds
Started Jun 24 05:21:12 PM PDT 24
Finished Jun 24 05:21:19 PM PDT 24
Peak memory 206320 kb
Host smart-54d7fa0e-d134-4c7c-bf2a-aa34879d4408
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3632423228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.3632423228
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.2629207621
Short name T819
Test name
Test status
Simulation time 13359639411 ps
CPU time 15.44 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:31 PM PDT 24
Peak memory 206308 kb
Host smart-57dbd5eb-2bd9-4d6d-8098-f96bb0c10851
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2629207621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.2629207621
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.1798935681
Short name T2063
Test name
Test status
Simulation time 23421505380 ps
CPU time 29.11 seconds
Started Jun 24 05:21:14 PM PDT 24
Finished Jun 24 05:21:46 PM PDT 24
Peak memory 206572 kb
Host smart-0b78bdf7-f616-48ac-8487-dfa8f81d74de
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1798935681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.1798935681
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2836380799
Short name T369
Test name
Test status
Simulation time 221143448 ps
CPU time 0.87 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:16 PM PDT 24
Peak memory 206056 kb
Host smart-06d6cf39-c3ca-4dbe-befe-046004139478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28363
80799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2836380799
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.2929354788
Short name T1364
Test name
Test status
Simulation time 178589575 ps
CPU time 0.77 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:17 PM PDT 24
Peak memory 206176 kb
Host smart-daaeddd0-45e6-4921-a47b-99c25e6f598f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29293
54788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.2929354788
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.2440713966
Short name T3
Test name
Test status
Simulation time 333688757 ps
CPU time 1.2 seconds
Started Jun 24 05:21:12 PM PDT 24
Finished Jun 24 05:21:14 PM PDT 24
Peak memory 206144 kb
Host smart-41249fae-8c28-452e-9d09-dd4c6fb53c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24407
13966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.2440713966
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.2016275332
Short name T429
Test name
Test status
Simulation time 1013512312 ps
CPU time 2.35 seconds
Started Jun 24 05:21:14 PM PDT 24
Finished Jun 24 05:21:19 PM PDT 24
Peak memory 206200 kb
Host smart-54a43e56-c399-468f-b5af-575b49e505f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20162
75332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2016275332
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.93172522
Short name T1690
Test name
Test status
Simulation time 13636310373 ps
CPU time 30.22 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:45 PM PDT 24
Peak memory 206276 kb
Host smart-1f140322-a5ca-4105-be7c-d4a083b981d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93172
522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.93172522
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.579195044
Short name T900
Test name
Test status
Simulation time 476944483 ps
CPU time 1.44 seconds
Started Jun 24 05:21:18 PM PDT 24
Finished Jun 24 05:21:21 PM PDT 24
Peak memory 206164 kb
Host smart-49d1698c-faa9-4156-a14c-96a0b9464648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57919
5044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.579195044
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.447344676
Short name T44
Test name
Test status
Simulation time 207242843 ps
CPU time 0.78 seconds
Started Jun 24 05:21:14 PM PDT 24
Finished Jun 24 05:21:17 PM PDT 24
Peak memory 206188 kb
Host smart-e957cd79-da25-4d83-8ef9-d2bec6a99d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44734
4676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.447344676
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3381674999
Short name T239
Test name
Test status
Simulation time 35115880 ps
CPU time 0.64 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:15 PM PDT 24
Peak memory 206184 kb
Host smart-5700a9dc-d350-41af-b271-5811aae2c003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33816
74999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3381674999
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.2181887201
Short name T2378
Test name
Test status
Simulation time 792019790 ps
CPU time 1.94 seconds
Started Jun 24 05:21:14 PM PDT 24
Finished Jun 24 05:21:19 PM PDT 24
Peak memory 206328 kb
Host smart-0925478c-20cf-4022-8f12-db2947398262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21818
87201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.2181887201
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2267044471
Short name T2432
Test name
Test status
Simulation time 256723446 ps
CPU time 1.64 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:17 PM PDT 24
Peak memory 206160 kb
Host smart-52124bb4-72a1-4b7c-82f0-68c8df6c8de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22670
44471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2267044471
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2166536940
Short name T512
Test name
Test status
Simulation time 189235410 ps
CPU time 0.94 seconds
Started Jun 24 05:21:27 PM PDT 24
Finished Jun 24 05:21:30 PM PDT 24
Peak memory 206176 kb
Host smart-c522bf0e-330a-402a-9857-b6e626178f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21665
36940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2166536940
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2515105113
Short name T957
Test name
Test status
Simulation time 153761087 ps
CPU time 0.76 seconds
Started Jun 24 05:21:20 PM PDT 24
Finished Jun 24 05:21:23 PM PDT 24
Peak memory 206200 kb
Host smart-02b5f2b0-c55d-493b-a219-ea2e805d31eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25151
05113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2515105113
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1876805245
Short name T1271
Test name
Test status
Simulation time 192739214 ps
CPU time 0.87 seconds
Started Jun 24 05:21:12 PM PDT 24
Finished Jun 24 05:21:15 PM PDT 24
Peak memory 206156 kb
Host smart-9048a9f3-6efd-43b4-a004-5cc9e4999953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18768
05245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1876805245
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.903163570
Short name T74
Test name
Test status
Simulation time 18430628021 ps
CPU time 133.98 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:23:30 PM PDT 24
Peak memory 206272 kb
Host smart-39f22762-c83a-460f-b4a7-b61c4bda7dc9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=903163570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.903163570
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.2339253750
Short name T380
Test name
Test status
Simulation time 215006998 ps
CPU time 0.9 seconds
Started Jun 24 05:21:18 PM PDT 24
Finished Jun 24 05:21:20 PM PDT 24
Peak memory 206172 kb
Host smart-d6f1cdef-cb71-44e0-9e9d-3b1bd612e6c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23392
53750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2339253750
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.2568620870
Short name T609
Test name
Test status
Simulation time 23329794173 ps
CPU time 27.32 seconds
Started Jun 24 05:21:14 PM PDT 24
Finished Jun 24 05:21:44 PM PDT 24
Peak memory 206232 kb
Host smart-87da38c8-243f-4238-96a1-3523c1743351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25686
20870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.2568620870
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.500177219
Short name T1782
Test name
Test status
Simulation time 3368943821 ps
CPU time 3.84 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:18 PM PDT 24
Peak memory 206188 kb
Host smart-f7eab766-bbd6-41c9-a26d-64257fa03238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50017
7219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.500177219
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.3587713157
Short name T1211
Test name
Test status
Simulation time 5228149607 ps
CPU time 154.41 seconds
Started Jun 24 05:21:14 PM PDT 24
Finished Jun 24 05:23:51 PM PDT 24
Peak memory 206320 kb
Host smart-0f54ce4d-ca04-4bb8-b2c2-653970c40f14
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3587713157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.3587713157
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.4185078278
Short name T1816
Test name
Test status
Simulation time 283959884 ps
CPU time 0.98 seconds
Started Jun 24 05:21:22 PM PDT 24
Finished Jun 24 05:21:26 PM PDT 24
Peak memory 206120 kb
Host smart-b4e61b55-489a-41b9-9873-2f296be3fb0e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4185078278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.4185078278
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2743033943
Short name T753
Test name
Test status
Simulation time 198151613 ps
CPU time 0.9 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:17 PM PDT 24
Peak memory 206196 kb
Host smart-204d5abb-8575-429f-8f74-9ee941dd3b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27430
33943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2743033943
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2661096235
Short name T1539
Test name
Test status
Simulation time 13981954187 ps
CPU time 388.09 seconds
Started Jun 24 05:21:12 PM PDT 24
Finished Jun 24 05:27:42 PM PDT 24
Peak memory 206256 kb
Host smart-5b5c981f-8718-4344-a35d-4004c1b6bc6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26610
96235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2661096235
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.2386776260
Short name T315
Test name
Test status
Simulation time 10765006609 ps
CPU time 106.77 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:23:01 PM PDT 24
Peak memory 206328 kb
Host smart-84f6398f-8eda-4d84-9c33-fa1db80a3c0d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2386776260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.2386776260
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.917763949
Short name T1098
Test name
Test status
Simulation time 166633708 ps
CPU time 0.78 seconds
Started Jun 24 05:21:22 PM PDT 24
Finished Jun 24 05:21:25 PM PDT 24
Peak memory 206096 kb
Host smart-c54ebc89-e5d6-49a6-865b-2e89ccc88fbf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=917763949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.917763949
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3927363565
Short name T602
Test name
Test status
Simulation time 215707838 ps
CPU time 0.87 seconds
Started Jun 24 05:21:12 PM PDT 24
Finished Jun 24 05:21:13 PM PDT 24
Peak memory 206192 kb
Host smart-12777112-8847-40c4-abad-d129d2039cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39273
63565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3927363565
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3030117072
Short name T123
Test name
Test status
Simulation time 255859666 ps
CPU time 0.94 seconds
Started Jun 24 05:21:15 PM PDT 24
Finished Jun 24 05:21:18 PM PDT 24
Peak memory 206128 kb
Host smart-719c0473-c6a4-418d-9acc-c2a855f9721f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30301
17072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3030117072
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.3122242614
Short name T908
Test name
Test status
Simulation time 219175859 ps
CPU time 0.92 seconds
Started Jun 24 05:21:15 PM PDT 24
Finished Jun 24 05:21:18 PM PDT 24
Peak memory 206424 kb
Host smart-53ec1d5e-0721-4276-9bd5-cf075866cc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31222
42614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3122242614
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3759864833
Short name T1909
Test name
Test status
Simulation time 158762040 ps
CPU time 0.8 seconds
Started Jun 24 05:21:14 PM PDT 24
Finished Jun 24 05:21:18 PM PDT 24
Peak memory 206168 kb
Host smart-5b867df5-63a3-46b0-8397-736abdd3005b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37598
64833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3759864833
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1177631061
Short name T983
Test name
Test status
Simulation time 159885298 ps
CPU time 0.8 seconds
Started Jun 24 05:21:16 PM PDT 24
Finished Jun 24 05:21:19 PM PDT 24
Peak memory 206164 kb
Host smart-e327faf7-b3cd-4fbc-bb89-25747c4df5e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11776
31061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1177631061
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.466295064
Short name T2487
Test name
Test status
Simulation time 143315949 ps
CPU time 0.8 seconds
Started Jun 24 05:21:28 PM PDT 24
Finished Jun 24 05:21:30 PM PDT 24
Peak memory 206180 kb
Host smart-dc052b36-3961-48dd-b80d-03ebab6f3386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46629
5064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.466295064
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.1054428565
Short name T1107
Test name
Test status
Simulation time 190623870 ps
CPU time 0.93 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:16 PM PDT 24
Peak memory 206180 kb
Host smart-91aa8b33-d742-44d6-b03c-49795d37657c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1054428565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.1054428565
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2239167001
Short name T550
Test name
Test status
Simulation time 177406541 ps
CPU time 0.77 seconds
Started Jun 24 05:21:18 PM PDT 24
Finished Jun 24 05:21:20 PM PDT 24
Peak memory 206176 kb
Host smart-1bb19ccf-b546-4183-b74a-9a394256cde3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22391
67001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2239167001
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.1731900223
Short name T1111
Test name
Test status
Simulation time 36350243 ps
CPU time 0.66 seconds
Started Jun 24 05:21:22 PM PDT 24
Finished Jun 24 05:21:25 PM PDT 24
Peak memory 206168 kb
Host smart-c2817da0-778d-49df-a110-df644e0e5381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17319
00223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1731900223
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1318857647
Short name T92
Test name
Test status
Simulation time 9126453643 ps
CPU time 20.47 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:35 PM PDT 24
Peak memory 206340 kb
Host smart-68e9f1a8-e27c-439c-b58a-9f16ce5a67f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13188
57647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1318857647
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.884547817
Short name T1525
Test name
Test status
Simulation time 176881917 ps
CPU time 0.8 seconds
Started Jun 24 05:21:15 PM PDT 24
Finished Jun 24 05:21:18 PM PDT 24
Peak memory 206120 kb
Host smart-d41cb634-1d4a-4681-b0f6-4758725abf81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88454
7817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.884547817
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.924944528
Short name T1574
Test name
Test status
Simulation time 230084111 ps
CPU time 0.91 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:15 PM PDT 24
Peak memory 206168 kb
Host smart-d13fa6f3-6f98-4b99-abbc-79ad811c0169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92494
4528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.924944528
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.2533567148
Short name T41
Test name
Test status
Simulation time 23560676212 ps
CPU time 148.45 seconds
Started Jun 24 05:21:15 PM PDT 24
Finished Jun 24 05:23:46 PM PDT 24
Peak memory 206300 kb
Host smart-4c230724-bbb6-4619-b461-769ae1f01e00
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2533567148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.2533567148
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.2528331147
Short name T2318
Test name
Test status
Simulation time 5958632211 ps
CPU time 41.37 seconds
Started Jun 24 05:21:12 PM PDT 24
Finished Jun 24 05:21:54 PM PDT 24
Peak memory 206372 kb
Host smart-912d95df-adfc-40b7-b53a-bd78b8a3be17
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2528331147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2528331147
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.3190596958
Short name T520
Test name
Test status
Simulation time 31031069851 ps
CPU time 747.68 seconds
Started Jun 24 05:21:12 PM PDT 24
Finished Jun 24 05:33:41 PM PDT 24
Peak memory 206436 kb
Host smart-78fe7b8e-ba74-48d7-9d68-de3c0fd3ec06
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3190596958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.3190596958
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.1484111109
Short name T1621
Test name
Test status
Simulation time 211439755 ps
CPU time 0.87 seconds
Started Jun 24 05:21:23 PM PDT 24
Finished Jun 24 05:21:27 PM PDT 24
Peak memory 206200 kb
Host smart-d18455d5-6e45-4b5b-a4d3-ea5f02c5283f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14841
11109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.1484111109
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.1194577089
Short name T2329
Test name
Test status
Simulation time 166629404 ps
CPU time 0.8 seconds
Started Jun 24 05:21:14 PM PDT 24
Finished Jun 24 05:21:18 PM PDT 24
Peak memory 206172 kb
Host smart-23769c71-add2-4daf-8fa9-766ac1453c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11945
77089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.1194577089
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.453911820
Short name T960
Test name
Test status
Simulation time 138576937 ps
CPU time 0.77 seconds
Started Jun 24 05:21:14 PM PDT 24
Finished Jun 24 05:21:17 PM PDT 24
Peak memory 206176 kb
Host smart-2b2c0051-0787-4418-873f-5d362c1abd67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45391
1820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.453911820
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.3175471995
Short name T2129
Test name
Test status
Simulation time 156683385 ps
CPU time 0.81 seconds
Started Jun 24 05:21:28 PM PDT 24
Finished Jun 24 05:21:30 PM PDT 24
Peak memory 206140 kb
Host smart-77c73f22-ffa6-45a0-8ce6-4c2799d8c379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31754
71995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3175471995
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2675895814
Short name T1233
Test name
Test status
Simulation time 151504722 ps
CPU time 0.78 seconds
Started Jun 24 05:21:26 PM PDT 24
Finished Jun 24 05:21:28 PM PDT 24
Peak memory 206172 kb
Host smart-b793ef61-c781-468d-9231-534a7ff533b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26758
95814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2675895814
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2343196376
Short name T1756
Test name
Test status
Simulation time 220344964 ps
CPU time 0.95 seconds
Started Jun 24 05:21:13 PM PDT 24
Finished Jun 24 05:21:16 PM PDT 24
Peak memory 206192 kb
Host smart-1394ee13-37a9-484f-af88-a45aea92afc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23431
96376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2343196376
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.3228637331
Short name T1285
Test name
Test status
Simulation time 6839786001 ps
CPU time 190.14 seconds
Started Jun 24 05:21:15 PM PDT 24
Finished Jun 24 05:24:28 PM PDT 24
Peak memory 206316 kb
Host smart-d7638106-b877-4ff6-9690-deb987a5ea1a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3228637331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.3228637331
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.3915044711
Short name T1088
Test name
Test status
Simulation time 185117764 ps
CPU time 0.79 seconds
Started Jun 24 05:21:20 PM PDT 24
Finished Jun 24 05:21:23 PM PDT 24
Peak memory 206172 kb
Host smart-5a4b55fc-6d68-45f7-9680-c920efa10699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39150
44711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3915044711
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.3683234607
Short name T1536
Test name
Test status
Simulation time 218610757 ps
CPU time 0.83 seconds
Started Jun 24 05:21:28 PM PDT 24
Finished Jun 24 05:21:30 PM PDT 24
Peak memory 206188 kb
Host smart-22eaf523-4efa-41c1-a055-ed7775121e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36832
34607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.3683234607
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3533721085
Short name T2485
Test name
Test status
Simulation time 7036443439 ps
CPU time 199.41 seconds
Started Jun 24 05:21:22 PM PDT 24
Finished Jun 24 05:24:44 PM PDT 24
Peak memory 206388 kb
Host smart-614da845-5974-42b9-9447-3999215fd11e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35337
21085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3533721085
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.2773126611
Short name T1101
Test name
Test status
Simulation time 4020027515 ps
CPU time 4.48 seconds
Started Jun 24 05:21:21 PM PDT 24
Finished Jun 24 05:21:28 PM PDT 24
Peak memory 206260 kb
Host smart-63d33614-36f2-477f-a639-8696cd3e7c92
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2773126611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.2773126611
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.2244258597
Short name T2093
Test name
Test status
Simulation time 13401078639 ps
CPU time 11.81 seconds
Started Jun 24 05:21:38 PM PDT 24
Finished Jun 24 05:21:51 PM PDT 24
Peak memory 206260 kb
Host smart-d9e56fba-c070-46b3-9682-5e0d74b1630d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2244258597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.2244258597
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.1771016797
Short name T1531
Test name
Test status
Simulation time 23401454341 ps
CPU time 20.79 seconds
Started Jun 24 05:21:20 PM PDT 24
Finished Jun 24 05:21:43 PM PDT 24
Peak memory 206396 kb
Host smart-2183d722-891f-48a8-b57c-a5451610fbba
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1771016797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.1771016797
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2801923663
Short name T1070
Test name
Test status
Simulation time 150477315 ps
CPU time 0.79 seconds
Started Jun 24 05:21:22 PM PDT 24
Finished Jun 24 05:21:26 PM PDT 24
Peak memory 206176 kb
Host smart-ecb3ca89-85f6-4226-b4e7-673539a12f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28019
23663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2801923663
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.2595056453
Short name T2345
Test name
Test status
Simulation time 176862434 ps
CPU time 0.79 seconds
Started Jun 24 05:21:22 PM PDT 24
Finished Jun 24 05:21:25 PM PDT 24
Peak memory 206176 kb
Host smart-5789e133-9ffc-499f-9b36-13e00b502e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25950
56453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.2595056453
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.3242025981
Short name T2183
Test name
Test status
Simulation time 290690748 ps
CPU time 1.14 seconds
Started Jun 24 05:21:18 PM PDT 24
Finished Jun 24 05:21:21 PM PDT 24
Peak memory 206408 kb
Host smart-8bf9acd8-a461-4f26-9afd-5d44393990cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32420
25981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.3242025981
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2831299162
Short name T2018
Test name
Test status
Simulation time 935874509 ps
CPU time 2.43 seconds
Started Jun 24 05:21:21 PM PDT 24
Finished Jun 24 05:21:25 PM PDT 24
Peak memory 206232 kb
Host smart-dd9e6ff8-8fe7-446b-bce6-a9e995a95117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28312
99162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2831299162
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.126683793
Short name T1973
Test name
Test status
Simulation time 13945621057 ps
CPU time 29.83 seconds
Started Jun 24 05:21:20 PM PDT 24
Finished Jun 24 05:21:51 PM PDT 24
Peak memory 206372 kb
Host smart-0c8f55f2-ea4a-4bd3-8e59-4c6cc517f2ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12668
3793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.126683793
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.3575337529
Short name T1122
Test name
Test status
Simulation time 430539246 ps
CPU time 1.33 seconds
Started Jun 24 05:21:23 PM PDT 24
Finished Jun 24 05:21:27 PM PDT 24
Peak memory 206104 kb
Host smart-e2f06ae7-2727-418a-a5af-97cd7d66fd71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35753
37529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.3575337529
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.2967657683
Short name T776
Test name
Test status
Simulation time 141829532 ps
CPU time 0.74 seconds
Started Jun 24 05:21:23 PM PDT 24
Finished Jun 24 05:21:26 PM PDT 24
Peak memory 206096 kb
Host smart-e8a0cea6-7bcb-4374-bf00-c9ee05a2c753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29676
57683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.2967657683
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2442446777
Short name T992
Test name
Test status
Simulation time 40266111 ps
CPU time 0.65 seconds
Started Jun 24 05:21:21 PM PDT 24
Finished Jun 24 05:21:24 PM PDT 24
Peak memory 206068 kb
Host smart-b4dbf001-7b30-466d-b4ea-af6ef1b6eb6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24424
46777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2442446777
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1944187872
Short name T531
Test name
Test status
Simulation time 747517204 ps
CPU time 1.84 seconds
Started Jun 24 05:21:20 PM PDT 24
Finished Jun 24 05:21:24 PM PDT 24
Peak memory 206180 kb
Host smart-5f063ea3-aaac-445b-966a-c70d25382d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19441
87872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1944187872
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2303404320
Short name T1629
Test name
Test status
Simulation time 274463674 ps
CPU time 1.67 seconds
Started Jun 24 05:21:22 PM PDT 24
Finished Jun 24 05:21:26 PM PDT 24
Peak memory 206336 kb
Host smart-f21ba6ea-a874-4779-bd1a-d5f4c69cd1bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23034
04320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2303404320
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3951326176
Short name T2399
Test name
Test status
Simulation time 210208523 ps
CPU time 0.82 seconds
Started Jun 24 05:21:28 PM PDT 24
Finished Jun 24 05:21:31 PM PDT 24
Peak memory 206176 kb
Host smart-1821e18f-2e84-4ab4-ab1a-d1df24126c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39513
26176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3951326176
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3588306434
Short name T1797
Test name
Test status
Simulation time 142376480 ps
CPU time 0.74 seconds
Started Jun 24 05:21:28 PM PDT 24
Finished Jun 24 05:21:31 PM PDT 24
Peak memory 206172 kb
Host smart-4cf4bb73-2192-40fd-813a-2091785b881d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35883
06434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3588306434
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.1086549910
Short name T2177
Test name
Test status
Simulation time 245414335 ps
CPU time 0.92 seconds
Started Jun 24 05:21:22 PM PDT 24
Finished Jun 24 05:21:25 PM PDT 24
Peak memory 206192 kb
Host smart-da976888-d733-42f2-9659-0a269237650d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10865
49910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.1086549910
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.2114387070
Short name T400
Test name
Test status
Simulation time 235768966 ps
CPU time 0.87 seconds
Started Jun 24 05:21:22 PM PDT 24
Finished Jun 24 05:21:25 PM PDT 24
Peak memory 206172 kb
Host smart-f5214565-2442-448e-a6d8-49c4b96157da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21143
87070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2114387070
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2938539322
Short name T848
Test name
Test status
Simulation time 23307286886 ps
CPU time 23.67 seconds
Started Jun 24 05:21:28 PM PDT 24
Finished Jun 24 05:21:53 PM PDT 24
Peak memory 206188 kb
Host smart-5635afb1-0098-4e78-affb-7bcd44ce7651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29385
39322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2938539322
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.2196509323
Short name T789
Test name
Test status
Simulation time 3305263981 ps
CPU time 3.99 seconds
Started Jun 24 05:21:23 PM PDT 24
Finished Jun 24 05:21:30 PM PDT 24
Peak memory 206164 kb
Host smart-f4c92e0b-ec32-4e3d-b9f6-5ee70afab5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21965
09323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.2196509323
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.1747944463
Short name T1943
Test name
Test status
Simulation time 14521480482 ps
CPU time 396.24 seconds
Started Jun 24 05:21:24 PM PDT 24
Finished Jun 24 05:28:03 PM PDT 24
Peak memory 206596 kb
Host smart-149dbb53-ab72-4085-bb53-5f5d965cc934
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1747944463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.1747944463
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2334657014
Short name T517
Test name
Test status
Simulation time 239816017 ps
CPU time 0.91 seconds
Started Jun 24 05:21:36 PM PDT 24
Finished Jun 24 05:21:38 PM PDT 24
Peak memory 206184 kb
Host smart-f74f7629-ac70-4a4b-b3c9-a0d4ababafcc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2334657014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2334657014
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1895044800
Short name T2187
Test name
Test status
Simulation time 193587932 ps
CPU time 0.83 seconds
Started Jun 24 05:21:19 PM PDT 24
Finished Jun 24 05:21:22 PM PDT 24
Peak memory 206116 kb
Host smart-c64cc970-e246-4cf1-b798-61d8fce0f426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18950
44800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1895044800
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.3282795521
Short name T1512
Test name
Test status
Simulation time 6149538419 ps
CPU time 59.26 seconds
Started Jun 24 05:21:22 PM PDT 24
Finished Jun 24 05:22:24 PM PDT 24
Peak memory 206340 kb
Host smart-b6b8f12e-668e-498b-a30b-4fbcb204a1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32827
95521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.3282795521
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.980067972
Short name T623
Test name
Test status
Simulation time 6767936919 ps
CPU time 195.86 seconds
Started Jun 24 05:21:21 PM PDT 24
Finished Jun 24 05:24:39 PM PDT 24
Peak memory 206292 kb
Host smart-1ad1b47a-7d60-47e5-ac13-e204d250ab18
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=980067972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.980067972
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.1130613418
Short name T1291
Test name
Test status
Simulation time 157711617 ps
CPU time 0.85 seconds
Started Jun 24 05:21:29 PM PDT 24
Finished Jun 24 05:21:31 PM PDT 24
Peak memory 206120 kb
Host smart-a386c8e1-9dab-48cd-9a89-85e441015853
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1130613418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.1130613418
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.179390444
Short name T806
Test name
Test status
Simulation time 153108148 ps
CPU time 0.81 seconds
Started Jun 24 05:21:22 PM PDT 24
Finished Jun 24 05:21:26 PM PDT 24
Peak memory 206192 kb
Host smart-4e14973c-bfe2-4e26-bd56-13a9639f2f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17939
0444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.179390444
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3756006378
Short name T138
Test name
Test status
Simulation time 288823588 ps
CPU time 0.98 seconds
Started Jun 24 05:21:22 PM PDT 24
Finished Jun 24 05:21:26 PM PDT 24
Peak memory 206196 kb
Host smart-dba01e91-46c1-4168-98df-875a1da2221a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37560
06378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3756006378
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1997240962
Short name T2040
Test name
Test status
Simulation time 190937070 ps
CPU time 0.93 seconds
Started Jun 24 05:21:27 PM PDT 24
Finished Jun 24 05:21:29 PM PDT 24
Peak memory 206072 kb
Host smart-8e828bca-9c46-42d2-b03a-6889fabfcc68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19972
40962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1997240962
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.936588225
Short name T2452
Test name
Test status
Simulation time 170792104 ps
CPU time 0.82 seconds
Started Jun 24 05:21:24 PM PDT 24
Finished Jun 24 05:21:28 PM PDT 24
Peak memory 206344 kb
Host smart-b647639a-726a-418c-aeb4-43ac93976604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93658
8225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.936588225
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1370041429
Short name T726
Test name
Test status
Simulation time 174223677 ps
CPU time 0.8 seconds
Started Jun 24 05:21:21 PM PDT 24
Finished Jun 24 05:21:24 PM PDT 24
Peak memory 206144 kb
Host smart-ece61b25-c5ee-425a-82cc-84ba8c9c5b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13700
41429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1370041429
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2238231444
Short name T181
Test name
Test status
Simulation time 150236969 ps
CPU time 0.77 seconds
Started Jun 24 05:21:34 PM PDT 24
Finished Jun 24 05:21:35 PM PDT 24
Peak memory 206384 kb
Host smart-cd4da2db-e792-46e1-ab5d-8aa6b0b7ab68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22382
31444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2238231444
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.3664258320
Short name T392
Test name
Test status
Simulation time 213116952 ps
CPU time 0.95 seconds
Started Jun 24 05:21:21 PM PDT 24
Finished Jun 24 05:21:24 PM PDT 24
Peak memory 206176 kb
Host smart-0def6ed8-ed54-4060-a0db-6168b04d45a1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3664258320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.3664258320
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2377877527
Short name T489
Test name
Test status
Simulation time 184416842 ps
CPU time 0.8 seconds
Started Jun 24 05:21:22 PM PDT 24
Finished Jun 24 05:21:25 PM PDT 24
Peak memory 206188 kb
Host smart-bb5e53b6-4130-469e-a448-f8cad6c5a8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23778
77527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2377877527
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.161640574
Short name T2362
Test name
Test status
Simulation time 61954324 ps
CPU time 0.75 seconds
Started Jun 24 05:21:28 PM PDT 24
Finished Jun 24 05:21:30 PM PDT 24
Peak memory 206184 kb
Host smart-cf2fcb02-b505-4b2e-a32e-934483f2f1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16164
0574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.161640574
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1993618340
Short name T905
Test name
Test status
Simulation time 9032664284 ps
CPU time 23.81 seconds
Started Jun 24 05:21:36 PM PDT 24
Finished Jun 24 05:22:00 PM PDT 24
Peak memory 206052 kb
Host smart-f8729aca-e2b9-4e49-a844-3569a41fd9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19936
18340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1993618340
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2488338167
Short name T2355
Test name
Test status
Simulation time 164739990 ps
CPU time 0.81 seconds
Started Jun 24 05:21:27 PM PDT 24
Finished Jun 24 05:21:30 PM PDT 24
Peak memory 206124 kb
Host smart-25e230b2-f5d8-4ee4-961f-4edd3b2f799e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24883
38167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2488338167
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2862618313
Short name T2223
Test name
Test status
Simulation time 185325230 ps
CPU time 0.82 seconds
Started Jun 24 05:21:29 PM PDT 24
Finished Jun 24 05:21:31 PM PDT 24
Peak memory 206152 kb
Host smart-16b13a65-d1da-4d94-80da-e92a2fc29e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28626
18313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2862618313
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3099813380
Short name T169
Test name
Test status
Simulation time 20719570507 ps
CPU time 116.82 seconds
Started Jun 24 05:21:36 PM PDT 24
Finished Jun 24 05:23:33 PM PDT 24
Peak memory 206040 kb
Host smart-89153774-854f-431e-af8a-2f920216c592
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3099813380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3099813380
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.3182056637
Short name T164
Test name
Test status
Simulation time 20203249981 ps
CPU time 535.01 seconds
Started Jun 24 05:21:28 PM PDT 24
Finished Jun 24 05:30:25 PM PDT 24
Peak memory 206388 kb
Host smart-ee716a4f-4443-4d48-8fe4-5d70cdb4208e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3182056637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.3182056637
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.260728243
Short name T1806
Test name
Test status
Simulation time 10903005516 ps
CPU time 203.26 seconds
Started Jun 24 05:21:29 PM PDT 24
Finished Jun 24 05:24:54 PM PDT 24
Peak memory 206432 kb
Host smart-f547e0ef-3db0-4ad5-bbfd-5d4b6a037013
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=260728243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.260728243
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.2798923579
Short name T1330
Test name
Test status
Simulation time 240690811 ps
CPU time 0.88 seconds
Started Jun 24 05:21:28 PM PDT 24
Finished Jun 24 05:21:31 PM PDT 24
Peak memory 206092 kb
Host smart-3f1d2e72-7b3c-4949-8449-c9a255ef9593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27989
23579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.2798923579
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.2949194821
Short name T857
Test name
Test status
Simulation time 179382133 ps
CPU time 0.82 seconds
Started Jun 24 05:21:34 PM PDT 24
Finished Jun 24 05:21:35 PM PDT 24
Peak memory 206352 kb
Host smart-425b43b8-f1bb-49ab-9a90-ef2e5ab4a1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29491
94821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.2949194821
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1574875984
Short name T747
Test name
Test status
Simulation time 197175339 ps
CPU time 0.8 seconds
Started Jun 24 05:21:28 PM PDT 24
Finished Jun 24 05:21:31 PM PDT 24
Peak memory 206108 kb
Host smart-d0842eed-6f0c-4cff-9519-bf9c22bab15d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15748
75984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1574875984
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.622873379
Short name T1412
Test name
Test status
Simulation time 177033755 ps
CPU time 0.79 seconds
Started Jun 24 05:21:30 PM PDT 24
Finished Jun 24 05:21:32 PM PDT 24
Peak memory 206144 kb
Host smart-cf2f964d-ce05-49b2-90d1-b1b9a379f251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62287
3379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.622873379
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.1429196690
Short name T1145
Test name
Test status
Simulation time 227186401 ps
CPU time 0.82 seconds
Started Jun 24 05:21:28 PM PDT 24
Finished Jun 24 05:21:31 PM PDT 24
Peak memory 206140 kb
Host smart-f76badb7-4e73-45ca-b62e-32d8eb9959f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14291
96690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.1429196690
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2824623710
Short name T2196
Test name
Test status
Simulation time 272189485 ps
CPU time 1.08 seconds
Started Jun 24 05:21:30 PM PDT 24
Finished Jun 24 05:21:32 PM PDT 24
Peak memory 206192 kb
Host smart-050b46f6-be50-4d84-9a4f-a748f257685f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28246
23710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2824623710
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.1606161694
Short name T2351
Test name
Test status
Simulation time 4036270884 ps
CPU time 26.75 seconds
Started Jun 24 05:21:34 PM PDT 24
Finished Jun 24 05:22:02 PM PDT 24
Peak memory 206576 kb
Host smart-36d92c61-0e50-444a-b27f-97ffa7cc941a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1606161694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.1606161694
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1617645278
Short name T1648
Test name
Test status
Simulation time 140483877 ps
CPU time 0.75 seconds
Started Jun 24 05:21:28 PM PDT 24
Finished Jun 24 05:21:30 PM PDT 24
Peak memory 206152 kb
Host smart-ad6ae2d2-c986-4a64-a8e3-d2c70aa19ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16176
45278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1617645278
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2363633130
Short name T1675
Test name
Test status
Simulation time 171383931 ps
CPU time 0.8 seconds
Started Jun 24 05:21:29 PM PDT 24
Finished Jun 24 05:21:31 PM PDT 24
Peak memory 206428 kb
Host smart-d91afb8f-3290-4c13-8716-560ab64d5e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23636
33130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2363633130
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.2497616804
Short name T1810
Test name
Test status
Simulation time 8926823703 ps
CPU time 84.65 seconds
Started Jun 24 05:21:36 PM PDT 24
Finished Jun 24 05:23:02 PM PDT 24
Peak memory 206324 kb
Host smart-6aaff90c-8c56-46d6-829e-a6289267e5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24976
16804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.2497616804
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.541458404
Short name T1045
Test name
Test status
Simulation time 4283733903 ps
CPU time 5.11 seconds
Started Jun 24 05:21:37 PM PDT 24
Finished Jun 24 05:21:43 PM PDT 24
Peak memory 206424 kb
Host smart-9963ceb9-3a19-4afc-9f3e-17df6bda2663
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=541458404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.541458404
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.1544698243
Short name T45
Test name
Test status
Simulation time 13356586870 ps
CPU time 15.04 seconds
Started Jun 24 05:21:38 PM PDT 24
Finished Jun 24 05:21:55 PM PDT 24
Peak memory 206192 kb
Host smart-e8ac2f89-e10d-4ed3-b429-fb6cad9b2e57
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1544698243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.1544698243
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.1714966067
Short name T700
Test name
Test status
Simulation time 23352520366 ps
CPU time 22.2 seconds
Started Jun 24 05:21:38 PM PDT 24
Finished Jun 24 05:22:02 PM PDT 24
Peak memory 206228 kb
Host smart-a23ca917-cd54-4c6b-85f0-a4762c1c27f4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1714966067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.1714966067
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2353422629
Short name T1183
Test name
Test status
Simulation time 155687198 ps
CPU time 0.85 seconds
Started Jun 24 05:21:35 PM PDT 24
Finished Jun 24 05:21:37 PM PDT 24
Peak memory 206176 kb
Host smart-3ba647b2-ac3c-49e8-bfbc-99a987c11c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23534
22629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2353422629
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.2981148661
Short name T1913
Test name
Test status
Simulation time 147083451 ps
CPU time 0.8 seconds
Started Jun 24 05:21:36 PM PDT 24
Finished Jun 24 05:21:39 PM PDT 24
Peak memory 206176 kb
Host smart-68aca9ff-5850-42d1-8ac3-46afe533fc16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29811
48661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.2981148661
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.3488646968
Short name T1605
Test name
Test status
Simulation time 477855154 ps
CPU time 1.46 seconds
Started Jun 24 05:21:36 PM PDT 24
Finished Jun 24 05:21:38 PM PDT 24
Peak memory 206324 kb
Host smart-959fd04b-489d-48ac-854b-eba4877f1f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34886
46968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.3488646968
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3916034520
Short name T1578
Test name
Test status
Simulation time 1235508916 ps
CPU time 3.08 seconds
Started Jun 24 05:21:36 PM PDT 24
Finished Jun 24 05:21:41 PM PDT 24
Peak memory 206148 kb
Host smart-d652f20c-5f96-4196-943a-19d3bb4e4168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39160
34520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3916034520
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.2705436762
Short name T1203
Test name
Test status
Simulation time 20119629193 ps
CPU time 39.05 seconds
Started Jun 24 05:21:37 PM PDT 24
Finished Jun 24 05:22:18 PM PDT 24
Peak memory 206316 kb
Host smart-61314e90-fe33-4c30-b9fb-a904fc61413a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27054
36762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2705436762
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.1395391296
Short name T1632
Test name
Test status
Simulation time 453697066 ps
CPU time 1.32 seconds
Started Jun 24 05:21:37 PM PDT 24
Finished Jun 24 05:21:40 PM PDT 24
Peak memory 206164 kb
Host smart-864c8594-8aee-446f-9b42-8f9fbddedd68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13953
91296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.1395391296
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.809294932
Short name T1802
Test name
Test status
Simulation time 135989059 ps
CPU time 0.74 seconds
Started Jun 24 05:21:36 PM PDT 24
Finished Jun 24 05:21:37 PM PDT 24
Peak memory 206072 kb
Host smart-79f370e5-cac1-4f24-9936-978c0eb9fab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80929
4932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.809294932
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.770812342
Short name T1381
Test name
Test status
Simulation time 38325958 ps
CPU time 0.68 seconds
Started Jun 24 05:21:37 PM PDT 24
Finished Jun 24 05:21:40 PM PDT 24
Peak memory 206164 kb
Host smart-9742ad8b-5e22-4339-9ef7-9751a72217a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77081
2342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.770812342
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.3415072646
Short name T2358
Test name
Test status
Simulation time 840618500 ps
CPU time 1.94 seconds
Started Jun 24 05:21:40 PM PDT 24
Finished Jun 24 05:21:43 PM PDT 24
Peak memory 206328 kb
Host smart-504263e8-33db-4f6d-96c9-2f377d23bd73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34150
72646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.3415072646
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.3798903983
Short name T2356
Test name
Test status
Simulation time 299013725 ps
CPU time 1.7 seconds
Started Jun 24 05:21:36 PM PDT 24
Finished Jun 24 05:21:40 PM PDT 24
Peak memory 206300 kb
Host smart-872697c0-e6a3-4739-b39d-2a8ebd1dc611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37989
03983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.3798903983
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.1247678140
Short name T2344
Test name
Test status
Simulation time 230106191 ps
CPU time 0.91 seconds
Started Jun 24 05:21:46 PM PDT 24
Finished Jun 24 05:21:49 PM PDT 24
Peak memory 206176 kb
Host smart-401b94cc-374e-45a6-a559-cca550b6bdde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12476
78140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.1247678140
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1494679776
Short name T1252
Test name
Test status
Simulation time 218357247 ps
CPU time 0.83 seconds
Started Jun 24 05:21:45 PM PDT 24
Finished Jun 24 05:21:49 PM PDT 24
Peak memory 206076 kb
Host smart-32a63d45-daa0-431e-a776-5a4ab8de528c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14946
79776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1494679776
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3266257716
Short name T770
Test name
Test status
Simulation time 222878997 ps
CPU time 1.02 seconds
Started Jun 24 05:21:36 PM PDT 24
Finished Jun 24 05:21:38 PM PDT 24
Peak memory 206124 kb
Host smart-0dd0317d-721c-444c-860e-46b3ecb72699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32662
57716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3266257716
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.293152563
Short name T880
Test name
Test status
Simulation time 9294444433 ps
CPU time 70.27 seconds
Started Jun 24 05:21:35 PM PDT 24
Finished Jun 24 05:22:46 PM PDT 24
Peak memory 206612 kb
Host smart-5463319b-7e1f-4a31-b2ef-36695192e94f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=293152563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.293152563
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3925989354
Short name T1965
Test name
Test status
Simulation time 200477869 ps
CPU time 0.87 seconds
Started Jun 24 05:21:37 PM PDT 24
Finished Jun 24 05:21:40 PM PDT 24
Peak memory 206116 kb
Host smart-83456e87-10e2-4662-9464-28d7593450dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39259
89354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3925989354
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.1344944765
Short name T1164
Test name
Test status
Simulation time 23338062989 ps
CPU time 25.69 seconds
Started Jun 24 05:21:37 PM PDT 24
Finished Jun 24 05:22:04 PM PDT 24
Peak memory 206156 kb
Host smart-c062890d-dc85-4299-ad3d-3b9612349247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13449
44765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.1344944765
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.357148410
Short name T372
Test name
Test status
Simulation time 3380519103 ps
CPU time 4.32 seconds
Started Jun 24 05:21:37 PM PDT 24
Finished Jun 24 05:21:43 PM PDT 24
Peak memory 206184 kb
Host smart-70153e8b-5726-4d45-b100-1815cfe8d982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35714
8410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.357148410
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.1331975819
Short name T354
Test name
Test status
Simulation time 14670476460 ps
CPU time 429.89 seconds
Started Jun 24 05:21:36 PM PDT 24
Finished Jun 24 05:28:48 PM PDT 24
Peak memory 206392 kb
Host smart-0ce4cd52-c48c-4625-806d-7438aefb3711
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1331975819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.1331975819
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.3519806244
Short name T505
Test name
Test status
Simulation time 232035272 ps
CPU time 0.91 seconds
Started Jun 24 05:21:45 PM PDT 24
Finished Jun 24 05:21:48 PM PDT 24
Peak memory 206076 kb
Host smart-2c2282ef-0197-4e9c-9506-5e5a4e945757
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3519806244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.3519806244
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.428397477
Short name T1552
Test name
Test status
Simulation time 187907534 ps
CPU time 0.84 seconds
Started Jun 24 05:21:40 PM PDT 24
Finished Jun 24 05:21:42 PM PDT 24
Peak memory 206192 kb
Host smart-d53d3902-a71a-41a4-8b0a-275ac607a332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42839
7477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.428397477
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.1014976996
Short name T2442
Test name
Test status
Simulation time 9230540987 ps
CPU time 254.4 seconds
Started Jun 24 05:21:37 PM PDT 24
Finished Jun 24 05:25:53 PM PDT 24
Peak memory 206300 kb
Host smart-92fb9ff6-3e19-4b79-b78f-60065eefd8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10149
76996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.1014976996
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2534863177
Short name T503
Test name
Test status
Simulation time 7639631500 ps
CPU time 58.74 seconds
Started Jun 24 05:21:35 PM PDT 24
Finished Jun 24 05:22:34 PM PDT 24
Peak memory 206420 kb
Host smart-03b39e68-3127-4acc-a9fc-2a8959545f3c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2534863177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2534863177
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.2588099026
Short name T402
Test name
Test status
Simulation time 227798881 ps
CPU time 0.88 seconds
Started Jun 24 05:21:51 PM PDT 24
Finished Jun 24 05:21:53 PM PDT 24
Peak memory 206180 kb
Host smart-61a6ed0c-731c-4055-a98c-9ecb4f5c4009
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2588099026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.2588099026
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1177388782
Short name T1021
Test name
Test status
Simulation time 173211112 ps
CPU time 0.76 seconds
Started Jun 24 05:21:39 PM PDT 24
Finished Jun 24 05:21:41 PM PDT 24
Peak memory 206356 kb
Host smart-cbef7dbb-a980-4925-b355-142de3954161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11773
88782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1177388782
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2616281252
Short name T2111
Test name
Test status
Simulation time 202889566 ps
CPU time 0.85 seconds
Started Jun 24 05:21:36 PM PDT 24
Finished Jun 24 05:21:38 PM PDT 24
Peak memory 206156 kb
Host smart-f3ebf82c-8701-4b10-b34a-1de28af9a618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26162
81252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2616281252
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.3211572269
Short name T1310
Test name
Test status
Simulation time 174356888 ps
CPU time 0.9 seconds
Started Jun 24 05:21:38 PM PDT 24
Finished Jun 24 05:21:40 PM PDT 24
Peak memory 206068 kb
Host smart-16bb7f41-7c4f-4d88-a9b0-0ae2bc57981e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32115
72269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.3211572269
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3666030627
Short name T1752
Test name
Test status
Simulation time 170240749 ps
CPU time 0.77 seconds
Started Jun 24 05:21:40 PM PDT 24
Finished Jun 24 05:21:42 PM PDT 24
Peak memory 206164 kb
Host smart-55a1c9fb-3476-4231-a4f3-52820219e887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36660
30627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3666030627
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.204506193
Short name T730
Test name
Test status
Simulation time 192398958 ps
CPU time 0.84 seconds
Started Jun 24 05:21:36 PM PDT 24
Finished Jun 24 05:21:39 PM PDT 24
Peak memory 206148 kb
Host smart-d2aea9e6-51e9-4371-aa98-90cea8b7f346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20450
6193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.204506193
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3015538312
Short name T563
Test name
Test status
Simulation time 147001227 ps
CPU time 0.81 seconds
Started Jun 24 05:21:50 PM PDT 24
Finished Jun 24 05:21:52 PM PDT 24
Peak memory 206428 kb
Host smart-735a9c14-4976-4bc1-a9d1-5095633cae4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30155
38312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3015538312
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.2216040646
Short name T2284
Test name
Test status
Simulation time 298958409 ps
CPU time 0.99 seconds
Started Jun 24 05:21:40 PM PDT 24
Finished Jun 24 05:21:42 PM PDT 24
Peak memory 206364 kb
Host smart-e64f4456-6450-4ecc-8256-50d30e068be8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2216040646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.2216040646
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1508812527
Short name T2042
Test name
Test status
Simulation time 148712438 ps
CPU time 0.79 seconds
Started Jun 24 05:21:36 PM PDT 24
Finished Jun 24 05:21:38 PM PDT 24
Peak memory 206116 kb
Host smart-c43c540e-3f5e-4539-9208-b508bf9ed08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15088
12527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1508812527
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2585232302
Short name T34
Test name
Test status
Simulation time 45693977 ps
CPU time 0.69 seconds
Started Jun 24 05:21:48 PM PDT 24
Finished Jun 24 05:21:51 PM PDT 24
Peak memory 206184 kb
Host smart-84e307e8-45d5-4e53-acea-1cd6abfd0760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25852
32302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2585232302
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.1113443215
Short name T1704
Test name
Test status
Simulation time 6438931823 ps
CPU time 14.74 seconds
Started Jun 24 05:21:35 PM PDT 24
Finished Jun 24 05:21:50 PM PDT 24
Peak memory 206348 kb
Host smart-2cae2c2b-008e-4a59-81e8-ebfc5c64fa86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11134
43215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1113443215
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3616493657
Short name T1243
Test name
Test status
Simulation time 173057006 ps
CPU time 0.82 seconds
Started Jun 24 05:21:46 PM PDT 24
Finished Jun 24 05:21:49 PM PDT 24
Peak memory 206176 kb
Host smart-0b570484-0051-49ff-87f3-2270e29d4c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36164
93657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3616493657
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3389554459
Short name T1004
Test name
Test status
Simulation time 192387139 ps
CPU time 0.82 seconds
Started Jun 24 05:21:45 PM PDT 24
Finished Jun 24 05:21:48 PM PDT 24
Peak memory 206164 kb
Host smart-1ad0b295-cfb9-49d4-a22c-12bced09ddc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33895
54459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3389554459
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.3529768492
Short name T1990
Test name
Test status
Simulation time 20994889586 ps
CPU time 561.54 seconds
Started Jun 24 05:21:45 PM PDT 24
Finished Jun 24 05:31:08 PM PDT 24
Peak memory 206356 kb
Host smart-17823a4c-4846-4272-931e-7e17429d1647
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3529768492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.3529768492
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.3339011803
Short name T414
Test name
Test status
Simulation time 15611876158 ps
CPU time 425.03 seconds
Started Jun 24 05:21:46 PM PDT 24
Finished Jun 24 05:28:54 PM PDT 24
Peak memory 206408 kb
Host smart-153ee232-46da-4855-8e00-1d4af02b73e2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3339011803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3339011803
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.3113149483
Short name T411
Test name
Test status
Simulation time 39871889537 ps
CPU time 1030.17 seconds
Started Jun 24 05:21:45 PM PDT 24
Finished Jun 24 05:38:58 PM PDT 24
Peak memory 206336 kb
Host smart-0645c5ea-3964-4291-9458-7328c4c5f6c1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3113149483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.3113149483
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.2136585801
Short name T801
Test name
Test status
Simulation time 216810405 ps
CPU time 0.93 seconds
Started Jun 24 05:21:51 PM PDT 24
Finished Jun 24 05:21:53 PM PDT 24
Peak memory 206200 kb
Host smart-221c0318-ca7c-4a86-815d-420ddeb8c90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21365
85801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.2136585801
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.866969244
Short name T1533
Test name
Test status
Simulation time 200426819 ps
CPU time 0.84 seconds
Started Jun 24 05:21:45 PM PDT 24
Finished Jun 24 05:21:47 PM PDT 24
Peak memory 206160 kb
Host smart-72e9c3d3-692b-45e7-b9c4-dee0b391c945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86696
9244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.866969244
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3903961644
Short name T72
Test name
Test status
Simulation time 169840131 ps
CPU time 0.79 seconds
Started Jun 24 05:21:46 PM PDT 24
Finished Jun 24 05:21:49 PM PDT 24
Peak memory 206132 kb
Host smart-b0302f49-e470-4326-8c68-7d5e4fa564b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39039
61644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3903961644
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.1728132308
Short name T859
Test name
Test status
Simulation time 179592762 ps
CPU time 0.88 seconds
Started Jun 24 05:21:46 PM PDT 24
Finished Jun 24 05:21:49 PM PDT 24
Peak memory 206188 kb
Host smart-514ba3a8-0155-46bf-9cea-328013c4c119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17281
32308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.1728132308
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2818704551
Short name T1404
Test name
Test status
Simulation time 198836498 ps
CPU time 0.79 seconds
Started Jun 24 05:21:46 PM PDT 24
Finished Jun 24 05:21:49 PM PDT 24
Peak memory 206176 kb
Host smart-ae66eb5d-c43a-4a9c-9ef6-a529f303af55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28187
04551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2818704551
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3057260005
Short name T1311
Test name
Test status
Simulation time 262511235 ps
CPU time 0.98 seconds
Started Jun 24 05:21:48 PM PDT 24
Finished Jun 24 05:21:51 PM PDT 24
Peak memory 206192 kb
Host smart-2232f4f1-733e-4896-8d4d-2576d4be8801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30572
60005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3057260005
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.728376874
Short name T1936
Test name
Test status
Simulation time 3247418508 ps
CPU time 83.43 seconds
Started Jun 24 05:21:47 PM PDT 24
Finished Jun 24 05:23:13 PM PDT 24
Peak memory 206392 kb
Host smart-8f9a92a0-c0c5-4653-a9aa-9acf08b94bb8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=728376874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.728376874
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.914968156
Short name T1593
Test name
Test status
Simulation time 176805975 ps
CPU time 0.85 seconds
Started Jun 24 05:21:46 PM PDT 24
Finished Jun 24 05:21:50 PM PDT 24
Peak memory 206188 kb
Host smart-68e012a0-c94e-4f79-a668-99a3235e128e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91496
8156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.914968156
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.4115905596
Short name T1259
Test name
Test status
Simulation time 193255620 ps
CPU time 0.87 seconds
Started Jun 24 05:21:45 PM PDT 24
Finished Jun 24 05:21:48 PM PDT 24
Peak memory 206192 kb
Host smart-53eacdc8-ac6a-419e-a553-ca6048b3a2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41159
05596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.4115905596
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3734335623
Short name T1789
Test name
Test status
Simulation time 10914516873 ps
CPU time 78.83 seconds
Started Jun 24 05:21:44 PM PDT 24
Finished Jun 24 05:23:05 PM PDT 24
Peak memory 206388 kb
Host smart-ac89c76d-4e48-458c-8cf9-61cb16354f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37343
35623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3734335623
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.3711632896
Short name T1709
Test name
Test status
Simulation time 3893331932 ps
CPU time 4.23 seconds
Started Jun 24 05:21:45 PM PDT 24
Finished Jun 24 05:21:52 PM PDT 24
Peak memory 206304 kb
Host smart-f82af7d0-ac7c-405c-87fd-a2550f5c6a87
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3711632896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.3711632896
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3578319339
Short name T1579
Test name
Test status
Simulation time 13373868454 ps
CPU time 15.67 seconds
Started Jun 24 05:21:46 PM PDT 24
Finished Jun 24 05:22:05 PM PDT 24
Peak memory 206316 kb
Host smart-c1445238-fc56-489c-b824-fc2ab021d37d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3578319339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3578319339
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.415219158
Short name T1123
Test name
Test status
Simulation time 23453560875 ps
CPU time 23.19 seconds
Started Jun 24 05:21:46 PM PDT 24
Finished Jun 24 05:22:12 PM PDT 24
Peak memory 206256 kb
Host smart-53cccfc5-f73a-420e-adb1-f2529e9c0ac1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=415219158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.415219158
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.901922623
Short name T2466
Test name
Test status
Simulation time 166178324 ps
CPU time 0.8 seconds
Started Jun 24 05:21:45 PM PDT 24
Finished Jun 24 05:21:48 PM PDT 24
Peak memory 206116 kb
Host smart-1f08eaca-a0ba-4655-881f-454094971986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90192
2623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.901922623
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.3665898328
Short name T59
Test name
Test status
Simulation time 144377060 ps
CPU time 0.77 seconds
Started Jun 24 05:21:44 PM PDT 24
Finished Jun 24 05:21:47 PM PDT 24
Peak memory 206176 kb
Host smart-8d4252e9-71e5-45a8-8a8b-2914e197c792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36658
98328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.3665898328
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.940799003
Short name T2073
Test name
Test status
Simulation time 590987438 ps
CPU time 1.76 seconds
Started Jun 24 05:21:45 PM PDT 24
Finished Jun 24 05:21:50 PM PDT 24
Peak memory 206156 kb
Host smart-09650a7f-75e8-4609-b8b3-823f23837f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94079
9003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.940799003
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3518284742
Short name T818
Test name
Test status
Simulation time 1116195286 ps
CPU time 2.66 seconds
Started Jun 24 05:21:46 PM PDT 24
Finished Jun 24 05:21:51 PM PDT 24
Peak memory 206120 kb
Host smart-ce22faa1-2b11-4d68-a184-b99e1fe05836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35182
84742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3518284742
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.3074005381
Short name T2062
Test name
Test status
Simulation time 21951338615 ps
CPU time 40.51 seconds
Started Jun 24 05:21:51 PM PDT 24
Finished Jun 24 05:22:32 PM PDT 24
Peak memory 206336 kb
Host smart-8d508e55-e1a4-4ba9-82d1-fb0daadda92d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30740
05381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.3074005381
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.1612208124
Short name T1792
Test name
Test status
Simulation time 372990982 ps
CPU time 1.28 seconds
Started Jun 24 05:21:44 PM PDT 24
Finished Jun 24 05:21:47 PM PDT 24
Peak memory 206176 kb
Host smart-d5660294-a0bb-4092-97f1-36a87cbfbcec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16122
08124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1612208124
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1112913003
Short name T1670
Test name
Test status
Simulation time 155014869 ps
CPU time 0.79 seconds
Started Jun 24 05:21:51 PM PDT 24
Finished Jun 24 05:21:53 PM PDT 24
Peak memory 206160 kb
Host smart-719ab3fc-dcc7-410d-9772-26b978136262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11129
13003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1112913003
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.2870566102
Short name T360
Test name
Test status
Simulation time 49772157 ps
CPU time 0.67 seconds
Started Jun 24 05:21:46 PM PDT 24
Finished Jun 24 05:21:50 PM PDT 24
Peak memory 206172 kb
Host smart-50a6efff-be1b-4281-a7ab-7b17d566bb9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28705
66102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2870566102
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3795086842
Short name T591
Test name
Test status
Simulation time 861139159 ps
CPU time 2.02 seconds
Started Jun 24 05:21:45 PM PDT 24
Finished Jun 24 05:21:49 PM PDT 24
Peak memory 206256 kb
Host smart-fd23010d-397a-422e-b8dd-ac7a272adcb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37950
86842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3795086842
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.99874063
Short name T1851
Test name
Test status
Simulation time 168508891 ps
CPU time 1.77 seconds
Started Jun 24 05:21:45 PM PDT 24
Finished Jun 24 05:21:50 PM PDT 24
Peak memory 206252 kb
Host smart-e889c5db-68f3-4d6b-a643-855da16caaa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99874
063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.99874063
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2805709763
Short name T702
Test name
Test status
Simulation time 178349378 ps
CPU time 0.83 seconds
Started Jun 24 05:21:52 PM PDT 24
Finished Jun 24 05:21:54 PM PDT 24
Peak memory 206192 kb
Host smart-4d0651b3-ddce-407a-8fff-1bf810a67bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28057
09763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2805709763
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2167340291
Short name T2278
Test name
Test status
Simulation time 143811636 ps
CPU time 0.79 seconds
Started Jun 24 05:21:55 PM PDT 24
Finished Jun 24 05:21:58 PM PDT 24
Peak memory 206192 kb
Host smart-802ba99f-af39-492f-972b-4e792bbea18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21673
40291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2167340291
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.287702010
Short name T808
Test name
Test status
Simulation time 201473683 ps
CPU time 0.85 seconds
Started Jun 24 05:21:43 PM PDT 24
Finished Jun 24 05:21:45 PM PDT 24
Peak memory 206408 kb
Host smart-add731bb-a9a8-47e4-babb-49e2bcec0692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28770
2010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.287702010
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3642376913
Short name T783
Test name
Test status
Simulation time 201273151 ps
CPU time 0.84 seconds
Started Jun 24 05:21:45 PM PDT 24
Finished Jun 24 05:21:47 PM PDT 24
Peak memory 206196 kb
Host smart-bc4d552b-3571-44cf-8434-23a33507c5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36423
76913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3642376913
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.602353352
Short name T1413
Test name
Test status
Simulation time 23296853870 ps
CPU time 21.07 seconds
Started Jun 24 05:21:51 PM PDT 24
Finished Jun 24 05:22:13 PM PDT 24
Peak memory 206196 kb
Host smart-1147b7df-d06c-4769-982e-5443bd79c3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60235
3352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.602353352
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.1673893176
Short name T1742
Test name
Test status
Simulation time 3315678177 ps
CPU time 3.86 seconds
Started Jun 24 05:21:50 PM PDT 24
Finished Jun 24 05:21:55 PM PDT 24
Peak memory 206232 kb
Host smart-929b4287-956e-4ab9-ad3c-f183a5f3b28b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16738
93176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.1673893176
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.2076901559
Short name T2493
Test name
Test status
Simulation time 10955098256 ps
CPU time 83.47 seconds
Started Jun 24 05:21:52 PM PDT 24
Finished Jun 24 05:23:17 PM PDT 24
Peak memory 206312 kb
Host smart-4ef0ea10-637f-458f-a846-2081ec268f04
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2076901559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.2076901559
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.2573775533
Short name T1633
Test name
Test status
Simulation time 266995068 ps
CPU time 0.94 seconds
Started Jun 24 05:21:55 PM PDT 24
Finished Jun 24 05:21:59 PM PDT 24
Peak memory 206108 kb
Host smart-e3df4062-eadb-4148-8a07-ba61174b9357
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2573775533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.2573775533
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3430885949
Short name T2120
Test name
Test status
Simulation time 192183504 ps
CPU time 0.83 seconds
Started Jun 24 05:21:49 PM PDT 24
Finished Jun 24 05:21:51 PM PDT 24
Peak memory 206196 kb
Host smart-bbf20127-0083-474c-b92c-402eb4266fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34308
85949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3430885949
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.2997151528
Short name T366
Test name
Test status
Simulation time 7023652520 ps
CPU time 190.61 seconds
Started Jun 24 05:21:54 PM PDT 24
Finished Jun 24 05:25:07 PM PDT 24
Peak memory 206328 kb
Host smart-e132c6fd-f253-4980-a789-bfb88e9fe1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29971
51528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.2997151528
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.755690294
Short name T549
Test name
Test status
Simulation time 5109782320 ps
CPU time 37.58 seconds
Started Jun 24 05:21:55 PM PDT 24
Finished Jun 24 05:22:35 PM PDT 24
Peak memory 206264 kb
Host smart-e26d48c8-ff80-4b82-a8f8-a47fc7dd7f13
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=755690294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.755690294
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.2468815221
Short name T1697
Test name
Test status
Simulation time 172226510 ps
CPU time 0.78 seconds
Started Jun 24 05:21:54 PM PDT 24
Finished Jun 24 05:21:57 PM PDT 24
Peak memory 206120 kb
Host smart-fbd08f43-1796-4f8f-860d-1519d22066fb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2468815221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.2468815221
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1123077739
Short name T1587
Test name
Test status
Simulation time 142985018 ps
CPU time 0.81 seconds
Started Jun 24 05:21:45 PM PDT 24
Finished Jun 24 05:21:49 PM PDT 24
Peak memory 206192 kb
Host smart-16ed6051-8652-422f-a0a6-b3d724a0ff09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11230
77739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1123077739
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.217300009
Short name T1903
Test name
Test status
Simulation time 172675075 ps
CPU time 0.88 seconds
Started Jun 24 05:21:58 PM PDT 24
Finished Jun 24 05:22:00 PM PDT 24
Peak memory 206188 kb
Host smart-af0a1a9b-d480-41f3-993c-4d78037b5b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21730
0009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.217300009
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2281154743
Short name T1097
Test name
Test status
Simulation time 188229549 ps
CPU time 0.81 seconds
Started Jun 24 05:21:55 PM PDT 24
Finished Jun 24 05:21:58 PM PDT 24
Peak memory 206176 kb
Host smart-fe089af3-d4f3-4235-b50c-23dc023cc934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22811
54743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2281154743
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.4239526073
Short name T2472
Test name
Test status
Simulation time 171477361 ps
CPU time 0.82 seconds
Started Jun 24 05:21:54 PM PDT 24
Finished Jun 24 05:21:57 PM PDT 24
Peak memory 206168 kb
Host smart-c726b318-1aa1-4ec0-bc74-83bb5b30daf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42395
26073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.4239526073
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2231128611
Short name T2051
Test name
Test status
Simulation time 237983855 ps
CPU time 0.87 seconds
Started Jun 24 05:21:54 PM PDT 24
Finished Jun 24 05:21:58 PM PDT 24
Peak memory 206172 kb
Host smart-3c38673b-f4fc-455a-939d-dc24ca505819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22311
28611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2231128611
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1282452806
Short name T1757
Test name
Test status
Simulation time 157836940 ps
CPU time 0.8 seconds
Started Jun 24 05:21:58 PM PDT 24
Finished Jun 24 05:22:00 PM PDT 24
Peak memory 206176 kb
Host smart-40ae1aec-0f15-4ea4-abcb-1366d157f06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12824
52806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1282452806
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.1671341477
Short name T1847
Test name
Test status
Simulation time 249649476 ps
CPU time 0.95 seconds
Started Jun 24 05:21:53 PM PDT 24
Finished Jun 24 05:21:55 PM PDT 24
Peak memory 206180 kb
Host smart-d0a321c4-41f9-46a4-87fe-829730dc0a94
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1671341477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.1671341477
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.1321642604
Short name T2024
Test name
Test status
Simulation time 158950866 ps
CPU time 0.78 seconds
Started Jun 24 05:21:53 PM PDT 24
Finished Jun 24 05:21:56 PM PDT 24
Peak memory 206188 kb
Host smart-99dd3059-f8c3-4835-bea1-1fad6eaa43aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13216
42604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.1321642604
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.826904192
Short name T688
Test name
Test status
Simulation time 36176590 ps
CPU time 0.71 seconds
Started Jun 24 05:21:58 PM PDT 24
Finished Jun 24 05:22:00 PM PDT 24
Peak memory 206184 kb
Host smart-ebc940a5-111b-42b9-8084-edf1df08cc4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82690
4192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.826904192
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2406332932
Short name T2246
Test name
Test status
Simulation time 21162766725 ps
CPU time 47.97 seconds
Started Jun 24 05:21:52 PM PDT 24
Finished Jun 24 05:22:42 PM PDT 24
Peak memory 206280 kb
Host smart-a97d83f1-646a-4f1c-8f15-7c97da41c269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24063
32932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2406332932
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.2270333034
Short name T405
Test name
Test status
Simulation time 210745350 ps
CPU time 0.86 seconds
Started Jun 24 05:21:58 PM PDT 24
Finished Jun 24 05:22:00 PM PDT 24
Peak memory 206176 kb
Host smart-8ea3ebf2-de0b-4c99-ac25-ea118aab15f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22703
33034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.2270333034
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1100656949
Short name T1516
Test name
Test status
Simulation time 188076078 ps
CPU time 0.88 seconds
Started Jun 24 05:21:53 PM PDT 24
Finished Jun 24 05:21:55 PM PDT 24
Peak memory 206192 kb
Host smart-82973aee-aabc-4576-b903-462311ef4388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11006
56949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1100656949
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3046701950
Short name T773
Test name
Test status
Simulation time 3734039284 ps
CPU time 31.28 seconds
Started Jun 24 05:21:54 PM PDT 24
Finished Jun 24 05:22:27 PM PDT 24
Peak memory 206376 kb
Host smart-3a9eb434-a8e2-4fe6-ae88-af175dea6c53
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3046701950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3046701950
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.3309599465
Short name T199
Test name
Test status
Simulation time 32070578941 ps
CPU time 226.33 seconds
Started Jun 24 05:21:53 PM PDT 24
Finished Jun 24 05:25:41 PM PDT 24
Peak memory 206340 kb
Host smart-6d097d18-fe41-4f7f-8bfc-92b54b344178
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3309599465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.3309599465
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.1610452520
Short name T894
Test name
Test status
Simulation time 222303120 ps
CPU time 0.86 seconds
Started Jun 24 05:21:55 PM PDT 24
Finished Jun 24 05:21:58 PM PDT 24
Peak memory 206200 kb
Host smart-06434f9e-5df3-4b6f-9ac7-9b90af3f82d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16104
52520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.1610452520
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.4199103263
Short name T977
Test name
Test status
Simulation time 172180089 ps
CPU time 0.83 seconds
Started Jun 24 05:21:58 PM PDT 24
Finished Jun 24 05:22:00 PM PDT 24
Peak memory 206176 kb
Host smart-81b58155-2179-41ad-afe2-771f0f0378b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41991
03263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.4199103263
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1693186442
Short name T71
Test name
Test status
Simulation time 152607465 ps
CPU time 0.77 seconds
Started Jun 24 05:21:55 PM PDT 24
Finished Jun 24 05:21:58 PM PDT 24
Peak memory 206100 kb
Host smart-ed019f06-db4f-49c0-a250-48f1e2a98ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16931
86442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1693186442
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.3538621897
Short name T1258
Test name
Test status
Simulation time 180473552 ps
CPU time 0.81 seconds
Started Jun 24 05:21:55 PM PDT 24
Finished Jun 24 05:21:58 PM PDT 24
Peak memory 206192 kb
Host smart-8c1a54ee-2789-457b-9536-d79a0bfb5c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35386
21897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.3538621897
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2873255038
Short name T1239
Test name
Test status
Simulation time 214367909 ps
CPU time 0.89 seconds
Started Jun 24 05:21:53 PM PDT 24
Finished Jun 24 05:21:56 PM PDT 24
Peak memory 206180 kb
Host smart-89138675-2f98-45bf-a076-c3bb146ad9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28732
55038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2873255038
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3420405541
Short name T596
Test name
Test status
Simulation time 250434160 ps
CPU time 0.94 seconds
Started Jun 24 05:21:54 PM PDT 24
Finished Jun 24 05:21:58 PM PDT 24
Peak memory 206088 kb
Host smart-436772b8-065c-4050-a0d1-835f9e732f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34204
05541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3420405541
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.1454523781
Short name T1397
Test name
Test status
Simulation time 6156418316 ps
CPU time 173.86 seconds
Started Jun 24 05:21:54 PM PDT 24
Finished Jun 24 05:24:50 PM PDT 24
Peak memory 206392 kb
Host smart-e6a8b4a6-d200-4a01-b939-06a223a4ed8a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1454523781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.1454523781
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3812359271
Short name T1010
Test name
Test status
Simulation time 259363793 ps
CPU time 0.86 seconds
Started Jun 24 05:21:53 PM PDT 24
Finished Jun 24 05:21:55 PM PDT 24
Peak memory 206072 kb
Host smart-0331772d-2bb3-44dc-ac65-e5335b39a4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38123
59271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3812359271
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1662993887
Short name T785
Test name
Test status
Simulation time 155802796 ps
CPU time 0.77 seconds
Started Jun 24 05:21:55 PM PDT 24
Finished Jun 24 05:21:58 PM PDT 24
Peak memory 206064 kb
Host smart-bf2fe60d-eb68-4606-9609-32f2baa496fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16629
93887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1662993887
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.610288218
Short name T840
Test name
Test status
Simulation time 14635234989 ps
CPU time 99.38 seconds
Started Jun 24 05:21:53 PM PDT 24
Finished Jun 24 05:23:34 PM PDT 24
Peak memory 206364 kb
Host smart-21f2a0f6-8a2a-4d28-a2e7-5a3ed724f884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61028
8218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.610288218
Directory /workspace/9.usbdev_streaming_out/latest
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