Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	41894	1		T1	5		T2	4		T3	2
all_values[1]	41894	1		T1	5		T2	4		T3	2
all_values[2]	41894	1		T1	5		T2	4		T3	2
all_values[3]	41894	1		T1	5		T2	4		T3	2
all_values[4]	41894	1		T1	5		T2	4		T3	2
all_values[5]	41894	1		T1	5		T2	4		T3	2
all_values[6]	41894	1		T1	5		T2	4		T3	2
all_values[7]	41894	1		T1	5		T2	4		T3	2
all_values[8]	41894	1		T1	5		T2	4		T3	2
all_values[9]	41894	1		T1	5		T2	4		T3	2
all_values[10]	41894	1		T1	5		T2	4		T3	2
all_values[11]	41894	1		T1	5		T2	4		T3	2
all_values[12]	41894	1		T1	5		T2	4		T3	2
all_values[13]	41894	1		T1	5		T2	4		T3	2
all_values[14]	41894	1		T1	5		T2	4		T3	2
all_values[15]	41894	1		T1	5		T2	4		T3	2
all_values[16]	41894	1		T1	5		T2	4		T3	2
all_values[17]	41894	1		T1	5		T2	4		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	746464	1		T1	88		T2	72		T3	36
auto[1]	7628	1		T1	2		T29	3		T30	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	749009	1		T1	90		T2	72		T3	36
auto[1]	5083	1		T202	130		T203	66		T204	124

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	40916	1		T1	5		T2	4		T3	2
all_values[0]	auto[0]	auto[1]	143	1		T202	2		T203	3		T204	1
all_values[0]	auto[1]	auto[0]	691	1		T29	3		T49	3		T20	3
all_values[0]	auto[1]	auto[1]	144	1		T202	5		T203	2		T204	5
all_values[1]	auto[0]	auto[0]	39396	1		T1	3		T2	4		T3	2
all_values[1]	auto[0]	auto[1]	153	1		T202	2		T204	6		T205	5
all_values[1]	auto[1]	auto[0]	2213	1		T1	2		T30	2		T51	3
all_values[1]	auto[1]	auto[1]	132	1		T202	5		T203	3		T204	2
all_values[2]	auto[0]	auto[0]	41475	1		T1	5		T2	4		T3	2
all_values[2]	auto[0]	auto[1]	142	1		T202	4		T203	4		T204	4
all_values[2]	auto[1]	auto[0]	115	1		T43	2		T44	2		T45	2
all_values[2]	auto[1]	auto[1]	162	1		T202	2		T203	1		T204	4
all_values[3]	auto[0]	auto[0]	40092	1		T1	5		T2	4		T3	2
all_values[3]	auto[0]	auto[1]	169	1		T202	5		T203	4		T204	6
all_values[3]	auto[1]	auto[0]	1501	1		T68	1485		T202	1		T268	2
all_values[3]	auto[1]	auto[1]	132	1		T202	2		T203	1		T204	2
all_values[4]	auto[0]	auto[0]	41593	1		T1	5		T2	4		T3	2
all_values[4]	auto[0]	auto[1]	128	1		T202	1		T203	3		T204	3
all_values[4]	auto[1]	auto[0]	30	1		T69	2		T202	1		T203	1
all_values[4]	auto[1]	auto[1]	143	1		T202	6		T204	5		T205	5
all_values[5]	auto[0]	auto[0]	41600	1		T1	5		T2	4		T3	2
all_values[5]	auto[0]	auto[1]	127	1		T202	2		T205	2		T269	3
all_values[5]	auto[1]	auto[0]	33	1		T204	3		T269	1		T266	1
all_values[5]	auto[1]	auto[1]	134	1		T202	5		T204	3		T205	6
all_values[6]	auto[0]	auto[0]	41586	1		T1	5		T2	4		T3	2
all_values[6]	auto[0]	auto[1]	142	1		T202	3		T203	3		T204	2
all_values[6]	auto[1]	auto[0]	26	1		T202	1		T270	1		T271	2
all_values[6]	auto[1]	auto[1]	140	1		T202	4		T203	2		T204	4
all_values[7]	auto[0]	auto[0]	41577	1		T1	5		T2	4		T3	2
all_values[7]	auto[0]	auto[1]	143	1		T202	3		T203	3		T204	6
all_values[7]	auto[1]	auto[0]	23	1		T52	2		T53	2		T203	1
all_values[7]	auto[1]	auto[1]	151	1		T202	5		T269	4		T266	5
all_values[8]	auto[0]	auto[0]	41576	1		T1	5		T2	4		T3	2
all_values[8]	auto[0]	auto[1]	146	1		T202	5		T204	6		T205	3
all_values[8]	auto[1]	auto[0]	35	1		T56	11		T266	3		T268	1
all_values[8]	auto[1]	auto[1]	137	1		T202	3		T203	4		T204	2
all_values[9]	auto[0]	auto[0]	41570	1		T1	5		T2	4		T3	2
all_values[9]	auto[0]	auto[1]	120	1		T202	3		T204	1		T205	5
all_values[9]	auto[1]	auto[0]	52	1		T65	5		T66	5		T67	5
all_values[9]	auto[1]	auto[1]	152	1		T202	3		T204	6		T205	3
all_values[10]	auto[0]	auto[0]	41596	1		T1	5		T2	4		T3	2
all_values[10]	auto[0]	auto[1]	120	1		T202	3		T204	3		T205	3
all_values[10]	auto[1]	auto[0]	29	1		T202	2		T204	2		T267	4
all_values[10]	auto[1]	auto[1]	149	1		T202	3		T203	3		T204	1
all_values[11]	auto[0]	auto[0]	41486	1		T1	5		T2	4		T3	2
all_values[11]	auto[0]	auto[1]	147	1		T202	6		T203	3		T204	3
all_values[11]	auto[1]	auto[0]	133	1		T75	2		T77	2		T78	2
all_values[11]	auto[1]	auto[1]	128	1		T202	2		T203	2		T204	4
all_values[12]	auto[0]	auto[0]	41571	1		T1	5		T2	4		T3	2
all_values[12]	auto[0]	auto[1]	153	1		T202	6		T203	4		T204	2
all_values[12]	auto[1]	auto[0]	36	1		T79	3		T80	3		T81	3
all_values[12]	auto[1]	auto[1]	134	1		T202	1		T203	1		T204	6
all_values[13]	auto[0]	auto[0]	41582	1		T1	5		T2	4		T3	2
all_values[13]	auto[0]	auto[1]	145	1		T202	2		T203	3		T204	5
all_values[13]	auto[1]	auto[0]	23	1		T203	1		T205	1		T266	1
all_values[13]	auto[1]	auto[1]	144	1		T202	6		T204	3		T205	4
all_values[14]	auto[0]	auto[0]	41578	1		T1	5		T2	4		T3	2
all_values[14]	auto[0]	auto[1]	129	1		T202	5		T204	4		T205	5
all_values[14]	auto[1]	auto[0]	20	1		T272	1		T268	1		T273	2
all_values[14]	auto[1]	auto[1]	167	1		T202	3		T203	4		T204	4
all_values[15]	auto[0]	auto[0]	41582	1		T1	5		T2	4		T3	2
all_values[15]	auto[0]	auto[1]	150	1		T202	3		T203	1		T204	1
all_values[15]	auto[1]	auto[0]	28	1		T203	1		T266	2		T268	2
all_values[15]	auto[1]	auto[1]	134	1		T202	5		T203	3		T204	5
all_values[16]	auto[0]	auto[0]	41561	1		T1	5		T2	4		T3	2
all_values[16]	auto[0]	auto[1]	153	1		T202	3		T204	4		T205	4
all_values[16]	auto[1]	auto[0]	58	1		T72	8		T73	8		T74	8
all_values[16]	auto[1]	auto[1]	122	1		T202	4		T203	4		T204	4
all_values[17]	auto[0]	auto[0]	41588	1		T1	5		T2	4		T3	2
all_values[17]	auto[0]	auto[1]	129	1		T202	4		T203	4		T204	2
all_values[17]	auto[1]	auto[0]	38	1		T58	2		T59	2		T60	2
all_values[17]	auto[1]	auto[1]	139	1		T202	4		T203	1		T204	5