Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	41894	1		T1	5		T2	4		T3	2
all_pins[1]	41894	1		T1	5		T2	4		T3	2
all_pins[2]	41894	1		T1	5		T2	4		T3	2
all_pins[3]	41894	1		T1	5		T2	4		T3	2
all_pins[4]	41894	1		T1	5		T2	4		T3	2
all_pins[5]	41894	1		T1	5		T2	4		T3	2
all_pins[6]	41894	1		T1	5		T2	4		T3	2
all_pins[7]	41894	1		T1	5		T2	4		T3	2
all_pins[8]	41894	1		T1	5		T2	4		T3	2
all_pins[9]	41894	1		T1	5		T2	4		T3	2
all_pins[10]	41894	1		T1	5		T2	4		T3	2
all_pins[11]	41894	1		T1	5		T2	4		T3	2
all_pins[12]	41894	1		T1	5		T2	4		T3	2
all_pins[13]	41894	1		T1	5		T2	4		T3	2
all_pins[14]	41894	1		T1	5		T2	4		T3	2
all_pins[15]	41894	1		T1	5		T2	4		T3	2
all_pins[16]	41894	1		T1	5		T2	4		T3	2
all_pins[17]	41894	1		T1	5		T2	4		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	751370	1		T1	89		T2	72		T3	36
values[0x1]	2722	1		T1	1		T30	1		T51	1
transitions[0x0=>0x1]	2401	1		T1	1		T30	1		T51	1
transitions[0x1=>0x0]	2408	1		T1	1		T30	1		T51	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	41771	1		T1	5		T2	4		T3	2
all_pins[0]	values[0x1]	123	1		T83	1		T274	1		T275	1
all_pins[0]	transitions[0x0=>0x1]	108	1		T83	1		T274	1		T275	1
all_pins[0]	transitions[0x1=>0x0]	1351	1		T1	1		T30	1		T51	1
all_pins[1]	values[0x0]	40528	1		T1	4		T2	4		T3	2
all_pins[1]	values[0x1]	1366	1		T1	1		T30	1		T51	1
all_pins[1]	transitions[0x0=>0x1]	1353	1		T1	1		T30	1		T51	1
all_pins[1]	transitions[0x1=>0x0]	116	1		T43	1		T44	1		T45	1
all_pins[2]	values[0x0]	41765	1		T1	5		T2	4		T3	2
all_pins[2]	values[0x1]	129	1		T43	1		T44	1		T45	1
all_pins[2]	transitions[0x0=>0x1]	106	1		T43	1		T44	1		T45	1
all_pins[2]	transitions[0x1=>0x0]	44	1		T68	1		T202	1		T205	2
all_pins[3]	values[0x0]	41827	1		T1	5		T2	4		T3	2
all_pins[3]	values[0x1]	67	1		T68	1		T202	1		T204	1
all_pins[3]	transitions[0x0=>0x1]	50	1		T68	1		T202	1		T204	1
all_pins[3]	transitions[0x1=>0x0]	59	1		T69	1		T202	3		T204	2
all_pins[4]	values[0x0]	41818	1		T1	5		T2	4		T3	2
all_pins[4]	values[0x1]	76	1		T69	1		T202	3		T204	2
all_pins[4]	transitions[0x0=>0x1]	51	1		T69	1		T202	2		T205	1
all_pins[4]	transitions[0x1=>0x0]	43	1		T205	1		T269	2		T272	2
all_pins[5]	values[0x0]	41826	1		T1	5		T2	4		T3	2
all_pins[5]	values[0x1]	68	1		T202	1		T204	2		T205	4
all_pins[5]	transitions[0x0=>0x1]	44	1		T202	1		T205	1		T269	2
all_pins[5]	transitions[0x1=>0x0]	50	1		T203	1		T204	1		T276	2
all_pins[6]	values[0x0]	41820	1		T1	5		T2	4		T3	2
all_pins[6]	values[0x1]	74	1		T203	1		T204	3		T205	3
all_pins[6]	transitions[0x0=>0x1]	56	1		T203	1		T204	3		T205	3
all_pins[6]	transitions[0x1=>0x0]	52	1		T52	1		T53	1		T202	2
all_pins[7]	values[0x0]	41824	1		T1	5		T2	4		T3	2
all_pins[7]	values[0x1]	70	1		T52	1		T53	1		T202	2
all_pins[7]	transitions[0x0=>0x1]	57	1		T52	1		T53	1		T202	1
all_pins[7]	transitions[0x1=>0x0]	50	1		T56	1		T203	1		T204	1
all_pins[8]	values[0x0]	41831	1		T1	5		T2	4		T3	2
all_pins[8]	values[0x1]	63	1		T56	1		T202	1		T203	1
all_pins[8]	transitions[0x0=>0x1]	42	1		T56	1		T202	1		T203	1
all_pins[8]	transitions[0x1=>0x0]	72	1		T65	2		T66	2		T67	2
all_pins[9]	values[0x0]	41801	1		T1	5		T2	4		T3	2
all_pins[9]	values[0x1]	93	1		T65	2		T66	2		T67	2
all_pins[9]	transitions[0x0=>0x1]	63	1		T65	2		T66	2		T67	2
all_pins[9]	transitions[0x1=>0x0]	53	1		T203	2		T204	1		T205	1
all_pins[10]	values[0x0]	41811	1		T1	5		T2	4		T3	2
all_pins[10]	values[0x1]	83	1		T202	2		T203	2		T204	1
all_pins[10]	transitions[0x0=>0x1]	66	1		T202	1		T203	2		T204	1
all_pins[10]	transitions[0x1=>0x0]	92	1		T75	1		T77	1		T78	1
all_pins[11]	values[0x0]	41785	1		T1	5		T2	4		T3	2
all_pins[11]	values[0x1]	109	1		T75	1		T77	1		T78	1
all_pins[11]	transitions[0x0=>0x1]	102	1		T75	1		T77	1		T78	1
all_pins[11]	transitions[0x1=>0x0]	44	1		T79	1		T80	1		T81	1
all_pins[12]	values[0x0]	41843	1		T1	5		T2	4		T3	2
all_pins[12]	values[0x1]	51	1		T79	1		T80	1		T81	1
all_pins[12]	transitions[0x0=>0x1]	45	1		T79	1		T80	1		T81	1
all_pins[12]	transitions[0x1=>0x0]	65	1		T202	1		T204	2		T205	3
all_pins[13]	values[0x0]	41823	1		T1	5		T2	4		T3	2
all_pins[13]	values[0x1]	71	1		T202	1		T204	2		T205	4
all_pins[13]	transitions[0x0=>0x1]	46	1		T202	1		T204	1		T205	3
all_pins[13]	transitions[0x1=>0x0]	51	1		T202	3		T203	2		T204	2
all_pins[14]	values[0x0]	41818	1		T1	5		T2	4		T3	2
all_pins[14]	values[0x1]	76	1		T202	3		T203	2		T204	3
all_pins[14]	transitions[0x0=>0x1]	58	1		T202	2		T204	2		T205	1
all_pins[14]	transitions[0x1=>0x0]	58	1		T202	1		T204	3		T269	2
all_pins[15]	values[0x0]	41818	1		T1	5		T2	4		T3	2
all_pins[15]	values[0x1]	76	1		T202	2		T203	2		T204	4
all_pins[15]	transitions[0x0=>0x1]	59	1		T202	2		T203	2		T204	2
all_pins[15]	transitions[0x1=>0x0]	49	1		T72	4		T73	4		T74	4
all_pins[16]	values[0x0]	41828	1		T1	5		T2	4		T3	2
all_pins[16]	values[0x1]	66	1		T72	4		T73	4		T74	4
all_pins[16]	transitions[0x0=>0x1]	57	1		T72	4		T73	4		T74	4
all_pins[16]	transitions[0x1=>0x0]	52	1		T58	1		T59	1		T60	1
all_pins[17]	values[0x0]	41833	1		T1	5		T2	4		T3	2
all_pins[17]	values[0x1]	61	1		T58	1		T59	1		T60	1
all_pins[17]	transitions[0x0=>0x1]	38	1		T58	1		T59	1		T60	1
all_pins[17]	transitions[0x1=>0x0]	107	1		T83	1		T274	1		T275	1