Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T202	7		T203	4		T204	7
all_values[1]	284	1		T202	7		T203	4		T204	7
all_values[2]	284	1		T202	7		T203	4		T204	7
all_values[3]	284	1		T202	7		T203	4		T204	7
all_values[4]	284	1		T202	7		T203	4		T204	7
all_values[5]	284	1		T202	7		T203	4		T204	7
all_values[6]	284	1		T202	7		T203	4		T204	7
all_values[7]	284	1		T202	7		T203	4		T204	7
all_values[8]	284	1		T202	7		T203	4		T204	7
all_values[9]	284	1		T202	7		T203	4		T204	7
all_values[10]	284	1		T202	7		T203	4		T204	7
all_values[11]	284	1		T202	7		T203	4		T204	7
all_values[12]	284	1		T202	7		T203	4		T204	7
all_values[13]	284	1		T202	7		T203	4		T204	7
all_values[14]	284	1		T202	7		T203	4		T204	7
all_values[15]	284	1		T202	7		T203	4		T204	7
all_values[16]	284	1		T202	7		T203	4		T204	7
all_values[17]	284	1		T202	7		T203	4		T204	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2842	1		T202	68		T203	50		T204	73
auto[1]	2270	1		T202	58		T203	22		T204	53

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	872	1		T202	14		T203	22		T204	20
auto[1]	4240	1		T202	112		T203	50		T204	106

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2965	1		T202	68		T203	51		T204	77
auto[1]	2147	1		T202	58		T203	21		T204	49

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	28	1		T202	1		T204	2		T269	1
all_values[0]	auto[0]	auto[0]	auto[1]	62	1		T202	1		T203	2		T204	1
all_values[0]	auto[0]	auto[1]	auto[0]	15	1		T277	1		T278	1		T279	1
all_values[0]	auto[0]	auto[1]	auto[1]	52	1		T202	1		T204	1		T205	2
all_values[0]	auto[1]	auto[0]	auto[1]	63	1		T202	1		T203	1		T205	2
all_values[0]	auto[1]	auto[1]	auto[1]	64	1		T202	3		T203	1		T204	3
all_values[1]	auto[0]	auto[0]	auto[0]	26	1		T202	1		T203	1		T266	1
all_values[1]	auto[0]	auto[0]	auto[1]	66	1		T204	4		T205	3		T276	1
all_values[1]	auto[0]	auto[1]	auto[0]	19	1		T203	1		T270	1		T280	2
all_values[1]	auto[0]	auto[1]	auto[1]	56	1		T202	2		T203	1		T205	1
all_values[1]	auto[1]	auto[0]	auto[1]	65	1		T202	2		T204	2		T205	2
all_values[1]	auto[1]	auto[1]	auto[1]	52	1		T202	2		T203	1		T204	1
all_values[2]	auto[0]	auto[0]	auto[0]	20	1		T202	2		T205	2		T276	1
all_values[2]	auto[0]	auto[0]	auto[1]	62	1		T202	2		T203	2		T204	2
all_values[2]	auto[0]	auto[1]	auto[0]	9	1		T281	3		T282	1		T283	2
all_values[2]	auto[0]	auto[1]	auto[1]	67	1		T203	1		T204	2		T205	2
all_values[2]	auto[1]	auto[0]	auto[1]	63	1		T203	1		T204	1		T205	1
all_values[2]	auto[1]	auto[1]	auto[1]	63	1		T202	3		T204	2		T205	2
all_values[3]	auto[0]	auto[0]	auto[0]	22	1		T202	1		T269	3		T268	3
all_values[3]	auto[0]	auto[0]	auto[1]	65	1		T202	1		T203	2		T204	3
all_values[3]	auto[0]	auto[1]	auto[0]	10	1		T268	1		T277	1		T281	1
all_values[3]	auto[0]	auto[1]	auto[1]	52	1		T202	2		T204	2		T205	1
all_values[3]	auto[1]	auto[0]	auto[1]	77	1		T202	1		T203	2		T204	2
all_values[3]	auto[1]	auto[1]	auto[1]	58	1		T202	2		T205	2		T266	1
all_values[4]	auto[0]	auto[0]	auto[0]	40	1		T202	1		T203	1		T272	1
all_values[4]	auto[0]	auto[0]	auto[1]	51	1		T203	1		T204	1		T269	3
all_values[4]	auto[0]	auto[1]	auto[0]	18	1		T203	1		T205	1		T270	1
all_values[4]	auto[0]	auto[1]	auto[1]	68	1		T202	1		T204	4		T205	4
all_values[4]	auto[1]	auto[0]	auto[1]	59	1		T202	1		T203	1		T204	2
all_values[4]	auto[1]	auto[1]	auto[1]	48	1		T202	4		T205	1		T276	2
all_values[5]	auto[0]	auto[0]	auto[0]	46	1		T202	1		T203	4		T204	3
all_values[5]	auto[0]	auto[0]	auto[1]	54	1		T202	2		T269	1		T271	1
all_values[5]	auto[0]	auto[1]	auto[0]	20	1		T204	2		T270	3		T268	1
all_values[5]	auto[0]	auto[1]	auto[1]	56	1		T202	1		T204	1		T205	2
all_values[5]	auto[1]	auto[0]	auto[1]	60	1		T202	2		T205	1		T269	1
all_values[5]	auto[1]	auto[1]	auto[1]	48	1		T202	1		T204	1		T205	4
all_values[6]	auto[0]	auto[0]	auto[0]	32	1		T202	1		T204	2		T269	1
all_values[6]	auto[0]	auto[0]	auto[1]	54	1		T203	2		T205	1		T269	2
all_values[6]	auto[0]	auto[1]	auto[0]	19	1		T270	1		T271	3		T277	2
all_values[6]	auto[0]	auto[1]	auto[1]	60	1		T202	1		T203	1		T204	1
all_values[6]	auto[1]	auto[0]	auto[1]	78	1		T202	3		T203	1		T204	2
all_values[6]	auto[1]	auto[1]	auto[1]	41	1		T202	2		T204	2		T205	2
all_values[7]	auto[0]	auto[0]	auto[0]	28	1		T203	2		T204	2		T205	3
all_values[7]	auto[0]	auto[0]	auto[1]	53	1		T202	3		T203	1		T204	3
all_values[7]	auto[0]	auto[1]	auto[0]	10	1		T205	2		T267	1		T279	1
all_values[7]	auto[0]	auto[1]	auto[1]	59	1		T202	2		T269	1		T266	2
all_values[7]	auto[1]	auto[0]	auto[1]	79	1		T202	2		T203	1		T204	2
all_values[7]	auto[1]	auto[1]	auto[1]	55	1		T269	2		T266	2		T272	2
all_values[8]	auto[0]	auto[0]	auto[0]	32	1		T203	1		T205	1		T269	1
all_values[8]	auto[0]	auto[0]	auto[1]	60	1		T202	1		T204	3		T205	1
all_values[8]	auto[0]	auto[1]	auto[0]	16	1		T266	2		T284	3		T285	1
all_values[8]	auto[0]	auto[1]	auto[1]	50	1		T202	2		T203	2		T204	1
all_values[8]	auto[1]	auto[0]	auto[1]	74	1		T202	2		T203	1		T204	2
all_values[8]	auto[1]	auto[1]	auto[1]	52	1		T202	2		T204	1		T205	3
all_values[9]	auto[0]	auto[0]	auto[0]	39	1		T202	1		T203	2		T204	1
all_values[9]	auto[0]	auto[0]	auto[1]	49	1		T202	1		T204	1		T205	2
all_values[9]	auto[0]	auto[1]	auto[0]	17	1		T202	1		T203	2		T268	1
all_values[9]	auto[0]	auto[1]	auto[1]	67	1		T202	2		T204	3		T205	1
all_values[9]	auto[1]	auto[0]	auto[1]	56	1		T202	1		T205	2		T269	1
all_values[9]	auto[1]	auto[1]	auto[1]	56	1		T202	1		T204	2		T205	2
all_values[10]	auto[0]	auto[0]	auto[0]	43	1		T202	1		T203	2		T204	3
all_values[10]	auto[0]	auto[0]	auto[1]	54	1		T202	1		T204	2		T205	1
all_values[10]	auto[0]	auto[1]	auto[0]	20	1		T202	1		T204	1		T267	2
all_values[10]	auto[0]	auto[1]	auto[1]	52	1		T202	1		T203	1		T269	1
all_values[10]	auto[1]	auto[0]	auto[1]	60	1		T205	1		T269	4		T276	1
all_values[10]	auto[1]	auto[1]	auto[1]	55	1		T202	3		T203	1		T204	1
all_values[11]	auto[0]	auto[0]	auto[0]	31	1		T204	1		T271	1		T268	2
all_values[11]	auto[0]	auto[0]	auto[1]	62	1		T202	2		T203	2		T204	1
all_values[11]	auto[0]	auto[1]	auto[0]	24	1		T205	1		T268	2		T278	1
all_values[11]	auto[0]	auto[1]	auto[1]	60	1		T202	1		T203	1		T204	2
all_values[11]	auto[1]	auto[0]	auto[1]	65	1		T202	4		T203	1		T204	2
all_values[11]	auto[1]	auto[1]	auto[1]	42	1		T204	1		T205	1		T269	1
all_values[12]	auto[0]	auto[0]	auto[0]	30	1		T202	1		T205	2		T276	1
all_values[12]	auto[0]	auto[0]	auto[1]	56	1		T202	3		T203	2		T204	1
all_values[12]	auto[0]	auto[1]	auto[0]	16	1		T205	1		T276	1		T266	1
all_values[12]	auto[0]	auto[1]	auto[1]	59	1		T202	2		T204	2		T205	3
all_values[12]	auto[1]	auto[0]	auto[1]	80	1		T202	1		T203	2		T204	2
all_values[12]	auto[1]	auto[1]	auto[1]	43	1		T204	2		T205	1		T269	2
all_values[13]	auto[0]	auto[0]	auto[0]	31	1		T203	2		T266	1		T270	1
all_values[13]	auto[0]	auto[0]	auto[1]	63	1		T202	1		T203	1		T204	3
all_values[13]	auto[0]	auto[1]	auto[0]	13	1		T205	1		T272	1		T267	1
all_values[13]	auto[0]	auto[1]	auto[1]	51	1		T202	3		T276	1		T266	2
all_values[13]	auto[1]	auto[0]	auto[1]	70	1		T202	1		T203	1		T204	2
all_values[13]	auto[1]	auto[1]	auto[1]	56	1		T202	2		T204	2		T205	4
all_values[14]	auto[0]	auto[0]	auto[0]	25	1		T203	1		T276	1		T270	2
all_values[14]	auto[0]	auto[0]	auto[1]	60	1		T202	2		T204	2		T205	3
all_values[14]	auto[0]	auto[1]	auto[0]	11	1		T272	1		T273	1		T285	1
all_values[14]	auto[0]	auto[1]	auto[1]	74	1		T202	1		T203	1		T204	1
all_values[14]	auto[1]	auto[0]	auto[1]	69	1		T202	3		T203	1		T204	2
all_values[14]	auto[1]	auto[1]	auto[1]	45	1		T202	1		T203	1		T204	2
all_values[15]	auto[0]	auto[0]	auto[0]	30	1		T203	1		T204	2		T266	1
all_values[15]	auto[0]	auto[0]	auto[1]	61	1		T202	2		T204	1		T205	1
all_values[15]	auto[0]	auto[1]	auto[0]	17	1		T266	1		T268	1		T267	1
all_values[15]	auto[0]	auto[1]	auto[1]	49	1		T202	1		T203	1		T204	1
all_values[15]	auto[1]	auto[0]	auto[1]	60	1		T202	2		T205	5		T269	2
all_values[15]	auto[1]	auto[1]	auto[1]	67	1		T202	2		T203	2		T204	3
all_values[16]	auto[0]	auto[0]	auto[0]	32	1		T202	1		T203	1		T276	3
all_values[16]	auto[0]	auto[0]	auto[1]	67	1		T202	3		T204	4		T205	1
all_values[16]	auto[0]	auto[1]	auto[0]	23	1		T205	1		T276	1		T270	1
all_values[16]	auto[0]	auto[1]	auto[1]	56	1		T202	2		T203	2		T204	2
all_values[16]	auto[1]	auto[0]	auto[1]	69	1		T203	1		T204	1		T205	1
all_values[16]	auto[1]	auto[1]	auto[1]	37	1		T202	1		T205	2		T269	2
all_values[17]	auto[0]	auto[0]	auto[0]	39	1		T204	1		T205	1		T269	5
all_values[17]	auto[0]	auto[0]	auto[1]	52	1		T202	3		T203	2		T205	1
all_values[17]	auto[0]	auto[1]	auto[0]	21	1		T269	2		T270	1		T280	4
all_values[17]	auto[0]	auto[1]	auto[1]	54	1		T202	1		T203	1		T204	2
all_values[17]	auto[1]	auto[0]	auto[1]	70	1		T202	2		T203	1		T204	2
all_values[17]	auto[1]	auto[1]	auto[1]	48	1		T202	1		T204	2		T205	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal